diff --git a/quad/Packages/.repos.xml b/quad/Packages/.repos.xml
new file mode 100644
index 0000000000000000000000000000000000000000..55f8c8ce5f744ba380f52387e4f8a11eb793104a
--- /dev/null
+++ b/quad/Packages/.repos.xml
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<repositories>
+  <repository>
+    <type>CMSIS Pack</type>
+    <name>Keil</name>
+    <url>http://www.keil.com/pack/index.idx</url>
+  </repository>
+  <repository>
+    <type>XCDL/CMSIS Pack</type>
+    <name>GNU ARM Eclipse</name>
+    <url>http://gnuarmeclipse.sourceforge.net/packages/content.xml</url>
+  </repository>
+</repositories>
diff --git a/quad/vivado_workspace/vivado_workspace.cache/wt/gui_resources.wdf b/quad/vivado_workspace/vivado_workspace.cache/wt/gui_resources.wdf
index 4893d45f56efff5aeb0376f03eb83b9a93cb8afc..350802b86f2c8a4bb519560360ae61d98bf40180 100644
--- a/quad/vivado_workspace/vivado_workspace.cache/wt/gui_resources.wdf
+++ b/quad/vivado_workspace/vivado_workspace.cache/wt/gui_resources.wdf
@@ -3,7 +3,7 @@ version:1
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6170706c797273626d756c74696175746f6d6174696f6e6469616c6f675f636865636b626f785f74726565:3138:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:626173656469616c6f675f63616e63656c:3232:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:626173656469616c6f675f6e6f:31:00:00
-70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:626173656469616c6f675f6f6b:3838:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:626173656469616c6f675f6f6b:3931:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:626173656469616c6f675f796573:3132:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:626173657265706f72747461625f726572756e:32:00:00
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@@ -20,7 +20,7 @@ version:1
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:637265617465727362706f72746469616c6f675f74797065:33:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:637573746f6d697a65636f72656469616c6f675f646f63756d656e746174696f6e:35:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:637573746f6d697a65636f72656469616c6f675f69705f6c6f636174696f6e:33:00:00
-70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3635:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3636:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:3232:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:67657474696e6773746172746564766965775f6f70656e5f70726f6a656374:32:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6861636763697073796d626f6c5f73686f775f64697361626c65645f706f727473:34:00:00
@@ -29,9 +29,9 @@ version:1
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:697073746174757373656374696f6e70616e656c5f757067726164655f73656c6563746564:31:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6c61756e636872756e6d73676469616c6f675f63616e63656c5f72756e:31:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6d696f636f6e666967747265657461626c6570616e656c5f6d696f5f636f6e6669675f747265655f7461626c65:37:00:00
-70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6d61696e6d656e756d67725f6578706f7274:3336:00:00
-70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6d61696e6d656e756d67725f66696c65:3632:00:00
-70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6d61696e6d656e756d67725f6f70656e5f726563656e745f66696c65:3333:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6d61696e6d656e756d67725f6578706f7274:3339:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6d61696e6d656e756d67725f66696c65:3638:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6d61696e6d656e756d67725f6f70656e5f726563656e745f66696c65:3336:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6d61696e6d656e756d67725f7265706f7274:35:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6d61696e6d656e756d67725f746f6f6c73:36:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6d61696e6d656e756d67725f77696e646f77:34:00:00
@@ -47,8 +47,8 @@ version:1
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6e65776578706f727468617264776172656469616c6f675f6578706f72745f746f:34:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6e65776578706f727468617264776172656469616c6f675f696e636c7564655f62697473747265616d:33:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6e6577697077697a6172645f6372656174655f6e65775f617869345f69705f6372656174655f61786934:31:00:00
-70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6e65776c61756e636868617264776172656469616c6f675f6c6f636174696f6e5f6f665f68617264776172655f6465736372697074696f6e5f66696c65:33:00:00
-70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6e65776c61756e636868617264776172656469616c6f675f776f726b7370616365:34:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6e65776c61756e636868617264776172656469616c6f675f6c6f636174696f6e5f6f665f68617264776172655f6465736372697074696f6e5f66696c65:34:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:6e65776c61756e636868617264776172656469616c6f675f776f726b7370616365:35:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:7061636f6d6d616e646e616d65735f6164645f736f7572636573:31:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:7061636f6d6d616e646e616d65735f6175746f5f7570646174655f68696572:33:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:7061636f6d6d616e646e616d65735f636f72655f67656e:31:00:00
@@ -57,7 +57,7 @@ version:1
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:7061636f6d6d616e646e616d65735f6578706f72745f62697473747265616d5f66696c6573:31:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:7061636f6d6d616e646e616d65735f6578706f72745f6861726477617265:3133:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:7061636f6d6d616e646e616d65735f69705f7061636b616765725f77697a617264:31:00:00
-70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:7061636f6d6d616e646e616d65735f6c61756e63685f6861726477617265:3131:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:7061636f6d6d616e646e616d65735f6c61756e63685f6861726477617265:3134:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:7061636f6d6d616e646e616d65735f726567656e65726174655f6c61796f7574:39:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:7061636f6d6d616e646e616d65735f73686f775f70726f647563745f6775696465:32:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:706176696577735f636f6465:36:00:00
@@ -79,7 +79,7 @@ version:1
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:7374616c6572756e6469616c6f675f796573:31:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:73746174656d6f6e69746f725f72657365745f72756e:31:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:73746174656d6f6e69746f725f72657365745f73746570:31:00:00
-70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f70726f6a65637473:32:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f70726f6a65637473:33:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:73796e7468657469636173746174656d6f6e69746f725f63616e63656c:32:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:73797374656d6275696c6465726d656e755f6164645f6970:32:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:73797374656d6275696c6465726d656e755f6372656174655f706f7274:36:00:00
@@ -91,4 +91,4 @@ version:1
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:746f756368706f696e747375727665796469616c6f675f6e6f:32:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:7870675f697073796d626f6c5f73686f775f64697361626c65645f706f727473:39:00:00
 70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:7870675f74616262656470616e655f7461626265645f70616e65:31:00:00
-eof:3770768208
+eof:4172758103
diff --git a/quad/vivado_workspace/vivado_workspace.cache/wt/java_command_handlers.wdf b/quad/vivado_workspace/vivado_workspace.cache/wt/java_command_handlers.wdf
index 8f9e95bfa2f0f235327cbd66d9f8c922121ffb10..b72bd0df4b6fe8124231cf49b2f2d4a93b49526e 100644
--- a/quad/vivado_workspace/vivado_workspace.cache/wt/java_command_handlers.wdf
+++ b/quad/vivado_workspace/vivado_workspace.cache/wt/java_command_handlers.wdf
@@ -12,7 +12,7 @@ version:1
 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:69707061636b6167657268616e646c6572:31:00:00
 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:69707061636b6167657277697a61726468616e646c6572:31:00:00
 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e65776578706f72746861726477617265:3133:00:00
-70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e65776c61756e63686861726477617265:3131:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e65776c61756e63686861726477617265:3134:00:00
 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e626c6f636b64657369676e:31:00:00
 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:32:00:00
 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:726567656e65726174657273626c61796f7574:39:00:00
@@ -23,4 +23,4 @@ version:1
 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:3131:00:00
 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:757067726164656970:31:00:00
 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b696d706c656d656e746174696f6e:32:00:00
-eof:1326644939
+eof:3312993437
diff --git a/quad/vivado_workspace/vivado_workspace.cache/wt/project.wpc b/quad/vivado_workspace/vivado_workspace.cache/wt/project.wpc
index 1f7e326bd3bc110d0053fb5ee32d8940e447ccf5..99b22c6d9defa235de8bd5ad1b8fcae0ef0ff5c5 100644
--- a/quad/vivado_workspace/vivado_workspace.cache/wt/project.wpc
+++ b/quad/vivado_workspace/vivado_workspace.cache/wt/project.wpc
@@ -1,4 +1,4 @@
 version:1
 57656254616c6b5472616e736d697373696f6e417474656d70746564:7
-6d6f64655f636f756e7465727c4755494d6f6465:20
+6d6f64655f636f756e7465727c4755494d6f6465:22
 eof:
diff --git a/quad/vivado_workspace/vivado_workspace.cache/wt/webtalk_pa.xml b/quad/vivado_workspace/vivado_workspace.cache/wt/webtalk_pa.xml
index 9d6dde3eb7a55286ea913276c7c8ed652ad83617..d8adfda8ab2914349fe7d981f1d3036fe12544d2 100644
--- a/quad/vivado_workspace/vivado_workspace.cache/wt/webtalk_pa.xml
+++ b/quad/vivado_workspace/vivado_workspace.cache/wt/webtalk_pa.xml
@@ -3,7 +3,7 @@
 <!--The data in this file is primarily intended for consumption by Xilinx tools.
 The structure and the elements are likely to change over the next few releases.
 This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="pa" timeStamp="Sat Dec  9 17:57:10 2017">
+<application name="pa" timeStamp="Sun Dec 10 19:19:13 2017">
 <section name="Project Information" visible="false">
 <property name="ProjectID" value="43fbab7971b9497fbc997c9c95d80965" type="ProjectID"/>
 <property name="ProjectIteration" value="13" type="ProjectIteration"/>
@@ -30,7 +30,7 @@ This means code written to parse this file will need to be revisited each subseq
 <property name="IPPackagerHandler" value="1" type="JavaHandler"/>
 <property name="IPPackagerWizardHandler" value="1" type="JavaHandler"/>
 <property name="NewExportHardware" value="13" type="JavaHandler"/>
-<property name="NewLaunchHardware" value="11" type="JavaHandler"/>
+<property name="NewLaunchHardware" value="14" type="JavaHandler"/>
 <property name="OpenBlockDesign" value="1" type="JavaHandler"/>
 <property name="OpenProject" value="2" type="JavaHandler"/>
 <property name="RegenerateRSBLayout" value="9" type="JavaHandler"/>
@@ -47,7 +47,7 @@ This means code written to parse this file will need to be revisited each subseq
 <property name="ApplyRSBMultiAutomationDialog_CHECKBOX_TREE" value="18" type="GuiResourceData"/>
 <property name="BaseDialog_CANCEL" value="22" type="GuiResourceData"/>
 <property name="BaseDialog_NO" value="1" type="GuiResourceData"/>
-<property name="BaseDialog_OK" value="88" type="GuiResourceData"/>
+<property name="BaseDialog_OK" value="91" type="GuiResourceData"/>
 <property name="BaseDialog_YES" value="12" type="GuiResourceData"/>
 <property name="BaseReportTab_RERUN" value="2" type="GuiResourceData"/>
 <property name="ClkConfigTreeTablePanel_CLK_CONFIG_TREE_TABLE" value="4" type="GuiResourceData"/>
@@ -64,7 +64,7 @@ This means code written to parse this file will need to be revisited each subseq
 <property name="CreateRSBPortDialog_TYPE" value="3" type="GuiResourceData"/>
 <property name="CustomizeCoreDialog_DOCUMENTATION" value="5" type="GuiResourceData"/>
 <property name="CustomizeCoreDialog_IP_LOCATION" value="3" type="GuiResourceData"/>
-<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="65" type="GuiResourceData"/>
+<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="66" type="GuiResourceData"/>
 <property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="22" type="GuiResourceData"/>
 <property name="GettingStartedView_OPEN_PROJECT" value="2" type="GuiResourceData"/>
 <property name="HACGCIPSymbol_SHOW_DISABLED_PORTS" value="4" type="GuiResourceData"/>
@@ -73,9 +73,9 @@ This means code written to parse this file will need to be revisited each subseq
 <property name="IPStatusSectionPanel_UPGRADE_SELECTED" value="1" type="GuiResourceData"/>
 <property name="LaunchRunMsgDialog_CANCEL_RUN" value="1" type="GuiResourceData"/>
 <property name="MIOConfigTreeTablePanel_MIO_CONFIG_TREE_TABLE" value="7" type="GuiResourceData"/>
-<property name="MainMenuMgr_EXPORT" value="36" type="GuiResourceData"/>
-<property name="MainMenuMgr_FILE" value="62" type="GuiResourceData"/>
-<property name="MainMenuMgr_OPEN_RECENT_FILE" value="33" type="GuiResourceData"/>
+<property name="MainMenuMgr_EXPORT" value="39" type="GuiResourceData"/>
+<property name="MainMenuMgr_FILE" value="68" type="GuiResourceData"/>
+<property name="MainMenuMgr_OPEN_RECENT_FILE" value="36" type="GuiResourceData"/>
 <property name="MainMenuMgr_REPORT" value="5" type="GuiResourceData"/>
 <property name="MainMenuMgr_TOOLS" value="6" type="GuiResourceData"/>
 <property name="MainMenuMgr_WINDOW" value="4" type="GuiResourceData"/>
@@ -91,8 +91,8 @@ This means code written to parse this file will need to be revisited each subseq
 <property name="NewExportHardwareDialog_EXPORT_TO" value="4" type="GuiResourceData"/>
 <property name="NewExportHardwareDialog_INCLUDE_BITSTREAM" value="3" type="GuiResourceData"/>
 <property name="NewIpWizard_CREATE_NEW_AXI4_IP_CREATE_AXI4" value="1" type="GuiResourceData"/>
-<property name="NewLaunchHardwareDialog_LOCATION_OF_HARDWARE_DESCRIPTION_FILE" value="3" type="GuiResourceData"/>
-<property name="NewLaunchHardwareDialog_WORKSPACE" value="4" type="GuiResourceData"/>
+<property name="NewLaunchHardwareDialog_LOCATION_OF_HARDWARE_DESCRIPTION_FILE" value="4" type="GuiResourceData"/>
+<property name="NewLaunchHardwareDialog_WORKSPACE" value="5" type="GuiResourceData"/>
 <property name="PACommandNames_ADD_SOURCES" value="1" type="GuiResourceData"/>
 <property name="PACommandNames_AUTO_UPDATE_HIER" value="3" type="GuiResourceData"/>
 <property name="PACommandNames_CORE_GEN" value="1" type="GuiResourceData"/>
@@ -101,7 +101,7 @@ This means code written to parse this file will need to be revisited each subseq
 <property name="PACommandNames_EXPORT_BITSTREAM_FILES" value="1" type="GuiResourceData"/>
 <property name="PACommandNames_EXPORT_HARDWARE" value="13" type="GuiResourceData"/>
 <property name="PACommandNames_IP_PACKAGER_WIZARD" value="1" type="GuiResourceData"/>
-<property name="PACommandNames_LAUNCH_HARDWARE" value="11" type="GuiResourceData"/>
+<property name="PACommandNames_LAUNCH_HARDWARE" value="14" type="GuiResourceData"/>
 <property name="PACommandNames_REGENERATE_LAYOUT" value="9" type="GuiResourceData"/>
 <property name="PACommandNames_SHOW_PRODUCT_GUIDE" value="2" type="GuiResourceData"/>
 <property name="PAViews_CODE" value="6" type="GuiResourceData"/>
@@ -123,7 +123,7 @@ This means code written to parse this file will need to be revisited each subseq
 <property name="StaleRunDialog_YES" value="1" type="GuiResourceData"/>
 <property name="StateMonitor_RESET_RUN" value="1" type="GuiResourceData"/>
 <property name="StateMonitor_RESET_STEP" value="1" type="GuiResourceData"/>
-<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="2" type="GuiResourceData"/>
+<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="3" type="GuiResourceData"/>
 <property name="SyntheticaStateMonitor_CANCEL" value="2" type="GuiResourceData"/>
 <property name="SystemBuilderMenu_ADD_IP" value="2" type="GuiResourceData"/>
 <property name="SystemBuilderMenu_CREATE_PORT" value="6" type="GuiResourceData"/>
@@ -136,6 +136,11 @@ This means code written to parse this file will need to be revisited each subseq
 <property name="XPG_IPSymbol_SHOW_DISABLED_PORTS" value="9" type="GuiResourceData"/>
 <property name="XPG_TabbedPane_TABBED_PANE" value="1" type="GuiResourceData"/>
 </item>
+<item name="Other">
+<property name="GuiMode" value="13" type="GuiMode"/>
+<property name="BatchMode" value="0" type="BatchMode"/>
+<property name="TclMode" value="8" type="TclMode"/>
+</item>
 </section>
 </application>
 </document>
diff --git a/quad/vivado_workspace/vivado_workspace.hw/vivado_workspace.lpr b/quad/vivado_workspace/vivado_workspace.hw/vivado_workspace.lpr
index 114157aecdcba7f07cd879182151b56d3bc27c91..b498eff922ab6a7d521d4326f17d2b469fd8d10f 100644
--- a/quad/vivado_workspace/vivado_workspace.hw/vivado_workspace.lpr
+++ b/quad/vivado_workspace/vivado_workspace.hw/vivado_workspace.lpr
@@ -3,4 +3,6 @@
 <!--                                                              -->
 <!-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.        -->
 
-<labtools version="1" minor="0"/>
+<labtools version="1" minor="0">
+  <HWSession Dir="hw_1" File="hw.xml"/>
+</labtools>
diff --git a/quad/vivado_workspace/vivado_workspace.runs/impl_1/gen_run.xml b/quad/vivado_workspace/vivado_workspace.runs/impl_1/gen_run.xml
index 505a6428fc2acc20d7a7ec2f243ebb30026c9cd6..7b740bd75adb4ae473ee3f9a5ffb7fef01136ba2 100644
--- a/quad/vivado_workspace/vivado_workspace.runs/impl_1/gen_run.xml
+++ b/quad/vivado_workspace/vivado_workspace.runs/impl_1/gen_run.xml
@@ -1,65 +1,65 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="impl_1" LaunchPart="xc7z010clg400-1" LaunchTime="1512863830">
-  <File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
-  <File Type="BG-DRC" Name="quad_wrapper.drc"/>
-  <File Type="BG-BGN" Name="quad_wrapper.bgn"/>
-  <File Type="BITSTR-SYSDEF" Name="quad_wrapper.sysdef"/>
-  <File Type="BITSTR-MMI" Name="quad_wrapper.mmi"/>
-  <File Type="BITSTR-BMM" Name="quad_wrapper_bd.bmm"/>
-  <File Type="BITSTR-NKY" Name="quad_wrapper.nky"/>
-  <File Type="BITSTR-RBT" Name="quad_wrapper.rbt"/>
-  <File Type="BITSTR-MSK" Name="quad_wrapper.msk"/>
-  <File Type="BG-BIN" Name="quad_wrapper.bin"/>
+  <File Type="ROUTE-PWR-RPX" Name="quad_wrapper_power_routed.rpx"/>
+  <File Type="ROUTE-PWR-SUM" Name="quad_wrapper_power_summary_routed.pb"/>
+  <File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="quad_wrapper_methodology_drc_routed.rpx"/>
+  <File Type="ROUTE-PWR" Name="quad_wrapper_power_routed.rpt"/>
+  <File Type="ROUTE-DRC-RPX" Name="quad_wrapper_drc_routed.rpx"/>
+  <File Type="ROUTE-METHODOLOGY-DRC-PB" Name="quad_wrapper_methodology_drc_routed.pb"/>
+  <File Type="ROUTE-DRC-PB" Name="quad_wrapper_drc_routed.pb"/>
+  <File Type="ROUTE-METHODOLOGY-DRC" Name="quad_wrapper_methodology_drc_routed.rpt"/>
+  <File Type="ROUTE-DRC" Name="quad_wrapper_drc_routed.rpt"/>
+  <File Type="ROUTE-BLACKBOX-DCP" Name="quad_wrapper_routed_bb.dcp"/>
+  <File Type="ROUTE-DCP" Name="quad_wrapper_routed.dcp"/>
+  <File Type="ROUTE-ERROR-DCP" Name="quad_wrapper_routed_error.dcp"/>
+  <File Type="PHYSOPT-DRC" Name="quad_wrapper_drc_physopted.rpt"/>
+  <File Type="PHYSOPT-DCP" Name="quad_wrapper_physopt.dcp"/>
+  <File Type="POSTPLACE-PWROPT-DCP" Name="quad_wrapper_postplace_pwropt.dcp"/>
+  <File Type="PA-TCL" Name="quad_wrapper.tcl"/>
+  <File Type="PLACE-SIMILARITY" Name="quad_wrapper_incremental_reuse_placed.rpt"/>
+  <File Type="PLACE-PRE-SIMILARITY" Name="quad_wrapper_incremental_reuse_pre_placed.rpt"/>
+  <File Type="OPT-METHODOLOGY-DRC" Name="quad_wrapper_methodology_drc_opted.rpt"/>
+  <File Type="OPT-DCP" Name="quad_wrapper_opt.dcp"/>
+  <File Type="OPT-DRC" Name="quad_wrapper_drc_opted.rpt"/>
+  <File Type="INIT-TIMING" Name="quad_wrapper_timing_summary_init.rpt"/>
+  <File Type="PLACE-TIMING" Name="quad_wrapper_timing_summary_placed.rpt"/>
+  <File Type="RDI-RDI" Name="quad_wrapper.vdi"/>
+  <File Type="POSTROUTE-PHYSOPT-DCP" Name="quad_wrapper_postroute_physopt.dcp"/>
   <File Type="BG-BIT" Name="quad_wrapper.bit"/>
-  <File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="quad_wrapper_timing_summary_postroute_physopted.rpx"/>
   <File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="quad_wrapper_timing_summary_postroute_physopted.pb"/>
-  <File Type="POSTROUTE-PHYSOPT-TIMING" Name="quad_wrapper_timing_summary_postroute_physopted.rpt"/>
-  <File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="quad_wrapper_postroute_physopt_bb.dcp"/>
-  <File Type="POSTROUTE-PHYSOPT-DCP" Name="quad_wrapper_postroute_physopt.dcp"/>
-  <File Type="ROUTE-CLK" Name="quad_wrapper_clock_utilization_routed.rpt"/>
-  <File Type="ROUTE-SIMILARITY" Name="quad_wrapper_incremental_reuse_routed.rpt"/>
-  <File Type="ROUTE-TIMING-RPX" Name="quad_wrapper_timing_summary_routed.rpx"/>
+  <File Type="BG-BIN" Name="quad_wrapper.bin"/>
   <File Type="ROUTE-TIMING-PB" Name="quad_wrapper_timing_summary_routed.pb"/>
+  <File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="quad_wrapper_timing_summary_postroute_physopted.rpx"/>
+  <File Type="BITSTR-MSK" Name="quad_wrapper.msk"/>
+  <File Type="ROUTE-TIMING-RPX" Name="quad_wrapper_timing_summary_routed.rpx"/>
+  <File Type="BITSTR-RBT" Name="quad_wrapper.rbt"/>
+  <File Type="ROUTE-SIMILARITY" Name="quad_wrapper_incremental_reuse_routed.rpt"/>
+  <File Type="BITSTR-NKY" Name="quad_wrapper.nky"/>
+  <File Type="ROUTE-CLK" Name="quad_wrapper_clock_utilization_routed.rpt"/>
+  <File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="quad_wrapper_postroute_physopt_bb.dcp"/>
+  <File Type="BG-DRC" Name="quad_wrapper.drc"/>
+  <File Type="BITSTR-MMI" Name="quad_wrapper.mmi"/>
+  <File Type="PLACE-DCP" Name="quad_wrapper_placed.dcp"/>
+  <File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
+  <File Type="POSTROUTE-PHYSOPT-TIMING" Name="quad_wrapper_timing_summary_postroute_physopted.rpt"/>
+  <File Type="BG-BGN" Name="quad_wrapper.bgn"/>
   <File Type="ROUTE-TIMINGSUMMARY" Name="quad_wrapper_timing_summary_routed.rpt"/>
+  <File Type="BITSTR-SYSDEF" Name="quad_wrapper.sysdef"/>
+  <File Type="PWROPT-DCP" Name="quad_wrapper_pwropt.dcp"/>
+  <File Type="BITSTR-BMM" Name="quad_wrapper_bd.bmm"/>
   <File Type="ROUTE-STATUS-PB" Name="quad_wrapper_route_status.pb"/>
   <File Type="ROUTE-STATUS" Name="quad_wrapper_route_status.rpt"/>
   <File Type="PLACE-CTRL" Name="quad_wrapper_control_sets_placed.rpt"/>
   <File Type="PLACE-IO" Name="quad_wrapper_io_placed.rpt"/>
   <File Type="PWROPT-TIMING" Name="quad_wrapper_timing_summary_pwropted.rpt"/>
-  <File Type="PLACE-DCP" Name="quad_wrapper_placed.dcp"/>
   <File Type="PLACE-UTIL-PB" Name="quad_wrapper_utilization_placed.pb"/>
   <File Type="PHYSOPT-TIMING" Name="quad_wrapper_timing_summary_physopted.rpt"/>
   <File Type="PWROPT-DRC" Name="quad_wrapper_drc_pwropted.rpt"/>
-  <File Type="PWROPT-DCP" Name="quad_wrapper_pwropt.dcp"/>
   <File Type="PLACE-UTIL" Name="quad_wrapper_utilization_placed.rpt"/>
   <File Type="POSTPLACE-PWROPT-TIMING" Name="quad_wrapper_timing_summary_postplace_pwropted.rpt"/>
   <File Type="OPT-TIMING" Name="quad_wrapper_timing_summary_opted.rpt"/>
   <File Type="OPT-HWDEF" Name="quad_wrapper.hwdef"/>
   <File Type="PLACE-CLK" Name="quad_wrapper_clock_utilization_placed.rpt"/>
-  <File Type="RDI-RDI" Name="quad_wrapper.vdi"/>
-  <File Type="PLACE-TIMING" Name="quad_wrapper_timing_summary_placed.rpt"/>
-  <File Type="INIT-TIMING" Name="quad_wrapper_timing_summary_init.rpt"/>
-  <File Type="OPT-DRC" Name="quad_wrapper_drc_opted.rpt"/>
-  <File Type="OPT-DCP" Name="quad_wrapper_opt.dcp"/>
-  <File Type="OPT-METHODOLOGY-DRC" Name="quad_wrapper_methodology_drc_opted.rpt"/>
-  <File Type="PLACE-PRE-SIMILARITY" Name="quad_wrapper_incremental_reuse_pre_placed.rpt"/>
-  <File Type="PLACE-SIMILARITY" Name="quad_wrapper_incremental_reuse_placed.rpt"/>
-  <File Type="PA-TCL" Name="quad_wrapper.tcl"/>
-  <File Type="POSTPLACE-PWROPT-DCP" Name="quad_wrapper_postplace_pwropt.dcp"/>
-  <File Type="PHYSOPT-DCP" Name="quad_wrapper_physopt.dcp"/>
-  <File Type="PHYSOPT-DRC" Name="quad_wrapper_drc_physopted.rpt"/>
-  <File Type="ROUTE-ERROR-DCP" Name="quad_wrapper_routed_error.dcp"/>
-  <File Type="ROUTE-DCP" Name="quad_wrapper_routed.dcp"/>
-  <File Type="ROUTE-BLACKBOX-DCP" Name="quad_wrapper_routed_bb.dcp"/>
-  <File Type="ROUTE-DRC" Name="quad_wrapper_drc_routed.rpt"/>
-  <File Type="ROUTE-METHODOLOGY-DRC" Name="quad_wrapper_methodology_drc_routed.rpt"/>
-  <File Type="ROUTE-DRC-PB" Name="quad_wrapper_drc_routed.pb"/>
-  <File Type="ROUTE-METHODOLOGY-DRC-PB" Name="quad_wrapper_methodology_drc_routed.pb"/>
-  <File Type="ROUTE-DRC-RPX" Name="quad_wrapper_drc_routed.rpx"/>
-  <File Type="ROUTE-PWR" Name="quad_wrapper_power_routed.rpt"/>
-  <File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="quad_wrapper_methodology_drc_routed.rpx"/>
-  <File Type="ROUTE-PWR-SUM" Name="quad_wrapper_power_summary_routed.pb"/>
-  <File Type="ROUTE-PWR-RPX" Name="quad_wrapper_power_routed.rpx"/>
   <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
     <Filter Type="Srcs"/>
     <File Path="$PSRCDIR/sources_1/bd/quad/quad.bd">
@@ -105,19 +105,19 @@
     <Step Id="post_route_phys_opt_design"/>
     <Step Id="write_bitstream"/>
   </Strategy>
-  <BlockFileSet Type="BlockSrcs" Name="quad_pwm_recorder_0_8"/>
-  <BlockFileSet Type="BlockSrcs" Name="quad_pwm_signal_out_0_3"/>
+  <BlockFileSet Type="BlockSrcs" Name="quad_pwm_signal_out_0_2"/>
+  <BlockFileSet Type="BlockSrcs" Name="quad_xbar_0"/>
+  <BlockFileSet Type="BlockSrcs" Name="quad_processing_system7_0_0"/>
+  <BlockFileSet Type="BlockSrcs" Name="quad_pwm_recorder_0_1"/>
+  <BlockFileSet Type="BlockSrcs" Name="quad_rst_ps7_0_100M_0"/>
+  <BlockFileSet Type="BlockSrcs" Name="quad_axi_gpio_1_0"/>
+  <BlockFileSet Type="BlockSrcs" Name="quad_pwm_recorder_0_11"/>
+  <BlockFileSet Type="BlockSrcs" Name="quad_pwm_recorder_0_0"/>
+  <BlockFileSet Type="BlockSrcs" Name="quad_axi_gpio_0_0"/>
   <BlockFileSet Type="BlockSrcs" Name="quad_pwm_recorder_0_10"/>
-  <BlockFileSet Type="BlockSrcs" Name="quad_pwm_recorder_0_9"/>
+  <BlockFileSet Type="BlockSrcs" Name="quad_pwm_signal_out_0_3"/>
+  <BlockFileSet Type="BlockSrcs" Name="quad_pwm_recorder_0_8"/>
   <BlockFileSet Type="BlockSrcs" Name="quad_pwm_signal_out_0_1"/>
+  <BlockFileSet Type="BlockSrcs" Name="quad_pwm_recorder_0_9"/>
   <BlockFileSet Type="BlockSrcs" Name="quad_pwm_signal_out_0_0"/>
-  <BlockFileSet Type="BlockSrcs" Name="quad_axi_gpio_0_0"/>
-  <BlockFileSet Type="BlockSrcs" Name="quad_pwm_recorder_0_0"/>
-  <BlockFileSet Type="BlockSrcs" Name="quad_pwm_recorder_0_11"/>
-  <BlockFileSet Type="BlockSrcs" Name="quad_axi_gpio_1_0"/>
-  <BlockFileSet Type="BlockSrcs" Name="quad_rst_ps7_0_100M_0"/>
-  <BlockFileSet Type="BlockSrcs" Name="quad_pwm_recorder_0_1"/>
-  <BlockFileSet Type="BlockSrcs" Name="quad_processing_system7_0_0"/>
-  <BlockFileSet Type="BlockSrcs" Name="quad_xbar_0"/>
-  <BlockFileSet Type="BlockSrcs" Name="quad_pwm_signal_out_0_2"/>
 </GenRun>
diff --git a/quad/vivado_workspace/vivado_workspace.runs/quad_axi_gpio_0_0_synth_1/gen_run.xml b/quad/vivado_workspace/vivado_workspace.runs/quad_axi_gpio_0_0_synth_1/gen_run.xml
index f9fbd57369de068325013e175bb24a1d85a43f11..bbcbf6c7fd59357c47f545ef0d273574ece822f4 100644
--- a/quad/vivado_workspace/vivado_workspace.runs/quad_axi_gpio_0_0_synth_1/gen_run.xml
+++ b/quad/vivado_workspace/vivado_workspace.runs/quad_axi_gpio_0_0_synth_1/gen_run.xml
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="quad_axi_gpio_0_0_synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1510860599">
-  <File Type="VDS-TIMING-PB" Name="quad_axi_gpio_0_0_timing_summary_synth.pb"/>
+  <File Type="RDS-DCP" Name="quad_axi_gpio_0_0.dcp"/>
+  <File Type="RDS-UTIL-PB" Name="quad_axi_gpio_0_0_utilization_synth.pb"/>
   <File Type="VDS-TIMINGSUMMARY" Name="quad_axi_gpio_0_0_timing_summary_synth.rpt"/>
+  <File Type="VDS-TIMING-PB" Name="quad_axi_gpio_0_0_timing_summary_synth.pb"/>
   <File Type="RDS-RDS" Name="quad_axi_gpio_0_0.vds"/>
   <File Type="PA-TCL" Name="quad_axi_gpio_0_0.tcl"/>
   <File Type="RDS-PROPCONSTRS" Name="quad_axi_gpio_0_0_drc_synth.rpt"/>
   <File Type="RDS-UTIL" Name="quad_axi_gpio_0_0_utilization_synth.rpt"/>
-  <File Type="RDS-UTIL-PB" Name="quad_axi_gpio_0_0_utilization_synth.pb"/>
-  <File Type="RDS-DCP" Name="quad_axi_gpio_0_0.dcp"/>
   <FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/quad_axi_gpio_0_0">
     <File Path="$PSRCDIR/sources_1/bd/quad/ip/quad_axi_gpio_0_0/quad_axi_gpio_0_0.xci">
       <FileInfo>
diff --git a/quad/vivado_workspace/vivado_workspace.runs/quad_axi_gpio_1_0_synth_1/gen_run.xml b/quad/vivado_workspace/vivado_workspace.runs/quad_axi_gpio_1_0_synth_1/gen_run.xml
index 08f85b704eb9415facea29b7c74267147575eb21..cb7570a508250f4aec12f3e868fe063b773b5eb2 100644
--- a/quad/vivado_workspace/vivado_workspace.runs/quad_axi_gpio_1_0_synth_1/gen_run.xml
+++ b/quad/vivado_workspace/vivado_workspace.runs/quad_axi_gpio_1_0_synth_1/gen_run.xml
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="quad_axi_gpio_1_0_synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1510860599">
-  <File Type="VDS-TIMING-PB" Name="quad_axi_gpio_1_0_timing_summary_synth.pb"/>
+  <File Type="RDS-DCP" Name="quad_axi_gpio_1_0.dcp"/>
+  <File Type="RDS-UTIL-PB" Name="quad_axi_gpio_1_0_utilization_synth.pb"/>
   <File Type="VDS-TIMINGSUMMARY" Name="quad_axi_gpio_1_0_timing_summary_synth.rpt"/>
+  <File Type="VDS-TIMING-PB" Name="quad_axi_gpio_1_0_timing_summary_synth.pb"/>
   <File Type="RDS-RDS" Name="quad_axi_gpio_1_0.vds"/>
   <File Type="PA-TCL" Name="quad_axi_gpio_1_0.tcl"/>
   <File Type="RDS-PROPCONSTRS" Name="quad_axi_gpio_1_0_drc_synth.rpt"/>
   <File Type="RDS-UTIL" Name="quad_axi_gpio_1_0_utilization_synth.rpt"/>
-  <File Type="RDS-UTIL-PB" Name="quad_axi_gpio_1_0_utilization_synth.pb"/>
-  <File Type="RDS-DCP" Name="quad_axi_gpio_1_0.dcp"/>
   <FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/quad_axi_gpio_1_0">
     <File Path="$PSRCDIR/sources_1/bd/quad/ip/quad_axi_gpio_1_0/quad_axi_gpio_1_0.xci">
       <FileInfo>
diff --git a/quad/vivado_workspace/vivado_workspace.runs/quad_processing_system7_0_0_synth_1/gen_run.xml b/quad/vivado_workspace/vivado_workspace.runs/quad_processing_system7_0_0_synth_1/gen_run.xml
index 0415155cf5156c21074cbe997194ad8adb1adc5f..3c9f32e0603eb7795f496a25549597d8941ef66d 100644
--- a/quad/vivado_workspace/vivado_workspace.runs/quad_processing_system7_0_0_synth_1/gen_run.xml
+++ b/quad/vivado_workspace/vivado_workspace.runs/quad_processing_system7_0_0_synth_1/gen_run.xml
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="quad_processing_system7_0_0_synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1510863088">
-  <File Type="VDS-TIMINGSUMMARY" Name="quad_processing_system7_0_0_timing_summary_synth.rpt"/>
+  <File Type="VDS-TIMING-PB" Name="quad_processing_system7_0_0_timing_summary_synth.pb"/>
+  <File Type="RDS-RDS" Name="quad_processing_system7_0_0.vds"/>
   <File Type="PA-TCL" Name="quad_processing_system7_0_0.tcl"/>
+  <File Type="VDS-TIMINGSUMMARY" Name="quad_processing_system7_0_0_timing_summary_synth.rpt"/>
   <File Type="RDS-DCP" Name="quad_processing_system7_0_0.dcp"/>
   <File Type="RDS-UTIL-PB" Name="quad_processing_system7_0_0_utilization_synth.pb"/>
   <File Type="RDS-UTIL" Name="quad_processing_system7_0_0_utilization_synth.rpt"/>
   <File Type="RDS-PROPCONSTRS" Name="quad_processing_system7_0_0_drc_synth.rpt"/>
-  <File Type="RDS-RDS" Name="quad_processing_system7_0_0.vds"/>
-  <File Type="VDS-TIMING-PB" Name="quad_processing_system7_0_0_timing_summary_synth.pb"/>
   <FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/quad_processing_system7_0_0">
     <File Path="$PSRCDIR/sources_1/bd/quad/ip/quad_processing_system7_0_0/quad_processing_system7_0_0.xci">
       <FileInfo>
diff --git a/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_recorder_0_0_synth_1/gen_run.xml b/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_recorder_0_0_synth_1/gen_run.xml
index 615b79c33db9748536435f8709356d669e0cec20..83663bf9b03ca9dcfa404ffe0403e7f7e0f46f48 100644
--- a/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_recorder_0_0_synth_1/gen_run.xml
+++ b/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_recorder_0_0_synth_1/gen_run.xml
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="quad_pwm_recorder_0_0_synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1512863829">
-  <File Type="VDS-TIMING-PB" Name="quad_pwm_recorder_0_0_timing_summary_synth.pb"/>
+  <File Type="RDS-DCP" Name="quad_pwm_recorder_0_0.dcp"/>
+  <File Type="RDS-UTIL-PB" Name="quad_pwm_recorder_0_0_utilization_synth.pb"/>
   <File Type="VDS-TIMINGSUMMARY" Name="quad_pwm_recorder_0_0_timing_summary_synth.rpt"/>
+  <File Type="VDS-TIMING-PB" Name="quad_pwm_recorder_0_0_timing_summary_synth.pb"/>
   <File Type="RDS-RDS" Name="quad_pwm_recorder_0_0.vds"/>
   <File Type="PA-TCL" Name="quad_pwm_recorder_0_0.tcl"/>
   <File Type="RDS-PROPCONSTRS" Name="quad_pwm_recorder_0_0_drc_synth.rpt"/>
   <File Type="RDS-UTIL" Name="quad_pwm_recorder_0_0_utilization_synth.rpt"/>
-  <File Type="RDS-UTIL-PB" Name="quad_pwm_recorder_0_0_utilization_synth.pb"/>
-  <File Type="RDS-DCP" Name="quad_pwm_recorder_0_0.dcp"/>
   <FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/quad_pwm_recorder_0_0">
     <File Path="$PSRCDIR/sources_1/bd/quad/ip/quad_pwm_recorder_0_0/quad_pwm_recorder_0_0.xci">
       <FileInfo>
@@ -35,9 +35,7 @@
     </Config>
   </FileSet>
   <Strategy Version="1" Minor="2">
-    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
-      <Desc>Vivado Synthesis Defaults</Desc>
-    </StratHandle>
+    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
     <Step Id="synth_design"/>
   </Strategy>
 </GenRun>
diff --git a/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_recorder_0_10_synth_1/gen_run.xml b/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_recorder_0_10_synth_1/gen_run.xml
index d7a918d803f11f0cc288523d251f8a7d1cb81988..1841a33b92e73bb2fa64c622ce4c5562af91960c 100644
--- a/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_recorder_0_10_synth_1/gen_run.xml
+++ b/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_recorder_0_10_synth_1/gen_run.xml
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="quad_pwm_recorder_0_10_synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1512863829">
-  <File Type="VDS-TIMING-PB" Name="quad_pwm_recorder_0_10_timing_summary_synth.pb"/>
+  <File Type="RDS-DCP" Name="quad_pwm_recorder_0_10.dcp"/>
+  <File Type="RDS-UTIL-PB" Name="quad_pwm_recorder_0_10_utilization_synth.pb"/>
   <File Type="VDS-TIMINGSUMMARY" Name="quad_pwm_recorder_0_10_timing_summary_synth.rpt"/>
+  <File Type="VDS-TIMING-PB" Name="quad_pwm_recorder_0_10_timing_summary_synth.pb"/>
   <File Type="RDS-RDS" Name="quad_pwm_recorder_0_10.vds"/>
   <File Type="PA-TCL" Name="quad_pwm_recorder_0_10.tcl"/>
   <File Type="RDS-PROPCONSTRS" Name="quad_pwm_recorder_0_10_drc_synth.rpt"/>
   <File Type="RDS-UTIL" Name="quad_pwm_recorder_0_10_utilization_synth.rpt"/>
-  <File Type="RDS-UTIL-PB" Name="quad_pwm_recorder_0_10_utilization_synth.pb"/>
-  <File Type="RDS-DCP" Name="quad_pwm_recorder_0_10.dcp"/>
   <FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/quad_pwm_recorder_0_10">
     <File Path="$PSRCDIR/sources_1/bd/quad/ip/quad_pwm_recorder_0_10/quad_pwm_recorder_0_10.xci">
       <FileInfo>
@@ -35,9 +35,7 @@
     </Config>
   </FileSet>
   <Strategy Version="1" Minor="2">
-    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
-      <Desc>Vivado Synthesis Defaults</Desc>
-    </StratHandle>
+    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
     <Step Id="synth_design"/>
   </Strategy>
 </GenRun>
diff --git a/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_recorder_0_11_synth_1/gen_run.xml b/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_recorder_0_11_synth_1/gen_run.xml
index c5840df28262576932e1e06e0922795012c66976..7c767140b2f2e84f9a6ecde6d15e677afb80775f 100644
--- a/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_recorder_0_11_synth_1/gen_run.xml
+++ b/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_recorder_0_11_synth_1/gen_run.xml
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="quad_pwm_recorder_0_11_synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1512863829">
-  <File Type="VDS-TIMING-PB" Name="quad_pwm_recorder_0_11_timing_summary_synth.pb"/>
+  <File Type="RDS-DCP" Name="quad_pwm_recorder_0_11.dcp"/>
+  <File Type="RDS-UTIL-PB" Name="quad_pwm_recorder_0_11_utilization_synth.pb"/>
   <File Type="VDS-TIMINGSUMMARY" Name="quad_pwm_recorder_0_11_timing_summary_synth.rpt"/>
+  <File Type="VDS-TIMING-PB" Name="quad_pwm_recorder_0_11_timing_summary_synth.pb"/>
   <File Type="RDS-RDS" Name="quad_pwm_recorder_0_11.vds"/>
   <File Type="PA-TCL" Name="quad_pwm_recorder_0_11.tcl"/>
   <File Type="RDS-PROPCONSTRS" Name="quad_pwm_recorder_0_11_drc_synth.rpt"/>
   <File Type="RDS-UTIL" Name="quad_pwm_recorder_0_11_utilization_synth.rpt"/>
-  <File Type="RDS-UTIL-PB" Name="quad_pwm_recorder_0_11_utilization_synth.pb"/>
-  <File Type="RDS-DCP" Name="quad_pwm_recorder_0_11.dcp"/>
   <FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/quad_pwm_recorder_0_11">
     <File Path="$PSRCDIR/sources_1/bd/quad/ip/quad_pwm_recorder_0_11/quad_pwm_recorder_0_11.xci">
       <FileInfo>
@@ -35,9 +35,7 @@
     </Config>
   </FileSet>
   <Strategy Version="1" Minor="2">
-    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
-      <Desc>Vivado Synthesis Defaults</Desc>
-    </StratHandle>
+    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
     <Step Id="synth_design"/>
   </Strategy>
 </GenRun>
diff --git a/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_recorder_0_1_synth_1/gen_run.xml b/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_recorder_0_1_synth_1/gen_run.xml
index 702069063feb415743a28c428649d2a085940173..5c0ff80fe0ba6edb6affbdabf5cb3c5ec8608ee9 100644
--- a/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_recorder_0_1_synth_1/gen_run.xml
+++ b/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_recorder_0_1_synth_1/gen_run.xml
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="quad_pwm_recorder_0_1_synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1512863829">
-  <File Type="VDS-TIMING-PB" Name="quad_pwm_recorder_0_1_timing_summary_synth.pb"/>
+  <File Type="RDS-DCP" Name="quad_pwm_recorder_0_1.dcp"/>
+  <File Type="RDS-UTIL-PB" Name="quad_pwm_recorder_0_1_utilization_synth.pb"/>
   <File Type="VDS-TIMINGSUMMARY" Name="quad_pwm_recorder_0_1_timing_summary_synth.rpt"/>
+  <File Type="VDS-TIMING-PB" Name="quad_pwm_recorder_0_1_timing_summary_synth.pb"/>
   <File Type="RDS-RDS" Name="quad_pwm_recorder_0_1.vds"/>
   <File Type="PA-TCL" Name="quad_pwm_recorder_0_1.tcl"/>
   <File Type="RDS-PROPCONSTRS" Name="quad_pwm_recorder_0_1_drc_synth.rpt"/>
   <File Type="RDS-UTIL" Name="quad_pwm_recorder_0_1_utilization_synth.rpt"/>
-  <File Type="RDS-UTIL-PB" Name="quad_pwm_recorder_0_1_utilization_synth.pb"/>
-  <File Type="RDS-DCP" Name="quad_pwm_recorder_0_1.dcp"/>
   <FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/quad_pwm_recorder_0_1">
     <File Path="$PSRCDIR/sources_1/bd/quad/ip/quad_pwm_recorder_0_1/quad_pwm_recorder_0_1.xci">
       <FileInfo>
@@ -35,9 +35,7 @@
     </Config>
   </FileSet>
   <Strategy Version="1" Minor="2">
-    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
-      <Desc>Vivado Synthesis Defaults</Desc>
-    </StratHandle>
+    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
     <Step Id="synth_design"/>
   </Strategy>
 </GenRun>
diff --git a/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_recorder_0_8_synth_1/gen_run.xml b/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_recorder_0_8_synth_1/gen_run.xml
index 9d36da121e70aa54076e82ccab6d82ca5d73f1c4..c1fb743334a1edb3e0123a776175689a1e797fd2 100644
--- a/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_recorder_0_8_synth_1/gen_run.xml
+++ b/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_recorder_0_8_synth_1/gen_run.xml
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="quad_pwm_recorder_0_8_synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1512863829">
-  <File Type="VDS-TIMING-PB" Name="quad_pwm_recorder_0_8_timing_summary_synth.pb"/>
+  <File Type="RDS-DCP" Name="quad_pwm_recorder_0_8.dcp"/>
+  <File Type="RDS-UTIL-PB" Name="quad_pwm_recorder_0_8_utilization_synth.pb"/>
   <File Type="VDS-TIMINGSUMMARY" Name="quad_pwm_recorder_0_8_timing_summary_synth.rpt"/>
+  <File Type="VDS-TIMING-PB" Name="quad_pwm_recorder_0_8_timing_summary_synth.pb"/>
   <File Type="RDS-RDS" Name="quad_pwm_recorder_0_8.vds"/>
   <File Type="PA-TCL" Name="quad_pwm_recorder_0_8.tcl"/>
   <File Type="RDS-PROPCONSTRS" Name="quad_pwm_recorder_0_8_drc_synth.rpt"/>
   <File Type="RDS-UTIL" Name="quad_pwm_recorder_0_8_utilization_synth.rpt"/>
-  <File Type="RDS-UTIL-PB" Name="quad_pwm_recorder_0_8_utilization_synth.pb"/>
-  <File Type="RDS-DCP" Name="quad_pwm_recorder_0_8.dcp"/>
   <FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/quad_pwm_recorder_0_8">
     <File Path="$PSRCDIR/sources_1/bd/quad/ip/quad_pwm_recorder_0_8/quad_pwm_recorder_0_8.xci">
       <FileInfo>
@@ -35,9 +35,7 @@
     </Config>
   </FileSet>
   <Strategy Version="1" Minor="2">
-    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
-      <Desc>Vivado Synthesis Defaults</Desc>
-    </StratHandle>
+    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
     <Step Id="synth_design"/>
   </Strategy>
 </GenRun>
diff --git a/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_recorder_0_9_synth_1/gen_run.xml b/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_recorder_0_9_synth_1/gen_run.xml
index a5e19b1a381b6e70d2fef711ea1ccafd7846dce9..c60fd367e9cf8da82ca0c7955a1f9f15d1efe448 100644
--- a/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_recorder_0_9_synth_1/gen_run.xml
+++ b/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_recorder_0_9_synth_1/gen_run.xml
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="quad_pwm_recorder_0_9_synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1512863829">
-  <File Type="VDS-TIMING-PB" Name="quad_pwm_recorder_0_9_timing_summary_synth.pb"/>
+  <File Type="RDS-DCP" Name="quad_pwm_recorder_0_9.dcp"/>
+  <File Type="RDS-UTIL-PB" Name="quad_pwm_recorder_0_9_utilization_synth.pb"/>
   <File Type="VDS-TIMINGSUMMARY" Name="quad_pwm_recorder_0_9_timing_summary_synth.rpt"/>
+  <File Type="VDS-TIMING-PB" Name="quad_pwm_recorder_0_9_timing_summary_synth.pb"/>
   <File Type="RDS-RDS" Name="quad_pwm_recorder_0_9.vds"/>
   <File Type="PA-TCL" Name="quad_pwm_recorder_0_9.tcl"/>
   <File Type="RDS-PROPCONSTRS" Name="quad_pwm_recorder_0_9_drc_synth.rpt"/>
   <File Type="RDS-UTIL" Name="quad_pwm_recorder_0_9_utilization_synth.rpt"/>
-  <File Type="RDS-UTIL-PB" Name="quad_pwm_recorder_0_9_utilization_synth.pb"/>
-  <File Type="RDS-DCP" Name="quad_pwm_recorder_0_9.dcp"/>
   <FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/quad_pwm_recorder_0_9">
     <File Path="$PSRCDIR/sources_1/bd/quad/ip/quad_pwm_recorder_0_9/quad_pwm_recorder_0_9.xci">
       <FileInfo>
@@ -35,9 +35,7 @@
     </Config>
   </FileSet>
   <Strategy Version="1" Minor="2">
-    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
-      <Desc>Vivado Synthesis Defaults</Desc>
-    </StratHandle>
+    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
     <Step Id="synth_design"/>
   </Strategy>
 </GenRun>
diff --git a/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_signal_out_0_0_synth_1/gen_run.xml b/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_signal_out_0_0_synth_1/gen_run.xml
index 4a83662dbeff5c16aed201b25c9d32a1a71fdb98..13ca48dcd674b2714c32b7a45fab252e2fe7957f 100644
--- a/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_signal_out_0_0_synth_1/gen_run.xml
+++ b/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_signal_out_0_0_synth_1/gen_run.xml
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="quad_pwm_signal_out_0_0_synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1512863829">
-  <File Type="VDS-TIMING-PB" Name="quad_pwm_signal_out_0_0_timing_summary_synth.pb"/>
+  <File Type="RDS-DCP" Name="quad_pwm_signal_out_0_0.dcp"/>
+  <File Type="RDS-UTIL-PB" Name="quad_pwm_signal_out_0_0_utilization_synth.pb"/>
   <File Type="VDS-TIMINGSUMMARY" Name="quad_pwm_signal_out_0_0_timing_summary_synth.rpt"/>
+  <File Type="VDS-TIMING-PB" Name="quad_pwm_signal_out_0_0_timing_summary_synth.pb"/>
   <File Type="RDS-RDS" Name="quad_pwm_signal_out_0_0.vds"/>
   <File Type="PA-TCL" Name="quad_pwm_signal_out_0_0.tcl"/>
   <File Type="RDS-PROPCONSTRS" Name="quad_pwm_signal_out_0_0_drc_synth.rpt"/>
   <File Type="RDS-UTIL" Name="quad_pwm_signal_out_0_0_utilization_synth.rpt"/>
-  <File Type="RDS-UTIL-PB" Name="quad_pwm_signal_out_0_0_utilization_synth.pb"/>
-  <File Type="RDS-DCP" Name="quad_pwm_signal_out_0_0.dcp"/>
   <FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/quad_pwm_signal_out_0_0">
     <File Path="$PSRCDIR/sources_1/bd/quad/ip/quad_pwm_signal_out_0_0/quad_pwm_signal_out_0_0.xci">
       <FileInfo>
@@ -35,9 +35,7 @@
     </Config>
   </FileSet>
   <Strategy Version="1" Minor="2">
-    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
-      <Desc>Vivado Synthesis Defaults</Desc>
-    </StratHandle>
+    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
     <Step Id="synth_design"/>
   </Strategy>
 </GenRun>
diff --git a/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_signal_out_0_1_synth_1/gen_run.xml b/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_signal_out_0_1_synth_1/gen_run.xml
index 124431ba0d3885ce39c0d7e8710b9f8bf709b309..57350e8feeb4024b8a15d27334b76a5f808dbdd2 100644
--- a/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_signal_out_0_1_synth_1/gen_run.xml
+++ b/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_signal_out_0_1_synth_1/gen_run.xml
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="quad_pwm_signal_out_0_1_synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1512863829">
-  <File Type="VDS-TIMING-PB" Name="quad_pwm_signal_out_0_1_timing_summary_synth.pb"/>
+  <File Type="RDS-DCP" Name="quad_pwm_signal_out_0_1.dcp"/>
+  <File Type="RDS-UTIL-PB" Name="quad_pwm_signal_out_0_1_utilization_synth.pb"/>
   <File Type="VDS-TIMINGSUMMARY" Name="quad_pwm_signal_out_0_1_timing_summary_synth.rpt"/>
+  <File Type="VDS-TIMING-PB" Name="quad_pwm_signal_out_0_1_timing_summary_synth.pb"/>
   <File Type="RDS-RDS" Name="quad_pwm_signal_out_0_1.vds"/>
   <File Type="PA-TCL" Name="quad_pwm_signal_out_0_1.tcl"/>
   <File Type="RDS-PROPCONSTRS" Name="quad_pwm_signal_out_0_1_drc_synth.rpt"/>
   <File Type="RDS-UTIL" Name="quad_pwm_signal_out_0_1_utilization_synth.rpt"/>
-  <File Type="RDS-UTIL-PB" Name="quad_pwm_signal_out_0_1_utilization_synth.pb"/>
-  <File Type="RDS-DCP" Name="quad_pwm_signal_out_0_1.dcp"/>
   <FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/quad_pwm_signal_out_0_1">
     <File Path="$PSRCDIR/sources_1/bd/quad/ip/quad_pwm_signal_out_0_1/quad_pwm_signal_out_0_1.xci">
       <FileInfo>
@@ -35,9 +35,7 @@
     </Config>
   </FileSet>
   <Strategy Version="1" Minor="2">
-    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
-      <Desc>Vivado Synthesis Defaults</Desc>
-    </StratHandle>
+    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
     <Step Id="synth_design"/>
   </Strategy>
 </GenRun>
diff --git a/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_signal_out_0_2_synth_1/gen_run.xml b/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_signal_out_0_2_synth_1/gen_run.xml
index ad5769af5e2ff232dca8dadcb566beef73f89664..9ee6ec2aba477f2bc2f93cb12c6b85481842ef95 100644
--- a/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_signal_out_0_2_synth_1/gen_run.xml
+++ b/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_signal_out_0_2_synth_1/gen_run.xml
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="quad_pwm_signal_out_0_2_synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1512863828">
-  <File Type="VDS-TIMING-PB" Name="quad_pwm_signal_out_0_2_timing_summary_synth.pb"/>
+  <File Type="RDS-DCP" Name="quad_pwm_signal_out_0_2.dcp"/>
+  <File Type="RDS-UTIL-PB" Name="quad_pwm_signal_out_0_2_utilization_synth.pb"/>
   <File Type="VDS-TIMINGSUMMARY" Name="quad_pwm_signal_out_0_2_timing_summary_synth.rpt"/>
+  <File Type="VDS-TIMING-PB" Name="quad_pwm_signal_out_0_2_timing_summary_synth.pb"/>
   <File Type="RDS-RDS" Name="quad_pwm_signal_out_0_2.vds"/>
   <File Type="PA-TCL" Name="quad_pwm_signal_out_0_2.tcl"/>
   <File Type="RDS-PROPCONSTRS" Name="quad_pwm_signal_out_0_2_drc_synth.rpt"/>
   <File Type="RDS-UTIL" Name="quad_pwm_signal_out_0_2_utilization_synth.rpt"/>
-  <File Type="RDS-UTIL-PB" Name="quad_pwm_signal_out_0_2_utilization_synth.pb"/>
-  <File Type="RDS-DCP" Name="quad_pwm_signal_out_0_2.dcp"/>
   <FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/quad_pwm_signal_out_0_2">
     <File Path="$PSRCDIR/sources_1/bd/quad/ip/quad_pwm_signal_out_0_2/quad_pwm_signal_out_0_2.xci">
       <FileInfo>
@@ -35,9 +35,7 @@
     </Config>
   </FileSet>
   <Strategy Version="1" Minor="2">
-    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
-      <Desc>Vivado Synthesis Defaults</Desc>
-    </StratHandle>
+    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
     <Step Id="synth_design"/>
   </Strategy>
 </GenRun>
diff --git a/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_signal_out_0_3_synth_1/gen_run.xml b/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_signal_out_0_3_synth_1/gen_run.xml
index 3637a15cdfa7e884f1d6fdb57f8da6829b8e3598..e4addce9f2d525101cac8681cd8a6e46460a14f2 100644
--- a/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_signal_out_0_3_synth_1/gen_run.xml
+++ b/quad/vivado_workspace/vivado_workspace.runs/quad_pwm_signal_out_0_3_synth_1/gen_run.xml
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="quad_pwm_signal_out_0_3_synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1512863829">
-  <File Type="VDS-TIMING-PB" Name="quad_pwm_signal_out_0_3_timing_summary_synth.pb"/>
+  <File Type="RDS-DCP" Name="quad_pwm_signal_out_0_3.dcp"/>
+  <File Type="RDS-UTIL-PB" Name="quad_pwm_signal_out_0_3_utilization_synth.pb"/>
   <File Type="VDS-TIMINGSUMMARY" Name="quad_pwm_signal_out_0_3_timing_summary_synth.rpt"/>
+  <File Type="VDS-TIMING-PB" Name="quad_pwm_signal_out_0_3_timing_summary_synth.pb"/>
   <File Type="RDS-RDS" Name="quad_pwm_signal_out_0_3.vds"/>
   <File Type="PA-TCL" Name="quad_pwm_signal_out_0_3.tcl"/>
   <File Type="RDS-PROPCONSTRS" Name="quad_pwm_signal_out_0_3_drc_synth.rpt"/>
   <File Type="RDS-UTIL" Name="quad_pwm_signal_out_0_3_utilization_synth.rpt"/>
-  <File Type="RDS-UTIL-PB" Name="quad_pwm_signal_out_0_3_utilization_synth.pb"/>
-  <File Type="RDS-DCP" Name="quad_pwm_signal_out_0_3.dcp"/>
   <FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/quad_pwm_signal_out_0_3">
     <File Path="$PSRCDIR/sources_1/bd/quad/ip/quad_pwm_signal_out_0_3/quad_pwm_signal_out_0_3.xci">
       <FileInfo>
@@ -35,9 +35,7 @@
     </Config>
   </FileSet>
   <Strategy Version="1" Minor="2">
-    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
-      <Desc>Vivado Synthesis Defaults</Desc>
-    </StratHandle>
+    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
     <Step Id="synth_design"/>
   </Strategy>
 </GenRun>
diff --git a/quad/vivado_workspace/vivado_workspace.runs/quad_rst_ps7_0_100M_0_synth_1/gen_run.xml b/quad/vivado_workspace/vivado_workspace.runs/quad_rst_ps7_0_100M_0_synth_1/gen_run.xml
index 7c7a4605423940cb3528327cb9c3a26b22c7b53f..5458efc32e2fa298ad8804d9b6cada9a9aada438 100644
--- a/quad/vivado_workspace/vivado_workspace.runs/quad_rst_ps7_0_100M_0_synth_1/gen_run.xml
+++ b/quad/vivado_workspace/vivado_workspace.runs/quad_rst_ps7_0_100M_0_synth_1/gen_run.xml
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="quad_rst_ps7_0_100M_0_synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1510860600">
-  <File Type="VDS-TIMING-PB" Name="quad_rst_ps7_0_100M_0_timing_summary_synth.pb"/>
+  <File Type="RDS-DCP" Name="quad_rst_ps7_0_100M_0.dcp"/>
+  <File Type="RDS-UTIL-PB" Name="quad_rst_ps7_0_100M_0_utilization_synth.pb"/>
   <File Type="VDS-TIMINGSUMMARY" Name="quad_rst_ps7_0_100M_0_timing_summary_synth.rpt"/>
+  <File Type="VDS-TIMING-PB" Name="quad_rst_ps7_0_100M_0_timing_summary_synth.pb"/>
   <File Type="RDS-RDS" Name="quad_rst_ps7_0_100M_0.vds"/>
   <File Type="PA-TCL" Name="quad_rst_ps7_0_100M_0.tcl"/>
   <File Type="RDS-PROPCONSTRS" Name="quad_rst_ps7_0_100M_0_drc_synth.rpt"/>
   <File Type="RDS-UTIL" Name="quad_rst_ps7_0_100M_0_utilization_synth.rpt"/>
-  <File Type="RDS-UTIL-PB" Name="quad_rst_ps7_0_100M_0_utilization_synth.pb"/>
-  <File Type="RDS-DCP" Name="quad_rst_ps7_0_100M_0.dcp"/>
   <FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/quad_rst_ps7_0_100M_0">
     <File Path="$PSRCDIR/sources_1/bd/quad/ip/quad_rst_ps7_0_100M_0/quad_rst_ps7_0_100M_0.xci">
       <FileInfo>
diff --git a/quad/vivado_workspace/vivado_workspace.runs/quad_xbar_0_synth_1/gen_run.xml b/quad/vivado_workspace/vivado_workspace.runs/quad_xbar_0_synth_1/gen_run.xml
index 6078b74c402e8421d92b0caf98de5635785aa61a..6c5966114c3c7553f33b9b7b1672673904e52b70 100644
--- a/quad/vivado_workspace/vivado_workspace.runs/quad_xbar_0_synth_1/gen_run.xml
+++ b/quad/vivado_workspace/vivado_workspace.runs/quad_xbar_0_synth_1/gen_run.xml
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="quad_xbar_0_synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1512863828">
-  <File Type="VDS-TIMING-PB" Name="quad_xbar_0_timing_summary_synth.pb"/>
+  <File Type="PA-TCL" Name="quad_xbar_0.tcl"/>
+  <File Type="RDS-RDS" Name="quad_xbar_0.vds"/>
   <File Type="VDS-TIMINGSUMMARY" Name="quad_xbar_0_timing_summary_synth.rpt"/>
+  <File Type="VDS-TIMING-PB" Name="quad_xbar_0_timing_summary_synth.pb"/>
   <File Type="RDS-DCP" Name="quad_xbar_0.dcp"/>
   <File Type="RDS-UTIL-PB" Name="quad_xbar_0_utilization_synth.pb"/>
   <File Type="RDS-UTIL" Name="quad_xbar_0_utilization_synth.rpt"/>
   <File Type="RDS-PROPCONSTRS" Name="quad_xbar_0_drc_synth.rpt"/>
-  <File Type="RDS-RDS" Name="quad_xbar_0.vds"/>
-  <File Type="PA-TCL" Name="quad_xbar_0.tcl"/>
   <FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/quad_xbar_0">
     <File Path="$PSRCDIR/sources_1/bd/quad/ip/quad_xbar_0/quad_xbar_0.xci">
       <FileInfo>
diff --git a/quad/vivado_workspace/vivado_workspace.runs/synth_1/gen_run.xml b/quad/vivado_workspace/vivado_workspace.runs/synth_1/gen_run.xml
index de87c9e9553e740433e9a0410ff083fe17cd1ea8..33134283032614ca541f21b4858bf6ee28febfdb 100644
--- a/quad/vivado_workspace/vivado_workspace.runs/synth_1/gen_run.xml
+++ b/quad/vivado_workspace/vivado_workspace.runs/synth_1/gen_run.xml
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1512863829">
-  <File Type="VDS-TIMING-PB" Name="quad_wrapper_timing_summary_synth.pb"/>
+  <File Type="PA-TCL" Name="quad_wrapper.tcl"/>
+  <File Type="RDS-RDS" Name="quad_wrapper.vds"/>
   <File Type="VDS-TIMINGSUMMARY" Name="quad_wrapper_timing_summary_synth.rpt"/>
+  <File Type="VDS-TIMING-PB" Name="quad_wrapper_timing_summary_synth.pb"/>
   <File Type="RDS-DCP" Name="quad_wrapper.dcp"/>
   <File Type="RDS-UTIL-PB" Name="quad_wrapper_utilization_synth.pb"/>
   <File Type="RDS-UTIL" Name="quad_wrapper_utilization_synth.rpt"/>
   <File Type="RDS-PROPCONSTRS" Name="quad_wrapper_drc_synth.rpt"/>
-  <File Type="RDS-RDS" Name="quad_wrapper.vds"/>
-  <File Type="PA-TCL" Name="quad_wrapper.tcl"/>
   <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
     <Filter Type="Srcs"/>
     <File Path="$PSRCDIR/sources_1/bd/quad/quad.bd">
@@ -45,19 +45,19 @@
     <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
     <Step Id="synth_design"/>
   </Strategy>
-  <BlockFileSet Type="BlockSrcs" Name="quad_pwm_recorder_0_8"/>
-  <BlockFileSet Type="BlockSrcs" Name="quad_pwm_signal_out_0_3"/>
+  <BlockFileSet Type="BlockSrcs" Name="quad_processing_system7_0_0"/>
+  <BlockFileSet Type="BlockSrcs" Name="quad_xbar_0"/>
+  <BlockFileSet Type="BlockSrcs" Name="quad_pwm_recorder_0_1"/>
+  <BlockFileSet Type="BlockSrcs" Name="quad_axi_gpio_0_0"/>
+  <BlockFileSet Type="BlockSrcs" Name="quad_axi_gpio_1_0"/>
+  <BlockFileSet Type="BlockSrcs" Name="quad_pwm_recorder_0_11"/>
+  <BlockFileSet Type="BlockSrcs" Name="quad_pwm_recorder_0_0"/>
+  <BlockFileSet Type="BlockSrcs" Name="quad_rst_ps7_0_100M_0"/>
+  <BlockFileSet Type="BlockSrcs" Name="quad_pwm_signal_out_0_2"/>
   <BlockFileSet Type="BlockSrcs" Name="quad_pwm_recorder_0_10"/>
-  <BlockFileSet Type="BlockSrcs" Name="quad_pwm_recorder_0_9"/>
+  <BlockFileSet Type="BlockSrcs" Name="quad_pwm_signal_out_0_3"/>
+  <BlockFileSet Type="BlockSrcs" Name="quad_pwm_recorder_0_8"/>
   <BlockFileSet Type="BlockSrcs" Name="quad_pwm_signal_out_0_1"/>
+  <BlockFileSet Type="BlockSrcs" Name="quad_pwm_recorder_0_9"/>
   <BlockFileSet Type="BlockSrcs" Name="quad_pwm_signal_out_0_0"/>
-  <BlockFileSet Type="BlockSrcs" Name="quad_pwm_signal_out_0_2"/>
-  <BlockFileSet Type="BlockSrcs" Name="quad_rst_ps7_0_100M_0"/>
-  <BlockFileSet Type="BlockSrcs" Name="quad_pwm_recorder_0_0"/>
-  <BlockFileSet Type="BlockSrcs" Name="quad_pwm_recorder_0_11"/>
-  <BlockFileSet Type="BlockSrcs" Name="quad_axi_gpio_1_0"/>
-  <BlockFileSet Type="BlockSrcs" Name="quad_axi_gpio_0_0"/>
-  <BlockFileSet Type="BlockSrcs" Name="quad_pwm_recorder_0_1"/>
-  <BlockFileSet Type="BlockSrcs" Name="quad_xbar_0"/>
-  <BlockFileSet Type="BlockSrcs" Name="quad_processing_system7_0_0"/>
 </GenRun>
diff --git a/quad/vivado_workspace/vivado_workspace.srcs/sources_1/bd/quad/ip/quad_processing_system7_0_0/quad_processing_system7_0_0.xml b/quad/vivado_workspace/vivado_workspace.srcs/sources_1/bd/quad/ip/quad_processing_system7_0_0/quad_processing_system7_0_0.xml
index 1e47d9df52aa8fbd7467cb790ac71d58675dbcb1..dcffd489add3565e305a2d9353457e3be19803ef 100644
--- a/quad/vivado_workspace/vivado_workspace.srcs/sources_1/bd/quad/ip/quad_processing_system7_0_0/quad_processing_system7_0_0.xml
+++ b/quad/vivado_workspace/vivado_workspace.srcs/sources_1/bd/quad/ip/quad_processing_system7_0_0/quad_processing_system7_0_0.xml
@@ -32282,13 +32282,6 @@
     <spirit:parameter>
       <spirit:name>PCW_I2C0_RESET_IO</spirit:name>
       <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_I2C0_RESET_IO" spirit:choiceRef="choice_list_d679c87d" spirit:order="6904">&lt;Select></spirit:value>
-      <spirit:vendorExtensions>
-        <xilinx:parameterInfo>
-          <xilinx:enablement>
-            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_I2C0_RESET_IO">false</xilinx:isEnabled>
-          </xilinx:enablement>
-        </xilinx:parameterInfo>
-      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PCW_I2C1_PERIPHERAL_ENABLE</spirit:name>
diff --git a/quad/vivado_workspace/vivado_workspace.srcs/sources_1/bd/quad/quad.bd b/quad/vivado_workspace/vivado_workspace.srcs/sources_1/bd/quad/quad.bd
index 0413feba47e0bb4cb3ff7cd127fcdb8dd9e5d6bb..6035de254d6535329e2c8a613dfc01961de6cc04 100644
--- a/quad/vivado_workspace/vivado_workspace.srcs/sources_1/bd/quad/quad.bd
+++ b/quad/vivado_workspace/vivado_workspace.srcs/sources_1/bd/quad/quad.bd
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<bd:repository xmlns:bd="http://www.xilinx.com/bd" bd:BoundaryCRC="0xD8318C2266273238" bd:device="xc7z010clg400-1" bd:isValidated="true" bd:synthFlowMode="Hierarchical" bd:tool_version="2017.1" bd:top="quad" bd:version="1.00.a">
+<bd:repository xmlns:bd="http://www.xilinx.com/bd" bd:BoundaryCRC="0xD8318C2266273238" bd:device="xc7z010clg400-1" bd:synthFlowMode="Hierarchical" bd:tool_version="2017.1" bd:top="quad" bd:version="1.00.a">
 
   <spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
     <spirit:vendor>xilinx.com</spirit:vendor>
@@ -18,133 +18,14 @@
         <spirit:master/>
         <spirit:busType spirit:library="interface" spirit:name="ddrx" spirit:vendor="xilinx.com" spirit:version="1.0"/>
         <spirit:abstractionType spirit:library="interface" spirit:name="ddrx_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>CAN_DEBUG</spirit:name>
-            <spirit:value>false</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="default"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
-          </spirit:parameter>
-          <spirit:parameter>
-            <spirit:name>TIMEPERIOD_PS</spirit:name>
-            <spirit:value>1250</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="default"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
-          </spirit:parameter>
-          <spirit:parameter>
-            <spirit:name>MEMORY_TYPE</spirit:name>
-            <spirit:value>COMPONENTS</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="default"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
-          </spirit:parameter>
-          <spirit:parameter>
-            <spirit:name>DATA_WIDTH</spirit:name>
-            <spirit:value>8</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="default"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
-          </spirit:parameter>
-          <spirit:parameter>
-            <spirit:name>CS_ENABLED</spirit:name>
-            <spirit:value>true</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="default"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
-          </spirit:parameter>
-          <spirit:parameter>
-            <spirit:name>DATA_MASK_ENABLED</spirit:name>
-            <spirit:value>true</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="default"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
-          </spirit:parameter>
-          <spirit:parameter>
-            <spirit:name>SLOT</spirit:name>
-            <spirit:value>Single</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="default"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
-          </spirit:parameter>
-          <spirit:parameter>
-            <spirit:name>MEM_ADDR_MAP</spirit:name>
-            <spirit:value>ROW_COLUMN_BANK</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="default"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
-          </spirit:parameter>
-          <spirit:parameter>
-            <spirit:name>BURST_LENGTH</spirit:name>
-            <spirit:value>8</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="default"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
-          </spirit:parameter>
-          <spirit:parameter>
-            <spirit:name>AXI_ARBITRATION_SCHEME</spirit:name>
-            <spirit:value>TDM</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="default"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
-          </spirit:parameter>
-          <spirit:parameter>
-            <spirit:name>CAS_LATENCY</spirit:name>
-            <spirit:value>11</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="default"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
-          </spirit:parameter>
-          <spirit:parameter>
-            <spirit:name>CAS_WRITE_LATENCY</spirit:name>
-            <spirit:value>11</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="default"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
-          </spirit:parameter>
-        </spirit:parameters>
+        <spirit:parameters/>
       </spirit:busInterface>
       <spirit:busInterface>
         <spirit:name>FIXED_IO</spirit:name>
         <spirit:master/>
         <spirit:busType spirit:library="display_processing_system7" spirit:name="fixedio" spirit:vendor="xilinx.com" spirit:version="1.0"/>
         <spirit:abstractionType spirit:library="display_processing_system7" spirit:name="fixedio_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>CAN_DEBUG</spirit:name>
-            <spirit:value>false</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="default"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
-          </spirit:parameter>
-        </spirit:parameters>
+        <spirit:parameters/>
       </spirit:busInterface>
       <spirit:busInterface>
         <spirit:name>btns_4bits</spirit:name>
@@ -187,63 +68,63 @@
           </spirit:wire>
         </spirit:port>
         <spirit:port>
-          <spirit:name>pwm_recorder_1</spirit:name>
+          <spirit:name>pwm_out_sm_3</spirit:name>
           <spirit:wire>
-            <spirit:direction>in</spirit:direction>
+            <spirit:direction>out</spirit:direction>
           </spirit:wire>
         </spirit:port>
         <spirit:port>
-          <spirit:name>pwm_recorder_0</spirit:name>
+          <spirit:name>pwm_out_sm_2</spirit:name>
           <spirit:wire>
-            <spirit:direction>in</spirit:direction>
+            <spirit:direction>out</spirit:direction>
           </spirit:wire>
         </spirit:port>
         <spirit:port>
-          <spirit:name>pwm_recorder_2</spirit:name>
+          <spirit:name>pwm_out_sm_1</spirit:name>
           <spirit:wire>
-            <spirit:direction>in</spirit:direction>
+            <spirit:direction>out</spirit:direction>
           </spirit:wire>
         </spirit:port>
         <spirit:port>
-          <spirit:name>pwm_recorder_3</spirit:name>
+          <spirit:name>pwm_out_sm_0</spirit:name>
           <spirit:wire>
-            <spirit:direction>in</spirit:direction>
+            <spirit:direction>out</spirit:direction>
           </spirit:wire>
         </spirit:port>
         <spirit:port>
-          <spirit:name>pwm_recorder_5</spirit:name>
+          <spirit:name>pwm_recorder_0</spirit:name>
           <spirit:wire>
             <spirit:direction>in</spirit:direction>
           </spirit:wire>
         </spirit:port>
         <spirit:port>
-          <spirit:name>pwm_recorder_4</spirit:name>
+          <spirit:name>pwm_recorder_1</spirit:name>
           <spirit:wire>
             <spirit:direction>in</spirit:direction>
           </spirit:wire>
         </spirit:port>
         <spirit:port>
-          <spirit:name>pwm_out_sm_0</spirit:name>
+          <spirit:name>pwm_recorder_2</spirit:name>
           <spirit:wire>
-            <spirit:direction>out</spirit:direction>
+            <spirit:direction>in</spirit:direction>
           </spirit:wire>
         </spirit:port>
         <spirit:port>
-          <spirit:name>pwm_out_sm_2</spirit:name>
+          <spirit:name>pwm_recorder_3</spirit:name>
           <spirit:wire>
-            <spirit:direction>out</spirit:direction>
+            <spirit:direction>in</spirit:direction>
           </spirit:wire>
         </spirit:port>
         <spirit:port>
-          <spirit:name>pwm_out_sm_1</spirit:name>
+          <spirit:name>pwm_recorder_4</spirit:name>
           <spirit:wire>
-            <spirit:direction>out</spirit:direction>
+            <spirit:direction>in</spirit:direction>
           </spirit:wire>
         </spirit:port>
         <spirit:port>
-          <spirit:name>pwm_out_sm_3</spirit:name>
+          <spirit:name>pwm_recorder_5</spirit:name>
           <spirit:wire>
-            <spirit:direction>out</spirit:direction>
+            <spirit:direction>in</spirit:direction>
           </spirit:wire>
         </spirit:port>
       </spirit:ports>
@@ -581,6 +462,16 @@
         <spirit:internalPortReference spirit:componentRef="rst_ps7_0_100M" spirit:portRef="peripheral_aresetn"/>
         <spirit:internalPortReference spirit:componentRef="axi_gpio_0" spirit:portRef="s_axi_aresetn"/>
         <spirit:internalPortReference spirit:componentRef="axi_gpio_1" spirit:portRef="s_axi_aresetn"/>
+        <spirit:internalPortReference spirit:componentRef="pwm_signal_out_0" spirit:portRef="s_axi_aresetn"/>
+        <spirit:internalPortReference spirit:componentRef="pwm_signal_out_1" spirit:portRef="s_axi_aresetn"/>
+        <spirit:internalPortReference spirit:componentRef="pwm_signal_out_2" spirit:portRef="s_axi_aresetn"/>
+        <spirit:internalPortReference spirit:componentRef="pwm_signal_out_3" spirit:portRef="s_axi_aresetn"/>
+        <spirit:internalPortReference spirit:componentRef="pwm_recorder_0" spirit:portRef="s_axi_aresetn"/>
+        <spirit:internalPortReference spirit:componentRef="pwm_recorder_1" spirit:portRef="s_axi_aresetn"/>
+        <spirit:internalPortReference spirit:componentRef="pwm_recorder_2" spirit:portRef="s_axi_aresetn"/>
+        <spirit:internalPortReference spirit:componentRef="pwm_recorder_3" spirit:portRef="s_axi_aresetn"/>
+        <spirit:internalPortReference spirit:componentRef="pwm_recorder_4" spirit:portRef="s_axi_aresetn"/>
+        <spirit:internalPortReference spirit:componentRef="pwm_recorder_5" spirit:portRef="s_axi_aresetn"/>
         <spirit:internalPortReference spirit:componentRef="ps7_0_axi_periph" spirit:portRef="S00_ARESETN"/>
         <spirit:internalPortReference spirit:componentRef="ps7_0_axi_periph" spirit:portRef="M00_ARESETN"/>
         <spirit:internalPortReference spirit:componentRef="ps7_0_axi_periph" spirit:portRef="M01_ARESETN"/>
@@ -594,16 +485,6 @@
         <spirit:internalPortReference spirit:componentRef="ps7_0_axi_periph" spirit:portRef="M09_ARESETN"/>
         <spirit:internalPortReference spirit:componentRef="ps7_0_axi_periph" spirit:portRef="M10_ARESETN"/>
         <spirit:internalPortReference spirit:componentRef="ps7_0_axi_periph" spirit:portRef="M11_ARESETN"/>
-        <spirit:internalPortReference spirit:componentRef="pwm_signal_out_0" spirit:portRef="s_axi_aresetn"/>
-        <spirit:internalPortReference spirit:componentRef="pwm_signal_out_1" spirit:portRef="s_axi_aresetn"/>
-        <spirit:internalPortReference spirit:componentRef="pwm_signal_out_2" spirit:portRef="s_axi_aresetn"/>
-        <spirit:internalPortReference spirit:componentRef="pwm_signal_out_3" spirit:portRef="s_axi_aresetn"/>
-        <spirit:internalPortReference spirit:componentRef="pwm_recorder_0" spirit:portRef="s_axi_aresetn"/>
-        <spirit:internalPortReference spirit:componentRef="pwm_recorder_1" spirit:portRef="s_axi_aresetn"/>
-        <spirit:internalPortReference spirit:componentRef="pwm_recorder_2" spirit:portRef="s_axi_aresetn"/>
-        <spirit:internalPortReference spirit:componentRef="pwm_recorder_3" spirit:portRef="s_axi_aresetn"/>
-        <spirit:internalPortReference spirit:componentRef="pwm_recorder_4" spirit:portRef="s_axi_aresetn"/>
-        <spirit:internalPortReference spirit:componentRef="pwm_recorder_5" spirit:portRef="s_axi_aresetn"/>
       </spirit:adHocConnection>
       <spirit:adHocConnection>
         <spirit:name>rst_ps7_0_100M_interconnect_aresetn</spirit:name>
@@ -627,6 +508,16 @@
         <spirit:internalPortReference spirit:componentRef="axi_gpio_0" spirit:portRef="s_axi_aclk"/>
         <spirit:internalPortReference spirit:componentRef="axi_gpio_1" spirit:portRef="s_axi_aclk"/>
         <spirit:internalPortReference spirit:componentRef="rst_ps7_0_100M" spirit:portRef="slowest_sync_clk"/>
+        <spirit:internalPortReference spirit:componentRef="pwm_signal_out_0" spirit:portRef="s_axi_aclk"/>
+        <spirit:internalPortReference spirit:componentRef="pwm_signal_out_1" spirit:portRef="s_axi_aclk"/>
+        <spirit:internalPortReference spirit:componentRef="pwm_signal_out_2" spirit:portRef="s_axi_aclk"/>
+        <spirit:internalPortReference spirit:componentRef="pwm_signal_out_3" spirit:portRef="s_axi_aclk"/>
+        <spirit:internalPortReference spirit:componentRef="pwm_recorder_0" spirit:portRef="s_axi_aclk"/>
+        <spirit:internalPortReference spirit:componentRef="pwm_recorder_1" spirit:portRef="s_axi_aclk"/>
+        <spirit:internalPortReference spirit:componentRef="pwm_recorder_2" spirit:portRef="s_axi_aclk"/>
+        <spirit:internalPortReference spirit:componentRef="pwm_recorder_3" spirit:portRef="s_axi_aclk"/>
+        <spirit:internalPortReference spirit:componentRef="pwm_recorder_4" spirit:portRef="s_axi_aclk"/>
+        <spirit:internalPortReference spirit:componentRef="pwm_recorder_5" spirit:portRef="s_axi_aclk"/>
         <spirit:internalPortReference spirit:componentRef="ps7_0_axi_periph" spirit:portRef="S00_ACLK"/>
         <spirit:internalPortReference spirit:componentRef="ps7_0_axi_periph" spirit:portRef="M00_ACLK"/>
         <spirit:internalPortReference spirit:componentRef="ps7_0_axi_periph" spirit:portRef="M01_ACLK"/>
@@ -641,16 +532,6 @@
         <spirit:internalPortReference spirit:componentRef="ps7_0_axi_periph" spirit:portRef="M09_ACLK"/>
         <spirit:internalPortReference spirit:componentRef="ps7_0_axi_periph" spirit:portRef="M10_ACLK"/>
         <spirit:internalPortReference spirit:componentRef="ps7_0_axi_periph" spirit:portRef="M11_ACLK"/>
-        <spirit:internalPortReference spirit:componentRef="pwm_signal_out_0" spirit:portRef="s_axi_aclk"/>
-        <spirit:internalPortReference spirit:componentRef="pwm_signal_out_1" spirit:portRef="s_axi_aclk"/>
-        <spirit:internalPortReference spirit:componentRef="pwm_signal_out_2" spirit:portRef="s_axi_aclk"/>
-        <spirit:internalPortReference spirit:componentRef="pwm_signal_out_3" spirit:portRef="s_axi_aclk"/>
-        <spirit:internalPortReference spirit:componentRef="pwm_recorder_0" spirit:portRef="s_axi_aclk"/>
-        <spirit:internalPortReference spirit:componentRef="pwm_recorder_1" spirit:portRef="s_axi_aclk"/>
-        <spirit:internalPortReference spirit:componentRef="pwm_recorder_2" spirit:portRef="s_axi_aclk"/>
-        <spirit:internalPortReference spirit:componentRef="pwm_recorder_3" spirit:portRef="s_axi_aclk"/>
-        <spirit:internalPortReference spirit:componentRef="pwm_recorder_4" spirit:portRef="s_axi_aclk"/>
-        <spirit:internalPortReference spirit:componentRef="pwm_recorder_5" spirit:portRef="s_axi_aclk"/>
       </spirit:adHocConnection>
       <spirit:adHocConnection>
         <spirit:name>pwm_signal_out_3_pwm_out_sm</spirit:name>
@@ -827,11 +708,6 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -874,20 +750,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>S00_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>S00_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -930,20 +796,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>M00_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>M00_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -986,20 +842,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>M01_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>M01_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -1042,20 +888,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>M02_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>M02_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -1098,20 +934,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>M03_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>M03_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -1154,20 +980,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>M04_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>M04_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -1210,20 +1026,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>M05_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>M05_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -1266,20 +1072,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>M06_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>M06_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -1322,20 +1118,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>M07_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>M07_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -1378,20 +1164,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>M08_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>M08_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -1434,20 +1210,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>M09_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>M09_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -1490,20 +1256,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>M10_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>M10_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -1546,20 +1302,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>M11_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>M11_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -2149,20 +1895,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>M_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>M_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -2205,20 +1941,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>S_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>S_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -2331,20 +2057,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>M_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>M_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -2387,20 +2103,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>S_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>S_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -2513,20 +2219,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>M_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>M_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -2569,20 +2265,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>S_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>S_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -2695,20 +2381,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>M_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>M_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -2751,20 +2427,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>S_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>S_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -2877,20 +2543,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>M_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>M_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -2933,20 +2589,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>S_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>S_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -3059,20 +2705,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>M_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>M_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -3115,20 +2751,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>S_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>S_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -3241,20 +2867,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>M_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>M_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -3297,20 +2913,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>S_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>S_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -3423,20 +3029,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>M_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>M_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -3479,20 +3075,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>S_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>S_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -3605,20 +3191,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>M_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>M_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -3661,20 +3237,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>S_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>S_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -3787,20 +3353,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>M_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>M_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -3843,20 +3399,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>S_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>S_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -3969,20 +3515,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>M_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>M_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -4025,20 +3561,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>S_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>S_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -4151,20 +3677,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>M_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>M_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -4207,20 +3723,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>S_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>S_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -4333,20 +3839,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>M_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>M_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
@@ -4389,20 +3885,10 @@
           <spirit:parameter>
             <spirit:name>ASSOCIATED_BUSIF</spirit:name>
             <spirit:value>S_AXI</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>ASSOCIATED_RESET</spirit:name>
             <spirit:value>S_ARESETN</spirit:value>
-            <spirit:vendorExtensions>
-              <bd:configElementInfos>
-                <bd:configElementInfo bd:valueSource="user"/>
-              </bd:configElementInfos>
-            </spirit:vendorExtensions>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:busInterface>
diff --git a/quad/vivado_workspace/vivado_workspace.srcs/sources_1/bd/quad/quad.bxml b/quad/vivado_workspace/vivado_workspace.srcs/sources_1/bd/quad/quad.bxml
index de68d98b22138a05fa363de5690aee5ba6ef202b..b170d1d657171b033fe5dd400b97e0bc134dfdc1 100644
--- a/quad/vivado_workspace/vivado_workspace.srcs/sources_1/bd/quad/quad.bxml
+++ b/quad/vivado_workspace/vivado_workspace.srcs/sources_1/bd/quad/quad.bxml
@@ -2,9 +2,9 @@
 <Root MajorVersion="0" MinorVersion="33">
   <CompositeFile CompositeFileTopName="quad" CanBeSetAsTop="false" CanDisplayChildGraph="true">
     <Description>Composite Fileset</Description>
-    <Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1512863825"/>
-    <Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1512863825"/>
-    <Generation Name="SIMULATION" State="GENERATED" Timestamp="1512863825"/>
+    <Generation Name="SYNTHESIS" State="STALE" Timestamp="1512953360"/>
+    <Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1512953360"/>
+    <Generation Name="SIMULATION" State="STALE" Timestamp="1512953360"/>
     <FileCollection Name="SOURCES" Type="SOURCES">
       <File Name="ip/quad_processing_system7_0_0/quad_processing_system7_0_0.xci" Type="IP">
         <Instance HierarchyPath="processing_system7_0"/>
diff --git a/quad/vivado_workspace/vivado_workspace.xpr b/quad/vivado_workspace/vivado_workspace.xpr
index 6842788c466217f3b437d3acb169ddb176e0260a..527d573689683a2b90cea828b982c1c649ba04c1 100644
--- a/quad/vivado_workspace/vivado_workspace.xpr
+++ b/quad/vivado_workspace/vivado_workspace.xpr
@@ -68,14 +68,8 @@
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
-        <CompFileExtendedInfo CompFileName="quad.bd" FileRelPathName="ip/quad_axi_gpio_0_0/quad_axi_gpio_0_0.xci">
-          <Proxy FileSetName="quad_axi_gpio_0_0"/>
-        </CompFileExtendedInfo>
-        <CompFileExtendedInfo CompFileName="quad.bd" FileRelPathName="ip/quad_axi_gpio_1_0/quad_axi_gpio_1_0.xci">
-          <Proxy FileSetName="quad_axi_gpio_1_0"/>
-        </CompFileExtendedInfo>
-        <CompFileExtendedInfo CompFileName="quad.bd" FileRelPathName="ip/quad_processing_system7_0_0/quad_processing_system7_0_0.xci">
-          <Proxy FileSetName="quad_processing_system7_0_0"/>
+        <CompFileExtendedInfo CompFileName="quad.bd" FileRelPathName="ip/quad_pwm_signal_out_0_0/quad_pwm_signal_out_0_0.xci">
+          <Proxy FileSetName="quad_pwm_signal_out_0_0"/>
         </CompFileExtendedInfo>
         <CompFileExtendedInfo CompFileName="quad.bd" FileRelPathName="ip/quad_xbar_0/quad_xbar_0.xci">
           <Proxy FileSetName="quad_xbar_0"/>
@@ -83,14 +77,23 @@
         <CompFileExtendedInfo CompFileName="quad.bd" FileRelPathName="ip/quad_rst_ps7_0_100M_0/quad_rst_ps7_0_100M_0.xci">
           <Proxy FileSetName="quad_rst_ps7_0_100M_0"/>
         </CompFileExtendedInfo>
+        <CompFileExtendedInfo CompFileName="quad.bd" FileRelPathName="ip/quad_pwm_signal_out_0_1/quad_pwm_signal_out_0_1.xci">
+          <Proxy FileSetName="quad_pwm_signal_out_0_1"/>
+        </CompFileExtendedInfo>
         <CompFileExtendedInfo CompFileName="quad.bd" FileRelPathName="ip/quad_pwm_signal_out_0_2/quad_pwm_signal_out_0_2.xci">
           <Proxy FileSetName="quad_pwm_signal_out_0_2"/>
         </CompFileExtendedInfo>
-        <CompFileExtendedInfo CompFileName="quad.bd" FileRelPathName="ip/quad_pwm_signal_out_0_0/quad_pwm_signal_out_0_0.xci">
-          <Proxy FileSetName="quad_pwm_signal_out_0_0"/>
+        <CompFileExtendedInfo CompFileName="quad.bd" FileRelPathName="ip/quad_pwm_signal_out_0_3/quad_pwm_signal_out_0_3.xci">
+          <Proxy FileSetName="quad_pwm_signal_out_0_3"/>
         </CompFileExtendedInfo>
-        <CompFileExtendedInfo CompFileName="quad.bd" FileRelPathName="ip/quad_pwm_signal_out_0_1/quad_pwm_signal_out_0_1.xci">
-          <Proxy FileSetName="quad_pwm_signal_out_0_1"/>
+        <CompFileExtendedInfo CompFileName="quad.bd" FileRelPathName="ip/quad_pwm_recorder_0_0/quad_pwm_recorder_0_0.xci">
+          <Proxy FileSetName="quad_pwm_recorder_0_0"/>
+        </CompFileExtendedInfo>
+        <CompFileExtendedInfo CompFileName="quad.bd" FileRelPathName="ip/quad_pwm_recorder_0_1/quad_pwm_recorder_0_1.xci">
+          <Proxy FileSetName="quad_pwm_recorder_0_1"/>
+        </CompFileExtendedInfo>
+        <CompFileExtendedInfo CompFileName="quad.bd" FileRelPathName="ip/quad_pwm_recorder_0_8/quad_pwm_recorder_0_8.xci">
+          <Proxy FileSetName="quad_pwm_recorder_0_8"/>
         </CompFileExtendedInfo>
         <CompFileExtendedInfo CompFileName="quad.bd" FileRelPathName="ip/quad_pwm_recorder_0_9/quad_pwm_recorder_0_9.xci">
           <Proxy FileSetName="quad_pwm_recorder_0_9"/>
@@ -101,17 +104,14 @@
         <CompFileExtendedInfo CompFileName="quad.bd" FileRelPathName="ip/quad_pwm_recorder_0_11/quad_pwm_recorder_0_11.xci">
           <Proxy FileSetName="quad_pwm_recorder_0_11"/>
         </CompFileExtendedInfo>
-        <CompFileExtendedInfo CompFileName="quad.bd" FileRelPathName="ip/quad_pwm_signal_out_0_3/quad_pwm_signal_out_0_3.xci">
-          <Proxy FileSetName="quad_pwm_signal_out_0_3"/>
-        </CompFileExtendedInfo>
-        <CompFileExtendedInfo CompFileName="quad.bd" FileRelPathName="ip/quad_pwm_recorder_0_0/quad_pwm_recorder_0_0.xci">
-          <Proxy FileSetName="quad_pwm_recorder_0_0"/>
+        <CompFileExtendedInfo CompFileName="quad.bd" FileRelPathName="ip/quad_processing_system7_0_0/quad_processing_system7_0_0.xci">
+          <Proxy FileSetName="quad_processing_system7_0_0"/>
         </CompFileExtendedInfo>
-        <CompFileExtendedInfo CompFileName="quad.bd" FileRelPathName="ip/quad_pwm_recorder_0_1/quad_pwm_recorder_0_1.xci">
-          <Proxy FileSetName="quad_pwm_recorder_0_1"/>
+        <CompFileExtendedInfo CompFileName="quad.bd" FileRelPathName="ip/quad_axi_gpio_0_0/quad_axi_gpio_0_0.xci">
+          <Proxy FileSetName="quad_axi_gpio_0_0"/>
         </CompFileExtendedInfo>
-        <CompFileExtendedInfo CompFileName="quad.bd" FileRelPathName="ip/quad_pwm_recorder_0_8/quad_pwm_recorder_0_8.xci">
-          <Proxy FileSetName="quad_pwm_recorder_0_8"/>
+        <CompFileExtendedInfo CompFileName="quad.bd" FileRelPathName="ip/quad_axi_gpio_1_0/quad_axi_gpio_1_0.xci">
+          <Proxy FileSetName="quad_axi_gpio_1_0"/>
         </CompFileExtendedInfo>
       </File>
       <File Path="$PSRCDIR/sources_1/bd/quad/hdl/quad_wrapper.vhd">
@@ -319,9 +319,7 @@
     </Run>
     <Run Id="quad_pwm_signal_out_0_2_synth_1" Type="Ft3:Synth" SrcSet="quad_pwm_signal_out_0_2" Part="xc7z010clg400-1" ConstrsSet="quad_pwm_signal_out_0_2" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/quad_pwm_signal_out_0_2_synth_1" IncludeInArchive="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -330,9 +328,7 @@
     </Run>
     <Run Id="quad_pwm_signal_out_0_0_synth_1" Type="Ft3:Synth" SrcSet="quad_pwm_signal_out_0_0" Part="xc7z010clg400-1" ConstrsSet="quad_pwm_signal_out_0_0" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/quad_pwm_signal_out_0_0_synth_1" IncludeInArchive="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -341,9 +337,7 @@
     </Run>
     <Run Id="quad_pwm_signal_out_0_1_synth_1" Type="Ft3:Synth" SrcSet="quad_pwm_signal_out_0_1" Part="xc7z010clg400-1" ConstrsSet="quad_pwm_signal_out_0_1" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/quad_pwm_signal_out_0_1_synth_1" IncludeInArchive="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -352,9 +346,7 @@
     </Run>
     <Run Id="quad_pwm_recorder_0_9_synth_1" Type="Ft3:Synth" SrcSet="quad_pwm_recorder_0_9" Part="xc7z010clg400-1" ConstrsSet="quad_pwm_recorder_0_9" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/quad_pwm_recorder_0_9_synth_1" IncludeInArchive="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -363,9 +355,7 @@
     </Run>
     <Run Id="quad_pwm_recorder_0_10_synth_1" Type="Ft3:Synth" SrcSet="quad_pwm_recorder_0_10" Part="xc7z010clg400-1" ConstrsSet="quad_pwm_recorder_0_10" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/quad_pwm_recorder_0_10_synth_1" IncludeInArchive="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -374,9 +364,7 @@
     </Run>
     <Run Id="quad_pwm_recorder_0_11_synth_1" Type="Ft3:Synth" SrcSet="quad_pwm_recorder_0_11" Part="xc7z010clg400-1" ConstrsSet="quad_pwm_recorder_0_11" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/quad_pwm_recorder_0_11_synth_1" IncludeInArchive="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -385,9 +373,7 @@
     </Run>
     <Run Id="quad_pwm_signal_out_0_3_synth_1" Type="Ft3:Synth" SrcSet="quad_pwm_signal_out_0_3" Part="xc7z010clg400-1" ConstrsSet="quad_pwm_signal_out_0_3" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/quad_pwm_signal_out_0_3_synth_1" IncludeInArchive="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -396,9 +382,7 @@
     </Run>
     <Run Id="quad_pwm_recorder_0_0_synth_1" Type="Ft3:Synth" SrcSet="quad_pwm_recorder_0_0" Part="xc7z010clg400-1" ConstrsSet="quad_pwm_recorder_0_0" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/quad_pwm_recorder_0_0_synth_1" IncludeInArchive="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -407,9 +391,7 @@
     </Run>
     <Run Id="quad_pwm_recorder_0_1_synth_1" Type="Ft3:Synth" SrcSet="quad_pwm_recorder_0_1" Part="xc7z010clg400-1" ConstrsSet="quad_pwm_recorder_0_1" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/quad_pwm_recorder_0_1_synth_1" IncludeInArchive="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -418,9 +400,7 @@
     </Run>
     <Run Id="quad_pwm_recorder_0_8_synth_1" Type="Ft3:Synth" SrcSet="quad_pwm_recorder_0_8" Part="xc7z010clg400-1" ConstrsSet="quad_pwm_recorder_0_8" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/quad_pwm_recorder_0_8_synth_1" IncludeInArchive="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -526,9 +506,7 @@
     </Run>
     <Run Id="quad_pwm_signal_out_0_2_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="quad_pwm_signal_out_0_2" Description="Default settings for Implementation." SynthRun="quad_pwm_signal_out_0_2_synth_1" IncludeInArchive="false">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017">
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017"/>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -544,9 +522,7 @@
     </Run>
     <Run Id="quad_pwm_signal_out_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="quad_pwm_signal_out_0_0" Description="Default settings for Implementation." SynthRun="quad_pwm_signal_out_0_0_synth_1" IncludeInArchive="false">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017">
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017"/>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -562,9 +538,7 @@
     </Run>
     <Run Id="quad_pwm_signal_out_0_1_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="quad_pwm_signal_out_0_1" Description="Default settings for Implementation." SynthRun="quad_pwm_signal_out_0_1_synth_1" IncludeInArchive="false">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017">
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017"/>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -580,9 +554,7 @@
     </Run>
     <Run Id="quad_pwm_recorder_0_9_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="quad_pwm_recorder_0_9" Description="Default settings for Implementation." SynthRun="quad_pwm_recorder_0_9_synth_1" IncludeInArchive="false">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017">
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017"/>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -598,9 +570,7 @@
     </Run>
     <Run Id="quad_pwm_recorder_0_10_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="quad_pwm_recorder_0_10" Description="Default settings for Implementation." SynthRun="quad_pwm_recorder_0_10_synth_1" IncludeInArchive="false">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017">
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017"/>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -616,9 +586,7 @@
     </Run>
     <Run Id="quad_pwm_recorder_0_11_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="quad_pwm_recorder_0_11" Description="Default settings for Implementation." SynthRun="quad_pwm_recorder_0_11_synth_1" IncludeInArchive="false">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017">
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017"/>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -634,9 +602,7 @@
     </Run>
     <Run Id="quad_pwm_signal_out_0_3_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="quad_pwm_signal_out_0_3" Description="Default settings for Implementation." SynthRun="quad_pwm_signal_out_0_3_synth_1" IncludeInArchive="false">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017">
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017"/>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -652,9 +618,7 @@
     </Run>
     <Run Id="quad_pwm_recorder_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="quad_pwm_recorder_0_0" Description="Default settings for Implementation." SynthRun="quad_pwm_recorder_0_0_synth_1" IncludeInArchive="false">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017">
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017"/>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -670,9 +634,7 @@
     </Run>
     <Run Id="quad_pwm_recorder_0_1_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="quad_pwm_recorder_0_1" Description="Default settings for Implementation." SynthRun="quad_pwm_recorder_0_1_synth_1" IncludeInArchive="false">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017">
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017"/>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -688,9 +650,7 @@
     </Run>
     <Run Id="quad_pwm_recorder_0_8_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="quad_pwm_recorder_0_8" Description="Default settings for Implementation." SynthRun="quad_pwm_recorder_0_8_synth_1" IncludeInArchive="false">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017">
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017"/>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
diff --git a/quad/xps_projects/system/XpsGuiSessionLock b/quad/xps_projects/system/XpsGuiSessionLock
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/quad/xps_projects/system/__xps/ise/system.xreport b/quad/xps_projects/system/__xps/ise/system.xreport
index 4ff62d6034a92a6cd7d7756a031953c703cbfcd3..ebdddb7a027a9671827a3a4a9a4c946beef34082 100644
--- a/quad/xps_projects/system/__xps/ise/system.xreport
+++ b/quad/xps_projects/system/__xps/ise/system.xreport
@@ -1,9 +1,9 @@
 <?xml version='1.0' encoding='UTF-8'?>
 <report-views version="2.0" >
  <header>
-  <DateModified>2017-12-09T18:06:46</DateModified>
+  <DateModified>2017-12-10T19:00:59</DateModified>
   <ModuleName>system</ModuleName>
-  <SummaryTimeStamp>2017-12-09T18:06:46</SummaryTimeStamp>
+  <SummaryTimeStamp>2017-12-10T19:00:59</SummaryTimeStamp>
   <SavedFilePath>/local/ucart/MicroCART/quad/xps_projects/system/__xps/ise/system.xreport</SavedFilePath>
   <FilterFile>filter.filter</FilterFile>
   <SavedFilterFilePath>/local/ucart/MicroCART/quad/xps_projects/system/__xps/ise</SavedFilterFilePath>
diff --git a/quad/xps_projects/system/__xps/system.xml b/quad/xps_projects/system/__xps/system.xml
index 9eceb95f0c1f11c2cbdce14b60c6bcfc00398c8a..314cd749675ed2bb2a79acedf77d12eceb675213 100644
--- a/quad/xps_projects/system/__xps/system.xml
+++ b/quad/xps_projects/system/__xps/system.xml
@@ -1,189 +1,7 @@
-<EDKSYSTEM EDKVERSION="14.7" EDWVERSION="1.2" TIMESTAMP="Sat Dec  9 18:06:47 2017">
 
-  <SYSTEMINFO ARCH="zynq" DEVICE="xc7z010" PACKAGE="clg400" PART="xc7z010clg400-1" SOURCE="/local/ucart/MicroCART/quad/xps_projects/system/system.xmp" SPEEDGRADE="-1"/>
+<EDKSYSTEM EDKVERSION="14.7" EDWVERSION="1.2" TIMESTAMP="Sun Dec 10 19:00:59 2017">
 
-  <EXTERNALPORTS>
-    <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="N" DIR="I" MHS_INDEX="0" NAME="CLK_N" SIGIS="CLK" SIGNAME="CLK">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="clock_generator_0" PORT="CLKIN"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="P" DIR="I" MHS_INDEX="1" NAME="CLK_P" SIGIS="CLK" SIGNAME="CLK">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="clock_generator_0" PORT="CLKIN"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="53" LSB="0" MHS_INDEX="2" MSB="53" NAME="processing_system7_0_MIO" RIGHT="0" SIGNAME="processing_system7_0_MIO">
-      <CONNECTIONS>
-        <CONNECTION BUSINTERFACE="[PS_REQUIRED_EXTERNAL_IO]" INSTANCE="processing_system7_0" PORT="MIO"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="I" MHS_INDEX="3" NAME="processing_system7_0_PS_SRSTB_pin" SIGNAME="processing_system7_0_PS_SRSTB">
-      <CONNECTIONS>
-        <CONNECTION BUSINTERFACE="[PS_REQUIRED_EXTERNAL_IO]" INSTANCE="processing_system7_0" PORT="PS_SRSTB"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="I" MHS_INDEX="4" NAME="processing_system7_0_PS_CLK_pin" SIGIS="CLK" SIGNAME="processing_system7_0_PS_CLK">
-      <CONNECTIONS>
-        <CONNECTION BUSINTERFACE="[PS_REQUIRED_EXTERNAL_IO]" INSTANCE="processing_system7_0" PORT="PS_CLK"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="I" MHS_INDEX="5" NAME="processing_system7_0_PS_PORB_pin" SIGNAME="processing_system7_0_PS_PORB">
-      <CONNECTIONS>
-        <CONNECTION BUSINTERFACE="[PS_REQUIRED_EXTERNAL_IO]" INSTANCE="processing_system7_0" PORT="PS_PORB"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="IO" MHS_INDEX="6" NAME="processing_system7_0_DDR_Clk" SIGIS="CLK" SIGNAME="processing_system7_0_DDR_Clk">
-      <CONNECTIONS>
-        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_Clk"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="IO" MHS_INDEX="7" NAME="processing_system7_0_DDR_Clk_n" SIGIS="CLK" SIGNAME="processing_system7_0_DDR_Clk_n">
-      <CONNECTIONS>
-        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_Clk_n"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="IO" MHS_INDEX="8" NAME="processing_system7_0_DDR_CKE" SIGNAME="processing_system7_0_DDR_CKE">
-      <CONNECTIONS>
-        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_CKE"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="IO" MHS_INDEX="9" NAME="processing_system7_0_DDR_CS_n" SIGNAME="processing_system7_0_DDR_CS_n">
-      <CONNECTIONS>
-        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_CS_n"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="IO" MHS_INDEX="10" NAME="processing_system7_0_DDR_RAS_n" SIGNAME="processing_system7_0_DDR_RAS_n">
-      <CONNECTIONS>
-        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_RAS_n"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="IO" MHS_INDEX="11" NAME="processing_system7_0_DDR_CAS_n" SIGNAME="processing_system7_0_DDR_CAS_n">
-      <CONNECTIONS>
-        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_CAS_n"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="O" MHS_INDEX="12" NAME="processing_system7_0_DDR_WEB_pin" SIGNAME="processing_system7_0_DDR_WEB">
-      <CONNECTIONS>
-        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_WEB"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="2" LSB="0" MHS_INDEX="13" MSB="2" NAME="processing_system7_0_DDR_BankAddr" RIGHT="0" SIGNAME="processing_system7_0_DDR_BankAddr">
-      <CONNECTIONS>
-        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_BankAddr"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="14" LSB="0" MHS_INDEX="14" MSB="14" NAME="processing_system7_0_DDR_Addr" RIGHT="0" SIGNAME="processing_system7_0_DDR_Addr">
-      <CONNECTIONS>
-        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_Addr"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="IO" MHS_INDEX="15" NAME="processing_system7_0_DDR_ODT" SIGNAME="processing_system7_0_DDR_ODT">
-      <CONNECTIONS>
-        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_ODT"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="IO" MHS_INDEX="16" NAME="processing_system7_0_DDR_DRSTB" SIGIS="RST" SIGNAME="processing_system7_0_DDR_DRSTB">
-      <CONNECTIONS>
-        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_DRSTB"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="31" LSB="0" MHS_INDEX="17" MSB="31" NAME="processing_system7_0_DDR_DQ" RIGHT="0" SIGNAME="processing_system7_0_DDR_DQ">
-      <CONNECTIONS>
-        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_DQ"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="18" MSB="3" NAME="processing_system7_0_DDR_DM" RIGHT="0" SIGNAME="processing_system7_0_DDR_DM">
-      <CONNECTIONS>
-        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_DM"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="19" MSB="3" NAME="processing_system7_0_DDR_DQS" RIGHT="0" SIGNAME="processing_system7_0_DDR_DQS">
-      <CONNECTIONS>
-        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_DQS"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="20" MSB="3" NAME="processing_system7_0_DDR_DQS_n" RIGHT="0" SIGNAME="processing_system7_0_DDR_DQS_n">
-      <CONNECTIONS>
-        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_DQS_n"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="IO" MHS_INDEX="21" NAME="processing_system7_0_DDR_VRN" SIGNAME="processing_system7_0_DDR_VRN">
-      <CONNECTIONS>
-        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_VRN"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="IO" MHS_INDEX="22" NAME="processing_system7_0_DDR_VRP" SIGNAME="processing_system7_0_DDR_VRP">
-      <CONNECTIONS>
-        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_VRP"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="I" MHS_INDEX="23" NAME="pwm_recorder_0_pwm_in_master_pin" SIGNAME="pwm_recorder_0_pwm_in_master">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="pwm_recorder_0" PORT="pwm_in_master"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="I" MHS_INDEX="24" NAME="pwm_recorder_1_pwm_in_master_pin" SIGNAME="pwm_recorder_1_pwm_in_master">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="pwm_recorder_1" PORT="pwm_in_master"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="I" MHS_INDEX="25" NAME="pwm_recorder_2_pwm_in_master_pin" SIGNAME="pwm_recorder_2_pwm_in_master">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="pwm_recorder_2" PORT="pwm_in_master"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="I" MHS_INDEX="26" NAME="pwm_recorder_3_pwm_in_master_pin" SIGNAME="pwm_recorder_3_pwm_in_master">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="pwm_recorder_3" PORT="pwm_in_master"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="I" MHS_INDEX="27" NAME="pwm_recorder_4_pwm_in_master_pin" SIGNAME="pwm_recorder_4_pwm_in_master">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="pwm_recorder_4" PORT="pwm_in_master"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="I" MHS_INDEX="28" NAME="pwm_recorder_5_pwm_in_master_pin" SIGNAME="pwm_recorder_5_pwm_in_master">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="pwm_recorder_5" PORT="pwm_in_master"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="29" MSB="3" NAME="BTNs_4Bits_TRI_IO_GPIO_IO_I_pin" RIGHT="0" SIGNAME="BTNs_4Bits_TRI_IO_GPIO_IO_I">
-      <CONNECTIONS>
-        <CONNECTION BUSINTERFACE="[gpio_0]" INSTANCE="BTNs_4Bits_TRI_IO" PORT="GPIO_IO_I"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="O" MHS_INDEX="30" NAME="processing_system7_0_UART0_TX_pin" SIGNAME="processing_system7_0_UART0_TX">
-      <CONNECTIONS>
-        <CONNECTION BUSINTERFACE="[UART_0]" INSTANCE="processing_system7_0" PORT="UART0_TX"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="I" MHS_INDEX="31" NAME="processing_system7_0_UART0_RX_pin" SIGNAME="processing_system7_0_UART0_RX">
-      <CONNECTIONS>
-        <CONNECTION BUSINTERFACE="[UART_0]" INSTANCE="processing_system7_0" PORT="UART0_RX"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="O" MHS_INDEX="32" NAME="pwm_signal_out_wkillswitch_0_pwm_out_sm_pin" SIGNAME="pwm_signal_out_wkillswitch_0_pwm_out_sm">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="pwm_signal_out_wkillswitch_0" PORT="pwm_out_sm"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="O" MHS_INDEX="33" NAME="pwm_signal_out_wkillswitch_1_pwm_out_sm_pin" SIGNAME="pwm_signal_out_wkillswitch_1_pwm_out_sm">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="pwm_signal_out_wkillswitch_1" PORT="pwm_out_sm"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="O" MHS_INDEX="34" NAME="pwm_signal_out_wkillswitch_2_pwm_out_sm_pin" SIGNAME="pwm_signal_out_wkillswitch_2_pwm_out_sm">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="pwm_signal_out_wkillswitch_2" PORT="pwm_out_sm"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="O" MHS_INDEX="35" NAME="pwm_signal_out_wkillswitch_3_pwm_out_sm_pin" SIGNAME="pwm_signal_out_wkillswitch_3_pwm_out_sm">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="pwm_signal_out_wkillswitch_3" PORT="pwm_out_sm"/>
-      </CONNECTIONS>
-    </PORT>
-  </EXTERNALPORTS>
+  <SYSTEMINFO ARCH="zynq" DEVICE="xc7z010" PACKAGE="clg400" PART="xc7z010clg400-1" SOURCE="/local/ucart/MicroCART/quad/xps_projects/system/system.xmp" SPEEDGRADE="-1"/>
 
   <MODULES>
     <MODULE HWVERSION="4.03.a" INSTANCE="clock_generator_0" IPTYPE="PERIPHERAL" MHS_INDEX="0" MODCLASS="IP" MODTYPE="clock_generator">
@@ -192,7 +10,6 @@
       <DOCUMENTATION>
         <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=clock_generator;v=v4_03_a;d=clock_generator.pdf" TYPE="IP"/>
       </DOCUMENTATION>
-      <LICENSEINFO ICON_NAME="ps_core_earlyaccess"/>
       <PARAMETERS>
         <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
         <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_DEVICE" TYPE="STRING" VALUE="7z010"/>
@@ -318,31 +135,78 @@
             <CONNECTION INSTANCE="reset_0" PORT="Dcm_locked"/>
           </CONNECTIONS>
         </PORT>
-        <PORT DIR="O" MPD_INDEX="1" NAME="CLKOUT0" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="2" NAME="CLKOUT1" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="3" NAME="CLKOUT2" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="CLKOUT3" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="5" NAME="CLKOUT4" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="6" NAME="CLKOUT5" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="7" NAME="CLKOUT6" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="8" NAME="CLKOUT7" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="9" NAME="CLKOUT8" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="10" NAME="CLKOUT9" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="11" NAME="CLKOUT10" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="12" NAME="CLKOUT11" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="13" NAME="CLKOUT12" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="14" NAME="CLKOUT13" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="15" NAME="CLKOUT14" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="16" NAME="CLKOUT15" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="17" NAME="CLKFBIN" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="18" NAME="CLKFBOUT" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="19" NAME="PSCLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="20" NAME="PSEN" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="21" NAME="PSINCDEC" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="22" NAME="PSDONE" SIGNAME="__NOC__"/>
-        <PORT DIR="I" MPD_INDEX="23" NAME="RST" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT DIR="O" MPD_INDEX="1" NAME="CLKOUT0" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="2" NAME="CLKOUT1" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="3" NAME="CLKOUT2" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="CLKOUT3" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="5" NAME="CLKOUT4" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="6" NAME="CLKOUT5" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="7" NAME="CLKOUT6" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="8" NAME="CLKOUT7" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="9" NAME="CLKOUT8" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="10" NAME="CLKOUT9" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="11" NAME="CLKOUT10" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="12" NAME="CLKOUT11" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="13" NAME="CLKOUT12" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="14" NAME="CLKOUT13" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="15" NAME="CLKOUT14" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="16" NAME="CLKOUT15" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="17" NAME="CLKFBIN" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="18" NAME="CLKFBOUT" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="19" NAME="PSCLK" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="20" NAME="PSEN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="21" NAME="PSINCDEC" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="22" NAME="PSDONE" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" MPD_INDEX="23" NAME="RST" SIGIS="RST" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
       </PORTS>
       <BUSINTERFACES/>
+      <LICENSEINFO ICON_NAME="ps_core_earlyaccess"/>
     </MODULE>
     <MODULE HWVERSION="3.00.a" INSTANCE="reset_0" IPTYPE="PERIPHERAL" MHS_INDEX="1" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset">
       <DESCRIPTION TYPE="SHORT">Processor System Reset Module</DESCRIPTION>
@@ -350,9 +214,7 @@
       <DOCUMENTATION>
         <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=proc_sys_reset;v=v3_00_a;d=proc_sys_reset.pdf" TYPE="IP"/>
       </DOCUMENTATION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
       <PARAMETERS>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="0" NAME="C_SUBFAMILY" TYPE="string" VALUE="lx"/>
         <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="1" NAME="C_EXT_RST_WIDTH" TYPE="integer" VALUE="4"/>
         <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_AUX_RST_WIDTH" TYPE="integer" VALUE="4"/>
         <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="std_logic" VALUE="1"/>
@@ -369,10 +231,18 @@
             <CONNECTION INSTANCE="clock_generator_0" PORT="LOCKED"/>
           </CONNECTIONS>
         </PORT>
-        <PORT DIR="I" MPD_INDEX="0" NAME="Slowest_sync_clk" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" MPD_INDEX="1" NAME="Ext_Reset_In" SIGIS="RST" SIGNAME="__NOC__"/>
-        <PORT DIR="I" MPD_INDEX="2" NAME="Aux_Reset_In" SIGIS="RST" SIGNAME="__NOC__"/>
-        <PORT DIR="I" MPD_INDEX="3" NAME="MB_Debug_Sys_Rst" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT DIR="I" MPD_INDEX="0" NAME="Slowest_sync_clk" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" MPD_INDEX="1" NAME="Ext_Reset_In" SIGIS="RST" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" MPD_INDEX="2" NAME="Aux_Reset_In" SIGIS="RST" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" MPD_INDEX="3" NAME="MB_Debug_Sys_Rst" SIGIS="RST" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
         <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="4" NAME="Core_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
         <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="5" NAME="Chip_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
         <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="6" NAME="System_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
@@ -385,11 +255,21 @@
         <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="14" NAME="RstcPPCresetcore_1" SIGIS="RST" SIGNAME="__NOC__"/>
         <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="15" NAME="RstcPPCresetchip_1" SIGIS="RST" SIGNAME="__NOC__"/>
         <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="16" NAME="RstcPPCresetsys_1" SIGIS="RST" SIGNAME="__NOC__"/>
-        <PORT DIR="O" MPD_INDEX="17" NAME="MB_Reset" SIGIS="RST" SIGNAME="__NOC__"/>
-        <PORT DIR="O" MPD_INDEX="18" NAME="Bus_Struct_Reset" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_BUS_RST-1]"/>
-        <PORT DIR="O" MPD_INDEX="19" NAME="Peripheral_Reset" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_RST-1]"/>
-        <PORT DIR="O" MPD_INDEX="20" NAME="Interconnect_aresetn" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_INTERCONNECT_ARESETN-1]"/>
-        <PORT DIR="O" MPD_INDEX="21" NAME="Peripheral_aresetn" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_ARESETN-1]"/>
+        <PORT DIR="O" MPD_INDEX="17" NAME="MB_Reset" SIGIS="RST" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" MPD_INDEX="18" NAME="Bus_Struct_Reset" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_BUS_RST-1]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" MPD_INDEX="19" NAME="Peripheral_Reset" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_RST-1]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" MPD_INDEX="20" NAME="Interconnect_aresetn" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_INTERCONNECT_ARESETN-1]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" MPD_INDEX="21" NAME="Peripheral_aresetn" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_ARESETN-1]">
+          <CONNECTIONS/>
+        </PORT>
       </PORTS>
       <BUSINTERFACES>
         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="0" NAME="RESETPPC0" TYPE="INITIATOR">
@@ -416,6 +296,7 @@
       <IOINTERFACES>
         <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
       </IOINTERFACES>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
     </MODULE>
     <MODULE HWVERSION="4.03.a" INSTANCE="processing_system7_0" IPTYPE="PROCESSOR" MHS_INDEX="2" MODCLASS="PROCESSOR" MODTYPE="processing_system7" PROCTYPE="ARM">
       <DESCRIPTION TYPE="SHORT">Processing System</DESCRIPTION>
@@ -423,7 +304,6 @@
       <DOCUMENTATION>
         <DOCUMENT SOURCE="/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/doc/pg082-processing_system7.pdf" TYPE="IP"/>
       </DOCUMENTATION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
       <PARAMETERS>
         <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_EN_EMIO_CAN0" TYPE="INTEGER" VALUE="0"/>
         <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_EN_EMIO_CAN1" TYPE="INTEGER" VALUE="0"/>
@@ -804,176 +684,510 @@
             <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_UART0_RX_pin"/>
           </CONNECTIONS>
         </PORT>
-        <PORT DIR="O" IOS="CAN_0" IS_VALID="FALSE" MPD_INDEX="0" NAME="CAN0_PHY_TX" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="CAN_0" IS_VALID="FALSE" MPD_INDEX="1" NAME="CAN0_PHY_RX" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="CAN_1" IS_VALID="FALSE" MPD_INDEX="2" NAME="CAN1_PHY_TX" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="CAN_1" IS_VALID="FALSE" MPD_INDEX="3" NAME="CAN1_PHY_RX" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="4" NAME="ENET0_GMII_TX_EN" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="5" NAME="ENET0_GMII_TX_ER" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="6" NAME="ENET0_MDIO_MDC" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="7" NAME="ENET0_MDIO_O" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="8" NAME="ENET0_MDIO_T" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="9" NAME="ENET0_PTP_DELAY_REQ_RX" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="10" NAME="ENET0_PTP_DELAY_REQ_TX" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="11" NAME="ENET0_PTP_PDELAY_REQ_RX" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="12" NAME="ENET0_PTP_PDELAY_REQ_TX" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="13" NAME="ENET0_PTP_PDELAY_RESP_RX" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="14" NAME="ENET0_PTP_PDELAY_RESP_TX" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="15" NAME="ENET0_PTP_SYNC_FRAME_RX" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="16" NAME="ENET0_PTP_SYNC_FRAME_TX" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="17" NAME="ENET0_SOF_RX" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="18" NAME="ENET0_SOF_TX" SIGNAME="__NOC__"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="ETHERNETIF_0" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="19" MSB="7" NAME="ENET0_GMII_TXD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
-        <PORT DIR="I" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="20" NAME="ENET0_GMII_COL" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="21" NAME="ENET0_GMII_CRS" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="22" NAME="ENET0_EXT_INTIN" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="23" NAME="ENET0_GMII_RX_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="24" NAME="ENET0_GMII_RX_DV" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="25" NAME="ENET0_GMII_RX_ER" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="26" NAME="ENET0_GMII_TX_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="27" NAME="ENET0_MDIO_I" SIGNAME="__NOC__"/>
-        <PORT DIR="I" ENDIAN="LITTLE" IOS="ETHERNETIF_0" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="28" MSB="7" NAME="ENET0_GMII_RXD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
-        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="29" NAME="ENET1_GMII_TX_EN" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="30" NAME="ENET1_GMII_TX_ER" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="31" NAME="ENET1_MDIO_MDC" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="32" NAME="ENET1_MDIO_O" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="33" NAME="ENET1_MDIO_T" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="34" NAME="ENET1_PTP_DELAY_REQ_RX" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="35" NAME="ENET1_PTP_DELAY_REQ_TX" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="36" NAME="ENET1_PTP_PDELAY_REQ_RX" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="37" NAME="ENET1_PTP_PDELAY_REQ_TX" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="38" NAME="ENET1_PTP_PDELAY_RESP_RX" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="39" NAME="ENET1_PTP_PDELAY_RESP_TX" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="40" NAME="ENET1_PTP_SYNC_FRAME_RX" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="41" NAME="ENET1_PTP_SYNC_FRAME_TX" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="42" NAME="ENET1_SOF_RX" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="43" NAME="ENET1_SOF_TX" SIGNAME="__NOC__"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="ETHERNETIF_1" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="44" MSB="7" NAME="ENET1_GMII_TXD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
-        <PORT DIR="I" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="45" NAME="ENET1_GMII_COL" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="46" NAME="ENET1_GMII_CRS" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="47" NAME="ENET1_EXT_INTIN" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="48" NAME="ENET1_GMII_RX_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="49" NAME="ENET1_GMII_RX_DV" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="50" NAME="ENET1_GMII_RX_ER" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="51" NAME="ENET1_GMII_TX_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="52" NAME="ENET1_MDIO_I" SIGNAME="__NOC__"/>
-        <PORT DIR="I" ENDIAN="LITTLE" IOS="ETHERNETIF_1" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="53" MSB="7" NAME="ENET1_GMII_RXD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
-        <PORT DIR="I" ENDIAN="LITTLE" IOS="GPIO_0" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="54" MSB="63" NAME="GPIO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_EMIO_GPIO_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="GPIO_0" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="55" MSB="63" NAME="GPIO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_EMIO_GPIO_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="GPIO_0" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="56" MSB="63" NAME="GPIO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_EMIO_GPIO_WIDTH-1):0]"/>
-        <PORT DIR="I" IOS="IIC_0" IS_VALID="FALSE" MPD_INDEX="57" NAME="I2C0_SDA_I" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="IIC_0" IS_VALID="FALSE" MPD_INDEX="58" NAME="I2C0_SDA_O" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="IIC_0" IS_VALID="FALSE" MPD_INDEX="59" NAME="I2C0_SDA_T" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="IIC_0" IS_VALID="FALSE" MPD_INDEX="60" NAME="I2C0_SCL_I" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="IIC_0" IS_VALID="FALSE" MPD_INDEX="61" NAME="I2C0_SCL_O" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="IIC_0" IS_VALID="FALSE" MPD_INDEX="62" NAME="I2C0_SCL_T" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="IIC_1" IS_VALID="FALSE" MPD_INDEX="63" NAME="I2C1_SDA_I" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="IIC_1" IS_VALID="FALSE" MPD_INDEX="64" NAME="I2C1_SDA_O" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="IIC_1" IS_VALID="FALSE" MPD_INDEX="65" NAME="I2C1_SDA_T" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="IIC_1" IS_VALID="FALSE" MPD_INDEX="66" NAME="I2C1_SCL_I" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="IIC_1" IS_VALID="FALSE" MPD_INDEX="67" NAME="I2C1_SCL_O" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="IIC_1" IS_VALID="FALSE" MPD_INDEX="68" NAME="I2C1_SCL_T" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="PJTAG" IS_VALID="FALSE" MPD_INDEX="69" NAME="PJTAG_TCK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="PJTAG" IS_VALID="FALSE" MPD_INDEX="70" NAME="PJTAG_TMS" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="PJTAG" IS_VALID="FALSE" MPD_INDEX="71" NAME="PJTAG_TD_I" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="PJTAG" IS_VALID="FALSE" MPD_INDEX="72" NAME="PJTAG_TD_T" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="PJTAG" IS_VALID="FALSE" MPD_INDEX="73" NAME="PJTAG_TD_O" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="SDIO_0" IS_VALID="FALSE" MPD_INDEX="74" NAME="SDIO0_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="SDIO_0" IS_VALID="FALSE" MPD_INDEX="75" NAME="SDIO0_CLK_FB" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="SDIO_0" IS_VALID="FALSE" MPD_INDEX="76" NAME="SDIO0_CMD_O" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="SDIO_0" IS_VALID="FALSE" MPD_INDEX="77" NAME="SDIO0_CMD_I" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="SDIO_0" IS_VALID="FALSE" MPD_INDEX="78" NAME="SDIO0_CMD_T" SIGNAME="__NOC__"/>
-        <PORT DIR="I" ENDIAN="LITTLE" IOS="SDIO_0" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="79" MSB="3" NAME="SDIO0_DATA_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="SDIO_0" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="80" MSB="3" NAME="SDIO0_DATA_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="SDIO_0" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="81" MSB="3" NAME="SDIO0_DATA_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
-        <PORT DIR="O" IOS="SDIO_0" IS_VALID="FALSE" MPD_INDEX="82" NAME="SDIO0_LED" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="SDIO_0" IS_VALID="FALSE" MPD_INDEX="83" NAME="SDIO0_CDN" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="SDIO_0" MPD_INDEX="84" NAME="SDIO0_WP" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="SDIO_0" IS_VALID="FALSE" MPD_INDEX="85" NAME="SDIO0_BUSPOW" SIGNAME="__NOC__"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="SDIO_0" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="86" MSB="2" NAME="SDIO0_BUSVOLT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
-        <PORT DIR="O" IOS="SDIO_1" IS_VALID="FALSE" MPD_INDEX="87" NAME="SDIO1_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="SDIO_1" IS_VALID="FALSE" MPD_INDEX="88" NAME="SDIO1_CLK_FB" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="SDIO_1" IS_VALID="FALSE" MPD_INDEX="89" NAME="SDIO1_CMD_O" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="SDIO_1" IS_VALID="FALSE" MPD_INDEX="90" NAME="SDIO1_CMD_I" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="SDIO_1" IS_VALID="FALSE" MPD_INDEX="91" NAME="SDIO1_CMD_T" SIGNAME="__NOC__"/>
-        <PORT DIR="I" ENDIAN="LITTLE" IOS="SDIO_1" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="92" MSB="3" NAME="SDIO1_DATA_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="SDIO_1" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="93" MSB="3" NAME="SDIO1_DATA_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="SDIO_1" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="94" MSB="3" NAME="SDIO1_DATA_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
-        <PORT DIR="O" IOS="SDIO_1" IS_VALID="FALSE" MPD_INDEX="95" NAME="SDIO1_LED" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="SDIO_1" IS_VALID="FALSE" MPD_INDEX="96" NAME="SDIO1_CDN" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="SDIO_1" IS_VALID="FALSE" MPD_INDEX="97" NAME="SDIO1_WP" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="SDIO_1" IS_VALID="FALSE" MPD_INDEX="98" NAME="SDIO1_BUSPOW" SIGNAME="__NOC__"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="SDIO_1" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="99" MSB="2" NAME="SDIO1_BUSVOLT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
-        <PORT DIR="I" IOS="SPI_0" IS_VALID="FALSE" MPD_INDEX="100" NAME="SPI0_SCLK_I" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="SPI_0" IS_VALID="FALSE" MPD_INDEX="101" NAME="SPI0_SCLK_O" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="SPI_0" IS_VALID="FALSE" MPD_INDEX="102" NAME="SPI0_SCLK_T" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="SPI_0" IS_VALID="FALSE" MPD_INDEX="103" NAME="SPI0_MOSI_I" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="SPI_0" IS_VALID="FALSE" MPD_INDEX="104" NAME="SPI0_MOSI_O" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="SPI_0" IS_VALID="FALSE" MPD_INDEX="105" NAME="SPI0_MOSI_T" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="SPI_0" IS_VALID="FALSE" MPD_INDEX="106" NAME="SPI0_MISO_I" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="SPI_0" IS_VALID="FALSE" MPD_INDEX="107" NAME="SPI0_MISO_O" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="SPI_0" IS_VALID="FALSE" MPD_INDEX="108" NAME="SPI0_MISO_T" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="SPI_0" IS_VALID="FALSE" MPD_INDEX="109" NAME="SPI0_SS_I" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="SPI_0" IS_VALID="FALSE" MPD_INDEX="110" NAME="SPI0_SS_O" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="SPI_0" IS_VALID="FALSE" MPD_INDEX="111" NAME="SPI0_SS1_O" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="SPI_0" IS_VALID="FALSE" MPD_INDEX="112" NAME="SPI0_SS2_O" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="SPI_0" IS_VALID="FALSE" MPD_INDEX="113" NAME="SPI0_SS_T" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="SPI_1" IS_VALID="FALSE" MPD_INDEX="114" NAME="SPI1_SCLK_I" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="SPI_1" IS_VALID="FALSE" MPD_INDEX="115" NAME="SPI1_SCLK_O" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="SPI_1" IS_VALID="FALSE" MPD_INDEX="116" NAME="SPI1_SCLK_T" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="SPI_1" IS_VALID="FALSE" MPD_INDEX="117" NAME="SPI1_MOSI_I" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="SPI_1" IS_VALID="FALSE" MPD_INDEX="118" NAME="SPI1_MOSI_O" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="SPI_1" IS_VALID="FALSE" MPD_INDEX="119" NAME="SPI1_MOSI_T" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="SPI_1" IS_VALID="FALSE" MPD_INDEX="120" NAME="SPI1_MISO_I" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="SPI_1" IS_VALID="FALSE" MPD_INDEX="121" NAME="SPI1_MISO_O" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="SPI_1" IS_VALID="FALSE" MPD_INDEX="122" NAME="SPI1_MISO_T" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="SPI_1" IS_VALID="FALSE" MPD_INDEX="123" NAME="SPI1_SS_I" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="SPI_1" IS_VALID="FALSE" MPD_INDEX="124" NAME="SPI1_SS_O" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="SPI_1" IS_VALID="FALSE" MPD_INDEX="125" NAME="SPI1_SS1_O" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="SPI_1" IS_VALID="FALSE" MPD_INDEX="126" NAME="SPI1_SS2_O" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="SPI_1" IS_VALID="FALSE" MPD_INDEX="127" NAME="SPI1_SS_T" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="UART_0" IS_VALID="FALSE" MPD_INDEX="128" NAME="UART0_DTRN" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="UART_0" IS_VALID="FALSE" MPD_INDEX="129" NAME="UART0_RTSN" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="UART_0" IS_VALID="FALSE" MPD_INDEX="131" NAME="UART0_CTSN" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="UART_0" IS_VALID="FALSE" MPD_INDEX="132" NAME="UART0_DCDN" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="UART_0" IS_VALID="FALSE" MPD_INDEX="133" NAME="UART0_DSRN" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="UART_0" IS_VALID="FALSE" MPD_INDEX="134" NAME="UART0_RIN" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="UART_1" IS_VALID="FALSE" MPD_INDEX="136" NAME="UART1_DTRN" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="UART_1" IS_VALID="FALSE" MPD_INDEX="137" NAME="UART1_RTSN" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="UART_1" IS_VALID="FALSE" MPD_INDEX="138" NAME="UART1_TX" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="UART_1" IS_VALID="FALSE" MPD_INDEX="139" NAME="UART1_CTSN" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="UART_1" IS_VALID="FALSE" MPD_INDEX="140" NAME="UART1_DCDN" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="UART_1" IS_VALID="FALSE" MPD_INDEX="141" NAME="UART1_DSRN" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="UART_1" IS_VALID="FALSE" MPD_INDEX="142" NAME="UART1_RIN" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="UART_1" IS_VALID="FALSE" MPD_INDEX="143" NAME="UART1_RX" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="TTC_0" IS_VALID="FALSE" MPD_INDEX="144" NAME="TTC0_WAVE0_OUT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="TTC_0" IS_VALID="FALSE" MPD_INDEX="145" NAME="TTC0_WAVE1_OUT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="TTC_0" IS_VALID="FALSE" MPD_INDEX="146" NAME="TTC0_WAVE2_OUT" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="TTC_0" IS_VALID="FALSE" MPD_INDEX="147" NAME="TTC0_CLK0_IN" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="TTC_0" IS_VALID="FALSE" MPD_INDEX="148" NAME="TTC0_CLK1_IN" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="TTC_0" IS_VALID="FALSE" MPD_INDEX="149" NAME="TTC0_CLK2_IN" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="TTC_1" IS_VALID="FALSE" MPD_INDEX="150" NAME="TTC1_WAVE0_OUT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="TTC_1" IS_VALID="FALSE" MPD_INDEX="151" NAME="TTC1_WAVE1_OUT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="TTC_1" IS_VALID="FALSE" MPD_INDEX="152" NAME="TTC1_WAVE2_OUT" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="TTC_1" IS_VALID="FALSE" MPD_INDEX="153" NAME="TTC1_CLK0_IN" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="TTC_1" IS_VALID="FALSE" MPD_INDEX="154" NAME="TTC1_CLK1_IN" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="TTC_1" IS_VALID="FALSE" MPD_INDEX="155" NAME="TTC1_CLK2_IN" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="WDT_0" IS_VALID="FALSE" MPD_INDEX="156" NAME="WDT_CLK_IN" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="WDT_0" IS_VALID="FALSE" MPD_INDEX="157" NAME="WDT_RST_OUT" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="TRACE_0" IS_VALID="FALSE" MPD_INDEX="158" NAME="TRACE_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="TRACE_0" IS_VALID="FALSE" MPD_INDEX="159" NAME="TRACE_CTL" SIGNAME="__NOC__"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="TRACE_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="160" MSB="31" NAME="TRACE_DATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31:0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="USBIND_0" LEFT="1" LSB="0" MPD_INDEX="161" MSB="1" NAME="USB0_PORT_INDCTL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="USBIND_1" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="162" MSB="1" NAME="USB1_PORT_INDCTL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
-        <PORT DIR="O" IOS="USBIND_0" MPD_INDEX="163" NAME="USB0_VBUS_PWRSELECT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="USBIND_1" IS_VALID="FALSE" MPD_INDEX="164" NAME="USB1_VBUS_PWRSELECT" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="USBIND_0" MPD_INDEX="165" NAME="USB0_VBUS_PWRFAULT" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="USBIND_1" IS_VALID="FALSE" MPD_INDEX="166" NAME="USB1_VBUS_PWRFAULT" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="167" NAME="SRAM_INTIN" SIGNAME="__NOC__"/>
-        <PORT DIR="O" MPD_INDEX="168" NAME="M_AXI_GP0_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_ARVALID" DIR="O" MPD_INDEX="169" NAME="M_AXI_GP0_ARVALID" SIGNAME="axi_interconnect_1_S_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_ARVALID"/>
+        <PORT DIR="O" IOS="CAN_0" IS_VALID="FALSE" MPD_INDEX="0" NAME="CAN0_PHY_TX" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="CAN_0" IS_VALID="FALSE" MPD_INDEX="1" NAME="CAN0_PHY_RX" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="CAN_1" IS_VALID="FALSE" MPD_INDEX="2" NAME="CAN1_PHY_TX" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="CAN_1" IS_VALID="FALSE" MPD_INDEX="3" NAME="CAN1_PHY_RX" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="4" NAME="ENET0_GMII_TX_EN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="5" NAME="ENET0_GMII_TX_ER" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="6" NAME="ENET0_MDIO_MDC" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="7" NAME="ENET0_MDIO_O" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="8" NAME="ENET0_MDIO_T" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="9" NAME="ENET0_PTP_DELAY_REQ_RX" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="10" NAME="ENET0_PTP_DELAY_REQ_TX" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="11" NAME="ENET0_PTP_PDELAY_REQ_RX" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="12" NAME="ENET0_PTP_PDELAY_REQ_TX" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="13" NAME="ENET0_PTP_PDELAY_RESP_RX" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="14" NAME="ENET0_PTP_PDELAY_RESP_TX" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="15" NAME="ENET0_PTP_SYNC_FRAME_RX" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="16" NAME="ENET0_PTP_SYNC_FRAME_TX" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="17" NAME="ENET0_SOF_RX" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="18" NAME="ENET0_SOF_TX" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="ETHERNETIF_0" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="19" MSB="7" NAME="ENET0_GMII_TXD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="20" NAME="ENET0_GMII_COL" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="21" NAME="ENET0_GMII_CRS" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="22" NAME="ENET0_EXT_INTIN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="23" NAME="ENET0_GMII_RX_CLK" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="24" NAME="ENET0_GMII_RX_DV" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="25" NAME="ENET0_GMII_RX_ER" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="26" NAME="ENET0_GMII_TX_CLK" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="27" NAME="ENET0_MDIO_I" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" ENDIAN="LITTLE" IOS="ETHERNETIF_0" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="28" MSB="7" NAME="ENET0_GMII_RXD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="29" NAME="ENET1_GMII_TX_EN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="30" NAME="ENET1_GMII_TX_ER" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="31" NAME="ENET1_MDIO_MDC" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="32" NAME="ENET1_MDIO_O" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="33" NAME="ENET1_MDIO_T" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="34" NAME="ENET1_PTP_DELAY_REQ_RX" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="35" NAME="ENET1_PTP_DELAY_REQ_TX" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="36" NAME="ENET1_PTP_PDELAY_REQ_RX" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="37" NAME="ENET1_PTP_PDELAY_REQ_TX" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="38" NAME="ENET1_PTP_PDELAY_RESP_RX" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="39" NAME="ENET1_PTP_PDELAY_RESP_TX" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="40" NAME="ENET1_PTP_SYNC_FRAME_RX" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="41" NAME="ENET1_PTP_SYNC_FRAME_TX" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="42" NAME="ENET1_SOF_RX" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="43" NAME="ENET1_SOF_TX" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="ETHERNETIF_1" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="44" MSB="7" NAME="ENET1_GMII_TXD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="45" NAME="ENET1_GMII_COL" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="46" NAME="ENET1_GMII_CRS" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="47" NAME="ENET1_EXT_INTIN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="48" NAME="ENET1_GMII_RX_CLK" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="49" NAME="ENET1_GMII_RX_DV" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="50" NAME="ENET1_GMII_RX_ER" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="51" NAME="ENET1_GMII_TX_CLK" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="52" NAME="ENET1_MDIO_I" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" ENDIAN="LITTLE" IOS="ETHERNETIF_1" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="53" MSB="7" NAME="ENET1_GMII_RXD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" ENDIAN="LITTLE" IOS="GPIO_0" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="54" MSB="63" NAME="GPIO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_EMIO_GPIO_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="GPIO_0" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="55" MSB="63" NAME="GPIO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_EMIO_GPIO_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="GPIO_0" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="56" MSB="63" NAME="GPIO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_EMIO_GPIO_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="IIC_0" IS_VALID="FALSE" MPD_INDEX="57" NAME="I2C0_SDA_I" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="IIC_0" IS_VALID="FALSE" MPD_INDEX="58" NAME="I2C0_SDA_O" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="IIC_0" IS_VALID="FALSE" MPD_INDEX="59" NAME="I2C0_SDA_T" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="IIC_0" IS_VALID="FALSE" MPD_INDEX="60" NAME="I2C0_SCL_I" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="IIC_0" IS_VALID="FALSE" MPD_INDEX="61" NAME="I2C0_SCL_O" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="IIC_0" IS_VALID="FALSE" MPD_INDEX="62" NAME="I2C0_SCL_T" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="IIC_1" IS_VALID="FALSE" MPD_INDEX="63" NAME="I2C1_SDA_I" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="IIC_1" IS_VALID="FALSE" MPD_INDEX="64" NAME="I2C1_SDA_O" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="IIC_1" IS_VALID="FALSE" MPD_INDEX="65" NAME="I2C1_SDA_T" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="IIC_1" IS_VALID="FALSE" MPD_INDEX="66" NAME="I2C1_SCL_I" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="IIC_1" IS_VALID="FALSE" MPD_INDEX="67" NAME="I2C1_SCL_O" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="IIC_1" IS_VALID="FALSE" MPD_INDEX="68" NAME="I2C1_SCL_T" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="PJTAG" IS_VALID="FALSE" MPD_INDEX="69" NAME="PJTAG_TCK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="PJTAG" IS_VALID="FALSE" MPD_INDEX="70" NAME="PJTAG_TMS" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="PJTAG" IS_VALID="FALSE" MPD_INDEX="71" NAME="PJTAG_TD_I" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="PJTAG" IS_VALID="FALSE" MPD_INDEX="72" NAME="PJTAG_TD_T" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="PJTAG" IS_VALID="FALSE" MPD_INDEX="73" NAME="PJTAG_TD_O" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SDIO_0" IS_VALID="FALSE" MPD_INDEX="74" NAME="SDIO0_CLK" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="SDIO_0" IS_VALID="FALSE" MPD_INDEX="75" NAME="SDIO0_CLK_FB" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SDIO_0" IS_VALID="FALSE" MPD_INDEX="76" NAME="SDIO0_CMD_O" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="SDIO_0" IS_VALID="FALSE" MPD_INDEX="77" NAME="SDIO0_CMD_I" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SDIO_0" IS_VALID="FALSE" MPD_INDEX="78" NAME="SDIO0_CMD_T" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" ENDIAN="LITTLE" IOS="SDIO_0" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="79" MSB="3" NAME="SDIO0_DATA_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="SDIO_0" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="80" MSB="3" NAME="SDIO0_DATA_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="SDIO_0" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="81" MSB="3" NAME="SDIO0_DATA_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SDIO_0" IS_VALID="FALSE" MPD_INDEX="82" NAME="SDIO0_LED" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="SDIO_0" IS_VALID="FALSE" MPD_INDEX="83" NAME="SDIO0_CDN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="SDIO_0" MPD_INDEX="84" NAME="SDIO0_WP" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SDIO_0" IS_VALID="FALSE" MPD_INDEX="85" NAME="SDIO0_BUSPOW" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="SDIO_0" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="86" MSB="2" NAME="SDIO0_BUSVOLT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SDIO_1" IS_VALID="FALSE" MPD_INDEX="87" NAME="SDIO1_CLK" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="SDIO_1" IS_VALID="FALSE" MPD_INDEX="88" NAME="SDIO1_CLK_FB" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SDIO_1" IS_VALID="FALSE" MPD_INDEX="89" NAME="SDIO1_CMD_O" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="SDIO_1" IS_VALID="FALSE" MPD_INDEX="90" NAME="SDIO1_CMD_I" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SDIO_1" IS_VALID="FALSE" MPD_INDEX="91" NAME="SDIO1_CMD_T" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" ENDIAN="LITTLE" IOS="SDIO_1" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="92" MSB="3" NAME="SDIO1_DATA_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="SDIO_1" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="93" MSB="3" NAME="SDIO1_DATA_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="SDIO_1" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="94" MSB="3" NAME="SDIO1_DATA_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SDIO_1" IS_VALID="FALSE" MPD_INDEX="95" NAME="SDIO1_LED" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="SDIO_1" IS_VALID="FALSE" MPD_INDEX="96" NAME="SDIO1_CDN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="SDIO_1" IS_VALID="FALSE" MPD_INDEX="97" NAME="SDIO1_WP" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SDIO_1" IS_VALID="FALSE" MPD_INDEX="98" NAME="SDIO1_BUSPOW" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="SDIO_1" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="99" MSB="2" NAME="SDIO1_BUSVOLT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="SPI_0" IS_VALID="FALSE" MPD_INDEX="100" NAME="SPI0_SCLK_I" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SPI_0" IS_VALID="FALSE" MPD_INDEX="101" NAME="SPI0_SCLK_O" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SPI_0" IS_VALID="FALSE" MPD_INDEX="102" NAME="SPI0_SCLK_T" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="SPI_0" IS_VALID="FALSE" MPD_INDEX="103" NAME="SPI0_MOSI_I" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SPI_0" IS_VALID="FALSE" MPD_INDEX="104" NAME="SPI0_MOSI_O" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SPI_0" IS_VALID="FALSE" MPD_INDEX="105" NAME="SPI0_MOSI_T" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="SPI_0" IS_VALID="FALSE" MPD_INDEX="106" NAME="SPI0_MISO_I" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SPI_0" IS_VALID="FALSE" MPD_INDEX="107" NAME="SPI0_MISO_O" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SPI_0" IS_VALID="FALSE" MPD_INDEX="108" NAME="SPI0_MISO_T" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="SPI_0" IS_VALID="FALSE" MPD_INDEX="109" NAME="SPI0_SS_I" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SPI_0" IS_VALID="FALSE" MPD_INDEX="110" NAME="SPI0_SS_O" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SPI_0" IS_VALID="FALSE" MPD_INDEX="111" NAME="SPI0_SS1_O" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SPI_0" IS_VALID="FALSE" MPD_INDEX="112" NAME="SPI0_SS2_O" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SPI_0" IS_VALID="FALSE" MPD_INDEX="113" NAME="SPI0_SS_T" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="SPI_1" IS_VALID="FALSE" MPD_INDEX="114" NAME="SPI1_SCLK_I" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SPI_1" IS_VALID="FALSE" MPD_INDEX="115" NAME="SPI1_SCLK_O" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SPI_1" IS_VALID="FALSE" MPD_INDEX="116" NAME="SPI1_SCLK_T" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="SPI_1" IS_VALID="FALSE" MPD_INDEX="117" NAME="SPI1_MOSI_I" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SPI_1" IS_VALID="FALSE" MPD_INDEX="118" NAME="SPI1_MOSI_O" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SPI_1" IS_VALID="FALSE" MPD_INDEX="119" NAME="SPI1_MOSI_T" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="SPI_1" IS_VALID="FALSE" MPD_INDEX="120" NAME="SPI1_MISO_I" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SPI_1" IS_VALID="FALSE" MPD_INDEX="121" NAME="SPI1_MISO_O" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SPI_1" IS_VALID="FALSE" MPD_INDEX="122" NAME="SPI1_MISO_T" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="SPI_1" IS_VALID="FALSE" MPD_INDEX="123" NAME="SPI1_SS_I" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SPI_1" IS_VALID="FALSE" MPD_INDEX="124" NAME="SPI1_SS_O" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SPI_1" IS_VALID="FALSE" MPD_INDEX="125" NAME="SPI1_SS1_O" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SPI_1" IS_VALID="FALSE" MPD_INDEX="126" NAME="SPI1_SS2_O" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="SPI_1" IS_VALID="FALSE" MPD_INDEX="127" NAME="SPI1_SS_T" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="UART_0" IS_VALID="FALSE" MPD_INDEX="128" NAME="UART0_DTRN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="UART_0" IS_VALID="FALSE" MPD_INDEX="129" NAME="UART0_RTSN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="UART_0" IS_VALID="FALSE" MPD_INDEX="131" NAME="UART0_CTSN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="UART_0" IS_VALID="FALSE" MPD_INDEX="132" NAME="UART0_DCDN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="UART_0" IS_VALID="FALSE" MPD_INDEX="133" NAME="UART0_DSRN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="UART_0" IS_VALID="FALSE" MPD_INDEX="134" NAME="UART0_RIN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="UART_1" IS_VALID="FALSE" MPD_INDEX="136" NAME="UART1_DTRN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="UART_1" IS_VALID="FALSE" MPD_INDEX="137" NAME="UART1_RTSN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="UART_1" IS_VALID="FALSE" MPD_INDEX="138" NAME="UART1_TX" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="UART_1" IS_VALID="FALSE" MPD_INDEX="139" NAME="UART1_CTSN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="UART_1" IS_VALID="FALSE" MPD_INDEX="140" NAME="UART1_DCDN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="UART_1" IS_VALID="FALSE" MPD_INDEX="141" NAME="UART1_DSRN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="UART_1" IS_VALID="FALSE" MPD_INDEX="142" NAME="UART1_RIN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="UART_1" IS_VALID="FALSE" MPD_INDEX="143" NAME="UART1_RX" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="TTC_0" IS_VALID="FALSE" MPD_INDEX="144" NAME="TTC0_WAVE0_OUT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="TTC_0" IS_VALID="FALSE" MPD_INDEX="145" NAME="TTC0_WAVE1_OUT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="TTC_0" IS_VALID="FALSE" MPD_INDEX="146" NAME="TTC0_WAVE2_OUT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="TTC_0" IS_VALID="FALSE" MPD_INDEX="147" NAME="TTC0_CLK0_IN" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="TTC_0" IS_VALID="FALSE" MPD_INDEX="148" NAME="TTC0_CLK1_IN" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="TTC_0" IS_VALID="FALSE" MPD_INDEX="149" NAME="TTC0_CLK2_IN" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="TTC_1" IS_VALID="FALSE" MPD_INDEX="150" NAME="TTC1_WAVE0_OUT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="TTC_1" IS_VALID="FALSE" MPD_INDEX="151" NAME="TTC1_WAVE1_OUT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="TTC_1" IS_VALID="FALSE" MPD_INDEX="152" NAME="TTC1_WAVE2_OUT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="TTC_1" IS_VALID="FALSE" MPD_INDEX="153" NAME="TTC1_CLK0_IN" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="TTC_1" IS_VALID="FALSE" MPD_INDEX="154" NAME="TTC1_CLK1_IN" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="TTC_1" IS_VALID="FALSE" MPD_INDEX="155" NAME="TTC1_CLK2_IN" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="WDT_0" IS_VALID="FALSE" MPD_INDEX="156" NAME="WDT_CLK_IN" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="WDT_0" IS_VALID="FALSE" MPD_INDEX="157" NAME="WDT_RST_OUT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="TRACE_0" IS_VALID="FALSE" MPD_INDEX="158" NAME="TRACE_CLK" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="TRACE_0" IS_VALID="FALSE" MPD_INDEX="159" NAME="TRACE_CTL" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="TRACE_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="160" MSB="31" NAME="TRACE_DATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="USBIND_0" LEFT="1" LSB="0" MPD_INDEX="161" MSB="1" NAME="USB0_PORT_INDCTL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="USBIND_1" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="162" MSB="1" NAME="USB1_PORT_INDCTL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="USBIND_0" MPD_INDEX="163" NAME="USB0_VBUS_PWRSELECT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="USBIND_1" IS_VALID="FALSE" MPD_INDEX="164" NAME="USB1_VBUS_PWRSELECT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="USBIND_0" MPD_INDEX="165" NAME="USB0_VBUS_PWRFAULT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="USBIND_1" IS_VALID="FALSE" MPD_INDEX="166" NAME="USB1_VBUS_PWRFAULT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="167" NAME="SRAM_INTIN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" MPD_INDEX="168" NAME="M_AXI_GP0_ARESETN" SIGIS="RST" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_ARVALID" DIR="O" MPD_INDEX="169" NAME="M_AXI_GP0_ARVALID" SIGNAME="axi_interconnect_1_S_ARVALID">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_ARVALID"/>
           </CONNECTIONS>
         </PORT>
         <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_AWVALID" DIR="O" MPD_INDEX="170" NAME="M_AXI_GP0_AWVALID" SIGNAME="axi_interconnect_1_S_AWVALID">
@@ -1161,7 +1375,9 @@
             <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_RDATA"/>
           </CONNECTIONS>
         </PORT>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="208" NAME="M_AXI_GP1_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="208" NAME="M_AXI_GP1_ARESETN" SIGIS="RST" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
         <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="209" NAME="M_AXI_GP1_ARVALID" SIGNAME="__NOC__"/>
         <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="210" NAME="M_AXI_GP1_AWVALID" SIGNAME="__NOC__"/>
         <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="211" NAME="M_AXI_GP1_BREADY" SIGNAME="__NOC__"/>
@@ -1201,7 +1417,9 @@
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         <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="246" MSB="1" NAME="M_AXI_GP1_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
         <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="247" MSB="31" NAME="M_AXI_GP1_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31:0]"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="248" NAME="S_AXI_GP0_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="248" NAME="S_AXI_GP0_ARESETN" SIGIS="RST" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
         <PORT BUS="S_AXI_GP0" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="249" NAME="S_AXI_GP0_ARREADY" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_GP0" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="250" NAME="S_AXI_GP0_AWREADY" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_GP0" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="251" NAME="S_AXI_GP0_BVALID" SIGNAME="__NOC__"/>
@@ -1241,7 +1459,9 @@
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         <PORT BUS="S_AXI_GP0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="286" MSB="5" NAME="S_AXI_GP0_AWID" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_GP0_ID_WIDTH - 1) : 0]"/>
         <PORT BUS="S_AXI_GP0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="287" MSB="5" NAME="S_AXI_GP0_WID" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_GP0_ID_WIDTH - 1) : 0]"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="288" NAME="S_AXI_GP1_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="288" NAME="S_AXI_GP1_ARESETN" SIGIS="RST" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
         <PORT BUS="S_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="289" NAME="S_AXI_GP1_ARREADY" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="290" NAME="S_AXI_GP1_AWREADY" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="291" NAME="S_AXI_GP1_BVALID" SIGNAME="__NOC__"/>
@@ -1281,7 +1501,9 @@
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         <PORT BUS="S_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="326" MSB="5" NAME="S_AXI_GP1_AWID" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_GP1_ID_WIDTH - 1) : 0]"/>
         <PORT BUS="S_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="327" MSB="5" NAME="S_AXI_GP1_WID" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_GP1_ID_WIDTH - 1) : 0]"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="328" NAME="S_AXI_ACP_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="328" NAME="S_AXI_ACP_ARESETN" SIGIS="RST" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
         <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="329" NAME="S_AXI_ACP_AWREADY" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="330" NAME="S_AXI_ACP_ARREADY" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="331" NAME="S_AXI_ACP_BVALID" SIGNAME="__NOC__"/>
@@ -1323,7 +1545,9 @@
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         <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="368" MSB="63" NAME="S_AXI_ACP_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[63:0]"/>
         <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="369" MSB="7" NAME="S_AXI_ACP_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="370" NAME="S_AXI_HP0_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="370" NAME="S_AXI_HP0_ARESETN" SIGIS="RST" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
         <PORT BUS="S_AXI_HP0" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="371" NAME="S_AXI_HP0_ARREADY" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_HP0" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="372" NAME="S_AXI_HP0_AWREADY" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_HP0" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="373" NAME="S_AXI_HP0_BVALID" SIGNAME="__NOC__"/>
@@ -1335,18 +1559,30 @@
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         <PORT BUS="S_AXI_HP0" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="380" MSB="5" NAME="S_AXI_HP0_RID" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_HP0_ID_WIDTH - 1) : 0]"/>
         <PORT BUS="S_AXI_HP0" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="381" MSB="63" NAME="S_AXI_HP0_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_HP0_DATA_WIDTH - 1) :0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP0_FIFO_CTRL" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="382" MSB="7" NAME="S_AXI_HP0_RCOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP0_FIFO_CTRL" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="383" MSB="7" NAME="S_AXI_HP0_WCOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP0_FIFO_CTRL" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="384" MSB="2" NAME="S_AXI_HP0_RACOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP0_FIFO_CTRL" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="385" MSB="5" NAME="S_AXI_HP0_WACOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[5:0]"/>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP0_FIFO_CTRL" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="382" MSB="7" NAME="S_AXI_HP0_RCOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP0_FIFO_CTRL" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="383" MSB="7" NAME="S_AXI_HP0_WCOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP0_FIFO_CTRL" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="384" MSB="2" NAME="S_AXI_HP0_RACOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP0_FIFO_CTRL" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="385" MSB="5" NAME="S_AXI_HP0_WACOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[5:0]">
+          <CONNECTIONS/>
+        </PORT>
         <PORT BUS="S_AXI_HP0" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="386" NAME="S_AXI_HP0_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_HP0" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="387" NAME="S_AXI_HP0_ARVALID" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_HP0" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="388" NAME="S_AXI_HP0_AWVALID" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_HP0" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="389" NAME="S_AXI_HP0_BREADY" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="S_AXI_HP0_FIFO_CTRL" IS_VALID="FALSE" MPD_INDEX="390" NAME="S_AXI_HP0_RDISSUECAP1_EN" SIGNAME="__NOC__"/>
+        <PORT DIR="I" IOS="S_AXI_HP0_FIFO_CTRL" IS_VALID="FALSE" MPD_INDEX="390" NAME="S_AXI_HP0_RDISSUECAP1_EN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
         <PORT BUS="S_AXI_HP0" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="391" NAME="S_AXI_HP0_RREADY" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_HP0" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="392" NAME="S_AXI_HP0_WLAST" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="S_AXI_HP0_FIFO_CTRL" IS_VALID="FALSE" MPD_INDEX="393" NAME="S_AXI_HP0_WRISSUECAP1_EN" SIGNAME="__NOC__"/>
+        <PORT DIR="I" IOS="S_AXI_HP0_FIFO_CTRL" IS_VALID="FALSE" MPD_INDEX="393" NAME="S_AXI_HP0_WRISSUECAP1_EN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
         <PORT BUS="S_AXI_HP0" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="394" NAME="S_AXI_HP0_WVALID" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_HP0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="395" MSB="1" NAME="S_AXI_HP0_ARBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
         <PORT BUS="S_AXI_HP0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="396" MSB="1" NAME="S_AXI_HP0_ARLOCK" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
@@ -1369,7 +1605,9 @@
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         <PORT BUS="S_AXI_HP0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="415" MSB="7" NAME="S_AXI_HP0_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S_AXI_HP0_DATA_WIDTH/8)-1):0]"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="416" NAME="S_AXI_HP1_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="416" NAME="S_AXI_HP1_ARESETN" SIGIS="RST" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
         <PORT BUS="S_AXI_HP1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="417" NAME="S_AXI_HP1_ARREADY" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_HP1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="418" NAME="S_AXI_HP1_AWREADY" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_HP1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="419" NAME="S_AXI_HP1_BVALID" SIGNAME="__NOC__"/>
@@ -1381,18 +1619,30 @@
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         <PORT BUS="S_AXI_HP1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="426" MSB="5" NAME="S_AXI_HP1_RID" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_HP1_ID_WIDTH - 1) : 0]"/>
         <PORT BUS="S_AXI_HP1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="427" MSB="63" NAME="S_AXI_HP1_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_HP1_DATA_WIDTH - 1) :0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP1_FIFO_CTRL" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="428" MSB="7" NAME="S_AXI_HP1_RCOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP1_FIFO_CTRL" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="429" MSB="7" NAME="S_AXI_HP1_WCOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP1_FIFO_CTRL" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="430" MSB="2" NAME="S_AXI_HP1_RACOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP1_FIFO_CTRL" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="431" MSB="5" NAME="S_AXI_HP1_WACOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[5:0]"/>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP1_FIFO_CTRL" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="428" MSB="7" NAME="S_AXI_HP1_RCOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP1_FIFO_CTRL" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="429" MSB="7" NAME="S_AXI_HP1_WCOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP1_FIFO_CTRL" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="430" MSB="2" NAME="S_AXI_HP1_RACOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP1_FIFO_CTRL" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="431" MSB="5" NAME="S_AXI_HP1_WACOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[5:0]">
+          <CONNECTIONS/>
+        </PORT>
         <PORT BUS="S_AXI_HP1" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="432" NAME="S_AXI_HP1_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_HP1" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="433" NAME="S_AXI_HP1_ARVALID" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_HP1" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="434" NAME="S_AXI_HP1_AWVALID" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_HP1" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="435" NAME="S_AXI_HP1_BREADY" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="S_AXI_HP1_FIFO_CTRL" IS_VALID="FALSE" MPD_INDEX="436" NAME="S_AXI_HP1_RDISSUECAP1_EN" SIGNAME="__NOC__"/>
+        <PORT DIR="I" IOS="S_AXI_HP1_FIFO_CTRL" IS_VALID="FALSE" MPD_INDEX="436" NAME="S_AXI_HP1_RDISSUECAP1_EN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
         <PORT BUS="S_AXI_HP1" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="437" NAME="S_AXI_HP1_RREADY" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_HP1" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="438" NAME="S_AXI_HP1_WLAST" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="S_AXI_HP1_FIFO_CTRL" IS_VALID="FALSE" MPD_INDEX="439" NAME="S_AXI_HP1_WRISSUECAP1_EN" SIGNAME="__NOC__"/>
+        <PORT DIR="I" IOS="S_AXI_HP1_FIFO_CTRL" IS_VALID="FALSE" MPD_INDEX="439" NAME="S_AXI_HP1_WRISSUECAP1_EN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
         <PORT BUS="S_AXI_HP1" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="440" NAME="S_AXI_HP1_WVALID" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_HP1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="441" MSB="1" NAME="S_AXI_HP1_ARBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
         <PORT BUS="S_AXI_HP1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="442" MSB="1" NAME="S_AXI_HP1_ARLOCK" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
@@ -1415,7 +1665,9 @@
         <PORT BUS="S_AXI_HP1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="459" MSB="5" NAME="S_AXI_HP1_WID" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_HP1_ID_WIDTH - 1) : 0]"/>
         <PORT BUS="S_AXI_HP1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="460" MSB="63" NAME="S_AXI_HP1_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_HP1_DATA_WIDTH - 1) :0]"/>
         <PORT BUS="S_AXI_HP1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="461" MSB="7" NAME="S_AXI_HP1_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S_AXI_HP1_DATA_WIDTH/8)-1):0]"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="462" NAME="S_AXI_HP2_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="462" NAME="S_AXI_HP2_ARESETN" SIGIS="RST" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
         <PORT BUS="S_AXI_HP2" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="463" NAME="S_AXI_HP2_ARREADY" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_HP2" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="464" NAME="S_AXI_HP2_AWREADY" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_HP2" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="465" NAME="S_AXI_HP2_BVALID" SIGNAME="__NOC__"/>
@@ -1427,18 +1679,30 @@
         <PORT BUS="S_AXI_HP2" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="471" MSB="5" NAME="S_AXI_HP2_BID" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_HP2_ID_WIDTH - 1) : 0]"/>
         <PORT BUS="S_AXI_HP2" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="472" MSB="5" NAME="S_AXI_HP2_RID" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_HP2_ID_WIDTH - 1) : 0]"/>
         <PORT BUS="S_AXI_HP2" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="473" MSB="63" NAME="S_AXI_HP2_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_HP2_DATA_WIDTH - 1) :0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP2_FIFO_CTRL" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="474" MSB="7" NAME="S_AXI_HP2_RCOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP2_FIFO_CTRL" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="475" MSB="7" NAME="S_AXI_HP2_WCOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP2_FIFO_CTRL" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="476" MSB="2" NAME="S_AXI_HP2_RACOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP2_FIFO_CTRL" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="477" MSB="5" NAME="S_AXI_HP2_WACOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[5:0]"/>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP2_FIFO_CTRL" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="474" MSB="7" NAME="S_AXI_HP2_RCOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP2_FIFO_CTRL" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="475" MSB="7" NAME="S_AXI_HP2_WCOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP2_FIFO_CTRL" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="476" MSB="2" NAME="S_AXI_HP2_RACOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP2_FIFO_CTRL" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="477" MSB="5" NAME="S_AXI_HP2_WACOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[5:0]">
+          <CONNECTIONS/>
+        </PORT>
         <PORT BUS="S_AXI_HP2" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="478" NAME="S_AXI_HP2_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_HP2" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="479" NAME="S_AXI_HP2_ARVALID" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_HP2" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="480" NAME="S_AXI_HP2_AWVALID" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_HP2" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="481" NAME="S_AXI_HP2_BREADY" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="S_AXI_HP2_FIFO_CTRL" IS_VALID="FALSE" MPD_INDEX="482" NAME="S_AXI_HP2_RDISSUECAP1_EN" SIGNAME="__NOC__"/>
+        <PORT DIR="I" IOS="S_AXI_HP2_FIFO_CTRL" IS_VALID="FALSE" MPD_INDEX="482" NAME="S_AXI_HP2_RDISSUECAP1_EN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
         <PORT BUS="S_AXI_HP2" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="483" NAME="S_AXI_HP2_RREADY" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_HP2" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="484" NAME="S_AXI_HP2_WLAST" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="S_AXI_HP2_FIFO_CTRL" IS_VALID="FALSE" MPD_INDEX="485" NAME="S_AXI_HP2_WRISSUECAP1_EN" SIGNAME="__NOC__"/>
+        <PORT DIR="I" IOS="S_AXI_HP2_FIFO_CTRL" IS_VALID="FALSE" MPD_INDEX="485" NAME="S_AXI_HP2_WRISSUECAP1_EN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
         <PORT BUS="S_AXI_HP2" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="486" NAME="S_AXI_HP2_WVALID" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_HP2" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="487" MSB="1" NAME="S_AXI_HP2_ARBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
         <PORT BUS="S_AXI_HP2" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="488" MSB="1" NAME="S_AXI_HP2_ARLOCK" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
@@ -1461,7 +1725,9 @@
         <PORT BUS="S_AXI_HP2" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="505" MSB="5" NAME="S_AXI_HP2_WID" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_HP2_ID_WIDTH - 1) : 0]"/>
         <PORT BUS="S_AXI_HP2" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="506" MSB="63" NAME="S_AXI_HP2_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_HP2_DATA_WIDTH - 1) :0]"/>
         <PORT BUS="S_AXI_HP2" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="507" MSB="7" NAME="S_AXI_HP2_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S_AXI_HP2_DATA_WIDTH/8)-1):0]"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="508" NAME="S_AXI_HP3_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="508" NAME="S_AXI_HP3_ARESETN" SIGIS="RST" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
         <PORT BUS="S_AXI_HP3" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="509" NAME="S_AXI_HP3_ARREADY" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_HP3" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="510" NAME="S_AXI_HP3_AWREADY" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_HP3" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="511" NAME="S_AXI_HP3_BVALID" SIGNAME="__NOC__"/>
@@ -1473,18 +1739,30 @@
         <PORT BUS="S_AXI_HP3" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="517" MSB="5" NAME="S_AXI_HP3_BID" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_HP3_ID_WIDTH - 1) : 0]"/>
         <PORT BUS="S_AXI_HP3" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="518" MSB="5" NAME="S_AXI_HP3_RID" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_HP3_ID_WIDTH - 1) : 0]"/>
         <PORT BUS="S_AXI_HP3" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="519" MSB="63" NAME="S_AXI_HP3_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_HP3_DATA_WIDTH - 1) :0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP3_FIFO_CTRL" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="520" MSB="7" NAME="S_AXI_HP3_RCOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP3_FIFO_CTRL" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="521" MSB="7" NAME="S_AXI_HP3_WCOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP3_FIFO_CTRL" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="522" MSB="2" NAME="S_AXI_HP3_RACOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP3_FIFO_CTRL" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="523" MSB="5" NAME="S_AXI_HP3_WACOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[5:0]"/>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP3_FIFO_CTRL" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="520" MSB="7" NAME="S_AXI_HP3_RCOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP3_FIFO_CTRL" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="521" MSB="7" NAME="S_AXI_HP3_WCOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP3_FIFO_CTRL" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="522" MSB="2" NAME="S_AXI_HP3_RACOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP3_FIFO_CTRL" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="523" MSB="5" NAME="S_AXI_HP3_WACOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[5:0]">
+          <CONNECTIONS/>
+        </PORT>
         <PORT BUS="S_AXI_HP3" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="524" NAME="S_AXI_HP3_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_HP3" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="525" NAME="S_AXI_HP3_ARVALID" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_HP3" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="526" NAME="S_AXI_HP3_AWVALID" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_HP3" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="527" NAME="S_AXI_HP3_BREADY" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="S_AXI_HP3_FIFO_CTRL" IS_VALID="FALSE" MPD_INDEX="528" NAME="S_AXI_HP3_RDISSUECAP1_EN" SIGNAME="__NOC__"/>
+        <PORT DIR="I" IOS="S_AXI_HP3_FIFO_CTRL" IS_VALID="FALSE" MPD_INDEX="528" NAME="S_AXI_HP3_RDISSUECAP1_EN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
         <PORT BUS="S_AXI_HP3" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="529" NAME="S_AXI_HP3_RREADY" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_HP3" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="530" NAME="S_AXI_HP3_WLAST" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="S_AXI_HP3_FIFO_CTRL" IS_VALID="FALSE" MPD_INDEX="531" NAME="S_AXI_HP3_WRISSUECAP1_EN" SIGNAME="__NOC__"/>
+        <PORT DIR="I" IOS="S_AXI_HP3_FIFO_CTRL" IS_VALID="FALSE" MPD_INDEX="531" NAME="S_AXI_HP3_WRISSUECAP1_EN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
         <PORT BUS="S_AXI_HP3" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="532" NAME="S_AXI_HP3_WVALID" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI_HP3" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="533" MSB="1" NAME="S_AXI_HP3_ARBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
         <PORT BUS="S_AXI_HP3" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="534" MSB="1" NAME="S_AXI_HP3_ARLOCK" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
@@ -1507,121 +1785,351 @@
         <PORT BUS="S_AXI_HP3" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="551" MSB="5" NAME="S_AXI_HP3_WID" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_HP3_ID_WIDTH - 1) : 0]"/>
         <PORT BUS="S_AXI_HP3" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="552" MSB="63" NAME="S_AXI_HP3_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_HP3_DATA_WIDTH - 1) :0]"/>
         <PORT BUS="S_AXI_HP3" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="553" MSB="7" NAME="S_AXI_HP3_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S_AXI_HP3_DATA_WIDTH/8)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="DMA0_REQ" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="554" MSB="1" NAME="DMA0_DATYPE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
-        <PORT DIR="O" IOS="DMA0_REQ" IS_VALID="FALSE" MPD_INDEX="555" NAME="DMA0_DAVALID" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="DMA0_REQ" IS_VALID="FALSE" MPD_INDEX="556" NAME="DMA0_DRREADY" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="DMA0_REQ" IS_VALID="FALSE" MPD_INDEX="557" NAME="DMA0_RSTN" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="DMA0_REQ" IS_VALID="FALSE" MPD_INDEX="558" NAME="DMA0_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="DMA0_REQ" IS_VALID="FALSE" MPD_INDEX="559" NAME="DMA0_DAREADY" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="DMA0_REQ" IS_VALID="FALSE" MPD_INDEX="560" NAME="DMA0_DRLAST" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="DMA0_REQ" IS_VALID="FALSE" MPD_INDEX="561" NAME="DMA0_DRVALID" SIGNAME="__NOC__"/>
-        <PORT DIR="I" ENDIAN="LITTLE" IOS="DMA0_REQ" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="562" MSB="1" NAME="DMA0_DRTYPE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="DMA1_REQ" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="563" MSB="1" NAME="DMA1_DATYPE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
-        <PORT DIR="O" IOS="DMA1_REQ" IS_VALID="FALSE" MPD_INDEX="564" NAME="DMA1_DAVALID" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="DMA1_REQ" IS_VALID="FALSE" MPD_INDEX="565" NAME="DMA1_DRREADY" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="DMA1_REQ" IS_VALID="FALSE" MPD_INDEX="566" NAME="DMA1_RSTN" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="DMA1_REQ" IS_VALID="FALSE" MPD_INDEX="567" NAME="DMA1_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="DMA1_REQ" IS_VALID="FALSE" MPD_INDEX="568" NAME="DMA1_DAREADY" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="DMA1_REQ" IS_VALID="FALSE" MPD_INDEX="569" NAME="DMA1_DRLAST" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="DMA1_REQ" IS_VALID="FALSE" MPD_INDEX="570" NAME="DMA1_DRVALID" SIGNAME="__NOC__"/>
-        <PORT DIR="I" ENDIAN="LITTLE" IOS="DMA1_REQ" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="571" MSB="1" NAME="DMA1_DRTYPE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="DMA2_REQ" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="572" MSB="1" NAME="DMA2_DATYPE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
-        <PORT DIR="O" IOS="DMA2_REQ" IS_VALID="FALSE" MPD_INDEX="573" NAME="DMA2_DAVALID" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="DMA2_REQ" IS_VALID="FALSE" MPD_INDEX="574" NAME="DMA2_DRREADY" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="DMA2_REQ" IS_VALID="FALSE" MPD_INDEX="575" NAME="DMA2_RSTN" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="DMA2_REQ" IS_VALID="FALSE" MPD_INDEX="576" NAME="DMA2_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="DMA2_REQ" IS_VALID="FALSE" MPD_INDEX="577" NAME="DMA2_DAREADY" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="DMA2_REQ" IS_VALID="FALSE" MPD_INDEX="578" NAME="DMA2_DRLAST" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="DMA2_REQ" IS_VALID="FALSE" MPD_INDEX="579" NAME="DMA2_DRVALID" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="DMA3_REQ" IS_VALID="FALSE" MPD_INDEX="580" NAME="DMA3_DRVALID" SIGNAME="__NOC__"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="DMA3_REQ" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="581" MSB="1" NAME="DMA3_DATYPE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
-        <PORT DIR="O" IOS="DMA3_REQ" IS_VALID="FALSE" MPD_INDEX="582" NAME="DMA3_DAVALID" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="DMA3_REQ" IS_VALID="FALSE" MPD_INDEX="583" NAME="DMA3_DRREADY" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="DMA3_REQ" IS_VALID="FALSE" MPD_INDEX="584" NAME="DMA3_RSTN" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="DMA3_REQ" IS_VALID="FALSE" MPD_INDEX="585" NAME="DMA3_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="DMA3_REQ" IS_VALID="FALSE" MPD_INDEX="586" NAME="DMA3_DAREADY" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="DMA3_REQ" IS_VALID="FALSE" MPD_INDEX="587" NAME="DMA3_DRLAST" SIGNAME="__NOC__"/>
-        <PORT DIR="I" ENDIAN="LITTLE" IOS="DMA2_REQ" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="588" MSB="1" NAME="DMA2_DRTYPE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
-        <PORT DIR="I" ENDIAN="LITTLE" IOS="DMA3_REQ" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="589" MSB="1" NAME="DMA3_DRTYPE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
-        <PORT DIR="I" ENDIAN="LITTLE" IOS="FTM_TRACE_DATA" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="590" MSB="31" NAME="FTMD_TRACEIN_DATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31:0]"/>
-        <PORT DIR="I" IOS="FTM_TRACE_DATA" IS_VALID="FALSE" MPD_INDEX="591" NAME="FTMD_TRACEIN_VALID" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="FTM_TRACE_DATA" IS_VALID="FALSE" MPD_INDEX="592" NAME="FTMD_TRACEIN_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" ENDIAN="LITTLE" IOS="FTM_TRACE_DATA" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="593" MSB="3" NAME="FTMD_TRACEIN_ATID" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
-        <PORT DIR="I" ENDIAN="LITTLE" IOS="FTM_TRIG" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="594" MSB="3" NAME="FTMT_F2P_TRIG" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="FTM_TRIG" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="595" MSB="3" NAME="FTMT_F2P_TRIGACK" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
-        <PORT DIR="I" ENDIAN="LITTLE" IOS="FTM_TRIG" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="596" MSB="31" NAME="FTMT_F2P_DEBUG" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31:0]"/>
-        <PORT DIR="I" ENDIAN="LITTLE" IOS="FTM_TRIG" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="597" MSB="3" NAME="FTMT_P2F_TRIGACK" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="FTM_TRIG" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="598" MSB="3" NAME="FTMT_P2F_TRIG" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="FTM_TRIG" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="599" MSB="31" NAME="FTMT_P2F_DEBUG" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31:0]"/>
-        <PORT CLKFREQUENCY="100000000" DIR="O" MPD_INDEX="600" NAME="FCLK_CLK3" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT CLKFREQUENCY="12264151" DIR="O" MPD_INDEX="601" NAME="FCLK_CLK2" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT CLKFREQUENCY="175000000" DIR="O" MPD_INDEX="602" NAME="FCLK_CLK1" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" MPD_INDEX="604" NAME="FCLK_CLKTRIG3_N" SIGNAME="__NOC__"/>
-        <PORT DIR="I" MPD_INDEX="605" NAME="FCLK_CLKTRIG2_N" SIGNAME="__NOC__"/>
-        <PORT DIR="I" MPD_INDEX="606" NAME="FCLK_CLKTRIG1_N" SIGNAME="__NOC__"/>
-        <PORT DIR="I" MPD_INDEX="607" NAME="FCLK_CLKTRIG0_N" SIGNAME="__NOC__"/>
-        <PORT DIR="O" MPD_INDEX="608" NAME="FCLK_RESET3_N" SIGIS="RST" SIGNAME="__NOC__"/>
-        <PORT DIR="O" MPD_INDEX="609" NAME="FCLK_RESET2_N" SIGIS="RST" SIGNAME="__NOC__"/>
-        <PORT DIR="O" MPD_INDEX="610" NAME="FCLK_RESET1_N" SIGIS="RST" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="612" NAME="FPGA_IDLE_N" SIGNAME="__NOC__"/>
-        <PORT DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="613" MSB="3" NAME="DDR_ARB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
-        <PORT DIR="I" MPD_INDEX="614" NAME="IRQ_F2P" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__" VECFORMULA="[(C_NUM_F2P_INTR_INPUTS-1) :0]"/>
-        <PORT DIR="I" MPD_INDEX="615" NAME="Core0_nFIQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="I" MPD_INDEX="616" NAME="Core0_nIRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="I" MPD_INDEX="617" NAME="Core1_nFIQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="I" MPD_INDEX="618" NAME="Core1_nIRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="619" NAME="EVENT_EVENTO" SIGNAME="__NOC__"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="620" MSB="1" NAME="EVENT_STANDBYWFE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="621" MSB="1" NAME="EVENT_STANDBYWFI" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
-        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="622" NAME="EVENT_EVENTI" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="644" NAME="IRQ_P2F_DMAC_ABORT" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="645" NAME="IRQ_P2F_DMAC0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="646" NAME="IRQ_P2F_DMAC1" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="647" NAME="IRQ_P2F_DMAC2" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="648" NAME="IRQ_P2F_DMAC3" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="649" NAME="IRQ_P2F_DMAC4" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="650" NAME="IRQ_P2F_DMAC5" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="651" NAME="IRQ_P2F_DMAC6" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="652" NAME="IRQ_P2F_DMAC7" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="653" NAME="IRQ_P2F_SMC" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" MPD_INDEX="654" NAME="IRQ_P2F_QSPI" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="655" NAME="IRQ_P2F_CTI" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" MPD_INDEX="656" NAME="IRQ_P2F_GPIO" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" MPD_INDEX="657" NAME="IRQ_P2F_USB0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" MPD_INDEX="658" NAME="IRQ_P2F_ENET0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" MPD_INDEX="659" NAME="IRQ_P2F_ENET_WAKE0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" MPD_INDEX="660" NAME="IRQ_P2F_SDIO0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" MPD_INDEX="661" NAME="IRQ_P2F_I2C0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="662" NAME="IRQ_P2F_SPI0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" MPD_INDEX="663" NAME="IRQ_P2F_UART0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="664" NAME="IRQ_P2F_CAN0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="665" NAME="IRQ_P2F_USB1" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="666" NAME="IRQ_P2F_ENET1" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="667" NAME="IRQ_P2F_ENET_WAKE1" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="668" NAME="IRQ_P2F_SDIO1" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" MPD_INDEX="669" NAME="IRQ_P2F_I2C1" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="670" NAME="IRQ_P2F_SPI1" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" MPD_INDEX="671" NAME="IRQ_P2F_UART1" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="672" NAME="IRQ_P2F_CAN1" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="IO" IOS="ETHERNETIF_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="673" NAME="ENET0_MDIO" SIGNAME="__NOC__" TRI_I="ENET0_MDIO_I" TRI_O="ENET0_MDIO_O" TRI_T="ENET0_MDIO_T"/>
-        <PORT DIR="IO" IOS="ETHERNETIF_1" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="674" NAME="ENET1_MDIO" SIGNAME="__NOC__" TRI_I="ENET1_MDIO_I" TRI_O="ENET1_MDIO_O" TRI_T="ENET1_MDIO_T"/>
-        <PORT DIR="IO" ENDIAN="LITTLE" IOS="GPIO_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="675" MSB="63" NAME="GPIO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO_I" TRI_O="GPIO_O" TRI_T="GPIO_T" VECFORMULA="[(C_EMIO_GPIO_WIDTH-1):0]"/>
-        <PORT DIR="IO" IOS="IIC_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="676" NAME="I2C0_SDA" SIGNAME="__NOC__" TRI_I="I2C0_SDA_I" TRI_O="I2C0_SDA_O" TRI_T="I2C0_SDA_T"/>
-        <PORT DIR="IO" IOS="IIC_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="677" NAME="I2C0_SCL" SIGNAME="__NOC__" TRI_I="I2C0_SCL_I" TRI_O="I2C0_SCL_O" TRI_T="I2C0_SCL_T"/>
-        <PORT DIR="IO" IOS="IIC_1" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="678" NAME="I2C1_SDA" SIGNAME="__NOC__" TRI_I="I2C1_SDA_I" TRI_O="I2C1_SDA_O" TRI_T="I2C1_SDA_T"/>
-        <PORT DIR="IO" IOS="IIC_1" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="679" NAME="I2C1_SCL" SIGNAME="__NOC__" TRI_I="I2C1_SCL_I" TRI_O="I2C1_SCL_O" TRI_T="I2C1_SCL_T"/>
-        <PORT DIR="IO" IOS="SDIO_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="680" NAME="SDIO0_CMD" SIGNAME="__NOC__" TRI_I="SDIO0_CMD_I" TRI_O="SDIO0_CMD_O" TRI_T="SDIO0_CMD_T"/>
-        <PORT DIR="IO" ENDIAN="LITTLE" IOS="SDIO_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="681" MSB="3" NAME="SDIO0_DATA" RIGHT="0" SIGNAME="__NOC__" TRI_I="SDIO0_DATA_I" TRI_O="SDIO0_DATA_O" TRI_T="SDIO0_DATA_T" VECFORMULA="[3:0]"/>
-        <PORT DIR="IO" IOS="SDIO_1" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="682" NAME="SDIO1_CMD" SIGNAME="__NOC__" TRI_I="SDIO1_CMD_I" TRI_O="SDIO1_CMD_O" TRI_T="SDIO1_CMD_T"/>
-        <PORT DIR="IO" ENDIAN="LITTLE" IOS="SDIO_1" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="683" MSB="3" NAME="SDIO1_DATA" RIGHT="0" SIGNAME="__NOC__" TRI_I="SDIO1_DATA_I" TRI_O="SDIO1_DATA_O" TRI_T="SDIO1_DATA_T" VECFORMULA="[3:0]"/>
-        <PORT DIR="IO" IOS="SPI_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="684" NAME="SPI0_SCLK" SIGIS="CLK" SIGNAME="__NOC__" TRI_I="SPI0_SCLK_I" TRI_O="SPI0_SCLK_O" TRI_T="SPI0_SCLK_T"/>
-        <PORT DIR="IO" IOS="SPI_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="685" NAME="SPI0_MOSI" SIGNAME="__NOC__" TRI_I="SPI0_MOSI_I" TRI_O="SPI0_MOSI_O" TRI_T="SPI0_MOSI_T"/>
-        <PORT DIR="IO" IOS="SPI_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="686" NAME="SPI0_MISO" SIGNAME="__NOC__" TRI_I="SPI0_MISO_I" TRI_O="SPI0_MISO_O" TRI_T="SPI0_MISO_T"/>
-        <PORT DIR="IO" IOS="SPI_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="687" NAME="SPI0_SS" SIGNAME="__NOC__" TRI_I="SPI0_SS_I" TRI_O="SPI0_SS_O" TRI_T="SPI0_SS_T"/>
-        <PORT DIR="IO" IOS="SPI_1" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="688" NAME="SPI1_SCLK" SIGIS="CLK" SIGNAME="__NOC__" TRI_I="SPI1_SCLK_I" TRI_O="SPI1_SCLK_O" TRI_T="SPI1_SCLK_T"/>
-        <PORT DIR="IO" IOS="SPI_1" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="689" NAME="SPI1_MOSI" SIGNAME="__NOC__" TRI_I="SPI1_MOSI_I" TRI_O="SPI1_MOSI_O" TRI_T="SPI1_MOSI_T"/>
-        <PORT DIR="IO" IOS="SPI_1" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="690" NAME="SPI1_MISO" SIGNAME="__NOC__" TRI_I="SPI1_MISO_I" TRI_O="SPI1_MISO_O" TRI_T="SPI1_MISO_T"/>
-        <PORT DIR="IO" IOS="SPI_1" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="691" NAME="SPI1_SS" SIGNAME="__NOC__" TRI_I="SPI1_SS_I" TRI_O="SPI1_SS_O" TRI_T="SPI1_SS_T"/>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="DMA0_REQ" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="554" MSB="1" NAME="DMA0_DATYPE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="DMA0_REQ" IS_VALID="FALSE" MPD_INDEX="555" NAME="DMA0_DAVALID" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="DMA0_REQ" IS_VALID="FALSE" MPD_INDEX="556" NAME="DMA0_DRREADY" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="DMA0_REQ" IS_VALID="FALSE" MPD_INDEX="557" NAME="DMA0_RSTN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="DMA0_REQ" IS_VALID="FALSE" MPD_INDEX="558" NAME="DMA0_ACLK" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="DMA0_REQ" IS_VALID="FALSE" MPD_INDEX="559" NAME="DMA0_DAREADY" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="DMA0_REQ" IS_VALID="FALSE" MPD_INDEX="560" NAME="DMA0_DRLAST" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="DMA0_REQ" IS_VALID="FALSE" MPD_INDEX="561" NAME="DMA0_DRVALID" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" ENDIAN="LITTLE" IOS="DMA0_REQ" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="562" MSB="1" NAME="DMA0_DRTYPE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="DMA1_REQ" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="563" MSB="1" NAME="DMA1_DATYPE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="DMA1_REQ" IS_VALID="FALSE" MPD_INDEX="564" NAME="DMA1_DAVALID" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="DMA1_REQ" IS_VALID="FALSE" MPD_INDEX="565" NAME="DMA1_DRREADY" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="DMA1_REQ" IS_VALID="FALSE" MPD_INDEX="566" NAME="DMA1_RSTN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="DMA1_REQ" IS_VALID="FALSE" MPD_INDEX="567" NAME="DMA1_ACLK" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="DMA1_REQ" IS_VALID="FALSE" MPD_INDEX="568" NAME="DMA1_DAREADY" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="DMA1_REQ" IS_VALID="FALSE" MPD_INDEX="569" NAME="DMA1_DRLAST" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="DMA1_REQ" IS_VALID="FALSE" MPD_INDEX="570" NAME="DMA1_DRVALID" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" ENDIAN="LITTLE" IOS="DMA1_REQ" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="571" MSB="1" NAME="DMA1_DRTYPE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="DMA2_REQ" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="572" MSB="1" NAME="DMA2_DATYPE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="DMA2_REQ" IS_VALID="FALSE" MPD_INDEX="573" NAME="DMA2_DAVALID" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="DMA2_REQ" IS_VALID="FALSE" MPD_INDEX="574" NAME="DMA2_DRREADY" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="DMA2_REQ" IS_VALID="FALSE" MPD_INDEX="575" NAME="DMA2_RSTN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="DMA2_REQ" IS_VALID="FALSE" MPD_INDEX="576" NAME="DMA2_ACLK" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="DMA2_REQ" IS_VALID="FALSE" MPD_INDEX="577" NAME="DMA2_DAREADY" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="DMA2_REQ" IS_VALID="FALSE" MPD_INDEX="578" NAME="DMA2_DRLAST" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="DMA2_REQ" IS_VALID="FALSE" MPD_INDEX="579" NAME="DMA2_DRVALID" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="DMA3_REQ" IS_VALID="FALSE" MPD_INDEX="580" NAME="DMA3_DRVALID" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="DMA3_REQ" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="581" MSB="1" NAME="DMA3_DATYPE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="DMA3_REQ" IS_VALID="FALSE" MPD_INDEX="582" NAME="DMA3_DAVALID" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="DMA3_REQ" IS_VALID="FALSE" MPD_INDEX="583" NAME="DMA3_DRREADY" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IOS="DMA3_REQ" IS_VALID="FALSE" MPD_INDEX="584" NAME="DMA3_RSTN" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="DMA3_REQ" IS_VALID="FALSE" MPD_INDEX="585" NAME="DMA3_ACLK" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="DMA3_REQ" IS_VALID="FALSE" MPD_INDEX="586" NAME="DMA3_DAREADY" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="DMA3_REQ" IS_VALID="FALSE" MPD_INDEX="587" NAME="DMA3_DRLAST" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" ENDIAN="LITTLE" IOS="DMA2_REQ" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="588" MSB="1" NAME="DMA2_DRTYPE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" ENDIAN="LITTLE" IOS="DMA3_REQ" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="589" MSB="1" NAME="DMA3_DRTYPE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" ENDIAN="LITTLE" IOS="FTM_TRACE_DATA" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="590" MSB="31" NAME="FTMD_TRACEIN_DATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="FTM_TRACE_DATA" IS_VALID="FALSE" MPD_INDEX="591" NAME="FTMD_TRACEIN_VALID" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IOS="FTM_TRACE_DATA" IS_VALID="FALSE" MPD_INDEX="592" NAME="FTMD_TRACEIN_CLK" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" ENDIAN="LITTLE" IOS="FTM_TRACE_DATA" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="593" MSB="3" NAME="FTMD_TRACEIN_ATID" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" ENDIAN="LITTLE" IOS="FTM_TRIG" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="594" MSB="3" NAME="FTMT_F2P_TRIG" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="FTM_TRIG" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="595" MSB="3" NAME="FTMT_F2P_TRIGACK" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" ENDIAN="LITTLE" IOS="FTM_TRIG" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="596" MSB="31" NAME="FTMT_F2P_DEBUG" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" ENDIAN="LITTLE" IOS="FTM_TRIG" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="597" MSB="3" NAME="FTMT_P2F_TRIGACK" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="FTM_TRIG" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="598" MSB="3" NAME="FTMT_P2F_TRIG" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="FTM_TRIG" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="599" MSB="31" NAME="FTMT_P2F_DEBUG" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT CLKFREQUENCY="100000000" DIR="O" MPD_INDEX="600" NAME="FCLK_CLK3" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT CLKFREQUENCY="12264151" DIR="O" MPD_INDEX="601" NAME="FCLK_CLK2" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT CLKFREQUENCY="175000000" DIR="O" MPD_INDEX="602" NAME="FCLK_CLK1" SIGIS="CLK" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" MPD_INDEX="604" NAME="FCLK_CLKTRIG3_N" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" MPD_INDEX="605" NAME="FCLK_CLKTRIG2_N" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" MPD_INDEX="606" NAME="FCLK_CLKTRIG1_N" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" MPD_INDEX="607" NAME="FCLK_CLKTRIG0_N" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" MPD_INDEX="608" NAME="FCLK_RESET3_N" SIGIS="RST" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" MPD_INDEX="609" NAME="FCLK_RESET2_N" SIGIS="RST" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" MPD_INDEX="610" NAME="FCLK_RESET1_N" SIGIS="RST" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="612" NAME="FPGA_IDLE_N" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="613" MSB="3" NAME="DDR_ARB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" MPD_INDEX="614" NAME="IRQ_F2P" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__" VECFORMULA="[(C_NUM_F2P_INTR_INPUTS-1) :0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" MPD_INDEX="615" NAME="Core0_nFIQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" MPD_INDEX="616" NAME="Core0_nIRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" MPD_INDEX="617" NAME="Core1_nFIQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" MPD_INDEX="618" NAME="Core1_nIRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="619" NAME="EVENT_EVENTO" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="620" MSB="1" NAME="EVENT_STANDBYWFE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="621" MSB="1" NAME="EVENT_STANDBYWFI" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="622" NAME="EVENT_EVENTI" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="644" NAME="IRQ_P2F_DMAC_ABORT" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="645" NAME="IRQ_P2F_DMAC0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="646" NAME="IRQ_P2F_DMAC1" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="647" NAME="IRQ_P2F_DMAC2" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="648" NAME="IRQ_P2F_DMAC3" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="649" NAME="IRQ_P2F_DMAC4" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="650" NAME="IRQ_P2F_DMAC5" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="651" NAME="IRQ_P2F_DMAC6" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="652" NAME="IRQ_P2F_DMAC7" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="653" NAME="IRQ_P2F_SMC" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" MPD_INDEX="654" NAME="IRQ_P2F_QSPI" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="655" NAME="IRQ_P2F_CTI" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" MPD_INDEX="656" NAME="IRQ_P2F_GPIO" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" MPD_INDEX="657" NAME="IRQ_P2F_USB0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" MPD_INDEX="658" NAME="IRQ_P2F_ENET0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" MPD_INDEX="659" NAME="IRQ_P2F_ENET_WAKE0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" MPD_INDEX="660" NAME="IRQ_P2F_SDIO0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" MPD_INDEX="661" NAME="IRQ_P2F_I2C0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="662" NAME="IRQ_P2F_SPI0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" MPD_INDEX="663" NAME="IRQ_P2F_UART0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="664" NAME="IRQ_P2F_CAN0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="665" NAME="IRQ_P2F_USB1" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="666" NAME="IRQ_P2F_ENET1" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="667" NAME="IRQ_P2F_ENET_WAKE1" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="668" NAME="IRQ_P2F_SDIO1" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" MPD_INDEX="669" NAME="IRQ_P2F_I2C1" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="670" NAME="IRQ_P2F_SPI1" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" MPD_INDEX="671" NAME="IRQ_P2F_UART1" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="672" NAME="IRQ_P2F_CAN1" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="IO" IOS="ETHERNETIF_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="673" NAME="ENET0_MDIO" SIGNAME="__NOC__" TRI_I="ENET0_MDIO_I" TRI_O="ENET0_MDIO_O" TRI_T="ENET0_MDIO_T">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="IO" IOS="ETHERNETIF_1" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="674" NAME="ENET1_MDIO" SIGNAME="__NOC__" TRI_I="ENET1_MDIO_I" TRI_O="ENET1_MDIO_O" TRI_T="ENET1_MDIO_T">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="IO" ENDIAN="LITTLE" IOS="GPIO_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="675" MSB="63" NAME="GPIO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO_I" TRI_O="GPIO_O" TRI_T="GPIO_T" VECFORMULA="[(C_EMIO_GPIO_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="IO" IOS="IIC_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="676" NAME="I2C0_SDA" SIGNAME="__NOC__" TRI_I="I2C0_SDA_I" TRI_O="I2C0_SDA_O" TRI_T="I2C0_SDA_T">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="IO" IOS="IIC_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="677" NAME="I2C0_SCL" SIGNAME="__NOC__" TRI_I="I2C0_SCL_I" TRI_O="I2C0_SCL_O" TRI_T="I2C0_SCL_T">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="IO" IOS="IIC_1" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="678" NAME="I2C1_SDA" SIGNAME="__NOC__" TRI_I="I2C1_SDA_I" TRI_O="I2C1_SDA_O" TRI_T="I2C1_SDA_T">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="IO" IOS="IIC_1" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="679" NAME="I2C1_SCL" SIGNAME="__NOC__" TRI_I="I2C1_SCL_I" TRI_O="I2C1_SCL_O" TRI_T="I2C1_SCL_T">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="IO" IOS="SDIO_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="680" NAME="SDIO0_CMD" SIGNAME="__NOC__" TRI_I="SDIO0_CMD_I" TRI_O="SDIO0_CMD_O" TRI_T="SDIO0_CMD_T">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="IO" ENDIAN="LITTLE" IOS="SDIO_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="681" MSB="3" NAME="SDIO0_DATA" RIGHT="0" SIGNAME="__NOC__" TRI_I="SDIO0_DATA_I" TRI_O="SDIO0_DATA_O" TRI_T="SDIO0_DATA_T" VECFORMULA="[3:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="IO" IOS="SDIO_1" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="682" NAME="SDIO1_CMD" SIGNAME="__NOC__" TRI_I="SDIO1_CMD_I" TRI_O="SDIO1_CMD_O" TRI_T="SDIO1_CMD_T">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="IO" ENDIAN="LITTLE" IOS="SDIO_1" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="683" MSB="3" NAME="SDIO1_DATA" RIGHT="0" SIGNAME="__NOC__" TRI_I="SDIO1_DATA_I" TRI_O="SDIO1_DATA_O" TRI_T="SDIO1_DATA_T" VECFORMULA="[3:0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="IO" IOS="SPI_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="684" NAME="SPI0_SCLK" SIGIS="CLK" SIGNAME="__NOC__" TRI_I="SPI0_SCLK_I" TRI_O="SPI0_SCLK_O" TRI_T="SPI0_SCLK_T">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="IO" IOS="SPI_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="685" NAME="SPI0_MOSI" SIGNAME="__NOC__" TRI_I="SPI0_MOSI_I" TRI_O="SPI0_MOSI_O" TRI_T="SPI0_MOSI_T">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="IO" IOS="SPI_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="686" NAME="SPI0_MISO" SIGNAME="__NOC__" TRI_I="SPI0_MISO_I" TRI_O="SPI0_MISO_O" TRI_T="SPI0_MISO_T">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="IO" IOS="SPI_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="687" NAME="SPI0_SS" SIGNAME="__NOC__" TRI_I="SPI0_SS_I" TRI_O="SPI0_SS_O" TRI_T="SPI0_SS_T">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="IO" IOS="SPI_1" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="688" NAME="SPI1_SCLK" SIGIS="CLK" SIGNAME="__NOC__" TRI_I="SPI1_SCLK_I" TRI_O="SPI1_SCLK_O" TRI_T="SPI1_SCLK_T">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="IO" IOS="SPI_1" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="689" NAME="SPI1_MOSI" SIGNAME="__NOC__" TRI_I="SPI1_MOSI_I" TRI_O="SPI1_MOSI_O" TRI_T="SPI1_MOSI_T">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="IO" IOS="SPI_1" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="690" NAME="SPI1_MISO" SIGNAME="__NOC__" TRI_I="SPI1_MISO_I" TRI_O="SPI1_MISO_O" TRI_T="SPI1_MISO_T">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="IO" IOS="SPI_1" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="691" NAME="SPI1_SS" SIGNAME="__NOC__" TRI_I="SPI1_SS_I" TRI_O="SPI1_SS_O" TRI_T="SPI1_SS_T">
+          <CONNECTIONS/>
+        </PORT>
       </PORTS>
       <BUSINTERFACES>
         <BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="M_AXI_GP0" PROTOCOL="AXI3" TYPE="MASTER">
@@ -2586,10 +3094,10 @@
         <PERIPHERAL INSTANCE="pwm_signal_out_wkillswitch_3"/>
         <PERIPHERAL INSTANCE="axi_timer_0"/>
       </PERIPHERALS>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
     </MODULE>
     <MODULE HWVERSION="1.04.a" INSTANCE="pwm_recorder_0" IPTYPE="PERIPHERAL" MHS_INDEX="3" MODCLASS="PERIPHERAL" MODTYPE="pwm_recorder">
       <DESCRIPTION TYPE="SHORT">PWM_RECORDER</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_local"/>
       <PARAMETERS>
         <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
         <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
@@ -2739,6 +3247,7 @@
           </SLAVES>
         </MEMRANGE>
       </MEMORYMAP>
+      <LICENSEINFO ICON_NAME="ps_core_local"/>
     </MODULE>
     <MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.06.a" INSTANCE="axi_interconnect_1" IPTYPE="BUS" MHS_INDEX="4" MODCLASS="BUS" MODTYPE="axi_interconnect">
       <DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
@@ -2746,7 +3255,6 @@
       <DOCUMENTATION>
         <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v1_06_a;d=ds768_axi_interconnect.pdf" TYPE="IP"/>
       </DOCUMENTATION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
       <PARAMETERS>
         <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
         <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="zynq"/>
@@ -2858,7 +3366,9 @@
             <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_ARESETN"/>
           </CONNECTIONS>
         </PORT>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
         <PORT DEF_SIGNAME="axi_interconnect_1_S_ACLK" DIR="I" MPD_INDEX="5" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="axi_interconnect_1_S_ACLK" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
           <CONNECTIONS/>
         </PORT>
@@ -3426,115 +3936,301 @@
             <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_RREADY"/>
           </CONNECTIONS>
         </PORT>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="95" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="96" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="98" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="99" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="100" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="101" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="102" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="103" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="104" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="105" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="106" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="107" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="108" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="109" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="110" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="111" NAME="INTERCONNECT_ARESET_OUT_N" SIGNAME="__NOC__"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="112" MSB="7" NAME="DEBUG_AW_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="113" MSB="7" NAME="DEBUG_AW_ARB_GRANT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="114" MSB="7" NAME="DEBUG_AR_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="115" MSB="7" NAME="DEBUG_AR_ARB_GRANT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="116" NAME="DEBUG_AW_TRANS_QUAL" SIGNAME="__NOC__" VECFORMULA="[(C_MAX_DEBUG_THREADS-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="117" MSB="7" NAME="DEBUG_AW_ACCEPT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="118" MSB="15" NAME="DEBUG_AW_ACTIVE_THREAD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(16-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="119" MSB="7" NAME="DEBUG_AW_ACTIVE_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="120" MSB="7" NAME="DEBUG_AW_ACTIVE_REGION" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="121" MSB="7" NAME="DEBUG_AW_ERROR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="122" MSB="7" NAME="DEBUG_AW_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="123" NAME="DEBUG_AR_TRANS_QUAL" SIGNAME="__NOC__" VECFORMULA="[(C_MAX_DEBUG_THREADS-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="124" MSB="7" NAME="DEBUG_AR_ACCEPT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="125" MSB="15" NAME="DEBUG_AR_ACTIVE_THREAD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(16-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="126" MSB="7" NAME="DEBUG_AR_ACTIVE_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="127" MSB="7" NAME="DEBUG_AR_ACTIVE_REGION" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="128" MSB="7" NAME="DEBUG_AR_ERROR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="129" MSB="7" NAME="DEBUG_AR_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="130" MSB="7" NAME="DEBUG_B_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="131" MSB="7" NAME="DEBUG_R_BEAT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="132" MSB="7" NAME="DEBUG_R_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="133" MSB="7" NAME="DEBUG_AW_ISSUING_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="134" MSB="7" NAME="DEBUG_AR_ISSUING_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="135" MSB="7" NAME="DEBUG_W_BEAT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="136" MSB="7" NAME="DEBUG_W_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="137" MSB="7" NAME="DEBUG_BID_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="138" NAME="DEBUG_BID_ERROR" SIGNAME="__NOC__"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="139" MSB="7" NAME="DEBUG_RID_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="140" NAME="DEBUG_RID_ERROR" SIGNAME="__NOC__"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="141" MSB="31" NAME="DEBUG_SR_SC_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="142" MSB="34" NAME="DEBUG_SR_SC_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="143" MSB="31" NAME="DEBUG_SR_SC_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="144" MSB="34" NAME="DEBUG_SR_SC_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="145" MSB="15" NAME="DEBUG_SR_SC_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="146" MSB="31" NAME="DEBUG_SR_SC_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="16" LSB="0" MPD_INDEX="147" MSB="16" NAME="DEBUG_SR_SC_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="148" MSB="31" NAME="DEBUG_SR_SC_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="149" MSB="6" NAME="DEBUG_SR_SC_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="150" MSB="31" NAME="DEBUG_SC_SF_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="151" MSB="34" NAME="DEBUG_SC_SF_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="152" MSB="31" NAME="DEBUG_SC_SF_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="153" MSB="34" NAME="DEBUG_SC_SF_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="154" MSB="15" NAME="DEBUG_SC_SF_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="155" MSB="31" NAME="DEBUG_SC_SF_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="16" LSB="0" MPD_INDEX="156" MSB="16" NAME="DEBUG_SC_SF_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="157" MSB="31" NAME="DEBUG_SC_SF_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="158" MSB="6" NAME="DEBUG_SC_SF_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="159" MSB="31" NAME="DEBUG_SF_CB_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="160" MSB="34" NAME="DEBUG_SF_CB_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="161" MSB="31" NAME="DEBUG_SF_CB_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="162" MSB="34" NAME="DEBUG_SF_CB_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="163" MSB="15" NAME="DEBUG_SF_CB_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="164" MSB="31" NAME="DEBUG_SF_CB_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="16" LSB="0" MPD_INDEX="165" MSB="16" NAME="DEBUG_SF_CB_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="166" MSB="31" NAME="DEBUG_SF_CB_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="167" MSB="6" NAME="DEBUG_SF_CB_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="168" MSB="31" NAME="DEBUG_CB_MF_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="169" MSB="34" NAME="DEBUG_CB_MF_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="170" MSB="31" NAME="DEBUG_CB_MF_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="171" MSB="34" NAME="DEBUG_CB_MF_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="172" MSB="15" NAME="DEBUG_CB_MF_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="173" MSB="31" NAME="DEBUG_CB_MF_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
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-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="177" MSB="31" NAME="DEBUG_MF_MC_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="178" MSB="34" NAME="DEBUG_MF_MC_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="179" MSB="31" NAME="DEBUG_MF_MC_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="180" MSB="34" NAME="DEBUG_MF_MC_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="181" MSB="15" NAME="DEBUG_MF_MC_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="182" MSB="31" NAME="DEBUG_MF_MC_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="16" LSB="0" MPD_INDEX="183" MSB="16" NAME="DEBUG_MF_MC_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="184" MSB="31" NAME="DEBUG_MF_MC_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="185" MSB="6" NAME="DEBUG_MF_MC_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="186" MSB="31" NAME="DEBUG_MC_MP_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="187" MSB="34" NAME="DEBUG_MC_MP_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="188" MSB="31" NAME="DEBUG_MC_MP_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="189" MSB="34" NAME="DEBUG_MC_MP_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="190" MSB="15" NAME="DEBUG_MC_MP_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="191" MSB="31" NAME="DEBUG_MC_MP_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="16" LSB="0" MPD_INDEX="192" MSB="16" NAME="DEBUG_MC_MP_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="193" MSB="31" NAME="DEBUG_MC_MP_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="194" MSB="6" NAME="DEBUG_MC_MP_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="195" MSB="31" NAME="DEBUG_MP_MR_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="196" MSB="34" NAME="DEBUG_MP_MR_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="197" MSB="31" NAME="DEBUG_MP_MR_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="198" MSB="34" NAME="DEBUG_MP_MR_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="199" MSB="15" NAME="DEBUG_MP_MR_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="200" MSB="31" NAME="DEBUG_MP_MR_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="16" LSB="0" MPD_INDEX="201" MSB="16" NAME="DEBUG_MP_MR_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="202" MSB="31" NAME="DEBUG_MP_MR_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="203" MSB="6" NAME="DEBUG_MP_MR_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="95" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="96" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="98" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="99" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="100" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="101" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="102" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="103" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="104" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="105" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="106" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="107" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="108" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="109" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
+        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="110" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="111" NAME="INTERCONNECT_ARESET_OUT_N" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="112" MSB="7" NAME="DEBUG_AW_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="113" MSB="7" NAME="DEBUG_AW_ARB_GRANT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="114" MSB="7" NAME="DEBUG_AR_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="115" MSB="7" NAME="DEBUG_AR_ARB_GRANT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="116" NAME="DEBUG_AW_TRANS_QUAL" SIGNAME="__NOC__" VECFORMULA="[(C_MAX_DEBUG_THREADS-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="117" MSB="7" NAME="DEBUG_AW_ACCEPT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="118" MSB="15" NAME="DEBUG_AW_ACTIVE_THREAD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(16-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="119" MSB="7" NAME="DEBUG_AW_ACTIVE_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="120" MSB="7" NAME="DEBUG_AW_ACTIVE_REGION" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="121" MSB="7" NAME="DEBUG_AW_ERROR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="122" MSB="7" NAME="DEBUG_AW_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="123" NAME="DEBUG_AR_TRANS_QUAL" SIGNAME="__NOC__" VECFORMULA="[(C_MAX_DEBUG_THREADS-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="124" MSB="7" NAME="DEBUG_AR_ACCEPT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="125" MSB="15" NAME="DEBUG_AR_ACTIVE_THREAD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(16-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="126" MSB="7" NAME="DEBUG_AR_ACTIVE_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="127" MSB="7" NAME="DEBUG_AR_ACTIVE_REGION" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="128" MSB="7" NAME="DEBUG_AR_ERROR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="129" MSB="7" NAME="DEBUG_AR_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="130" MSB="7" NAME="DEBUG_B_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="131" MSB="7" NAME="DEBUG_R_BEAT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="132" MSB="7" NAME="DEBUG_R_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="133" MSB="7" NAME="DEBUG_AW_ISSUING_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="134" MSB="7" NAME="DEBUG_AR_ISSUING_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="135" MSB="7" NAME="DEBUG_W_BEAT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="136" MSB="7" NAME="DEBUG_W_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="137" MSB="7" NAME="DEBUG_BID_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="138" NAME="DEBUG_BID_ERROR" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="139" MSB="7" NAME="DEBUG_RID_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="140" NAME="DEBUG_RID_ERROR" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="141" MSB="31" NAME="DEBUG_SR_SC_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="142" MSB="34" NAME="DEBUG_SR_SC_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="143" MSB="31" NAME="DEBUG_SR_SC_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="144" MSB="34" NAME="DEBUG_SR_SC_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="145" MSB="15" NAME="DEBUG_SR_SC_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="146" MSB="31" NAME="DEBUG_SR_SC_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="16" LSB="0" MPD_INDEX="147" MSB="16" NAME="DEBUG_SR_SC_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="148" MSB="31" NAME="DEBUG_SR_SC_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="149" MSB="6" NAME="DEBUG_SR_SC_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="150" MSB="31" NAME="DEBUG_SC_SF_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="151" MSB="34" NAME="DEBUG_SC_SF_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="152" MSB="31" NAME="DEBUG_SC_SF_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="153" MSB="34" NAME="DEBUG_SC_SF_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="154" MSB="15" NAME="DEBUG_SC_SF_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="155" MSB="31" NAME="DEBUG_SC_SF_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="16" LSB="0" MPD_INDEX="156" MSB="16" NAME="DEBUG_SC_SF_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="157" MSB="31" NAME="DEBUG_SC_SF_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="158" MSB="6" NAME="DEBUG_SC_SF_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="159" MSB="31" NAME="DEBUG_SF_CB_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="160" MSB="34" NAME="DEBUG_SF_CB_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="161" MSB="31" NAME="DEBUG_SF_CB_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="162" MSB="34" NAME="DEBUG_SF_CB_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="163" MSB="15" NAME="DEBUG_SF_CB_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="164" MSB="31" NAME="DEBUG_SF_CB_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="16" LSB="0" MPD_INDEX="165" MSB="16" NAME="DEBUG_SF_CB_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="166" MSB="31" NAME="DEBUG_SF_CB_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="167" MSB="6" NAME="DEBUG_SF_CB_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="168" MSB="31" NAME="DEBUG_CB_MF_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="169" MSB="34" NAME="DEBUG_CB_MF_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="170" MSB="31" NAME="DEBUG_CB_MF_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="171" MSB="34" NAME="DEBUG_CB_MF_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="172" MSB="15" NAME="DEBUG_CB_MF_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="173" MSB="31" NAME="DEBUG_CB_MF_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="16" LSB="0" MPD_INDEX="174" MSB="16" NAME="DEBUG_CB_MF_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="175" MSB="31" NAME="DEBUG_CB_MF_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="176" MSB="6" NAME="DEBUG_CB_MF_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="177" MSB="31" NAME="DEBUG_MF_MC_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="178" MSB="34" NAME="DEBUG_MF_MC_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="179" MSB="31" NAME="DEBUG_MF_MC_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="180" MSB="34" NAME="DEBUG_MF_MC_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="181" MSB="15" NAME="DEBUG_MF_MC_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="182" MSB="31" NAME="DEBUG_MF_MC_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="16" LSB="0" MPD_INDEX="183" MSB="16" NAME="DEBUG_MF_MC_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="184" MSB="31" NAME="DEBUG_MF_MC_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="185" MSB="6" NAME="DEBUG_MF_MC_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="186" MSB="31" NAME="DEBUG_MC_MP_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="187" MSB="34" NAME="DEBUG_MC_MP_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="188" MSB="31" NAME="DEBUG_MC_MP_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="189" MSB="34" NAME="DEBUG_MC_MP_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="190" MSB="15" NAME="DEBUG_MC_MP_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="191" MSB="31" NAME="DEBUG_MC_MP_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="16" LSB="0" MPD_INDEX="192" MSB="16" NAME="DEBUG_MC_MP_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="193" MSB="31" NAME="DEBUG_MC_MP_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="194" MSB="6" NAME="DEBUG_MC_MP_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="195" MSB="31" NAME="DEBUG_MP_MR_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="196" MSB="34" NAME="DEBUG_MP_MR_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="197" MSB="31" NAME="DEBUG_MP_MR_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="198" MSB="34" NAME="DEBUG_MP_MR_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="199" MSB="15" NAME="DEBUG_MP_MR_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="200" MSB="31" NAME="DEBUG_MP_MR_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="16" LSB="0" MPD_INDEX="201" MSB="16" NAME="DEBUG_MP_MR_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="202" MSB="31" NAME="DEBUG_MP_MR_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="203" MSB="6" NAME="DEBUG_MP_MR_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]">
+          <CONNECTIONS/>
+        </PORT>
       </PORTS>
       <BUSINTERFACES>
         <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
@@ -3566,10 +4262,10 @@
           </SLAVES>
         </MEMRANGE>
       </MEMORYMAP>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
     </MODULE>
     <MODULE HWVERSION="1.04.a" INSTANCE="pwm_recorder_1" IPTYPE="PERIPHERAL" MHS_INDEX="5" MODCLASS="PERIPHERAL" MODTYPE="pwm_recorder">
       <DESCRIPTION TYPE="SHORT">PWM_RECORDER</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_local"/>
       <PARAMETERS>
         <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
         <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
@@ -3719,10 +4415,10 @@
           </SLAVES>
         </MEMRANGE>
       </MEMORYMAP>
+      <LICENSEINFO ICON_NAME="ps_core_local"/>
     </MODULE>
     <MODULE HWVERSION="1.04.a" INSTANCE="pwm_recorder_2" IPTYPE="PERIPHERAL" MHS_INDEX="6" MODCLASS="PERIPHERAL" MODTYPE="pwm_recorder">
       <DESCRIPTION TYPE="SHORT">PWM_RECORDER</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_local"/>
       <PARAMETERS>
         <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
         <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
@@ -3872,10 +4568,10 @@
           </SLAVES>
         </MEMRANGE>
       </MEMORYMAP>
+      <LICENSEINFO ICON_NAME="ps_core_local"/>
     </MODULE>
     <MODULE HWVERSION="1.04.a" INSTANCE="pwm_recorder_3" IPTYPE="PERIPHERAL" MHS_INDEX="7" MODCLASS="PERIPHERAL" MODTYPE="pwm_recorder">
       <DESCRIPTION TYPE="SHORT">PWM_RECORDER</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_local"/>
       <PARAMETERS>
         <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
         <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
@@ -4025,10 +4721,10 @@
           </SLAVES>
         </MEMRANGE>
       </MEMORYMAP>
+      <LICENSEINFO ICON_NAME="ps_core_local"/>
     </MODULE>
     <MODULE HWVERSION="1.04.a" INSTANCE="pwm_recorder_4" IPTYPE="PERIPHERAL" MHS_INDEX="8" MODCLASS="PERIPHERAL" MODTYPE="pwm_recorder">
       <DESCRIPTION TYPE="SHORT">PWM_RECORDER</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_local"/>
       <PARAMETERS>
         <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
         <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
@@ -4178,10 +4874,10 @@
           </SLAVES>
         </MEMRANGE>
       </MEMORYMAP>
+      <LICENSEINFO ICON_NAME="ps_core_local"/>
     </MODULE>
     <MODULE HWVERSION="1.04.a" INSTANCE="pwm_recorder_5" IPTYPE="PERIPHERAL" MHS_INDEX="9" MODCLASS="PERIPHERAL" MODTYPE="pwm_recorder">
       <DESCRIPTION TYPE="SHORT">PWM_RECORDER</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_local"/>
       <PARAMETERS>
         <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
         <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
@@ -4331,6 +5027,7 @@
           </SLAVES>
         </MEMRANGE>
       </MEMORYMAP>
+      <LICENSEINFO ICON_NAME="ps_core_local"/>
     </MODULE>
     <MODULE HWVERSION="1.01.b" INSTANCE="BTNs_4Bits_TRI_IO" IPTYPE="PERIPHERAL" MHS_INDEX="10" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio">
       <DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION>
@@ -4338,7 +5035,6 @@
       <DOCUMENTATION>
         <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_gpio;v=v1_01_b;d=ds744_axi_gpio.pdf" TYPE="IP"/>
       </DOCUMENTATION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
       <PARAMETERS>
         <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
         <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_INSTANCE" TYPE="STRING" VALUE="BTNs_4Bits_TRI_IO"/>
@@ -4459,17 +5155,31 @@
             <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
           </CONNECTIONS>
         </PORT>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="19" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="21" MSB="3" NAME="GPIO_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="22" MSB="3" NAME="GPIO_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
-        <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="23" MSB="31" NAME="GPIO2_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="24" MSB="31" NAME="GPIO2_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="25" MSB="31" NAME="GPIO2_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
+        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="19" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="21" MSB="3" NAME="GPIO_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="22" MSB="3" NAME="GPIO_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="23" MSB="31" NAME="GPIO2_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="24" MSB="31" NAME="GPIO2_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="25" MSB="31" NAME="GPIO2_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]">
+          <CONNECTIONS/>
+        </PORT>
         <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" LEFT="3" LSB="0" MPD_INDEX="26" MSB="3" NAME="GPIO_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
           <DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
+          <CONNECTIONS/>
         </PORT>
         <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="27" MSB="31" NAME="GPIO2_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[(C_GPIO2_WIDTH-1):0]">
           <DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
+          <CONNECTIONS/>
         </PORT>
       </PORTS>
       <BUSINTERFACES>
@@ -4518,10 +5228,10 @@
           </SLAVES>
         </MEMRANGE>
       </MEMORYMAP>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
     </MODULE>
     <MODULE HWVERSION="1.00.a" INSTANCE="pwm_signal_out_wkillswitch_0" IPTYPE="PERIPHERAL" MHS_INDEX="11" MODCLASS="PERIPHERAL" MODTYPE="pwm_signal_out_wkillswitch">
       <DESCRIPTION TYPE="SHORT">PWM_SIGNAL_OUT_WKILLSWITCH</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_local"/>
       <PARAMETERS>
         <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
         <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
@@ -4671,10 +5381,10 @@
           </SLAVES>
         </MEMRANGE>
       </MEMORYMAP>
+      <LICENSEINFO ICON_NAME="ps_core_local"/>
     </MODULE>
     <MODULE HWVERSION="1.00.a" INSTANCE="pwm_signal_out_wkillswitch_1" IPTYPE="PERIPHERAL" MHS_INDEX="12" MODCLASS="PERIPHERAL" MODTYPE="pwm_signal_out_wkillswitch">
       <DESCRIPTION TYPE="SHORT">PWM_SIGNAL_OUT_WKILLSWITCH</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_local"/>
       <PARAMETERS>
         <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
         <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
@@ -4824,10 +5534,10 @@
           </SLAVES>
         </MEMRANGE>
       </MEMORYMAP>
+      <LICENSEINFO ICON_NAME="ps_core_local"/>
     </MODULE>
     <MODULE HWVERSION="1.00.a" INSTANCE="pwm_signal_out_wkillswitch_2" IPTYPE="PERIPHERAL" MHS_INDEX="13" MODCLASS="PERIPHERAL" MODTYPE="pwm_signal_out_wkillswitch">
       <DESCRIPTION TYPE="SHORT">PWM_SIGNAL_OUT_WKILLSWITCH</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_local"/>
       <PARAMETERS>
         <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
         <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
@@ -4977,10 +5687,10 @@
           </SLAVES>
         </MEMRANGE>
       </MEMORYMAP>
+      <LICENSEINFO ICON_NAME="ps_core_local"/>
     </MODULE>
     <MODULE HWVERSION="1.00.a" INSTANCE="pwm_signal_out_wkillswitch_3" IPTYPE="PERIPHERAL" MHS_INDEX="14" MODCLASS="PERIPHERAL" MODTYPE="pwm_signal_out_wkillswitch">
       <DESCRIPTION TYPE="SHORT">PWM_SIGNAL_OUT_WKILLSWITCH</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_local"/>
       <PARAMETERS>
         <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
         <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
@@ -5130,6 +5840,7 @@
           </SLAVES>
         </MEMRANGE>
       </MEMORYMAP>
+      <LICENSEINFO ICON_NAME="ps_core_local"/>
     </MODULE>
     <MODULE HWVERSION="1.03.a" INSTANCE="axi_timer_0" IPTYPE="PERIPHERAL" MHS_INDEX="15" MODCLASS="PERIPHERAL" MODTYPE="axi_timer">
       <DESCRIPTION TYPE="SHORT">AXI Timer/Counter</DESCRIPTION>
@@ -5137,7 +5848,6 @@
       <DOCUMENTATION>
         <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_timer;v=v1_03_a;d=axi_timer_ds764.pdf" TYPE="IP"/>
       </DOCUMENTATION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
       <PARAMETERS>
         <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
         <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
@@ -5161,21 +5871,30 @@
         </PORT>
         <PORT DIR="I" MPD_INDEX="0" NAME="CaptureTrig0" SIGNAME="__NOC__">
           <DESCRIPTION>Capture Trig 0</DESCRIPTION>
+          <CONNECTIONS/>
         </PORT>
         <PORT DIR="I" MPD_INDEX="1" NAME="CaptureTrig1" SIGNAME="__NOC__">
           <DESCRIPTION>Capture Trig 1</DESCRIPTION>
+          <CONNECTIONS/>
         </PORT>
         <PORT DIR="O" MPD_INDEX="2" NAME="GenerateOut0" SIGNAME="__NOC__">
           <DESCRIPTION>Generate Out 0</DESCRIPTION>
+          <CONNECTIONS/>
         </PORT>
         <PORT DIR="O" MPD_INDEX="3" NAME="GenerateOut1" SIGNAME="__NOC__">
           <DESCRIPTION>Generate Out 1</DESCRIPTION>
+          <CONNECTIONS/>
         </PORT>
         <PORT DIR="O" MPD_INDEX="4" NAME="PWM0" SIGNAME="__NOC__">
           <DESCRIPTION>Pulse Width Modulation 0</DESCRIPTION>
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="O" MPD_INDEX="5" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__">
+          <CONNECTIONS/>
+        </PORT>
+        <PORT DIR="I" MPD_INDEX="6" NAME="Freeze" SIGNAME="__NOC__">
+          <CONNECTIONS/>
         </PORT>
-        <PORT DIR="O" MPD_INDEX="5" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="I" MPD_INDEX="6" NAME="Freeze" SIGNAME="__NOC__"/>
         <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="8" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
           <CONNECTIONS>
             <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
@@ -5299,7 +6018,191 @@
           </SLAVES>
         </MEMRANGE>
       </MEMORYMAP>
+      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
     </MODULE>
   </MODULES>
 
+  <EXTERNALPORTS>
+    <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="N" DIR="I" MHS_INDEX="0" NAME="CLK_N" SIGIS="CLK" SIGNAME="CLK">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="clock_generator_0" PORT="CLKIN"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="P" DIR="I" MHS_INDEX="1" NAME="CLK_P" SIGIS="CLK" SIGNAME="CLK">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="clock_generator_0" PORT="CLKIN"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="53" LSB="0" MHS_INDEX="2" MSB="53" NAME="processing_system7_0_MIO" RIGHT="0" SIGNAME="processing_system7_0_MIO">
+      <CONNECTIONS>
+        <CONNECTION BUSINTERFACE="[PS_REQUIRED_EXTERNAL_IO]" INSTANCE="processing_system7_0" PORT="MIO"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="I" MHS_INDEX="3" NAME="processing_system7_0_PS_SRSTB_pin" SIGNAME="processing_system7_0_PS_SRSTB">
+      <CONNECTIONS>
+        <CONNECTION BUSINTERFACE="[PS_REQUIRED_EXTERNAL_IO]" INSTANCE="processing_system7_0" PORT="PS_SRSTB"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="I" MHS_INDEX="4" NAME="processing_system7_0_PS_CLK_pin" SIGIS="CLK" SIGNAME="processing_system7_0_PS_CLK">
+      <CONNECTIONS>
+        <CONNECTION BUSINTERFACE="[PS_REQUIRED_EXTERNAL_IO]" INSTANCE="processing_system7_0" PORT="PS_CLK"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="I" MHS_INDEX="5" NAME="processing_system7_0_PS_PORB_pin" SIGNAME="processing_system7_0_PS_PORB">
+      <CONNECTIONS>
+        <CONNECTION BUSINTERFACE="[PS_REQUIRED_EXTERNAL_IO]" INSTANCE="processing_system7_0" PORT="PS_PORB"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="IO" MHS_INDEX="6" NAME="processing_system7_0_DDR_Clk" SIGIS="CLK" SIGNAME="processing_system7_0_DDR_Clk">
+      <CONNECTIONS>
+        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_Clk"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="IO" MHS_INDEX="7" NAME="processing_system7_0_DDR_Clk_n" SIGIS="CLK" SIGNAME="processing_system7_0_DDR_Clk_n">
+      <CONNECTIONS>
+        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_Clk_n"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="IO" MHS_INDEX="8" NAME="processing_system7_0_DDR_CKE" SIGNAME="processing_system7_0_DDR_CKE">
+      <CONNECTIONS>
+        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_CKE"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="IO" MHS_INDEX="9" NAME="processing_system7_0_DDR_CS_n" SIGNAME="processing_system7_0_DDR_CS_n">
+      <CONNECTIONS>
+        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_CS_n"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="IO" MHS_INDEX="10" NAME="processing_system7_0_DDR_RAS_n" SIGNAME="processing_system7_0_DDR_RAS_n">
+      <CONNECTIONS>
+        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_RAS_n"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="IO" MHS_INDEX="11" NAME="processing_system7_0_DDR_CAS_n" SIGNAME="processing_system7_0_DDR_CAS_n">
+      <CONNECTIONS>
+        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_CAS_n"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="O" MHS_INDEX="12" NAME="processing_system7_0_DDR_WEB_pin" SIGNAME="processing_system7_0_DDR_WEB">
+      <CONNECTIONS>
+        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_WEB"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="2" LSB="0" MHS_INDEX="13" MSB="2" NAME="processing_system7_0_DDR_BankAddr" RIGHT="0" SIGNAME="processing_system7_0_DDR_BankAddr">
+      <CONNECTIONS>
+        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_BankAddr"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="14" LSB="0" MHS_INDEX="14" MSB="14" NAME="processing_system7_0_DDR_Addr" RIGHT="0" SIGNAME="processing_system7_0_DDR_Addr">
+      <CONNECTIONS>
+        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_Addr"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="IO" MHS_INDEX="15" NAME="processing_system7_0_DDR_ODT" SIGNAME="processing_system7_0_DDR_ODT">
+      <CONNECTIONS>
+        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_ODT"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="IO" MHS_INDEX="16" NAME="processing_system7_0_DDR_DRSTB" SIGIS="RST" SIGNAME="processing_system7_0_DDR_DRSTB">
+      <CONNECTIONS>
+        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_DRSTB"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="31" LSB="0" MHS_INDEX="17" MSB="31" NAME="processing_system7_0_DDR_DQ" RIGHT="0" SIGNAME="processing_system7_0_DDR_DQ">
+      <CONNECTIONS>
+        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_DQ"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="18" MSB="3" NAME="processing_system7_0_DDR_DM" RIGHT="0" SIGNAME="processing_system7_0_DDR_DM">
+      <CONNECTIONS>
+        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_DM"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="19" MSB="3" NAME="processing_system7_0_DDR_DQS" RIGHT="0" SIGNAME="processing_system7_0_DDR_DQS">
+      <CONNECTIONS>
+        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_DQS"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="20" MSB="3" NAME="processing_system7_0_DDR_DQS_n" RIGHT="0" SIGNAME="processing_system7_0_DDR_DQS_n">
+      <CONNECTIONS>
+        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_DQS_n"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="IO" MHS_INDEX="21" NAME="processing_system7_0_DDR_VRN" SIGNAME="processing_system7_0_DDR_VRN">
+      <CONNECTIONS>
+        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_VRN"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="IO" MHS_INDEX="22" NAME="processing_system7_0_DDR_VRP" SIGNAME="processing_system7_0_DDR_VRP">
+      <CONNECTIONS>
+        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_VRP"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="I" MHS_INDEX="23" NAME="pwm_recorder_0_pwm_in_master_pin" SIGNAME="pwm_recorder_0_pwm_in_master">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="pwm_recorder_0" PORT="pwm_in_master"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="I" MHS_INDEX="24" NAME="pwm_recorder_1_pwm_in_master_pin" SIGNAME="pwm_recorder_1_pwm_in_master">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="pwm_recorder_1" PORT="pwm_in_master"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="I" MHS_INDEX="25" NAME="pwm_recorder_2_pwm_in_master_pin" SIGNAME="pwm_recorder_2_pwm_in_master">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="pwm_recorder_2" PORT="pwm_in_master"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="I" MHS_INDEX="26" NAME="pwm_recorder_3_pwm_in_master_pin" SIGNAME="pwm_recorder_3_pwm_in_master">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="pwm_recorder_3" PORT="pwm_in_master"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="I" MHS_INDEX="27" NAME="pwm_recorder_4_pwm_in_master_pin" SIGNAME="pwm_recorder_4_pwm_in_master">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="pwm_recorder_4" PORT="pwm_in_master"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="I" MHS_INDEX="28" NAME="pwm_recorder_5_pwm_in_master_pin" SIGNAME="pwm_recorder_5_pwm_in_master">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="pwm_recorder_5" PORT="pwm_in_master"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="29" MSB="3" NAME="BTNs_4Bits_TRI_IO_GPIO_IO_I_pin" RIGHT="0" SIGNAME="BTNs_4Bits_TRI_IO_GPIO_IO_I">
+      <CONNECTIONS>
+        <CONNECTION BUSINTERFACE="[gpio_0]" INSTANCE="BTNs_4Bits_TRI_IO" PORT="GPIO_IO_I"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="O" MHS_INDEX="30" NAME="processing_system7_0_UART0_TX_pin" SIGNAME="processing_system7_0_UART0_TX">
+      <CONNECTIONS>
+        <CONNECTION BUSINTERFACE="[UART_0]" INSTANCE="processing_system7_0" PORT="UART0_TX"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="I" MHS_INDEX="31" NAME="processing_system7_0_UART0_RX_pin" SIGNAME="processing_system7_0_UART0_RX">
+      <CONNECTIONS>
+        <CONNECTION BUSINTERFACE="[UART_0]" INSTANCE="processing_system7_0" PORT="UART0_RX"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="O" MHS_INDEX="32" NAME="pwm_signal_out_wkillswitch_0_pwm_out_sm_pin" SIGNAME="pwm_signal_out_wkillswitch_0_pwm_out_sm">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="pwm_signal_out_wkillswitch_0" PORT="pwm_out_sm"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="O" MHS_INDEX="33" NAME="pwm_signal_out_wkillswitch_1_pwm_out_sm_pin" SIGNAME="pwm_signal_out_wkillswitch_1_pwm_out_sm">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="pwm_signal_out_wkillswitch_1" PORT="pwm_out_sm"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="O" MHS_INDEX="34" NAME="pwm_signal_out_wkillswitch_2_pwm_out_sm_pin" SIGNAME="pwm_signal_out_wkillswitch_2_pwm_out_sm">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="pwm_signal_out_wkillswitch_2" PORT="pwm_out_sm"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="O" MHS_INDEX="35" NAME="pwm_signal_out_wkillswitch_3_pwm_out_sm_pin" SIGNAME="pwm_signal_out_wkillswitch_3_pwm_out_sm">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="pwm_signal_out_wkillswitch_3" PORT="pwm_out_sm"/>
+      </CONNECTIONS>
+    </PORT>
+  </EXTERNALPORTS>
+
 </EDKSYSTEM>
\ No newline at end of file
diff --git a/quad/xps_projects/system/implementation/system_summary.html b/quad/xps_projects/system/implementation/system_summary.html
index b44d60b2f1877f4fab838c7ca46c3a8daa25a562..17fd5b717a39b8cd2780e7459993c2caca1aa427 100644
--- a/quad/xps_projects/system/implementation/system_summary.html
+++ b/quad/xps_projects/system/implementation/system_summary.html
@@ -2,7 +2,7 @@
 <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
 <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
-<TD ALIGN=CENTER COLSPAN='4'><B>Project Status (12/09/2017 - 18:06:46)</B></TD></TR>
+<TD ALIGN=CENTER COLSPAN='4'><B>Project Status (12/10/2017 - 19:00:59)</B></TD></TR>
 <TR ALIGN=LEFT>
 <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
 <TD>system.xmp</TD>
@@ -31,7 +31,7 @@
 <TR ALIGN=LEFT><TD><A HREF_DISABLED='/local/ucart/MicroCART/quad/xps_projects/system/platgen.log'>Platgen Log File</A></TD><TD>Sat Dec 9 17:33:28 2017</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/local/ucart/MicroCART/quad/xps_projects/system/__xps/ise/_xmsgs/platgen.xmsgs?&DataKey=Warning'>3 Warnings (3 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/local/ucart/MicroCART/quad/xps_projects/system/__xps/ise/_xmsgs/platgen.xmsgs?&DataKey=Info'>16 Infos (16 new)</A></TD></TR>
 <TR ALIGN=LEFT><TD>Simgen Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
 <TR ALIGN=LEFT><TD>BitInit Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/local/ucart/MicroCART/quad/xps_projects/system/system.log'>System Log File</A></TD><TD>Sat Dec 9 17:33:28 2017</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/local/ucart/MicroCART/quad/xps_projects/system/system.log'>System Log File</A></TD><TD>Sat Dec 9 18:08:44 2017</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
 </TABLE>
 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>XPS Synthesis Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=EDKSynthesisSumary"><B>[-]</B></a></TD></TR>
@@ -506,5 +506,5 @@
 </TABLE>
 
 
-<br><center><b>Date Generated:</b> 12/09/2017 - 18:06:46</center>
+<br><center><b>Date Generated:</b> 12/10/2017 - 19:00:59</center>
 </BODY></HTML>
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/.project b/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/.project
index 78e72aea4aa0127ca09735179024265291cc7d30..4b136bb878ba10d802df5910af23b0caf0789aac 100644
--- a/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/.project
+++ b/quad/xsdk_workspace_vivado/quad_wrapper_hw_platform_0/.project
@@ -11,7 +11,7 @@
 	</natures>
 	<filteredResources>
 		<filter>
-			<id>1512864278292</id>
+			<id>1512948894437</id>
 			<name></name>
 			<type>6</type>
 			<matcher>
@@ -20,7 +20,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1512864278296</id>
+			<id>1512948894441</id>
 			<name></name>
 			<type>6</type>
 			<matcher>
@@ -29,7 +29,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1512864278298</id>
+			<id>1512948894444</id>
 			<name></name>
 			<type>6</type>
 			<matcher>
diff --git a/quad/xsdk_workspace_vivado/real_quad/.cproject b/quad/xsdk_workspace_vivado/real_quad/.cproject
index 57f76856b0208ef5824dd1bc3f413b84b8f3c3cf..c758d82d890c5a9040937e963df1eb8873ae38a8 100644
--- a/quad/xsdk_workspace_vivado/real_quad/.cproject
+++ b/quad/xsdk_workspace_vivado/real_quad/.cproject
@@ -1,7 +1,5 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?>
-
-<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
 	<storageModule moduleId="org.eclipse.cdt.core.settings">
 		<cconfiguration id="xilinx.gnu.arm.exe.debug.980189137">
 			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.arm.exe.debug.980189137" moduleId="org.eclipse.cdt.core.settings" name="Debug">
@@ -16,7 +14,7 @@
 				</extensions>
 			</storageModule>
 			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="xilinx.gnu.arm.exe.debug.980189137" name="Debug" parent="xilinx.gnu.arm.exe.debug">
+				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="xilinx.gnu.arm.exe.debug.980189137" name="Debug" parent="xilinx.gnu.arm.exe.debug">
 					<folderInfo id="xilinx.gnu.arm.exe.debug.980189137." name="/" resourcePath="">
 						<toolChain id="xilinx.gnu.arm.exe.debug.toolchain.1195127676" name="Xilinx ARM GNU Toolchain" resourceTypeBasedDiscovery="true" superClass="xilinx.gnu.arm.exe.debug.toolchain">
 							<targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.arm" id="xilinx.arm.target.gnu.base.debug.2072264921" isAbstract="false" name="Debug Platform" superClass="xilinx.arm.target.gnu.base.debug"/>
@@ -53,12 +51,11 @@
 								<option id="xilinx.gnu.linker.inferred.swplatform.lpath.47881921" name="Software Platform Library Path" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
 									<listOptionValue builtIn="false" value="../../system_bsp/ps7_cortexa9_0/lib"/>
 								</option>
-								<option id="xilinx.gnu.linker.inferred.swplatform.flags.349145084" name="Software Platform Inferred Flags" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
-									<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
-								</option>
+								<option id="xilinx.gnu.linker.inferred.swplatform.flags.349145084" name="Software Platform Inferred Flags" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs"/>
 								<option id="xilinx.gnu.c.linker.option.lscript.972374298" name="Linker Script" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
 								<option id="xilinx.gnu.c.link.option.libs.1025826490" name="Libraries (-l)" superClass="xilinx.gnu.c.link.option.libs" valueType="libs">
 									<listOptionValue builtIn="false" value="m"/>
+									<listOptionValue builtIn="false" srcPrefixMapping="" srcRootPath="" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
 								</option>
 								<option id="xilinx.gnu.c.link.option.paths.1462160427" name="Library search path (-L)" superClass="xilinx.gnu.c.link.option.paths"/>
 								<inputType id="xilinx.gnu.linker.input.777404607" superClass="xilinx.gnu.linker.input">
@@ -99,7 +96,7 @@
 				</extensions>
 			</storageModule>
 			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="xilinx.gnu.arm.exe.release.255973624" name="Release" parent="xilinx.gnu.arm.exe.release">
+				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" id="xilinx.gnu.arm.exe.release.255973624" name="Release" parent="xilinx.gnu.arm.exe.release">
 					<folderInfo id="xilinx.gnu.arm.exe.release.255973624." name="/" resourcePath="">
 						<toolChain id="xilinx.gnu.arm.exe.release.toolchain.1375808537" name="Xilinx ARM GNU Toolchain" superClass="xilinx.gnu.arm.exe.release.toolchain">
 							<targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.arm" id="xilinx.arm.target.gnu.base.release.230721338" isAbstract="false" name="Release Platform" superClass="xilinx.arm.target.gnu.base.release"/>
@@ -176,10 +173,10 @@
 		<project id="modular_quad_pid.xilinx.gnu.arm.exe.832182557" name="Xilinx ARM Executable" projectType="xilinx.gnu.arm.exe"/>
 	</storageModule>
 	<storageModule moduleId="refreshScope" versionNumber="2">
-		<configuration configurationName="Release">
+		<configuration configurationName="Debug">
 			<resource resourceType="PROJECT" workspacePath="/modular_quad_pid"/>
 		</configuration>
-		<configuration configurationName="Debug">
+		<configuration configurationName="Release">
 			<resource resourceType="PROJECT" workspacePath="/modular_quad_pid"/>
 		</configuration>
 	</storageModule>
diff --git a/quad/xsdk_workspace_vivado/real_quad/.project b/quad/xsdk_workspace_vivado/real_quad/.project
index 131ce10c1d2d7578c4e9a5753019bd1f0e84592e..46c57bad4c94f61a2c45fb391561fdbf9eda08cc 100644
--- a/quad/xsdk_workspace_vivado/real_quad/.project
+++ b/quad/xsdk_workspace_vivado/real_quad/.project
@@ -4,7 +4,6 @@
 	<comment></comment>
 	<projects>
 		<project>system_bsp</project>
-		<project>system_hw_platform</project>
 	</projects>
 	<buildSpec>
 		<buildCommand>
@@ -53,7 +52,7 @@
 	</linkedResources>
 	<filteredResources>
 		<filter>
-			<id>1490997289335</id>
+			<id>1512949820706</id>
 			<name></name>
 			<type>10</type>
 			<matcher>
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo.c b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo.c
index df4cd13a3180ba7fe76c125cc8a72ce89e9aaa8c..43515c5d014b527198dec47bd835a4ce734bd474 100644
--- a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo.c
+++ b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo.c
@@ -64,15 +64,15 @@ struct TimerDriver create_zybo_global_timer() {
   global_timer.read = zybo_global_timer_read;
   return global_timer;
 }
-
-struct TimerDriver create_zybo_axi_timer() {
-  struct TimerDriver axi_timer;
-  axi_timer.state = NULL;
-  axi_timer.reset = zybo_axi_timer_reset;
-  axi_timer.restart = zybo_axi_timer_restart;
-  axi_timer.read = zybo_axi_timer_read;
-  return axi_timer;
-}
+//
+//struct TimerDriver create_zybo_axi_timer() {
+//  struct TimerDriver axi_timer;
+//  axi_timer.state = NULL;
+//  //axi_timer.reset = zybo_axi_timer_reset;
+//  axi_timer.restart = zybo_axi_timer_restart;
+//  axi_timer.read = zybo_axi_timer_read;
+//  return axi_timer;
+//}
 
 struct LEDDriver create_zybo_mio7_led() {
   struct LEDDriver mio7_led;
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo.h b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo.h
index 8f439cdf1872f1da5bcd0638d76a152f58c27f8f..d8738b71c248dd0b678837b3edac8e7d1d2b227f 100644
--- a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo.h
+++ b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo.h
@@ -5,7 +5,6 @@
 
 #include <sleep.h>
 #include <stdlib.h>
-#include <xtmrctr.h>
 #include <xgpiops.h>
 #include "xiicps.h"
 #include "xparameters.h"
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_axi_timer.c b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_axi_timer.c
deleted file mode 100644
index fa4bb05a6a5bb0bea2167446297a9a29c0b6b9ca..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_axi_timer.c
+++ /dev/null
@@ -1,22 +0,0 @@
-#include "hw_impl_zybo.h"
-
-#define PL_CLK_CNTS_PER_USEC 100
-
-int zybo_axi_timer_reset(struct TimerDriver *self) {
-  if (self->state == NULL) {
-    self->state = malloc(sizeof(XTmrCtr));
-  }
-  return XTmrCtr_Initialize(self->state, XPAR_AXI_TIMER_0_DEVICE_ID);
-}
-
-int zybo_axi_timer_restart(struct TimerDriver *self) {
-  XTmrCtr_Reset(self->state, 0);
-  XTmrCtr_Start(self->state, 0);
-  return 0;
-}
-
-int zybo_axi_timer_read(struct TimerDriver *self, u64 *us) {
-  // Returns the number of useconds
-  *us = XTmrCtr_GetValue(self->state, 0) / PL_CLK_CNTS_PER_USEC;
-  return 0;
-}
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_motor.c b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_motor.c
index 576c1ecaf353bf3caf7f0f63999ac500b8353a84..8e8e27ab70d1983c3dffeef7207516dc998e0aec 100644
--- a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_motor.c
+++ b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_motor.c
@@ -20,10 +20,10 @@ int zybo_motor_reset(struct MotorDriver *self) {
   }
   struct MotorDriverState *state = self->state;
 
-  state->outputs[0] = (int *) XPAR_PWM_SIGNAL_OUT_WKILLSWITCH_0_BASEADDR;
-  state->outputs[1] = (int *) XPAR_PWM_SIGNAL_OUT_WKILLSWITCH_1_BASEADDR;
-  state->outputs[2] = (int *) XPAR_PWM_SIGNAL_OUT_WKILLSWITCH_2_BASEADDR;
-  state->outputs[3] = (int *) XPAR_PWM_SIGNAL_OUT_WKILLSWITCH_3_BASEADDR;
+  state->outputs[0] = (int *) XPAR_PWM_SIGNAL_OUT_0_S_AXI_BASEADDR;
+  state->outputs[1] = (int *) XPAR_PWM_SIGNAL_OUT_1_S_AXI_BASEADDR;
+  state->outputs[2] = (int *) XPAR_PWM_SIGNAL_OUT_2_S_AXI_BASEADDR;
+  state->outputs[3] = (int *) XPAR_PWM_SIGNAL_OUT_3_S_AXI_BASEADDR;
 
   // Set period width of PWM pulse
   *(state->outputs[0]) = PERIOD_WIDTH;
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_rc_receiver.c b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_rc_receiver.c
index 63d6ab525b330789670b251008bbcbc7d863b0ad..391333b0a65cc7d60213930ae36a37f0e7fef786 100644
--- a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_rc_receiver.c
+++ b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_rc_receiver.c
@@ -21,12 +21,12 @@ int zybo_rc_receiver_reset(struct RCReceiverDriver *self) {
 
   // Save the addresses of the input PWM recorders
   struct RCReceiverDriverState *state = self->state;
-  state->channels[0] = (int *) XPAR_PWM_RECORDER_0_BASEADDR;
-  state->channels[1] = (int *) XPAR_PWM_RECORDER_1_BASEADDR;
-  state->channels[2] = (int *) XPAR_PWM_RECORDER_2_BASEADDR;
-  state->channels[3] = (int *) XPAR_PWM_RECORDER_3_BASEADDR;
-  state->channels[4] = (int *) XPAR_PWM_RECORDER_4_BASEADDR;
-  state->channels[5] = (int *) XPAR_PWM_RECORDER_5_BASEADDR;
+  state->channels[0] = (int *) XPAR_PWM_RECORDER_0_S_AXI_BASEADDR;
+  state->channels[1] = (int *) XPAR_PWM_RECORDER_1_S_AXI_BASEADDR;
+  state->channels[2] = (int *) XPAR_PWM_RECORDER_2_S_AXI_BASEADDR;
+  state->channels[3] = (int *) XPAR_PWM_RECORDER_3_S_AXI_BASEADDR;
+  state->channels[4] = (int *) XPAR_PWM_RECORDER_4_S_AXI_BASEADDR;
+  state->channels[5] = (int *) XPAR_PWM_RECORDER_5_S_AXI_BASEADDR;
   return 0;
 }
 
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_tests.c b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_tests.c
index a38e87306620ba54d308d61cd450cf7e817614cc..4b3942ea7bd62f4f65a1f2a1285b04995fd36494 100644
--- a/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_tests.c
+++ b/quad/xsdk_workspace_vivado/real_quad/src/hw_impl_zybo_tests.c
@@ -222,27 +222,27 @@ int test_zybo_motors() {
  * 4) Run main.c
  * 5) Observe MIO7 LED on board blinking at 1 second intervals.
  */
-int test_zybo_axi_timer() {
-  struct TimerDriver axi = create_zybo_axi_timer();
-  struct LEDDriver led = create_zybo_mio7_led();
-  axi.reset(&axi);
-  led.reset(&led);
-
-  unsigned long time;
-
-  while (1) {
-    axi.restart(&axi);
-    time = 0;
-    while (time < 1000000) {
-      axi.read(&axi, &time);
-    }
-    led.turn_off(&led);
-    while (time < 2000000) {
-      axi.read(&axi, &time);
-    }
-    led.turn_on(&led);
-  }
-}
+//int test_zybo_axi_timer() {
+//  //struct TimerDriver axi = create_zybo_axi_timer();
+//  struct LEDDriver led = create_zybo_mio7_led();
+//  //axi.reset(&axi);
+//  led.reset(&led);
+//
+//  unsigned long time;
+//
+//  while (1) {
+//    //axi.restart(&axi);
+//    time = 0;
+//    while (time < 1000000) {
+//      axi.read(&axi, &time);
+//    }
+//    led.turn_off(&led);
+//    while (time < 2000000) {
+//      axi.read(&axi, &time);
+//    }
+//    led.turn_on(&led);
+//  }
+//}
 
 /**
  * Test for the Global timer, using LEDDriver.
diff --git a/quad/xsdk_workspace_vivado/real_quad/src/main.c b/quad/xsdk_workspace_vivado/real_quad/src/main.c
index f6991aca7623d2a99bdba5eb5a048e424874b5ff..716a876a9602109397b7aeda3d9b9e8119da4b00 100644
--- a/quad/xsdk_workspace_vivado/real_quad/src/main.c
+++ b/quad/xsdk_workspace_vivado/real_quad/src/main.c
@@ -29,7 +29,7 @@ int setup_hardware(hardware_t *hardware) {
   hardware->comm = create_zybo_comm(&hardware->uart_0);
   hardware->gps = create_zybo_gps(&hardware->uart_1);
   hardware->global_timer = create_zybo_global_timer();
-  hardware->axi_timer = create_zybo_axi_timer();
+  //hardware->axi_timer = create_zybo_axi_timer();
   hardware->mio7_led = create_zybo_mio7_led();
   hardware->sys = create_zybo_system();
   hardware->i2c_0 = create_zybo_i2c(0);
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/.cproject b/quad/xsdk_workspace_vivado/real_quad_fresh/.cproject
new file mode 100644
index 0000000000000000000000000000000000000000..7977661867ca1f755351023b3914959b9e6bace1
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/real_quad_fresh/.cproject
@@ -0,0 +1,202 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="xilinx.gnu.arm.exe.debug.980189137">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.arm.exe.debug.980189137" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.xilinx.sdk.managedbuilder.XELF.arm" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="xilinx.gnu.arm.exe.debug.980189137" name="Debug" parent="xilinx.gnu.arm.exe.debug">
+					<folderInfo id="xilinx.gnu.arm.exe.debug.980189137." name="/" resourcePath="">
+						<toolChain id="xilinx.gnu.arm.exe.debug.toolchain.1195127676" name="Xilinx ARM GNU Toolchain" resourceTypeBasedDiscovery="true" superClass="xilinx.gnu.arm.exe.debug.toolchain">
+							<targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.arm" id="xilinx.arm.target.gnu.base.debug.2072264921" isAbstract="false" name="Debug Platform" superClass="xilinx.arm.target.gnu.base.debug"/>
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+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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+								<option id="xilinx.gnu.compiler.inferred.swplatform.includes.687694973" name="Software Platform Include Path" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
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+								</option>
+								<option id="xilinx.gnu.compiler.symbols.defined.1562495938" name="Defined symbols (-D)" superClass="xilinx.gnu.compiler.symbols.defined" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="NDEBUG=1"/>
+								</option>
+								<option id="xilinx.gnu.compiler.dircategory.includes.1873624761" name="Include Paths" superClass="xilinx.gnu.compiler.dircategory.includes" valueType="includePath">
+									<listOptionValue builtIn="false" value="../../system_bsp/ps7_cortexa9_0/include"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/real_quad/ext/computation_graph}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/real_quad/ext/quad_app}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/real_quad/ext/queue}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/real_quad/ext/commands}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/real_quad/ext/graph_blocks}&quot;"/>
+								</option>
+								<inputType id="xilinx.gnu.arm.c.compiler.input.846429887" name="C source files" superClass="xilinx.gnu.arm.c.compiler.input"/>
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+								<option id="xilinx.gnu.compiler.option.debugging.level.1485305325" name="Debug Level" superClass="xilinx.gnu.compiler.option.debugging.level" value="gnu.c.debugging.level.none" valueType="enumerated"/>
+								<option id="xilinx.gnu.compiler.inferred.swplatform.includes.2144106422" name="Software Platform Include Path" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
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+								<option id="xilinx.gnu.c.link.option.libs.962400757" name="Libraries (-l)" superClass="xilinx.gnu.c.link.option.libs" valueType="libs">
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+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC"/>
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+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="xilinx.gnu.arm.exe.release.255973624;xilinx.gnu.arm.exe.release.255973624.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC"/>
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+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMGCCManagedMakePerProjectProfileC"/>
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diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/.gitignore b/quad/xsdk_workspace_vivado/real_quad_fresh/.gitignore
new file mode 100644
index 0000000000000000000000000000000000000000..8274dfc9f03b3d46129a53606ca8ddd09c715e2f
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/real_quad_fresh/.gitignore
@@ -0,0 +1,7 @@
+*.o
+*.d
+*.elf
+*.size
+bootimage/
+Debug/
+Release/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/.project b/quad/xsdk_workspace_vivado/real_quad_fresh/.project
new file mode 100644
index 0000000000000000000000000000000000000000..3c4c0ec6929c3335780830cddcf2063c5218757f
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/real_quad_fresh/.project
@@ -0,0 +1,152 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>real_quad</name>
+	<comment></comment>
+	<projects>
+		<project>standalone_bsp_0</project>
+		<project>system_hw_platform</project>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>ext/commands</name>
+			<type>2</type>
+			<location>/local/ucart/MicroCART/quad/src/commands</location>
+		</link>
+		<link>
+			<name>ext/computation_graph</name>
+			<type>2</type>
+			<locationURI>QUAD_LOC/src/computation_graph</locationURI>
+		</link>
+		<link>
+			<name>ext/graph_blocks</name>
+			<type>2</type>
+			<location>/local/ucart/MicroCART/quad/src/graph_blocks</location>
+		</link>
+		<link>
+			<name>ext/quad_app</name>
+			<type>2</type>
+			<locationURI>QUAD_LOC/src/quad_app</locationURI>
+		</link>
+		<link>
+			<name>ext/queue</name>
+			<type>2</type>
+			<locationURI>QUAD_LOC/src/queue</locationURI>
+		</link>
+	</linkedResources>
+	<filteredResources>
+		<filter>
+			<id>1490997289335</id>
+			<name></name>
+			<type>10</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-obj</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>0</id>
+			<name>ext/computation_graph</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-*.c</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>0</id>
+			<name>ext/computation_graph</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-*.h</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>0</id>
+			<name>ext/computation_graph</name>
+			<type>10</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-*</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>0</id>
+			<name>ext/quad_app</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-*.c</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>0</id>
+			<name>ext/quad_app</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-*.h</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>0</id>
+			<name>ext/quad_app</name>
+			<type>10</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-*</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>0</id>
+			<name>ext/queue</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-*.c</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>0</id>
+			<name>ext/queue</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-*.h</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>0</id>
+			<name>ext/queue</name>
+			<type>10</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-*</arguments>
+			</matcher>
+		</filter>
+	</filteredResources>
+	<variableList>
+		<variable>
+			<name>QUAD_LOC</name>
+			<value>$%7BPARENT-1-WORKSPACE_LOC%7D</value>
+		</variable>
+	</variableList>
+</projectDescription>
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/.settings/org.eclipse.cdt.codan.core.prefs b/quad/xsdk_workspace_vivado/real_quad_fresh/.settings/org.eclipse.cdt.codan.core.prefs
new file mode 100644
index 0000000000000000000000000000000000000000..8e0550446a2bb045d01a9f8b73d47305f777665c
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/real_quad_fresh/.settings/org.eclipse.cdt.codan.core.prefs
@@ -0,0 +1,34 @@
+eclipse.preferences.version=1
+org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},implicit\=>false}
+org.eclipse.cdt.codan.checkers.errreturnvalue.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.checkers.noreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},implicit\=>false}
+org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},no_break_comment\=>"no break",last_case_param\=>false,empty_case_param\=>false}
+org.eclipse.cdt.codan.internal.checkers.CatchByReference.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},unknown\=>false,exceptions\=>()}
+org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},skip\=>true}
+org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},pattern\=>"^[a-z]",macro\=>true,exceptions\=>()}
+org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.OverloadProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true,exceptions\=>()}
+org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},paramNot\=>false}
+org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},else\=>false,afterelse\=>false}
+org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true}
+org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true}
+org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true,exceptions\=>("@(\#)","$Id")}
+org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/README.md b/quad/xsdk_workspace_vivado/real_quad_fresh/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..88089fe73a20d66069f58a28385db78db8ebed51
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/real_quad_fresh/README.md
@@ -0,0 +1,10 @@
+# The Real Quad
+_It is real, because it flies._
+
+Welcome to the most lame README in MicroCART. Everything we are about to say
+has already been said elsewhere, including [Our quad folder README][1], [xsdk_workspace README][2], and [HOW_TO_USE_XSDK markdown][3].
+So we aren't saying it here. Hence, this README is pretty empty. Hence... lame.
+
+[1]: ../README.md
+[2]: ../../README.md
+[3]: ../../doc/how_to_use_XSDK.md
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/ext/__CAUTION__.md b/quad/xsdk_workspace_vivado/real_quad_fresh/ext/__CAUTION__.md
new file mode 100644
index 0000000000000000000000000000000000000000..6f7e2a00feb6d7083997b71389dcad6b36a0d616
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/real_quad_fresh/ext/__CAUTION__.md
@@ -0,0 +1,12 @@
+****************************************
+  Do not edit files in this directory!
+****************************************
+
+The fine print
+----
+
+Files in this directory are simlinked to external libraries. They exist here
+purely to help fascilitate the build process and permit debugging of those
+libraries within XSDK. Editing them here might build within XSDK, but it might
+break in its original context. Hence, don't edit these files within XSDK. Edit
+them within a workflow that uses the Makefile in the top-level quad folder.
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo.c
new file mode 100644
index 0000000000000000000000000000000000000000..fdc34f8acac210c314bd2a749b569533511c8567
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo.c
@@ -0,0 +1,116 @@
+#include "hw_impl_zybo.h"
+
+struct UARTDriver create_zybo_uart(int devId) {
+  struct UARTDriver uart;
+  uart.state = malloc(sizeof(struct ZyboUARTState));
+  struct ZyboUARTState *state = uart.state;
+  state->inst = malloc(sizeof(XUartPs));
+  state->queue = queue_malloc(MAX_UART_BUFFER_SIZE);
+  state->devId = devId;
+
+  uart.reset = zybo_uart_reset;
+  uart.write = zybo_uart_write;
+  uart.read = zybo_uart_read;
+  return uart;
+}
+
+struct GPSDriver create_zybo_gps(struct UARTDriver *uart) {
+  struct GPSDriver gps;
+  gps.uart = uart;
+  gps.reset = zybo_gps_reset;
+  gps.read = zybo_gps_read;
+  return gps;
+}
+
+struct CommDriver create_zybo_comm(struct UARTDriver *uart) {
+  struct CommDriver comm;
+  comm.uart = uart;
+  return comm;
+}
+
+struct MotorDriver create_zybo_motors() {
+  struct MotorDriver motors;
+  motors.state = NULL;
+  motors.reset = zybo_motor_reset;
+  motors.write = zybo_motor_write;
+  return motors;
+}
+
+struct RCReceiverDriver create_zybo_rc_receiver() {
+  struct RCReceiverDriver rc_receiver;
+  rc_receiver.state = NULL;
+  rc_receiver.reset = zybo_rc_receiver_reset;
+  rc_receiver.read = zybo_rc_receiver_read;
+  return rc_receiver;
+}
+
+struct I2CDriver create_zybo_i2c(int busId) {
+  struct I2CDriver i2c;
+  i2c.state = malloc(sizeof(struct ZyboI2CState));
+  struct ZyboI2CState *state = i2c.state;
+  state->inst = malloc(sizeof(XIicPs));
+  state->busId = busId;
+  i2c.reset = zybo_i2c_reset;
+  i2c.write = zybo_i2c_write;
+  i2c.read = zybo_i2c_read;
+  return i2c;
+}
+
+struct TimerDriver create_zybo_global_timer() {
+  struct TimerDriver global_timer;
+  global_timer.state = NULL;
+  global_timer.reset = zybo_global_timer_reset;
+  global_timer.restart = zybo_global_timer_restart;
+  global_timer.read = zybo_global_timer_read;
+  return global_timer;
+}
+
+//struct TimerDriver create_zybo_axi_timer() {
+//  struct TimerDriver axi_timer;
+//  axi_timer.state = NULL;
+//  axi_timer.reset = zybo_axi_timer_reset;
+//  axi_timer.restart = zybo_axi_timer_restart;
+//  axi_timer.read = zybo_axi_timer_read;
+//  return axi_timer;
+//}
+
+struct LEDDriver create_zybo_mio7_led() {
+  struct LEDDriver mio7_led;
+  mio7_led.state = NULL;
+  mio7_led.reset = zybo_mio7_led_reset;
+  mio7_led.turn_on = zybo_mio7_led_turn_on;
+  mio7_led.turn_off = zybo_mio7_led_turn_off;
+  return mio7_led;
+}
+
+struct SystemDriver create_zybo_system() {
+  struct SystemDriver sys;
+  sys.state = NULL;
+  sys.reset = zybo_system_reset;
+  sys.sleep = zybo_system_sleep;
+  return sys;
+}
+
+struct IMUDriver create_zybo_imu(struct I2CDriver *i2c) {
+  struct IMUDriver imu;
+  imu.i2c = i2c;
+  imu.reset = zybo_imu_reset;
+  imu.read = zybo_imu_read;
+  return imu;
+}
+
+struct LidarDriver create_zybo_lidar(struct I2CDriver *i2c) {
+  struct LidarDriver lidar;
+  lidar.i2c = i2c;
+  lidar.reset = zybo_lidar_reset;
+  lidar.read = zybo_lidar_read;
+  return lidar;
+}
+
+struct OpticalFlowDriver create_zybo_optical_flow(struct I2CDriver *i2c) {
+  struct OpticalFlowDriver of;
+  of.i2c = i2c;
+  of.reset = zybo_optical_flow_reset;
+  of.read = zybo_optical_flow_read;
+  return of;
+}
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo.h b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo.h
new file mode 100644
index 0000000000000000000000000000000000000000..d8738b71c248dd0b678837b3edac8e7d1d2b227f
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo.h
@@ -0,0 +1,105 @@
+#ifndef HW_IMPL_ZYBO
+#define HW_IMPL_ZYBO
+
+#include "hw_iface.h"
+
+#include <sleep.h>
+#include <stdlib.h>
+#include <xgpiops.h>
+#include "xiicps.h"
+#include "xparameters.h"
+#include "xgpiops.h"
+#include "xil_types.h"
+#include "xscugic.h"
+#include "xtime_l.h"
+#include "xuartps.h"
+#include "queue.h"
+#include "platform.h"
+#include "sleep.h"
+#include "type_def.h"
+
+// Ideally, these defines would only be in the optical flow file, but
+// i2c needs it for a certain hack
+#define PX4FLOW_DEVICE_ADDR			0x42
+#define PX4FLOW_QUAL_MIN			(100)
+
+#define MAX_UART_BUFFER_SIZE 2048
+
+struct ZyboI2CState {
+  XIicPs *inst;
+  int busId;
+};
+
+struct ZyboUARTState {
+  struct Queue *queue;
+  XUartPs *inst;
+  XScuGic xscugic;
+  int devId;
+};
+
+int zybo_uart_reset(struct UARTDriver *self);
+int zybo_uart_write(struct UARTDriver *self, unsigned char c);
+int zybo_uart_read(struct UARTDriver *self, unsigned char *c);
+
+int zybo_motor_reset(struct MotorDriver *self);
+int zybo_motor_write(struct MotorDriver *self, unsigned int channel, float magnitude);
+
+int zybo_rc_receiver_reset(struct RCReceiverDriver *self);
+int zybo_rc_receiver_read(struct RCReceiverDriver *self, unsigned int channel, float *magnitude);
+
+int zybo_i2c_reset(struct I2CDriver *self);
+int zybo_i2c_write(struct I2CDriver *self,
+                   unsigned short device_addr,
+                   unsigned char *data,
+                   unsigned int length);
+int zybo_i2c_read(struct I2CDriver *self,
+                  unsigned short device_addr,
+                  unsigned char *buff,
+                  unsigned int length);
+
+int zybo_global_timer_reset(struct TimerDriver *self);
+int zybo_global_timer_restart(struct TimerDriver *self);
+int zybo_global_timer_read(struct TimerDriver *self, u64 *us);
+
+int zybo_axi_timer_reset(struct TimerDriver *self);
+int zybo_axi_timer_restart(struct TimerDriver *self);
+int zybo_axi_timer_read(struct TimerDriver *self, u64 *us);
+
+int zybo_mio7_led_reset(struct LEDDriver *self);
+int zybo_mio7_led_turn_on(struct LEDDriver *self);
+int zybo_mio7_led_turn_off(struct LEDDriver *self);
+
+int zybo_system_reset(struct SystemDriver *self);
+int zybo_system_sleep(struct SystemDriver *self, unsigned long us);
+
+int zybo_imu_reset(struct IMUDriver *self, struct gam *gam);
+int zybo_imu_read(struct IMUDriver *self, struct gam *gam);
+
+int zybo_lidar_reset(struct LidarDriver *self, struct lidar *lidar);
+int zybo_lidar_read(struct LidarDriver *self, struct lidar *lidar);
+
+int zybo_optical_flow_reset(struct OpticalFlowDriver *self, struct px4flow *of);
+int zybo_optical_flow_read(struct OpticalFlowDriver *self, struct px4flow *of);
+
+int zybo_gps_reset(struct GPSDriver *self, gps_t *gps);
+int zybo_gps_read(struct GPSDriver *self, gps_t *gps);
+
+struct UARTDriver create_zybo_uart(int devId);
+struct CommDriver create_zybo_comm(struct UARTDriver *uart);
+struct GPSDriver create_zybo_gps(struct UARTDriver *uart);
+struct MotorDriver create_zybo_motors();
+struct RCReceiverDriver create_zybo_rc_receiver();
+struct I2CDriver create_zybo_i2c(int busId);
+struct TimerDriver create_zybo_global_timer();
+struct TimerDriver create_zybo_axi_timer();
+struct LEDDriver create_zybo_mio7_led();
+struct SystemDriver create_zybo_system();
+struct IMUDriver create_zybo_imu(struct I2CDriver *i2c);
+struct LidarDriver create_zybo_lidar(struct I2CDriver *i2c);
+struct OpticalFlowDriver create_zybo_optical_flow(struct I2CDriver *i2c);
+
+int test_zybo_i2c();
+int test_zybo_mio7_led_and_system();
+int test_zybo_rc_receivers();
+
+#endif
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_global_timer.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_global_timer.c
new file mode 100644
index 0000000000000000000000000000000000000000..c1024a62f57e9e16eda073268e991012973ec35b
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_global_timer.c
@@ -0,0 +1,18 @@
+#include "hw_impl_zybo.h"
+
+int zybo_global_timer_reset(struct TimerDriver *self) {
+  // Nothing to initialize
+  return 0;
+}
+
+int zybo_global_timer_restart(struct TimerDriver *self) {
+  XTime_SetTime(0);
+  return 0;
+}
+
+int zybo_global_timer_read(struct TimerDriver *self, u64 *us) {
+  XTime time;
+  XTime_GetTime(&time);
+  *us = ((u64)time * 1000000) / COUNTS_PER_SECOND; // (ticks)(1000000us/s)(s/ticks)
+  return 0;
+}
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_gps.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_gps.c
new file mode 100644
index 0000000000000000000000000000000000000000..ff495afdbc2a597e3e2ca9ba89343cefeee6ed09
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_gps.c
@@ -0,0 +1,12 @@
+#include "hw_iface.h"
+#include "hw_impl_zybo.h"
+
+int zybo_gps_reset(struct GPSDriver *self, gps_t *gps) {
+  // TODO
+  return -1;
+}
+
+int zybo_gps_read(struct GPSDriver *self, gps_t *gps) {
+  // TODO
+  return -1;
+}
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_i2c.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_i2c.c
new file mode 100644
index 0000000000000000000000000000000000000000..751ae4ccf5bbc741def8cea9ea0e555be8f230f0
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_i2c.c
@@ -0,0 +1,485 @@
+#include "hw_impl_zybo.h"
+#include "xiicps.h"
+// System configuration registers
+// (Please see Appendix B: System Level Control Registers in the Zybo TRM)
+#define IIC_SYSTEM_CONTROLLER_RESET_REG_ADDR 	(0xF8000224)
+#define IO_CLK_CONTROL_REG_ADDR 				(0xF800012C)
+
+// Error code could be returned on an iic read if the watchdog timer triggers
+#define IIC_RX_TIMEOUT_FAILURE (-88)
+/*
+// IIC0 Registers
+#define IIC0_CONTROL_REG_ADDR 		(0xE0004000)
+#define IIC0_STATUS_REG_ADDR 		(0xE0004004)
+#define IIC0_SLAVE_ADDR_REG 		(0xE0004008)
+#define IIC0_DATA_REG_ADDR 			(0xE000400C)
+#define IIC0_INTR_STATUS_REG_ADDR 	(0xE0004010)
+#define IIC0_TRANFER_SIZE_REG_ADDR	(0xE0004014)
+#define IIC0_INTR_EN			    (0xE0004024)
+#define IIC0_TIMEOUT_REG_ADDR 		(0xE000401C)
+*/
+//Interrupt Status Register Masks
+#define ARB_LOST       (0x200)
+#define RX_UNF          (0x80)
+#define TX_OVF          (0x40)
+#define RX_OVF          (0x20)
+#define SLV_RDY         (0x10)
+#define TIME_OUT        (0x08)
+#define NACK      		(0x04)
+#define MORE_DAT 	    (0x02)
+#define TRANS_COMPLETE 	(0x01)
+
+#define WRITE_INTR_MASK (ARB_LOST | TIME_OUT | RX_OVF | TX_OVF | NACK)
+#define READ_INTR_MASK (ARB_LOST | TIME_OUT | RX_OVF | RX_UNF | NACK)
+
+#define IO_CLK_CONTROL_REG_ADDR	(0xF800012C)
+#define I2C0_CPU_1XCLKACT	(0x00040000)
+#define I2C1_CPU_1XCLKACT	(0x00080000)
+
+int XIicPs_MasterSendPolled_ours(XIicPs *InstancePtr, u8 *MsgPtr,
+				 int ByteCount, u16 SlaveAddr);
+int XIicPs_MasterRecvPolled_ours(XIicPs *InstancePtr, u8 *MsgPtr,
+				int ByteCount, u16 SlaveAddr);
+int XIicPs_SetupMaster(XIicPs *InstancePtr, int Role);
+
+int zybo_i2c_reset(struct I2CDriver *self) {
+  // ensure all required memory is allocated
+  struct ZyboI2CState *state = self->state;
+  if (state == NULL) return -1;
+  if (state->inst == NULL) return -1;
+  if (state->busId > 1) return -1;
+  int i2cID = state->busId;
+  XIicPs *inst = state->inst;
+
+  //Make sure CPU_1x clk is enabled fostatusr I2C controller
+  u16 *aper_ctrl = (u16 *) IO_CLK_CONTROL_REG_ADDR;
+  u32 aper_mask = (i2cID == 0) ? (I2C0_CPU_1XCLKACT) : (I2C1_CPU_1XCLKACT);
+
+  if (*aper_ctrl & aper_mask){
+    xil_printf("CPU_1x is set to I2C0\r\n");
+  }
+
+  else {
+    xil_printf("CPU_1x is not set to I2C..Setting now\r\n");
+    *aper_ctrl |= aper_mask;
+  }
+
+  // Look up
+  XIicPs_Config *i2c_config = XIicPs_LookupConfig(i2cID);
+  XStatus status = XIicPs_CfgInitialize(inst, i2c_config, i2c_config->BaseAddress);
+
+  // Check if initialization was successful
+  if(status != XST_SUCCESS){
+    return -1;
+  }
+
+  // Reset the controller and set the clock to 400kHz
+  XIicPs_Reset(inst);
+  XIicPs_SetSClk(inst, 400000);
+
+  return 0;
+}
+
+int zybo_i2c_write(struct I2CDriver *self,
+                   unsigned short device_addr,
+                   unsigned char *data,
+                   unsigned int length) {
+  struct ZyboI2CState *state = self->state;
+  XIicPs *inst = state->inst;
+  if (device_addr == PX4FLOW_DEVICE_ADDR) {
+	  // If we are sending a request to optical flow, drop down to 100kHz
+	  XIicPs_SetSClk(inst, 100000);
+  }
+  int error = XIicPs_MasterSendPolled_ours(inst, data, length, device_addr);
+  if (device_addr == PX4FLOW_DEVICE_ADDR) {
+	  // Put it back to 400kHz
+	  XIicPs_SetSClk(inst, 400000);
+  }
+  usleep(5);
+  return error;
+}
+
+int zybo_i2c_read(struct I2CDriver *self,
+                  unsigned short device_addr,
+                  unsigned char *buff,
+                  unsigned int length) {
+  struct ZyboI2CState *state = self->state;
+  XIicPs *inst = state->inst;
+  if (device_addr == PX4FLOW_DEVICE_ADDR) {
+	  // If we are sending a request to optical flow, drop down to 100kHz
+	  XIicPs_SetSClk(inst, 100000);
+  }
+  int error = XIicPs_MasterRecvPolled_ours(inst, buff, length, device_addr);
+  if (device_addr == PX4FLOW_DEVICE_ADDR) {
+	  // Put it back to 400kHz
+	  XIicPs_SetSClk(inst, 400000);
+  }
+  usleep(5);
+  return error;
+}
+
+/*****************************************************************************/
+/**
+* NOTE to MicroCART: This function is originally from the Xilinx library,
+* but we noticed that the original function didn't check for a NACK, which
+* would cause the original polling function to enter an infinite loop in the
+* event of a NACK. Notice that we have added that NACK check at the final
+* while loop of this function.
+*
+*
+* This function initiates a polled mode send in master mode.
+*u16 i2cID
+* It sends data to the FIFO and waits for the slave to pick them up.
+* If slave fails to remove data from FIFO, the send fails with
+* time out.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the send buffer.
+* @param	ByteCount is the number of bytes to be sent.
+* @param	SlaveAddr is the address of the slave we are sending to.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if timed out.
+*
+* @note		This send routine is for polled mode transfer only.
+*
+****************************************************************************/
+int XIicPs_MasterSendPolled_ours(XIicPs *InstancePtr, u8 *MsgPtr,
+		 int ByteCount, u16 SlaveAddr)
+{
+	u32 IntrStatusReg;
+	u32 StatusReg;
+	u32 BaseAddr;
+	u32 Intrs;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->SendBufferPtr = MsgPtr;
+	InstancePtr->SendByteCount = ByteCount;
+
+	XIicPs_SetupMaster(InstancePtr, SENDING_ROLE);
+
+	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
+
+	/*
+	 * Intrs keeps all the error-related interrupts.
+	 */
+	Intrs = XIICPS_IXR_ARB_LOST_MASK | XIICPS_IXR_TX_OVR_MASK |
+			XIICPS_IXR_TO_MASK | XIICPS_IXR_NACK_MASK;
+
+	/*
+	 * Clear the interrupt status register before use it to monitor.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Transmit first FIFO full of data.
+	 */
+	TransmitFifoFill(InstancePtr);
+
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+
+	/*
+	 * Continue sending as long as there is more data and
+	 * there are no errors.
+	 */
+	while ((InstancePtr->SendByteCount > 0) &&
+		((IntrStatusReg & Intrs) == 0)) {
+		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+		/*
+		 * Wait until transmit FIFO is empty.
+		 */
+		if ((StatusReg & XIICPS_SR_TXDV_MASK) != 0) {
+			IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+					XIICPS_ISR_OFFSET);
+			continue;
+		}
+
+		/*
+		 * Send more data out through transmit FIFO.
+		 */
+		TransmitFifoFill(InstancePtr);
+	}
+
+	/*
+	 * Check for completion of transfer.
+	 */
+	// NOTE for MicroCART: Corrected function. Original left for reference.
+//	while ((XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET) &
+//		XIICPS_IXR_COMP_MASK) != XIICPS_IXR_COMP_MASK);
+	while (!(IntrStatusReg & (Intrs | XIICPS_IXR_COMP_MASK))) {
+		IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	}
+
+	/*
+	 * If there is an error, tell the caller.
+	 */
+	if (IntrStatusReg & Intrs) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+static XTime get_time() {
+    XTime time;
+    XTime_GetTime(&time);
+    u64 us = (u64)time * (1000000 / COUNTS_PER_SECOND); // (ticks)(1000000us/s)(s/ticks)
+    return us;
+}
+
+/*****************************************************************************/
+/**
+* This function initiates a polled mode receive in master mode.
+*
+* It repeatedly sets the transfer size register so the slave can
+* send data to us. It polls the data register for data to come in.
+* If slave fails to send us data, it fails with time out.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the receive buffer.
+* @param	ByteCount is the number of bytes to be received.
+* @param	SlaveAddr is the address of the slave we are receiving from.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if timed out.
+*
+* @note		This receive routine is for polled mode transfer only.
+*
+****************************************************************************/
+int XIicPs_MasterRecvPolled_ours(XIicPs *InstancePtr, u8 *MsgPtr,
+				int ByteCount, u16 SlaveAddr)
+{
+	u32 IntrStatusReg;
+	u32 Intrs;
+	u32 StatusReg;
+	u32 BaseAddr;
+	int BytesToRecv;
+	int BytesToRead;
+	int TransSize;
+	int Tmp;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->RecvBufferPtr = MsgPtr;
+	InstancePtr->RecvByteCount = ByteCount;
+
+	XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
+
+	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
+
+	/*
+	 * Intrs keeps all the error-related interrupts.
+	 */
+	Intrs = XIICPS_IXR_ARB_LOST_MASK | XIICPS_IXR_RX_OVR_MASK |
+			XIICPS_IXR_RX_UNF_MASK | XIICPS_IXR_TO_MASK |
+			XIICPS_IXR_NACK_MASK;
+
+	/*
+	 * Clear the interrupt status register before use it to monitor.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Set up the transfer size register so the slave knows how much
+	 * to send to us.
+	 */
+	if (ByteCount > XIICPS_FIFO_DEPTH) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
+			 XIICPS_FIFO_DEPTH);
+	}else {
+		XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
+			 ByteCount);
+	}
+
+/* <--- MicroCART additions (iic watchdog timer hack) ---> */
+	u32 iic_freq = XIicPs_GetSClk(InstancePtr);
+	// (1000000 * 9 / iic_freq) is the number of microseconds required to send 1 byte of data
+	// Using 5 times as an upper bound
+	u32 max_usec_per_byte = 5 * 1000000 * 9 / iic_freq;
+	u64 start_time = get_time();
+/* <--- End hack ---> */
+
+	/*
+	 * Pull the interrupt status register to find the errors.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	while ((InstancePtr->RecvByteCount > 0) &&
+			((IntrStatusReg & Intrs) == 0) && !(IntrStatusReg & XIICPS_IXR_COMP_MASK)) {
+/* <--- MicroCART additions (iic watchdog timer hack) ---> */
+		u64 usec_passed = get_time() - start_time;
+		// Add 1 so it has a chance to read
+		if (usec_passed > max_usec_per_byte * (1 + ByteCount - InstancePtr->RecvByteCount)) {
+			return IIC_RX_TIMEOUT_FAILURE;
+		}
+/* <--- End hack ---> */
+		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+		/*
+		 * If there is no data in the FIFO, check the interrupt
+		 * status register for error, and continue.
+		 */
+		if ((StatusReg & XIICPS_SR_RXDV_MASK) == 0) {
+			IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+					XIICPS_ISR_OFFSET);
+			continue;
+		}
+
+		/*
+		 * The transfer size register shows how much more data slave
+		 * needs to send to us.
+		 */
+		TransSize = XIicPs_ReadReg(BaseAddr,
+		XIICPS_TRANS_SIZE_OFFSET);
+
+		BytesToRead = InstancePtr->RecvByteCount;
+
+		/*
+		 * If expected number of bytes is greater than FIFO size,
+		 * the master needs to wait for data comes in and set the
+		 * transfer size register for slave to send more.
+		 */
+		if (InstancePtr->RecvByteCount > XIICPS_FIFO_DEPTH) {
+			/* wait slave to send data */
+			while ((TransSize > 2) &&
+				((IntrStatusReg & Intrs) == 0)) {
+				TransSize = XIicPs_ReadReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET);
+				IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+							XIICPS_ISR_OFFSET);
+			}
+
+			/*
+			 * If timeout happened, it is an error.
+			 */
+			if (IntrStatusReg & XIICPS_IXR_TO_MASK) {
+				return XST_FAILURE;
+			}
+			TransSize = XIicPs_ReadReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET);
+
+			/*
+			 * Take trans size into account of how many more should
+			 * be received.
+			 */
+			BytesToRecv = InstancePtr->RecvByteCount -
+					XIICPS_FIFO_DEPTH + TransSize;
+
+			/* Tell slave to send more to us */
+			if (BytesToRecv > XIICPS_FIFO_DEPTH) {
+				XIicPs_WriteReg(BaseAddr,
+					XIICPS_TRANS_SIZE_OFFSET,
+					XIICPS_FIFO_DEPTH);
+			} else{
+				XIicPs_WriteReg(BaseAddr,
+					XIICPS_TRANS_SIZE_OFFSET, BytesToRecv);
+			}
+
+			BytesToRead = XIICPS_FIFO_DEPTH - TransSize;
+		}
+
+		Tmp = 0;
+		IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+		while ((Tmp < BytesToRead) &&
+				((IntrStatusReg & Intrs) == 0)) {
+			StatusReg = XIicPs_ReadReg(BaseAddr,
+					XIICPS_SR_OFFSET);
+			IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+					XIICPS_ISR_OFFSET);
+
+			if ((StatusReg & XIICPS_SR_RXDV_MASK) == 0) {
+				/* No data in fifo */
+				continue;
+			}
+			XIicPs_RecvByte(InstancePtr);
+			Tmp ++;
+		}
+	}
+
+	if ((IntrStatusReg & Intrs) || InstancePtr->RecvByteCount > 0) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/*
+* NOTE to MicroCART: This function is required by the send polling method above,
+* but it was originally static, so we had to copy it word-for-word here.
+*
+* This function prepares a device to transfers as a master.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @param	Role specifies whether the device is sending or receiving.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if bus is busy.
+*
+* @note		Interrupts are always disabled, device which needs to use
+*		interrupts needs to setup interrupts after this call.
+*
+****************************************************************************/
+int XIicPs_SetupMaster(XIicPs *InstancePtr, int Role)
+{
+	u32 ControlReg;
+	u32 BaseAddr;
+	u32 EnabledIntr = 0x0;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	ControlReg = XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET);
+
+
+	/*
+	 * Only check if bus is busy when repeated start option is not set.
+	 */
+	if ((ControlReg & XIICPS_CR_HOLD_MASK) == 0) {
+		if (XIicPs_BusIsBusy(InstancePtr)) {
+			return XST_FAILURE;
+		}
+	}
+
+	/*
+	 * Set up master, AckEn, nea and also clear fifo.
+	 */
+	ControlReg |= XIICPS_CR_ACKEN_MASK | XIICPS_CR_CLR_FIFO_MASK |
+		 	XIICPS_CR_NEA_MASK | XIICPS_CR_MS_MASK;
+
+	if (Role == RECVING_ROLE) {
+		ControlReg |= XIICPS_CR_RD_WR_MASK;
+		EnabledIntr = XIICPS_IXR_DATA_MASK |XIICPS_IXR_RX_OVR_MASK;
+	}else {
+		ControlReg &= ~XIICPS_CR_RD_WR_MASK;
+	}
+	EnabledIntr |= XIICPS_IXR_COMP_MASK | XIICPS_IXR_ARB_LOST_MASK;
+
+	XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, ControlReg);
+
+	XIicPs_DisableAllInterrupts(BaseAddr);
+
+	return XST_SUCCESS;
+}
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_imu.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_imu.c
new file mode 100644
index 0000000000000000000000000000000000000000..31b68f49d66c93896cb02f9f17afa4fe37f4cb34
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_imu.c
@@ -0,0 +1,265 @@
+#include "hw_iface.h"
+#include "hw_impl_zybo.h"
+#include "type_def.h"
+
+#include <string.h>
+
+#define MPU9150_DEVICE_ADDR 		0b01101000
+#define MPU9150_COMPASS_ADDR 		0x0C
+
+#define ACCEL_GYRO_READ_SIZE 		14		//Bytes
+#define ACCEL_GYRO_BASE_ADDR		0x3B	//Starting register address
+
+#define MAG_READ_SIZE 				6
+#define MAG_BASE_ADDR 				0x03
+
+#define MAG_DRDY_TIMEOUT			(10)
+
+#define RAD_TO_DEG 57.29578
+#define DEG_TO_RAD 0.0174533
+
+// Array indicies when reading from ACCEL_GYRO_BASE_ADDR
+#define ACC_X_H 0
+#define ACC_X_L 1
+#define ACC_Y_H 2
+#define ACC_Y_L 3
+#define ACC_Z_H 4
+#define ACC_Z_L 5
+
+#define GYR_X_H 8
+#define GYR_X_L 9
+#define GYR_Y_H 10
+#define GYR_Y_L 11
+#define GYR_Z_H 12
+#define GYR_Z_L 13
+
+#define MAG_X_L 0
+#define MAG_X_H 1
+#define MAG_Y_L 2
+#define MAG_Y_H 3
+#define MAG_Z_L 4
+#define MAG_Z_H 5
+
+// Gyro is configured for +/-2000dps
+// Sensitivity gain is based off MPU9150 datasheet (pg. 11)
+#define GYRO_SENS 16.4
+
+#define GYRO_X_BIAS	0.005f
+#define GYRO_Y_BIAS	-0.014f
+#define GYRO_Z_BIAS	0.0534//0.0541f
+
+#define ACCEL_X_BIAS	0.023f
+#define ACCEL_Y_BIAS	0.009f
+#define ACCEL_Z_BIAS	0.0686f
+
+int mpu9150_write(struct I2CDriver *i2c, u8 register_addr, u8 data);
+int mpu9150_read(struct I2CDriver *i2c, u8* recv_buffer, u8 register_addr, int size);
+
+int mpu9150_calc_mag_sensitivity(struct IMUDriver *self, gam_t *gam);
+int mpu9150_read_mag(struct IMUDriver *self, gam_t* gam);
+int mpu9150_read_gyro_accel(gam_t* gam);
+
+int zybo_imu_reset(struct IMUDriver *self, gam_t *gam) {
+  memset(gam, 0, sizeof(gam_t));
+
+  struct I2CDriver *i2c = self->i2c;
+
+  // Device Reset & Wake up
+  mpu9150_write(i2c, 0x6B, 0x80);
+  usleep(5000);
+
+  // Set clock reference to Z Gyro
+  mpu9150_write(i2c, 0x6B, 0x03);
+  // Configure Digital Low/High Pass filter
+  mpu9150_write(i2c, 0x1A,0x03); // Level 3 low pass on gyroscope
+
+  // Configure Gyro to 2000dps, Accel. to +/-8G
+  mpu9150_write(i2c, 0x1B, 0x18);
+  mpu9150_write(i2c, 0x1C, 0x10);
+
+  // Enable I2C bypass for AUX I2C (Magnetometer)
+  mpu9150_write(i2c, 0x37, 0x02);
+
+  usleep(100000);
+
+  //Calculate magnetometer sensitivities
+  mpu9150_calc_mag_sensitivity(self, gam);
+
+  usleep(10000);
+
+  //Enable single measurement mode
+  mpu9150_write(i2c, 0x0A, 0x00);
+  mpu9150_write(i2c, 0x0A, 0x01);
+
+  int i;
+
+  // Do about 20 reads to warm up the device
+  for(i=0; i < 20; ++i){
+    self->read(self, gam);
+    usleep(1000);
+  }
+
+  return 0;
+}
+
+int mpu9150_calc_mag_sensitivity(struct IMUDriver *self, gam_t *gam) {
+	u8 buf[3];
+	u8 ASAX, ASAY, ASAZ;
+
+	// Quickly read from the factory ROM to get correction coefficents
+	int status = mpu9150_write(self->i2c, 0x0A, 0x0F);
+	if(status != 0) {
+		return status;
+	}
+
+	usleep(10000);
+
+	// Read raw adjustment values
+	status = mpu9150_read(self->i2c, buf, 0x10,3);
+	if(status != 0) {
+		return status;
+	}
+	ASAX = buf[0];
+	ASAY = buf[1];
+	ASAZ = buf[2];
+
+	// Set the correction coefficients
+	gam->magX_correction = (ASAX-128)*0.5/128 + 1;
+	gam->magY_correction = (ASAY-128)*0.5/128 + 1;
+	gam->magZ_correction = (ASAZ-128)*0.5/128 + 1;
+
+	return 0;
+}
+
+int zybo_imu_read(struct IMUDriver *self, gam_t *gam) {
+  struct I2CDriver *i2c = self->i2c;
+  i16 raw_accel_x, raw_accel_y, raw_accel_z;
+  i16 gyro_x, gyro_y, gyro_z;
+
+  u8 sensor_data[ACCEL_GYRO_READ_SIZE] = {};
+
+  int error = mpu9150_read(i2c, sensor_data, ACCEL_GYRO_BASE_ADDR, ACCEL_GYRO_READ_SIZE);
+  if (error) return error;
+
+  //Calculate accelerometer data
+  raw_accel_x = sensor_data[ACC_X_H] << 8 | sensor_data[ACC_X_L];
+  raw_accel_y = sensor_data[ACC_Y_H] << 8 | sensor_data[ACC_Y_L];
+  raw_accel_z = sensor_data[ACC_Z_H] << 8 | sensor_data[ACC_Z_L];
+
+  // put in G's
+  gam->accel_x = (raw_accel_x / 4096.0) + ACCEL_X_BIAS; // 4,096 is the gain per LSB of the measurement reading based on a configuration range of +-8g
+  gam->accel_y = (raw_accel_y / 4096.0) + ACCEL_Y_BIAS;
+  gam->accel_z = (raw_accel_z / 4096.0) + ACCEL_Z_BIAS;
+
+  //Convert gyro data to rate (we're only using the most 12 significant bits)
+  gyro_x = (sensor_data[GYR_X_H] << 8) | (sensor_data[GYR_X_L]); //* G_GAIN;
+  gyro_y = (sensor_data[GYR_Y_H] << 8 | sensor_data[GYR_Y_L]);// * G_GAIN;
+  gyro_z = (sensor_data[GYR_Z_H] << 8 | sensor_data[GYR_Z_L]);// * G_GAIN;
+
+  //Get the number of degrees
+  //javey: converted to radians to following SI units
+  gam->gyro_xVel_p = ((gyro_x / GYRO_SENS) * DEG_TO_RAD) + GYRO_X_BIAS;
+  gam->gyro_yVel_q = ((gyro_y / GYRO_SENS) * DEG_TO_RAD) + GYRO_Y_BIAS;
+  gam->gyro_zVel_r = ((gyro_z / GYRO_SENS) * DEG_TO_RAD) + GYRO_Z_BIAS;
+
+  // Magnometer
+  mpu9150_read_mag(self, gam);
+
+  return error;
+}
+
+//////////////////////
+// Helper functions
+/////////////////////
+
+int mpu9150_write(struct I2CDriver *i2c, u8 register_addr, u8 data){
+
+  u16 device_addr = MPU9150_DEVICE_ADDR;
+  u8 buf[] = {register_addr, data};
+
+  // Check if within register range
+  if(register_addr < 0 || register_addr > 0x75){
+    return -1;
+  }
+
+  if(register_addr <= 0x12){
+    device_addr = MPU9150_COMPASS_ADDR;
+  }
+
+  return i2c->write(i2c, device_addr, buf, 2);
+}
+
+int mpu9150_read(struct I2CDriver *i2c, u8* recv_buffer, u8 register_addr, int size){
+
+  u16 device_addr = MPU9150_DEVICE_ADDR;
+  u8 buf[] = {register_addr};
+
+  // Check if within register range
+  if(register_addr < 0 || register_addr > 0x75){
+  }
+
+  // Set device address to the if 0x00 <= register address <= 0x12
+  if(register_addr <= 0x12){
+    device_addr = MPU9150_COMPASS_ADDR;
+  }
+
+
+  int error = i2c->write(i2c, device_addr, buf, 1);
+  if (error) return error;
+  return i2c->read(i2c, device_addr, recv_buffer, size);
+}
+
+
+int mpu9150_read_mag(struct IMUDriver *self, gam_t* gam){
+	u8 mag_data[6];
+	u8 mag_status;
+	i16 raw_magX, raw_magY, raw_magZ;
+
+	int trigger = 0;
+
+	int status = mpu9150_read(self->i2c, mag_data, 0x02, 1);
+	if(status != 0) {
+		return status;
+	}
+
+	if(mag_data[0] & 0x01) {
+		// Get mag data
+		status = mpu9150_read(self->i2c, mag_data, 0x03, 6);
+		if(status != 0) {
+			return status;
+		}
+
+		status = mpu9150_read(self->i2c, &mag_status, 0x09, 1);
+		if(status != 0) {
+			return status;
+		}
+
+		raw_magX = (mag_data[1] << 8) | mag_data[0];
+		raw_magY = (mag_data[3] << 8) | mag_data[2];
+		raw_magZ = (mag_data[5] << 8) | mag_data[4];
+
+		// Set magnetometer data to output
+		gam->mag_x = raw_magX * gam->magX_correction;
+		gam->mag_y = raw_magY * gam->magY_correction;
+		gam->mag_z = raw_magZ * gam->magZ_correction;
+
+		trigger = 1;
+	}
+	else {
+		gam->magDRDYCount++;
+
+		if(gam->magDRDYCount > MAG_DRDY_TIMEOUT) {
+			gam->magDRDYCount = 0;
+
+			trigger = 1;
+		}
+	}
+
+	if(trigger) {
+		//Start next reading
+		mpu9150_write(self->i2c, 0x0A, 0x00);
+		mpu9150_write(self->i2c, 0x0A, 0x01);
+	}
+
+	return 0;
+}
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_lidar.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_lidar.c
new file mode 100644
index 0000000000000000000000000000000000000000..32d0fad0cd243c3e871c58eaaa10ead16c3d246b
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_lidar.c
@@ -0,0 +1,68 @@
+#include "hw_iface.h"
+#include "hw_impl_zybo.h"
+#include "type_def.h"
+#include <string.h>
+
+#define LIDARLITE_DEVICE_ADDR		0x62
+#define LIDAR_OFFSET (0.016666) // Distance from LiDAR sensor to ground, in meters
+
+int lidarlite_write(struct I2CDriver *i2c, u8 register_addr, u8 data);
+int lidarlite_read(struct I2CDriver *i2c, u8* recv_buffer, u8 register_addr, int size);
+
+int zybo_lidar_reset(struct LidarDriver *self, lidar_t *lidar) {
+  // initialize lidar
+	memset(lidar, 0, sizeof(lidar_t));
+
+  struct I2CDriver *i2c = self->i2c;
+
+  int error = 0;
+
+  // Device Reset & Wake up with default settings
+  error = lidarlite_write(i2c, 0x00, 0x00);
+  if (error) return error;
+  usleep(15000);
+
+  // Enable Free Running Mode and distance measurements with correction
+  error = lidarlite_write(i2c, 0x11, 0xff);
+  if (error) return error;
+  error = lidarlite_write(i2c, 0x00, 0x04);
+  return error;
+}
+
+int zybo_lidar_read(struct LidarDriver *self, lidar_t *lidar) {
+  struct I2CDriver *i2c = self->i2c;
+  u8 buf[2];
+  int error = 0;
+
+  // Read the sensor value
+  error = lidarlite_read(i2c, buf, 0x8f, 2);
+  if (error) return error;
+  float distance_cm = (float)(buf[0] << 8 | buf[1]);
+  lidar->distance_m = (distance_cm * 0.01) + LIDAR_OFFSET;
+
+  return error;
+}
+
+////////////////////
+// Helper functions
+////////////////////
+
+int lidarlite_write(struct I2CDriver *i2c, u8 register_addr, u8 data) {
+  u8 buf[] = {register_addr, data};
+  return i2c->write(i2c, LIDARLITE_DEVICE_ADDR, buf, 2);
+}
+
+int lidarlite_read(struct I2CDriver *i2c, u8* recv_buffer, u8 register_addr, int size) {
+  u8 buf[] = {register_addr};
+  int error = 0;
+
+  error = i2c->write(i2c, LIDARLITE_DEVICE_ADDR, buf, 1);
+  if (error) return error;
+  error = i2c->read(i2c, LIDARLITE_DEVICE_ADDR, recv_buffer, size);
+  return error;
+}
+
+// Maybe this will be useful?
+int lidarlite_sleep(struct I2CDriver *i2c) {
+  return lidarlite_write(i2c, 0x65, 0x84);
+}
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_mio7_led.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_mio7_led.c
new file mode 100644
index 0000000000000000000000000000000000000000..03a192671114b7e0cbf224b84fbb4c0752bbcd97
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_mio7_led.c
@@ -0,0 +1,22 @@
+#include "hw_impl_zybo.h"
+
+int zybo_mio7_led_reset(struct LEDDriver *self) {
+  if (self->state == NULL) {
+    self->state = malloc(sizeof(XGpioPs));
+  }
+
+  XGpioPs_Config *ConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
+  XGpioPs_CfgInitialize(self->state, ConfigPtr, ConfigPtr->BaseAddr);
+  XGpioPs_SetDirectionPin(self->state, 7, 1);
+  return 0;
+}
+
+int zybo_mio7_led_turn_on(struct LEDDriver *self) {
+  XGpioPs_WritePin(self->state, 7, 0x01);
+  return 0;
+}
+
+int zybo_mio7_led_turn_off(struct LEDDriver *self) {
+  XGpioPs_WritePin(self->state, 7, 0x00);
+  return 0;
+}
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_motor.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_motor.c
new file mode 100644
index 0000000000000000000000000000000000000000..8e8e27ab70d1983c3dffeef7207516dc998e0aec
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_motor.c
@@ -0,0 +1,55 @@
+#include "hw_impl_zybo.h"
+
+#define SYS_CLOCK_RATE 100000000 // ticks per second
+#define FREQUENCY 450
+#define PERIOD_WIDTH SYS_CLOCK_RATE/FREQUENCY
+#define PULSE_WIDTH_LOW SYS_CLOCK_RATE/1000 // 1 ms
+#define PULSE_WIDTH_HIGH SYS_CLOCK_RATE/500 // 2 ms
+#define PULSE_WIDTH_ADDR_OFFSET 1
+
+struct MotorDriverState {
+  int *outputs[4];
+};
+
+int zybo_motor_reset(struct MotorDriver *self) {
+  if (self->state == NULL) {
+    self->state = malloc(sizeof(struct MotorDriverState));
+    if (self->state == NULL) {
+      return -1;
+    }
+  }
+  struct MotorDriverState *state = self->state;
+
+  state->outputs[0] = (int *) XPAR_PWM_SIGNAL_OUT_0_S_AXI_BASEADDR;
+  state->outputs[1] = (int *) XPAR_PWM_SIGNAL_OUT_1_S_AXI_BASEADDR;
+  state->outputs[2] = (int *) XPAR_PWM_SIGNAL_OUT_2_S_AXI_BASEADDR;
+  state->outputs[3] = (int *) XPAR_PWM_SIGNAL_OUT_3_S_AXI_BASEADDR;
+
+  // Set period width of PWM pulse
+  *(state->outputs[0]) = PERIOD_WIDTH;
+  *(state->outputs[1]) = PERIOD_WIDTH;
+  *(state->outputs[2]) = PERIOD_WIDTH;
+  *(state->outputs[3]) = PERIOD_WIDTH;
+
+  // Set a low pulse (1 ms) so that outputs are off
+  *(state->outputs[0] + PULSE_WIDTH_ADDR_OFFSET) = PULSE_WIDTH_LOW;
+  *(state->outputs[1] + PULSE_WIDTH_ADDR_OFFSET) = PULSE_WIDTH_LOW;
+  *(state->outputs[2] + PULSE_WIDTH_ADDR_OFFSET) = PULSE_WIDTH_LOW;
+  *(state->outputs[3] + PULSE_WIDTH_ADDR_OFFSET) = PULSE_WIDTH_LOW;
+
+  usleep(1000000);
+  return 0;
+}
+
+int zybo_motor_write(struct MotorDriver *self,
+                          unsigned int channel,
+                          float magnitude) {
+  if (magnitude > 1)
+    magnitude = 1;
+  if (magnitude < 0)
+    magnitude = 0;
+  struct MotorDriverState *state = self->state;
+  unsigned long pulse_width_ticks = (unsigned long) (magnitude * (float) (PULSE_WIDTH_HIGH - PULSE_WIDTH_LOW)) + PULSE_WIDTH_LOW;
+  *(state->outputs[channel] + PULSE_WIDTH_ADDR_OFFSET) = pulse_width_ticks;
+  return 0;
+}
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_optical_flow.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_optical_flow.c
new file mode 100644
index 0000000000000000000000000000000000000000..c45ca68a9c9063653b8eda70b4827c83e05fcea1
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_optical_flow.c
@@ -0,0 +1,74 @@
+#include "hw_iface.h"
+#include "hw_impl_zybo.h"
+#include <stdint.h>
+#include <string.h>
+#include "type_def.h"
+
+int px4flow_write(struct I2CDriver *i2c, u8 register_addr, u8 data);
+int px4flow_read(struct I2CDriver *i2c, u8* recv_buffer, u8 register_addr, int size);
+
+int zybo_optical_flow_reset(struct OpticalFlowDriver *self, px4flow_t *of) {
+  memset(of, 0, sizeof(px4flow_t));
+
+  return 0;
+}
+
+int zybo_optical_flow_read(struct OpticalFlowDriver *self, px4flow_t *of) {
+  struct I2CDriver *i2c = self->i2c;
+  int error = 0;
+
+  // Note: Despite documentation, do not mark this as a "packed" struct. The actual code does not pack it.
+  struct i2c_integral_frame
+  {
+      uint16_t frame_count_since_last_readout;//number of flow measurements since last I2C readout [#frames]
+      int16_t pixel_flow_x_integral;//accumulated flow in radians*10000 around x axis since last I2C readout [rad*10000]
+      int16_t pixel_flow_y_integral;//accumulated flow in radians*10000 around y axis since last I2C readout [rad*10000]
+      int16_t gyro_x_rate_integral;//accumulated gyro x rates in radians*10000 since last I2C readout [rad*10000] 
+      int16_t gyro_y_rate_integral;//accumulated gyro y rates in radians*10000 since last I2C readout [rad*10000] 
+      int16_t gyro_z_rate_integral;//accumulated gyro z rates in radians*10000 since last I2C readout [rad*10000] 
+      uint32_t integration_timespan;//accumulation timespan in microseconds since last I2C readout [microseconds]
+      uint32_t sonar_timestamp;// time since last sonar update [microseconds]
+      int16_t ground_distance;// Ground distance in meters*1000 [meters*1000]
+      int16_t gyro_temperature;// Temperature * 100 in centi-degrees Celsius [degcelsius*100]
+      uint8_t quality;// averaged quality of accumulated flow values [0:bad quality;255: max quality]
+  } i2c_integral_frame;
+
+  u8 buf[sizeof(i2c_integral_frame)];
+
+  // Read the sensor value
+  error = px4flow_read(i2c, buf, 0x16, 26);
+
+  if(error == 0) {
+    //Copy into struct
+    memcpy(&i2c_integral_frame, buf, sizeof(i2c_integral_frame));
+
+    of->flow_x_rad = 0.0001 * i2c_integral_frame.pixel_flow_x_integral;
+    of->flow_y_rad = 0.0001 * i2c_integral_frame.pixel_flow_y_integral;
+    of->quality = i2c_integral_frame.quality;
+    of->dt = (double)i2c_integral_frame.integration_timespan / 1000000;
+  }
+  return error;
+}
+
+/////////////////////
+// Helper functions
+/////////////////////
+
+int px4flow_write(struct I2CDriver *i2c, u8 register_addr, u8 data) {
+	u8 buf[] = {register_addr, data};
+
+	return i2c->write(i2c, PX4FLOW_DEVICE_ADDR, buf, 2);
+}
+
+int px4flow_read(struct I2CDriver *i2c, u8* recv_buffer, u8 register_addr, int size) {
+	u8 buf[] = {register_addr};
+	int error = 0;
+
+	error = i2c->write(i2c, PX4FLOW_DEVICE_ADDR, buf, 1);
+	if (error) {
+		return error;
+	}
+	error = i2c->read(i2c, PX4FLOW_DEVICE_ADDR, recv_buffer, size);
+	return error;
+}
+
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_rc_receiver.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_rc_receiver.c
new file mode 100644
index 0000000000000000000000000000000000000000..391333b0a65cc7d60213930ae36a37f0e7fef786
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_rc_receiver.c
@@ -0,0 +1,40 @@
+#include "hw_impl_zybo.h"
+
+#define SYS_CLOCK_RATE 100000000 // ticks per second
+#define FREQUENCY 450
+#define PERIOD_WIDTH SYS_CLOCK_RATE/FREQUENCY
+#define PULSE_WIDTH_LOW SYS_CLOCK_RATE/1000 // 1 ms
+#define PULSE_WIDTH_HIGH SYS_CLOCK_RATE/500 // 2 ms
+#define PULSE_WIDTH_ADDR_OFFSET 1
+
+struct RCReceiverDriverState {
+  int *channels[6];
+};
+
+int zybo_rc_receiver_reset(struct RCReceiverDriver *self) {
+  if (self->state == NULL) {
+    self->state = malloc(sizeof(struct RCReceiverDriverState));
+    if (self->state == NULL) {
+      return -1;
+    }
+  }
+
+  // Save the addresses of the input PWM recorders
+  struct RCReceiverDriverState *state = self->state;
+  state->channels[0] = (int *) XPAR_PWM_RECORDER_0_S_AXI_BASEADDR;
+  state->channels[1] = (int *) XPAR_PWM_RECORDER_1_S_AXI_BASEADDR;
+  state->channels[2] = (int *) XPAR_PWM_RECORDER_2_S_AXI_BASEADDR;
+  state->channels[3] = (int *) XPAR_PWM_RECORDER_3_S_AXI_BASEADDR;
+  state->channels[4] = (int *) XPAR_PWM_RECORDER_4_S_AXI_BASEADDR;
+  state->channels[5] = (int *) XPAR_PWM_RECORDER_5_S_AXI_BASEADDR;
+  return 0;
+}
+
+int zybo_rc_receiver_read(struct RCReceiverDriver *self,
+                        unsigned int channel,
+                        float *magnitude) {
+  struct RCReceiverDriverState *state = self->state;
+  unsigned long pulse_width_ticks = (long) *((int *) state->channels[channel]);
+  *magnitude = (float) (pulse_width_ticks - PULSE_WIDTH_LOW) / (float) (PULSE_WIDTH_HIGH - PULSE_WIDTH_LOW);
+  return 0;
+}
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_system.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_system.c
new file mode 100644
index 0000000000000000000000000000000000000000..2adcc4007d4891b0f830b58cc03258abf63ef62d
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_system.c
@@ -0,0 +1,11 @@
+#include "hw_impl_zybo.h"
+
+int zybo_system_reset(struct SystemDriver *sys) {
+  return 0;
+}
+
+int zybo_system_sleep(struct SystemDriver *sys, unsigned long us) {
+  usleep(us);
+  return 0;
+}
+
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_tests.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_tests.c
new file mode 100644
index 0000000000000000000000000000000000000000..732c6256a2fd9354254fdccb2758537570ae3d9e
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_tests.c
@@ -0,0 +1,321 @@
+#include "hw_impl_zybo.h"
+#include "type_def.h"
+#include <stdio.h>
+
+/**
+ * Test for the LEDDriver and SystemDriver.
+ *
+ * This is essentially a basic "blink" program, using the mio7 LED
+ * on the Zybo board.
+ *
+ * Instructions:
+ * 1) Connect Zybo board to computer by USB cable.
+ * 2) Set the RUN_TESTS macro in main.c
+ * 3) Uncomment only this test in main.c
+ * 4) Run main.c
+ * 5) Observe MIO7 LED on board blinking at 1 second intervals.
+ */
+int test_zybo_mio7_led_and_system() {
+  struct LEDDriver mio7 = create_zybo_mio7_led();
+  struct SystemDriver sys = create_zybo_system();
+  mio7.reset(&mio7);
+  sys.reset(&sys);
+
+  while (1) {
+    mio7.turn_on(&mio7);
+    sys.sleep(&sys, 1000000);
+    mio7.turn_off(&mio7);
+    sys.sleep(&sys, 1000000);
+  }
+
+  return 0;
+}
+
+/**
+ * Tests for the I2CDriver (one for each I2C device we use)
+ *
+ * Instructions:
+ * 1) Connect Zybo Board to computer by USB cable.
+ * 2) Prepare a breadboard to accomplish the following connections:
+ *   - Zybo GND     <-> LIDAR GND
+ *   - Zybo WALL    <-> LIDAR VCC
+ *   - Zybo VV5V0   <-> LIDAR VCC
+ *   - Zybo SDA/SCL <-> LIDAR SDA/SCL
+ *     - The Zybo I2C SCL and SDA pins are on pins 1 and 2 of PORT JF, respectively
+ * 3) Place breakpoint in this test function, somewhere in the while loop.
+ * 4) Set the RUN_TESTS macro in main.c
+ * 5) Uncomment only this test in main.c
+ * 6) Debug main.c
+ * 7) Step through the while loop, observing x change as you physically change the
+ *    distance of the LIDAR sensor.
+ */
+int test_zybo_i2c() {
+  struct I2CDriver i2c = create_zybo_i2c(0);
+  struct LidarDriver ld = create_zybo_lidar(&i2c);
+  i2c.reset(&i2c);
+
+  lidar_t lidar = { };
+  if (ld.reset(&ld, &lidar)) return 0;
+  while (1) {
+    ld.read(&ld, &lidar);
+  }
+  return 0;
+}
+
+int test_zybo_i2c_imu() {
+  struct I2CDriver i2c = create_zybo_i2c(0);
+  struct IMUDriver imu = create_zybo_imu(&i2c);
+
+  gam_t gam;
+  if (i2c.reset(&i2c)) return 0;
+  if (imu.reset(&imu, &gam)) return 0;
+
+  int status = 0;
+  while (!status) {
+    status = imu.read(&imu, &gam);
+  }
+  return 0;
+}
+
+int test_zybo_i2c_px4flow() {
+  struct I2CDriver i2c = create_zybo_i2c(0);
+  struct OpticalFlowDriver ofd = create_zybo_optical_flow(&i2c);
+  i2c.reset(&i2c);
+  px4flow_t of;
+
+  if (ofd.reset(&ofd, &of)) return 0;
+
+  int status = 0;
+  while(!status) {
+    usleep(5000);
+    status = ofd.read(&ofd, &of);
+  }
+
+  return 0;
+}
+
+int test_zybo_i2c_lidar() {
+  struct I2CDriver i2c = create_zybo_i2c(1);
+  struct LidarDriver lidarDriver = create_zybo_lidar(&i2c);
+  i2c.reset(&i2c);
+  lidar_t lidar;
+
+  if (lidarDriver.reset(&lidarDriver, &lidar))
+	  return 0;
+
+  int status = 0;
+  while(!status) {
+    usleep(5000);
+    status = lidarDriver.read(&lidarDriver, &lidar);
+  }
+
+  return 0;
+}
+
+int test_zybo_i2c_all() {
+  struct I2CDriver i2c_0 = create_zybo_i2c(0);
+  struct IMUDriver imu = create_zybo_imu(&i2c_0);
+  struct I2CDriver i2c_1 = create_zybo_i2c(1);
+  struct LidarDriver ld = create_zybo_lidar(&i2c_1);
+  struct OpticalFlowDriver ofd = create_zybo_optical_flow(&i2c_0);
+  i2c_0.reset(&i2c_0);
+  i2c_1.reset(&i2c_1);
+
+  lidar_t lidar;
+  px4flow_t of;
+  gam_t gam;
+
+  if (ld.reset(&ld, &lidar)) return 0;
+  if (imu.reset(&imu, &gam)) return 0;
+  if (ofd.reset(&ofd, &of)) return 0;
+
+
+  int lidarErrors = 0;
+  int gamErrors = 0;
+  int nLoops = 0;
+  int of_errors = 0;
+
+  for(;;) {
+    ld.read(&ld, &lidar);
+    imu.read(&imu, &gam);
+    ofd.read(&ofd, &of);
+
+    if (lidar.distance_m > 50) {
+    	lidarErrors += 1;
+    }
+    if (gam.accel_z > -0.8) {
+    	gamErrors += 1;
+    }
+    nLoops += 1;
+  }
+  return 0;
+}
+
+/**
+ * Test for the PWMInputDriver.
+ *
+ * Instructions:
+ * 1) Connect the quad Zybo board to computer using USB.
+ * 2) Move jumper on Zybo board to use JTAG instead of SD.
+ * 3) Turn on Zybo board and turn on Spektrum handheld controller.
+ *   - Verify receiver on quad pairs with controller (orange LED should turn on)
+ * 3) Place breakpoint somewhere in the while loop of this function.
+ * 4) Set the RUN_TESTS macro in main.c
+ * 5) Uncomment only this test in main.c
+ * 6) Debug main.
+ * 7) Observe the values of pwm_inputs in debugger changing as you use the
+ *    Spektrum RC controller.
+ */
+int test_zybo_rc_receiver() {
+  struct RCReceiverDriver rc_receiver = create_zybo_rc_receiver();
+  rc_receiver.reset(&rc_receiver);
+
+  float pwms[6];
+  while (1) {
+    int i;
+    for (i = 0; i < 6; i += 1) {
+      rc_receiver.read(&rc_receiver, i, &pwms[i]);
+    }
+    continue;
+  }
+}
+
+/**
+ * Test for the PWMOutputDriver.
+ *
+ * Instructions:
+ * 1) Connect the quad Zybo board to computer using USB.
+ * 2) Move jumper on Zybo board to use JTAG instead of SD.
+ * 3) Get an oscilloscope and observe PMOD outputs JE7-JE10
+ * 4) Set the RUN_TESTS macro in main.c
+ * 5) Uncomment only this test in main.c
+ * 6) Run main.
+ * 7) Observe the PWM width of those PMOD pins changing with time
+ */
+int test_zybo_motors() {
+  struct MotorDriver motors = create_zybo_motors();
+  motors.reset(&motors);
+
+  double j = 0;
+  while (1) {
+    for (j = 0; j < 1.0; j += 0.01) {
+      int i = 0;
+      for (i = 0; i < 4; i += 1) {
+        motors.write(&motors, i, j);
+        usleep(50000);
+      }
+    }
+  }
+  return 0;
+}
+
+/**
+ * Test for the AXI timer, using LEDDriver.
+ *
+ * This is essentially a basic "blink" program, using the mio7 LED
+ * on the Zybo board.
+ *
+ * Instructions:
+ * 1) Connect Zybo board to computer by USB cable.
+ * 2) Set the RUN_TESTS macro in main.c
+ * 3) Uncomment only this test in main.c
+ * 4) Run main.c
+ * 5) Observe MIO7 LED on board blinking at 1 second intervals.
+ */
+//int test_zybo_axi_timer() {
+//  struct TimerDriver axi = create_zybo_axi_timer();
+//  struct LEDDriver led = create_zybo_mio7_led();
+//  axi.reset(&axi);
+//  led.reset(&led);
+//
+//  unsigned long time;
+//
+//  while (1) {
+//    axi.restart(&axi);
+//    time = 0;
+//    while (time < 1000000) {
+//      axi.read(&axi, &time);
+//    }
+//    led.turn_off(&led);
+//    while (time < 2000000) {
+//      axi.read(&axi, &time);
+//    }
+//    led.turn_on(&led);
+//  }
+//}
+
+/**
+ * Test for the Global timer, using LEDDriver.
+ *
+ * This is essentially a basic "blink" program, using the mio7 LED
+ * on the Zybo board.
+ *
+ * Instructions:
+ * 1) Connect Zybo board to computer by USB cable.
+ * 2) Set the RUN_TESTS macro in main.c
+ * 3) Uncomment only this test in main.c
+ * 4) Run main.c
+ * 5) Observe MIO7 LED on board blinking at 1 second intervals.
+ */
+int test_zybo_global_timer() {
+  struct TimerDriver global = create_zybo_global_timer();
+  struct LEDDriver led = create_zybo_mio7_led();
+  global.reset(&global);
+  led.reset(&led);
+
+  unsigned long time;
+
+  while (1) {
+    global.restart(&global);
+    time = 0;
+    while (time < 1000000) {
+      global.read(&global, &time);
+    }
+    led.turn_off(&led);
+    while (time < 2000000) {
+      global.read(&global, &time);
+    }
+    led.turn_on(&led);
+  }
+}
+
+/**
+ * Communication tests using the UARTDriver.
+ *
+ * Instructions:
+ * 1) Connect Zybo board to computer by USB cable.
+ * 2) Get a FTDI Basic Sparkfun board in order to connect the UART pins
+ *    on the Zybo to the computer by USB.
+ *    - Zybo PMOD JC2 (TX) <-> Sparkfun Board RX
+ *    - Zybo PMOD JC3 (RX) <-> sparkfun Board Tx
+ *    - Zybo PMOD JC5 (GND) <-> Sparkfun Board GDN
+ * 2) Set the RUN_TESTS macro in main.c
+ * 3) Uncomment only this test in main.c
+ * 4) Run main.c
+ * 5) Execute quad/scripts/tests/test_zybo_uart.py
+ *    - Observe test results on terminal
+ *    - You might be able to see LED MIO7 blink when it receives bytes
+ */
+int test_zybo_uart_comm() {
+  struct UARTDriver uart = create_zybo_uart(0);
+  struct CommDriver comm = create_zybo_comm(&uart);
+  struct LEDDriver led = create_zybo_mio7_led();
+  uart.reset(&uart);
+  led.reset(&led);
+
+  unsigned char c;
+  while (1) {
+    if (comm.uart->read(comm.uart, &c)) {
+      // read failed
+      led.turn_off(&led);
+    } else {
+      // read successful
+      led.turn_on(&led);
+      uart.write(&uart, c);
+    }
+  }
+
+  return 0;
+}
+
+
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_uart.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_uart.c
new file mode 100644
index 0000000000000000000000000000000000000000..9d3ff70509cdd8837a2278f4e721d6340bb3d77b
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/real_quad_fresh/src/hw_impl_zybo_uart.c
@@ -0,0 +1,282 @@
+#include "hw_impl_zybo.h"
+
+#define BAUD_RATE 921600
+
+
+int XUartPs_SetBaudRate_ours(XUartPs *InstancePtr, u32 BaudRate);
+int SetupInterruptSystem(struct ZyboUARTState *state, u16 UartIntrId, Xil_ExceptionHandler handler);
+void uart_interrupt_handler(struct ZyboUARTState *state);
+
+int zybo_uart_reset(struct UARTDriver *self) {
+  // Ensure all required memory is allocated
+  struct ZyboUARTState *state = self->state;
+  if (state == NULL) return -1;
+  if (state->inst == NULL) return -1;
+  if (state->queue == NULL) return -1;
+
+  XUartPs *inst = state->inst;
+
+  // Configure XUartPs instance
+  XUartPs_Config* config = XUartPs_LookupConfig(XPAR_PS7_UART_0_DEVICE_ID);
+  if (XUartPs_CfgInitialize(inst, config, config->BaseAddress) != XST_SUCCESS) {
+    return -1;
+  }
+
+  // Set UART Baudrate
+  if(XUartPs_SetBaudRate_ours(inst, BAUD_RATE) != XST_SUCCESS) {
+    return -1;
+  }
+
+  // Clear Tx/Rx FIFOs
+  int* uart_ctrl_reg = (int*) inst->Config.BaseAddress;
+  *uart_ctrl_reg |= 0x00000003; // clear TX & RX
+
+  // Setup Interrupts
+  if (SetupInterruptSystem(state, XPAR_PS7_UART_0_INTR, (Xil_ExceptionHandler) uart_interrupt_handler) != XST_SUCCESS) {
+    return -1;
+  }
+
+  // Interrupts selected: Rx FIFO threashold reached, RX overflow, timeout
+  u32 IntrMask = XUARTPS_IXR_RXFULL | XUARTPS_IXR_RXOVR | XUARTPS_IXR_TOUT;
+  XUartPs_SetInterruptMask(inst, IntrMask);
+
+  /*
+   * Set the receiver timeout. If it is not set, and the last few bytes
+   * of data do not trigger the over-water or full interrupt, the bytes
+   * will not be received. By default it is disabled.
+   * Timeout duration = RecvTimeout x 4 x Bit Period. 0 disables the
+   * timeout function.
+   *
+   * The setting of 8 will timeout after 8 x 4 = 32 character times.
+   * Increase the time out value if baud rate is high, decrease it if
+   * baud rate is low.
+   */
+  XUartPs_SetRecvTimeout(inst, 8);
+
+  // Second argument is the number of bytes to trigger an interrupt at
+  XUartPs_SetFifoThreshold(inst, 48);
+
+  return 0;
+}
+
+int zybo_uart_write(struct UARTDriver *self, unsigned char c) {
+  struct ZyboUARTState *state = self->state;
+  XUartPs *inst = state->inst;
+  XUartPs_SendByte(inst->Config.BaseAddress, c);
+  return 0;
+}
+
+int zybo_uart_read(struct UARTDriver *self, unsigned char *c) {
+  struct ZyboUARTState *state = self->state;
+  struct Queue *queue = state->queue;
+  if (queue_remove(queue, c)) return -1;
+  else return 0;
+}
+
+//This is copied from xuart driver
+/***************************************************/
+
+#define XUARTPS_MAX_BAUD_ERROR_RATE              3      /* max % error allowed */
+int XUartPs_SetBaudRate_ours(XUartPs *InstancePtr, u32 BaudRate)
+{
+  u8 IterBAUDDIV;               /* Iterator for available baud divisor values */
+  u32 BRGR_Value;               /* Calculated value for baud rate generator */
+  u32 CalcBaudRate;     /* Calculated baud rate */
+  u32 BaudError;                /* Diff between calculated and requested baud rate */
+  u32 Best_BRGR = 0;    /* Best value for baud rate generator */
+  u8 Best_BAUDDIV = 0;  /* Best value for baud divisor */
+  u32 Best_Error = 0xFFFFFFFF;
+  u32 PercentError;
+  u32 ModeReg;
+  u32 InputClk;
+
+  /*
+   * Asserts validate the input arguments
+   */
+  Xil_AssertNonvoid(InstancePtr != NULL);
+  Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+  //Xil_AssertNonvoid(BaudRate <= XUARTPS_MAX_RATE);
+  Xil_AssertNonvoid(BaudRate >= XUARTPS_MIN_RATE);
+
+  /*
+   * Make sure the baud rate is not impossilby large.
+   * Fastest possible baud rate is Input Clock / 2.
+   */
+  if ((BaudRate * 2) > InstancePtr->Config.InputClockHz) {
+    return XST_UART_BAUD_ERROR;
+  }
+  /*
+   * Check whether the input clock is divided by 8
+   */
+  ModeReg = XUartPs_ReadReg( InstancePtr->Config.BaseAddress,
+                             XUARTPS_MR_OFFSET);
+
+  InputClk = InstancePtr->Config.InputClockHz;
+  if(ModeReg & XUARTPS_MR_CLKSEL) {
+    InputClk = InstancePtr->Config.InputClockHz / 8;
+  }
+
+  /*
+   * Determine the Baud divider. It can be 4to 254.
+   * Loop through all possible combinations
+   */
+  for (IterBAUDDIV = 4; IterBAUDDIV < 255; IterBAUDDIV++) {
+
+    /*
+     * Calculate the value for BRGR register
+     */
+    BRGR_Value = InputClk / (BaudRate * (IterBAUDDIV + 1));
+
+    /*
+     * Calculate the baud rate from the BRGR value
+     */
+    CalcBaudRate = InputClk/ (BRGR_Value * (IterBAUDDIV + 1));
+
+    /*
+     * Avoid unsigned integer underflow
+     */
+    if (BaudRate > CalcBaudRate) {
+      BaudError = BaudRate - CalcBaudRate;
+    }
+    else {
+      BaudError = CalcBaudRate - BaudRate;
+    }
+
+    /*
+     * Find the calculated baud rate closest to requested baud rate.
+     */
+    if (Best_Error > BaudError) {
+
+      Best_BRGR = BRGR_Value;
+      Best_BAUDDIV = IterBAUDDIV;
+      Best_Error = BaudError;
+    }
+  }
+
+  /*
+   * Make sure the best error is not too large.
+   */
+  PercentError = (Best_Error * 100) / BaudRate;
+  if (XUARTPS_MAX_BAUD_ERROR_RATE < PercentError) {
+    return XST_UART_BAUD_ERROR;
+  }
+
+  /*
+   * Disable TX and RX to avoid glitches when setting the baud rate.
+   */
+  XUartPs_DisableUart(InstancePtr);
+
+  XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+                   XUARTPS_BAUDGEN_OFFSET, Best_BRGR);
+  XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+                   XUARTPS_BAUDDIV_OFFSET, Best_BAUDDIV);
+
+  /*
+   * Enable device
+   */
+  XUartPs_EnableUart(InstancePtr);
+
+  InstancePtr->BaudRate = BaudRate;
+
+  return XST_SUCCESS;
+
+}
+
+void uart_interrupt_handler(struct ZyboUARTState *state) {
+  u32 IsrStatus;
+  XUartPs *InstancePtr = state->inst;
+  struct Queue *queue = state->queue;
+
+  /*
+   * Read the interrupt ID register to determine which
+   * interrupt is active
+   */
+  IsrStatus = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+                              XUARTPS_IMR_OFFSET);
+
+  IsrStatus &= XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+                               XUARTPS_ISR_OFFSET);
+
+  /*
+   * Read the Channel Status Register to determine if there is any data in
+   * the RX FIFO
+   */
+
+  u32 CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+                                    XUARTPS_SR_OFFSET);
+
+  while (0 == (CsrRegister & XUARTPS_SR_RXEMPTY)) {
+    u8 byte = XUartPs_ReadReg(InstancePtr->Config.BaseAddress, XUARTPS_FIFO_OFFSET);
+    queue_add(queue, byte);
+    CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress, XUARTPS_SR_OFFSET);
+  }
+
+  // Clear the interrupt status.
+  XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_ISR_OFFSET,
+                   IsrStatus);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets up the interrupt system so interrupts can occur for the
+* Uart. This function is application-specific.
+*
+* @param	IntcInstancePtr is a pointer to the instance of the INTC.
+* @param	UartInstancePtr contains a pointer to the instance of the UART
+*		driver which is going to be connected to the interrupt
+*		controller.
+* @param	UartIntrId is the interrupt Id and is typically
+*		XPAR_<UARTPS_instance>_INTR value from xparameters.h.
+*
+* @return	XST_SUCCESS if successful, otherwise XST_FAILURE.
+*
+* @note		None.
+*
+****************************************************************************/
+int SetupInterruptSystem(struct ZyboUARTState *state, u16 UartIntrId, Xil_ExceptionHandler handler)
+{
+	int Status;
+	XScuGic_Config *IntcConfig; /* Config for interrupt controller */
+
+	/* Initialize the interrupt controller driver */
+	IntcConfig = XScuGic_LookupConfig(XPAR_SCUGIC_SINGLE_DEVICE_ID);
+	if (NULL == IntcConfig) {
+		return XST_FAILURE;
+	}
+
+    memset(&state->xscugic, 0, sizeof(XScuGic));
+	Status = XScuGic_CfgInitialize(&state->xscugic, IntcConfig,
+					IntcConfig->CpuBaseAddress);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Connect the interrupt controller interrupt handler to the
+	 * hardware interrupt handling logic in the processor.
+	 */
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+				(Xil_ExceptionHandler) XScuGic_InterruptHandler,
+				&state->xscugic);
+
+	/*
+	 * Connect a device driver handler that will be called when an
+	 * interrupt for the device occurs, the device driver handler
+	 * performs the specific interrupt processing for the device
+	 */
+	Status = XScuGic_Connect(&state->xscugic, UartIntrId,
+				  handler,
+				  (void *) state);
+	if (Status != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	/* Enable the interrupt for the device */
+	XScuGic_Enable(&state->xscugic, UartIntrId);
+
+	/* Enable interrupts */
+	 Xil_ExceptionEnable();
+
+	return XST_SUCCESS;
+}
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/lscript.ld b/quad/xsdk_workspace_vivado/real_quad_fresh/src/lscript.ld
new file mode 100644
index 0000000000000000000000000000000000000000..a9e7524bb4b15ca61a3d8c76f6a001e3b4c86e9f
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/real_quad_fresh/src/lscript.ld
@@ -0,0 +1,284 @@
+/*******************************************************************/
+/*                                                                 */
+/* This file is automatically generated by linker script generator.*/
+/*                                                                 */
+/* Version: Xilinx EDK 14.7 EDK_P.20131013                                */
+/*                                                                 */
+/* Copyright (c) 2010 Xilinx, Inc.  All rights reserved.           */
+/*                                                                 */
+/* Description : Cortex-A9 Linker Script                          */
+/*                                                                 */
+/*******************************************************************/
+
+_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x100000;
+_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x6400000;
+
+_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
+_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
+_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
+_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
+
+/* Define Memories in the system */
+
+MEMORY
+{
+   ps7_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x00100000, LENGTH = 0x1FF00000
+   ps7_ram_0_S_AXI_BASEADDR : ORIGIN = 0x00000000, LENGTH = 0x00030000
+   ps7_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x0000FE00
+}
+
+/* Specify the default entry point to the program */
+
+ENTRY(_vector_table)
+
+/* Define the sections, and where they are mapped in memory */
+
+SECTIONS
+{
+.text : {
+   *(.vectors)
+   *(.boot)
+   *(.text)
+   *(.text.*)
+   *(.gnu.linkonce.t.*)
+   *(.plt)
+   *(.gnu_warning)
+   *(.gcc_execpt_table)
+   *(.glue_7)
+   *(.glue_7t)
+   *(.vfp11_veneer)
+   *(.ARM.extab)
+   *(.gnu.linkonce.armextab.*)
+} > ps7_ddr_0_S_AXI_BASEADDR
+
+.init : {
+   KEEP (*(.init))
+} > ps7_ddr_0_S_AXI_BASEADDR
+
+.fini : {
+   KEEP (*(.fini))
+} > ps7_ddr_0_S_AXI_BASEADDR
+
+.rodata : {
+   __rodata_start = .;
+   *(.rodata)
+   *(.rodata.*)
+   *(.gnu.linkonce.r.*)
+   __rodata_end = .;
+} > ps7_ddr_0_S_AXI_BASEADDR
+
+.rodata1 : {
+   __rodata1_start = .;
+   *(.rodata1)
+   *(.rodata1.*)
+   __rodata1_end = .;
+} > ps7_ddr_0_S_AXI_BASEADDR
+
+.sdata2 : {
+   __sdata2_start = .;
+   *(.sdata2)
+   *(.sdata2.*)
+   *(.gnu.linkonce.s2.*)
+   __sdata2_end = .;
+} > ps7_ddr_0_S_AXI_BASEADDR
+
+.sbss2 : {
+   __sbss2_start = .;
+   *(.sbss2)
+   *(.sbss2.*)
+   *(.gnu.linkonce.sb2.*)
+   __sbss2_end = .;
+} > ps7_ddr_0_S_AXI_BASEADDR
+
+.data : {
+   __data_start = .;
+   *(.data)
+   *(.data.*)
+   *(.gnu.linkonce.d.*)
+   *(.jcr)
+   *(.got)
+   *(.got.plt)
+   __data_end = .;
+} > ps7_ddr_0_S_AXI_BASEADDR
+
+.data1 : {
+   __data1_start = .;
+   *(.data1)
+   *(.data1.*)
+   __data1_end = .;
+} > ps7_ddr_0_S_AXI_BASEADDR
+
+.got : {
+   *(.got)
+} > ps7_ddr_0_S_AXI_BASEADDR
+
+.ctors : {
+   __CTOR_LIST__ = .;
+   ___CTORS_LIST___ = .;
+   KEEP (*crtbegin.o(.ctors))
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
+   KEEP (*(SORT(.ctors.*)))
+   KEEP (*(.ctors))
+   __CTOR_END__ = .;
+   ___CTORS_END___ = .;
+} > ps7_ddr_0_S_AXI_BASEADDR
+
+.dtors : {
+   __DTOR_LIST__ = .;
+   ___DTORS_LIST___ = .;
+   KEEP (*crtbegin.o(.dtors))
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
+   KEEP (*(SORT(.dtors.*)))
+   KEEP (*(.dtors))
+   __DTOR_END__ = .;
+   ___DTORS_END___ = .;
+} > ps7_ddr_0_S_AXI_BASEADDR
+
+.fixup : {
+   __fixup_start = .;
+   *(.fixup)
+   __fixup_end = .;
+} > ps7_ddr_0_S_AXI_BASEADDR
+
+.eh_frame : {
+   *(.eh_frame)
+} > ps7_ddr_0_S_AXI_BASEADDR
+
+.eh_framehdr : {
+   __eh_framehdr_start = .;
+   *(.eh_framehdr)
+   __eh_framehdr_end = .;
+} > ps7_ddr_0_S_AXI_BASEADDR
+
+.gcc_except_table : {
+   *(.gcc_except_table)
+} > ps7_ddr_0_S_AXI_BASEADDR
+
+.mmu_tbl (ALIGN(16384)) : {
+   __mmu_tbl_start = .;
+   *(.mmu_tbl)
+   __mmu_tbl_end = .;
+} > ps7_ddr_0_S_AXI_BASEADDR
+
+.ARM.exidx : {
+   __exidx_start = .;
+   *(.ARM.exidx*)
+   *(.gnu.linkonce.armexidix.*.*)
+   __exidx_end = .;
+} > ps7_ddr_0_S_AXI_BASEADDR
+
+.preinit_array : {
+   __preinit_array_start = .;
+   KEEP (*(SORT(.preinit_array.*)))
+   KEEP (*(.preinit_array))
+   __preinit_array_end = .;
+} > ps7_ddr_0_S_AXI_BASEADDR
+
+.init_array : {
+   __init_array_start = .;
+   KEEP (*(SORT(.init_array.*)))
+   KEEP (*(.init_array))
+   __init_array_end = .;
+} > ps7_ddr_0_S_AXI_BASEADDR
+
+.fini_array : {
+   __fini_array_start = .;
+   KEEP (*(SORT(.fini_array.*)))
+   KEEP (*(.fini_array))
+   __fini_array_end = .;
+} > ps7_ddr_0_S_AXI_BASEADDR
+
+.ARM.attributes : {
+   __ARM.attributes_start = .;
+   *(.ARM.attributes)
+   __ARM.attributes_end = .;
+} > ps7_ddr_0_S_AXI_BASEADDR
+
+.sdata : {
+   __sdata_start = .;
+   *(.sdata)
+   *(.sdata.*)
+   *(.gnu.linkonce.s.*)
+   __sdata_end = .;
+} > ps7_ddr_0_S_AXI_BASEADDR
+
+.sbss (NOLOAD) : {
+   __sbss_start = .;
+   *(.sbss)
+   *(.sbss.*)
+   *(.gnu.linkonce.sb.*)
+   __sbss_end = .;
+} > ps7_ddr_0_S_AXI_BASEADDR
+
+.tdata : {
+   __tdata_start = .;
+   *(.tdata)
+   *(.tdata.*)
+   *(.gnu.linkonce.td.*)
+   __tdata_end = .;
+} > ps7_ddr_0_S_AXI_BASEADDR
+
+.tbss : {
+   __tbss_start = .;
+   *(.tbss)
+   *(.tbss.*)
+   *(.gnu.linkonce.tb.*)
+   __tbss_end = .;
+} > ps7_ddr_0_S_AXI_BASEADDR
+
+.bss (NOLOAD) : {
+   __bss_start = .;
+   *(.bss)
+   *(.bss.*)
+   *(.gnu.linkonce.b.*)
+   *(COMMON)
+   __bss_end = .;
+} > ps7_ddr_0_S_AXI_BASEADDR
+
+_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
+
+_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
+
+/* Generate Stack and Heap definitions */
+
+.heap (NOLOAD) : {
+   . = ALIGN(16);
+   _heap = .;
+   HeapBase = .;
+   _heap_start = .;
+   . += _HEAP_SIZE;
+   _heap_end = .;
+   HeapLimit = .;
+} > ps7_ddr_0_S_AXI_BASEADDR
+
+.stack (NOLOAD) : {
+   . = ALIGN(16);
+   _stack_end = .;
+   . += _STACK_SIZE;
+   _stack = .;
+   __stack = _stack;
+   . = ALIGN(16);
+   _irq_stack_end = .;
+   . += _STACK_SIZE;
+   __irq_stack = .;
+   _supervisor_stack_end = .;
+   . += _SUPERVISOR_STACK_SIZE;
+   . = ALIGN(16);
+   __supervisor_stack = .;
+   _abort_stack_end = .;
+   . += _ABORT_STACK_SIZE;
+   . = ALIGN(16);
+   __abort_stack = .;
+   _fiq_stack_end = .;
+   . += _FIQ_STACK_SIZE;
+   . = ALIGN(16);
+   __fiq_stack = .;
+   _undef_stack_end = .;
+   . += _UNDEF_STACK_SIZE;
+   . = ALIGN(16);
+   __undef_stack = .;
+} > ps7_ddr_0_S_AXI_BASEADDR
+
+_end = .;
+}
+
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/main.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/main.c
new file mode 100644
index 0000000000000000000000000000000000000000..716a876a9602109397b7aeda3d9b9e8119da4b00
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/real_quad_fresh/src/main.c
@@ -0,0 +1,72 @@
+#include <stdio.h>
+#include "hw_impl_zybo.h"
+#include "quad_app.h"
+#include "type_def.h"
+#include "platform.h"
+
+//#define RUN_TESTS
+
+/**
+ * Create the hardware drivers, and place them on the hardware struct.
+ *
+ * Things to keep in mind:
+ * - The CommDriver requires a UART. Hence, make the a UARTDriver first
+ *   and then give that instance to the CommDriver.
+ * - Same for GPSDriver, except it needs a different hardware device.
+ * - The I2C devices (IMU, LIDAR, Optical Flow), need a I2C bus. Hence
+ *   make a I2CDriver first, then give the appropariate instance the
+ *   device drivers.
+ *   - Currently, we are putting the Lidar on its own bus. Apparently,
+ *     when looking at an OScope with the Lidar on a bus with other
+ *     devices, it does not look right. The SCL line would never
+ *     go all the way back down to 0 volts
+ */
+int setup_hardware(hardware_t *hardware) {
+  hardware->rc_receiver = create_zybo_rc_receiver();
+  hardware->motors = create_zybo_motors();
+  hardware->uart_0 = create_zybo_uart(0);
+  hardware->uart_1 = create_zybo_uart(1);
+  hardware->comm = create_zybo_comm(&hardware->uart_0);
+  hardware->gps = create_zybo_gps(&hardware->uart_1);
+  hardware->global_timer = create_zybo_global_timer();
+  //hardware->axi_timer = create_zybo_axi_timer();
+  hardware->mio7_led = create_zybo_mio7_led();
+  hardware->sys = create_zybo_system();
+  hardware->i2c_0 = create_zybo_i2c(0);
+  hardware->i2c_1 = create_zybo_i2c(1);
+  hardware->imu = create_zybo_imu(&hardware->i2c_0);
+  hardware->lidar = create_zybo_lidar(&hardware->i2c_1);
+  hardware->of = create_zybo_optical_flow(&hardware->i2c_0);
+  return 0;
+}
+
+int main()
+{
+  // Zynq initialization
+  init_platform();
+
+#ifdef RUN_TESTS
+  //test_zybo_mio7_led_and_system();
+  //test_zybo_i2c();
+  //test_zybo_i2c_imu();
+  test_zybo_i2c_px4flow();
+  //test_zybo_i2c_lidar();
+  //test_zybo_i2c_all();
+  //test_zybo_rc_receiver();
+  //test_zybo_motors();
+  //test_zybo_uart();
+  //test_zybo_axi_timer();
+  //test_zybo_uart_comm();
+  return 0;
+#endif
+
+  // Run the main quad application
+  quad_main(setup_hardware);
+
+  while(1) {
+	  volatile int i = 0;
+	  i++;
+  }
+
+  return 0;
+}
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/platform.c b/quad/xsdk_workspace_vivado/real_quad_fresh/src/platform.c
new file mode 100644
index 0000000000000000000000000000000000000000..ea7849798004dd889c3c4bfa76a67c0867e023d3
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/real_quad_fresh/src/platform.c
@@ -0,0 +1,112 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+#include "xparameters.h"
+#include "xil_cache.h"
+
+#include "platform_config.h"
+
+/*
+ * Uncomment the following line if ps7 init source files are added in the
+ * source directory for compiling example outside of SDK.
+ */
+/*#include "ps7_init.h"*/
+
+#ifdef STDOUT_IS_16550
+ #include "xuartns550_l.h"
+
+ #define UART_BAUD 9600
+#endif
+
+void
+enable_caches()
+{
+#ifdef __PPC__
+    Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK);
+    Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK);
+#elif __MICROBLAZE__
+#ifdef XPAR_MICROBLAZE_USE_ICACHE
+    Xil_ICacheEnable();
+#endif
+#ifdef XPAR_MICROBLAZE_USE_DCACHE
+    Xil_DCacheEnable();
+#endif
+#endif
+}
+
+void
+disable_caches()
+{
+    Xil_DCacheDisable();
+    Xil_ICacheDisable();
+}
+
+void
+init_uart()
+{
+#ifdef STDOUT_IS_16550
+    XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD);
+    XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
+#endif
+#ifdef STDOUT_IS_PS7_UART
+    /* Bootrom/BSP configures PS7 UART to 115200 bps */
+#endif
+}
+
+void
+init_platform()
+{
+    /*
+     * If you want to run this example outside of SDK,
+     * uncomment the following line and also #include "ps7_init.h" at the top.
+     * Make sure that the ps7_init.c and ps7_init.h files are included
+     * along with this example source files for compilation.
+     */
+    /* ps7_init();*/
+    enable_caches();
+    init_uart();
+}
+
+void
+cleanup_platform()
+{
+    disable_caches();
+}
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/platform.h b/quad/xsdk_workspace_vivado/real_quad_fresh/src/platform.h
new file mode 100644
index 0000000000000000000000000000000000000000..efc90882b0b336c2038d1f8a0a02ffed7d6e7ae3
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/real_quad_fresh/src/platform.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2008 Xilinx, Inc.  All rights reserved.
+ *
+ * Xilinx, Inc.
+ * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+ * COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+ * ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
+ * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
+ * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
+ * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+ * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+ * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
+ * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+ * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ */
+
+#ifndef __PLATFORM_H_
+#define __PLATFORM_H_
+
+#include "platform_config.h"
+
+void init_platform();
+void cleanup_platform();
+
+#endif
diff --git a/quad/xsdk_workspace_vivado/real_quad_fresh/src/platform_config.h b/quad/xsdk_workspace_vivado/real_quad_fresh/src/platform_config.h
new file mode 100644
index 0000000000000000000000000000000000000000..c07ab1cba9631113470838bd69dce3964dd386fa
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/real_quad_fresh/src/platform_config.h
@@ -0,0 +1,10 @@
+#ifndef __PLATFORM_CONFIG_H_
+#define __PLATFORM_CONFIG_H_
+
+#define STDOUT_IS_PS7_UART
+#define UART_DEVICE_ID 0
+#ifdef __PPC__
+#define CACHEABLE_REGION_MASK 0xf0000001
+#endif
+
+#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/.cproject b/quad/xsdk_workspace_vivado/standalone_bsp_0/.cproject
new file mode 100644
index 0000000000000000000000000000000000000000..00ffbf8764b9327b7ef01ee1cf39ea498ce1459c
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/.cproject
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="org.eclipse.cdt.core.default.config.1030668811">
+			<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1030668811" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
+				<externalSettings/>
+				<extensions/>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+</cproject>
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/.project b/quad/xsdk_workspace_vivado/standalone_bsp_0/.project
new file mode 100644
index 0000000000000000000000000000000000000000..cf86d526d4dfbf9b118eb65bf43cd220b2286fa5
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/.project
@@ -0,0 +1,75 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>standalone_bsp_0</name>
+	<comment>Created by SDK v2017.1</comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.make.core.makeBuilder</name>
+			<arguments>
+				<dictionary>
+					<key>org.eclipse.cdt.core.errorOutputParser</key>
+					<value>org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser;</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.build.arguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.build.command</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.build.target.auto</key>
+					<value>all</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.build.target.clean</key>
+					<value>clean</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.build.target.inc</key>
+					<value>all</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enabledIncrementalBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.environment</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>com.xilinx.sdk.sw.SwProjectNature</nature>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.make.core.makeNature</nature>
+	</natures>
+</projectDescription>
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/.sdkproject b/quad/xsdk_workspace_vivado/standalone_bsp_0/.sdkproject
new file mode 100644
index 0000000000000000000000000000000000000000..6e301ca60b93be481ba7ea99c4fba9bd211a98a7
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/.sdkproject
@@ -0,0 +1,4 @@
+THIRPARTY=false
+HW_PROJECT_REFERENCE=quad_wrapper_hw_platform_0
+PROCESSOR=ps7_cortexa9_0
+MSS_FILE=system.mss
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/Makefile b/quad/xsdk_workspace_vivado/standalone_bsp_0/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..1ace345f6a38ecafefb9629dda2e2ad8a9fc5de7
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/Makefile
@@ -0,0 +1,35 @@
+# Makefile generated by Xilinx.
+
+PROCESSOR = ps7_cortexa9_0
+LIBRARIES = ${PROCESSOR}/lib/libxil.a
+BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile)
+SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES))
+
+ifneq (,$(findstring win,$(RDI_PLATFORM)))
+ SHELL = CMD
+endif
+
+all: libs
+	@echo 'Finished building libraries'
+
+include: $(addsuffix /make.include,$(SUBDIRS))
+
+libs: $(addsuffix /make.libs,$(SUBDIRS))
+
+clean: $(addsuffix /make.clean,$(SUBDIRS))
+
+$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a
+	cp -f $< $@
+
+%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,)
+	@echo "Running Make include in $(subst /make.include,,$@)"
+	$(MAKE) -C $(subst /make.include,,$@) -s include  "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -Wall -Wextra"
+
+%/make.libs: include
+	@echo "Running Make libs in $(subst /make.libs,,$@)"
+	$(MAKE) -C $(subst /make.libs,,$@) -s libs  "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -Wall -Wextra"
+
+%/make.clean: 
+	$(MAKE) -C $(subst /make.clean,,$@) -s clean 
+clean:
+	rm -f ${PROCESSOR}/lib/libxil.a
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/_profile_timer_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/_profile_timer_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..2cee66b09ec02849f667a2e6731e44e6ab6163e4
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/_profile_timer_hw.h
@@ -0,0 +1,312 @@
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************
+*
+* _program_timer_hw.h:
+*	Timer related functions
+*
+******************************************************************************/
+
+#ifndef PROFILE_TIMER_HW_H
+#define PROFILE_TIMER_HW_H
+
+#include "profile.h"
+
+#ifdef PROC_PPC
+#if defined __GNUC__
+#  define SYNCHRONIZE_IO __asm__ volatile ("eieio")
+#elif defined __DCC__
+#  define SYNCHRONIZE_IO __asm volatile(" eieio")
+#else
+#  define SYNCHRONIZE_IO
+#endif
+#endif
+
+#ifdef PROC_PPC
+#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; }
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
+#else
+#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); }
+#endif
+
+#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
+	ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] +	\
+			   (u32)(RegOffset)), (u32)(ValueToWrite))
+
+#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset)	\
+	ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset))
+
+#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
+	ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET,     \
+					   (RegisterValue))
+
+#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber)		\
+	ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef PROC_PPC
+#include "xexception_l.h"
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#endif
+
+#ifdef TIMER_CONNECT_INTC
+#include "xintc_l.h"
+#include "xintc.h"
+#endif	/* TIMER_CONNECT_INTC */
+
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+#include "xtmrctr_l.h"
+#endif
+
+#ifdef PROC_CORTEXA9
+#include "xscutimer_hw.h"
+#include "xscugic.h"
+#endif
+
+extern u32 timer_clk_ticks ;
+
+/*--------------------------------------------------------------------
+ * PowerPC Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_PPC
+
+#ifdef PPC_PIT_INTERRUPT
+u32 timer_lo_clk_ticks ;	/* Clk ticks when Timer is disabled in CG */
+#endif
+
+#ifdef PROC_PPC440
+#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
+#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
+#define XREG_SPR_PIT XREG_SPR_DEC
+#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
+#endif
+
+/* --------------------------------------------------------------------
+ * Disable the Timer - During Profiling
+ *
+ * For PIT Timer -
+ *	1. XTime_PITDisableInterrupt() ;
+ *	2. Store the remaining timer clk tick
+ *	3. Stop the PIT Timer
+ *-------------------------------------------------------------------- */
+
+#ifdef PPC_PIT_INTERRUPT
+#define disable_timer() 		\
+	{				\
+		u32 val;	\
+		val=mfspr(XREG_SPR_TCR);	\
+		mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE));	\
+		timer_lo_clk_ticks = mfspr(XREG_SPR_PIT);			\
+		mtspr(XREG_SPR_PIT, 0);	\
+	}
+#else
+#define disable_timer() 	\
+   { \
+      u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+      u32 tmp_v = ProfIo_In32(addr); \
+      tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \
+      ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+   }
+#endif
+
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer
+ *
+ * For PIT Timer -
+ *	1. Load the remaining timer clk ticks
+ *	2. XTime_PITEnableInterrupt() ;
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+#define enable_timer()				\
+	{					\
+		u32 val;		\
+		val=mfspr(XREG_SPR_TCR);	\
+		mtspr(XREG_SPR_PIT, timer_lo_clk_ticks);	\
+		mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
+	}
+#else
+#define enable_timer()						\
+	{							\
+      u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+      u32 tmp_v = ProfIo_In32(addr); \
+      tmp_v = tmp_v |  XTC_CSR_ENABLE_TMR_MASK; \
+      ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+	}
+#endif
+
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ * For PIT Timer -
+ * 	1. Load the timer clk ticks
+ *	2. Enable AutoReload and Interrupt
+ *	3. Clear PIT Timer Status bits
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+#define timer_ack()							\
+	{								\
+		u32 val;					\
+		mtspr(XREG_SPR_PIT, timer_clk_ticks);			\
+		mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS);	\
+		val=mfspr(XREG_SPR_TCR);				\
+		mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
+	}
+#else
+#define timer_ack()				\
+	{						\
+		u32 csr;			\
+		csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0);	\
+		ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr);	\
+	}
+#endif
+
+/*-------------------------------------------------------------------- */
+#endif	/* PROC_PPC */
+/* -------------------------------------------------------------------- */
+
+
+
+
+/* --------------------------------------------------------------------
+ * MicroBlaze Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_MICROBLAZE
+
+/* --------------------------------------------------------------------
+ * Disable the Timer during Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define disable_timer()					\
+	{						\
+      u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
+	  Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+	  Addr += (u32)XTC_TCSR_OFFSET; \
+      u32 tmp_v = ProfIo_In32(Addr); \
+      tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \
+      u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \
+      OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+      OutAddr += (u32)XTC_TCSR_OFFSET; \
+      ProfIo_Out32(OutAddr, (u32)tmp_v); \
+    }
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer after Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define enable_timer()					\
+	{						\
+      u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
+	  Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+	  Addr += (u32)XTC_TCSR_OFFSET; \
+      u32 tmp_v = (u32)ProfIo_In32(Addr); \
+      tmp_v = tmp_v |  (u32)XTC_CSR_ENABLE_TMR_MASK; \
+      ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \
+	}
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ *-------------------------------------------------------------------- */
+#define timer_ack()				\
+	{						\
+		u32 csr;			\
+		csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0);	\
+		ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr);	\
+	}
+
+/*-------------------------------------------------------------------- */
+#endif	/* PROC_MICROBLAZE */
+/*-------------------------------------------------------------------- */
+
+/* --------------------------------------------------------------------
+ * Cortex A9 Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_CORTEXA9
+
+/* --------------------------------------------------------------------
+ * Disable the Timer during Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define disable_timer()							\
+{								\
+	u32 Reg;							\
+	Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+	Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\
+	Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer after Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define enable_timer()							\
+{								\
+	u32 Reg;							\
+	Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+	Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
+	Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ *-------------------------------------------------------------------- */
+#define timer_ack()						\
+{							\
+	Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \
+		(u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\
+}
+
+/*-------------------------------------------------------------------- */
+#endif	/* PROC_CORTEXA9 */
+/*-------------------------------------------------------------------- */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/bspconfig.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/bspconfig.h
new file mode 100644
index 0000000000000000000000000000000000000000..87363749e348f1100d7bfdb61d6d5221c3260a14
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/bspconfig.h
@@ -0,0 +1,40 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Configurations for Standalone BSP
+*
+*******************************************************************/
+
+#define MICROBLAZE_PVR_NONE
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/mblaze_nt_types.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/mblaze_nt_types.h
new file mode 100644
index 0000000000000000000000000000000000000000..7096a92d804e8cbd2a660b78a32d5ea3a7256862
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/mblaze_nt_types.h
@@ -0,0 +1,54 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+
+#ifndef _MBLAZE_NT_TYPES_H
+#define _MBLAZE_NT_TYPES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef char            byte;
+typedef short           half;
+typedef int             word;
+typedef unsigned char   ubyte;
+typedef unsigned short  uhalf;
+typedef unsigned int    uword;
+typedef ubyte           boolean;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/profile.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/profile.h
new file mode 100644
index 0000000000000000000000000000000000000000..4cb07a7d3e230e647f9e6c5dbcb1447be4bfed5a
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/profile.h
@@ -0,0 +1,131 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#ifndef	PROFILE_H
+#define	PROFILE_H	1
+
+#include <stdio.h>
+#include "xil_types.h"
+#include "profile_config.h"
+
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void _system_init( void ) ;
+void _system_clean( void ) ;
+void mcount(u32 frompc, u32 selfpc);
+void profile_intr_handler( void ) ;
+void _profile_init( void );
+
+
+
+/****************************************************************************
+ * Profiling on hardware - Hash table maintained on hardware and data sent
+ * to xmd for gmon.out generation.
+ ****************************************************************************/
+/*
+ * histogram counters are unsigned shorts (according to the kernel).
+ */
+#define	HISTCOUNTER	u16
+
+struct tostruct {
+	u32  selfpc;
+	s32	 count;
+	s16  link;
+	u16	 pad;
+};
+
+struct fromstruct {
+	u32 frompc ;
+	s16 link ;
+	u16 pad ;
+} ;
+
+/*
+ * general rounding functions.
+ */
+#define ROUNDDOWN(x,y)	(((x)/(y))*(y))
+#define ROUNDUP(x,y)	((((x)+(y)-1)/(y))*(y))
+
+/*
+ * The profiling data structures are housed in this structure.
+ */
+struct gmonparam {
+	s32		state;
+
+	/* Histogram Information */
+	u16		*kcount;	/* No. of bins in histogram */
+	u32		kcountsize;	/* Histogram samples */
+
+	/* Call-graph Information */
+	struct fromstruct	*froms;
+	u32		fromssize;
+	struct tostruct		*tos;
+	u32		tossize;
+
+	/* Initialization I/Ps */
+	u32    	lowpc;
+	u32		highpc;
+	u32		textsize;
+	/* u32 		cg_froms, */
+	/* u32 		cg_tos, */
+};
+extern struct gmonparam *_gmonparam;
+extern s32 n_gmon_sections;
+
+/*
+ * Possible states of profiling.
+ */
+#define	GMON_PROF_ON	0
+#define	GMON_PROF_BUSY	1
+#define	GMON_PROF_ERROR	2
+#define	GMON_PROF_OFF	3
+
+/*
+ * Sysctl definitions for extracting profiling information from the kernel.
+ */
+#define	GPROF_STATE	0	/* int: profiling enabling variable */
+#define	GPROF_COUNT	1	/* struct: profile tick count buffer */
+#define	GPROF_FROMS	2	/* struct: from location hash bucket */
+#define	GPROF_TOS	3	/* struct: destination/count structure */
+#define	GPROF_GMONPARAM	4	/* struct: profiling parameters (see above) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 		/* PROFILE_H */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/pwm_recorder.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/pwm_recorder.h
new file mode 100644
index 0000000000000000000000000000000000000000..cedcc1e5074066ee8d882c8034363d639255f7dd
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/pwm_recorder.h
@@ -0,0 +1,79 @@
+
+#ifndef PWM_RECORDER_H
+#define PWM_RECORDER_H
+
+
+/****************** Include Files ********************/
+#include "xil_types.h"
+#include "xstatus.h"
+
+#define PWM_RECORDER_S_AXI_SLV_REG0_OFFSET 0
+#define PWM_RECORDER_S_AXI_SLV_REG1_OFFSET 4
+#define PWM_RECORDER_S_AXI_SLV_REG2_OFFSET 8
+#define PWM_RECORDER_S_AXI_SLV_REG3_OFFSET 12
+
+
+/**************************** Type Definitions *****************************/
+/**
+ *
+ * Write a value to a PWM_RECORDER register. A 32 bit write is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is written.
+ *
+ * @param   BaseAddress is the base address of the PWM_RECORDERdevice.
+ * @param   RegOffset is the register offset from the base to write to.
+ * @param   Data is the data written to the register.
+ *
+ * @return  None.
+ *
+ * @note
+ * C-style signature:
+ * 	void PWM_RECORDER_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
+ *
+ */
+#define PWM_RECORDER_mWriteReg(BaseAddress, RegOffset, Data) \
+  	Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/**
+ *
+ * Read a value from a PWM_RECORDER register. A 32 bit read is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is read from the register. The most significant data
+ * will be read as 0.
+ *
+ * @param   BaseAddress is the base address of the PWM_RECORDER device.
+ * @param   RegOffset is the register offset from the base to write to.
+ *
+ * @return  Data is the data from the register.
+ *
+ * @note
+ * C-style signature:
+ * 	u32 PWM_RECORDER_mReadReg(u32 BaseAddress, unsigned RegOffset)
+ *
+ */
+#define PWM_RECORDER_mReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ****************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the PWM_RECORDER instance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus PWM_RECORDER_Reg_SelfTest(void * baseaddr_p);
+
+#endif // PWM_RECORDER_H
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/pwm_signal_out.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/pwm_signal_out.h
new file mode 100644
index 0000000000000000000000000000000000000000..4a80786f653d5f83b9b3dd6e992e4f6e5afab37a
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/pwm_signal_out.h
@@ -0,0 +1,79 @@
+
+#ifndef PWM_SIGNAL_OUT_H
+#define PWM_SIGNAL_OUT_H
+
+
+/****************** Include Files ********************/
+#include "xil_types.h"
+#include "xstatus.h"
+
+#define PWM_SIGNAL_OUT_S_AXI_SLV_REG0_OFFSET 0
+#define PWM_SIGNAL_OUT_S_AXI_SLV_REG1_OFFSET 4
+#define PWM_SIGNAL_OUT_S_AXI_SLV_REG2_OFFSET 8
+#define PWM_SIGNAL_OUT_S_AXI_SLV_REG3_OFFSET 12
+
+
+/**************************** Type Definitions *****************************/
+/**
+ *
+ * Write a value to a PWM_SIGNAL_OUT register. A 32 bit write is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is written.
+ *
+ * @param   BaseAddress is the base address of the PWM_SIGNAL_OUTdevice.
+ * @param   RegOffset is the register offset from the base to write to.
+ * @param   Data is the data written to the register.
+ *
+ * @return  None.
+ *
+ * @note
+ * C-style signature:
+ * 	void PWM_SIGNAL_OUT_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
+ *
+ */
+#define PWM_SIGNAL_OUT_mWriteReg(BaseAddress, RegOffset, Data) \
+  	Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/**
+ *
+ * Read a value from a PWM_SIGNAL_OUT register. A 32 bit read is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is read from the register. The most significant data
+ * will be read as 0.
+ *
+ * @param   BaseAddress is the base address of the PWM_SIGNAL_OUT device.
+ * @param   RegOffset is the register offset from the base to write to.
+ *
+ * @return  Data is the data from the register.
+ *
+ * @note
+ * C-style signature:
+ * 	u32 PWM_SIGNAL_OUT_mReadReg(u32 BaseAddress, unsigned RegOffset)
+ *
+ */
+#define PWM_SIGNAL_OUT_mReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ****************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the PWM_SIGNAL_OUT instance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus PWM_SIGNAL_OUT_Reg_SelfTest(void * baseaddr_p);
+
+#endif // PWM_SIGNAL_OUT_H
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/sleep.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/sleep.h
new file mode 100644
index 0000000000000000000000000000000000000000..27add66057b8dcbf8e137ed34844d58969fcb12f
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/sleep.h
@@ -0,0 +1,50 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#ifndef SLEEP_H
+#define SLEEP_H
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int usleep(unsigned long useconds);
+unsigned sleep(unsigned int seconds);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/smc.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/smc.h
new file mode 100644
index 0000000000000000000000000000000000000000..5a4d33608256f53d59b1c6470b9627803ea20b55
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/smc.h
@@ -0,0 +1,114 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file smc.h
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  11/03/09 Initial release.
+* 4.2	pkp	 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
+*					  as smc.c is removed
+* </pre>
+*
+* @note		None.
+*
+******************************************************************************/
+
+#ifndef SMC_H /* prevent circular inclusions */
+#define SMC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xil_io.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Memory controller configuration register offset */
+#define XSMCPSS_MC_STATUS		0x000U	/* Controller status reg, RO */
+#define XSMCPSS_MC_INTERFACE_CONFIG	0x004U	/* Interface config reg, RO */
+#define XSMCPSS_MC_SET_CONFIG		0x008U	/* Set configuration reg, WO */
+#define XSMCPSS_MC_CLR_CONFIG		0x00CU	/* Clear config reg, WO */
+#define XSMCPSS_MC_DIRECT_CMD		0x010U	/* Direct command reg, WO */
+#define XSMCPSS_MC_SET_CYCLES		0x014U	/* Set cycles register, WO */
+#define XSMCPSS_MC_SET_OPMODE		0x018U	/* Set opmode register, WO */
+#define XSMCPSS_MC_REFRESH_PERIOD_0	0x020U	/* Refresh period_0 reg, RW */
+#define XSMCPSS_MC_REFRESH_PERIOD_1	0x024U	/* Refresh period_1 reg, RW */
+
+/* Chip select configuration register offset */
+#define XSMCPSS_CS_IF0_CHIP_0_OFFSET	0x100U	/* Interface 0 chip 0 config */
+#define XSMCPSS_CS_IF0_CHIP_1_OFFSET	0x120U	/* Interface 0 chip 1 config */
+#define XSMCPSS_CS_IF0_CHIP_2_OFFSET	0x140U	/* Interface 0 chip 2 config */
+#define XSMCPSS_CS_IF0_CHIP_3_OFFSET	0x160U	/* Interface 0 chip 3 config */
+#define XSMCPSS_CS_IF1_CHIP_0_OFFSET	0x180U	/* Interface 1 chip 0 config */
+#define XSMCPSS_CS_IF1_CHIP_1_OFFSET	0x1A0U	/* Interface 1 chip 1 config */
+#define XSMCPSS_CS_IF1_CHIP_2_OFFSET	0x1C0U	/* Interface 1 chip 2 config */
+#define XSMCPSS_CS_IF1_CHIP_3_OFFSET	0x1E0U	/* Interface 1 chip 3 config */
+
+/* User configuration register offset */
+#define XSMCPSS_UC_STATUS_OFFSET	0x200U	/* User status reg, RO */
+#define XSMCPSS_UC_CONFIG_OFFSET	0x204U	/* User config reg, WO */
+
+/* Integration test register offset */
+#define XSMCPSS_IT_OFFSET		0xE00U
+
+/* ID configuration register offset */
+#define XSMCPSS_ID_PERIP_0_OFFSET	0xFE0U
+#define XSMCPSS_ID_PERIP_1_OFFSET	0xFE4U
+#define XSMCPSS_ID_PERIP_2_OFFSET	0xFE8U
+#define XSMCPSS_ID_PERIP_3_OFFSET	0xFECU
+#define XSMCPSS_ID_PCELL_0_OFFSET	0xFF0U
+#define XSMCPSS_ID_PCELL_1_OFFSET	0xFF4U
+#define XSMCPSS_ID_PCELL_2_OFFSET	0xFF8U
+#define XSMCPSS_ID_PCELL_3_OFFSET	0xFFCU
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* SMC_H */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/vectors.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/vectors.h
new file mode 100644
index 0000000000000000000000000000000000000000..bb599b5602601d799de56541046a0530075fedff
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/vectors.h
@@ -0,0 +1,88 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file vectors.h
+*
+* This file contains the C level vector prototypes for the ARM Cortex A9 core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/10 Initial version, moved over from bsp area
+* 6.0   mus  07/27/16 Consolidated vectors for a9,a53 and r5 processors
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _VECTORS_H_
+#define _VECTORS_H_
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void FIQInterrupt(void);
+void IRQInterrupt(void);
+#if !defined (__aarch64__)
+void SWInterrupt(void);
+void DataAbortInterrupt(void);
+void PrefetchAbortInterrupt(void);
+void UndefinedException(void);
+#else
+void SynchronousInterrupt(void);
+void SErrorInterrupt(void);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xadcps.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xadcps.h
new file mode 100644
index 0000000000000000000000000000000000000000..9b6737d3729f8b34b97c66fc97d503aa7facc9da
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xadcps.h
@@ -0,0 +1,589 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps.h
+* @addtogroup xadcps_v2_2
+* @{
+* @details
+*
+* The XAdcPs driver supports the Xilinx XADC/ADC device.
+*
+* The XADC/ADC device has the following features:
+*	- 10-bit, 200-KSPS (kilo samples per second)
+*		Analog-to-Digital Converter (ADC)
+*	- Monitoring of on-chip supply voltages and temperature
+*	- 1 dedicated differential analog-input pair and
+*	  16 auxiliary differential analog-input pairs
+*	- Automatic alarms based on user defined limits for the on-chip
+*	  supply voltages and temperature
+*	- Automatic Channel Sequencer, programmable averaging, programmable
+*	  acquisition time for the external inputs, unipolar or differential
+*	  input selection for the external inputs
+*	- Inbuilt Calibration
+*	- Optional interrupt request generation
+*
+*
+* The user should refer to the hardware device specification for detailed
+* information about the device.
+*
+* This header file contains the prototypes of driver functions that can
+* be used to access the XADC/ADC device.
+*
+*
+* <b> XADC Channel Sequencer Modes </b>
+*
+* The  XADC Channel Sequencer supports the following operating modes:
+*
+*   - <b> Default </b>: This is the default mode after power up.
+*		In this mode of operation the XADC operates in
+*		a sequence mode, monitoring the on chip sensors:
+*		Temperature, VCCINT, and VCCAUX.
+*   - <b> One pass through sequence </b>: In this mode the XADC
+*		converts the channels enabled in the Sequencer Channel Enable
+*		registers for a single pass and then stops.
+*   - <b> Continuous cycling of sequence </b>: In this mode the XADC
+*		converts the channels enabled in the Sequencer Channel Enable
+*		registers continuously.
+*   - <b> Single channel mode</b>: In this mode the XADC Channel
+*		Sequencer is disabled and the XADC operates in a
+*		Single Channel Mode.
+*		The XADC can operate either in a Continuous or Event
+*		driven sampling mode in the single channel mode.
+*   - <b> Simultaneous Sampling Mode</b>: In this mode the XADC Channel
+*		Sequencer will automatically sequence through eight fixed pairs
+*		of auxiliary analog input channels for simulataneous conversion.
+*   - <b> Independent ADC mode</b>: In this mode the first ADC (A) is used to
+*		is used to implement a fixed monitoring mode similar to the
+*		default mode but the alarm fucntions ar eenabled.
+*		The second ADC (B) is available to be used with external analog
+*		input channels only.
+*
+* Read the XADC spec for more information about the sequencer modes.
+*
+* <b> Initialization and Configuration </b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the XADC/ADC device.
+*
+* XAdcPs_CfgInitialize() API is used to initialize the XADC/ADC
+* device. The user needs to first call the XAdcPs_LookupConfig() API which
+* returns the Configuration structure pointer which is passed as a parameter to
+* the XAdcPs_CfgInitialize() API.
+*
+*
+* <b>Interrupts</b>
+*
+* The XADC/ADC device supports interrupt driven mode and the default
+* operation mode is polling mode.
+*
+* The interrupt mode is available only if hardware is configured to support
+* interrupts.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* device in interrupt mode.
+*
+*
+* <b> Virtual Memory </b>
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+*
+* <b> Threads </b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+*
+* <b> Asserts </b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+*
+* <b> Building the driver </b>
+*
+* The XAdcPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* <b> Limitations of the driver </b>
+*
+* XADC/ADC device can be accessed through the JTAG port and the PLB
+* interface. The driver implementation does not support the simultaneous access
+* of the device by both these interfaces. The user has to care of this situation
+* in the user application code.
+*
+* <br><br>
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI xadc driver
+* 1.01a bss    02/18/13	Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
+*			XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
+*			in xadcps.c to fix CR #693371
+* 1.03a bss    11/01/13 Modified xadcps_hw.h to use correct Register offsets
+*			CR#749687
+* 2.1   bss    08/05/14 Added declarations for XAdcPs_SetSequencerEvent,
+*			XAdcPs_GetSamplingMode, XAdcPs_SetMuxMode,
+*			XAdcPs_SetPowerdownMode and XAdcPs_GetPowerdownMode
+*			functions.
+*			Modified Assert for XAdcPs_SetSingleChParams in
+*			xadcps.c to fix CR #807563.
+* 2.2   bss    04/27/14 Modified to use correct Device Config base address in
+*						xadcps.c (CR#854437).
+*       ms     01/23/17 Added xil_printf statement in main function for all
+*                       examples to ensure that "Successfully ran" and "Failed"
+*                       strings are available in all examples. This is a fix
+*                       for CR-965028.
+*       ms     03/17/17 Added readme.txt file in examples folder for doxygen
+*                       generation.
+*
+*
+* </pre>
+*
+*****************************************************************************/
+#ifndef XADCPS_H /* Prevent circular inclusions */
+#define XADCPS_H /* by using protection macros  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xadcps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**
+ * @name Indexes for the different channels.
+ * @{
+ */
+#define XADCPS_CH_TEMP		0x0  /**< On Chip Temperature */
+#define XADCPS_CH_VCCINT	0x1  /**< VCCINT */
+#define XADCPS_CH_VCCAUX	0x2  /**< VCCAUX */
+#define XADCPS_CH_VPVN		0x3  /**< VP/VN Dedicated analog inputs */
+#define XADCPS_CH_VREFP		0x4  /**< VREFP */
+#define XADCPS_CH_VREFN		0x5  /**< VREFN */
+#define XADCPS_CH_VBRAM		0x6  /**< On-chip VBRAM Data Reg, 7 series */
+#define XADCPS_CH_SUPPLY_CALIB	0x07 /**< Supply Calib Data Reg */
+#define XADCPS_CH_ADC_CALIB	0x08 /**< ADC Offset Channel Reg */
+#define XADCPS_CH_GAINERR_CALIB 0x09 /**< Gain Error Channel Reg  */
+#define XADCPS_CH_VCCPINT	0x0D /**< On-chip PS VCCPINT Channel , Zynq */
+#define XADCPS_CH_VCCPAUX	0x0E /**< On-chip PS VCCPAUX Channel , Zynq */
+#define XADCPS_CH_VCCPDRO	0x0F /**< On-chip PS VCCPDRO Channel , Zynq */
+#define XADCPS_CH_AUX_MIN	 16 /**< Channel number for 1st Aux Channel */
+#define XADCPS_CH_AUX_MAX	 31 /**< Channel number for Last Aux channel */
+
+/*@}*/
+
+
+/**
+ * @name Indexes for reading the Calibration Coefficient Data.
+ * @{
+ */
+#define XADCPS_CALIB_SUPPLY_COEFF     0 /**< Supply Offset Calib Coefficient */
+#define XADCPS_CALIB_ADC_COEFF        1 /**< ADC Offset Calib Coefficient */
+#define XADCPS_CALIB_GAIN_ERROR_COEFF 2 /**< Gain Error Calib Coefficient*/
+/*@}*/
+
+
+/**
+ * @name Indexes for reading the Minimum/Maximum Measurement Data.
+ * @{
+ */
+#define XADCPS_MAX_TEMP		0 /**< Maximum Temperature Data */
+#define XADCPS_MAX_VCCINT	1 /**< Maximum VCCINT Data */
+#define XADCPS_MAX_VCCAUX	2 /**< Maximum VCCAUX Data */
+#define XADCPS_MAX_VBRAM	3 /**< Maximum VBRAM Data */
+#define XADCPS_MIN_TEMP		4 /**< Minimum Temperature Data */
+#define XADCPS_MIN_VCCINT	5 /**< Minimum VCCINT Data */
+#define XADCPS_MIN_VCCAUX	6 /**< Minimum VCCAUX Data */
+#define XADCPS_MIN_VBRAM	7 /**< Minimum VBRAM Data */
+#define XADCPS_MAX_VCCPINT	8 /**< Maximum VCCPINT Register , Zynq */
+#define XADCPS_MAX_VCCPAUX	9 /**< Maximum VCCPAUX Register , Zynq */
+#define XADCPS_MAX_VCCPDRO	0xA /**< Maximum VCCPDRO Register , Zynq */
+#define XADCPS_MIN_VCCPINT	0xC /**< Minimum VCCPINT Register , Zynq */
+#define XADCPS_MIN_VCCPAUX	0xD /**< Minimum VCCPAUX Register , Zynq */
+#define XADCPS_MIN_VCCPDRO	0xE /**< Minimum VCCPDRO Register , Zynq */
+
+/*@}*/
+
+
+/**
+ * @name Alarm Threshold(Limit) Register (ATR) indexes.
+ * @{
+ */
+#define XADCPS_ATR_TEMP_UPPER	 0 /**< High user Temperature */
+#define XADCPS_ATR_VCCINT_UPPER  1 /**< VCCINT high voltage limit register */
+#define XADCPS_ATR_VCCAUX_UPPER  2 /**< VCCAUX high voltage limit register */
+#define XADCPS_ATR_OT_UPPER	 3 /**< VCCAUX high voltage limit register */
+#define XADCPS_ATR_TEMP_LOWER	 4 /**< Upper Over Temperature limit Reg */
+#define XADCPS_ATR_VCCINT_LOWER	 5 /**< VCCINT high voltage limit register */
+#define XADCPS_ATR_VCCAUX_LOWER	 6 /**< VCCAUX low voltage limit register  */
+#define XADCPS_ATR_OT_LOWER	 7 /**< Lower Over Temperature limit */
+#define XADCPS_ATR_VBRAM_UPPER_  8 /**< VRBAM Upper Alarm Reg, 7 Series */
+#define XADCPS_ATR_VCCPINT_UPPER 9 /**< VCCPINT Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VCCPAUX_UPPER 0xA /**< VCCPAUX Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VCCPDRO_UPPER 0xB /**< VCCPDRO Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VBRAM_LOWER	 0xC /**< VRBAM Lower Alarm Reg, 7 Series */
+#define XADCPS_ATR_VCCPINT_LOWER 0xD /**< VCCPINT Lower Alarm Reg , Zynq */
+#define XADCPS_ATR_VCCPAUX_LOWER 0xE /**< VCCPAUX Lower Alarm Reg , Zynq */
+#define XADCPS_ATR_VCCPDRO_LOWER 0xF /**< VCCPDRO Lower Alarm Reg , Zynq */
+
+/*@}*/
+
+
+/**
+ * @name Averaging to be done for the channels.
+ * @{
+ */
+#define XADCPS_AVG_0_SAMPLES	0  /**< No Averaging */
+#define XADCPS_AVG_16_SAMPLES	1  /**< Average 16 samples */
+#define XADCPS_AVG_64_SAMPLES	2  /**< Average 64 samples */
+#define XADCPS_AVG_256_SAMPLES	3  /**< Average 256 samples */
+
+/*@}*/
+
+
+/**
+ * @name Channel Sequencer Modes of operation
+ * @{
+ */
+#define XADCPS_SEQ_MODE_SAFE		0  /**< Default Safe Mode */
+#define XADCPS_SEQ_MODE_ONEPASS		1  /**< Onepass through Sequencer */
+#define XADCPS_SEQ_MODE_CONTINPASS	2  /**< Continuous Cycling Sequencer */
+#define XADCPS_SEQ_MODE_SINGCHAN	3  /**< Single channel -No Sequencing */
+#define XADCPS_SEQ_MODE_SIMUL_SAMPLING	4  /**< Simultaneous sampling */
+#define XADCPS_SEQ_MODE_INDEPENDENT	8  /**< Independent mode */
+
+/*@}*/
+
+
+
+/**
+ * @name Power Down Modes
+ * @{
+ */
+#define XADCPS_PD_MODE_NONE		0  /**< No Power Down  */
+#define XADCPS_PD_MODE_ADCB		1  /**< Power Down ADC B */
+#define XADCPS_PD_MODE_XADC		2  /**< Power Down ADC A and ADC B */
+/*@}*/
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the XADC/ADC
+ * device.
+ */
+typedef struct {
+	u16  DeviceId;		/**< Unique ID of device */
+	u32  BaseAddress;	/**< Device base address */
+} XAdcPs_Config;
+
+
+/**
+ * The driver's instance data. The user is required to allocate a variable
+ * of this type for every XADC/ADC device in the system. A pointer to
+ * a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XAdcPs_Config Config;	/**< XAdcPs_Config of current device */
+	u32  IsReady;		/**< Device is initialized and ready  */
+
+} XAdcPs;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the XADC device is in Event Sampling mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+*		- TRUE if the device is in Event Sampling Mode.
+*		- FALSE if the device is in Continuous Sampling Mode.
+*
+* @note		C-Style signature:
+*		int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_IsEventSamplingModeSet(InstancePtr)			\
+	(((XAdcPs_ReadInternalReg(InstancePtr,	 			\
+			XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ?	\
+			TRUE : FALSE))
+
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the XADC device is in External Mux mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+*		- TRUE if the device is in External Mux Mode.
+*		- FALSE if the device is NOT in External Mux Mode.
+*
+* @note		C-Style signature:
+*		int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_IsExternalMuxModeSet(InstancePtr)			\
+	(((XAdcPs_ReadInternalReg(InstancePtr,	 			\
+			XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ?	\
+			TRUE : FALSE))
+
+/****************************************************************************/
+/**
+*
+* This macro converts XADC Raw Data to Temperature(centigrades).
+*
+* @param	AdcData is the Raw ADC Data from XADC.
+*
+* @return 	The Temperature in centigrades.
+*
+* @note		C-Style signature:
+*		float XAdcPs_RawToTemperature(u32 AdcData);
+*
+*****************************************************************************/
+#define XAdcPs_RawToTemperature(AdcData)				\
+	((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts XADC/ADC Raw Data to Voltage(volts).
+*
+* @param	AdcData is the XADC/ADC Raw Data.
+*
+* @return 	The Voltage in volts.
+*
+* @note		C-Style signature:
+*		float XAdcPs_RawToVoltage(u32 AdcData);
+*
+*****************************************************************************/
+#define XAdcPs_RawToVoltage(AdcData) 					\
+	((((float)(AdcData))* (3.0f))/65536.0f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts Temperature in centigrades to XADC/ADC Raw Data.
+*
+* @param	Temperature is the Temperature in centigrades to be
+*		converted to XADC/ADC Raw Data.
+*
+* @return 	The XADC/ADC Raw Data.
+*
+* @note		C-Style signature:
+*		int XAdcPs_TemperatureToRaw(float Temperature);
+*
+*****************************************************************************/
+#define XAdcPs_TemperatureToRaw(Temperature)				\
+	((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f))
+
+/****************************************************************************/
+/**
+*
+* This macro converts Voltage in Volts to XADC/ADC Raw Data.
+*
+* @param	Voltage is the Voltage in volts to be converted to
+*		XADC/ADC Raw Data.
+*
+* @return 	The XADC/ADC Raw Data.
+*
+* @note		C-Style signature:
+*		int XAdcPs_VoltageToRaw(float Voltage);
+*
+*****************************************************************************/
+#define XAdcPs_VoltageToRaw(Voltage)			 		\
+	((int)((Voltage)*65536.0f/3.0f))
+
+
+/****************************************************************************/
+/**
+*
+* This macro is used for writing to the XADC Registers using the
+* command FIFO.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data);
+*
+*****************************************************************************/
+#define XAdcPs_WriteFifo(InstancePtr, Data)				\
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,		\
+			  XADCPS_CMDFIFO_OFFSET, Data);
+
+
+/****************************************************************************/
+/**
+*
+* This macro is used for reading from the XADC Registers using the
+* data FIFO.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	Data read from the FIFO
+*
+* @note		C-Style signature:
+*		u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_ReadFifo(InstancePtr)				\
+	XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,	\
+			  XADCPS_RDFIFO_OFFSET);
+
+
+/************************** Function Prototypes *****************************/
+
+
+
+/**
+ * Functions in xadcps_sinit.c
+ */
+XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId);
+
+/**
+ * Functions in xadcps.c
+ */
+int XAdcPs_CfgInitialize(XAdcPs *InstancePtr,
+				XAdcPs_Config *ConfigPtr,
+				u32 EffectiveAddr);
+
+
+u32 XAdcPs_GetStatus(XAdcPs *InstancePtr);
+
+u32 XAdcPs_GetAlarmOutputStatus(XAdcPs *InstancePtr);
+
+void XAdcPs_StartAdcConversion(XAdcPs *InstancePtr);
+
+void XAdcPs_Reset(XAdcPs *InstancePtr);
+
+u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel);
+
+u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType);
+
+u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType);
+
+void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average);
+u8 XAdcPs_GetAvg(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
+				u8 Channel,
+				int IncreaseAcqCycles,
+				int IsEventMode,
+				int IsDifferentialMode);
+
+
+void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask);
+u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr);
+
+void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration);
+u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr);
+
+void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode);
+u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr);
+
+void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor);
+u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask);
+u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask);
+u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask);
+u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask);
+u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr);
+
+void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value);
+u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg);
+
+void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr);
+void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr);
+
+void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode);
+
+int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr);
+
+void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel);
+
+void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode);
+
+u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr);
+
+/**
+ * Functions in xadcps_selftest.c
+ */
+int XAdcPs_SelfTest(XAdcPs *InstancePtr);
+
+/**
+ * Functions in xadcps_intr.c
+ */
+void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask);
+void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask);
+u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr);
+
+u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr);
+void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* End of protection macro. */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xadcps_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xadcps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..55a47a440a6a9933952aa7d70ad73b5e198c689b
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xadcps_hw.h
@@ -0,0 +1,502 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps_hw.h
+* @addtogroup xadcps_v2_2
+* @{
+*
+* This header file contains identifiers and basic driver functions (or
+* macros) that can be used to access the XADC device through the Device
+* Config Interface of the Zynq.
+*
+*
+* Refer to the device specification for more information about this driver.
+*
+* @note	 None.
+*
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss    12/22/11 First release based on the XPS/AXI xadc driver
+* 1.03a bss    11/01/13 Modified macros to use correct Register offsets
+*			CR#749687
+*
+* </pre>
+*
+*****************************************************************************/
+#ifndef XADCPS_HW_H /* Prevent circular inclusions */
+#define XADCPS_HW_H /* by using protection macros  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**@name Register offsets of XADC in the Device Config
+ *
+ * The following constants provide access to each of the registers of the
+ * XADC device.
+ * @{
+ */
+
+#define XADCPS_CFG_OFFSET	 0x00 /**< Configuration Register */
+#define XADCPS_INT_STS_OFFSET	 0x04 /**< Interrupt Status Register */
+#define XADCPS_INT_MASK_OFFSET	 0x08 /**< Interrupt Mask Register */
+#define XADCPS_MSTS_OFFSET	 0x0C /**< Misc status register */
+#define XADCPS_CMDFIFO_OFFSET	 0x10 /**< Command FIFO Register */
+#define XADCPS_RDFIFO_OFFSET	 0x14 /**< Read FIFO Register */
+#define XADCPS_MCTL_OFFSET	 0x18 /**< Misc control register */
+
+/* @} */
+
+
+
+
+
+/** @name XADC Config Register Bit definitions
+  * @{
+ */
+#define XADCPS_CFG_ENABLE_MASK	 0x80000000 /**< Enable access from PS mask */
+#define XADCPS_CFG_CFIFOTH_MASK  0x00F00000 /**< Command FIFO Threshold mask */
+#define XADCPS_CFG_DFIFOTH_MASK  0x000F0000 /**< Data FIFO Threshold mask */
+#define XADCPS_CFG_WEDGE_MASK	 0x00002000 /**< Write Edge Mask */
+#define XADCPS_CFG_REDGE_MASK	 0x00001000 /**< Read Edge Mask */
+#define XADCPS_CFG_TCKRATE_MASK  0x00000300 /**< Clock freq control */
+#define XADCPS_CFG_IGAP_MASK	 0x0000001F /**< Idle Gap between
+						* successive commands */
+/* @} */
+
+
+/** @name XADC Interrupt Status/Mask Register Bit definitions
+  *
+  * The definitions are same for the Interrupt Status Register and
+  * Interrupt Mask Register. They are defined only once.
+  * @{
+ */
+#define XADCPS_INTX_ALL_MASK   	   0x000003FF /**< Alarm Signals Mask  */
+#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200 /**< CMD FIFO less than threshold */
+#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100 /**< Data FIFO greater than threshold */
+#define XADCPS_INTX_OT_MASK	   0x00000080 /**< Over temperature Alarm Status */
+#define XADCPS_INTX_ALM_ALL_MASK   0x0000007F /**< Alarm Signals Mask  */
+#define XADCPS_INTX_ALM6_MASK	   0x00000040 /**< Alarm 6 Mask  */
+#define XADCPS_INTX_ALM5_MASK	   0x00000020 /**< Alarm 5 Mask  */
+#define XADCPS_INTX_ALM4_MASK	   0x00000010 /**< Alarm 4 Mask  */
+#define XADCPS_INTX_ALM3_MASK	   0x00000008 /**< Alarm 3 Mask  */
+#define XADCPS_INTX_ALM2_MASK	   0x00000004 /**< Alarm 2 Mask  */
+#define XADCPS_INTX_ALM1_MASK	   0x00000002 /**< Alarm 1 Mask  */
+#define XADCPS_INTX_ALM0_MASK	   0x00000001 /**< Alarm 0 Mask  */
+
+/* @} */
+
+
+/** @name XADC Miscellaneous Register Bit definitions
+  * @{
+ */
+#define XADCPS_MSTS_CFIFO_LVL_MASK  0x000F0000 /**< Command FIFO Level mask */
+#define XADCPS_MSTS_DFIFO_LVL_MASK  0x0000F000 /**< Data FIFO Level Mask  */
+#define XADCPS_MSTS_CFIFOF_MASK     0x00000800 /**< Command FIFO Full Mask  */
+#define XADCPS_MSTS_CFIFOE_MASK     0x00000400 /**< Command FIFO Empty Mask  */
+#define XADCPS_MSTS_DFIFOF_MASK     0x00000200 /**< Data FIFO Full Mask  */
+#define XADCPS_MSTS_DFIFOE_MASK     0x00000100 /**< Data FIFO Empty Mask  */
+#define XADCPS_MSTS_OT_MASK	    0x00000080 /**< Over Temperature Mask */
+#define XADCPS_MSTS_ALM_MASK	    0x0000007F /**< Alarms Mask  */
+/* @} */
+
+
+/** @name XADC Miscellaneous Control Register Bit definitions
+  * @{
+ */
+#define XADCPS_MCTL_RESET_MASK      0x00000010 /**< Reset XADC */
+#define XADCPS_MCTL_FLUSH_MASK      0x00000001 /**< Flush the FIFOs */
+/* @} */
+
+
+/**@name Internal Register offsets of the XADC
+ *
+ * The following constants provide access to each of the internal registers of
+ * the XADC device.
+ * @{
+ */
+
+/*
+ * XADC Internal Channel Registers
+ */
+#define XADCPS_TEMP_OFFSET		  0x00 /**< On-chip Temperature Reg */
+#define XADCPS_VCCINT_OFFSET		  0x01 /**< On-chip VCCINT Data Reg */
+#define XADCPS_VCCAUX_OFFSET		  0x02 /**< On-chip VCCAUX Data Reg */
+#define XADCPS_VPVN_OFFSET		  0x03 /**< ADC out of VP/VN	   */
+#define XADCPS_VREFP_OFFSET		  0x04 /**< On-chip VREFP Data Reg */
+#define XADCPS_VREFN_OFFSET		  0x05 /**< On-chip VREFN Data Reg */
+#define XADCPS_VBRAM_OFFSET		  0x06 /**< On-chip VBRAM , 7 Series */
+#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET  0x08 /**< ADC A Supply Offset Reg */
+#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET  0x09 /**< ADC A Offset Data Reg */
+#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0A /**< ADC A Gain Error Reg  */
+#define XADCPS_VCCPINT_OFFSET		  0x0D /**< On-chip VCCPINT Reg, Zynq */
+#define XADCPS_VCCPAUX_OFFSET		  0x0E /**< On-chip VCCPAUX Reg, Zynq */
+#define XADCPS_VCCPDRO_OFFSET		  0x0F /**< On-chip VCCPDRO Reg, Zynq */
+
+/*
+ * XADC External Channel Registers
+ */
+#define XADCPS_AUX00_OFFSET	0x10 /**< ADC out of VAUXP0/VAUXN0 */
+#define XADCPS_AUX01_OFFSET	0x11 /**< ADC out of VAUXP1/VAUXN1 */
+#define XADCPS_AUX02_OFFSET	0x12 /**< ADC out of VAUXP2/VAUXN2 */
+#define XADCPS_AUX03_OFFSET	0x13 /**< ADC out of VAUXP3/VAUXN3 */
+#define XADCPS_AUX04_OFFSET	0x14 /**< ADC out of VAUXP4/VAUXN4 */
+#define XADCPS_AUX05_OFFSET	0x15 /**< ADC out of VAUXP5/VAUXN5 */
+#define XADCPS_AUX06_OFFSET	0x16 /**< ADC out of VAUXP6/VAUXN6 */
+#define XADCPS_AUX07_OFFSET	0x17 /**< ADC out of VAUXP7/VAUXN7 */
+#define XADCPS_AUX08_OFFSET	0x18 /**< ADC out of VAUXP8/VAUXN8 */
+#define XADCPS_AUX09_OFFSET	0x19 /**< ADC out of VAUXP9/VAUXN9 */
+#define XADCPS_AUX10_OFFSET	0x1A /**< ADC out of VAUXP10/VAUXN10 */
+#define XADCPS_AUX11_OFFSET	0x1B /**< ADC out of VAUXP11/VAUXN11 */
+#define XADCPS_AUX12_OFFSET	0x1C /**< ADC out of VAUXP12/VAUXN12 */
+#define XADCPS_AUX13_OFFSET	0x1D /**< ADC out of VAUXP13/VAUXN13 */
+#define XADCPS_AUX14_OFFSET	0x1E /**< ADC out of VAUXP14/VAUXN14 */
+#define XADCPS_AUX15_OFFSET	0x1F /**< ADC out of VAUXP15/VAUXN15 */
+
+/*
+ * XADC Registers for Maximum/Minimum data captured for the
+ * on chip Temperature/VCCINT/VCCAUX data.
+ */
+#define XADCPS_MAX_TEMP_OFFSET		0x20 /**< Max Temperature Reg */
+#define XADCPS_MAX_VCCINT_OFFSET	0x21 /**< Max VCCINT Register */
+#define XADCPS_MAX_VCCAUX_OFFSET	0x22 /**< Max VCCAUX Register */
+#define XADCPS_MAX_VCCBRAM_OFFSET	0x23 /**< Max BRAM Register, 7 series */
+#define XADCPS_MIN_TEMP_OFFSET		0x24 /**< Min Temperature Reg */
+#define XADCPS_MIN_VCCINT_OFFSET	0x25 /**< Min VCCINT Register */
+#define XADCPS_MIN_VCCAUX_OFFSET	0x26 /**< Min VCCAUX Register */
+#define XADCPS_MIN_VCCBRAM_OFFSET	0x27 /**< Min BRAM Register, 7 series */
+#define XADCPS_MAX_VCCPINT_OFFSET	0x28 /**< Max VCCPINT Register, Zynq */
+#define XADCPS_MAX_VCCPAUX_OFFSET	0x29 /**< Max VCCPAUX Register, Zynq */
+#define XADCPS_MAX_VCCPDRO_OFFSET	0x2A /**< Max VCCPDRO Register, Zynq */
+#define XADCPS_MIN_VCCPINT_OFFSET	0x2C /**< Min VCCPINT Register, Zynq */
+#define XADCPS_MIN_VCCPAUX_OFFSET	0x2D /**< Min VCCPAUX Register, Zynq */
+#define XADCPS_MIN_VCCPDRO_OFFSET	0x2E /**< Min VCCPDRO Register,Zynq */
+ /* Undefined 0x2F to 0x3E */
+#define XADCPS_FLAG_OFFSET		0x3F /**< Flag Register */
+
+/*
+ * XADC Configuration Registers
+ */
+#define XADCPS_CFR0_OFFSET	0x40	/**< Configuration Register 0 */
+#define XADCPS_CFR1_OFFSET	0x41	/**< Configuration Register 1 */
+#define XADCPS_CFR2_OFFSET	0x42	/**< Configuration Register 2 */
+
+/* Test Registers 0x43 to 0x47 */
+
+/*
+ * XADC Sequence Registers
+ */
+#define XADCPS_SEQ00_OFFSET	0x48 /**< Seq Reg 00 Adc Channel Selection */
+#define XADCPS_SEQ01_OFFSET	0x49 /**< Seq Reg 01 Adc Channel Selection */
+#define XADCPS_SEQ02_OFFSET	0x4A /**< Seq Reg 02 Adc Average Enable */
+#define XADCPS_SEQ03_OFFSET	0x4B /**< Seq Reg 03 Adc Average Enable */
+#define XADCPS_SEQ04_OFFSET	0x4C /**< Seq Reg 04 Adc Input Mode Select */
+#define XADCPS_SEQ05_OFFSET	0x4D /**< Seq Reg 05 Adc Input Mode Select */
+#define XADCPS_SEQ06_OFFSET	0x4E /**< Seq Reg 06 Adc Acquisition Select */
+#define XADCPS_SEQ07_OFFSET	0x4F /**< Seq Reg 07 Adc Acquisition Select */
+
+/*
+ * XADC Alarm Threshold/Limit Registers (ATR)
+ */
+#define XADCPS_ATR_TEMP_UPPER_OFFSET	0x50 /**< Temp Upper Alarm Register */
+#define XADCPS_ATR_VCCINT_UPPER_OFFSET	0x51 /**< VCCINT Upper Alarm Reg */
+#define XADCPS_ATR_VCCAUX_UPPER_OFFSET	0x52 /**< VCCAUX Upper Alarm Reg */
+#define XADCPS_ATR_OT_UPPER_OFFSET	0x53 /**< Over Temp Upper Alarm Reg */
+#define XADCPS_ATR_TEMP_LOWER_OFFSET	0x54 /**< Temp Lower Alarm Register */
+#define XADCPS_ATR_VCCINT_LOWER_OFFSET	0x55 /**< VCCINT Lower Alarm Reg */
+#define XADCPS_ATR_VCCAUX_LOWER_OFFSET	0x56 /**< VCCAUX Lower Alarm Reg */
+#define XADCPS_ATR_OT_LOWER_OFFSET	0x57 /**< Over Temp Lower Alarm Reg */
+#define XADCPS_ATR_VBRAM_UPPER_OFFSET	0x58 /**< VBRAM Upper Alarm, 7 series */
+#define XADCPS_ATR_VCCPINT_UPPER_OFFSET	0x59 /**< VCCPINT Upper Alarm, Zynq */
+#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET	0x5A /**< VCCPAUX Upper Alarm, Zynq */
+#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET	0x5B /**< VCCPDRO Upper Alarm, Zynq */
+#define XADCPS_ATR_VBRAM_LOWER_OFFSET	0x5C /**< VRBAM Lower Alarm, 7 Series */
+#define XADCPS_ATR_VCCPINT_LOWER_OFFSET	0x5D /**< VCCPINT Lower Alarm, Zynq */
+#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET	0x5E /**< VCCPAUX Lower Alarm, Zynq */
+#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET	0x5F /**< VCCPDRO Lower Alarm, Zynq */
+
+/* Undefined 0x60 to 0x7F */
+
+/*@}*/
+
+
+
+/**
+ * @name Configuration Register 0 (CFR0) mask(s)
+ * @{
+ */
+#define XADCPS_CFR0_CAL_AVG_MASK	0x8000 /**< Averaging enable Mask */
+#define XADCPS_CFR0_AVG_VALID_MASK	0x3000 /**< Averaging bit Mask */
+#define XADCPS_CFR0_AVG1_MASK		0x0000 /**< No Averaging */
+#define XADCPS_CFR0_AVG16_MASK		0x1000 /**< Average 16 samples */
+#define XADCPS_CFR0_AVG64_MASK	 	0x2000 /**< Average 64 samples */
+#define XADCPS_CFR0_AVG256_MASK 	0x3000 /**< Average 256 samples */
+#define XADCPS_CFR0_AVG_SHIFT	 	12     /**< Averaging bits shift */
+#define XADCPS_CFR0_MUX_MASK	 	0x0800 /**< External Mask Enable */
+#define XADCPS_CFR0_DU_MASK	 	0x0400 /**< Bipolar/Unipolar mode */
+#define XADCPS_CFR0_EC_MASK	 	0x0200 /**< Event driven/
+						 *  Continuous mode selection
+						 */
+#define XADCPS_CFR0_ACQ_MASK	 	0x0100 /**< Add acquisition by 6 ADCCLK */
+#define XADCPS_CFR0_CHANNEL_MASK	0x001F /**< Channel number bit Mask */
+
+/*@}*/
+
+/**
+ * @name Configuration Register 1 (CFR1) mask(s)
+ * @{
+ */
+#define XADCPS_CFR1_SEQ_VALID_MASK	  0xF000 /**< Sequence bit Mask */
+#define XADCPS_CFR1_SEQ_SAFEMODE_MASK	  0x0000 /**< Default Safe Mode */
+#define XADCPS_CFR1_SEQ_ONEPASS_MASK	  0x1000 /**< Onepass through Seq */
+#define XADCPS_CFR1_SEQ_CONTINPASS_MASK	     0x2000 /**< Continuous Cycling Seq */
+#define XADCPS_CFR1_SEQ_SINGCHAN_MASK	     0x3000 /**< Single channel - No Seq */
+#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK  0x4000 /**< Simulataneous Sampling Mask */
+#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK  0x8000 /**< Independent Mode */
+#define XADCPS_CFR1_SEQ_SHIFT		  12     /**< Sequence bit shift */
+#define XADCPS_CFR1_ALM_VCCPDRO_MASK	  0x0800 /**< Alm 6 - VCCPDRO, Zynq  */
+#define XADCPS_CFR1_ALM_VCCPAUX_MASK	  0x0400 /**< Alm 5 - VCCPAUX, Zynq */
+#define XADCPS_CFR1_ALM_VCCPINT_MASK	  0x0200 /**< Alm 4 - VCCPINT, Zynq */
+#define XADCPS_CFR1_ALM_VBRAM_MASK	  0x0100 /**< Alm 3 - VBRAM, 7 series */
+#define XADCPS_CFR1_CAL_VALID_MASK	  0x00F0 /**< Valid Calibration Mask */
+#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK  0x0080 /**< Calibration 3 -Power
+							Supply Gain/Offset
+							Enable */
+#define XADCPS_CFR1_CAL_PS_OFFSET_MASK	  0x0040 /**< Calibration 2 -Power
+							Supply Offset Enable */
+#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x0020 /**< Calibration 1 -ADC Gain
+							Offset Enable */
+#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK	 0x0010 /**< Calibration 0 -ADC Offset
+							Enable */
+#define XADCPS_CFR1_CAL_DISABLE_MASK	0x0000 /**< No Calibration */
+#define XADCPS_CFR1_ALM_ALL_MASK	0x0F0F /**< Mask for all alarms */
+#define XADCPS_CFR1_ALM_VCCAUX_MASK	0x0008 /**< Alarm 2 - VCCAUX Enable */
+#define XADCPS_CFR1_ALM_VCCINT_MASK	0x0004 /**< Alarm 1 - VCCINT Enable */
+#define XADCPS_CFR1_ALM_TEMP_MASK	0x0002 /**< Alarm 0 - Temperature */
+#define XADCPS_CFR1_OT_MASK		0x0001 /**< Over Temperature Enable */
+
+/*@}*/
+
+/**
+ * @name Configuration Register 2 (CFR2) mask(s)
+ * @{
+ */
+#define XADCPS_CFR2_CD_VALID_MASK	0xFF00  /**<Clock Divisor bit Mask   */
+#define XADCPS_CFR2_CD_SHIFT		8	/**<Num of shift on division */
+#define XADCPS_CFR2_CD_MIN		8	/**<Minimum value of divisor */
+#define XADCPS_CFR2_CD_MAX		255	/**<Maximum value of divisor */
+
+#define XADCPS_CFR2_CD_MIN		8	/**<Minimum value of divisor */
+#define XADCPS_CFR2_PD_MASK		0x0030	/**<Power Down Mask */
+#define XADCPS_CFR2_PD_XADC_MASK	0x0030	/**<Power Down XADC Mask */
+#define XADCPS_CFR2_PD_ADC1_MASK	0x0020	/**<Power Down ADC1 Mask */
+#define XADCPS_CFR2_PD_SHIFT		4	/**<Power Down Shift */
+/*@}*/
+
+/**
+ * @name Sequence Register (SEQ) Bit Definitions
+ * @{
+ */
+#define XADCPS_SEQ_CH_CALIB	0x00000001 /**< ADC Calibration Channel */
+#define XADCPS_SEQ_CH_VCCPINT	0x00000020 /**< VCCPINT, Zynq Only */
+#define XADCPS_SEQ_CH_VCCPAUX	0x00000040 /**< VCCPAUX, Zynq Only */
+#define XADCPS_SEQ_CH_VCCPDRO	0x00000080 /**< VCCPDRO, Zynq Only */
+#define XADCPS_SEQ_CH_TEMP	0x00000100 /**< On Chip Temperature Channel */
+#define XADCPS_SEQ_CH_VCCINT	0x00000200 /**< VCCINT Channel */
+#define XADCPS_SEQ_CH_VCCAUX	0x00000400 /**< VCCAUX Channel */
+#define XADCPS_SEQ_CH_VPVN	0x00000800 /**< VP/VN analog inputs Channel */
+#define XADCPS_SEQ_CH_VREFP	0x00001000 /**< VREFP Channel */
+#define XADCPS_SEQ_CH_VREFN	0x00002000 /**< VREFN Channel */
+#define XADCPS_SEQ_CH_VBRAM	0x00004000 /**< VBRAM Channel, 7 series */
+#define XADCPS_SEQ_CH_AUX00	0x00010000 /**< 1st Aux Channel */
+#define XADCPS_SEQ_CH_AUX01	0x00020000 /**< 2nd Aux Channel */
+#define XADCPS_SEQ_CH_AUX02	0x00040000 /**< 3rd Aux Channel */
+#define XADCPS_SEQ_CH_AUX03	0x00080000 /**< 4th Aux Channel */
+#define XADCPS_SEQ_CH_AUX04	0x00100000 /**< 5th Aux Channel */
+#define XADCPS_SEQ_CH_AUX05	0x00200000 /**< 6th Aux Channel */
+#define XADCPS_SEQ_CH_AUX06	0x00400000 /**< 7th Aux Channel */
+#define XADCPS_SEQ_CH_AUX07	0x00800000 /**< 8th Aux Channel */
+#define XADCPS_SEQ_CH_AUX08	0x01000000 /**< 9th Aux Channel */
+#define XADCPS_SEQ_CH_AUX09	0x02000000 /**< 10th Aux Channel */
+#define XADCPS_SEQ_CH_AUX10	0x04000000 /**< 11th Aux Channel */
+#define XADCPS_SEQ_CH_AUX11	0x08000000 /**< 12th Aux Channel */
+#define XADCPS_SEQ_CH_AUX12	0x10000000 /**< 13th Aux Channel */
+#define XADCPS_SEQ_CH_AUX13	0x20000000 /**< 14th Aux Channel */
+#define XADCPS_SEQ_CH_AUX14	0x40000000 /**< 15th Aux Channel */
+#define XADCPS_SEQ_CH_AUX15	0x80000000 /**< 16th Aux Channel */
+
+#define XADCPS_SEQ00_CH_VALID_MASK  0x7FE1 /**< Mask for the valid channels */
+#define XADCPS_SEQ01_CH_VALID_MASK  0xFFFF /**< Mask for the valid channels */
+
+#define XADCPS_SEQ02_CH_VALID_MASK  0x7FE0 /**< Mask for the valid channels */
+#define XADCPS_SEQ03_CH_VALID_MASK  0xFFFF /**< Mask for the valid channels */
+
+#define XADCPS_SEQ04_CH_VALID_MASK  0x0800 /**< Mask for the valid channels */
+#define XADCPS_SEQ05_CH_VALID_MASK  0xFFFF /**< Mask for the valid channels */
+
+#define XADCPS_SEQ06_CH_VALID_MASK  0x0800 /**< Mask for the valid channels */
+#define XADCPS_SEQ07_CH_VALID_MASK  0xFFFF /**< Mask for the valid channels */
+
+
+#define XADCPS_SEQ_CH_AUX_SHIFT	16 /**< Shift for the Aux Channel */
+
+/*@}*/
+
+/**
+ * @name OT Upper Alarm Threshold Register Bit Definitions
+ * @{
+ */
+
+#define XADCPS_ATR_OT_UPPER_ENB_MASK	0x000F /**< Mask for OT enable */
+#define XADCPS_ATR_OT_UPPER_VAL_MASK	0xFFF0 /**< Mask for OT value */
+#define XADCPS_ATR_OT_UPPER_VAL_SHIFT	4      /**< Shift for OT value */
+#define XADCPS_ATR_OT_UPPER_ENB_VAL	0x0003 /**< Value for OT enable */
+#define XADCPS_ATR_OT_UPPER_VAL_MAX	0x0FFF /**< Max OT value */
+
+/*@}*/
+
+
+/**
+ * @name JTAG DRP Bit Definitions
+ * @{
+ */
+#define XADCPS_JTAG_DATA_MASK		0x0000FFFF /**< Mask for the Data */
+#define XADCPS_JTAG_ADDR_MASK		0x03FF0000 /**< Mask for the Addr */
+#define XADCPS_JTAG_ADDR_SHIFT		16	   /**< Shift for the Addr */
+#define XADCPS_JTAG_CMD_MASK		0x3C000000 /**< Mask for the Cmd */
+#define XADCPS_JTAG_CMD_WRITE_MASK	0x08000000 /**< Mask for CMD Write */
+#define XADCPS_JTAG_CMD_READ_MASK	0x04000000 /**< Mask for CMD Read */
+#define XADCPS_JTAG_CMD_SHIFT		26	   /**< Shift for the Cmd */
+
+/*@}*/
+
+/** @name Unlock Register Definitions
+  * @{
+ */
+ #define XADCPS_UNLK_OFFSET	 0x034 /**< Unlock Register */
+ #define XADCPS_UNLK_VALUE	 0x757BDF0D /**< Unlock Value */
+
+ /* @} */
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+*
+* Read a register of the XADC device. This macro provides register
+* access to all registers using the register offsets defined above.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset is the offset of the register to read.
+*
+* @return	The contents of the register.
+*
+* @note		C-style Signature:
+*		u32 XAdcPs_ReadReg(u32 BaseAddress, u32 RegOffset);
+*
+******************************************************************************/
+#define XAdcPs_ReadReg(BaseAddress, RegOffset) \
+			(Xil_In32((BaseAddress) + (RegOffset)))
+
+/*****************************************************************************/
+/**
+*
+* Write a register of the XADC device. This macro provides
+* register access to all registers using the register offsets defined above.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset is the offset of the register to write.
+* @param	Data is the value to write to the register.
+*
+* @return	None.
+*
+* @note 	C-style Signature:
+*		void XAdcPs_WriteReg(u32 BaseAddress,
+*					u32 RegOffset,u32 Data)
+*
+******************************************************************************/
+#define XAdcPs_WriteReg(BaseAddress, RegOffset, Data) \
+		(Xil_Out32((BaseAddress) + (RegOffset), (Data)))
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Formats the data to be written to the the XADC registers.
+*
+* @param	RegOffset is the offset of the Register
+* @param	Data is the data to be written to the Register if it is
+*		a write.
+* @param	ReadWrite specifies whether it is a Read or a Write.
+*		Use 0 for Read, 1 for Write.
+*
+* @return	None.
+*
+* @note 	C-style Signature:
+*		void XAdcPs_FormatWriteData(u32 RegOffset,
+*					     u16 Data, int ReadWrite)
+*
+******************************************************************************/
+#define XAdcPs_FormatWriteData(RegOffset, Data, ReadWrite) 	    \
+    ((ReadWrite ? XADCPS_JTAG_CMD_WRITE_MASK : XADCPS_JTAG_CMD_READ_MASK ) | \
+     ((RegOffset << XADCPS_JTAG_ADDR_SHIFT) & XADCPS_JTAG_ADDR_MASK) | 	     \
+     (Data & XADCPS_JTAG_DATA_MASK))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* End of protection macro. */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xbasic_types.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xbasic_types.h
new file mode 100644
index 0000000000000000000000000000000000000000..787212ca75ff368e405799266b103f095b0b22a1
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xbasic_types.h
@@ -0,0 +1,119 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xbasic_types.h
+*
+*
+* @note  Dummy File for backwards compatibility
+*
+
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a adk   1/31/14  Added in bsp common folder for backward compatibility
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XBASIC_TYPES_H	/* prevent circular inclusions */
+#define XBASIC_TYPES_H	/* by using protection macros */
+
+/** @name Legacy types
+ * Deprecated legacy types.
+ * @{
+ */
+typedef unsigned char	Xuint8;		/**< unsigned 8-bit */
+typedef char		Xint8;		/**< signed 8-bit */
+typedef unsigned short	Xuint16;	/**< unsigned 16-bit */
+typedef short		Xint16;		/**< signed 16-bit */
+typedef unsigned long	Xuint32;	/**< unsigned 32-bit */
+typedef long		Xint32;		/**< signed 32-bit */
+typedef float		Xfloat32;	/**< 32-bit floating point */
+typedef double		Xfloat64;	/**< 64-bit double precision FP */
+typedef unsigned long	Xboolean;	/**< boolean (XTRUE or XFALSE) */
+
+#if !defined __XUINT64__
+typedef struct
+{
+	Xuint32 Upper;
+	Xuint32 Lower;
+} Xuint64;
+#endif
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XIL_TYPES_H
+typedef Xuint32         u32;
+typedef Xuint16         u16;
+typedef Xuint8          u8;
+#endif
+#else
+#include <linux/types.h>
+#endif
+
+#ifndef TRUE
+#  define TRUE		1U
+#endif
+
+#ifndef FALSE
+#  define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+/*
+ * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
+ * Please use NULL, TRUE and FALSE
+ */
+#define XNULL		NULL
+#define XTRUE		TRUE
+#define XFALSE		FALSE
+
+/*
+ * This file is deprecated and users
+ * should use xil_types.h and xil_assert.h\n\r
+ */
+#warning  The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
+#warning  Please refer the Standalone BSP UG647 for further details
+
+
+#endif	/* end of protection macro */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xcoresightpsdcc.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xcoresightpsdcc.h
new file mode 100644
index 0000000000000000000000000000000000000000..a732b235d6839c79fb42039fc06a42785de2928d
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xcoresightpsdcc.h
@@ -0,0 +1,74 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcoresightpsdcc.h
+* @addtogroup coresightps_dcc_v1_1
+* @{
+* @details
+*
+* CoreSight driver component.
+*
+* The coresight is a part of debug communication channel (DCC) group. Jtag UART
+* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an
+* ARM target in XSDB console before running the jtag terminal command. Using the
+* coresight driver component, the output stream can be directed to a log file.
+*
+* @note 	None.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date		Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00  kvn    02/14/15 First release
+* 1.1   kvn    06/12/15 Add support for Zynq Ultrascale+ MP.
+*       kvn    08/18/15 Modified Makefile according to compiler changes.
+* 1.3   asa    07/01/16 Made changes to ensure that the file does not compile
+*                       for MB BSPs. Instead it throws up a warning. This
+*                       fixes the CR#953056.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#ifndef __MICROBLAZE__
+#include <xil_types.h>
+
+void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
+
+u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
+#endif
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xcpu_cortexa9.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xcpu_cortexa9.h
new file mode 100644
index 0000000000000000000000000000000000000000..4d441e53e6691168cfba555258ab1eb54d6207ea
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xcpu_cortexa9.h
@@ -0,0 +1,43 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcpu_cortexa9.h
+* @addtogroup cpu_cortexa9_v2_1
+* @{
+* @details
+*
+* dummy file
+*
+******************************************************************************/
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xddrps.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xddrps.h
new file mode 100644
index 0000000000000000000000000000000000000000..fe7adb066edcb52c1f8c35615e813ed23b1b11f6
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xddrps.h
@@ -0,0 +1,66 @@
+/*******************************************************************************
+ *
+ * Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * Use of the Software is limited solely to applications:
+ * (a) running on a Xilinx device, or
+ * (b) that interact with a Xilinx device through a bus or interconnect.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+*******************************************************************************/
+/******************************************************************************/
+/**
+ *
+ * @file xddrps.h
+ * @addtogroup ddrps_v1_0
+ * @{
+ * @details
+ *
+ * The Xilinx DdrPs driver. This driver supports the Xilinx ddrps
+ * IP core.
+ *
+ * @note	None.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0	 nsk  08/06/15 First Release
+ * 1.0	 nsk  08/20/15 Updated define_addr_params in ddrps.tcl
+ *		       to support PBD Designs (CR #876857)
+ *
+ * </pre>
+ *
+*******************************************************************************/
+
+#ifndef XDDRPS_H_
+/* Prevent circular inclusions by using protection macros. */
+#define XDDRPS_H_
+
+/******************************* Include Files ********************************/
+
+
+#endif /* XDDRPS_H_ */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xdebug.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xdebug.h
new file mode 100644
index 0000000000000000000000000000000000000000..650946bd01f4555daaeaf12db9919130e4aecf7d
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xdebug.h
@@ -0,0 +1,32 @@
+#ifndef XDEBUG  /* prevent circular inclusions */
+#define XDEBUG  /* by using protection macros */
+
+#if defined(DEBUG) && !defined(NDEBUG)
+
+#ifndef XDEBUG_WARNING
+#define XDEBUG_WARNING
+#warning DEBUG is enabled
+#endif
+
+int printf(const char *format, ...);
+
+#define XDBG_DEBUG_ERROR             0x00000001U    /* error  condition messages */
+#define XDBG_DEBUG_GENERAL           0x00000002U    /* general debug  messages */
+#define XDBG_DEBUG_ALL               0xFFFFFFFFU    /* all debugging data */
+
+#define xdbg_current_types (XDBG_DEBUG_GENERAL)
+
+#define xdbg_stmnt(x)  x
+
+#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
+
+
+#else /* defined(DEBUG) && !defined(NDEBUG) */
+
+#define xdbg_stmnt(x)
+
+#define xdbg_printf(...)
+
+#endif /* defined(DEBUG) && !defined(NDEBUG) */
+
+#endif /* XDEBUG */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xdevcfg.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xdevcfg.h
new file mode 100644
index 0000000000000000000000000000000000000000..7fc1332a513a9181c17b712c7386a911657a61d4
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xdevcfg.h
@@ -0,0 +1,399 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg.h
+* @addtogroup devcfg_v3_3
+* @{
+* @details
+*
+* The is the main header file for the Device Configuration Interface of the Zynq
+* device. The device configuration interface has three main functionality.
+*  1. AXI-PCAP
+*  2. Security Policy
+*  3. XADC
+* This current version of the driver supports only the AXI-PCAP and Security
+* Policy blocks. There is a separate driver for XADC.
+*
+* AXI-PCAP is used for download/upload an encrypted or decrypted bitstream.
+* DMA embedded in the AXI PCAP provides the master interface to
+* the Device configuration block for any DMA transfers. The data transfer can
+* take place between the Tx/RxFIFOs of AXI-PCAP and memory (on chip
+* RAM/DDR/peripheral memory).
+*
+* The current driver only supports the downloading the FPGA bitstream and
+* readback of the decrypted image (sort of loopback).
+* The driver does not know what information needs to be written to the FPGA to
+* readback FPGA configuration register or memory data. The application above the
+* driver should take care of creating the data that needs to be downloaded to
+* the FPGA so that the bitstream can be readback.
+* This driver also does not support the reading of the internal registers of the
+* PCAP. The driver has no knowledge of the PCAP internals.
+*
+* <b> Initialization and Configuration </b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Device Configuration device.
+*
+* XDcfg_CfgInitialize() API is used to initialize the Device Configuration
+* Interface. The user needs to first call the XDcfg_LookupConfig() API which
+* returns the Configuration structure pointer which is passed as a parameter to
+* the XDcfg_CfgInitialize() API.
+*
+* <b>Interrupts</b>
+* The Driver implements an interrupt handler to support the interrupts provided
+* by this interface.
+*
+* <b> Threads </b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* <b> Asserts </b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* <b> Building the driver </b>
+*
+* The XDcfg driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* <br><br>
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.00a nm  05/31/12 Updated the driver for CR 660835 so that input length for
+*		     source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
+*		     APIs is words (32 bit) and not bytes.
+* 		     Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
+*		     to add information that 2 LSBs of the Source/Destination
+*		     address when equal to 2�b01 indicate the last DMA command
+*		     of an overall transfer.
+*		     Destination Address passed to this API for secure transfers
+*		     instead of using 0xFFFFFFFF for CR 662197. This issue was
+*		     resulting in the failure of secure transfers of
+*		     non-bitstream images.
+* 2.01a nm  07/07/12 Updated the XDcfg_IntrClear function to directly
+*		     set the mask instead of oring it with the
+*		     value read from the interrupt status register
+* 		     Added defines for the PS Version bits,
+*	             removed the FIFO Flush bits from the
+*		     Miscellaneous Control Reg.
+*		     Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface
+*		     and XDcfg_SelectPcapInterface APIs for CR 643295
+*		     The user has to call the XDcfg_SelectIcapInterface API
+*		     for the PL reconfiguration using AXI HwIcap.
+*		     Updated the XDcfg_Transfer API to clear the
+*		     QUARTER_PCAP_RATE_EN bit in the control register for
+*		     non secure writes for CR 675543.
+* 2.02a nm  01/31/13 Fixed CR# 679335.
+* 		     Added Setting and Clearing the internal PCAP loopback.
+*		     Removed code for enabling/disabling AES engine as BootROM
+*		     locks down this setting.
+*		     Fixed CR# 681976.
+*		     Skip Checking the PCFG_INIT in case of non-secure DMA
+*		     loopback.
+*		     Fixed CR# 699558.
+*		     XDcfg_Transfer fails to transfer data in loopback mode.
+*		     Fixed CR# 701348.
+*                    Peripheral test fails with  Running
+* 		     DcfgSelfTestExample() in SECURE bootmode.
+* 2.03a nm  04/19/13 Fixed CR# 703728.
+*		     Updated the register definitions as per the latest TRM
+*		     version UG585 (v1.4) November 16, 2012.
+* 3.0   adk 10/12/13 Updated as per the New Tcl API's
+* 3.0   kpc 21/02/14 Added function prototype for XDcfg_ClearControlRegister
+* 3.2   sb  08/25/14 Fixed XDcfg_PcapReadback() function
+*		     updated driver code with != instead of ==,
+*		     while checking for Interrupt Status with DMA and
+*		     PCAP Done Mask
+*		     ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+*			XDCFG_INT_STS_OFFSET) &
+*			XDCFG_IXR_D_P_DONE_MASK) !=
+*			XDCFG_IXR_D_P_DONE_MASK);
+*		     A new example has been added to read back the
+*		     configuration registers from the PL region.
+*		     xdevcfg_reg_readback_example.c
+* 3.3   sk  04/06/15 Modified XDcfg_ReadMultiBootConfig Macro CR# 851335.
+*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+*                    generation.
+*
+* </pre>
+*
+******************************************************************************/
+#ifndef XDCFG_H		/* prevent circular inclusions */
+#define XDCFG_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg_hw.h"
+#include "xstatus.h"
+#include "xil_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/* Types of PCAP transfers */
+
+#define XDCFG_NON_SECURE_PCAP_WRITE		1
+#define XDCFG_SECURE_PCAP_WRITE			2
+#define XDCFG_PCAP_READBACK			3
+#define XDCFG_CONCURRENT_SECURE_READ_WRITE	4
+#define XDCFG_CONCURRENT_NONSEC_READ_WRITE	5
+
+
+/**************************** Type Definitions *******************************/
+/**
+* The handler data type allows the user to define a callback function to
+* respond to interrupt events in the system. This function is executed
+* in interrupt context, so amount of processing should be minimized.
+*
+* @param	CallBackRef is the callback reference passed in by the upper
+*		layer when setting the callback functions, and passed back to
+*		the upper layer when the callback is invoked. Its type is
+*		unimportant to the driver component, so it is a void pointer.
+* @param	Status is the Interrupt status of the XDcfg device.
+*/
+typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID of device */
+	u32 BaseAddr;		/**< Base address of the device */
+} XDcfg_Config;
+
+/**
+ * The XDcfg driver instance data.
+ */
+typedef struct {
+	XDcfg_Config Config;	/**< Hardware Configuration */
+	u32 IsReady;		/**< Device is initialized and ready */
+	u32 IsStarted;		/**< Device Configuration Interface
+				  * is running
+				  */
+	XDcfg_IntrHandler StatusHandler;  /* Event handler function */
+	void *CallBackRef;	/* Callback reference for event handler */
+} XDcfg;
+
+/****************************************************************************/
+/**
+*
+* Unlock the Device Config Interface block.
+*
+* @param	InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XDcfg_Unlock(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_Unlock(InstancePtr)					\
+	XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, 			\
+	XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA)
+
+
+
+/****************************************************************************/
+/**
+*
+* Get the version number of the PS from the Miscellaneous Control Register.
+*
+* @param	InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return	Version of the PS.
+*
+* @note		C-style signature:
+*		void XDcfg_GetPsVersion(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_GetPsVersion(InstancePtr)					\
+	((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, 		\
+			XDCFG_MCTRL_OFFSET)) & 				\
+			XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> 		\
+			XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
+
+
+
+/****************************************************************************/
+/**
+*
+* Read the multiboot config register value.
+*
+* @param	InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_ReadMultiBootConfig(InstancePtr)			\
+	XDcfg_ReadReg((InstancePtr)->Config.BaseAddr,  		\
+			XDCFG_MULTIBOOT_ADDR_OFFSET)
+
+
+/****************************************************************************/
+/**
+*
+* Selects ICAP interface for reconfiguration after the initial configuration
+* of the PL.
+*
+* @param	InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XDcfg_SelectIcapInterface(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_SelectIcapInterface(InstancePtr)				  \
+	XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET,   \
+	((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
+	& ( ~XDCFG_CTRL_PCAP_PR_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Selects PCAP interface for reconfiguration after the initial configuration
+* of the PL.
+*
+* @param	InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XDcfg_SelectPcapInterface(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_SelectPcapInterface(InstancePtr)				   \
+	XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET,    \
+	((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET))  \
+	| XDCFG_CTRL_PCAP_PR_MASK))
+
+
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xdevcfg_sinit.c.
+ */
+XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xdevcfg_selftest.c
+ */
+int XDcfg_SelfTest(XDcfg *InstancePtr);
+
+/*
+ * Interface functions in xdevcfg.c
+ */
+int XDcfg_CfgInitialize(XDcfg *InstancePtr,
+			 XDcfg_Config *ConfigPtr, u32 EffectiveAddress);
+
+void XDcfg_EnablePCAP(XDcfg *InstancePtr);
+
+void XDcfg_DisablePCAP(XDcfg *InstancePtr);
+
+void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_GetControlRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetLockRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr);
+
+u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr);
+
+void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
+				u32 SrcWordLength, u32 DestWordLength);
+
+u32 XDcfg_Transfer(XDcfg *InstancePtr,
+				void *SourcePtr, u32 SrcWordLength,
+				void *DestPtr, u32 DestWordLength,
+				u32 TransferType);
+
+/*
+ * Interrupt related function prototypes implemented in xdevcfg_intr.c
+ */
+void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr);
+
+u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr);
+
+void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_InterruptHandler(XDcfg *InstancePtr);
+
+void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
+				void *CallBackRef);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xdevcfg_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xdevcfg_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..c506ca59fc936b96086d96b074f85bee0959c104
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xdevcfg_hw.h
@@ -0,0 +1,395 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg_hw.h
+* @addtogroup devcfg_v3_3
+* @{
+*
+* This file contains the hardware interface to the Device Config Interface.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.01a nm  08/01/12 Added defines for the PS Version bits,
+*	             removed the FIFO Flush bits from the
+*		     Miscellaneous Control Reg
+* 2.03a nm  04/19/13 Fixed CR# 703728.
+*		     Updated the register definitions as per the latest TRM
+*		     version UG585 (v1.4) November 16, 2012.
+* 2.04a	kpc	10/07/13 Added function prototype.
+* 3.00a	kpc	25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
+* </pre>
+*
+******************************************************************************/
+#ifndef XDCFG_HW_H		/* prevent circular inclusions */
+#define XDCFG_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device
+ * @{
+ */
+
+#define XDCFG_CTRL_OFFSET		0x00 /**< Control Register */
+#define XDCFG_LOCK_OFFSET		0x04 /**< Lock Register */
+#define XDCFG_CFG_OFFSET		0x08 /**< Configuration Register */
+#define XDCFG_INT_STS_OFFSET		0x0C /**< Interrupt Status Register */
+#define XDCFG_INT_MASK_OFFSET		0x10 /**< Interrupt Mask Register */
+#define XDCFG_STATUS_OFFSET		0x14 /**< Status Register */
+#define XDCFG_DMA_SRC_ADDR_OFFSET	0x18 /**< DMA Source Address Register */
+#define XDCFG_DMA_DEST_ADDR_OFFSET	0x1C /**< DMA Destination Address Reg */
+#define XDCFG_DMA_SRC_LEN_OFFSET	0x20 /**< DMA Source Transfer Length */
+#define XDCFG_DMA_DEST_LEN_OFFSET	0x24 /**< DMA Destination Transfer */
+#define XDCFG_ROM_SHADOW_OFFSET		0x28 /**< DMA ROM Shadow Register */
+#define XDCFG_MULTIBOOT_ADDR_OFFSET	0x2C /**< Multi BootAddress Pointer */
+#define XDCFG_SW_ID_OFFSET		0x30 /**< Software ID Register */
+#define XDCFG_UNLOCK_OFFSET		0x34 /**< Unlock Register */
+#define XDCFG_MCTRL_OFFSET		0x80 /**< Miscellaneous Control Reg */
+
+/* @} */
+
+/** @name Control Register Bit definitions
+  * @{
+ */
+
+#define XDCFG_CTRL_FORCE_RST_MASK	0x80000000 /**< Force  into
+						     * Secure Reset
+						     */
+#define XDCFG_CTRL_PCFG_PROG_B_MASK	0x40000000 /**< Program signal to
+						     *  Reset FPGA
+						     */
+#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK	0x20000000 /**< Control PL POR timer */
+#define XDCFG_CTRL_PCAP_PR_MASK	  	0x08000000 /**< Enable PCAP for PR */
+#define XDCFG_CTRL_PCAP_MODE_MASK	0x04000000 /**< Enable PCAP */
+#define XDCFG_CTRL_PCAP_RATE_EN_MASK	0x02000000 /**< Enable PCAP send data
+						     *  to FPGA every 4 PCAP
+						     *  cycles
+						     */
+#define XDCFG_CTRL_MULTIBOOT_EN_MASK	0x01000000 /**< Multiboot Enable */
+#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK	0x00800000 /**< JTAG Chain Disable */
+#define XDCFG_CTRL_USER_MODE_MASK	0x00008000 /**< User Mode Mask */
+#define XDCFG_CTRL_PCFG_AES_FUSE_MASK	0x00001000 /**< AES key source */
+#define XDCFG_CTRL_PCFG_AES_EN_MASK	0x00000E00 /**< AES Enable Mask */
+#define XDCFG_CTRL_SEU_EN_MASK		0x00000100 /**< SEU Enable Mask */
+#define XDCFG_CTRL_SEC_EN_MASK		0x00000080 /**< Secure/Non Secure
+						     *  Status mask
+						     */
+#define XDCFG_CTRL_SPNIDEN_MASK		0x00000040 /**< Secure Non Invasive
+						     *  Debug Enable
+						     */
+#define XDCFG_CTRL_SPIDEN_MASK		0x00000020 /**< Secure Invasive
+						     *  Debug Enable
+						     */
+#define XDCFG_CTRL_NIDEN_MASK		0x00000010 /**< Non-Invasive Debug
+						     *  Enable
+						     */
+#define XDCFG_CTRL_DBGEN_MASK		0x00000008 /**< Invasive Debug
+						     *  Enable
+						     */
+#define XDCFG_CTRL_DAP_EN_MASK		0x00000007 /**< DAP Enable Mask */
+
+/* @} */
+
+/** @name Lock register bit definitions
+  * @{
+ */
+
+#define XDCFG_LOCK_AES_EFUSE_MASK	0x00000010 /**< Lock AES Efuse bit */
+#define XDCFG_LOCK_AES_EN_MASK		0x00000008 /**< Lock AES_EN update */
+#define XDCFG_LOCK_SEU_MASK		0x00000004 /**< Lock SEU_En update */
+#define XDCFG_LOCK_SEC_MASK		0x00000002 /**< Lock SEC_EN and
+						     *  USER_MODE
+						     */
+#define XDCFG_LOCK_DBG_MASK		0x00000001 /**< This bit locks
+						     *  security config
+						     *  including: DAP_En,
+						     *  DBGEN,,
+						     *  NIDEN, SPNIEN
+						     */
+/*@}*/
+
+
+
+/** @name Config Register Bit definitions
+  * @{
+ */
+#define XDCFG_CFG_RFIFO_TH_MASK	  	0x00000C00 /**< Read FIFO
+						     *  Threshold Mask
+						     */
+#define XDCFG_CFG_WFIFO_TH_MASK	  	0x00000300 /**< Write FIFO Threshold
+						     *  Mask
+						     */
+#define XDCFG_CFG_RCLK_EDGE_MASK	0x00000080 /**< Read data active
+						     *  clock edge
+						     */
+#define XDCFG_CFG_WCLK_EDGE_MASK	0x00000040 /**< Write data active
+						     *  clock edge
+						     */
+#define XDCFG_CFG_DISABLE_SRC_INC_MASK	0x00000020 /**< Disable Source address
+						     *  increment mask
+						     */
+#define XDCFG_CFG_DISABLE_DST_INC_MASK	0x00000010 /**< Disable Destination
+						     *  address increment
+						     *  mask
+						     */
+/* @} */
+
+
+/** @name Interrupt Status/Mask Register Bit definitions
+  * @{
+ */
+#define XDCFG_IXR_PSS_GTS_USR_B_MASK	0x80000000 /**< Tri-state IO during
+						     *  HIZ
+						     */
+#define XDCFG_IXR_PSS_FST_CFG_B_MASK	0x40000000 /**< First configuration
+						     *  done
+						     */
+#define XDCFG_IXR_PSS_GPWRDWN_B_MASK	0x20000000 /**< Global power down */
+#define XDCFG_IXR_PSS_GTS_CFG_B_MASK	0x10000000 /**< Tri-state IO during
+						     *  configuration
+						     */
+#define XDCFG_IXR_PSS_CFG_RESET_B_MASK	0x08000000 /**< PL configuration
+						     *  reset
+						     */
+#define XDCFG_IXR_AXI_WTO_MASK		0x00800000 /**< AXI Write Address
+						     *  or Data or response
+						     *  timeout
+						     */
+#define XDCFG_IXR_AXI_WERR_MASK		0x00400000 /**< AXI Write response
+						     *  error
+						     */
+#define XDCFG_IXR_AXI_RTO_MASK		0x00200000 /**< AXI Read Address or
+						     *  response timeout
+						     */
+#define XDCFG_IXR_AXI_RERR_MASK		0x00100000 /**< AXI Read response
+						     *  error
+						     */
+#define XDCFG_IXR_RX_FIFO_OV_MASK	0x00040000 /**< Rx FIFO Overflow */
+#define XDCFG_IXR_WR_FIFO_LVL_MASK	0x00020000 /**< Tx FIFO less than
+						     *  threshold */
+#define XDCFG_IXR_RD_FIFO_LVL_MASK	0x00010000 /**< Rx FIFO greater than
+						     *  threshold */
+#define XDCFG_IXR_DMA_CMD_ERR_MASK	0x00008000 /**< Illegal DMA command */
+#define XDCFG_IXR_DMA_Q_OV_MASK		0x00004000 /**< DMA command queue
+						     *  overflow
+						     */
+#define XDCFG_IXR_DMA_DONE_MASK		0x00002000 /**< DMA Command Done */
+#define XDCFG_IXR_D_P_DONE_MASK		0x00001000 /**< DMA and PCAP
+						     *  transfers Done
+						     */
+#define XDCFG_IXR_P2D_LEN_ERR_MASK	0x00000800 /**< PCAP to DMA transfer
+						     *  length error
+						     */
+#define XDCFG_IXR_PCFG_HMAC_ERR_MASK	0x00000040 /**< HMAC error mask */
+#define XDCFG_IXR_PCFG_SEU_ERR_MASK	0x00000020 /**< SEU Error mask */
+#define XDCFG_IXR_PCFG_POR_B_MASK	0x00000010 /**< FPGA POR mask */
+#define XDCFG_IXR_PCFG_CFG_RST_MASK	0x00000008 /**< FPGA Reset mask */
+#define XDCFG_IXR_PCFG_DONE_MASK	0x00000004 /**< Done Signal  Mask */
+#define XDCFG_IXR_PCFG_INIT_PE_MASK	0x00000002 /**< Detect Positive edge
+						     *  of Init Signal
+						     */
+#define XDCFG_IXR_PCFG_INIT_NE_MASK  	0x00000001 /**< Detect Negative edge
+						     *  of Init Signal
+						     */
+#define XDCFG_IXR_ERROR_FLAGS_MASK		(XDCFG_IXR_AXI_WTO_MASK | \
+						XDCFG_IXR_AXI_WERR_MASK | \
+						XDCFG_IXR_AXI_RTO_MASK |  \
+						XDCFG_IXR_AXI_RERR_MASK | \
+						XDCFG_IXR_RX_FIFO_OV_MASK | \
+						XDCFG_IXR_DMA_CMD_ERR_MASK |\
+						XDCFG_IXR_DMA_Q_OV_MASK |   \
+						XDCFG_IXR_P2D_LEN_ERR_MASK |\
+						XDCFG_IXR_PCFG_HMAC_ERR_MASK)
+
+
+#define XDCFG_IXR_ALL_MASK			0x00F7F8EF
+
+
+
+/* @} */
+
+
+/** @name Status Register Bit definitions
+  * @{
+ */
+#define XDCFG_STATUS_DMA_CMD_Q_F_MASK	0x80000000 /**< DMA command
+						     *  Queue full
+						     */
+#define XDCFG_STATUS_DMA_CMD_Q_E_MASK	0x40000000 /**< DMA command
+						     *  Queue empty
+						     */
+#define XDCFG_STATUS_DMA_DONE_CNT_MASK	0x30000000 /**< Number of
+						     *  completed DMA
+						     *  transfers
+						     */
+#define XDCFG_STATUS_RX_FIFO_LVL_MASK	0x01F000000 /**< Rx FIFO level */
+#define XDCFG_STATUS_TX_FIFO_LVL_MASK	0x0007F000  /**< Tx FIFO level */
+
+#define XDCFG_STATUS_PSS_GTS_USR_B	0x00000800  /**< Tri-state IO
+						      *  during HIZ
+						      */
+#define XDCFG_STATUS_PSS_FST_CFG_B	0x00000400  /**< First PL config
+						      *  done
+						      */
+#define XDCFG_STATUS_PSS_GPWRDWN_B	0x00000200  /**< Global power down */
+#define XDCFG_STATUS_PSS_GTS_CFG_B	0x00000100  /**< Tri-state IO during
+						      *  config
+						      */
+#define XDCFG_STATUS_SECURE_RST_MASK	0x00000080  /**< Secure Reset
+						      *  POR Status
+						      */
+#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 	0x00000040 /**< Illegal APB
+							     *  access
+							     */
+#define XDCFG_STATUS_PSS_CFG_RESET_B		0x00000020 /**< PL config
+							     *  reset status
+							     */
+#define XDCFG_STATUS_PCFG_INIT_MASK		0x00000010 /**< FPGA Init
+							     *  Status
+							     */
+#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK	0x00000008
+							   /**< BBRAM key
+							     *  disable
+							     */
+#define XDCFG_STATUS_EFUSE_SEC_EN_MASK		0x00000004 /**< Efuse Security
+							     *  Enable Status
+							     */
+#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK	0x00000002 /**< EFuse JTAG
+							     *  Disable
+							     *  status
+							     */
+/* @} */
+
+
+/** @name DMA Source/Destination Transfer Length Register Bit definitions
+ * @{
+ */
+#define XDCFG_DMA_LEN_MASK		0x7FFFFFF /**< Length Mask */
+/*@}*/
+
+
+
+
+/** @name Miscellaneous Control  Register Bit definitions
+  * @{
+ */
+#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK  0xF0000000 /**< PS Version Mask */
+#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28	     /**< PS Version Shift */
+#define XDCFG_MCTRL_PCAP_LPBK_MASK	  0x00000010 /**< PCAP loopback mask */
+/* @} */
+
+/** @name FIFO Threshold Bit definitions
+  * @{
+ */
+
+#define XDCFG_CFG_FIFO_QUARTER		0x0	 /**< Quarter empty */
+#define XDCFG_CFG_FIFO_HALF		0x1	 /**< Half empty */
+#define XDCFG_CFG_FIFO_3QUARTER		0x2	 /**< 3/4 empty */
+#define XDCFG_CFG_FIFO_EMPTY		0x4	 /**< Empty */
+/* @}*/
+
+
+/* Miscellaneous constant values */
+#define XDCFG_DMA_INVALID_ADDRESS	0xFFFFFFFF  /**< Invalid DMA address */
+#define XDCFG_UNLOCK_DATA		0x757BDF0D  /**< First APB access data*/
+#define XDCFG_BASE_ADDRESS		0xF8007000  /**< Device Config base
+						      * address
+						      */
+#define XDCFG_CONFIG_RESET_VALUE	0x508	/**< Config reg reset value */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param	BaseAddr is the base address of the device
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note		C-style signature:
+*		u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XDcfg_ReadReg(BaseAddr, RegOffset)		\
+	Xil_In32((BaseAddr) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write to the given register.
+*
+* @param	BaseAddr is the base address of the device
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XDcfg_WriteReg(BaseAddr, RegOffset, Data)	\
+	Xil_Out32((BaseAddr) + (RegOffset), (Data))
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the devcfg interface
+ */
+void XDcfg_ResetHw(u32 BaseAddr);
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xdmaps.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xdmaps.h
new file mode 100644
index 0000000000000000000000000000000000000000..e0a283600e01f3514af7d1040cb545649f93a1e8
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xdmaps.h
@@ -0,0 +1,352 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal 
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps.h
+* @addtogroup dmaps_v2_1
+* @{
+* @details
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  	Date     Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	hbm    08/19/10 First Release
+* 1.01a nm     12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+*		        the maximum number of channels.
+*		        Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+*                       with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h.
+*			Added the tcl file to automatically generate the
+*			xparameters.h
+* 1.02a sg     05/16/12 Made changes for doxygen and moved some function
+*			header from the xdmaps.h file to xdmaps.c file
+*			Other cleanup for coding guidelines and CR 657109
+*			and CR 657898
+*			The xdmaps_example_no_intr.c example is removed
+*			as it is using interrupts  and is similar to
+*			the interrupt example - CR 652477
+* 1.03a sg     07/16/2012 changed inline to __inline for CR665681
+* 1.04a nm     10/22/2012 Fixed CR# 681671.
+* 1.05a nm     04/15/2013 Fixed CR# 704396. Removed warnings when compiled
+*			  with -Wall and -Wextra option in bsp.
+*	       05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
+*			  function description.
+*			  Fixed CR# 704396. Removed unused variables
+*			  UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
+*			  function.
+* 1.07a asa    11/02/13. Made changes to fix compilation issues for iarcc.
+*			   Removed the PDBG prints. By default they were always
+*			   defined out and never used. The PDBG is non-standard for
+*			   Xilinx drivers and no other driver does something similar.
+*			   Since there is no easy way to fix compilation issues with
+*			   the IARCC compiler around PDBG, it is better to remove it.
+*			   Users can always use xil_printfs if they want to debug.
+* 2.0   adk    10/12/13  Updated as per the New Tcl API's
+* 2.01  kpc    08/23/14  Fixed the IAR compiler reported errors
+* 2.2   mus    08/12/16  Declared all inline functions in xdmaps.c as extern, to avoid
+*                        linker error for IAR compiler
+* 2.3   ms     01/23/17 Modified xil_printf statement in main function for all
+*                       examples to ensure that "Successfully ran" and "Failed"
+*                       strings are available in all examples. This is a fix
+*                       for CR-965028.
+*       ms     03/17/17 Added readme.txt file in examples folder for doxygen
+*                       generation.
+* </pre>
+*
+*****************************************************************************/
+
+#ifndef XDMAPS_H		/* prevent circular inclusions */
+#define XDMAPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xparameters.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+
+#include "xdmaps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;	 /**< Unique ID  of device */
+	u32 BaseAddress; /**< Base address of device (IPIF) */
+} XDmaPs_Config;
+
+
+/** DMA channle control structure. It's for AXI bus transaction.
+ * This struct will be translated into a 32-bit channel control register value.
+ */
+typedef struct {
+	unsigned int EndianSwapSize;	/**< Endian swap size. */
+	unsigned int DstCacheCtrl;	/**< Destination cache control */
+	unsigned int DstProtCtrl;	/**< Destination protection control */
+	unsigned int DstBurstLen;	/**< Destination burst length */
+	unsigned int DstBurstSize;	/**< Destination burst size */
+	unsigned int DstInc;		/**< Destination incrementing or fixed
+					 *   address */
+	unsigned int SrcCacheCtrl;	/**< Source cache control */
+	unsigned int SrcProtCtrl;	/**< Source protection control */
+	unsigned int SrcBurstLen;	/**< Source burst length */
+	unsigned int SrcBurstSize;	/**< Source burst size */
+	unsigned int SrcInc;		/**< Source incrementing or fixed
+					 *   address */
+} XDmaPs_ChanCtrl;
+
+/** DMA block descriptor stucture.
+ */
+typedef struct {
+	u32 SrcAddr;		/**< Source starting address */
+	u32 DstAddr;		/**< Destination starting address */
+	unsigned int Length;	/**< Number of bytes for the block */
+} XDmaPs_BD;
+
+/**
+ * A DMA command consisits of a channel control struct, a block descriptor,
+ * a user defined program, a pointer pointing to generated DMA program, and
+ * execution result.
+ *
+ */
+typedef struct {
+	XDmaPs_ChanCtrl ChanCtrl; 	/**< Channel Control Struct */
+	XDmaPs_BD BD;			/**< Together with SgLength field,
+					  *  it's a scatter-gather list.
+					  */
+	void *UserDmaProg;		/**< If user wants the driver to
+					  *  execute their own DMA program,
+					  *  this field points to the DMA
+					  *  program.
+					  */
+	int UserDmaProgLength;		/**< The length of user defined
+					  *  DMA program.
+					  */
+
+	void *GeneratedDmaProg;		/**< The DMA program genreated
+					 * by the driver. This field will be
+					 * set if a user invokes the DMA
+					 * program generation function. Or
+					 * the DMA command is finished and
+					 * a user informs the driver not to
+					 * release the program buffer.
+					 * This field has two purposes, one
+					 * is to ask the driver to generate
+					 * a DMA program while the DMAC is
+					 * performaning DMA transactions. The
+					 * other purpose is to debug the
+					 * driver.
+					 */
+	int GeneratedDmaProgLength;	 /**< The length of the DMA program
+					  * generated by the driver
+					  */
+	int DmaStatus;			/**< 0 on success, otherwise error code
+					 */
+	u32 ChanFaultType;	/**< Channel fault type in case of fault
+				 */
+	u32 ChanFaultPCAddr;	/**< Channel fault PC address
+				 */
+} XDmaPs_Cmd;
+
+/**
+ * It's the done handler a user can set for a channel
+ */
+typedef void (*XDmaPsDoneHandler) (unsigned int Channel,
+				    XDmaPs_Cmd *DmaCmd,
+				    void *CallbackRef);
+
+/**
+ * It's the fault handler a user can set for a channel
+ */
+typedef void (*XDmaPsFaultHandler) (unsigned int Channel,
+				     XDmaPs_Cmd *DmaCmd,
+				     void *CallbackRef);
+
+#define XDMAPS_MAX_CHAN_BUFS	2
+#define XDMAPS_CHAN_BUF_LEN	128
+
+/**
+ * The XDmaPs_ProgBuf is the struct for a DMA program buffer.
+ */
+typedef struct {
+	char Buf[XDMAPS_CHAN_BUF_LEN];  /**< The actual buffer the holds the
+					  *  content */
+	unsigned Len;			/**< The actual length of the DMA
+					  *  program in bytes. */
+	int Allocated;			/**< A tag indicating whether the
+					  *  buffer is allocated or not */
+} XDmaPs_ProgBuf;
+
+/**
+ * The XDmaPs_ChannelData is a struct to book keep individual channel of
+ * the DMAC.
+ */
+typedef struct {
+	unsigned DevId;		 	/**< Device id indicating which DMAC */
+	unsigned ChanId; 		/**< Channel number of the DMAC */
+	XDmaPs_ProgBuf ProgBufPool[XDMAPS_MAX_CHAN_BUFS]; /**< A pool of
+							      program buffers*/
+	XDmaPsDoneHandler DoneHandler; 	/**< Done interrupt handler */
+	void *DoneRef;			/**< Done interrupt callback data */
+	XDmaPs_Cmd *DmaCmdToHw; 	/**< DMA command being executed */
+	XDmaPs_Cmd *DmaCmdFromHw; 	/**< DMA  command that is finished.
+				     	  *  This field is for debugging purpose
+				     	  */
+	int HoldDmaProg;		/**< A tag indicating whether to hold the
+					  *  DMA program after the DMA is done.
+					  */
+
+} XDmaPs_ChannelData;
+
+/**
+ * The XDmaPs driver instance data structure. A pointer to an instance data
+ * structure is passed around by functions to refer to a specific driver
+ * instance.
+ */
+typedef struct {
+	XDmaPs_Config Config;	/**< Configuration data structure */
+	int IsReady;		/**< Device is Ready */
+	int CacheLength;	/**< icache length */
+	XDmaPsFaultHandler FaultHandler; /**< fault interrupt handler */
+	void *FaultRef;	/**< fault call back data */
+	XDmaPs_ChannelData Chans[XDMAPS_CHANNELS_PER_DEV];
+	/**<
+	 * channel data
+	 */
+} XDmaPs;
+
+/*
+ * Functions implemented in xdmaps.c
+ */
+int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
+			  XDmaPs_Config *Config,
+			  u32 EffectiveAddr);
+
+int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
+		  XDmaPs_Cmd *Cmd,
+		  int HoldDmaProg);
+
+int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel);
+int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel,
+		       XDmaPs_Cmd *Cmd);
+int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel,
+			XDmaPs_Cmd *Cmd);
+void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
+
+
+int XDmaPs_ResetManager(XDmaPs *InstPtr);
+int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel);
+
+
+int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
+			   unsigned Channel,
+			   XDmaPsDoneHandler DoneHandler,
+			   void *CallbackRef);
+
+int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
+			    XDmaPsFaultHandler FaultHandler,
+			    void *CallbackRef);
+
+void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
+
+/**
+ * To avoid linking error,Declare all inline functions as extern for
+ * IAR compiler
+ */
+#ifdef __ICCARM__
+extern INLINE int XDmaPs_Instr_DMAEND(char *DmaProg);
+extern INLINE void XDmaPs_Memcpy4(char *Dst, char *Src);
+extern INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
+			       u32 Imm, unsigned int Ns);
+extern INLINE int XDmaPs_Instr_DMALD(char *DmaProg);
+extern INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
+	       unsigned LoopIterations);
+extern INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc);
+extern INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm);
+extern INLINE int XDmaPs_Instr_DMANOP(char *DmaProg);
+extern INLINE int XDmaPs_Instr_DMARMB(char *DmaProg);
+extern INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber);
+extern INLINE int XDmaPs_Instr_DMAST(char *DmaProg);
+extern INLINE int XDmaPs_Instr_DMAWMB(char *DmaProg);
+extern INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize);
+extern INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize);
+#endif
+
+/**
+ * Driver done interrupt service routines for the channels.
+ * We need this done ISR mainly because the driver needs to release the
+ * DMA program buffer. This is the one that connects the GIC
+ */
+void XDmaPs_DoneISR_0(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_1(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_2(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_3(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_4(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_5(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_6(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_7(XDmaPs *InstPtr);
+
+/**
+ * Driver fault interrupt service routine
+ */
+void XDmaPs_FaultISR(XDmaPs *InstPtr);
+
+
+/*
+ * Static loopup function implemented in xdmaps_sinit.c
+ */
+XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId);
+
+
+/*
+ * self-test functions in xdmaps_selftest.c
+ */
+int XDmaPs_SelfTest(XDmaPs *InstPtr);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xdmaps_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xdmaps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..1186107ac0c3adbfbe389b1dae44e15edfa5765d
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xdmaps_hw.h
@@ -0,0 +1,293 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal 
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xdmaps_hw.h
+* @addtogroup dmaps_v2_1
+* @{
+*
+* This header file contains the hardware interface of an XDmaPs device.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who   Date     Changes
+* ----- ----  -------- ----------------------------------------------
+* 1.00a	hbm   08/18/10 First Release
+* 1.01a nm    12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+*		       the maximum number of channels.
+*		       Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+*                      with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h
+* 1.02a sg    05/16/12 Made changes for doxygen
+* 1.06a kpc   07/10/13 Added function prototype
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XDMAPS_HW_H		/* prevent circular inclusions */
+#define XDMAPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the DMAC.
+ * @{
+ */
+
+#define XDMAPS_DS_OFFSET		0x000 /* DMA Status Register */
+#define XDMAPS_DPC_OFFSET	0x004 /* DMA Program Counter Rregister */
+#define XDMAPS_INTEN_OFFSET	0X020 /* DMA Interrupt Enable Register */
+#define XDMAPS_ES_OFFSET		0x024 /* DMA Event Status Register */
+#define XDMAPS_INTSTATUS_OFFSET	0x028 /* DMA Interrupt Status Register
+					       */
+#define XDMAPS_INTCLR_OFFSET	0x02c /* DMA Interrupt Clear Register */
+#define XDMAPS_FSM_OFFSET 	0x030 /* DMA Fault Status DMA Manager
+				       * Register
+				       */
+#define XDMAPS_FSC_OFFSET	0x034 /* DMA Fault Status DMA Chanel Register
+				       */
+#define XDMAPS_FTM_OFFSET	0x038 /* DMA Fault Type DMA Manager Register */
+
+#define XDMAPS_FTC0_OFFSET	0x040 /* DMA Fault Type for DMA Channel 0 */
+/*
+ * The offset for the rest of the FTC registers is calculated as
+ * FTC0 + dev_chan_num * 4
+ */
+#define XDmaPs_FTCn_OFFSET(ch)	(XDMAPS_FTC0_OFFSET + (ch) * 4)
+
+#define XDMAPS_CS0_OFFSET	0x100 /* Channel Status for DMA Channel 0 */
+/*
+ * The offset for the rest of the CS registers is calculated as
+ * CS0 + * dev_chan_num * 0x08
+ */
+#define XDmaPs_CSn_OFFSET(ch)	(XDMAPS_CS0_OFFSET + (ch) * 8)
+
+#define XDMAPS_CPC0_OFFSET	0x104 /* Channel Program Counter for DMA
+				       * Channel 0
+				       */
+/*
+ * The offset for the rest of the CPC registers is calculated as
+ * CPC0 + dev_chan_num * 0x08
+ */
+#define XDmaPs_CPCn_OFFSET(ch)	(XDMAPS_CPC0_OFFSET + (ch) * 8)
+
+#define XDMAPS_SA_0_OFFSET	0x400 /* Source Address Register for DMA
+				       * Channel 0
+				       */
+/* The offset for the rest of the SA registers is calculated as
+ * SA_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_SA_n_OFFSET(ch)	(XDMAPS_SA_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_DA_0_OFFSET	0x404 /* Destination Address Register for
+				       * DMA Channel 0
+				       */
+/* The offset for the rest of the DA registers is calculated as
+ * DA_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_DA_n_OFFSET(ch)	(XDMAPS_DA_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_CC_0_OFFSET	0x408 /* Channel Control Register for
+				       * DMA Channel 0
+				       */
+/*
+ * The offset for the rest of the CC registers is calculated as
+ * CC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_CC_n_OFFSET(ch)	(XDMAPS_CC_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_LC0_0_OFFSET	0x40C /* Loop Counter 0 for DMA Channel 0 */
+/*
+ * The offset for the rest of the LC0 registers is calculated as
+ * LC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_LC0_n_OFFSET(ch)	(XDMAPS_LC0_0_OFFSET + (ch) * 0x20)
+#define XDMAPS_LC1_0_OFFSET	0x410 /* Loop Counter 1 for DMA Channel 0 */
+/*
+ * The offset for the rest of the LC1 registers is calculated as
+ * LC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_LC1_n_OFFSET(ch)	(XDMAPS_LC1_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_DBGSTATUS_OFFSET	0xD00 /* Debug Status Register */
+#define XDMAPS_DBGCMD_OFFSET	0xD04 /* Debug Command Register */
+#define XDMAPS_DBGINST0_OFFSET	0xD08 /* Debug Instruction 0 Register */
+#define XDMAPS_DBGINST1_OFFSET	0xD0C /* Debug Instruction 1 Register */
+
+#define XDMAPS_CR0_OFFSET	0xE00 /* Configuration Register 0 */
+#define XDMAPS_CR1_OFFSET	0xE04 /* Configuration Register 1 */
+#define XDMAPS_CR2_OFFSET	0xE08 /* Configuration Register 2 */
+#define XDMAPS_CR3_OFFSET	0xE0C /* Configuration Register 3 */
+#define XDMAPS_CR4_OFFSET	0xE10 /* Configuration Register 4 */
+#define XDMAPS_CRDN_OFFSET	0xE14 /* Configuration Register Dn */
+
+#define XDMAPS_PERIPH_ID_0_OFFSET	0xFE0 /* Peripheral Identification
+					       * Register 0
+					       */
+#define XDMAPS_PERIPH_ID_1_OFFSET	0xFE4 /* Peripheral Identification
+					       * Register 1
+					       */
+#define XDMAPS_PERIPH_ID_2_OFFSET	0xFE8 /* Peripheral Identification
+					       * Register 2
+					       */
+#define XDMAPS_PERIPH_ID_3_OFFSET	0xFEC /* Peripheral Identification
+					       * Register 3
+					       */
+#define XDMAPS_PCELL_ID_0_OFFSET	0xFF0 /* PrimeCell Identification
+				       * Register 0
+				       */
+#define XDMAPS_PCELL_ID_1_OFFSET	0xFF4 /* PrimeCell Identification
+				       * Register 1
+				       */
+#define XDMAPS_PCELL_ID_2_OFFSET	0xFF8 /* PrimeCell Identification
+				       * Register 2
+				       */
+#define XDMAPS_PCELL_ID_3_OFFSET	0xFFC /* PrimeCell Identification
+				       * Register 3
+				       */
+
+/*
+ * Some useful register masks
+ */
+#define XDMAPS_DS_DMA_STATUS		0x0F /* DMA status mask */
+#define XDMAPS_DS_DMA_STATUS_STOPPED	0x00 /* debug status busy mask */
+
+#define XDMAPS_DBGSTATUS_BUSY		0x01 /* debug status busy mask */
+
+#define XDMAPS_CS_ACTIVE_MASK		0x07 /* channel status active mask,
+					      * llast 3 bits of CS register
+					      */
+
+#define XDMAPS_CR1_I_CACHE_LEN_MASK	0x07 /* i_cache_len mask */
+
+
+/*
+ * XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register.
+ * @b1: Instruction byte 1
+ * @b0: Instruction byte 0
+ * @ch: Channel number
+ * @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel
+ */
+#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \
+	(((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1)))
+
+/* @} */
+
+/** @name Control Register
+ *
+ * The Control register (CR) controls the major functions of the device.
+ *
+ * Control Register Bit Definition
+ */
+
+/* @}*/
+
+
+#define XDMAPS_CHANNELS_PER_DEV		8
+
+
+/** @name Mode Register
+ *
+ * The mode register (MR) defines the mode of transfer as well as the data
+ * format. If this register is modified during transmission or reception,
+ * data validity cannot be guaranteed.
+ *
+ * Mode Register Bit Definition
+ * @{
+ */
+
+/* @} */
+
+
+/** @name Interrupt Registers
+ *
+ * Interrupt control logic uses the interrupt enable register (IER) and the
+ * interrupt disable register (IDR) to set the value of the bits in the
+ * interrupt mask register (IMR). The IMR determines whether to pass an
+ * interrupt to the interrupt status register (ISR).
+ * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
+ * interrupt. IMR and ISR are read only, and IER and IDR are write only.
+ * Reading either IER or IDR returns 0x00.
+ *
+ * All four registers have the same bit definitions.
+ *
+ * @{
+ */
+
+/* @} */
+#define XDMAPS_INTCLR_ALL_MASK		0xFF
+
+#define XDmaPs_ReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write a DMAC register.
+*
+* @param    BaseAddress contains the base address of the device.
+* @param    RegOffset contains the offset from the base address of the device.
+* @param    RegisterValue is the value to be written to the register.
+*
+* @return   None.
+*
+* @note
+* C-Style signature:
+*    void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset,
+*                          u32 RegisterValue)
+******************************************************************************/
+#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+    Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes *****************************/
+/*
+ * Perform reset operation to the dmaps interface
+ */
+void XDmaPs_ResetHw(u32 BaseAddr);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xemacps.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xemacps.h
new file mode 100644
index 0000000000000000000000000000000000000000..1dbdbb20d80a732c8424cf28b6e0d27c4e425ab9
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xemacps.h
@@ -0,0 +1,798 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+ *
+ * @file xemacps.h
+* @addtogroup emacps_v3_1
+* @{
+* @details
+ *
+ * The Xilinx Embedded Processor Block Ethernet driver.
+ *
+ * For a full description of XEMACPS features, please see the hardware spec.
+ * This driver supports the following features:
+ *   - Memory mapped access to host interface registers
+ *   - Statistics counter registers for RMON/MIB
+ *   - API for interrupt driven frame transfers for hardware configured DMA
+ *   - Virtual memory support
+ *   - Unicast, broadcast, and multicast receive address filtering
+ *   - Full and half duplex operation
+ *   - Automatic PAD & FCS insertion and stripping
+ *   - Flow control
+ *   - Support up to four 48bit addresses
+ *   - Address checking for four specific 48bit addresses
+ *   - VLAN frame support
+ *   - Pause frame support
+ *   - Large frame support up to 1536 bytes
+ *   - Checksum offload
+ *
+ * <b>Driver Description</b>
+ *
+ * The device driver enables higher layer software (e.g., an application) to
+ * communicate to the XEmacPs. The driver handles transmission and reception
+ * of Ethernet frames, as well as configuration and control. No pre or post
+ * processing of frame data is performed. The driver does not validate the
+ * contents of an incoming frame in addition to what has already occurred in
+ * hardware.
+ * A single device driver can support multiple devices even when those devices
+ * have significantly different configurations.
+ *
+ * <b>Initialization & Configuration</b>
+ *
+ * The XEmacPs_Config structure is used by the driver to configure itself.
+ * This configuration structure is typically created by the tool-chain based
+ * on hardware build properties.
+ *
+ * The driver instance can be initialized in
+ *
+ *   - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress):  Uses a
+ *     configuration structure provided by the caller. If running in a system
+ *     with address translation, the provided virtual memory base address
+ *     replaces the physical address present in the configuration structure.
+ *
+ * The device supports DMA only as current development plan. No FIFO mode is
+ * supported. The driver expects to start the DMA channels and expects that
+ * the user has set up the buffer descriptor lists.
+ *
+ * <b>Interrupts and Asynchronous Callbacks</b>
+ *
+ * The driver has no dependencies on the interrupt controller. When an
+ * interrupt occurs, the handler will perform a small amount of
+ * housekeeping work, determine the source of the interrupt, and call the
+ * appropriate callback function. All callbacks are registered by the user
+ * level application.
+ *
+ * <b>Virtual Memory</b>
+ *
+ * All virtual to physical memory mappings must occur prior to accessing the
+ * driver API.
+ *
+ * For DMA transactions, user buffers supplied to the driver must be in terms
+ * of their physical address.
+ *
+ * <b>DMA</b>
+ *
+ * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames.
+ * These BDs are typically chained together into a list the hardware follows
+ * when transferring data in and out of the packet buffers. Each BD describes
+ * a memory region containing either a full or partial Ethernet packet.
+ *
+ * Interrupt coalescing is not suppoted from this built-in DMA engine.
+ *
+ * This API requires the user to understand how the DMA operates. The
+ * following paragraphs provide some explanation, but the user is encouraged
+ * to read documentation in xemacps_bdring.h as well as study example code
+ * that accompanies this driver.
+ *
+ * The API is designed to get BDs to and from the DMA engine in the most
+ * efficient means possible. The first step is to establish a  memory region
+ * to contain all BDs for a specific channel. This is done with
+ * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will
+ * follow as BDs are processed. The ring will consist of a user defined number
+ * of BDs which will all be partially initialized. For example on the transmit
+ * channel, the driver will initialize all BDs' so that they are configured
+ * for transmit. The more fields that can be permanently setup at
+ * initialization, then the fewer accesses will be needed to each BD while
+ * the DMA engine is in operation resulting in better throughput and CPU
+ * utilization. The best case initialization would require the user to set
+ * only a frame buffer address and length prior to submitting the BD to the
+ * engine.
+ *
+ * BDs move through the engine with the help of functions
+ * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(),
+ * and XEmacPs_BdRingFree().
+ * All these functions handle BDs that are in place. That is, there are no
+ * copies of BDs kept anywhere and any BD the user interacts with is an actual
+ * BD from the same ring hardware accesses.
+ *
+ * BDs in the ring go through a series of states as follows:
+ *   1. Idle. The driver controls BDs in this state.
+ *   2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to
+ *      reserve BD(s). Once allocated, the user may setup the BD(s) with
+ *      frame buffer address, length, and other attributes. The user controls
+ *      BDs in this state.
+ *   3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs
+ *      in this state are either waiting to be processed by hardware, are in
+ *      process, or have been processed. The DMA engine controls BDs in this
+ *      state.
+ *   4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the
+ *      user. Once retrieved, the user can examine each BD for the outcome of
+ *      the DMA transfer. The user controls BDs in this state. After examining
+ *      the BDs the user calls XEmacPs_BdRingFree() which places the BDs back
+ *      into state 1.
+ *
+ * Each of the four BD accessor functions operate on a set of BDs. A set is
+ * defined as a segment of the BD ring consisting of one or more BDs. The user
+ * views the set as a pointer to the first BD along with the number of BDs for
+ * that set. The set can be navigated by using macros XEmacPs_BdNext(). The
+ * user must exercise extreme caution when changing BDs in a set as there is
+ * nothing to prevent doing a mBdNext past the end of the set and modifying a
+ * BD out of bounds.
+ *
+ * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as
+ * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in
+ * tandem. The same BD set retrieved with BdRingAlloc should be the same one
+ * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and
+ * BdRIngFree.
+ *
+ * <b>Alignment & Data Cache Restrictions</b>
+ *
+ * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte
+ * aligned. Please reference xemacps_bd.h for cache related macros.
+ *
+ * DMA Tx:
+ *
+ *   - If frame buffers exist in cached memory, then they must be flushed
+ *     prior to committing them to hardware.
+ *
+ * DMA Rx:
+ *
+ *   - If frame buffers exist in cached memory, then the cache must be
+ *     invalidated for the memory region containing the frame prior to data
+ *     access
+ *
+ * Both cache invalidate/flush are taken care of in driver code.
+ *
+ * <b>Buffer Copying</b>
+ *
+ * The driver is designed for a zero-copy buffer scheme. That is, the driver
+ * will not copy buffers. This avoids potential throughput bottlenecks within
+ * the driver. If byte copying is required, then the transfer will take longer
+ * to complete.
+ *
+ * <b>Checksum Offloading</b>
+ *
+ * The Embedded Processor Block Ethernet can be configured to perform IP, TCP
+ * and UDP checksum offloading in both receive and transmit directions.
+ *
+ * IP packets contain a 16-bit checksum field, which is the 16-bit 1s
+ * complement of the 1s complement sum of all 16-bit words in the header.
+ * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit
+ * 1s complement of the 1s complement sum of all 16-bit words in the header,
+ * the data and a conceptual pseudo header.
+ *
+ * To calculate these checksums in software requires each byte of the packet
+ * to be read. For TCP and UDP this can use a large amount of processing power.
+ * Offloading the checksum calculation to hardware can result in significant
+ * performance improvements.
+ *
+ * The transmit checksum offload is only available to use DMA in packet buffer
+ * mode. This is because the complete frame to be transmitted must be read
+ * into the packet buffer memory before the checksum can be calculated and
+ * written to the header at the beginning of the frame.
+ *
+ * For IP, TCP or UDP receive checksum offload to be useful, the operating
+ * system containing the protocol stack must be aware that this offload is
+ * available so that it can make use of the fact that the hardware has verified
+ * the checksum.
+ *
+ * When receive checksum offloading is enabled in the hardware, the IP header
+ * checksum is checked, where the packet meets the following criteria:
+ *
+ * 1. If present, the VLAN header must be four octets long and the CFI bit
+ *    must not be set.
+ * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP
+ *    encoding.
+ * 3. IP v4 packet.
+ * 4. IP header is of a valid length.
+ * 5. Good IP header checksum.
+ * 6. No IP fragmentation.
+ * 7. TCP or UDP packet.
+ *
+ * When an IP, TCP or UDP frame is received, the receive buffer descriptor
+ * gives an indication if the hardware was able to verify the checksums.
+ * There is also an indication if the frame had SNAP encapsulation. These
+ * indication bits will replace the type ID match indication bits when the
+ * receive checksum offload is enabled.
+ *
+ * If any of the checksums are verified incorrect by the hardware, the packet
+ * is discarded and the appropriate statistics counter incremented.
+ *
+ * <b>PHY Interfaces</b>
+ *
+ * RGMII 1.3 is the only interface supported.
+ *
+ * <b>Asserts</b>
+ *
+ * Asserts are used within all Xilinx drivers to enforce constraints on
+ * parameters. Asserts can be turned off on a system-wide basis by defining,
+ * at compile time, the NDEBUG identifier. By default, asserts are turned on
+ * and it is recommended that users leave asserts on during development. For
+ * deployment use -DNDEBUG compiler switch to remove assert code.
+ *
+ * @note
+ *
+ * Xilinx drivers are typically composed of two parts, one is the driver
+ * and the other is the adapter.  The driver is independent of OS and processor
+ * and is intended to be highly portable.  The adapter is OS-specific and
+ * facilitates communication between the driver and an OS.
+ * This driver is intended to be RTOS and processor independent. Any needs for
+ * dynamic memory management, threads or thread mutual exclusion, or cache
+ * control must be satisfied bythe layer above this driver.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ * 1.00a asa  11/21/11 The function XEmacPs_BdRingFromHwTx in file
+ *		       xemacps_bdring.c is modified. Earlier it was checking for
+ *		       "BdLimit"(passed argument) number of BDs for finding out
+ *		       which BDs are successfully processed. Now one more check
+ *		       is added. It looks for BDs till the current BD pointer
+ *		       reaches HwTail. By doing this processing time is saved.
+ * 1.00a asa  01/24/12 The function XEmacPs_BdRingFromHwTx in file
+ *		       xemacps_bdring.c is modified. Now start of packet is
+ *		       searched for returning the number of BDs processed.
+ * 1.02a asa  11/05/12 Added a new API for deleting an entry from the HASH
+ *		       registers. Added a new API to set the bust length.
+ *		       Added some new hash-defines.
+ * 1.03a asa  01/23/12 Fix for CR #692702 which updates error handling for
+ *		       Rx errors. Under heavy Rx traffic, there will be a large
+ *		       number of errors related to receive buffer not available.
+ *		       Because of a HW bug (SI #692601), under such heavy errors,
+ *		       the Rx data path can become unresponsive. To reduce the
+ *		       probabilities for hitting this HW bug, the SW writes to
+ *		       bit 18 to flush a packet from Rx DPRAM immediately. The
+ *		       changes for it are done in the function
+ *		       XEmacPs_IntrHandler.
+ * 1.05a asa  09/23/13 Cache operations on BDs are not required and hence
+ *		       removed. It is expected that all BDs are allocated in
+ *		       from uncached area.
+ * 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+ *				to 0x1fff. This fixes the CR#744902.
+ *			  Made changes in example file xemacps_example.h to fix compilation
+ *			  issues with iarcc compiler.
+ * 2.0   adk  10/12/13 Updated as per the New Tcl API's
+ * 2.1   adk  11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
+ * 2.1   bss  09/08/14 Modified driver tcl to fix CR#820349 to export phy
+ *		       address in xparameters.h when GMII to RGMII converter
+ *		       is present in hw.
+ * 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
+ *		       changes.
+ * 2.2   adk  29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
+ *                    1000BASE-X mode export proper values to the xparameters.h
+ *                    file. Changes are made in the driver tcl file.
+ * 3.0   adk  08/1/15  Don't include gem in peripheral test when gem is
+ *                    configured with PCS/PMA Core. Changes are made in the
+ *		       test app tcl(CR:827686).
+ * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0   hk   03/18/15 Added support for jumbo frames. Increase AHB burst.
+ *                     Disable extended mode. Perform all 64 bit changes under
+ *                     check for arch64.
+ *                     Remove "used bit set" from TX error interrupt masks.
+ * 3.1   hk   07/27/15 Do not call error handler with '0' error code when
+ *                     there is no error. CR# 869403
+ *            08/10/15 Update upper 32 bit tx and rx queue ptr registers.
+ * 3.2   hk   02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+ * 3.4   ms   01/23/17 Modified xil_printf statement in main function for all
+ *                     examples to ensure that "Successfully ran" and "Failed"
+ *                     strings are available in all examples. This is a fix
+ *                     for CR-965028.
+ *       ms   03/17/17 Modified text file in examples folder for doxygen
+ *                     generation.
+ * </pre>
+ *
+ ****************************************************************************/
+
+#ifndef XEMACPS_H		/* prevent circular inclusions */
+#define XEMACPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xemacps_hw.h"
+#include "xemacps_bd.h"
+#include "xemacps_bdring.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * Device information
+ */
+#define XEMACPS_DEVICE_NAME     "xemacps"
+#define XEMACPS_DEVICE_DESC     "Xilinx PS 10/100/1000 MAC"
+
+
+/** @name Configuration options
+ *
+ * Device configuration options. See the XEmacPs_SetOptions(),
+ * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to
+ * use options.
+ *
+ * The default state of the options are noted and are what the device and
+ * driver will be set to after calling XEmacPs_Reset() or
+ * XEmacPs_Initialize().
+ *
+ * @{
+ */
+
+#define XEMACPS_PROMISC_OPTION               0x00000001U
+/**< Accept all incoming packets.
+ *   This option defaults to disabled (cleared) */
+
+#define XEMACPS_FRAME1536_OPTION             0x00000002U
+/**< Frame larger than 1516 support for Tx & Rx.
+ *   This option defaults to disabled (cleared) */
+
+#define XEMACPS_VLAN_OPTION                  0x00000004U
+/**< VLAN Rx & Tx frame support.
+ *   This option defaults to disabled (cleared) */
+
+#define XEMACPS_FLOW_CONTROL_OPTION          0x00000010U
+/**< Enable recognition of flow control frames on Rx
+ *   This option defaults to enabled (set) */
+
+#define XEMACPS_FCS_STRIP_OPTION             0x00000020U
+/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
+ *   stripped.
+ *   This option defaults to enabled (set) */
+
+#define XEMACPS_FCS_INSERT_OPTION            0x00000040U
+/**< Generate FCS field and add PAD automatically for outgoing frames.
+ *   This option defaults to disabled (cleared) */
+
+#define XEMACPS_LENTYPE_ERR_OPTION           0x00000080U
+/**< Enable Length/Type error checking for incoming frames. When this option is
+ *   set, the MAC will filter frames that have a mismatched type/length field
+ *   and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these
+ *   types of frames are encountered. When this option is cleared, the MAC will
+ *   allow these types of frames to be received.
+ *
+ *   This option defaults to disabled (cleared) */
+
+#define XEMACPS_TRANSMITTER_ENABLE_OPTION    0x00000100U
+/**< Enable the transmitter.
+ *   This option defaults to enabled (set) */
+
+#define XEMACPS_RECEIVER_ENABLE_OPTION       0x00000200U
+/**< Enable the receiver
+ *   This option defaults to enabled (set) */
+
+#define XEMACPS_BROADCAST_OPTION             0x00000400U
+/**< Allow reception of the broadcast address
+ *   This option defaults to enabled (set) */
+
+#define XEMACPS_MULTICAST_OPTION             0x00000800U
+/**< Allows reception of multicast addresses programmed into hash
+ *   This option defaults to disabled (clear) */
+
+#define XEMACPS_RX_CHKSUM_ENABLE_OPTION      0x00001000U
+/**< Enable the RX checksum offload
+ *   This option defaults to enabled (set) */
+
+#define XEMACPS_TX_CHKSUM_ENABLE_OPTION      0x00002000U
+/**< Enable the TX checksum offload
+ *   This option defaults to enabled (set) */
+
+#define XEMACPS_JUMBO_ENABLE_OPTION	0x00004000U
+#define XEMACPS_SGMII_ENABLE_OPTION	0x00008000U
+
+#define XEMACPS_DEFAULT_OPTIONS                     \
+    ((u32)XEMACPS_FLOW_CONTROL_OPTION |                  \
+     (u32)XEMACPS_FCS_INSERT_OPTION |                    \
+     (u32)XEMACPS_FCS_STRIP_OPTION |                     \
+     (u32)XEMACPS_BROADCAST_OPTION |                     \
+     (u32)XEMACPS_LENTYPE_ERR_OPTION |                   \
+     (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION |            \
+     (u32)XEMACPS_RECEIVER_ENABLE_OPTION |               \
+     (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION |              \
+     (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
+
+/**< Default options set when device is initialized or reset */
+/*@}*/
+
+/** @name Callback identifiers
+ *
+ * These constants are used as parameters to XEmacPs_SetHandler()
+ * @{
+ */
+#define XEMACPS_HANDLER_DMASEND 1U
+#define XEMACPS_HANDLER_DMARECV 2U
+#define XEMACPS_HANDLER_ERROR   3U
+/*@}*/
+
+/* Constants to determine the configuration of the hardware device. They are
+ * used to allow the driver to verify it can operate with the hardware.
+ */
+#define XEMACPS_MDIO_DIV_DFT    MDC_DIV_32 /**< Default MDIO clock divisor */
+
+/* The next few constants help upper layers determine the size of memory
+ * pools used for Ethernet buffers and descriptor lists.
+ */
+#define XEMACPS_MAC_ADDR_SIZE   6U	/* size of Ethernet header */
+
+#define XEMACPS_MTU             1500U	/* max MTU size of Ethernet frame */
+#define XEMACPS_MTU_JUMBO       10240U	/* max MTU size of jumbo frame */
+#define XEMACPS_HDR_SIZE        14U	/* size of Ethernet header */
+#define XEMACPS_HDR_VLAN_SIZE   18U	/* size of Ethernet header with VLAN */
+#define XEMACPS_TRL_SIZE        4U	/* size of Ethernet trailer (FCS) */
+#define XEMACPS_MAX_FRAME_SIZE       (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
+        XEMACPS_TRL_SIZE)
+#define XEMACPS_MAX_VLAN_FRAME_SIZE  (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
+        XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
+#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO  (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \
+        XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
+
+/* DMACR Bust length hash defines */
+
+#define XEMACPS_SINGLE_BURST	0x00000001
+#define XEMACPS_4BYTE_BURST		0x00000004
+#define XEMACPS_8BYTE_BURST		0x00000008
+#define XEMACPS_16BYTE_BURST	0x00000010
+
+
+/**************************** Type Definitions ******************************/
+/** @name Typedefs for callback functions
+ *
+ * These callbacks are invoked in interrupt context.
+ * @{
+ */
+/**
+ * Callback invoked when frame(s) have been sent or received in interrupt
+ * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler().
+ *
+ * @param CallBackRef is user data assigned when the callback was set.
+ *
+ * @note
+ * See xemacps_hw.h for bitmasks definitions and the device hardware spec for
+ * further information on their meaning.
+ *
+ */
+typedef void (*XEmacPs_Handler) (void *CallBackRef);
+
+/**
+ * Callback when an asynchronous error occurs. To set this callback, invoke
+ * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType
+ * paramter.
+ *
+ * @param CallBackRef is user data assigned when the callback was set.
+ * @param Direction defines either receive or transmit error(s) has occurred.
+ * @param ErrorWord definition varies with Direction
+ *
+ */
+typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
+				     u32 ErrorWord);
+
+/*@}*/
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+	u16 DeviceId;	/**< Unique ID  of device */
+	UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
+} XEmacPs_Config;
+
+
+/**
+ * The XEmacPs driver instance data. The user is required to allocate a
+ * structure of this type for every XEmacPs device in the system. A pointer
+ * to a structure of this type is then passed to the driver API functions.
+ */
+typedef struct XEmacPs_Instance {
+	XEmacPs_Config Config;	/* Hardware configuration */
+	u32 IsStarted;		/* Device is currently started */
+	u32 IsReady;		/* Device is initialized and ready */
+	u32 Options;		/* Current options word */
+
+	XEmacPs_BdRing TxBdRing;	/* Transmit BD ring */
+	XEmacPs_BdRing RxBdRing;	/* Receive BD ring */
+
+	XEmacPs_Handler SendHandler;
+	XEmacPs_Handler RecvHandler;
+	void *SendRef;
+	void *RecvRef;
+
+	XEmacPs_ErrHandler ErrorHandler;
+	void *ErrorRef;
+	u32 Version;
+	u32 RxBufMask;
+	u32 MaxMtuSize;
+	u32 MaxFrameSize;
+	u32 MaxVlanFrameSize;
+
+} XEmacPs;
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Retrieve the Tx ring object. This object can be used in the various Ring
+* API functions.
+*
+* @param  InstancePtr is the DMA channel to operate on.
+*
+* @return TxBdRing attribute
+*
+* @note
+* C-style signature:
+*    XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing)
+
+/****************************************************************************/
+/**
+* Retrieve the Rx ring object. This object can be used in the various Ring
+* API functions.
+*
+* @param  InstancePtr is the DMA channel to operate on.
+*
+* @return RxBdRing attribute
+*
+* @note
+* C-style signature:
+*    XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing)
+
+/****************************************************************************/
+/**
+*
+* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
+* each bit set to 1 in <i>Mask</i>, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to enable. The mask can
+*        be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+*     void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntEnable(InstancePtr, Mask)                            \
+	XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
+		XEMACPS_IER_OFFSET,                                     \
+		((Mask) & XEMACPS_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
+* each bit set to 1 in <i>Mask</i>, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to disable. The mask can
+*        be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+*     void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntDisable(InstancePtr, Mask)                           \
+	XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
+		XEMACPS_IDR_OFFSET,                                     \
+		((Mask) & XEMACPS_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
+* each bit set to 1 in <i>Mask</i>, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to enable. The mask can
+*        be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+*     void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntQ1Enable(InstancePtr, Mask)                            \
+	XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
+		XEMACPS_INTQ1_IER_OFFSET,                                \
+		((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
+* each bit set to 1 in <i>Mask</i>, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to disable. The mask can
+*        be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+*     void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntQ1Disable(InstancePtr, Mask)                           \
+	XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
+		XEMACPS_INTQ1_IDR_OFFSET,                               \
+		((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* This macro triggers trasmit circuit to send data currently in TX buffer(s).
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* @note
+*
+* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_Transmit(InstancePtr)                              \
+        XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,          \
+        XEMACPS_NWCTRL_OFFSET,                                     \
+        (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress,          \
+        XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
+
+/****************************************************************************/
+/**
+*
+* This macro determines if the device is configured with checksum offloading
+* on the receive channel
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* Boolean TRUE if the device is configured with checksum offloading, or
+* FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_IsRxCsum(InstancePtr)                                     \
+        ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress,             \
+          XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U     \
+          ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* This macro determines if the device is configured with checksum offloading
+* on the transmit channel
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* Boolean TRUE if the device is configured with checksum offloading, or
+* FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_IsTxCsum(InstancePtr)                                     \
+        ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress,              \
+          XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U       \
+          ? TRUE : FALSE)
+
+/************************** Function Prototypes *****************************/
+
+/*
+ * Initialization functions in xemacps.c
+ */
+LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
+			   UINTPTR EffectiveAddress);
+void XEmacPs_Start(XEmacPs *InstancePtr);
+void XEmacPs_Stop(XEmacPs *InstancePtr);
+void XEmacPs_Reset(XEmacPs *InstancePtr);
+void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
+			 u16 Direction);
+
+/*
+ * Lookup configuration in xemacps_sinit.c
+ */
+XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Interrupt-related functions in xemacps_intr.c
+ * DMA only and FIFO is not supported. This DMA does not support coalescing.
+ */
+LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
+			void *FuncPointer, void *CallBackRef);
+void XEmacPs_IntrHandler(void *XEmacPsPtr);
+
+/*
+ * MAC configuration/control functions in XEmacPs_control.c
+ */
+LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options);
+LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options);
+u32 XEmacPs_GetOptions(XEmacPs *InstancePtr);
+
+LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
+LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr);
+void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
+
+LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr);
+void XEmacPs_ClearHash(XEmacPs *InstancePtr);
+void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
+
+void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
+				XEmacPs_MdcDiv Divisor);
+void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
+u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
+LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
+		     u32 RegisterNum, u16 *PhyDataPtr);
+LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
+		      u32 RegisterNum, u16 PhyData);
+LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
+
+LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr);
+void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xemacps_bd.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xemacps_bd.h
new file mode 100644
index 0000000000000000000000000000000000000000..52c5f7e7e2b6f845f7010acb26ccdcd127bacc28
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xemacps_bd.h
@@ -0,0 +1,804 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xemacps_bd.h
+* @addtogroup emacps_v3_1
+* @{
+ *
+ * This header provides operations to manage buffer descriptors in support
+ * of scatter-gather DMA.
+ *
+ * The API exported by this header defines abstracted macros that allow the
+ * user to read/write specific BD fields.
+ *
+ * <b>Buffer Descriptors</b>
+ *
+ * A buffer descriptor (BD) defines a DMA transaction. The macros defined by
+ * this header file allow access to most fields within a BD to tailor a DMA
+ * transaction according to user and hardware requirements.  See the hardware
+ * IP DMA spec for more information on BD fields and how they affect transfers.
+ *
+ * The XEmacPs_Bd structure defines a BD. The organization of this structure
+ * is driven mainly by the hardware for use in scatter-gather DMA transfers.
+ *
+ * <b>Performance</b>
+ *
+ * Limiting I/O to BDs can improve overall performance of the DMA channel.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ * 2.1   srt  07/15/14 Add support for Zynq Ultrascale MP GEM specification
+ *                     and 64-bit changes.
+ * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0   hk   02/20/15 Added support for jumbo frames.
+ *                     Disable extended mode. Perform all 64 bit changes under
+ *                     check for arch64.
+ * 3.2   hk   11/18/15 Change BD typedef and number of words.
+ *
+ * </pre>
+ *
+ * ***************************************************************************
+ */
+
+#ifndef XEMACPS_BD_H		/* prevent circular inclusions */
+#define XEMACPS_BD_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include <string.h>
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+#ifdef __aarch64__
+/* Minimum BD alignment */
+#define XEMACPS_DMABD_MINIMUM_ALIGNMENT  64U
+#define XEMACPS_BD_NUM_WORDS 4U
+#else
+/* Minimum BD alignment */
+#define XEMACPS_DMABD_MINIMUM_ALIGNMENT  4U
+#define XEMACPS_BD_NUM_WORDS 2U
+#endif
+
+/**
+ * The XEmacPs_Bd is the type for buffer descriptors (BDs).
+ */
+typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ * Zero out BD fields
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @return Nothing
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdClear(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClear(BdPtr)                                  \
+    memset((BdPtr), 0, sizeof(XEmacPs_Bd))
+
+/****************************************************************************/
+/**
+*
+* Read the given Buffer Descriptor word.
+*
+* @param    BaseAddress is the base address of the BD to read
+* @param    Offset is the word offset to be read
+*
+* @return   The 32-bit value of the field
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset)
+*
+*****************************************************************************/
+#define XEmacPs_BdRead(BaseAddress, Offset)             \
+	(*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Buffer Descriptor word.
+*
+* @param    BaseAddress is the base address of the BD to write
+* @param    Offset is the word offset to be written
+* @param    Data is the 32-bit value to write to the field
+*
+* @return   None.
+*
+* @note
+* C-style signature:
+*    void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data)
+*
+*****************************************************************************/
+#define XEmacPs_BdWrite(BaseAddress, Offset, Data)              \
+    (*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data))
+
+/*****************************************************************************/
+/**
+ * Set the BD's Address field (word 0).
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ * @param  Addr  is the value to write to BD's status field.
+ *
+ * @note :
+ *
+ * C-style signature:
+ *    void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
+ *
+ *****************************************************************************/
+#ifdef __aarch64__
+#define XEmacPs_BdSetAddressTx(BdPtr, Addr)                        \
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET,		\
+			(u32)((Addr) & ULONG64_LO_MASK));		\
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET,		\
+	(u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
+#else
+#define XEmacPs_BdSetAddressTx(BdPtr, Addr)                        \
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set the BD's Address field (word 0).
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ * @param  Addr  is the value to write to BD's status field.
+ *
+ * @note : Due to some bits are mixed within recevie BD's address field,
+ *         read-modify-write is performed.
+ *
+ * C-style signature:
+ *    void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
+ *
+ *****************************************************************************/
+#ifdef __aarch64__
+#define XEmacPs_BdSetAddressRx(BdPtr, Addr)                        \
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET,              \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) &           \
+	~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK))));  \
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, 	\
+	(u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
+#else
+#define XEmacPs_BdSetAddressRx(BdPtr, Addr)                        \
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET,              \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) &           \
+    ~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr)))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set the BD's Status field (word 1).
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ * @param  Data  is the value to write to BD's status field.
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetStatus(BdPtr, Data)                           \
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,              \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data))
+
+
+/*****************************************************************************/
+/**
+ * Retrieve the BD's Packet DMA transfer status word (word 1).
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @return Status word
+ *
+ * @note
+ * C-style signature:
+ *    u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr)
+ *
+ * Due to the BD bit layout differences in transmit and receive. User's
+ * caution is required.
+ *****************************************************************************/
+#define XEmacPs_BdGetStatus(BdPtr)                                 \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET)
+
+
+/*****************************************************************************/
+/**
+ * Get the address (bits 0..31) of the BD's buffer address (word 0)
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#ifdef __aarch64__
+#define XEmacPs_BdGetBufAddr(BdPtr)                               \
+    (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) |		  \
+	(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
+#else
+#define XEmacPs_BdGetBufAddr(BdPtr)                               \
+    (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set transfer length in bytes for the given BD. The length must be set each
+ * time a BD is submitted to hardware.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ * @param  LenBytes is the number of bytes to transfer.
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetLength(BdPtr, LenBytes)                       \
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,              \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
+
+
+
+/*****************************************************************************/
+/**
+ * Set transfer length in bytes for the given BD. The length must be set each
+ * time a BD is submitted to hardware.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ * @param  LenBytes is the number of bytes to transfer.
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetLength(BdPtr, LenBytes)                       \
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,              \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
+
+
+/*****************************************************************************/
+/**
+ * Retrieve the BD length field.
+ *
+ * For Tx channels, the returned value is the same as that written with
+ * XEmacPs_BdSetLength().
+ *
+ * For Rx channels, the returned value is the size of the received packet.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @return Length field processed by hardware or set by
+ *         XEmacPs_BdSetLength().
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr)
+ *    XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK.
+ *
+ *****************************************************************************/
+#define XEmacPs_BdGetLength(BdPtr)                                 \
+    (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &            \
+    XEMACPS_RXBUF_LEN_MASK)
+
+/*****************************************************************************/
+/**
+ * Retrieve the RX frame size.
+ *
+ * The returned value is the size of the received packet.
+ * This API supports jumbo frame sizes if enabled.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @return Length field processed by hardware or set by
+ *         XEmacPs_BdSetLength().
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr)
+ *    RxBufMask is dependent on whether jumbo is enabled or not.
+ *
+ *****************************************************************************/
+#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr)                   \
+    (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &            \
+    (InstancePtr)->RxBufMask)
+
+/*****************************************************************************/
+/**
+ * Test whether the given BD has been marked as the last BD of a packet.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsLast(BdPtr)                                    \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Tell the DMA engine that the given transmit BD marks the end of the current
+ * packet to be processed.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetLast(BdPtr)                                   \
+    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) |             \
+    XEMACPS_TXBUF_LAST_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Tell the DMA engine that the current packet does not end with the given
+ * BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearLast(BdPtr)                                 \
+    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &             \
+    ~XEMACPS_TXBUF_LAST_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Set this bit to mark the last descriptor in the receive buffer descriptor
+ * list.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+/*#define XEmacPs_BdSetRxWrap(BdPtr)                                 \
+    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET,             \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) |             \
+    XEMACPS_RXBUF_WRAP_MASK))
+*/
+
+/*****************************************************************************/
+/**
+ * Determine the wrap bit of the receive BD which indicates end of the
+ * BD list.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxWrap(BdPtr)                                  \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) &           \
+    XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Sets this bit to mark the last descriptor in the transmit buffer
+ * descriptor list.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+/*#define XEmacPs_BdSetTxWrap(BdPtr)                                 \
+    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) |             \
+    XEMACPS_TXBUF_WRAP_MASK))
+*/
+
+/*****************************************************************************/
+/**
+ * Determine the wrap bit of the transmit BD which indicates end of the
+ * BD list.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxWrap(BdPtr)                                  \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/*
+ * Must clear this bit to enable the MAC to write data to the receive
+ * buffer. Hardware sets this bit once it has successfully written a frame to
+ * memory. Once set, software has to clear the bit before the buffer can be
+ * used again. This macro clear the new bit of the receive BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearRxNew(BdPtr)                                \
+    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET,             \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) &             \
+    ~XEMACPS_RXBUF_NEW_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the new bit of the receive BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxNew(BdPtr)                                   \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) &           \
+    XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Software sets this bit to disable the buffer to be read by the hardware.
+ * Hardware sets this bit for the first buffer of a frame once it has been
+ * successfully transmitted. This macro sets this bit of transmit BD to avoid
+ * confusion.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetTxUsed(BdPtr)                                 \
+    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) |             \
+    XEMACPS_TXBUF_USED_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Software clears this bit to enable the buffer to be read by the hardware.
+ * Hardware sets this bit for the first buffer of a frame once it has been
+ * successfully transmitted. This macro clears this bit of transmit BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearTxUsed(BdPtr)                               \
+    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &             \
+    ~XEMACPS_TXBUF_USED_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the used bit of the transmit BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxUsed(BdPtr)                                  \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to too many retries.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxRetry(BdPtr)                                 \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to data can not be
+ * feteched in time or buffers are exhausted.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxUrun(BdPtr)                                  \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to buffer is exhausted
+ * mid-frame.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxExh(BdPtr)                                   \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Sets this bit, no CRC will be appended to the current frame. This control
+ * bit must be set for the first buffer in a frame and will be ignored for
+ * the subsequent buffers of a frame.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * This bit must be clear when using the transmit checksum generation offload,
+ * otherwise checksum generation and substitution will not occur.
+ *
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetTxNoCRC(BdPtr)                                \
+    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) |             \
+    XEMACPS_TXBUF_NOCRC_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Clear this bit, CRC will be appended to the current frame. This control
+ * bit must be set for the first buffer in a frame and will be ignored for
+ * the subsequent buffers of a frame.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * This bit must be clear when using the transmit checksum generation offload,
+ * otherwise checksum generation and substitution will not occur.
+ *
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearTxNoCRC(BdPtr)                              \
+    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &             \
+    ~XEMACPS_TXBUF_NOCRC_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the broadcast bit of the receive BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxBcast(BdPtr)                                 \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the multicast hash bit of the receive BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxMultiHash(BdPtr)                             \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the unicast hash bit of the receive BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxUniHash(BdPtr)                               \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame is a VLAN Tagged frame.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxVlan(BdPtr)                                  \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame has Type ID of 8100h and null VLAN
+ * identifier(Priority tag).
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxPri(BdPtr)                                   \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame's Concatenation Format Indicator (CFI) of
+ * the frames VLANTCI field was set.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxCFI(BdPtr)                                   \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the End Of Frame (EOF) bit of the receive BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxEOF(BdPtr)                                   \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the Start Of Frame (SOF) bit of the receive BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxSOF(BdPtr)                                   \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xemacps_bdring.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xemacps_bdring.h
new file mode 100644
index 0000000000000000000000000000000000000000..de78cf28f7e14d645d9a7d065bacd1b5de373ad7
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xemacps_bdring.h
@@ -0,0 +1,238 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_bdring.h
+* @addtogroup emacps_v3_1
+* @{
+*
+* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
+* DMA functionalities.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp architecture.
+* 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XEMACPS_BDRING_H	/* prevent curcular inclusions */
+#define XEMACPS_BDRING_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**************************** Type Definitions *******************************/
+
+/** This is an internal structure used to maintain the DMA list */
+typedef struct {
+	UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
+	UINTPTR BaseBdAddr;	 /**< Virtual address of 1st BD in list */
+	UINTPTR HighBdAddr;	 /**< Virtual address of last BD in the list */
+	u32 Length;	 /**< Total size of ring in bytes */
+	u32 RunState;	 /**< Flag to indicate DMA is started */
+	u32 Separation;	 /**< Number of bytes between the starting address
+                                  of adjacent BDs */
+	XEmacPs_Bd *FreeHead;
+			     /**< First BD in the free group */
+	XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
+	XEmacPs_Bd *HwHead; /**< First BD in the work group */
+	XEmacPs_Bd *HwTail; /**< Last BD in the work group */
+	XEmacPs_Bd *PostHead;
+			     /**< First BD in the post-work group */
+	XEmacPs_Bd *BdaRestart;
+			     /**< BDA to load when channel is started */
+
+	u32 HwCnt;	     /**< Number of BDs in work group */
+	u32 PreCnt;     /**< Number of BDs in pre-work group */
+	u32 FreeCnt;    /**< Number of allocatable BDs in the free group */
+	u32 PostCnt;    /**< Number of BDs in post-work group */
+	u32 AllCnt;     /**< Total Number of BDs for channel */
+} XEmacPs_BdRing;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many BDs will fit
+* in a BD list within the given memory constraints.
+*
+* The results of this macro can be provided to XEmacPs_BdRingCreate().
+*
+* @param Alignment specifies what byte alignment the BDs must fall on and
+*        must be a power of 2 to get an accurate calculation (32, 64, 128,...)
+* @param Bytes is the number of bytes to be used to store BDs.
+*
+* @return Number of BDs that can fit in the given memory area
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)
+*
+******************************************************************************/
+#define XEmacPs_BdRingCntCalc(Alignment, Bytes)                    \
+    (u32)((Bytes) / (sizeof(XEmacPs_Bd)))
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many bytes of memory
+* is required to contain a given number of BDs at a given alignment.
+*
+* @param Alignment specifies what byte alignment the BDs must fall on. This
+*        parameter must be a power of 2 to get an accurate calculation (32, 64,
+*        128,...)
+* @param NumBd is the number of BDs to calculate memory size requirements for
+*
+* @return The number of bytes of memory required to create a BD list with the
+*         given memory constraints.
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)
+*
+******************************************************************************/
+#define XEmacPs_BdRingMemCalc(Alignment, NumBd)                    \
+    (u32)(sizeof(XEmacPs_Bd) * (NumBd))
+
+/****************************************************************************/
+/**
+* Return the total number of BDs allocated by this channel with
+* XEmacPs_BdRingCreate().
+*
+* @param  RingPtr is the DMA channel to operate on.
+*
+* @return The total number of BDs allocated for this channel.
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
+
+/****************************************************************************/
+/**
+* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre-
+* processing.
+*
+* @param  RingPtr is the DMA channel to operate on.
+*
+* @return The number of BDs currently allocatable.
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetFreeCnt(RingPtr)   ((RingPtr)->FreeCnt)
+
+/****************************************************************************/
+/**
+* Return the next BD from BdPtr in a list.
+*
+* @param  RingPtr is the DMA channel to operate on.
+* @param  BdPtr is the BD to operate on.
+*
+* @return The next BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+*    XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr,
+*                                      XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingNext(RingPtr, BdPtr)                           \
+    (((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ?                     \
+    (XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) :                              \
+    (XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation))
+
+/****************************************************************************/
+/**
+* Return the previous BD from BdPtr in the list.
+*
+* @param  RingPtr is the DMA channel to operate on.
+* @param  BdPtr is the BD to operate on
+*
+* @return The previous BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+*    XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr,
+*                                      XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingPrev(RingPtr, BdPtr)                           \
+    (((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ?                     \
+    (XEmacPs_Bd*)(RingPtr)->HighBdAddr :                              \
+    (XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Scatter gather DMA related functions in xemacps_bdring.c
+ */
+LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
+			  UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
+LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
+			 u8 Direction);
+LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			 XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			   XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			XEmacPs_Bd * BdSetPtr);
+u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+				 XEmacPs_Bd ** BdSetPtr);
+u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+				 XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* end of protection macros */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xemacps_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xemacps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..953cc6265bfbc92359b6639d5d5d833663a287af
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xemacps_hw.h
@@ -0,0 +1,656 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_hw.h
+* @addtogroup emacps_v3_1
+* @{
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
+* High-level driver functions are defined in xemacps.h.
+*
+* @note
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release.
+* 1.02a asa  11/05/12 Added hash defines for DMACR burst length configuration.
+* 1.05a kpc  28/06/13 Added XEmacPs_ResetHw function prototype
+* 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+*					  to 0x1fff. This fixes the CR#744902.
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
+* 3.0   kvn  12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
+*					  XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
+* 3.0  kpc   1/23/15  Corrected the extended descriptor macro values.
+* 3.0  kvn   02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.0  hk   03/18/15 Added support for jumbo frames.
+*                    Remove "used bit set" from TX error interrupt masks.
+* 3.1  hk   08/10/15 Update upper 32 bit tx and rx queue ptr register offsets.
+* 3.2   hk   02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XEMACPS_HW_H		/* prevent circular inclusions */
+#define XEMACPS_HW_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+#define XEMACPS_MAX_MAC_ADDR     4U   /**< Maxmum number of mac address
+                                           supported */
+#define XEMACPS_MAX_TYPE_ID      4U   /**< Maxmum number of type id supported */
+
+#ifdef __aarch64__
+#define XEMACPS_BD_ALIGNMENT     64U   /**< Minimum buffer descriptor alignment
+                                           on the local bus */
+#else
+
+#define XEMACPS_BD_ALIGNMENT     4U   /**< Minimum buffer descriptor alignment
+                                           on the local bus */
+#endif
+#define XEMACPS_RX_BUF_ALIGNMENT 4U   /**< Minimum buffer alignment when using
+                                           options that impose alignment
+                                           restrictions on the buffer data on
+                                           the local bus */
+
+/** @name Direction identifiers
+ *
+ *  These are used by several functions and callbacks that need
+ *  to specify whether an operation specifies a send or receive channel.
+ * @{
+ */
+#define XEMACPS_SEND        1U	      /**< send direction */
+#define XEMACPS_RECV        2U	      /**< receive direction */
+/*@}*/
+
+/**  @name MDC clock division
+ *  currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
+ * @{
+ */
+typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
+	MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
+} XEmacPs_MdcDiv;
+
+/*@}*/
+
+#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
+                                       bytes, 64, 128, ... 10240 */
+#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U
+
+#define XEMACPS_RX_BUF_UNIT   64U /**< Number of receive buffer bytes as a
+                                       unit, this is HW setup */
+
+#define XEMACPS_MAX_RXBD     128U /**< Size of RX buffer descriptor queues */
+#define XEMACPS_MAX_TXBD     128U /**< Size of TX buffer descriptor queues */
+
+#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */
+
+/* Register offset definitions. Unless otherwise noted, register access is
+ * 32 bit. Names are self explained here.
+ */
+
+#define XEMACPS_NWCTRL_OFFSET        0x00000000U /**< Network Control reg */
+#define XEMACPS_NWCFG_OFFSET         0x00000004U /**< Network Config reg */
+#define XEMACPS_NWSR_OFFSET          0x00000008U /**< Network Status reg */
+
+#define XEMACPS_DMACR_OFFSET         0x00000010U /**< DMA Control reg */
+#define XEMACPS_TXSR_OFFSET          0x00000014U /**< TX Status reg */
+#define XEMACPS_RXQBASE_OFFSET       0x00000018U /**< RX Q Base address reg */
+#define XEMACPS_TXQBASE_OFFSET       0x0000001CU /**< TX Q Base address reg */
+#define XEMACPS_RXSR_OFFSET          0x00000020U /**< RX Status reg */
+
+#define XEMACPS_ISR_OFFSET           0x00000024U /**< Interrupt Status reg */
+#define XEMACPS_IER_OFFSET           0x00000028U /**< Interrupt Enable reg */
+#define XEMACPS_IDR_OFFSET           0x0000002CU /**< Interrupt Disable reg */
+#define XEMACPS_IMR_OFFSET           0x00000030U /**< Interrupt Mask reg */
+
+#define XEMACPS_PHYMNTNC_OFFSET      0x00000034U /**< Phy Maintaince reg */
+#define XEMACPS_RXPAUSE_OFFSET       0x00000038U /**< RX Pause Time reg */
+#define XEMACPS_TXPAUSE_OFFSET       0x0000003CU /**< TX Pause Time reg */
+
+#define XEMACPS_JUMBOMAXLEN_OFFSET   0x00000048U /**< Jumbo max length reg */
+
+#define XEMACPS_HASHL_OFFSET         0x00000080U /**< Hash Low address reg */
+#define XEMACPS_HASHH_OFFSET         0x00000084U /**< Hash High address reg */
+
+#define XEMACPS_LADDR1L_OFFSET       0x00000088U /**< Specific1 addr low reg */
+#define XEMACPS_LADDR1H_OFFSET       0x0000008CU /**< Specific1 addr high reg */
+#define XEMACPS_LADDR2L_OFFSET       0x00000090U /**< Specific2 addr low reg */
+#define XEMACPS_LADDR2H_OFFSET       0x00000094U /**< Specific2 addr high reg */
+#define XEMACPS_LADDR3L_OFFSET       0x00000098U /**< Specific3 addr low reg */
+#define XEMACPS_LADDR3H_OFFSET       0x0000009CU /**< Specific3 addr high reg */
+#define XEMACPS_LADDR4L_OFFSET       0x000000A0U /**< Specific4 addr low reg */
+#define XEMACPS_LADDR4H_OFFSET       0x000000A4U /**< Specific4 addr high reg */
+
+#define XEMACPS_MATCH1_OFFSET        0x000000A8U /**< Type ID1 Match reg */
+#define XEMACPS_MATCH2_OFFSET        0x000000ACU /**< Type ID2 Match reg */
+#define XEMACPS_MATCH3_OFFSET        0x000000B0U /**< Type ID3 Match reg */
+#define XEMACPS_MATCH4_OFFSET        0x000000B4U /**< Type ID4 Match reg */
+
+#define XEMACPS_STRETCH_OFFSET       0x000000BCU /**< IPG Stretch reg */
+
+#define XEMACPS_OCTTXL_OFFSET        0x00000100U /**< Octects transmitted Low
+                                                      reg */
+#define XEMACPS_OCTTXH_OFFSET        0x00000104U /**< Octects transmitted High
+                                                      reg */
+
+#define XEMACPS_TXCNT_OFFSET         0x00000108U /**< Error-free Frmaes
+                                                      transmitted counter */
+#define XEMACPS_TXBCCNT_OFFSET       0x0000010CU /**< Error-free Broadcast
+                                                      Frames counter*/
+#define XEMACPS_TXMCCNT_OFFSET       0x00000110U /**< Error-free Multicast
+                                                      Frame counter */
+#define XEMACPS_TXPAUSECNT_OFFSET    0x00000114U /**< Pause Frames Transmitted
+                                                      Counter */
+#define XEMACPS_TX64CNT_OFFSET       0x00000118U /**< Error-free 64 byte Frames
+                                                      Transmitted counter */
+#define XEMACPS_TX65CNT_OFFSET       0x0000011CU /**< Error-free 65-127 byte
+                                                      Frames Transmitted
+                                                      counter */
+#define XEMACPS_TX128CNT_OFFSET      0x00000120U /**< Error-free 128-255 byte
+                                                      Frames Transmitted
+                                                      counter*/
+#define XEMACPS_TX256CNT_OFFSET      0x00000124U /**< Error-free 256-511 byte
+                                                      Frames transmitted
+                                                      counter */
+#define XEMACPS_TX512CNT_OFFSET      0x00000128U /**< Error-free 512-1023 byte
+                                                      Frames transmitted
+                                                      counter */
+#define XEMACPS_TX1024CNT_OFFSET     0x0000012CU /**< Error-free 1024-1518 byte
+                                                      Frames transmitted
+                                                      counter */
+#define XEMACPS_TX1519CNT_OFFSET     0x00000130U /**< Error-free larger than
+                                                      1519 byte Frames
+                                                      transmitted counter */
+#define XEMACPS_TXURUNCNT_OFFSET     0x00000134U /**< TX under run error
+                                                      counter */
+
+#define XEMACPS_SNGLCOLLCNT_OFFSET   0x00000138U /**< Single Collision Frame
+                                                      Counter */
+#define XEMACPS_MULTICOLLCNT_OFFSET  0x0000013CU /**< Multiple Collision Frame
+                                                      Counter */
+#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame
+                                                      Counter */
+#define XEMACPS_LATECOLLCNT_OFFSET   0x00000144U /**< Late Collision Frame
+                                                      Counter */
+#define XEMACPS_TXDEFERCNT_OFFSET    0x00000148U /**< Deferred Transmission
+                                                      Frame Counter */
+#define XEMACPS_TXCSENSECNT_OFFSET   0x0000014CU /**< Transmit Carrier Sense
+                                                      Error Counter */
+
+#define XEMACPS_OCTRXL_OFFSET        0x00000150U /**< Octects Received register
+                                                      Low */
+#define XEMACPS_OCTRXH_OFFSET        0x00000154U /**< Octects Received register
+                                                      High */
+
+#define XEMACPS_RXCNT_OFFSET         0x00000158U /**< Error-free Frames
+                                                      Received Counter */
+#define XEMACPS_RXBROADCNT_OFFSET    0x0000015CU /**< Error-free Broadcast
+                                                      Frames Received Counter */
+#define XEMACPS_RXMULTICNT_OFFSET    0x00000160U /**< Error-free Multicast
+                                                      Frames Received Counter */
+#define XEMACPS_RXPAUSECNT_OFFSET    0x00000164U /**< Pause Frames
+                                                      Received Counter */
+#define XEMACPS_RX64CNT_OFFSET       0x00000168U /**< Error-free 64 byte Frames
+                                                      Received Counter */
+#define XEMACPS_RX65CNT_OFFSET       0x0000016CU /**< Error-free 65-127 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX128CNT_OFFSET      0x00000170U /**< Error-free 128-255 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX256CNT_OFFSET      0x00000174U /**< Error-free 256-512 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX512CNT_OFFSET      0x00000178U /**< Error-free 512-1023 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX1024CNT_OFFSET     0x0000017CU /**< Error-free 1024-1518 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX1519CNT_OFFSET     0x00000180U /**< Error-free 1519-max byte
+                                                      Frames Received Counter */
+#define XEMACPS_RXUNDRCNT_OFFSET     0x00000184U /**< Undersize Frames Received
+                                                      Counter */
+#define XEMACPS_RXOVRCNT_OFFSET      0x00000188U /**< Oversize Frames Received
+                                                      Counter */
+#define XEMACPS_RXJABCNT_OFFSET      0x0000018CU /**< Jabbers Received
+                                                      Counter */
+#define XEMACPS_RXFCSCNT_OFFSET      0x00000190U /**< Frame Check Sequence
+                                                      Error Counter */
+#define XEMACPS_RXLENGTHCNT_OFFSET   0x00000194U /**< Length Field Error
+                                                      Counter */
+#define XEMACPS_RXSYMBCNT_OFFSET     0x00000198U /**< Symbol Error Counter */
+#define XEMACPS_RXALIGNCNT_OFFSET    0x0000019CU /**< Alignment Error Counter */
+#define XEMACPS_RXRESERRCNT_OFFSET   0x000001A0U /**< Receive Resource Error
+                                                      Counter */
+#define XEMACPS_RXORCNT_OFFSET       0x000001A4U /**< Receive Overrun Counter */
+#define XEMACPS_RXIPCCNT_OFFSET      0x000001A8U /**< IP header Checksum Error
+                                                      Counter */
+#define XEMACPS_RXTCPCCNT_OFFSET     0x000001ACU /**< TCP Checksum Error
+                                                      Counter */
+#define XEMACPS_RXUDPCCNT_OFFSET     0x000001B0U /**< UDP Checksum Error
+                                                      Counter */
+#define XEMACPS_LAST_OFFSET          0x000001B4U /**< Last statistic counter
+						      offset, for clearing */
+
+#define XEMACPS_1588_SEC_OFFSET      0x000001D0U /**< 1588 second counter */
+#define XEMACPS_1588_NANOSEC_OFFSET  0x000001D4U /**< 1588 nanosecond counter */
+#define XEMACPS_1588_ADJ_OFFSET      0x000001D8U /**< 1588 nanosecond
+						      adjustment counter */
+#define XEMACPS_1588_INC_OFFSET      0x000001DCU /**< 1588 nanosecond
+						      increment counter */
+#define XEMACPS_PTP_TXSEC_OFFSET     0x000001E0U /**< 1588 PTP transmit second
+						      counter */
+#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
+						      nanosecond counter */
+#define XEMACPS_PTP_RXSEC_OFFSET     0x000001E8U /**< 1588 PTP receive second
+						      counter */
+#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
+						      nanosecond counter */
+#define XEMACPS_PTPP_TXSEC_OFFSET    0x000001F0U /**< 1588 PTP peer transmit
+						      second counter */
+#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
+						      nanosecond counter */
+#define XEMACPS_PTPP_RXSEC_OFFSET    0x000001F8U /**< 1588 PTP peer receive
+						      second counter */
+#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
+						      nanosecond counter */
+
+#define XEMACPS_INTQ1_STS_OFFSET     0x00000400U /**< Interrupt Q1 Status
+							reg */
+#define XEMACPS_TXQ1BASE_OFFSET	     0x00000440U /**< TX Q1 Base address
+							reg */
+#define XEMACPS_RXQ1BASE_OFFSET	     0x00000480U /**< RX Q1 Base address
+							reg */
+#define XEMACPS_MSBBUF_TXQBASE_OFFSET  0x000004C8U /**< MSB Buffer TX Q Base
+							reg */
+#define XEMACPS_MSBBUF_RXQBASE_OFFSET  0x000004D4U /**< MSB Buffer RX Q Base
+							reg */
+#define XEMACPS_INTQ1_IER_OFFSET     0x00000600U /**< Interrupt Q1 Enable
+							reg */
+#define XEMACPS_INTQ1_IDR_OFFSET     0x00000620U /**< Interrupt Q1 Disable
+							reg */
+#define XEMACPS_INTQ1_IMR_OFFSET     0x00000640U /**< Interrupt Q1 Mask
+							reg */
+
+/* Define some bit positions for registers. */
+
+/** @name network control register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK	0x00040000U /**< Flush a packet from
+							Rx SRAM */
+#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
+                                                         pause frame */
+#define XEMACPS_NWCTRL_PAUSETX_MASK     0x00000800U /**< Transmit pause frame */
+#define XEMACPS_NWCTRL_HALTTX_MASK      0x00000400U /**< Halt transmission
+                                                         after current frame */
+#define XEMACPS_NWCTRL_STARTTX_MASK     0x00000200U /**< Start tx (tx_go) */
+
+#define XEMACPS_NWCTRL_STATWEN_MASK     0x00000080U /**< Enable writing to
+                                                         stat counters */
+#define XEMACPS_NWCTRL_STATINC_MASK     0x00000040U /**< Increment statistic
+                                                         registers */
+#define XEMACPS_NWCTRL_STATCLR_MASK     0x00000020U /**< Clear statistic
+                                                         registers */
+#define XEMACPS_NWCTRL_MDEN_MASK        0x00000010U /**< Enable MDIO port */
+#define XEMACPS_NWCTRL_TXEN_MASK        0x00000008U /**< Enable transmit */
+#define XEMACPS_NWCTRL_RXEN_MASK        0x00000004U /**< Enable receive */
+#define XEMACPS_NWCTRL_LOOPEN_MASK      0x00000002U /**< local loopback */
+/*@}*/
+
+/** @name network configuration register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of
+                                                        non-standard preamble */
+#define XEMACPS_NWCFG_IPDSTRETCH_MASK  0x10000000U /**< enable transmit IPG */
+#define XEMACPS_NWCFG_SGMIIEN_MASK     0x08000000U /**< SGMII Enable */
+#define XEMACPS_NWCFG_FCSIGNORE_MASK   0x04000000U /**< disable rejection of
+                                                        FCS error */
+#define XEMACPS_NWCFG_HDRXEN_MASK      0x02000000U /**< RX half duplex */
+#define XEMACPS_NWCFG_RXCHKSUMEN_MASK  0x01000000U /**< enable RX checksum
+                                                        offload */
+#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
+                                                        Frames to memory */
+#define XEMACPS_NWCFG_DWIDTH_64_MASK   0x00200000U /**< 64 bit Data bus width */
+#define XEMACPS_NWCFG_MDC_SHIFT_MASK   18U	   /**< shift bits for MDC */
+#define XEMACPS_NWCFG_MDCCLKDIV_MASK   0x001C0000U /**< MDC Mask PCLK divisor */
+#define XEMACPS_NWCFG_FCSREM_MASK      0x00020000U /**< Discard FCS from
+                                                        received frames */
+#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
+/**< RX length error discard */
+#define XEMACPS_NWCFG_RXOFFS_MASK      0x0000C000U /**< RX buffer offset */
+#define XEMACPS_NWCFG_PAUSEEN_MASK     0x00002000U /**< Enable pause RX */
+#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
+#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
+/**< External address match enable */
+#define XEMACPS_NWCFG_PCSSEL_MASK      0x00000800U /**< PCS Select */
+#define XEMACPS_NWCFG_1000_MASK        0x00000400U /**< 1000 Mbps */
+#define XEMACPS_NWCFG_1536RXEN_MASK    0x00000100U /**< Enable 1536 byte
+                                                        frames reception */
+#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash
+                                                        frames */
+#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash
+                                                        frames */
+#define XEMACPS_NWCFG_BCASTDI_MASK     0x00000020U /**< Do not receive
+                                                        broadcast frames */
+#define XEMACPS_NWCFG_COPYALLEN_MASK   0x00000010U /**< Copy all frames */
+#define XEMACPS_NWCFG_JUMBO_MASK       0x00000008U /**< Jumbo frames */
+#define XEMACPS_NWCFG_NVLANDISC_MASK   0x00000004U /**< Receive only VLAN
+                                                        frames */
+#define XEMACPS_NWCFG_FDEN_MASK        0x00000002U/**< full duplex */
+#define XEMACPS_NWCFG_100_MASK         0x00000001U /**< 100 Mbps */
+#define XEMACPS_NWCFG_RESET_MASK       0x00080000U/**< reset value */
+/*@}*/
+
+/** @name network status register bit definitaions
+ * @{
+ */
+#define XEMACPS_NWSR_MDIOIDLE_MASK     0x00000004U /**< PHY management idle */
+#define XEMACPS_NWSR_MDIO_MASK         0x00000002U /**< Status of mdio_in */
+/*@}*/
+
+
+/** @name MAC address register word 1 mask
+ * @{
+ */
+#define XEMACPS_LADDR_MACH_MASK        0x0000FFFFU /**< Address bits[47:32]
+                                                      bit[31:0] are in BOTTOM */
+/*@}*/
+
+
+/** @name DMA control register bit definitions
+ * @{
+ */
+#define XEMACPS_DMACR_ADDR_WIDTH_64		0x40000000U /**< 64 bit address bus */
+#define XEMACPS_DMACR_TXEXTEND_MASK		0x20000000U /**< Tx Extended desc mode */
+#define XEMACPS_DMACR_RXEXTEND_MASK		0x10000000U /**< Rx Extended desc mode */
+#define XEMACPS_DMACR_RXBUF_MASK		0x00FF0000U /**< Mask bit for RX buffer
+													size */
+#define XEMACPS_DMACR_RXBUF_SHIFT 		16U	/**< Shift bit for RX buffer
+												size */
+#define XEMACPS_DMACR_TCPCKSUM_MASK		0x00000800U /**< enable/disable TX
+													    checksum offload */
+#define XEMACPS_DMACR_TXSIZE_MASK		0x00000400U /**< TX buffer memory size */
+#define XEMACPS_DMACR_RXSIZE_MASK		0x00000300U /**< RX buffer memory size */
+#define XEMACPS_DMACR_ENDIAN_MASK		0x00000080U /**< endian configuration */
+#define XEMACPS_DMACR_BLENGTH_MASK		0x0000001FU /**< buffer burst length */
+#define XEMACPS_DMACR_SINGLE_AHB_BURST	0x00000001U /**< single AHB bursts */
+#define XEMACPS_DMACR_INCR4_AHB_BURST	0x00000004U /**< 4 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR8_AHB_BURST	0x00000008U /**< 8 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR16_AHB_BURST	0x00000010U /**< 16 bytes AHB bursts */
+/*@}*/
+
+/** @name transmit status register bit definitions
+ * @{
+ */
+#define XEMACPS_TXSR_HRESPNOK_MASK    0x00000100U /**< Transmit hresp not OK */
+#define XEMACPS_TXSR_URUN_MASK        0x00000040U /**< Transmit underrun */
+#define XEMACPS_TXSR_TXCOMPL_MASK     0x00000020U /**< Transmit completed OK */
+#define XEMACPS_TXSR_BUFEXH_MASK      0x00000010U /**< Transmit buffs exhausted
+                                                       mid frame */
+#define XEMACPS_TXSR_TXGO_MASK        0x00000008U /**< Status of go flag */
+#define XEMACPS_TXSR_RXOVR_MASK       0x00000004U /**< Retry limit exceeded */
+#define XEMACPS_TXSR_FRAMERX_MASK     0x00000002U /**< Collision tx frame */
+#define XEMACPS_TXSR_USEDREAD_MASK    0x00000001U /**< TX buffer used bit set */
+
+#define XEMACPS_TXSR_ERROR_MASK      ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \
+                                       (u32)XEMACPS_TXSR_URUN_MASK | \
+                                       (u32)XEMACPS_TXSR_BUFEXH_MASK | \
+                                       (u32)XEMACPS_TXSR_RXOVR_MASK | \
+                                       (u32)XEMACPS_TXSR_FRAMERX_MASK | \
+                                       (u32)XEMACPS_TXSR_USEDREAD_MASK)
+/*@}*/
+
+/**
+ * @name receive status register bit definitions
+ * @{
+ */
+#define XEMACPS_RXSR_HRESPNOK_MASK    0x00000008U /**< Receive hresp not OK */
+#define XEMACPS_RXSR_RXOVR_MASK       0x00000004U /**< Receive overrun */
+#define XEMACPS_RXSR_FRAMERX_MASK     0x00000002U /**< Frame received OK */
+#define XEMACPS_RXSR_BUFFNA_MASK      0x00000001U /**< RX buffer used bit set */
+
+#define XEMACPS_RXSR_ERROR_MASK      ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \
+                                       (u32)XEMACPS_RXSR_RXOVR_MASK | \
+                                       (u32)XEMACPS_RXSR_BUFFNA_MASK)
+/*@}*/
+
+/**
+ * @name Interrupt Q1 status register bit definitions
+ * @{
+ */
+#define XEMACPS_INTQ1SR_TXCOMPL_MASK	0x00000080U /**< Transmit completed OK */
+#define XEMACPS_INTQ1SR_TXERR_MASK	0x00000040U /**< Transmit AMBA Error */
+
+#define XEMACPS_INTQ1_IXR_ALL_MASK	((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
+					 (u32)XEMACPS_INTQ1SR_TXERR_MASK)
+
+/*@}*/
+
+/**
+ * @name interrupts bit definitions
+ * Bits definitions are same in XEMACPS_ISR_OFFSET,
+ * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
+ * @{
+ */
+#define XEMACPS_IXR_PTPPSTX_MASK    0x02000000U /**< PTP Psync transmitted */
+#define XEMACPS_IXR_PTPPDRTX_MASK   0x01000000U /**< PTP Pdelay_req
+						     transmitted */
+#define XEMACPS_IXR_PTPSTX_MASK     0x00800000U /**< PTP Sync transmitted */
+#define XEMACPS_IXR_PTPDRTX_MASK    0x00400000U /**< PTP Delay_req transmitted
+						*/
+#define XEMACPS_IXR_PTPPSRX_MASK    0x00200000U /**< PTP Psync received */
+#define XEMACPS_IXR_PTPPDRRX_MASK   0x00100000U /**< PTP Pdelay_req received */
+#define XEMACPS_IXR_PTPSRX_MASK     0x00080000U /**< PTP Sync received */
+#define XEMACPS_IXR_PTPDRRX_MASK    0x00040000U /**< PTP Delay_req received */
+#define XEMACPS_IXR_PAUSETX_MASK    0x00004000U	/**< Pause frame transmitted */
+#define XEMACPS_IXR_PAUSEZERO_MASK  0x00002000U	/**< Pause time has reached
+                                                     zero */
+#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U	/**< Pause frame received */
+#define XEMACPS_IXR_HRESPNOK_MASK   0x00000800U	/**< hresp not ok */
+#define XEMACPS_IXR_RXOVR_MASK      0x00000400U	/**< Receive overrun occurred */
+#define XEMACPS_IXR_TXCOMPL_MASK    0x00000080U	/**< Frame transmitted ok */
+#define XEMACPS_IXR_TXEXH_MASK      0x00000040U	/**< Transmit err occurred or
+                                                     no buffers*/
+#define XEMACPS_IXR_RETRY_MASK      0x00000020U	/**< Retry limit exceeded */
+#define XEMACPS_IXR_URUN_MASK       0x00000010U	/**< Transmit underrun */
+#define XEMACPS_IXR_TXUSED_MASK     0x00000008U	/**< Tx buffer used bit read */
+#define XEMACPS_IXR_RXUSED_MASK     0x00000004U	/**< Rx buffer used bit read */
+#define XEMACPS_IXR_FRAMERX_MASK    0x00000002U	/**< Frame received ok */
+#define XEMACPS_IXR_MGMNT_MASK      0x00000001U	/**< PHY management complete */
+#define XEMACPS_IXR_ALL_MASK        0x00007FFFU	/**< Everything! */
+
+#define XEMACPS_IXR_TX_ERR_MASK    ((u32)XEMACPS_IXR_TXEXH_MASK |         \
+                                     (u32)XEMACPS_IXR_RETRY_MASK |         \
+                                     (u32)XEMACPS_IXR_URUN_MASK)
+
+
+#define XEMACPS_IXR_RX_ERR_MASK    ((u32)XEMACPS_IXR_HRESPNOK_MASK |      \
+                                     (u32)XEMACPS_IXR_RXUSED_MASK |        \
+                                     (u32)XEMACPS_IXR_RXOVR_MASK)
+
+/*@}*/
+
+/** @name PHY Maintenance bit definitions
+ * @{
+ */
+#define XEMACPS_PHYMNTNC_OP_MASK    0x40020000U	/**< operation mask bits */
+#define XEMACPS_PHYMNTNC_OP_R_MASK  0x20000000U	/**< read operation */
+#define XEMACPS_PHYMNTNC_OP_W_MASK  0x10000000U	/**< write operation */
+#define XEMACPS_PHYMNTNC_ADDR_MASK  0x0F800000U	/**< Address bits */
+#define XEMACPS_PHYMNTNC_REG_MASK   0x007C0000U	/**< register bits */
+#define XEMACPS_PHYMNTNC_DATA_MASK  0x00000FFFU	/**< data bits */
+#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK   23U	/**< Shift bits for PHYAD */
+#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK   18U	/**< Shift bits for PHREG */
+/*@}*/
+
+/* Transmit buffer descriptor status words offset
+ * @{
+ */
+#define XEMACPS_BD_ADDR_OFFSET  0x00000000U /**< word 0/addr of BDs */
+#define XEMACPS_BD_STAT_OFFSET  0x00000004U /**< word 1/status of BDs */
+#define XEMACPS_BD_ADDR_HI_OFFSET  0x00000008U /**< word 2/addr of BDs */
+
+/*
+ * @}
+ */
+
+/* Transmit buffer descriptor status words bit positions.
+ * Transmit buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit address pointing to the location of
+ * the transmit data.
+ * The following register - word1, consists of various information to control
+ * the XEmacPs transmit process.  After transmit, this is updated with status
+ * information, whether the frame was transmitted OK or why it had failed.
+ * @{
+ */
+#define XEMACPS_TXBUF_USED_MASK  0x80000000U /**< Used bit. */
+#define XEMACPS_TXBUF_WRAP_MASK  0x40000000U /**< Wrap bit, last descriptor */
+#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
+#define XEMACPS_TXBUF_URUN_MASK  0x10000000U /**< Transmit underrun occurred */
+#define XEMACPS_TXBUF_EXH_MASK   0x08000000U /**< Buffers exhausted */
+#define XEMACPS_TXBUF_TCP_MASK   0x04000000U /**< Late collision. */
+#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
+#define XEMACPS_TXBUF_LAST_MASK  0x00008000U /**< Last buffer */
+#define XEMACPS_TXBUF_LEN_MASK   0x00003FFFU /**< Mask for length field */
+/*
+ * @}
+ */
+
+/* Receive buffer descriptor status words bit positions.
+ * Receive buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit word aligned address pointing to the
+ * address of the buffer. The lower two bits make up the wrap bit indicating
+ * the last descriptor and the ownership bit to indicate it has been used by
+ * the XEmacPs.
+ * The following register - word1, contains status information regarding why
+ * the frame was received (the filter match condition) as well as other
+ * useful info.
+ * @{
+ */
+#define XEMACPS_RXBUF_BCAST_MASK     0x80000000U /**< Broadcast frame */
+#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
+#define XEMACPS_RXBUF_UNIHASH_MASK   0x20000000U /**< Unicast hashed frame */
+#define XEMACPS_RXBUF_EXH_MASK       0x08000000U /**< buffer exhausted */
+#define XEMACPS_RXBUF_AMATCH_MASK    0x06000000U /**< Specific address
+                                                      matched */
+#define XEMACPS_RXBUF_IDFOUND_MASK   0x01000000U /**< Type ID matched */
+#define XEMACPS_RXBUF_IDMATCH_MASK   0x00C00000U /**< ID matched mask */
+#define XEMACPS_RXBUF_VLAN_MASK      0x00200000U /**< VLAN tagged */
+#define XEMACPS_RXBUF_PRI_MASK       0x00100000U /**< Priority tagged */
+#define XEMACPS_RXBUF_VPRI_MASK      0x000E0000U /**< Vlan priority */
+#define XEMACPS_RXBUF_CFI_MASK       0x00010000U /**< CFI frame */
+#define XEMACPS_RXBUF_EOF_MASK       0x00008000U /**< End of frame. */
+#define XEMACPS_RXBUF_SOF_MASK       0x00004000U /**< Start of frame. */
+#define XEMACPS_RXBUF_LEN_MASK       0x00001FFFU /**< Mask for length field */
+#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */
+
+#define XEMACPS_RXBUF_WRAP_MASK      0x00000002U /**< Wrap bit, last BD */
+#define XEMACPS_RXBUF_NEW_MASK       0x00000001U /**< Used bit.. */
+#define XEMACPS_RXBUF_ADD_MASK       0xFFFFFFFCU /**< Mask for address */
+/*
+ * @}
+ */
+
+/*
+ * Define appropriate I/O access method to memory mapped I/O or other
+ * interface if necessary.
+ */
+
+#define XEmacPs_In32  Xil_In32
+#define XEmacPs_Out32 Xil_Out32
+
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param    BaseAddress is the base address of the device
+* @param    RegOffset is the register offset to be read
+*
+* @return   The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
+    XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param    BaseAddress is the base address of the device
+* @param    RegOffset is the register offset to be written
+* @param    Data is the 32-bit value to write to the register
+*
+* @return   None.
+*
+* @note
+* C-style signature:
+*    void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
+*         u32 Data)
+*
+*****************************************************************************/
+#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
+    XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes *****************************/
+/*
+ * Perform reset operation to the emacps interface
+ */
+void XEmacPs_ResetHw(u32 BaseAddr);
+
+#ifdef __cplusplus
+  }
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xenv.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xenv.h
new file mode 100644
index 0000000000000000000000000000000000000000..3d97bebd450eda76d8221c8a9b012bb723c9b6ca
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xenv.h
@@ -0,0 +1,187 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv.h
+*
+* Defines common services that are typically found in a host operating.
+* environment. This include file simply includes an OS specific file based
+* on the compile-time constant BUILD_ENV_*, where * is the name of the target
+* environment.
+*
+* All services are defined as macros.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b ch   10/24/02 Added XENV_LINUX
+* 1.00a rmm  04/17/02 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XENV_H /* prevent circular inclusions */
+#define XENV_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Select which target environment we are operating under
+ */
+
+/* VxWorks target environment */
+#if defined XENV_VXWORKS
+#include "xenv_vxworks.h"
+
+/* Linux target environment */
+#elif defined XENV_LINUX
+#include "xenv_linux.h"
+
+/* Unit test environment */
+#elif defined XENV_UNITTEST
+#include "ut_xenv.h"
+
+/* Integration test environment */
+#elif defined XENV_INTTEST
+#include "int_xenv.h"
+
+/* Standalone environment selected */
+#else
+#include "xenv_standalone.h"
+#endif
+
+
+/*
+ * The following comments specify the types and macro wrappers that are
+ * expected to be defined by the target specific header files
+ */
+
+/**************************** Type Definitions *******************************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP
+ *
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param   DestPtr is the destination address to copy data to.
+ * @param   SrcPtr is the source address to copy data from.
+ * @param   Bytes is the number of bytes to copy.
+ *
+ * @return  None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param   DestPtr is the destination address to set.
+ * @param   Data contains the value to set.
+ * @param   Bytes is the number of bytes to set.
+ *
+ * @return  None
+ */
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ *
+ * Samples the processor's or external timer's time base counter.
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param   Stamp1Ptr - First sampled time stamp.
+ * @param   Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return  An unsigned int value with units of microseconds.
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param   Stamp1Ptr - First sampled time stamp.
+ * @param   Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return  An unsigned int value with units of milliseconds.
+ */
+
+/*****************************************************************************//**
+ *
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds.
+ *
+ * @param   delay is the number of microseconds to delay.
+ *
+ * @return  None
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xenv_standalone.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xenv_standalone.h
new file mode 100644
index 0000000000000000000000000000000000000000..f18601874bb5b8a84f10954730b4aca1bc988598
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xenv_standalone.h
@@ -0,0 +1,368 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv_standalone.h
+*
+* Defines common services specified by xenv.h.
+*
+* @note
+* 	This file is not intended to be included directly by driver code.
+* 	Instead, the generic xenv.h file is intended to be included by driver
+* 	code.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr  02/28/07 Added cache handling macros.
+* 1.00a wgr  02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a rmm  01/24/06 Implemented XENV_USLEEP. Assume implementation is being
+*                     used under Xilinx standalone BSP.
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* 1.00a rmm  03/21/02 First release
+* 1.00a wgr  03/22/07 Converted to new coding style.
+* 1.00a rpm  06/29/07 Added udelay macro for standalone
+* 1.00a xd   07/19/07 Included xparameters.h as XPAR_ constants are referred
+*                     to in MICROBLAZE section
+* 1.00a ecm  09/19/08 updated for v7.20 of Microblaze, new functionality
+*
+* </pre>
+*
+*
+******************************************************************************/
+
+#ifndef XENV_STANDALONE_H
+#define XENV_STANDALONE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+/******************************************************************************
+ *
+ * Get the processor dependent includes
+ *
+ ******************************************************************************/
+
+#include <string.h>
+
+#if defined __MICROBLAZE__
+#  include "mb_interface.h"
+#  include "xparameters.h"   /* XPAR constants used below in MB section */
+
+#elif defined __PPC__
+#  include "sleep.h"
+#  include "xcache_l.h"      /* also include xcache_l.h for caching macros */
+#endif
+
+/******************************************************************************
+ *
+ * MEMCPY / MEMSET related macros.
+ *
+ * The following are straight forward implementations of memset and memcpy.
+ *
+ * NOTE: memcpy may not work if source and target memory area are overlapping.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	SrcPtr
+ * 		Source address to copy data from.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note
+ * 		The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
+ *
+ * @note
+ * 		This implemention MAY BREAK work if source and target memory
+ * 		area are overlapping.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
+	memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
+
+
+
+/*****************************************************************************/
+/**
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	Data
+ * 		Value to set.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note
+ * 		The use of XENV_MEM_FILL is deprecated. Use memset() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
+	memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
+
+
+
+/******************************************************************************
+ *
+ * TIME related macros
+ *
+ ******************************************************************************/
+
+/**
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+typedef s32 XENV_TIME_STAMP;
+
+/*****************************************************************************/
+/**
+ *
+ * Time is derived from the 64 bit PPC timebase register
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None.
+ *
+ * @note
+ *
+ * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ * <br><br>
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_GET(StampPtr)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds. Not implemented without OS
+ * support.
+ *
+ * @param	delay
+ * 		Number of microseconds to delay.
+ *
+ * @return	None.
+ *
+ *****************************************************************************/
+
+#ifdef __PPC__
+#define XENV_USLEEP(delay)	usleep(delay)
+#define udelay(delay)	usleep(delay)
+#else
+#define XENV_USLEEP(delay)
+#define udelay(delay)
+#endif
+
+
+/******************************************************************************
+ *
+ * CACHE handling macros / mappings
+ *
+ ******************************************************************************/
+/******************************************************************************
+ *
+ * Processor independent macros
+ *
+ ******************************************************************************/
+
+#define XCACHE_ENABLE_CACHE()	\
+		{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
+
+#define XCACHE_DISABLE_CACHE()	\
+		{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
+
+
+/******************************************************************************
+ *
+ * MicroBlaze case
+ *
+ * NOTE: Currently the following macros will only work on systems that contain
+ * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
+ * system is built using a xparameters.h file.
+ *
+ ******************************************************************************/
+
+#if defined __MICROBLAZE__
+
+/* Check if MicroBlaze data cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
+#  define XCACHE_ENABLE_DCACHE()		microblaze_enable_dcache()
+#  define XCACHE_DISABLE_DCACHE()		microblaze_disable_dcache()
+#  define XCACHE_INVALIDATE_DCACHE()  	microblaze_invalidate_dcache()
+
+#  define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+
+#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
+#  define XCACHE_FLUSH_DCACHE()  		microblaze_flush_dcache()
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+			microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
+#else
+#  define XCACHE_FLUSH_DCACHE()  		microblaze_invalidate_dcache()
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+#endif	/*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
+
+#else
+#  define XCACHE_ENABLE_DCACHE()
+#  define XCACHE_DISABLE_DCACHE()
+#  define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
+#endif	/*XPAR_MICROBLAZE_USE_DCACHE*/
+
+
+/* Check if MicroBlaze instruction cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
+#  define XCACHE_ENABLE_ICACHE()		microblaze_enable_icache()
+#  define XCACHE_DISABLE_ICACHE()		microblaze_disable_icache()
+
+#  define XCACHE_INVALIDATE_ICACHE()  	microblaze_invalidate_icache()
+
+#  define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
+
+#else
+#  define XCACHE_ENABLE_ICACHE()
+#  define XCACHE_DISABLE_ICACHE()
+#endif	/*XPAR_MICROBLAZE_USE_ICACHE*/
+
+
+/******************************************************************************
+ *
+ * PowerPC case
+ *
+ *   Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
+ *   specific memory region (0x80000001). Each bit (0-30) in the regions
+ *   bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
+ *   range.
+ *
+ *   regions    --> cached address range
+ *   ------------|--------------------------------------------------
+ *   0x80000000  | [0, 0x7FFFFFF]
+ *   0x00000001  | [0xF8000000, 0xFFFFFFFF]
+ *   0x80000001  | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
+ *
+ ******************************************************************************/
+
+#elif defined __PPC__
+
+#define XCACHE_ENABLE_DCACHE()		XCache_EnableDCache(0x80000001)
+#define XCACHE_DISABLE_DCACHE()		XCache_DisableDCache()
+#define XCACHE_ENABLE_ICACHE()		XCache_EnableICache(0x80000001)
+#define XCACHE_DISABLE_ICACHE()		XCache_DisableICache()
+
+#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+		XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+		XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_INVALIDATE_ICACHE()	XCache_InvalidateICache()
+
+
+/******************************************************************************
+ *
+ * Unknown processor / architecture
+ *
+ ******************************************************************************/
+
+#else
+/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* #ifndef XENV_STANDALONE_H */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xgpio.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xgpio.h
new file mode 100644
index 0000000000000000000000000000000000000000..fc3f0bd338a05a0c1a5f72e2026125187cddfc3c
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xgpio.h
@@ -0,0 +1,214 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xgpio.h
+* @addtogroup gpio_v4_2
+* @{
+* @details
+*
+* This file contains the software API definition of the Xilinx General Purpose
+* I/O (XGpio) device driver.
+*
+* The Xilinx GPIO controller is a soft IP core designed for Xilinx FPGAs and
+* contains the following general features:
+*   - Support for up to 32 I/O discretes for each channel (64 bits total).
+*   - Each of the discretes can be configured for input or output.
+*   - Configurable support for dual channels and interrupt generation.
+*
+* The driver provides interrupt management functions. Implementation of
+* interrupt handlers is left to the user. Refer to the provided interrupt
+* example in the examples directory for details.
+*
+* This driver is intended to be RTOS and processor independent. Any needs for
+* dynamic memory management, threads or thread mutual exclusion, virtual
+* memory, or cache control must be satisfied by the layer above this driver.
+*
+* <b>Initialization & Configuration</b>
+*
+* The XGpio_Config structure is used by the driver to configure itself. This
+* configuration structure is typically created by the tool-chain based on HW
+* build properties.
+*
+* To support multiple runtime loading and initialization strategies employed
+* by various operating systems, the driver instance can be initialized in one
+* of the following ways:
+*
+*   - XGpio_Initialize(InstancePtr, DeviceId) - The driver looks up its own
+*     configuration structure created by the tool-chain based on an ID provided
+*     by the tool-chain.
+*
+*   - XGpio_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+*     configuration structure provided by the caller. If running in a system
+*     with address translation, the provided virtual memory base address
+*     replaces the physical address present in the configuration structure.
+*
+* @note
+*
+* This API utilizes 32 bit I/O to the GPIO registers. With less than 32 bits,
+* the unused bits from registers are read as zero and written as don't cares.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a rmm  03/13/02 First release
+* 2.00a jhl  11/26/03 Added support for dual channels and interrupts
+* 2.01a jvb  12/14/05 I separated dependency on the static config table and
+*                     xparameters.h from the driver initialization by moving
+*                     _Initialize and _LookupConfig to _sinit.c. I also added
+*                     the new _CfgInitialize routine.
+* 2.11a mta  03/21/07 Updated to new coding style, added GetDataDirection
+* 2.12a sv   11/21/07 Updated driver to support access through DCR bus
+* 2.12a sv   06/05/08 Updated driver to fix the XGpio_InterruptDisable function
+*		      to properly update the Interrupt Enable register
+* 2.13a sdm  08/22/08 Removed support for static interrupt handlers from the MDD
+*		      file
+* 3.00a sv   11/21/09 Updated to use HAL Processor APIs.
+*		      Renamed the macros XGpio_mWriteReg to XGpio_WriteReg and
+*		      XGpio_mReadReg to XGpio_ReadReg. Removed the macros
+*		      XGpio_mSetDataDirection, XGpio_mGetDataReg and
+*		      XGpio_mSetDataReg. Users should use XGpio_WriteReg and
+*		      XGpio_ReadReg to achieve the same functionality.
+* 3.01a bss  04/18/13 Updated driver tcl to generate Canonical params in
+*		      xparameters.h. CR#698589
+* 4.0   adk  19/12/13 Updated as per the New Tcl API's
+* 4.1   lks  11/18/15 Updated to use cannonical xparameters in examples and
+*		      clean up of the comments, removed support for DCR bridge
+*		      and removed xgpio_intr_example for CR 900381
+* 4.2   sk   08/16/16 Used UINTPTR instead of u32 for Baseaddress as part of
+*                     adding 64 bit support. CR# 867425.
+*                     Changed the prototype of XGpio_CfgInitialize API.
+* 4.3   sk   09/29/16 Modified the example to make it work when LED_bits are
+*                     configured as an output. CR# 958644
+*       ms   01/23/17 Added xil_printf statement in main function for all
+*                     examples to ensure that "Successfully ran" and "Failed"
+*                     strings are available in all examples. This is a fix
+*                     for CR-965028.
+*       ms   03/17/17 Added readme.txt file in examples folder for doxygen
+*                     generation.
+*
+* </pre>
+*****************************************************************************/
+
+#ifndef XGPIO_H			/* prevent circular inclusions */
+#define XGPIO_H			/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xgpio_l.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;		/* Unique ID  of device */
+	UINTPTR BaseAddress;	/* Device base address */
+	int InterruptPresent;	/* Are interrupts supported in h/w */
+	int IsDual;		/* Are 2 channels supported in h/w */
+} XGpio_Config;
+
+/**
+ * The XGpio driver instance data. The user is required to allocate a
+ * variable of this type for every GPIO device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	UINTPTR BaseAddress;	/* Device base address */
+	u32 IsReady;		/* Device is initialized and ready */
+	int InterruptPresent;	/* Are interrupts supported in h/w */
+	int IsDual;		/* Are 2 channels supported in h/w */
+} XGpio;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+/*
+ * Initialization functions in xgpio_sinit.c
+ */
+int XGpio_Initialize(XGpio *InstancePtr, u16 DeviceId);
+XGpio_Config *XGpio_LookupConfig(u16 DeviceId);
+
+/*
+ * API Basic functions implemented in xgpio.c
+ */
+int XGpio_CfgInitialize(XGpio *InstancePtr, XGpio_Config * Config,
+			UINTPTR EffectiveAddr);
+void XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel,
+			    u32 DirectionMask);
+u32 XGpio_GetDataDirection(XGpio *InstancePtr, unsigned Channel);
+u32 XGpio_DiscreteRead(XGpio *InstancePtr, unsigned Channel);
+void XGpio_DiscreteWrite(XGpio *InstancePtr, unsigned Channel, u32 Mask);
+
+
+/*
+ * API Functions implemented in xgpio_extra.c
+ */
+void XGpio_DiscreteSet(XGpio *InstancePtr, unsigned Channel, u32 Mask);
+void XGpio_DiscreteClear(XGpio *InstancePtr, unsigned Channel, u32 Mask);
+
+/*
+ * API Functions implemented in xgpio_selftest.c
+ */
+int XGpio_SelfTest(XGpio *InstancePtr);
+
+/*
+ * API Functions implemented in xgpio_intr.c
+ */
+void XGpio_InterruptGlobalEnable(XGpio *InstancePtr);
+void XGpio_InterruptGlobalDisable(XGpio *InstancePtr);
+void XGpio_InterruptEnable(XGpio *InstancePtr, u32 Mask);
+void XGpio_InterruptDisable(XGpio *InstancePtr, u32 Mask);
+void XGpio_InterruptClear(XGpio *InstancePtr, u32 Mask);
+u32 XGpio_InterruptGetEnabled(XGpio *InstancePtr);
+u32 XGpio_InterruptGetStatus(XGpio *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xgpio_l.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xgpio_l.h
new file mode 100644
index 0000000000000000000000000000000000000000..9c88aba2e7d6198a9d175eea234b472cca1a6ae6
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xgpio_l.h
@@ -0,0 +1,193 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpio_l.h
+* @addtogroup gpio_v4_2
+* @{
+*
+* This header file contains identifiers and driver functions (or
+* macros) that can be used to access the device.  The user should refer to the
+* hardware device specification for more details of the device operation.
+*
+* The macros that are available in this file use a multiply to calculate the
+* addresses of registers. The user can control whether that multiply is done
+* at run time or at compile time. A constant passed as the channel parameter
+* will cause the multiply to be done at compile time. A variable passed as the
+* channel parameter will cause it to occur at run time.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a jhl  04/24/02 First release of low level driver
+* 2.00a jhl  11/26/03 Added support for dual channels and interrupts. This
+*                     change required the functions to be changed such that
+*                     the interface is not compatible with previous versions.
+*                     See the examples in the example directory for macros
+*                     to help compile an application that was designed for
+*                     previous versions of the driver. The interrupt registers
+*                     are accessible using the ReadReg and WriteReg macros and
+*                     a channel parameter was added to the other macros.
+* 2.11a mta  03/21/07 Updated to new coding style
+* 2.12a sv   11/21/07 Updated driver to support access through DCR bus.
+* 3.00a sv   11/21/09 Renamed the macros XGpio_mWriteReg to XGpio_WriteReg
+*		      XGpio_mReadReg to XGpio_ReadReg.
+*		      Removed the macros XGpio_mSetDataDirection,
+*		      XGpio_mGetDataReg and XGpio_mSetDataReg. Users
+*		      should use XGpio_WriteReg/XGpio_ReadReg to achieve the
+*		      same functionality.
+* 4.1  lks   11/18/15 Removed support for DCR bridge
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XGPIO_L_H		/* prevent circular inclusions */
+#define XGPIO_L_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+
+/************************** Constant Definitions *****************************/
+
+/** @name Registers
+ *
+ * Register offsets for this device.
+ * @{
+ */
+#define XGPIO_DATA_OFFSET	0x0   /**< Data register for 1st channel */
+#define XGPIO_TRI_OFFSET	0x4   /**< I/O direction reg for 1st channel */
+#define XGPIO_DATA2_OFFSET	0x8   /**< Data register for 2nd channel */
+#define XGPIO_TRI2_OFFSET	0xC   /**< I/O direction reg for 2nd channel */
+
+#define XGPIO_GIE_OFFSET	0x11C /**< Glogal interrupt enable register */
+#define XGPIO_ISR_OFFSET	0x120 /**< Interrupt status register */
+#define XGPIO_IER_OFFSET	0x128 /**< Interrupt enable register */
+
+/* @} */
+
+/* The following constant describes the offset of each channels data and
+ * tristate register from the base address.
+ */
+#define XGPIO_CHAN_OFFSET  8
+
+/** @name Interrupt Status and Enable Register bitmaps and masks
+ *
+ * Bit definitions for the interrupt status register and interrupt enable
+ * registers.
+ * @{
+ */
+#define XGPIO_IR_MASK		0x3 /**< Mask of all bits */
+#define XGPIO_IR_CH1_MASK	0x1 /**< Mask for the 1st channel */
+#define XGPIO_IR_CH2_MASK	0x2 /**< Mask for the 2nd channel */
+/*@}*/
+
+
+/** @name Global Interrupt Enable Register bitmaps and masks
+ *
+ * Bit definitions for the Global Interrupt  Enable register
+ * @{
+ */
+#define XGPIO_GIE_GINTR_ENABLE_MASK	0x80000000
+/*@}*/
+
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XGpio_In32  Xil_In32
+#define XGpio_Out32 Xil_Out32
+
+
+/****************************************************************************/
+/**
+*
+* Write a value to a GPIO register. A 32 bit write is performed. If the
+* GPIO core is implemented in a smaller width, only the least significant data
+* is written.
+*
+* @param	BaseAddress is the base address of the GPIO device.
+* @param	RegOffset is the register offset from the base to write to.
+* @param	Data is the data written to the register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XGpio_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+****************************************************************************/
+#define XGpio_WriteReg(BaseAddress, RegOffset, Data) \
+	XGpio_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/****************************************************************************/
+/**
+*
+* Read a value from a GPIO register. A 32 bit read is performed. If the
+* GPIO core is implemented in a smaller width, only the least
+* significant data is read from the register. The most significant data
+* will be read as 0.
+*
+* @param	BaseAddress is the base address of the GPIO device.
+* @param	RegOffset is the register offset from the base to read from.
+*
+* @return	Data read from the register.
+*
+* @note		C-style signature:
+*		u32 XGpio_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+****************************************************************************/
+#define XGpio_ReadReg(BaseAddress, RegOffset) \
+	XGpio_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xgpiops.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xgpiops.h
new file mode 100644
index 0000000000000000000000000000000000000000..367380656282ba41858dcb558f819eb39f23fbdd
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xgpiops.h
@@ -0,0 +1,270 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops.h
+* @addtogroup gpiops_v3_1
+* @{
+* @details
+*
+* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
+* Controller.
+*
+* The GPIO Controller supports the following features:
+*	- 4 banks
+*	- Masked writes (There are no masked reads)
+*	- Bypass mode
+*	- Configurable Interrupts (Level/Edge)
+*
+* This driver is intended to be RTOS and processor independent. Any needs for
+* dynamic memory management, threads or thread mutual exclusion, virtual
+* memory, or cache control must be satisfied by the layer above this driver.
+
+* This driver supports all the features listed above, if applicable.
+*
+* <b>Driver Description</b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the GPIO.
+*
+* <b>Interrupts</b>
+*
+* The driver provides interrupt management functions and an interrupt handler.
+* Users of this driver need to provide callback functions. An interrupt handler
+* example is available with the driver.
+*
+* <b>Threads</b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* <b>Asserts</b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* <b>Building the driver</b>
+*
+* The XGpioPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+* <br><br>
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.01a sv   04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+*                     XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+*		      relevant to Zynq device.The interrupts are disabled
+*		      for output pins on all banks during initialization.
+* 1.02a hk   08/22/13 Added low level reset API
+* 2.1   hk   04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+* 2.2	sk	 10/13/14 Used Pin number in Bank instead of pin number
+* 					  passed to APIs. CR# 822636
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+*       ms   03/17/17 Added readme.txt file in examples folder for doxygen
+*                     generation.
+*
+* </pre>
+*
+******************************************************************************/
+#ifndef XGPIOPS_H		/* prevent circular inclusions */
+#define XGPIOPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xgpiops_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Interrupt types
+ *  @{
+ * The following constants define the interrupt types that can be set for each
+ * GPIO pin.
+ */
+#define XGPIOPS_IRQ_TYPE_EDGE_RISING	0x00U  /**< Interrupt on Rising edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_FALLING	0x01U  /**< Interrupt Falling edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_BOTH	0x02U  /**< Interrupt on both edges */
+#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH	0x03U  /**< Interrupt on high level */
+#define XGPIOPS_IRQ_TYPE_LEVEL_LOW	0x04U  /**< Interrupt on low level */
+/*@}*/
+
+#define XGPIOPS_BANK_MAX_PINS		(u32)32 /**< Max pins in a GPIO bank */
+#define XGPIOPS_BANK0			0x00U  /**< GPIO Bank 0 */
+#define XGPIOPS_BANK1			0x01U  /**< GPIO Bank 1 */
+#define XGPIOPS_BANK2			0x02U  /**< GPIO Bank 2 */
+#define XGPIOPS_BANK3			0x03U  /**< GPIO Bank 3 */
+
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+#define XGPIOPS_BANK4			0x04U  /**< GPIO Bank 4 */
+#define XGPIOPS_BANK5			0x05U  /**< GPIO Bank 5 */
+#endif
+
+#define XGPIOPS_MAX_BANKS_ZYNQMP		0x06U  /**< Max banks in a
+										*	Zynq Ultrascale+ MP GPIO device
+										*/
+#define XGPIOPS_MAX_BANKS		0x04U  /**< Max banks in a Zynq GPIO device */
+
+#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP	(u32)174 /**< Max pins in the
+						  *	Zynq Ultrascale+ MP GPIO device
+					      * 0 - 25,  Bank 0
+					      * 26 - 51, Bank 1
+					      *	52 - 77, Bank 2
+					      *	78 - 109, Bank 3
+					      *	110 - 141, Bank 4
+					      *	142 - 173, Bank 5
+					      */
+#define XGPIOPS_DEVICE_MAX_PIN_NUM	(u32)118 /**< Max pins in the Zynq GPIO device
+					      * 0 - 31,  Bank 0
+					      * 32 - 53, Bank 1
+					      *	54 - 85, Bank 2
+					      *	86 - 117, Bank 3
+					      */
+
+/**************************** Type Definitions *******************************/
+
+/****************************************************************************/
+/**
+ * This handler data type allows the user to define a callback function to
+ * handle the interrupts for the GPIO device. The application using this
+ * driver is expected to define a handler of this type, to support interrupt
+ * driven mode. The handler executes in an interrupt context such that minimal
+ * processing should be performed.
+ *
+ * @param	CallBackRef is a callback reference passed in by the upper layer
+ *		when setting the callback functions for a GPIO bank. It is
+ *		passed back to the upper layer when the callback is invoked. Its
+ *		type is not important to the driver component, so it is a void
+ *		pointer.
+ * @param	Bank is the bank for which the interrupt status has changed.
+ * @param	Status is the Interrupt status of the GPIO bank.
+ *
+ *****************************************************************************/
+typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID of device */
+	u32 BaseAddr;		/**< Register base address */
+} XGpioPs_Config;
+
+/**
+ * The XGpioPs driver instance data. The user is required to allocate a
+ * variable of this type for the GPIO device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XGpioPs_Config GpioConfig;	/**< Device configuration */
+	u32 IsReady;			/**< Device is initialized and ready */
+	XGpioPs_Handler Handler;	/**< Status handlers for all banks */
+	void *CallBackRef; 		/**< Callback ref for bank handlers */
+	u32 Platform;			/**< Platform data */
+	u32 MaxPinNum;			/**< Max pins in the GPIO device */
+	u8 MaxBanks;			/**< Max banks in a GPIO device */
+} XGpioPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/* Functions in xgpiops.c */
+s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
+			   u32 EffectiveAddr);
+
+/* Bank APIs in xgpiops.c */
+u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data);
+void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction);
+u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
+u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_GetBankPin(u8 PinNumber,	u8 *BankNumber, u8 *PinNumberInBank);
+
+/* Pin APIs in xgpiops.c */
+u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data);
+void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction);
+u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
+u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin);
+
+/* Diagnostic functions in xgpiops_selftest.c */
+s32 XGpioPs_SelfTest(XGpioPs *InstancePtr);
+
+/* Functions in xgpiops_intr.c */
+/* Bank APIs in xgpiops_intr.c */
+void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank);
+u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
+			  u32 IntrPolarity, u32 IntrOnAny);
+void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
+			  u32 *IntrPolarity, u32 *IntrOnAny);
+void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
+			     XGpioPs_Handler FuncPointer);
+void XGpioPs_IntrHandler(XGpioPs *InstancePtr);
+
+/* Pin APIs in xgpiops_intr.c */
+void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
+u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin);
+
+void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin);
+u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin);
+u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin);
+
+/* Functions in xgpiops_sinit.c */
+XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xgpiops_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xgpiops_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..81e8d6a9ffd1b8ca42f717278bf5dcd4447d973b
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xgpiops_hw.h
@@ -0,0 +1,164 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_hw.h
+* @addtogroup gpiops_v3_1
+* @{
+*
+* This header file contains the identifiers and basic driver functions (or
+* macros) that can be used to access the device. Other driver functions
+* are defined in xgpiops.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.02a hk   08/22/13 Added low level reset API function prototype and
+*                     related constant definitions
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Corrected reset values of banks.
+* </pre>
+*
+******************************************************************************/
+#ifndef XGPIOPS_HW_H		/* prevent circular inclusions */
+#define XGPIOPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register offsets for the GPIO. Each register is 32 bits.
+ *  @{
+ */
+#define XGPIOPS_DATA_LSW_OFFSET  0x00000000U  /* Mask and Data Register LSW, WO */
+#define XGPIOPS_DATA_MSW_OFFSET  0x00000004U  /* Mask and Data Register MSW, WO */
+#define XGPIOPS_DATA_OFFSET	 0x00000040U  /* Data Register, RW */
+#define XGPIOPS_DATA_RO_OFFSET	 0x00000060U  /* Data Register - Input, RO */
+#define XGPIOPS_DIRM_OFFSET	 0x00000204U  /* Direction Mode Register, RW */
+#define XGPIOPS_OUTEN_OFFSET	 0x00000208U  /* Output Enable Register, RW */
+#define XGPIOPS_INTMASK_OFFSET	 0x0000020CU  /* Interrupt Mask Register, RO */
+#define XGPIOPS_INTEN_OFFSET	 0x00000210U  /* Interrupt Enable Register, WO */
+#define XGPIOPS_INTDIS_OFFSET	 0x00000214U  /* Interrupt Disable Register, WO*/
+#define XGPIOPS_INTSTS_OFFSET	 0x00000218U  /* Interrupt Status Register, RO */
+#define XGPIOPS_INTTYPE_OFFSET	 0x0000021CU  /* Interrupt Type Register, RW */
+#define XGPIOPS_INTPOL_OFFSET	 0x00000220U  /* Interrupt Polarity Register, RW */
+#define XGPIOPS_INTANY_OFFSET	 0x00000224U  /* Interrupt On Any Register, RW */
+/* @} */
+
+/** @name Register offsets for each Bank.
+ *  @{
+ */
+#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U  /* Data/Mask Registers offset */
+#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U  /* Data Registers offset */
+#define XGPIOPS_REG_MASK_OFFSET  0x00000040U  /* Registers offset */
+/* @} */
+
+/* For backwards compatibility */
+#define XGPIOPS_BYPM_MASK_OFFSET	(u32)0x40
+
+/** @name Interrupt type reset values for each bank
+ *  @{
+ */
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+#define XGPIOPS_INTTYPE_BANK0_RESET  0x03FFFFFFU  /* Resets specific to Zynq Ultrascale+ MP */
+#define XGPIOPS_INTTYPE_BANK1_RESET  0x03FFFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET  0x03FFFFFFU
+#else
+#define XGPIOPS_INTTYPE_BANK0_RESET  0xFFFFFFFFU  /* Resets specific to Zynq */
+#define XGPIOPS_INTTYPE_BANK1_RESET  0x003FFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET  0xFFFFFFFFU
+#endif
+
+#define XGPIOPS_INTTYPE_BANK3_RESET  0xFFFFFFFFU  /* Reset common to both platforms */
+#define XGPIOPS_INTTYPE_BANK4_RESET  0xFFFFFFFFU  /* Resets specific to Zynq Ultrascale+ MP */
+#define XGPIOPS_INTTYPE_BANK5_RESET  0xFFFFFFFFU
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param	BaseAddr is the base address of the device.
+* @param	RegOffset is the register offset to be read.
+*
+* @return	The 32-bit value of the register
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XGpioPs_ReadReg(BaseAddr, RegOffset)		\
+		Xil_In32((BaseAddr) + (u32)(RegOffset))
+
+/****************************************************************************/
+/**
+*
+* This macro writes to the given register.
+*
+* @param	BaseAddr is the base address of the device.
+* @param	RegOffset is the offset of the register to be written.
+* @param	Data is the 32-bit value to write to the register.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data)	\
+		Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes ******************************/
+
+void XGpioPs_ResetHw(u32 BaseAddress);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XGPIOPS_HW_H */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xiicps.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xiicps.h
new file mode 100644
index 0000000000000000000000000000000000000000..a7b956f64a11a963435455c09b6a3b77047626b1
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xiicps.h
@@ -0,0 +1,423 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps.h
+* @addtogroup iicps_v3_0
+* @{
+* @details
+*
+* This is an implementation of IIC driver in the PS block. The device can
+* be either a master or a slave on the IIC bus. This implementation supports
+* both interrupt mode transfer and polled mode transfer. Only 7-bit address
+* is used in the driver, although the hardware also supports 10-bit address.
+*
+* IIC is a 2-wire serial interface.  The master controls the clock, so it can
+* regulate when it wants to send or receive data. The slave is under control of
+* the master, it must respond quickly since it has no control of the clock and
+* must send/receive data as fast or as slow as the master does.
+*
+* The higher level software must implement a higher layer protocol to inform
+* the slave what to send to the master.
+*
+* <b>Initialization & Configuration</b>
+*
+* The XIicPs_Config structure is used by the driver to configure itself. This
+* configuration structure is typically created by the tool-chain based on HW
+* build properties.
+*
+* To support multiple runtime loading and initialization strategies employed by
+* various operating systems, the driver instance can be initialized in the
+* following way:
+*
+*    - XIicPs_LookupConfig(DeviceId) - Use the device identifier to find
+*      the static configuration structure defined in xiicps_g.c. This is
+*      setup by the tools. For some operating systems the config structure
+*      will be initialized by the software and this call is not needed.
+*
+*   - XIicPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+*     configuration structure provided by the caller. If running in a
+*     system with address translation, the provided virtual memory base
+*     address replaces the physical address in the configuration
+*     structure.
+*
+* <b>Multiple Masters</b>
+*
+* More than one master can exist, bus arbitration is defined in the IIC
+* standard. Lost of arbitration causes arbitration loss interrupt on the device.
+*
+* <b>Multiple Slaves</b>
+*
+* Multiple slaves are supported by selecting them with unique addresses. It is
+* up to the system designer to be sure all devices on the IIC bus have
+* unique addresses.
+*
+* <b>Addressing</b>
+*
+* The IIC hardware can use 7 or 10 bit addresses.  The driver provides the
+* ability to control which address size is sent in messages as a master to a
+* slave device.
+*
+* <b>FIFO Size </b>
+* The hardware FIFO is 32 bytes deep. The user must know the limitations of
+* other IIC devices on the bus. Some are only able to receive a limited number
+* of bytes in a single transfer.
+*
+* <b>Data Rates</b>
+*
+* The data rate is set by values in the control register. The formula for
+* determining the correct register values is:
+* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
+*
+* When the device is configured as a slave, the slck setting controls the
+* sample rate and so must be set to be at least as fast as the fastest scl
+* expected to be seen in the system.
+*
+* <b>Polled Mode Operation</b>
+*
+* This driver supports polled mode transfers.
+*
+* <b>Interrupts</b>
+*
+* The user must connect the interrupt handler of the driver,
+* XIicPs_InterruptHandler to an interrupt system such that it will be called
+* when an interrupt occurs. This function does not save and restore the
+* processor context such that the user must provide this processing.
+*
+* The driver handles the following interrupts:
+* - Transfer complete
+* - More Data
+* - Transfer not Acknowledged
+* - Transfer Time out
+* - Monitored slave ready - master mode only
+* - Receive Overflow
+* - Transmit FIFO overflow
+* - Receive FIFO underflow
+* - Arbitration lost
+*
+* <b>Bus Busy</b>
+*
+* Bus busy is checked before the setup of a master mode device, to avoid
+* unnecessary arbitration loss interrupt.
+*
+* <b>RTOS Independence</b>
+*
+* This driver is intended to be RTOS and processor independent.  It works with
+* physical addresses only.  Any needs for dynamic memory management, threads or
+* thread mutual exclusion, virtual memory, or cache control must be satisfied by
+* the layer above this driver.
+*
+*<b>Repeated Start</b>
+*
+* The I2C controller does not indicate completion of a receive transfer if HOLD
+* bit is set. Due to this errata, repeated start cannot be used if a receive
+* transfer is followed by any other transfer.
+*
+* <pre> MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/08 First release
+* 1.00a sdm     09/21/11 Fixed an issue in the XIicPs_SetOptions and
+*			 XIicPs_ClearOptions where the InstancePtr->Options
+*			 was not updated correctly.
+* 			 Updated the InstancePtr->Options in the
+*			 XIicPs_CfgInitialize by calling XIicPs_GetOptions.
+*			 Updated the XIicPs_SetupMaster to not check for
+*			 Bus Busy condition when the Hold Bit is set.
+*			 Removed some unused variables.
+* 1.01a sg      03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
+*			 check for transfer completion is added, which indicates
+*			 the completion of current transfer.
+* 1.02a sg	08/29/12 Updated the logic to arrive at the best divisors
+*			 to achieve I2C clock with minimum error for
+*			 CR #674195
+* 1.03a hk  05/04/13 Initialized BestDivA and BestDivB to 0.
+*			 This is fix for CR#704398 to remove warning.
+* 2.0   hk  03/07/14 Added check for error status in the while loop that
+*                    checks for completion.
+*                    (XIicPs_MasterSendPolled function). CR# 762244, 764875.
+*                    Limited frequency set when 100KHz or 400KHz is
+*                    selected. This is a hardware limitation. CR#779290.
+* 2.1   hk  04/24/14 Fix for CR# 789821 to handle >14 byte transfers.
+*                    Explicitly reset CR and clear FIFO in Abort function
+*                    and state the same in the comments. CR# 784254.
+*                    Fix for CR# 761060 - provision for repeated start.
+* 2.2   hk  08/23/14 Slave monitor mode changes - clear FIFO, enable
+*                    read mode and clear transfer size register.
+*                    Disable NACK to avoid interrupts on each retry.
+* 2.3	sk	10/07/14 Repeated start feature deleted.
+* 3.0	sk	11/03/14 Modified TimeOut Register value to 0xFF
+* 					 in XIicPs_Reset.
+* 			12/06/14 Implemented Repeated start feature.
+*			01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*			02/18/15 Implemented larger data transfer using repeated start
+*					  in Zynq UltraScale MP.
+* 3.3   kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
+*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+*                    generation.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIICPS_H       /* prevent circular inclusions */
+#define XIICPS_H       /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xiicps_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Configuration options
+ *
+ * The following options may be specified or retrieved for the device and
+ * enable/disable additional features of the IIC.  Each of the options
+ * are bit fields, so more than one may be specified.
+ *
+ * @{
+ */
+#define XIICPS_7_BIT_ADDR_OPTION	0x01U  /**< 7-bit address mode */
+#define XIICPS_10_BIT_ADDR_OPTION	0x02U  /**< 10-bit address mode */
+#define XIICPS_SLAVE_MON_OPTION		0x04U  /**< Slave monitor mode */
+#define XIICPS_REP_START_OPTION		0x08U  /**< Repeated Start */
+/*@}*/
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that are passed to an application
+ * event handler from the driver.  These constants are bit masks such that
+ * more than one event can be passed to the handler.
+ *
+ * @{
+ */
+#define XIICPS_EVENT_COMPLETE_SEND	0x0001U  /**< Transmit Complete Event*/
+#define XIICPS_EVENT_COMPLETE_RECV	0x0002U  /**< Receive Complete Event*/
+#define XIICPS_EVENT_TIME_OUT		0x0004U  /**< Transfer timed out */
+#define XIICPS_EVENT_ERROR			0x0008U  /**< Receive error */
+#define XIICPS_EVENT_ARB_LOST		0x0010U  /**< Arbitration lost */
+#define XIICPS_EVENT_NACK			0x0020U  /**< NACK Received */
+#define XIICPS_EVENT_SLAVE_RDY		0x0040U  /**< Slave ready */
+#define XIICPS_EVENT_RX_OVR			0x0080U  /**< RX overflow */
+#define XIICPS_EVENT_TX_OVR			0x0100U  /**< TX overflow */
+#define XIICPS_EVENT_RX_UNF			0x0200U  /**< RX underflow */
+/*@}*/
+
+/** @name Role constants
+ *
+ * These constants are used to pass into the device setup routines to
+ * set up the device according to transfer direction.
+ */
+#define SENDING_ROLE		1  /**< Transfer direction is sending */
+#define RECVING_ROLE		0  /**< Transfer direction is receiving */
+
+/* Maximum transfer size */
+#define XIICPS_MAX_TRANSFER_SIZE	(u32)(255U - 3U)
+
+/**************************** Type Definitions *******************************/
+
+/**
+* The handler data type allows the user to define a callback function to
+* respond to interrupt events in the system. This function is executed
+* in interrupt context, so amount of processing should be minimized.
+*
+* @param	CallBackRef is the callback reference passed in by the upper
+*		layer when setting the callback functions, and passed back to
+*		the upper layer when the callback is invoked. Its type is
+*		not important to the driver, so it is a void pointer.
+* @param	StatusEvent indicates one or more status events that occurred.
+*/
+typedef void (*XIicPs_IntrHandler) (void *CallBackRef, u32 StatusEvent);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;     /**< Unique ID  of device */
+	u32 BaseAddress;  /**< Base address of the device */
+	u32 InputClockHz; /**< Input clock frequency */
+} XIicPs_Config;
+
+/**
+ * The XIicPs driver instance data. The user is required to allocate a
+ * variable of this type for each IIC device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XIicPs_Config Config;	/* Configuration structure */
+	u32 IsReady;		/* Device is initialized and ready */
+	u32 Options;		/* Options set in the device */
+
+	u8 *SendBufferPtr;	/* Pointer to send buffer */
+	u8 *RecvBufferPtr;	/* Pointer to recv buffer */
+	s32 SendByteCount;	/* Number of bytes still expected to send */
+	s32 RecvByteCount;	/* Number of bytes still expected to receive */
+	s32 CurrByteCount;	/* No. of bytes expected in current transfer */
+
+	s32 UpdateTxSize;	/* If tx size register has to be updated */
+	s32 IsSend;		/* Whether master is sending or receiving */
+	s32 IsRepeatedStart;	/* Indicates if user set repeated start */
+
+	XIicPs_IntrHandler StatusHandler;  /* Event handler function */
+	void *CallBackRef;	/* Callback reference for event handler */
+} XIicPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/****************************************************************************/
+/*
+*
+* Place one byte into the transmit FIFO.
+*
+* @param	InstancePtr is the instance of IIC
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XIicPs_SendByte(XIicPs *InstancePtr)
+*
+*****************************************************************************/
+#define XIicPs_SendByte(InstancePtr)					\
+{									\
+	u8 Data;							\
+	Data = *((InstancePtr)->SendBufferPtr);				\
+	 XIicPs_Out32((InstancePtr)->Config.BaseAddress			\
+			 + (u32)(XIICPS_DATA_OFFSET), 			\
+					(u32)(Data));			\
+	(InstancePtr)->SendBufferPtr += 1;				\
+	(InstancePtr)->SendByteCount -= 1;\
+}
+
+/****************************************************************************/
+/*
+*
+* Receive one byte from FIFO.
+*
+* @param	InstancePtr is the instance of IIC
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		u8 XIicPs_RecvByte(XIicPs *InstancePtr)
+*
+*****************************************************************************/
+#define XIicPs_RecvByte(InstancePtr)					\
+{									\
+	u8 *Data, Value;						\
+	Value = (u8)(XIicPs_In32((InstancePtr)->Config.BaseAddress	\
+		  + (u32)XIICPS_DATA_OFFSET));  			\
+	Data = &Value;							\
+	*(InstancePtr)->RecvBufferPtr = *Data;				\
+	(InstancePtr)->RecvBufferPtr += 1;				\
+	 (InstancePtr)->RecvByteCount --; 				\
+}
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Function for configuration lookup, in xiicps_sinit.c
+ */
+XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Functions for general setup, in xiicps.c
+ */
+s32 XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config * ConfigPtr,
+				  u32 EffectiveAddr);
+
+void XIicPs_Abort(XIicPs *InstancePtr);
+void XIicPs_Reset(XIicPs *InstancePtr);
+
+s32 XIicPs_BusIsBusy(XIicPs *InstancePtr);
+s32 TransmitFifoFill(XIicPs *InstancePtr);
+
+/*
+ * Functions for interrupts, in xiicps_intr.c
+ */
+void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef,
+				  XIicPs_IntrHandler FunctionPtr);
+
+/*
+ * Functions for device as master, in xiicps_master.c
+ */
+void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		u16 SlaveAddr);
+void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		u16 SlaveAddr);
+s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		u16 SlaveAddr);
+s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		u16 SlaveAddr);
+void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr);
+void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr);
+void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr);
+
+/*
+ * Functions for device as slave, in xiicps_slave.c
+ */
+void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr);
+void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+s32 XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr);
+
+/*
+ * Functions for selftest, in xiicps_selftest.c
+ */
+s32 XIicPs_SelfTest(XIicPs *InstancePtr);
+
+/*
+ * Functions for setting and getting data rate, in xiicps_options.c
+ */
+s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options);
+s32 XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options);
+u32 XIicPs_GetOptions(XIicPs *InstancePtr);
+
+s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz);
+u32 XIicPs_GetSClk(XIicPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xiicps_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xiicps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..3b00cf8b17c45a75162e3d7fdcb4cc0f554a96f2
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xiicps_hw.h
@@ -0,0 +1,383 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_hw.h
+* @addtogroup iicps_v3_0
+* @{
+*
+* This header file contains the hardware definition for an IIC device.
+* It includes register definitions and interface functions to read/write
+* the registers.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who 	Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/10 First release
+* 1.04a kpc		11/07/13 Added function prototype.
+* 3.0	sk		11/03/14 Modified the TimeOut Register value to 0xFF
+*				01/31/15 Modified the code according to MISRAC 2012 Compliant.
+* </pre>
+*
+******************************************************************************/
+#ifndef XIICPS_HW_H		/* prevent circular inclusions */
+#define XIICPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the IIC.
+ * @{
+ */
+#define XIICPS_CR_OFFSET			0x00U  /**< 32-bit Control */
+#define XIICPS_SR_OFFSET			0x04U  /**< Status */
+#define XIICPS_ADDR_OFFSET			0x08U  /**< IIC Address */
+#define XIICPS_DATA_OFFSET			0x0CU  /**< IIC FIFO Data */
+#define XIICPS_ISR_OFFSET			0x10U  /**< Interrupt Status */
+#define XIICPS_TRANS_SIZE_OFFSET	0x14U  /**< Transfer Size */
+#define XIICPS_SLV_PAUSE_OFFSET		0x18U  /**< Slave monitor pause */
+#define XIICPS_TIME_OUT_OFFSET		0x1CU  /**< Time Out */
+#define XIICPS_IMR_OFFSET			0x20U  /**< Interrupt Enabled Mask */
+#define XIICPS_IER_OFFSET			0x24U  /**< Interrupt Enable */
+#define XIICPS_IDR_OFFSET			0x28U  /**< Interrupt Disable */
+/* @} */
+
+/** @name Control Register
+ *
+ * This register contains various control bits that
+ * affects the operation of the IIC controller. Read/Write.
+ * @{
+ */
+
+#define XIICPS_CR_DIV_A_MASK	0x0000C000U /**< Clock Divisor A */
+#define XIICPS_CR_DIV_A_SHIFT			14U /**< Clock Divisor A shift */
+#define XIICPS_DIV_A_MAX				 4U /**< Maximum value of Divisor A */
+#define XIICPS_CR_DIV_B_MASK	0x00003F00U /**< Clock Divisor B */
+#define XIICPS_CR_DIV_B_SHIFT			 8U /**< Clock Divisor B shift */
+#define XIICPS_CR_CLR_FIFO_MASK	0x00000040U /**< Clear FIFO, auto clears*/
+#define XIICPS_CR_SLVMON_MASK	0x00000020U /**< Slave monitor mode */
+#define XIICPS_CR_HOLD_MASK		0x00000010U /**<  Hold bus 1=Hold scl,
+												0=terminate transfer */
+#define XIICPS_CR_ACKEN_MASK	0x00000008U /**< Enable TX of ACK when
+												Master receiver*/
+#define XIICPS_CR_NEA_MASK		0x00000004U /**< Addressing Mode 1=7 bit,
+												0=10 bit */
+#define XIICPS_CR_MS_MASK		0x00000002U /**< Master mode bit 1=Master,
+												0=Slave */
+#define XIICPS_CR_RD_WR_MASK	0x00000001U /**< Read or Write Master
+												transfer  0=Transmitter,
+												1=Receiver*/
+#define XIICPS_CR_RESET_VALUE			 0U /**< Reset value of the Control
+												register */
+/* @} */
+
+/** @name IIC Status Register
+ *
+ * This register is used to indicate status of the IIC controller. Read only
+ * @{
+ */
+#define XIICPS_SR_BA_MASK		0x00000100U  /**< Bus Active Mask */
+#define XIICPS_SR_RXOVF_MASK	0x00000080U  /**< Receiver Overflow Mask */
+#define XIICPS_SR_TXDV_MASK		0x00000040U  /**< Transmit Data Valid Mask */
+#define XIICPS_SR_RXDV_MASK		0x00000020U  /**< Receiver Data Valid Mask */
+#define XIICPS_SR_RXRW_MASK		0x00000008U  /**< Receive read/write Mask */
+/* @} */
+
+/** @name IIC Address Register
+ *
+ * Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0].
+ * A write access to this register always initiates a transfer if the IIC is in
+ * master mode. Read/Write
+ * @{
+ */
+#define XIICPS_ADDR_MASK	0x000003FF  /**< IIC Address Mask */
+/* @} */
+
+/** @name IIC Data Register
+ *
+ * When written to, the data register sets data to transmit. When read from, the
+ * data register reads the last received byte of data. Read/Write
+ * @{
+ */
+#define XIICPS_DATA_MASK	0x000000FF  /**< IIC Data Mask */
+/* @} */
+
+/** @name IIC Interrupt Registers
+ *
+ * <b>IIC Interrupt Status Register</b>
+ *
+ * This register holds the interrupt status flags for the IIC controller. Some
+ * of the flags are level triggered
+ * - i.e. are set as long as the interrupt condition exists.  Other flags are
+ *   edge triggered, which means they are set one the interrupt condition occurs
+ *   then remain set until they are cleared by software.
+ *   The interrupts are cleared by writing a one to the interrupt bit position
+ *   in the Interrupt Status Register. Read/Write.
+ *
+ * <b>IIC Interrupt Enable Register</b>
+ *
+ * This register is used to enable interrupt sources for the IIC controller.
+ * Writing a '1' to a bit in this register clears the corresponding bit in the
+ * IIC Interrupt Mask register.  Write only.
+ *
+ * <b>IIC Interrupt Disable Register </b>
+ *
+ * This register is used to disable interrupt sources for the IIC controller.
+ * Writing a '1' to a bit in this register sets the corresponding bit in the
+ * IIC Interrupt Mask register. Write only.
+ *
+ * <b>IIC Interrupt Mask Register</b>
+ *
+ * This register shows the enabled/disabled status of each IIC controller
+ * interrupt source. A bit set to 1 will ignore the corresponding interrupt in
+ * the status register. A bit set to 0 means the interrupt is enabled.
+ * All mask bits are set and all interrupts are disabled after reset. Read only.
+ *
+ * All four registers have the same bit definitions. They are only defined once
+ * for each of the Interrupt Enable Register, Interrupt Disable Register,
+ * Interrupt Mask Register, and Interrupt Status Register
+ * @{
+ */
+
+#define XIICPS_IXR_ARB_LOST_MASK  0x00000200U	 /**< Arbitration Lost Interrupt
+													mask */
+#define XIICPS_IXR_RX_UNF_MASK    0x00000080U	 /**< FIFO Recieve Underflow
+													Interrupt mask */
+#define XIICPS_IXR_TX_OVR_MASK    0x00000040U	 /**< Transmit Overflow
+													Interrupt mask */
+#define XIICPS_IXR_RX_OVR_MASK    0x00000020U	 /**< Receive Overflow Interrupt
+													mask */
+#define XIICPS_IXR_SLV_RDY_MASK   0x00000010U	 /**< Monitored Slave Ready
+													Interrupt mask */
+#define XIICPS_IXR_TO_MASK        0x00000008U	 /**< Transfer Time Out
+													Interrupt mask */
+#define XIICPS_IXR_NACK_MASK      0x00000004U	 /**< NACK Interrupt mask */
+#define XIICPS_IXR_DATA_MASK      0x00000002U	 /**< Data Interrupt mask */
+#define XIICPS_IXR_COMP_MASK      0x00000001U	 /**< Transfer Complete
+													Interrupt mask */
+#define XIICPS_IXR_DEFAULT_MASK   0x000002FFU	 /**< Default ISR Mask */
+#define XIICPS_IXR_ALL_INTR_MASK  0x000002FFU	 /**< All ISR Mask */
+/* @} */
+
+
+/** @name IIC Transfer Size Register
+*
+* The register's meaning varies according to the operating mode as follows:
+*   - Master transmitter mode: number of data bytes still not transmitted minus
+*     one
+*   - Master receiver mode: number of data bytes that are still expected to be
+*     received
+*   - Slave transmitter mode: number of bytes remaining in the FIFO after the
+*     master terminates the transfer
+*   - Slave receiver mode: number of valid data bytes in the FIFO
+*
+* This register is cleared if CLR_FIFO bit in the control register is set.
+* Read/Write
+* @{
+*/
+#define XIICPS_TRANS_SIZE_MASK  0x0000003F /**< IIC Transfer Size Mask */
+#define XIICPS_FIFO_DEPTH          16	  /**< Number of bytes in the FIFO */
+#define XIICPS_DATA_INTR_DEPTH     14    /**< Number of bytes at DATA intr */
+/* @} */
+
+
+/** @name IIC Slave Monitor Pause Register
+*
+* This register is associated with the slave monitor mode of the I2C interface.
+* It is meaningful only when the module is in master mode and bit SLVMON in the
+* control register is set.
+*
+* This register defines the pause interval between consecutive attempts to
+* address the slave once a write to an I2C address register is done by the
+* host. It represents the number of sclk cycles minus one between two attempts.
+*
+* The reset value of the register is 0, which results in the master repeatedly
+* trying to access the slave immediately after unsuccessful attempt.
+* Read/Write
+* @{
+*/
+#define XIICPS_SLV_PAUSE_MASK    0x0000000F  /**< Slave monitor pause mask */
+/* @} */
+
+
+/** @name IIC Time Out Register
+*
+* The value of time out register represents the time out interval in number of
+* sclk cycles minus one.
+*
+* When the accessed slave holds the sclk line low for longer than the time out
+* period, thus prohibiting the I2C interface in master mode to complete the
+* current transfer, an interrupt is generated and TO interrupt flag is set.
+*
+* The reset value of the register is 0x1f.
+* Read/Write
+* @{
+ */
+#define XIICPS_TIME_OUT_MASK    0x000000FFU    /**< IIC Time Out mask */
+#define XIICPS_TO_RESET_VALUE   0x000000FFU    /**< IIC Time Out reset value */
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XIicPs_In32 Xil_In32
+#define XIicPs_Out32 Xil_Out32
+
+/****************************************************************************/
+/**
+* Read an IIC register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to select the specific register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XIicPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XIicPs_ReadReg(BaseAddress, RegOffset) \
+	XIicPs_In32((BaseAddress) + (u32)(RegOffset))
+
+/***************************************************************************/
+/**
+* Write an IIC register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to select the specific register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note	C-Style signature:
+*	void XIicPs_WriteReg(u32 BaseAddress, int RegOffset, u32 RegisterValue)
+*
+******************************************************************************/
+#define XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+	XIicPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
+
+/***************************************************************************/
+/**
+* Read the interrupt enable register.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	Current bit mask that represents currently enabled interrupts.
+*
+* @note		C-Style signature:
+*		u32 XIicPs_ReadIER(u32 BaseAddress)
+*
+******************************************************************************/
+#define XIicPs_ReadIER(BaseAddress) \
+	XIicPs_ReadReg((BaseAddress),  XIICPS_IER_OFFSET)
+
+/***************************************************************************/
+/**
+* Write to the interrupt enable register.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @param	IntrMask is the interrupts to be enabled.
+*
+* @return	None.
+*
+* @note	C-Style signature:
+*	void XIicPs_EnabledInterrupts(u32 BaseAddress, u32 IntrMask)
+*
+******************************************************************************/
+#define XIicPs_EnableInterrupts(BaseAddress, IntrMask) \
+	XIicPs_WriteReg((BaseAddress), XIICPS_IER_OFFSET, (IntrMask))
+
+/***************************************************************************/
+/**
+* Disable all interrupts.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XIicPs_DisableAllInterrupts(u32 BaseAddress)
+*
+******************************************************************************/
+#define XIicPs_DisableAllInterrupts(BaseAddress) \
+	XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
+		XIICPS_IXR_ALL_INTR_MASK)
+
+/***************************************************************************/
+/**
+* Disable selected interrupts.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @param	IntrMask is the interrupts to be disabled.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XIicPs_DisableInterrupts(u32 BaseAddress, u32 IntrMask)
+*
+******************************************************************************/
+#define XIicPs_DisableInterrupts(BaseAddress, IntrMask) \
+	XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
+		(IntrMask))
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the I2c interface
+ */
+void XIicPs_ResetHw(u32 BaseAddress);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_assert.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_assert.h
new file mode 100644
index 0000000000000000000000000000000000000000..add4124e2c0c48a8844dfb3aad307c8ec5ae6e38
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_assert.h
@@ -0,0 +1,195 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.h
+*
+* @addtogroup common_assert_apis Assert APIs and Macros
+*
+* The xil_assert.h file contains assert related functions and macros.
+* Assert APIs/Macros specifies that a application program satisfies certain
+* conditions at particular points in its execution. These function can be
+* used by application programs to ensure that, application code is satisfying
+* certain conditions.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* 6.0   kvn  05/31/16 Make Xil_AsserWait a global variable
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_ASSERT_H	/* prevent circular inclusions */
+#define XIL_ASSERT_H	/* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+
+/************************** Constant Definitions *****************************/
+
+#define XIL_ASSERT_NONE     0U
+#define XIL_ASSERT_OCCURRED 1U
+#define XNULL NULL
+
+extern u32 Xil_AssertStatus;
+extern s32 Xil_AssertWait;
+extern void Xil_Assert(const char8 *File, s32 Line);
+void XNullHandler(void *NullParameter);
+
+/**
+ * This data type defines a callback to be invoked when an
+ * assert occurs. The callback is invoked only when asserts are enabled
+ */
+typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#ifndef NDEBUG
+
+/*****************************************************************************/
+/**
+* @brief    This assert macro is to be used for void functions. This in
+*           conjunction with the Xil_AssertWait boolean can be used to
+*           accomodate tests so that asserts which fail allow execution to
+*           continue.
+*
+* @param    Expression: expression to be evaluated. If it evaluates to
+*           false, the assert occurs.
+*
+* @return   Returns void unless the Xil_AssertWait variable is true, in which
+*           case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertVoid(Expression)                \
+{                                                  \
+    if (Expression) {                              \
+        Xil_AssertStatus = XIL_ASSERT_NONE;       \
+    } else {                                       \
+        Xil_Assert(__FILE__, __LINE__);            \
+        Xil_AssertStatus = XIL_ASSERT_OCCURRED;   \
+        return;                                    \
+    }                                              \
+}
+
+/*****************************************************************************/
+/**
+* @brief    This assert macro is to be used for functions that do return a
+*           value. This in conjunction with the Xil_AssertWait boolean can be
+*           used to accomodate tests so that asserts which fail allow execution
+*           to continue.
+*
+* @param    Expression: expression to be evaluated. If it evaluates to false,
+*           the assert occurs.
+*
+* @return   Returns 0 unless the Xil_AssertWait variable is true, in which
+* 	        case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertNonvoid(Expression)             \
+{                                                  \
+    if (Expression) {                              \
+        Xil_AssertStatus = XIL_ASSERT_NONE;       \
+    } else {                                       \
+        Xil_Assert(__FILE__, __LINE__);            \
+        Xil_AssertStatus = XIL_ASSERT_OCCURRED;   \
+        return 0;                                  \
+    }                                              \
+}
+
+/*****************************************************************************/
+/**
+* @brief     Always assert. This assert macro is to be used for void functions.
+*            Use for instances where an assert should always occur.
+*
+* @return    Returns void unless the Xil_AssertWait variable is true, in which
+*	         case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertVoidAlways()                   \
+{                                                  \
+   Xil_Assert(__FILE__, __LINE__);                 \
+   Xil_AssertStatus = XIL_ASSERT_OCCURRED;        \
+   return;                                         \
+}
+
+/*****************************************************************************/
+/**
+* @brief   Always assert. This assert macro is to be used for functions that
+*          do return a value. Use for instances where an assert should always
+*          occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+*	      case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertNonvoidAlways()                \
+{                                                  \
+   Xil_Assert(__FILE__, __LINE__);                 \
+   Xil_AssertStatus = XIL_ASSERT_OCCURRED;        \
+   return 0;                                       \
+}
+
+
+#else
+
+#define Xil_AssertVoid(Expression)
+#define Xil_AssertVoidAlways()
+#define Xil_AssertNonvoid(Expression)
+#define Xil_AssertNonvoidAlways()
+
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_AssertSetCallback(Xil_AssertCallback Routine);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/**
+* @} End of "addtogroup common_assert_apis".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_cache.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_cache.h
new file mode 100644
index 0000000000000000000000000000000000000000..b6614d5f992709379ce97da6e8be0cfb9eb80d8b
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_cache.h
@@ -0,0 +1,121 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.h
+*
+* @addtogroup a9_cache_apis Cortex A9 Processor Cache Functions
+*
+* Cache functions provide access to cache related operations such as flush
+* and invalidate for instruction and data caches. It gives option to perform
+* the cache operations on a single cacheline, a range of memory and an entire
+* cache.
+*
+* @{
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  01/29/10 First release
+* 3.04a sdm  01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
+*		      APIs.
+* </pre>
+*
+******************************************************************************/
+#ifndef XIL_CACHE_H
+#define XIL_CACHE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __GNUC__
+
+#define asm_cp15_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+			XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+			XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \
+			XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
+
+#define asm_cp15_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
+			XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
+			XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
+
+#elif defined (__ICCARM__)
+
+#define asm_cp15_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
+			XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
+			XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_inval_ic_line_mva_pou(param) __asm volatile ("mcr " \
+			XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
+
+#define asm_cp15_inval_dc_line_sw(param) __asm volatile ("mcr " \
+			XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_sw(param) __asm volatile ("mcr " \
+			XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
+
+#endif
+
+void Xil_DCacheEnable(void);
+void Xil_DCacheDisable(void);
+void Xil_DCacheInvalidate(void);
+void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
+void Xil_DCacheFlush(void);
+void Xil_DCacheFlushRange(INTPTR adr, u32 len);
+
+void Xil_ICacheEnable(void);
+void Xil_ICacheDisable(void);
+void Xil_ICacheInvalidate(void);
+void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_cache_apis".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_cache_l.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_cache_l.h
new file mode 100644
index 0000000000000000000000000000000000000000..fa92c6b1c4087b05b80e256770a5c0d023d99fe2
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_cache_l.h
@@ -0,0 +1,100 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_l.h
+*
+* Contains L1 and L2 specific functions for the ARM cache functionality
+* used by xcache.c. This functionality is being made available here for
+* more sophisticated users.
+*
+* @addtogroup a9_cache_apis
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  01/24/10 First release
+* </pre>
+*
+******************************************************************************/
+#ifndef XIL_CACHE_MACH_H
+#define XIL_CACHE_MACH_H
+
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_DCacheInvalidateLine(u32 adr);
+void Xil_DCacheFlushLine(u32 adr);
+void Xil_DCacheStoreLine(u32 adr);
+void Xil_ICacheInvalidateLine(u32 adr);
+
+void Xil_L1DCacheEnable(void);
+void Xil_L1DCacheDisable(void);
+void Xil_L1DCacheInvalidate(void);
+void Xil_L1DCacheInvalidateLine(u32 adr);
+void Xil_L1DCacheInvalidateRange(u32 adr, u32 len);
+void Xil_L1DCacheFlush(void);
+void Xil_L1DCacheFlushLine(u32 adr);
+void Xil_L1DCacheFlushRange(u32 adr, u32 len);
+void Xil_L1DCacheStoreLine(u32 adr);
+
+void Xil_L1ICacheEnable(void);
+void Xil_L1ICacheDisable(void);
+void Xil_L1ICacheInvalidate(void);
+void Xil_L1ICacheInvalidateLine(u32 adr);
+void Xil_L1ICacheInvalidateRange(u32 adr, u32 len);
+
+void Xil_L2CacheEnable(void);
+void Xil_L2CacheDisable(void);
+void Xil_L2CacheInvalidate(void);
+void Xil_L2CacheInvalidateLine(u32 adr);
+void Xil_L2CacheInvalidateRange(u32 adr, u32 len);
+void Xil_L2CacheFlush(void);
+void Xil_L2CacheFlushLine(u32 adr);
+void Xil_L2CacheFlushRange(u32 adr, u32 len);
+void Xil_L2CacheStoreLine(u32 adr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_cache_apis".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_cache_vxworks.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_cache_vxworks.h
new file mode 100644
index 0000000000000000000000000000000000000000..6e8cfa75fbfaa26744b0f9f9bf3114753dc9b5f8
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_cache_vxworks.h
@@ -0,0 +1,93 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_vxworks.h
+*
+* Contains the cache related functions for VxWorks that is wrapped by
+* xil_cache.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  12/11/09 Initial release
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_CACHE_VXWORKS_H
+#define XIL_CACHE_VXWORKS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "vxWorks.h"
+#include "vxLib.h"
+#include "sysLibExtra.h"
+#include "cacheLib.h"
+
+#if (CPU_FAMILY==PPC)
+
+#define Xil_DCacheEnable()		cacheEnable(DATA_CACHE)
+
+#define Xil_DCacheDisable()		cacheDisable(DATA_CACHE)
+
+#define Xil_DCacheInvalidateRange(Addr, Len) \
+		cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_DCacheFlushRange(Addr, Len) \
+		cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_ICacheEnable()		cacheEnable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheDisable()		cacheDisable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheInvalidateRange(Addr, Len) \
+		cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
+
+
+#else
+#error "Unknown processor / architecture. Must be PPC for VxWorks."
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_errata.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_errata.h
new file mode 100644
index 0000000000000000000000000000000000000000..800fcd562e8e32ec28ce4494ce37dcdf167396f8
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_errata.h
@@ -0,0 +1,127 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_errata.h
+*
+* @addtogroup a9_errata Cortex A9 Processor and pl310 Errata Support
+* @{
+* Various ARM errata are handled in the standalone BSP. The implementation for
+* errata handling follows ARM guidelines and is based on the open source Linux
+* support for these errata.
+*
+* @note
+* The errata handling is enabled by default. To disable handling of all the
+* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
+* disable errata on a per-erratum basis, un-define relevant macros in
+* xil_errata.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a srt  04/18/13 First release
+* </pre>
+*
+******************************************************************************/
+#ifndef XIL_ERRATA_H
+#define XIL_ERRATA_H
+
+/**
+ * @name errata_definitions
+ *
+ * The errata conditions handled in the standalone BSP are listed below
+ * @{
+ */
+
+#define ENABLE_ARM_ERRATA 1
+
+#ifdef ENABLE_ARM_ERRATA
+
+/**
+ *  Errata No: 	 742230
+ *  Description: DMB operation may be faulty
+ */
+#define CONFIG_ARM_ERRATA_742230 1
+
+/**
+ *  Errata No: 	 743622
+ *  Description: Faulty hazard checking in the Store Buffer may lead
+ *	         	 to data corruption.
+ */
+#define CONFIG_ARM_ERRATA_743622 1
+
+/**
+ *  Errata No: 	 775420
+ *  Description: A data cache maintenance operation which aborts,
+ *		 		 might lead to deadlock
+ */
+#define CONFIG_ARM_ERRATA_775420 1
+
+/**
+ *  Errata No: 	 794073
+ *  Description: Speculative instruction fetches with MMU disabled
+ *               might not comply with architectural requirements
+ */
+#define CONFIG_ARM_ERRATA_794073 1
+
+
+/** PL310 L2 Cache Errata */
+
+/**
+ *  Errata No: 	 588369
+ *  Description: Clean & Invalidate maintenance operations do not
+ *	   	 		 invalidate clean lines
+ */
+#define CONFIG_PL310_ERRATA_588369 1
+
+/**
+ *  Errata No: 	 727915
+ *  Description: Background Clean and Invalidate by Way operation
+ *		 can cause data corruption
+ */
+#define CONFIG_PL310_ERRATA_727915 1
+
+/**
+ *  Errata No: 	 753970
+ *  Description: Cache sync operation may be faulty
+ */
+#define CONFIG_PL310_ERRATA_753970 1
+/*@}*/
+#endif  /* ENABLE_ARM_ERRATA */
+
+#endif  /* XIL_ERRATA_H */
+/**
+* @} End of "addtogroup a9_errata".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_exception.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_exception.h
new file mode 100644
index 0000000000000000000000000000000000000000..ad48222058678dde33905835a16816fb2b834dea
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_exception.h
@@ -0,0 +1,256 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_exception.h
+*
+* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.
+* For exception related functions that can be used across all Xilinx supported
+* processors, please use xil_exception.h.
+*
+* @addtogroup arm_exception_apis ARM Processor Exception Handling
+* @{
+* ARM processors specific exception related APIs for cortex A53,A9 and R5 can
+* utilized for enabling/disabling IRQ, registering/removing handler for
+* exceptions or initializing exception vector table with null handler.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.2	pkp  	 28/05/15 First release
+* 6.0   mus      27/07/16 Consolidated file for a53,a9 and r5 processors
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
+#define XIL_EXCEPTION_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions ****************************/
+
+#define XIL_EXCEPTION_FIQ	XREG_CPSR_FIQ_ENABLE
+#define XIL_EXCEPTION_IRQ	XREG_CPSR_IRQ_ENABLE
+#define XIL_EXCEPTION_ALL	(XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
+
+#define XIL_EXCEPTION_ID_FIRST			0U
+#if defined (__aarch64__)
+#define XIL_EXCEPTION_ID_SYNC_INT		1U
+#define XIL_EXCEPTION_ID_IRQ_INT		2U
+#define XIL_EXCEPTION_ID_FIQ_INT		3U
+#define XIL_EXCEPTION_ID_SERROR_ABORT_INT		4U
+#define XIL_EXCEPTION_ID_LAST			5U
+#else
+#define XIL_EXCEPTION_ID_RESET			0U
+#define XIL_EXCEPTION_ID_UNDEFINED_INT		1U
+#define XIL_EXCEPTION_ID_SWI_INT		2U
+#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT	3U
+#define XIL_EXCEPTION_ID_DATA_ABORT_INT		4U
+#define XIL_EXCEPTION_ID_IRQ_INT		5U
+#define XIL_EXCEPTION_ID_FIQ_INT		6U
+#define XIL_EXCEPTION_ID_LAST			6U
+#endif
+
+/*
+ * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
+ */
+#define XIL_EXCEPTION_ID_INT	XIL_EXCEPTION_ID_IRQ_INT
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef is the exception handler function.
+ */
+typedef void (*Xil_ExceptionHandler)(void *data);
+typedef void (*Xil_InterruptHandler)(void *data);
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* @brief	Enable Exceptions.
+*
+* @param	Mask: Value for enabling the exceptions.
+*
+* @return	None.
+*
+* @note		If bit is 0, exception is enabled.
+*			C-Style signature: void Xil_ExceptionEnableMask(Mask)
+*
+******************************************************************************/
+#if defined (__GNUC__) || defined (__ICCARM__)
+#define Xil_ExceptionEnableMask(Mask)	\
+		mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionEnableMask(Mask)	\
+		{								\
+		  register u32 Reg __asm("cpsr"); \
+		  mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
+		}
+#endif
+/****************************************************************************/
+/**
+* @brief	Enable the IRQ exception.
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+#define Xil_ExceptionEnable() \
+		Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
+
+/****************************************************************************/
+/**
+* @brief	Disable Exceptions.
+*
+* @param	Mask: Value for disabling the exceptions.
+*
+* @return	None.
+*
+* @note		If bit is 1, exception is disabled.
+*			C-Style signature: Xil_ExceptionDisableMask(Mask)
+*
+******************************************************************************/
+#if defined (__GNUC__) || defined (__ICCARM__)
+#define Xil_ExceptionDisableMask(Mask)	\
+		mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionDisableMask(Mask)	\
+		{									\
+		  register u32 Reg __asm("cpsr"); \
+		  mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
+		}
+#endif
+/****************************************************************************/
+/**
+* Disable the IRQ exception.
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+#define Xil_ExceptionDisable() \
+		Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
+
+#if !defined (__aarch64__) && !defined (ARMA53_32)
+/****************************************************************************/
+/**
+* @brief	Enable nested interrupts by clearing the I and F bits in CPSR. This
+* 			API is defined for cortex-a9 and cortex-r5.
+*
+* @return   None.
+*
+* @note     This macro is supposed to be used from interrupt handlers. In the
+*			interrupt handler the interrupts are disabled by default (I and F
+*			are 1). To allow nesting of interrupts, this macro should be
+*			used. It clears the I and F bits by changing the ARM mode to
+*			system mode. Once these bits are cleared and provided the
+*			preemption of interrupt conditions are met in the GIC, nesting of
+*			interrupts will start happening.
+*			Caution: This macro must be used with caution. Before calling this
+*			macro, the user must ensure that the source of the current IRQ
+*			is appropriately cleared. Otherwise, as soon as we clear the I and
+*			F bits, there can be an infinite loop of interrupts with an
+*			eventual crash (all the stack space getting consumed).
+******************************************************************************/
+#define Xil_EnableNestedInterrupts() \
+		__asm__ __volatile__ ("stmfd   sp!, {lr}"); \
+		__asm__ __volatile__ ("mrs     lr, spsr");  \
+		__asm__ __volatile__ ("stmfd   sp!, {lr}"); \
+		__asm__ __volatile__ ("msr     cpsr_c, #0x1F"); \
+		__asm__ __volatile__ ("stmfd   sp!, {lr}");
+
+/****************************************************************************/
+/**
+* @brief	Disable the nested interrupts by setting the I and F bits. This API
+*			is defined for cortex-a9 and cortex-r5.
+*
+* @return   None.
+*
+* @note     This macro is meant to be called in the interrupt service routines.
+*			This macro cannot be used independently. It can only be used when
+*			nesting of interrupts have been enabled by using the macro
+*			Xil_EnableNestedInterrupts(). In a typical flow, the user first
+*			calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
+*			point. The user then must call this macro before exiting the interrupt
+*			service routine. This macro puts the ARM back in IRQ/FIQ mode and
+*			hence sets back the I and F bits.
+******************************************************************************/
+#define Xil_DisableNestedInterrupts() \
+		__asm__ __volatile__ ("ldmfd   sp!, {lr}");   \
+		__asm__ __volatile__ ("msr     cpsr_c, #0x92"); \
+		__asm__ __volatile__ ("ldmfd   sp!, {lr}"); \
+		__asm__ __volatile__ ("msr     spsr_cxsf, lr"); \
+		__asm__ __volatile__ ("ldmfd   sp!, {lr}"); \
+
+#endif
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
+					 Xil_ExceptionHandler Handler,
+					 void *Data);
+
+extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
+
+extern void Xil_ExceptionInit(void);
+#if defined (__aarch64__)
+void Xil_SyncAbortHandler(void *CallBackRef);
+void Xil_SErrorAbortHandler(void *CallBackRef);
+#else
+extern void Xil_DataAbortHandler(void *CallBackRef);
+extern void Xil_PrefetchAbortHandler(void *CallBackRef);
+extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_EXCEPTION_H */
+/**
+* @} End of "addtogroup arm_exception_apis".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_hal.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_hal.h
new file mode 100644
index 0000000000000000000000000000000000000000..d4434d07fa748457f2f476ebf82f9f8b20c93c91
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_hal.h
@@ -0,0 +1,61 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_hal.h
+*
+* Contains all the HAL header files.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/28/09 Initial release
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_HAL_H
+#define XIL_HAL_H
+
+#include "xil_cache.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xil_types.h"
+
+#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_io.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_io.h
new file mode 100644
index 0000000000000000000000000000000000000000..99bf4d05d92aff0610e8e442f9183c030d53f523
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_io.h
@@ -0,0 +1,345 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.h
+*
+* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
+*
+* The xil_io.h file contains the interface for the general I/O component, which
+* encapsulates the Input/Output functions for the processors that do not
+* require any special I/O handling.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 6.00  mus      08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
+*                         ARM processors
+* </pre>
+******************************************************************************/
+
+#ifndef XIL_IO_H           /* prevent circular inclusions */
+#define XIL_IO_H           /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_printf.h"
+
+#if defined (__MICROBLAZE__)
+#include "mb_interface.h"
+#else
+#include "xpseudo_asm.h"
+#endif
+
+/************************** Function Prototypes ******************************/
+u16 Xil_EndianSwap16(u16 Data);
+u32 Xil_EndianSwap32(u32 Data);
+#ifdef ENABLE_SAFETY
+extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
+#endif
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#if defined __GNUC__
+#if defined (__MICROBLAZE__)
+#  define INST_SYNC		mbar(0)
+#  define DATA_SYNC		mbar(1)
+# else
+#  define SYNCHRONIZE_IO	dmb()
+#  define INST_SYNC		isb()
+#  define DATA_SYNC		dsb()
+# endif
+#else
+# define SYNCHRONIZE_IO
+# define INST_SYNC
+# define DATA_SYNC
+# define INST_SYNC
+# define DATA_SYNC
+#endif
+
+#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
+#define INLINE inline
+#else
+#define INLINE __inline
+#endif
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an input operation for a memory location by reading
+*           from the specified address and returning the 8 bit Value read from
+*            that address.
+*
+* @param	Addr: contains the address to perform the input operation
+*
+* @return	The 8 bit Value read from the specified input address.
+
+*
+******************************************************************************/
+static INLINE u8 Xil_In8(UINTPTR Addr)
+{
+	return *(volatile u8 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an input operation for a memory location by reading from
+*           the specified address and returning the 16 bit Value read from that
+*           address.
+*
+* @param	Addr: contains the address to perform the input operation
+*
+* @return	The 16 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u16 Xil_In16(UINTPTR Addr)
+{
+	return *(volatile u16 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an input operation for a memory location by
+*           reading from the specified address and returning the 32 bit Value
+*           read  from that address.
+*
+* @param	Addr: contains the address to perform the input operation
+*
+* @return	The 32 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u32 Xil_In32(UINTPTR Addr)
+{
+	return *(volatile u32 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief     Performs an input operation for a memory location by reading the
+*            64 bit Value read  from that address.
+*
+*
+* @param	Addr: contains the address to perform the input operation
+*
+* @return	The 64 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u64 Xil_In64(UINTPTR Addr)
+{
+	return *(volatile u64 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an output operation for an memory location by
+*           writing the 8 bit Value to the the specified address.
+*
+* @param	Addr: contains the address to perform the output operation
+* @param	Value: contains the 8 bit Value to be written at the specified
+*           address.
+*
+* @return	None.
+*
+******************************************************************************/
+static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
+{
+	volatile u8 *LocalAddr = (volatile u8 *)Addr;
+	*LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an output operation for a memory location by writing the
+*            16 bit Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+* @param	Value contains the Value to be written at the specified address.
+*
+* @return	None.
+*
+******************************************************************************/
+static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
+{
+	volatile u16 *LocalAddr = (volatile u16 *)Addr;
+	*LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an output operation for a memory location by writing the
+*           32 bit Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+* @param	Value contains the 32 bit Value to be written at the specified
+*           address.
+*
+* @return	None.
+*
+******************************************************************************/
+static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
+{
+#ifndef ENABLE_SAFETY
+	volatile u32 *LocalAddr = (volatile u32 *)Addr;
+	*LocalAddr = Value;
+#else
+	XStl_RegUpdate(Addr, Value);
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an output operation for a memory location by writing the
+*           64 bit Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+* @param	Value contains 64 bit Value to be written at the specified address.
+*
+* @return	None.
+*
+******************************************************************************/
+static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
+{
+	volatile u64 *LocalAddr = (volatile u64 *)Addr;
+	*LocalAddr = Value;
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+# define Xil_In16LE	Xil_In16
+# define Xil_In32LE	Xil_In32
+# define Xil_Out16LE	Xil_Out16
+# define Xil_Out32LE	Xil_Out32
+# define Xil_Htons	Xil_EndianSwap16
+# define Xil_Htonl	Xil_EndianSwap32
+# define Xil_Ntohs	Xil_EndianSwap16
+# define Xil_Ntohl	Xil_EndianSwap32
+# else
+# define Xil_In16BE	Xil_In16
+# define Xil_In32BE	Xil_In32
+# define Xil_Out16BE	Xil_Out16
+# define Xil_Out32BE	Xil_Out32
+# define Xil_Htons(Data) (Data)
+# define Xil_Htonl(Data) (Data)
+# define Xil_Ntohs(Data) (Data)
+# define Xil_Ntohl(Data) (Data)
+#endif
+#else
+# define Xil_In16LE	Xil_In16
+# define Xil_In32LE	Xil_In32
+# define Xil_Out16LE	Xil_Out16
+# define Xil_Out32LE	Xil_Out32
+# define Xil_Htons	Xil_EndianSwap16
+# define Xil_Htonl	Xil_EndianSwap32
+# define Xil_Ntohs	Xil_EndianSwap16
+# define Xil_Ntohl	Xil_EndianSwap32
+#endif
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#else
+static INLINE u16 Xil_In16LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#endif
+{
+	u16 value = Xil_In16(Addr);
+	return Xil_EndianSwap16(value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#else
+static INLINE u32 Xil_In32LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#endif
+{
+	u16 value = Xil_In32(Addr);
+	return Xil_EndianSwap32(value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#else
+static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
+#endif
+#else
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#endif
+{
+	Value = Xil_EndianSwap16(Value);
+	Xil_Out16(Addr, Value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#else
+static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
+#endif
+#else
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#endif
+{
+	Value = Xil_EndianSwap32(Value);
+	Xil_Out32(Addr, Value);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_io_interfacing_apis".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_macroback.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_macroback.h
new file mode 100644
index 0000000000000000000000000000000000000000..ebafde87d7ff8a38bd28724a08ecca7701ea4f58
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_macroback.h
@@ -0,0 +1,1052 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*********************************************************************/
+/**
+ * @file xil_macroback.h
+ *
+ * This header file is meant to bring back the removed _m macros.
+ * This header file must be included last.
+ * The following macros are not defined here due to the driver change:
+ *   XGpio_mSetDataDirection
+ *   XGpio_mGetDataReg
+ *   XGpio_mSetDataReg
+ *   XIIC_RESET
+ *   XIIC_CLEAR_STATS
+ *   XSpi_mReset
+ *   XSysAce_mSetCfgAddr
+ *   XSysAce_mIsCfgDone
+ *   XTft_mSetPixel
+ *   XTft_mGetPixel
+ *   XWdtTb_mEnableWdt
+ *   XWdtTb_mDisbleWdt
+ *   XWdtTb_mRestartWdt
+ *   XWdtTb_mGetTimebaseReg
+ *   XWdtTb_mHasReset
+ *
+ * Please refer the corresonding driver document for replacement.
+ *
+ *********************************************************************/
+
+#ifndef XIL_MACROBACK_H
+#define XIL_MACROBACK_H
+
+/*********************************************************************/
+/**
+ * Macros for Driver XCan
+ *
+ *********************************************************************/
+#ifndef XCan_mReadReg
+#define XCan_mReadReg XCan_ReadReg
+#endif
+
+#ifndef XCan_mWriteReg
+#define XCan_mWriteReg XCan_WriteReg
+#endif
+
+#ifndef XCan_mIsTxDone
+#define XCan_mIsTxDone XCan_IsTxDone
+#endif
+
+#ifndef XCan_mIsTxFifoFull
+#define XCan_mIsTxFifoFull XCan_IsTxFifoFull
+#endif
+
+#ifndef XCan_mIsHighPriorityBufFull
+#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull
+#endif
+
+#ifndef XCan_mIsRxEmpty
+#define XCan_mIsRxEmpty XCan_IsRxEmpty
+#endif
+
+#ifndef XCan_mIsAcceptFilterBusy
+#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy
+#endif
+
+#ifndef XCan_mCreateIdValue
+#define XCan_mCreateIdValue XCan_CreateIdValue
+#endif
+
+#ifndef XCan_mCreateDlcValue
+#define XCan_mCreateDlcValue XCan_CreateDlcValue
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDmaCentral
+ *
+ *********************************************************************/
+#ifndef XDmaCentral_mWriteReg
+#define XDmaCentral_mWriteReg XDmaCentral_WriteReg
+#endif
+
+#ifndef XDmaCentral_mReadReg
+#define XDmaCentral_mReadReg XDmaCentral_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsAdc
+ *
+ *********************************************************************/
+#ifndef XDsAdc_mWriteReg
+#define XDsAdc_mWriteReg XDsAdc_WriteReg
+#endif
+
+#ifndef XDsAdc_mReadReg
+#define XDsAdc_mReadReg XDsAdc_ReadReg
+#endif
+
+#ifndef XDsAdc_mIsEmpty
+#define XDsAdc_mIsEmpty XDsAdc_IsEmpty
+#endif
+
+#ifndef XDsAdc_mSetFstmReg
+#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg
+#endif
+
+#ifndef XDsAdc_mGetFstmReg
+#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg
+#endif
+
+#ifndef XDsAdc_mEnableConversion
+#define XDsAdc_mEnableConversion XDsAdc_EnableConversion
+#endif
+
+#ifndef XDsAdc_mDisableConversion
+#define XDsAdc_mDisableConversion XDsAdc_DisableConversion
+#endif
+
+#ifndef XDsAdc_mGetFifoOccyReg
+#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsDac
+ *
+ *********************************************************************/
+#ifndef XDsDac_mWriteReg
+#define XDsDac_mWriteReg XDsDac_WriteReg
+#endif
+
+#ifndef XDsDac_mReadReg
+#define XDsDac_mReadReg XDsDac_ReadReg
+#endif
+
+#ifndef XDsDac_mIsEmpty
+#define XDsDac_mIsEmpty XDsDac_IsEmpty
+#endif
+
+#ifndef XDsDac_mFifoIsFull
+#define XDsDac_mFifoIsFull XDsDac_FifoIsFull
+#endif
+
+#ifndef XDsDac_mGetVacancy
+#define XDsDac_mGetVacancy XDsDac_GetVacancy
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XEmacLite
+ *
+ *********************************************************************/
+#ifndef XEmacLite_mReadReg
+#define XEmacLite_mReadReg XEmacLite_ReadReg
+#endif
+
+#ifndef XEmacLite_mWriteReg
+#define XEmacLite_mWriteReg XEmacLite_WriteReg
+#endif
+
+#ifndef XEmacLite_mGetTxStatus
+#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus
+#endif
+
+#ifndef XEmacLite_mSetTxStatus
+#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus
+#endif
+
+#ifndef XEmacLite_mGetRxStatus
+#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus
+#endif
+
+#ifndef XEmacLite_mSetRxStatus
+#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus
+#endif
+
+#ifndef XEmacLite_mIsTxDone
+#define XEmacLite_mIsTxDone XEmacLite_IsTxDone
+#endif
+
+#ifndef XEmacLite_mIsRxEmpty
+#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty
+#endif
+
+#ifndef XEmacLite_mNextTransmitAddr
+#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr
+#endif
+
+#ifndef XEmacLite_mNextReceiveAddr
+#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr
+#endif
+
+#ifndef XEmacLite_mIsMdioConfigured
+#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured
+#endif
+
+#ifndef XEmacLite_mIsLoopbackConfigured
+#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured
+#endif
+
+#ifndef XEmacLite_mGetReceiveDataLength
+#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength
+#endif
+
+#ifndef XEmacLite_mGetTxActive
+#define XEmacLite_mGetTxActive XEmacLite_GetTxActive
+#endif
+
+#ifndef XEmacLite_mSetTxActive
+#define XEmacLite_mSetTxActive XEmacLite_SetTxActive
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XGpio
+ *
+ *********************************************************************/
+#ifndef XGpio_mWriteReg
+#define XGpio_mWriteReg XGpio_WriteReg
+#endif
+
+#ifndef XGpio_mReadReg
+#define XGpio_mReadReg XGpio_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XHwIcap
+ *
+ *********************************************************************/
+#ifndef XHwIcap_mFifoWrite
+#define XHwIcap_mFifoWrite XHwIcap_FifoWrite
+#endif
+
+#ifndef XHwIcap_mFifoRead
+#define XHwIcap_mFifoRead XHwIcap_FifoRead
+#endif
+
+#ifndef XHwIcap_mSetSizeReg
+#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg
+#endif
+
+#ifndef XHwIcap_mGetControlReg
+#define XHwIcap_mGetControlReg XHwIcap_GetControlReg
+#endif
+
+#ifndef XHwIcap_mStartConfig
+#define XHwIcap_mStartConfig XHwIcap_StartConfig
+#endif
+
+#ifndef XHwIcap_mStartReadBack
+#define XHwIcap_mStartReadBack XHwIcap_StartReadBack
+#endif
+
+#ifndef XHwIcap_mGetStatusReg
+#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg
+#endif
+
+#ifndef XHwIcap_mIsTransferDone
+#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone
+#endif
+
+#ifndef XHwIcap_mIsDeviceBusy
+#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy
+#endif
+
+#ifndef XHwIcap_mIntrGlobalEnable
+#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable
+#endif
+
+#ifndef XHwIcap_mIntrGlobalDisable
+#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable
+#endif
+
+#ifndef XHwIcap_mIntrGetStatus
+#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus
+#endif
+
+#ifndef XHwIcap_mIntrDisable
+#define XHwIcap_mIntrDisable XHwIcap_IntrDisable
+#endif
+
+#ifndef XHwIcap_mIntrEnable
+#define XHwIcap_mIntrEnable XHwIcap_IntrEnable
+#endif
+
+#ifndef XHwIcap_mIntrGetEnabled
+#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled
+#endif
+
+#ifndef XHwIcap_mIntrClear
+#define XHwIcap_mIntrClear XHwIcap_IntrClear
+#endif
+
+#ifndef XHwIcap_mGetWrFifoVacancy
+#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy
+#endif
+
+#ifndef XHwIcap_mGetRdFifoOccupancy
+#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy
+#endif
+
+#ifndef XHwIcap_mSliceX2Col
+#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col
+#endif
+
+#ifndef XHwIcap_mSliceY2Row
+#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row
+#endif
+
+#ifndef XHwIcap_mSliceXY2Slice
+#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice
+#endif
+
+#ifndef XHwIcap_mReadReg
+#define XHwIcap_mReadReg XHwIcap_ReadReg
+#endif
+
+#ifndef XHwIcap_mWriteReg
+#define XHwIcap_mWriteReg XHwIcap_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIic
+ *
+ *********************************************************************/
+#ifndef XIic_mReadReg
+#define XIic_mReadReg XIic_ReadReg
+#endif
+
+#ifndef XIic_mWriteReg
+#define XIic_mWriteReg XIic_WriteReg
+#endif
+
+#ifndef XIic_mEnterCriticalRegion
+#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIic_mExitCriticalRegion
+#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_GINTR_DISABLE
+#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIIC_GINTR_ENABLE
+#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_IS_GINTR_ENABLED
+#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled
+#endif
+
+#ifndef XIIC_WRITE_IISR
+#define XIIC_WRITE_IISR XIic_WriteIisr
+#endif
+
+#ifndef XIIC_READ_IISR
+#define XIIC_READ_IISR XIic_ReadIisr
+#endif
+
+#ifndef XIIC_WRITE_IIER
+#define XIIC_WRITE_IIER XIic_WriteIier
+#endif
+
+#ifndef XIic_mClearIisr
+#define XIic_mClearIisr XIic_ClearIisr
+#endif
+
+#ifndef XIic_mSend7BitAddress
+#define XIic_mSend7BitAddress XIic_Send7BitAddress
+#endif
+
+#ifndef XIic_mDynSend7BitAddress
+#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress
+#endif
+
+#ifndef XIic_mDynSendStartStopAddress
+#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress
+#endif
+
+#ifndef XIic_mDynSendStop
+#define XIic_mDynSendStop XIic_DynSendStop
+#endif
+
+#ifndef XIic_mSend10BitAddrByte1
+#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1
+#endif
+
+#ifndef XIic_mSend10BitAddrByte2
+#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2
+#endif
+
+#ifndef XIic_mSend7BitAddr
+#define XIic_mSend7BitAddr XIic_Send7BitAddr
+#endif
+
+#ifndef XIic_mDisableIntr
+#define XIic_mDisableIntr XIic_DisableIntr
+#endif
+
+#ifndef XIic_mEnableIntr
+#define XIic_mEnableIntr XIic_EnableIntr
+#endif
+
+#ifndef XIic_mClearIntr
+#define XIic_mClearIntr XIic_ClearIntr
+#endif
+
+#ifndef XIic_mClearEnableIntr
+#define XIic_mClearEnableIntr XIic_ClearEnableIntr
+#endif
+
+#ifndef XIic_mFlushRxFifo
+#define XIic_mFlushRxFifo XIic_FlushRxFifo
+#endif
+
+#ifndef XIic_mFlushTxFifo
+#define XIic_mFlushTxFifo XIic_FlushTxFifo
+#endif
+
+#ifndef XIic_mReadRecvByte
+#define XIic_mReadRecvByte XIic_ReadRecvByte
+#endif
+
+#ifndef XIic_mWriteSendByte
+#define XIic_mWriteSendByte XIic_WriteSendByte
+#endif
+
+#ifndef XIic_mSetControlRegister
+#define XIic_mSetControlRegister XIic_SetControlRegister
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIntc
+ *
+ *********************************************************************/
+#ifndef XIntc_mMasterEnable
+#define XIntc_mMasterEnable XIntc_MasterEnable
+#endif
+
+#ifndef XIntc_mMasterDisable
+#define XIntc_mMasterDisable XIntc_MasterDisable
+#endif
+
+#ifndef XIntc_mEnableIntr
+#define XIntc_mEnableIntr XIntc_EnableIntr
+#endif
+
+#ifndef XIntc_mDisableIntr
+#define XIntc_mDisableIntr XIntc_DisableIntr
+#endif
+
+#ifndef XIntc_mAckIntr
+#define XIntc_mAckIntr XIntc_AckIntr
+#endif
+
+#ifndef XIntc_mGetIntrStatus
+#define XIntc_mGetIntrStatus XIntc_GetIntrStatus
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XLlDma
+ *
+ *********************************************************************/
+#ifndef XLlDma_mBdRead
+#define XLlDma_mBdRead XLlDma_BdRead
+#endif
+
+#ifndef XLlDma_mBdWrite
+#define XLlDma_mBdWrite XLlDma_BdWrite
+#endif
+
+#ifndef XLlDma_mWriteReg
+#define XLlDma_mWriteReg XLlDma_WriteReg
+#endif
+
+#ifndef XLlDma_mReadReg
+#define XLlDma_mReadReg XLlDma_ReadReg
+#endif
+
+#ifndef XLlDma_mBdClear
+#define XLlDma_mBdClear XLlDma_BdClear
+#endif
+
+#ifndef XLlDma_mBdSetStsCtrl
+#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdGetStsCtrl
+#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdSetLength
+#define XLlDma_mBdSetLength XLlDma_BdSetLength
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mBdSetId
+#define XLlDma_mBdSetId XLlDma_BdSetId
+#endif
+
+#ifndef XLlDma_mBdGetId
+#define XLlDma_mBdGetId XLlDma_BdGetId
+#endif
+
+#ifndef XLlDma_mBdSetBufAddr
+#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetBufAddr
+#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mGetTxRing
+#define XLlDma_mGetTxRing XLlDma_GetTxRing
+#endif
+
+#ifndef XLlDma_mGetRxRing
+#define XLlDma_mGetRxRing XLlDma_GetRxRing
+#endif
+
+#ifndef XLlDma_mGetCr
+#define XLlDma_mGetCr XLlDma_GetCr
+#endif
+
+#ifndef XLlDma_mSetCr
+#define XLlDma_mSetCr XLlDma_SetCr
+#endif
+
+#ifndef XLlDma_mBdRingCntCalc
+#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc
+#endif
+
+#ifndef XLlDma_mBdRingMemCalc
+#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc
+#endif
+
+#ifndef XLlDma_mBdRingGetCnt
+#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt
+#endif
+
+#ifndef XLlDma_mBdRingGetFreeCnt
+#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt
+#endif
+
+#ifndef XLlDma_mBdRingSnapShotCurrBd
+#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd
+#endif
+
+#ifndef XLlDma_mBdRingNext
+#define XLlDma_mBdRingNext XLlDma_BdRingNext
+#endif
+
+#ifndef XLlDma_mBdRingPrev
+#define XLlDma_mBdRingPrev XLlDma_BdRingPrev
+#endif
+
+#ifndef XLlDma_mBdRingGetSr
+#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr
+#endif
+
+#ifndef XLlDma_mBdRingSetSr
+#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr
+#endif
+
+#ifndef XLlDma_mBdRingGetCr
+#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr
+#endif
+
+#ifndef XLlDma_mBdRingSetCr
+#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr
+#endif
+
+#ifndef XLlDma_mBdRingBusy
+#define XLlDma_mBdRingBusy XLlDma_BdRingBusy
+#endif
+
+#ifndef XLlDma_mBdRingIntEnable
+#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable
+#endif
+
+#ifndef XLlDma_mBdRingIntDisable
+#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable
+#endif
+
+#ifndef XLlDma_mBdRingIntGetEnabled
+#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled
+#endif
+
+#ifndef XLlDma_mBdRingGetIrq
+#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq
+#endif
+
+#ifndef XLlDma_mBdRingAckIrq
+#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMbox
+ *
+ *********************************************************************/
+#ifndef XMbox_mWriteReg
+#define XMbox_mWriteReg XMbox_WriteReg
+#endif
+
+#ifndef XMbox_mReadReg
+#define XMbox_mReadReg XMbox_ReadReg
+#endif
+
+#ifndef XMbox_mWriteMBox
+#define XMbox_mWriteMBox XMbox_WriteMBox
+#endif
+
+#ifndef XMbox_mReadMBox
+#define XMbox_mReadMBox XMbox_ReadMBox
+#endif
+
+#ifndef XMbox_mFSLReadMBox
+#define XMbox_mFSLReadMBox XMbox_FSLReadMBox
+#endif
+
+#ifndef XMbox_mFSLWriteMBox
+#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox
+#endif
+
+#ifndef XMbox_mFSLIsEmpty
+#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty
+#endif
+
+#ifndef XMbox_mFSLIsFull
+#define XMbox_mFSLIsFull XMbox_FSLIsFull
+#endif
+
+#ifndef XMbox_mIsEmpty
+#define XMbox_mIsEmpty XMbox_IsEmptyHw
+#endif
+
+#ifndef XMbox_mIsFull
+#define XMbox_mIsFull XMbox_IsFullHw
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMpmc
+ *
+ *********************************************************************/
+#ifndef XMpmc_mReadReg
+#define XMpmc_mReadReg XMpmc_ReadReg
+#endif
+
+#ifndef XMpmc_mWriteReg
+#define XMpmc_mWriteReg XMpmc_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMutex
+ *
+ *********************************************************************/
+#ifndef XMutex_mWriteReg
+#define XMutex_mWriteReg XMutex_WriteReg
+#endif
+
+#ifndef XMutex_mReadReg
+#define XMutex_mReadReg XMutex_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XPcie
+ *
+ *********************************************************************/
+#ifndef XPcie_mReadReg
+#define XPcie_mReadReg XPcie_ReadReg
+#endif
+
+#ifndef XPcie_mWriteReg
+#define XPcie_mWriteReg XPcie_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSpi
+ *
+ *********************************************************************/
+#ifndef XSpi_mIntrGlobalEnable
+#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable
+#endif
+
+#ifndef XSpi_mIntrGlobalDisable
+#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable
+#endif
+
+#ifndef XSpi_mIsIntrGlobalEnabled
+#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled
+#endif
+
+#ifndef XSpi_mIntrGetStatus
+#define XSpi_mIntrGetStatus XSpi_IntrGetStatus
+#endif
+
+#ifndef XSpi_mIntrClear
+#define XSpi_mIntrClear XSpi_IntrClear
+#endif
+
+#ifndef XSpi_mIntrEnable
+#define XSpi_mIntrEnable XSpi_IntrEnable
+#endif
+
+#ifndef XSpi_mIntrDisable
+#define XSpi_mIntrDisable XSpi_IntrDisable
+#endif
+
+#ifndef XSpi_mIntrGetEnabled
+#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled
+#endif
+
+#ifndef XSpi_mSetControlReg
+#define XSpi_mSetControlReg XSpi_SetControlReg
+#endif
+
+#ifndef XSpi_mGetControlReg
+#define XSpi_mGetControlReg XSpi_GetControlReg
+#endif
+
+#ifndef XSpi_mGetStatusReg
+#define XSpi_mGetStatusReg XSpi_GetStatusReg
+#endif
+
+#ifndef XSpi_mSetSlaveSelectReg
+#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mGetSlaveSelectReg
+#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mEnable
+#define XSpi_mEnable XSpi_Enable
+#endif
+
+#ifndef XSpi_mDisable
+#define XSpi_mDisable XSpi_Disable
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysAce
+ *
+ *********************************************************************/
+#ifndef XSysAce_mGetControlReg
+#define XSysAce_mGetControlReg XSysAce_GetControlReg
+#endif
+
+#ifndef XSysAce_mSetControlReg
+#define XSysAce_mSetControlReg XSysAce_SetControlReg
+#endif
+
+#ifndef XSysAce_mOrControlReg
+#define XSysAce_mOrControlReg XSysAce_OrControlReg
+#endif
+
+#ifndef XSysAce_mAndControlReg
+#define XSysAce_mAndControlReg XSysAce_AndControlReg
+#endif
+
+#ifndef XSysAce_mGetErrorReg
+#define XSysAce_mGetErrorReg XSysAce_GetErrorReg
+#endif
+
+#ifndef XSysAce_mGetStatusReg
+#define XSysAce_mGetStatusReg XSysAce_GetStatusReg
+#endif
+
+#ifndef XSysAce_mWaitForLock
+#define XSysAce_mWaitForLock XSysAce_WaitForLock
+#endif
+
+#ifndef XSysAce_mEnableIntr
+#define XSysAce_mEnableIntr XSysAce_EnableIntr
+#endif
+
+#ifndef XSysAce_mDisableIntr
+#define XSysAce_mDisableIntr XSysAce_DisableIntr
+#endif
+
+#ifndef XSysAce_mIsReadyForCmd
+#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd
+#endif
+
+#ifndef XSysAce_mIsMpuLocked
+#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked
+#endif
+
+#ifndef XSysAce_mIsIntrEnabled
+#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysMon
+ *
+ *********************************************************************/
+#ifndef XSysMon_mIsEventSamplingModeSet
+#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet
+#endif
+
+#ifndef XSysMon_mIsDrpBusy
+#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy
+#endif
+
+#ifndef XSysMon_mIsDrpLocked
+#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked
+#endif
+
+#ifndef XSysMon_mRawToTemperature
+#define XSysMon_mRawToTemperature XSysMon_RawToTemperature
+#endif
+
+#ifndef XSysMon_mRawToVoltage
+#define XSysMon_mRawToVoltage XSysMon_RawToVoltage
+#endif
+
+#ifndef XSysMon_mTemperatureToRaw
+#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw
+#endif
+
+#ifndef XSysMon_mVoltageToRaw
+#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw
+#endif
+
+#ifndef XSysMon_mReadReg
+#define XSysMon_mReadReg XSysMon_ReadReg
+#endif
+
+#ifndef XSysMon_mWriteReg
+#define XSysMon_mWriteReg XSysMon_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XTmrCtr
+ *
+ *********************************************************************/
+#ifndef XTimerCtr_mReadReg
+#define XTimerCtr_mReadReg XTimerCtr_ReadReg
+#endif
+
+#ifndef XTmrCtr_mWriteReg
+#define XTmrCtr_mWriteReg XTmrCtr_WriteReg
+#endif
+
+#ifndef XTmrCtr_mSetControlStatusReg
+#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetControlStatusReg
+#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetTimerCounterReg
+#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mSetLoadReg
+#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg
+#endif
+
+#ifndef XTmrCtr_mGetLoadReg
+#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg
+#endif
+
+#ifndef XTmrCtr_mEnable
+#define XTmrCtr_mEnable XTmrCtr_Enable
+#endif
+
+#ifndef XTmrCtr_mDisable
+#define XTmrCtr_mDisable XTmrCtr_Disable
+#endif
+
+#ifndef XTmrCtr_mEnableIntr
+#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr
+#endif
+
+#ifndef XTmrCtr_mDisableIntr
+#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr
+#endif
+
+#ifndef XTmrCtr_mLoadTimerCounterReg
+#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mHasEventOccurred
+#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartLite
+ *
+ *********************************************************************/
+#ifndef XUartLite_mUpdateStats
+#define XUartLite_mUpdateStats XUartLite_UpdateStats
+#endif
+
+#ifndef XUartLite_mWriteReg
+#define XUartLite_mWriteReg XUartLite_WriteReg
+#endif
+
+#ifndef XUartLite_mReadReg
+#define XUartLite_mReadReg XUartLite_ReadReg
+#endif
+
+#ifndef XUartLite_mClearStats
+#define XUartLite_mClearStats XUartLite_ClearStats
+#endif
+
+#ifndef XUartLite_mSetControlReg
+#define XUartLite_mSetControlReg XUartLite_SetControlReg
+#endif
+
+#ifndef XUartLite_mGetStatusReg
+#define XUartLite_mGetStatusReg XUartLite_GetStatusReg
+#endif
+
+#ifndef XUartLite_mIsReceiveEmpty
+#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty
+#endif
+
+#ifndef XUartLite_mIsTransmitFull
+#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull
+#endif
+
+#ifndef XUartLite_mIsIntrEnabled
+#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled
+#endif
+
+#ifndef XUartLite_mEnableIntr
+#define XUartLite_mEnableIntr XUartLite_EnableIntr
+#endif
+
+#ifndef XUartLite_mDisableIntr
+#define XUartLite_mDisableIntr XUartLite_DisableIntr
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartNs550
+ *
+ *********************************************************************/
+#ifndef XUartNs550_mUpdateStats
+#define XUartNs550_mUpdateStats XUartNs550_UpdateStats
+#endif
+
+#ifndef XUartNs550_mReadReg
+#define XUartNs550_mReadReg XUartNs550_ReadReg
+#endif
+
+#ifndef XUartNs550_mWriteReg
+#define XUartNs550_mWriteReg XUartNs550_WriteReg
+#endif
+
+#ifndef XUartNs550_mClearStats
+#define XUartNs550_mClearStats XUartNs550_ClearStats
+#endif
+
+#ifndef XUartNs550_mGetLineStatusReg
+#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg
+#endif
+
+#ifndef XUartNs550_mGetLineControlReg
+#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg
+#endif
+
+#ifndef XUartNs550_mSetLineControlReg
+#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg
+#endif
+
+#ifndef XUartNs550_mEnableIntr
+#define XUartNs550_mEnableIntr XUartNs550_EnableIntr
+#endif
+
+#ifndef XUartNs550_mDisableIntr
+#define XUartNs550_mDisableIntr XUartNs550_DisableIntr
+#endif
+
+#ifndef XUartNs550_mIsReceiveData
+#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData
+#endif
+
+#ifndef XUartNs550_mIsTransmitEmpty
+#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUsb
+ *
+ *********************************************************************/
+#ifndef XUsb_mReadReg
+#define XUsb_mReadReg XUsb_ReadReg
+#endif
+
+#ifndef XUsb_mWriteReg
+#define XUsb_mWriteReg XUsb_WriteReg
+#endif
+
+#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_mem.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_mem.h
new file mode 100644
index 0000000000000000000000000000000000000000..a2d5e6681d9b82f40e81baa106789d512da27f6b
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_mem.h
@@ -0,0 +1,59 @@
+/******************************************************************************/
+/**
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* @file xil_mem.h
+*
+* @addtogroup common_mem_operation_api Customized APIs for Memory Operations
+*
+* The xil_mem.h file contains prototype for functions related
+* to memory operations. These APIs are applicable for all processors supported
+* by Xilinx.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.1   nsk      11/07/16 First release.
+*
+* </pre>
+*
+*****************************************************************************/
+
+/************************** Function Prototypes *****************************/
+
+void Xil_MemCpy(void* dst, const void* src, u32 cnt);
+/**
+* @} End of "addtogroup common_mem_operation_api".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_misc_psreset_api.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_misc_psreset_api.h
new file mode 100644
index 0000000000000000000000000000000000000000..c228c988eb3035912db6e0d906d41609afac4b38
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_misc_psreset_api.h
@@ -0,0 +1,277 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_misc_psreset_api.h
+*
+* This file contains the various register defintions and function prototypes for
+* implementing the reset functionality of zynq ps devices
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00b kpc   03/07/13 First release.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_MISC_RESET_H		/* prevent circular inclusions */
+#define XIL_MISC_RESET_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+#define XDDRC_CTRL_BASEADDR				0xF8006000U
+#define XSLCR_BASEADDR					0xF8000000U
+/**< OCM configuration register */
+#define XSLCR_OCM_CFG_ADDR				(XSLCR_BASEADDR + 0x00000910U)
+/**< SLCR unlock register */
+#define XSLCR_UNLOCK_ADDR				(XSLCR_BASEADDR + 0x00000008U)
+/**< SLCR GEM0 rx clock control register */
+#define XSLCR_GEM0_RCLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x00000138U)
+/**< SLCR GEM1 rx clock control register */
+#define XSLCR_GEM1_RCLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x0000013CU)
+/**< SLCR GEM0 clock control register */
+#define XSLCR_GEM0_CLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x00000140U)
+/**< SLCR GEM1 clock control register */
+#define XSLCR_GEM1_CLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x00000144U)
+/**< SLCR SMC clock control register */
+#define XSLCR_SMC_CLK_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000148U)
+/**< SLCR GEM reset control register */
+#define XSLCR_GEM_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000214U)
+/**< SLCR USB0 clock control register */
+#define XSLCR_USB0_CLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x00000130U)
+/**< SLCR USB1 clock control register */
+#define XSLCR_USB1_CLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x00000134U)
+/**< SLCR USB1 reset control register */
+#define XSLCR_USB_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000210U)
+/**< SLCR SMC reset control register */
+#define XSLCR_SMC_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000234U)
+/**< SLCR Level shifter enable register */
+#define XSLCR_LVL_SHFTR_EN_ADDR			(XSLCR_BASEADDR + 0x00000900U)
+/**< SLCR ARM pll control register */
+#define XSLCR_ARM_PLL_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000100U)
+/**< SLCR DDR pll control register */
+#define XSLCR_DDR_PLL_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000104U)
+/**< SLCR IO pll control register */
+#define XSLCR_IO_PLL_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000108U)
+/**< SLCR ARM pll configuration register */
+#define XSLCR_ARM_PLL_CFG_ADDR			(XSLCR_BASEADDR + 0x00000110U)
+/**< SLCR DDR pll configuration register */
+#define XSLCR_DDR_PLL_CFG_ADDR			(XSLCR_BASEADDR + 0x00000114U)
+/**< SLCR IO pll configuration register */
+#define XSLCR_IO_PLL_CFG_ADDR			(XSLCR_BASEADDR + 0x00000118U)
+/**< SLCR ARM clock control register */
+#define XSLCR_ARM_CLK_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000120U)
+/**< SLCR DDR clock control register */
+#define XSLCR_DDR_CLK_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000124U)
+/**< SLCR MIO pin address register */
+#define XSLCR_MIO_PIN_00_ADDR			(XSLCR_BASEADDR + 0x00000700U)
+/**< SLCR DMAC reset control address register */
+#define XSLCR_DMAC_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x0000020CU)
+/**< SLCR USB reset control address register */
+/*#define XSLCR_USB_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000210U)*/
+/**< SLCR GEM reset control address register */
+/*#define XSLCR_GEM_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000214U)*/
+/**< SLCR SDIO reset control address register */
+#define XSLCR_SDIO_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000218U)
+/**< SLCR SPI reset control address register */
+#define XSLCR_SPI_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x0000021CU)
+/**< SLCR CAN reset control address register */
+#define XSLCR_CAN_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000220U)
+/**< SLCR I2C reset control address register */
+#define XSLCR_I2C_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000224U)
+/**< SLCR UART reset control address register */
+#define XSLCR_UART_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000228U)
+/**< SLCR GPIO reset control address register */
+#define XSLCR_GPIO_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x0000022CU)
+/**< SLCR LQSPI reset control address register */
+#define XSLCR_LQSPI_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000230U)
+/**< SLCR SMC reset control address register */
+/*#define XSLCR_SMC_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000234U)*/
+/**< SLCR OCM reset control address register */
+#define XSLCR_OCM_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000238U)
+
+/**< SMC mem controller clear config register */
+#define XSMC_MEMC_CLR_CONFIG_OFFSET			0x0000000CU
+/**< SMC idlecount configuration register */
+#define XSMC_REFRESH_PERIOD_0_OFFSET		0x00000020U
+#define XSMC_REFRESH_PERIOD_1_OFFSET		0x00000024U
+/**< SMC ECC configuration register */
+#define XSMC_ECC_MEMCFG1_OFFSET				0x00000404U
+/**< SMC ECC command 1 register */
+#define XSMC_ECC_MEMCMD1_OFFSET				0x00000404U
+/**< SMC ECC command 2 register */
+#define XSMC_ECC_MEMCMD2_OFFSET				0x00000404U
+
+/**< SLCR unlock code */
+#define XSLCR_UNLOCK_CODE		0x0000DF0DU
+
+/**< SMC mem clear configuration mask */
+#define XSMC_MEMC_CLR_CONFIG_MASK 	0x000005FU
+/**< SMC ECC memconfig 1 reset value */
+#define XSMC_ECC_MEMCFG1_RESET_VAL 	0x0000043U
+/**< SMC ECC memcommand 1 reset value */
+#define XSMC_ECC_MEMCMD1_RESET_VAL 	0x01300080U
+/**< SMC ECC memcommand 2 reset value */
+#define XSMC_ECC_MEMCMD2_RESET_VAL 	0x01E00585U
+
+/**< DDR controller reset bit mask */
+#define XDDRPS_CTRL_RESET_MASK 		0x00000001U
+/**< SLCR OCM configuration reset value*/
+#define XSLCR_OCM_CFG_RESETVAL		0x00000008U
+/**< SLCR OCM bank selection mask*/
+#define XSLCR_OCM_CFG_HIADDR_MASK	0x0000000FU
+/**< SLCR level shifter enable mask*/
+#define XSLCR_LVL_SHFTR_EN_MASK		0x0000000FU
+
+/**< SLCR PLL register reset values */
+#define XSLCR_ARM_PLL_CTRL_RESET_VAL	0x0001A008U
+#define XSLCR_DDR_PLL_CTRL_RESET_VAL	0x0001A008U
+#define XSLCR_IO_PLL_CTRL_RESET_VAL		0x0001A008U
+#define XSLCR_ARM_PLL_CFG_RESET_VAL		0x00177EA0U
+#define XSLCR_DDR_PLL_CFG_RESET_VAL		0x00177EA0U
+#define XSLCR_IO_PLL_CFG_RESET_VAL		0x00177EA0U
+#define XSLCR_ARM_CLK_CTRL_RESET_VAL	0x1F000400U
+#define XSLCR_DDR_CLK_CTRL_RESET_VAL	0x18400003U
+
+/**< SLCR MIO register default values */
+#define XSLCR_MIO_PIN_00_RESET_VAL		0x00001601U
+#define XSLCR_MIO_PIN_02_RESET_VAL		0x00000601U
+
+/**< SLCR Reset control registers default values */
+#define XSLCR_DMAC_RST_CTRL_VAL			0x00000001U
+#define XSLCR_GEM_RST_CTRL_VAL			0x000000F3U
+#define XSLCR_USB_RST_CTRL_VAL			0x00000003U
+#define XSLCR_I2C_RST_CTRL_VAL			0x00000003U
+#define XSLCR_SPI_RST_CTRL_VAL			0x0000000FU
+#define XSLCR_UART_RST_CTRL_VAL			0x0000000FU
+#define XSLCR_QSPI_RST_CTRL_VAL			0x00000003U
+#define XSLCR_GPIO_RST_CTRL_VAL			0x00000001U
+#define XSLCR_SMC_RST_CTRL_VAL			0x00000003U
+#define XSLCR_OCM_RST_CTRL_VAL			0x00000001U
+#define XSLCR_SDIO_RST_CTRL_VAL			0x00000033U
+#define XSLCR_CAN_RST_CTRL_VAL			0x00000003U
+/**************************** Type Definitions *******************************/
+
+/* the following data type is used to hold a null terminated version string
+ * consisting of the following format, "X.YYX"
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+/*
+ * Performs reset operation to the ddr interface
+ */
+void XDdr_ResetHw(void);
+/*
+ * Map the ocm region to post bootrom state
+ */
+void XOcm_Remap(void);
+/*
+ * Performs the smc interface reset
+ */
+void XSmc_ResetHw(u32 BaseAddress);
+/*
+ * updates the MIO registers with reset values
+ */
+void XSlcr_MioWriteResetValues(void);
+/*
+ * updates the PLL and clock registers with reset values
+ */
+void XSlcr_PllWriteResetValues(void);
+/*
+ * Disables the level shifters
+ */
+void XSlcr_DisableLevelShifters(void);
+/*
+ * provides softreset to the GPIO interface
+ */
+void XSlcr_GpioPsReset(void);
+/*
+ * provides softreset to the DMA interface
+ */
+void XSlcr_DmaPsReset(void);
+/*
+ * provides softreset to the SMC interface
+ */
+void XSlcr_SmcPsReset(void);
+/*
+ * provides softreset to the CAN interface
+ */
+void XSlcr_CanPsReset(void);
+/*
+ * provides softreset to the Uart interface
+ */
+void XSlcr_UartPsReset(void);
+/*
+ * provides softreset to the I2C interface
+ */
+void XSlcr_I2cPsReset(void);
+/*
+ * provides softreset to the SPI interface
+ */
+void XSlcr_SpiPsReset(void);
+/*
+ * provides softreset to the QSPI interface
+ */
+void XSlcr_QspiPsReset(void);
+/*
+ * provides softreset to the USB interface
+ */
+void XSlcr_UsbPsReset(void);
+/*
+ * provides softreset to the GEM interface
+ */
+void XSlcr_EmacPsReset(void);
+/*
+ * provides softreset to the OCM interface
+ */
+void XSlcr_OcmReset(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XIL_MISC_RESET_H */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_mmu.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_mmu.h
new file mode 100644
index 0000000000000000000000000000000000000000..dd14b63b7057e38c5df9eadbab636379d684e30e
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_mmu.h
@@ -0,0 +1,108 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.h
+*
+* @addtogroup a9_mmu_apis Cortex A9 Processor MMU Functions
+*
+* MMU functions equip users to enable MMU, disable MMU and modify default
+* memory attributes of MMU table as per the need.
+*
+* @{
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  01/12/12 Initial version
+* 4.2	pkp	 07/21/14 Included xil_types.h file which contains definition for
+*					  u32 which resolves issue of CR#805869
+* 5.4	pkp	 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API
+* </pre>
+*
+*
+******************************************************************************/
+
+#ifndef XIL_MMU_H
+#define XIL_MMU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Memory type */
+#define NORM_NONCACHE 0x11DE2 	/* Normal Non-cacheable */
+#define STRONG_ORDERED 0xC02	/* Strongly ordered */
+#define DEVICE_MEMORY 0xC06		/* Device memory */
+#define RESERVED 0x0			/* reserved memory */
+
+/* Normal write-through cacheable shareable */
+#define NORM_WT_CACHE 0x16DEA
+
+/* Normal write back cacheable shareable */
+#define NORM_WB_CACHE 0x15DE6
+
+/* shareability attribute */
+#define SHAREABLE (0x1 << 16)
+#define NON_SHAREABLE	(~(0x1 << 16))
+
+/* Execution type */
+#define EXECUTE_NEVER ((0x1 << 4) | (0x1 << 0))
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);
+void Xil_EnableMMU(void);
+void Xil_DisableMMU(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_MMU_H */
+/**
+* @} End of "addtogroup a9_mmu_apis".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_printf.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_printf.h
new file mode 100644
index 0000000000000000000000000000000000000000..2be5c5734c7c9a2b1fe7ee657cb1cca328e16e77
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_printf.h
@@ -0,0 +1,44 @@
+ #ifndef XIL_PRINTF_H
+ #define XIL_PRINTF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <ctype.h>
+#include <string.h>
+#include <stdarg.h>
+#include "xil_types.h"
+#include "xparameters.h"
+
+/*----------------------------------------------------*/
+/* Use the following parameter passing structure to   */
+/* make xil_printf re-entrant.                        */
+/*----------------------------------------------------*/
+
+struct params_s;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the  */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and   */
+/* that is unacceptable in most embedded systems.    */
+/*---------------------------------------------------*/
+
+typedef char8* charptr;
+typedef s32 (*func_ptr)(int c);
+
+/*                                                   */
+
+void xil_printf( const char8 *ctrl1, ...);
+void print( const char8 *ptr);
+extern void outbyte (char8 c);
+extern char8 inbyte(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_testcache.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_testcache.h
new file mode 100644
index 0000000000000000000000000000000000000000..c35e9a463f05d7fa7e176b96369f5af1493d3127
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_testcache.h
@@ -0,0 +1,71 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testcache.h
+*
+* @addtogroup common_test_utils
+* <h2>Cache test </h2>
+* The xil_testcache.h file contains utility functions to test cache.
+*
+* @{
+* <pre>
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  07/29/09 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_TESTCACHE_H	/* prevent circular inclusions */
+#define XIL_TESTCACHE_H	/* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern s32 Xil_TestDCacheRange(void);
+extern s32 Xil_TestDCacheAll(void);
+extern s32 Xil_TestICacheRange(void);
+extern s32 Xil_TestICacheAll(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_testio.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_testio.h
new file mode 100644
index 0000000000000000000000000000000000000000..ad68ead6430fef3b1a961165119aca5b8c557652
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_testio.h
@@ -0,0 +1,94 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testio.h
+*
+* @addtogroup common_test_utils Test Utilities
+* <h2>I/O test </h2>
+* The xil_testio.h file contains utility functions to test endian related memory
+* IO functions.
+*
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00 hbm  08/05/09 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_TESTIO_H	/* prevent circular inclusions */
+#define XIL_TESTIO_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+#define XIL_TESTIO_DEFAULT 	0
+#define XIL_TESTIO_LE		1
+#define XIL_TESTIO_BE		2
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value);
+extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap);
+extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_testmem.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_testmem.h
new file mode 100644
index 0000000000000000000000000000000000000000..c204728223b2c15e57d4e9f8afc944ad02a40c76
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_testmem.h
@@ -0,0 +1,158 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmem.h
+* @addtogroup common_test_utils
+*
+* <h2>Memory test</h2>
+*
+* The xil_testmem.h file contains utility functions to test memory.
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+* Following list describes the supported memory tests:
+*
+*  - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests.
+*
+*  - XIL_TESTMEM_INCREMENT: This test
+* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the
+* test value for memory.
+*
+*  - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test
+* uses a walking '1' as the test value for memory.
+* @code
+*          location 1 = 0x00000001
+*          location 2 = 0x00000002
+*          ...
+* @endcode
+*
+*  - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test.
+* This test uses the inverse value of the walking ones test
+* as the test value for memory.
+* @code
+*       location 1 = 0xFFFFFFFE
+*       location 2 = 0xFFFFFFFD
+*       ...
+*@endcode
+*
+*  - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test.
+* This test uses the inverse of the address of the location under test
+* as the test value for memory.
+*
+*  - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test.
+* This test uses the provided patters as the test value for memory.
+* If zero is provided as the pattern the test uses '0xDEADBEEF".
+*
+* @warning
+* The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces
+* have been set up.
+* The address provided to the memory tests is not checked for
+* validity except for the NULL case. It is possible to provide a code-space
+* pointer for this test to start with and ultimately destroy executable code
+* causing random failures.
+*
+* @note
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_TESTMEM_H	/* prevent circular inclusions */
+#define XIL_TESTMEM_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* xutil_memtest defines */
+
+#define XIL_TESTMEM_INIT_VALUE	1U
+
+/** @name Memory subtests
+ * @{
+ */
+/**
+ * See the detailed description of the subtests in the file description.
+ */
+#define XIL_TESTMEM_ALLMEMTESTS     0x00U
+#define XIL_TESTMEM_INCREMENT       0x01U
+#define XIL_TESTMEM_WALKONES        0x02U
+#define XIL_TESTMEM_WALKZEROS       0x03U
+#define XIL_TESTMEM_INVERSEADDR     0x04U
+#define XIL_TESTMEM_FIXEDPATTERN    0x05U
+#define XIL_TESTMEM_MAXTEST         XIL_TESTMEM_FIXEDPATTERN
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/* xutil_testmem prototypes */
+
+extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
+extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
+extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_types.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_types.h
new file mode 100644
index 0000000000000000000000000000000000000000..8143aff1ea4481ade21acf41eba4c361096081a9
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xil_types.h
@@ -0,0 +1,209 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_types.h
+*
+* @addtogroup common_types Basic Data types for Xilinx&reg; Software IP
+*
+* The xil_types.h file contains basic types for Xilinx software IP. These data types
+* are applicable for all processors supported by Xilinx.
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* 3.03a sdm  05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+* 5.00 	pkp  05/29/14 Made changes for 64 bit architecture
+*	srt  07/14/14 Use standard definitions from stdint.h and stddef.h
+*		      Define LONG and ULONG datatypes and mask values
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_TYPES_H	/* prevent circular inclusions */
+#define XIL_TYPES_H	/* by using protection macros */
+
+#include <stdint.h>
+#include <stddef.h>
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#  define TRUE		1U
+#endif
+
+#ifndef FALSE
+#  define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+#define XIL_COMPONENT_IS_READY     0x11111111U  /**< In device drivers, This macro will be
+                                                 assigend to "IsReady" member of driver
+												 instance to indicate that driver
+												 instance is initialized and ready to use. */
+#define XIL_COMPONENT_IS_STARTED   0x22222222U  /**< In device drivers, This macro will be assigend to
+                                                 "IsStarted" member of driver instance
+												 to indicate that driver instance is
+												 started and it can be enabled. */
+
+/* @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XBASIC_TYPES_H
+/*
+ * guarded against xbasic_types.h.
+ */
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+/** @}*/
+#define __XUINT64__
+typedef struct
+{
+	u32 Upper;
+	u32 Lower;
+} Xuint64;
+
+
+/*****************************************************************************/
+/**
+* @brief    Return the most significant half of the 64 bit data type.
+*
+* @param    x is the 64 bit word.
+*
+* @return   The upper 32 bits of the 64 bit word.
+*
+******************************************************************************/
+#define XUINT64_MSW(x) ((x).Upper)
+
+/*****************************************************************************/
+/**
+* @brief    Return the least significant half of the 64 bit data type.
+*
+* @param    x is the 64 bit word.
+*
+* @return   The lower 32 bits of the 64 bit word.
+*
+******************************************************************************/
+#define XUINT64_LSW(x) ((x).Lower)
+
+#endif /* XBASIC_TYPES_H */
+
+/*
+ * xbasic_types.h does not typedef s* or u64
+ */
+/** @{ */
+typedef char char8;
+typedef int8_t s8;
+typedef int16_t s16;
+typedef int32_t s32;
+typedef int64_t s64;
+typedef uint64_t u64;
+typedef int sint32;
+
+typedef intptr_t INTPTR;
+typedef uintptr_t UINTPTR;
+typedef ptrdiff_t PTRDIFF;
+/** @}*/
+#if !defined(LONG) || !defined(ULONG)
+typedef long LONG;
+typedef unsigned long ULONG;
+#endif
+
+#define ULONG64_HI_MASK	0xFFFFFFFF00000000U
+#define ULONG64_LO_MASK	~ULONG64_HI_MASK
+
+#else
+#include <linux/types.h>
+#endif
+
+/** @{ */
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/**
+ * This data type defines an exception handler for a processor.
+ * The argument points to the instance of the component
+ */
+typedef void (*XExceptionHandler) (void *InstancePtr);
+
+/**
+ * @brief  Returns 32-63 bits of a number.
+ * @param  n : Number being accessed.
+ * @return Bits 32-63 of number.
+ *
+ * @note    A basic shift-right of a 64- or 32-bit quantity.
+ *          Use this to suppress the "right shift count >= width of type"
+ *          warning when that quantity is 32-bits.
+ */
+#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
+
+/**
+ * @brief  Returns 0-31 bits of a number
+ * @param  n : Number being accessed.
+ * @return Bits 0-31 of number
+ */
+#define LOWER_32_BITS(n) ((u32)(n))
+
+
+
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#define TRUE		1U
+#endif
+
+#ifndef FALSE
+#define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+#endif	/* end of protection macro */
+/**
+* @} End of "addtogroup common_types".
+*/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xl2cc.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xl2cc.h
new file mode 100644
index 0000000000000000000000000000000000000000..735e26dd4df8663a93b4f22ce5eb5cd712bc6653
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xl2cc.h
@@ -0,0 +1,172 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xl2cc.h
+*
+* This file contains the address definitions for the PL310 Level-2 Cache
+* Controller.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  02/01/10 Initial version
+* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
+*		      'xil_errata.h' for errata description
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XL2CC_H_
+#define _XL2CC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+/* L2CC Register Offsets */
+#define XPS_L2CC_ID_OFFSET		0x0000U
+#define XPS_L2CC_TYPE_OFFSET		0x0004U
+#define XPS_L2CC_CNTRL_OFFSET		0x0100U
+#define XPS_L2CC_AUX_CNTRL_OFFSET	0x0104U
+#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET	0x0108U
+#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET	0x010CU
+
+#define XPS_L2CC_EVNT_CNTRL_OFFSET	0x0200U
+#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET	0x0204U
+#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET	0x0208U
+#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET	0x020CU
+#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET	0x0210U
+
+#define XPS_L2CC_IER_OFFSET		0x0214U		/* Interrupt Mask */
+#define XPS_L2CC_IPR_OFFSET		0x0218U		/* Masked interrupt status */
+#define XPS_L2CC_ISR_OFFSET		0x021CU		/* Raw Interrupt Status */
+#define XPS_L2CC_IAR_OFFSET		0x0220U		/* Interrupt Clear */
+
+#define XPS_L2CC_CACHE_SYNC_OFFSET		0x0730U		/* Cache Sync */
+#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET	0x0740U		/* Dummy Register for Cache Sync */
+#define XPS_L2CC_CACHE_INVLD_PA_OFFSET		0x0770U		/* Cache Invalid by PA */
+#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET		0x077CU		/* Cache Invalid by Way */
+#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET		0x07B0U		/* Cache Clean by PA */
+#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET	0x07B8U		/* Cache Clean by Index */
+#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET		0x07BCU		/* Cache Clean by Way */
+#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET	0x07F0U		/* Cache Invalidate and Clean by PA */
+#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET	0x07F8U		/* Cache Invalidate and Clean by Index */
+#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET	0x07FCU		/* Cache Invalidate and Clean by Way */
+
+#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET	0x0900U		/* Cache Data Lockdown 0 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET	0x0904U		/* Cache Instruction Lockdown 0 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET	0x0908U		/* Cache Data Lockdown 1 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET	0x090CU		/* Cache Instruction Lockdown 1 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET	0x0910U		/* Cache Data Lockdown 2 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET	0x0914U		/* Cache Instruction Lockdown 2 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET	0x0918U		/* Cache Data Lockdown 3 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET	0x091CU		/* Cache Instruction Lockdown 3 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET	0x0920U		/* Cache Data Lockdown 4 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET	0x0924U		/* Cache Instruction Lockdown 4 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET	0x0928U		/* Cache Data Lockdown 5 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET	0x092CU		/* Cache Instruction Lockdown 5 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET	0x0930U		/* Cache Data Lockdown 6 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET	0x0934U		/* Cache Instruction Lockdown 6 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET	0x0938U		/* Cache Data Lockdown 7 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET	0x093CU		/* Cache Instruction Lockdown 7 by Way */
+
+#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950U		/* Cache Lockdown Line Enable */
+#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET	0x0954U		/* Cache Unlock All Lines by Way */
+
+#define XPS_L2CC_ADDR_FILTER_START_OFFSET	0x0C00U		/* Start of address filtering */
+#define XPS_L2CC_ADDR_FILTER_END_OFFSET		0x0C04U		/* Start of address filtering */
+
+#define XPS_L2CC_DEBUG_CTRL_OFFSET		0x0F40U		/* Debug Control Register */
+
+/* XPS_L2CC_CNTRL_OFFSET bit masks */
+#define XPS_L2CC_ENABLE_MASK		0x00000001U	/* enables the L2CC */
+
+/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */
+#define XPS_L2CC_AUX_EBRESPE_MASK	0x40000000U	/* Early BRESP Enable */
+#define XPS_L2CC_AUX_IPFE_MASK		0x20000000U	/* Instruction Prefetch Enable */
+#define XPS_L2CC_AUX_DPFE_MASK		0x10000000U	/* Data Prefetch Enable */
+#define XPS_L2CC_AUX_NSIC_MASK		0x08000000U	/* Non-secure interrupt access control */
+#define XPS_L2CC_AUX_NSLE_MASK		0x04000000U	/* Non-secure lockdown enable */
+#define XPS_L2CC_AUX_CRP_MASK		0x02000000U	/* Cache replacement policy */
+#define XPS_L2CC_AUX_FWE_MASK		0x01800000U	/* Force write allocate */
+#define XPS_L2CC_AUX_SAOE_MASK		0x00400000U	/* Shared attribute override enable */
+#define XPS_L2CC_AUX_PE_MASK		0x00200000U	/* Parity enable */
+#define XPS_L2CC_AUX_EMBE_MASK		0x00100000U	/* Event monitor bus enable */
+#define XPS_L2CC_AUX_WAY_SIZE_MASK	0x000E0000U	/* Way-size */
+#define XPS_L2CC_AUX_ASSOC_MASK		0x00010000U	/* Associativity */
+#define XPS_L2CC_AUX_SAIE_MASK		0x00002000U	/* Shared attribute invalidate enable */
+#define XPS_L2CC_AUX_EXCL_CACHE_MASK	0x00001000U	/* Exclusive cache configuration */
+#define XPS_L2CC_AUX_SBDLE_MASK		0x00000800U	/* Store buffer device limitation Enable */
+#define XPS_L2CC_AUX_HPSODRE_MASK	0x00000400U	/* High Priority for SO and Dev Reads Enable */
+#define XPS_L2CC_AUX_FLZE_MASK		0x00000001U	/* Full line of zero enable */
+
+#define XPS_L2CC_AUX_REG_DEFAULT_MASK	0x72360000U	/* Enable all prefetching, */
+                                                    /* Cache replacement policy, Parity enable, */
+                                                    /* Event monitor bus enable and Way Size (64 KB) */
+#define XPS_L2CC_AUX_REG_ZERO_MASK	0xFFF1FFFFU	/* */
+
+#define XPS_L2CC_TAG_RAM_DEFAULT_MASK	0x00000111U	/* latency for TAG RAM */
+#define XPS_L2CC_DATA_RAM_DEFAULT_MASK	0x00000121U	/* latency for DATA RAM */
+
+/* Interrupt bit masks */
+#define XPS_L2CC_IXR_DECERR_MASK	0x00000100U	/* DECERR from L3 */
+#define XPS_L2CC_IXR_SLVERR_MASK	0x00000080U	/* SLVERR from L3 */
+#define XPS_L2CC_IXR_ERRRD_MASK		0x00000040U	/* Error on L2 data RAM (Read) */
+#define XPS_L2CC_IXR_ERRRT_MASK		0x00000020U	/* Error on L2 tag RAM (Read) */
+#define XPS_L2CC_IXR_ERRWD_MASK		0x00000010U	/* Error on L2 data RAM (Write) */
+#define XPS_L2CC_IXR_ERRWT_MASK		0x00000008U	/* Error on L2 tag RAM (Write) */
+#define XPS_L2CC_IXR_PARRD_MASK		0x00000004U	/* Parity Error on L2 data RAM (Read) */
+#define XPS_L2CC_IXR_PARRT_MASK		0x00000002U	/* Parity Error on L2 tag RAM (Read) */
+#define XPS_L2CC_IXR_ECNTR_MASK		0x00000001U	/* Event Counter1/0 Overflow Increment */
+
+/* Address filtering mask and enable bit */
+#define XPS_L2CC_ADDR_FILTER_VALID_MASK	0xFFF00000U	/* Address filtering valid bits*/
+#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001U	/* Address filtering enable bit*/
+
+/* Debug control bits */
+#define XPS_L2CC_DEBUG_SPIDEN_MASK	0x00000004U	/* Debug SPIDEN bit */
+#define XPS_L2CC_DEBUG_DWB_MASK		0x00000002U	/* Debug DWB bit, forces write through */
+#define XPS_L2CC_DEBUG_DCL_MASK		0x00000002U	/* Debug DCL bit, disables cache line fill */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xl2cc_counter.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xl2cc_counter.h
new file mode 100644
index 0000000000000000000000000000000000000000..8d0a61f07d193f41dc887b73052a3be9b1b5b78f
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xl2cc_counter.h
@@ -0,0 +1,113 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xl2cc_counter.h
+*
+* @addtogroup l2_event_counter_apis PL310 L2 Event Counters Functions
+*
+* xl2cc_counter.h contains APIs for configuring and controlling the event
+* counters in PL310 L2 cache controller.
+* PL310 has two event counters which can be used to count variety of events
+* like DRHIT, DRREQ, DWHIT, DWREQ, etc. xl2cc_counter.h contains definitions
+* for different configurations which can be used for the event counters to
+* count a set of events.
+*
+*
+* @{
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+* 3.07a asa  08/30/12 Updated for CR 675636 to provide the L2 Base Address
+*		      inside the APIs
+* </pre>
+*
+******************************************************************************/
+
+#ifndef L2CCCOUNTER_H /* prevent circular inclusions */
+#define L2CCCOUNTER_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants define the event codes for the event counters.
+ */
+#define XL2CC_CO		0x1
+#define XL2CC_DRHIT		0x2
+#define XL2CC_DRREQ		0x3
+#define XL2CC_DWHIT		0x4
+#define XL2CC_DWREQ		0x5
+#define XL2CC_DWTREQ		0x6
+#define XL2CC_IRHIT		0x7
+#define XL2CC_IRREQ		0x8
+#define XL2CC_WA		0x9
+#define XL2CC_IPFALLOC		0xa
+#define XL2CC_EPFHIT		0xb
+#define XL2CC_EPFALLOC		0xc
+#define XL2CC_SRRCVD		0xd
+#define XL2CC_SRCONF		0xe
+#define XL2CC_EPFRCVD		0xf
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+void XL2cc_EventCtrInit(s32 Event0, s32 Event1);
+void XL2cc_EventCtrStart(void);
+void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* L2CCCOUNTER_H */
+/**
+* @} End of "addtogroup l2_event_counter_apis".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xparameters.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xparameters.h
new file mode 100644
index 0000000000000000000000000000000000000000..85419e8c5c84e0635caf6685fcc29e45429fd5b5
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xparameters.h
@@ -0,0 +1,600 @@
+#ifndef XPARAMETERS_H   /* prevent circular inclusions */
+#define XPARAMETERS_H   /* by using protection macros */
+
+/* Definition for CPU ID */
+#define XPAR_CPU_ID 0
+
+/* Definitions for peripheral PS7_CORTEXA9_0 */
+#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 650000000
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_CORTEXA9_0 */
+#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 650000000
+
+
+/******************************************************************/
+
+#include "xparameters_ps.h"
+
+#define STDIN_BASEADDRESS 0xE0000000
+#define STDOUT_BASEADDRESS 0xE0000000
+
+/******************************************************************/
+
+
+/* Definitions for peripheral PS7_DDR_0 */
+#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
+#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x1FFFFFFF
+
+
+/******************************************************************/
+
+/* Definitions for driver DEVCFG */
+#define XPAR_XDCFG_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_DEV_CFG_0 */
+#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0
+#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000
+#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_DEV_CFG_0 */
+#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID
+#define XPAR_XDCFG_0_BASEADDR 0xF8007000
+#define XPAR_XDCFG_0_HIGHADDR 0xF80070FF
+
+
+/******************************************************************/
+
+/* Definitions for driver DMAPS */
+#define XPAR_XDMAPS_NUM_INSTANCES 2
+
+/* Definitions for peripheral PS7_DMA_NS */
+#define XPAR_PS7_DMA_NS_DEVICE_ID 0
+#define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000
+#define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF
+
+
+/* Definitions for peripheral PS7_DMA_S */
+#define XPAR_PS7_DMA_S_DEVICE_ID 1
+#define XPAR_PS7_DMA_S_BASEADDR 0xF8003000
+#define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_DMA_NS */
+#define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID
+#define XPAR_XDMAPS_0_BASEADDR 0xF8004000
+#define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF
+
+/* Canonical definitions for peripheral PS7_DMA_S */
+#define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID
+#define XPAR_XDMAPS_1_BASEADDR 0xF8003000
+#define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF
+
+
+/******************************************************************/
+
+/* Definitions for driver EMACPS */
+#define XPAR_XEMACPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_ETHERNET_0 */
+#define XPAR_PS7_ETHERNET_0_DEVICE_ID 0
+#define XPAR_PS7_ETHERNET_0_BASEADDR 0xE000B000
+#define XPAR_PS7_ETHERNET_0_HIGHADDR 0xE000BFFF
+#define XPAR_PS7_ETHERNET_0_ENET_CLK_FREQ_HZ 125000000
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 8
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 8
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 8
+#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_ETHERNET_0 */
+#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID
+#define XPAR_XEMACPS_0_BASEADDR 0xE000B000
+#define XPAR_XEMACPS_0_HIGHADDR 0xE000BFFF
+#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 125000000
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 8
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 8
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 8
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50
+
+
+/******************************************************************/
+
+
+/* Definitions for peripheral PS7_AFI_0 */
+#define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000
+#define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF
+
+
+/* Definitions for peripheral PS7_AFI_1 */
+#define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000
+#define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF
+
+
+/* Definitions for peripheral PS7_AFI_2 */
+#define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000
+#define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF
+
+
+/* Definitions for peripheral PS7_AFI_3 */
+#define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000
+#define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF
+
+
+/* Definitions for peripheral PS7_DDRC_0 */
+#define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000
+#define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF
+
+
+/* Definitions for peripheral PS7_GLOBALTIMER_0 */
+#define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200
+#define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF
+
+
+/* Definitions for peripheral PS7_GPV_0 */
+#define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000
+#define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF
+
+
+/* Definitions for peripheral PS7_INTC_DIST_0 */
+#define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000
+#define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF
+
+
+/* Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */
+#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000
+#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF
+
+
+/* Definitions for peripheral PS7_L2CACHEC_0 */
+#define XPAR_PS7_L2CACHEC_0_S_AXI_BASEADDR 0xF8F02000
+#define XPAR_PS7_L2CACHEC_0_S_AXI_HIGHADDR 0xF8F02FFF
+
+
+/* Definitions for peripheral PS7_OCMC_0 */
+#define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000
+#define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF
+
+
+/* Definitions for peripheral PS7_PL310_0 */
+#define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000
+#define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF
+
+
+/* Definitions for peripheral PS7_PMU_0 */
+#define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000
+#define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF
+#define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000
+#define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF
+
+
+/* Definitions for peripheral PS7_QSPI_LINEAR_0 */
+#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
+#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFCFFFFFF
+
+
+/* Definitions for peripheral PS7_RAM_0 */
+#define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000
+#define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF
+
+
+/* Definitions for peripheral PS7_RAM_1 */
+#define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000
+#define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
+
+
+/* Definitions for peripheral PS7_SCUC_0 */
+#define XPAR_PS7_SCUC_0_S_AXI_BASEADDR 0xF8F00000
+#define XPAR_PS7_SCUC_0_S_AXI_HIGHADDR 0xF8F000FC
+
+
+/* Definitions for peripheral PS7_SLCR_0 */
+#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000
+#define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF
+
+
+/******************************************************************/
+
+/* Definitions for driver GPIO */
+#define XPAR_XGPIO_NUM_INSTANCES 2
+
+/* Definitions for peripheral AXI_GPIO_0 */
+#define XPAR_AXI_GPIO_0_BASEADDR 0x41200000
+#define XPAR_AXI_GPIO_0_HIGHADDR 0x4120FFFF
+#define XPAR_AXI_GPIO_0_DEVICE_ID 0
+#define XPAR_AXI_GPIO_0_INTERRUPT_PRESENT 0
+#define XPAR_AXI_GPIO_0_IS_DUAL 1
+
+
+/* Definitions for peripheral AXI_GPIO_1 */
+#define XPAR_AXI_GPIO_1_BASEADDR 0x41210000
+#define XPAR_AXI_GPIO_1_HIGHADDR 0x4121FFFF
+#define XPAR_AXI_GPIO_1_DEVICE_ID 1
+#define XPAR_AXI_GPIO_1_INTERRUPT_PRESENT 0
+#define XPAR_AXI_GPIO_1_IS_DUAL 0
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral AXI_GPIO_0 */
+#define XPAR_GPIO_0_BASEADDR 0x41200000
+#define XPAR_GPIO_0_HIGHADDR 0x4120FFFF
+#define XPAR_GPIO_0_DEVICE_ID XPAR_AXI_GPIO_0_DEVICE_ID
+#define XPAR_GPIO_0_INTERRUPT_PRESENT 0
+#define XPAR_GPIO_0_IS_DUAL 1
+
+/* Canonical definitions for peripheral AXI_GPIO_1 */
+#define XPAR_GPIO_1_BASEADDR 0x41210000
+#define XPAR_GPIO_1_HIGHADDR 0x4121FFFF
+#define XPAR_GPIO_1_DEVICE_ID XPAR_AXI_GPIO_1_DEVICE_ID
+#define XPAR_GPIO_1_INTERRUPT_PRESENT 0
+#define XPAR_GPIO_1_IS_DUAL 0
+
+
+/******************************************************************/
+
+/* Definitions for driver GPIOPS */
+#define XPAR_XGPIOPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_GPIO_0 */
+#define XPAR_PS7_GPIO_0_DEVICE_ID 0
+#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
+#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_GPIO_0 */
+#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
+#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
+#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
+
+
+/******************************************************************/
+
+/* Definitions for driver IICPS */
+#define XPAR_XIICPS_NUM_INSTANCES 2
+
+/* Definitions for peripheral PS7_I2C_0 */
+#define XPAR_PS7_I2C_0_DEVICE_ID 0
+#define XPAR_PS7_I2C_0_BASEADDR 0xE0004000
+#define XPAR_PS7_I2C_0_HIGHADDR 0xE0004FFF
+#define XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ 108333336
+
+
+/* Definitions for peripheral PS7_I2C_1 */
+#define XPAR_PS7_I2C_1_DEVICE_ID 1
+#define XPAR_PS7_I2C_1_BASEADDR 0xE0005000
+#define XPAR_PS7_I2C_1_HIGHADDR 0xE0005FFF
+#define XPAR_PS7_I2C_1_I2C_CLK_FREQ_HZ 108333336
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_I2C_0 */
+#define XPAR_XIICPS_0_DEVICE_ID XPAR_PS7_I2C_0_DEVICE_ID
+#define XPAR_XIICPS_0_BASEADDR 0xE0004000
+#define XPAR_XIICPS_0_HIGHADDR 0xE0004FFF
+#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 108333336
+
+/* Canonical definitions for peripheral PS7_I2C_1 */
+#define XPAR_XIICPS_1_DEVICE_ID XPAR_PS7_I2C_1_DEVICE_ID
+#define XPAR_XIICPS_1_BASEADDR 0xE0005000
+#define XPAR_XIICPS_1_HIGHADDR 0xE0005FFF
+#define XPAR_XIICPS_1_I2C_CLK_FREQ_HZ 108333336
+
+
+/******************************************************************/
+
+/* Definitions for driver PWM_RECORDER */
+#define XPAR_PWM_RECORDER_NUM_INSTANCES 6
+
+/* Definitions for peripheral PWM_RECORDER_0 */
+#define XPAR_PWM_RECORDER_0_DEVICE_ID 0
+#define XPAR_PWM_RECORDER_0_S_AXI_BASEADDR 0x43C40000
+#define XPAR_PWM_RECORDER_0_S_AXI_HIGHADDR 0x43C4FFFF
+
+
+/* Definitions for peripheral PWM_RECORDER_1 */
+#define XPAR_PWM_RECORDER_1_DEVICE_ID 1
+#define XPAR_PWM_RECORDER_1_S_AXI_BASEADDR 0x43C50000
+#define XPAR_PWM_RECORDER_1_S_AXI_HIGHADDR 0x43C5FFFF
+
+
+/* Definitions for peripheral PWM_RECORDER_2 */
+#define XPAR_PWM_RECORDER_2_DEVICE_ID 2
+#define XPAR_PWM_RECORDER_2_S_AXI_BASEADDR 0x43C60000
+#define XPAR_PWM_RECORDER_2_S_AXI_HIGHADDR 0x43C6FFFF
+
+
+/* Definitions for peripheral PWM_RECORDER_3 */
+#define XPAR_PWM_RECORDER_3_DEVICE_ID 3
+#define XPAR_PWM_RECORDER_3_S_AXI_BASEADDR 0x43C70000
+#define XPAR_PWM_RECORDER_3_S_AXI_HIGHADDR 0x43C7FFFF
+
+
+/* Definitions for peripheral PWM_RECORDER_4 */
+#define XPAR_PWM_RECORDER_4_DEVICE_ID 4
+#define XPAR_PWM_RECORDER_4_S_AXI_BASEADDR 0x43C80000
+#define XPAR_PWM_RECORDER_4_S_AXI_HIGHADDR 0x43C8FFFF
+
+
+/* Definitions for peripheral PWM_RECORDER_5 */
+#define XPAR_PWM_RECORDER_5_DEVICE_ID 5
+#define XPAR_PWM_RECORDER_5_S_AXI_BASEADDR 0x43C90000
+#define XPAR_PWM_RECORDER_5_S_AXI_HIGHADDR 0x43C9FFFF
+
+
+/******************************************************************/
+
+/* Definitions for driver PWM_SIGNAL_OUT */
+#define XPAR_PWM_SIGNAL_OUT_NUM_INSTANCES 4
+
+/* Definitions for peripheral PWM_SIGNAL_OUT_0 */
+#define XPAR_PWM_SIGNAL_OUT_0_DEVICE_ID 0
+#define XPAR_PWM_SIGNAL_OUT_0_S_AXI_BASEADDR 0x43C00000
+#define XPAR_PWM_SIGNAL_OUT_0_S_AXI_HIGHADDR 0x43C0FFFF
+
+
+/* Definitions for peripheral PWM_SIGNAL_OUT_1 */
+#define XPAR_PWM_SIGNAL_OUT_1_DEVICE_ID 1
+#define XPAR_PWM_SIGNAL_OUT_1_S_AXI_BASEADDR 0x43C10000
+#define XPAR_PWM_SIGNAL_OUT_1_S_AXI_HIGHADDR 0x43C1FFFF
+
+
+/* Definitions for peripheral PWM_SIGNAL_OUT_2 */
+#define XPAR_PWM_SIGNAL_OUT_2_DEVICE_ID 2
+#define XPAR_PWM_SIGNAL_OUT_2_S_AXI_BASEADDR 0x43C20000
+#define XPAR_PWM_SIGNAL_OUT_2_S_AXI_HIGHADDR 0x43C2FFFF
+
+
+/* Definitions for peripheral PWM_SIGNAL_OUT_3 */
+#define XPAR_PWM_SIGNAL_OUT_3_DEVICE_ID 3
+#define XPAR_PWM_SIGNAL_OUT_3_S_AXI_BASEADDR 0x43C30000
+#define XPAR_PWM_SIGNAL_OUT_3_S_AXI_HIGHADDR 0x43C3FFFF
+
+
+/******************************************************************/
+
+/* Definitions for driver QSPIPS */
+#define XPAR_XQSPIPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_QSPI_0 */
+#define XPAR_PS7_QSPI_0_DEVICE_ID 0
+#define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000
+#define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF
+#define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000
+#define XPAR_PS7_QSPI_0_QSPI_MODE 0
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_QSPI_0 */
+#define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID
+#define XPAR_XQSPIPS_0_BASEADDR 0xE000D000
+#define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF
+#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000
+#define XPAR_XQSPIPS_0_QSPI_MODE 0
+
+
+/******************************************************************/
+
+/* Definitions for driver SCUGIC */
+#define XPAR_XSCUGIC_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SCUGIC_0 */
+#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0
+#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100
+#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FF
+#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_SCUGIC_0 */
+#define XPAR_SCUGIC_0_DEVICE_ID 0
+#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100
+#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FF
+#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000
+
+
+/******************************************************************/
+
+/* Definitions for driver SCUTIMER */
+#define XPAR_XSCUTIMER_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SCUTIMER_0 */
+#define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0
+#define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600
+#define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_SCUTIMER_0 */
+#define XPAR_XSCUTIMER_0_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID
+#define XPAR_XSCUTIMER_0_BASEADDR 0xF8F00600
+#define XPAR_XSCUTIMER_0_HIGHADDR 0xF8F0061F
+
+
+/******************************************************************/
+
+/* Definitions for driver SCUWDT */
+#define XPAR_XSCUWDT_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SCUWDT_0 */
+#define XPAR_PS7_SCUWDT_0_DEVICE_ID 0
+#define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620
+#define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_SCUWDT_0 */
+#define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID
+#define XPAR_SCUWDT_0_BASEADDR 0xF8F00620
+#define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF
+
+
+/******************************************************************/
+
+/* Definitions for driver SDPS */
+#define XPAR_XSDPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SD_0 */
+#define XPAR_PS7_SD_0_DEVICE_ID 0
+#define XPAR_PS7_SD_0_BASEADDR 0xE0100000
+#define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF
+#define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000
+#define XPAR_PS7_SD_0_HAS_CD 1
+#define XPAR_PS7_SD_0_HAS_WP 1
+#define XPAR_PS7_SD_0_BUS_WIDTH 0
+#define XPAR_PS7_SD_0_MIO_BANK 0
+#define XPAR_PS7_SD_0_HAS_EMIO 0
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_SD_0 */
+#define XPAR_XSDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID
+#define XPAR_XSDPS_0_BASEADDR 0xE0100000
+#define XPAR_XSDPS_0_HIGHADDR 0xE0100FFF
+#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 50000000
+#define XPAR_XSDPS_0_HAS_CD 1
+#define XPAR_XSDPS_0_HAS_WP 1
+#define XPAR_XSDPS_0_BUS_WIDTH 0
+#define XPAR_XSDPS_0_MIO_BANK 0
+#define XPAR_XSDPS_0_HAS_EMIO 0
+
+
+/******************************************************************/
+
+/* Definitions for driver TTCPS */
+#define XPAR_XTTCPS_NUM_INSTANCES 3
+
+/* Definitions for peripheral PS7_TTC_0 */
+#define XPAR_PS7_TTC_0_DEVICE_ID 0
+#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000
+#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 108333336
+#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0
+#define XPAR_PS7_TTC_1_DEVICE_ID 1
+#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004
+#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 108333336
+#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0
+#define XPAR_PS7_TTC_2_DEVICE_ID 2
+#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008
+#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 108333336
+#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_TTC_0 */
+#define XPAR_XTTCPS_0_DEVICE_ID XPAR_PS7_TTC_0_DEVICE_ID
+#define XPAR_XTTCPS_0_BASEADDR 0xF8001000
+#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 108333336
+#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0
+
+#define XPAR_XTTCPS_1_DEVICE_ID XPAR_PS7_TTC_1_DEVICE_ID
+#define XPAR_XTTCPS_1_BASEADDR 0xF8001004
+#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 108333336
+#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0
+
+#define XPAR_XTTCPS_2_DEVICE_ID XPAR_PS7_TTC_2_DEVICE_ID
+#define XPAR_XTTCPS_2_BASEADDR 0xF8001008
+#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 108333336
+#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0
+
+
+/******************************************************************/
+
+/* Definitions for driver UARTPS */
+#define XPAR_XUARTPS_NUM_INSTANCES 2
+
+/* Definitions for peripheral PS7_UART_0 */
+#define XPAR_PS7_UART_0_DEVICE_ID 0
+#define XPAR_PS7_UART_0_BASEADDR 0xE0000000
+#define XPAR_PS7_UART_0_HIGHADDR 0xE0000FFF
+#define XPAR_PS7_UART_0_UART_CLK_FREQ_HZ 100000000
+#define XPAR_PS7_UART_0_HAS_MODEM 0
+
+
+/* Definitions for peripheral PS7_UART_1 */
+#define XPAR_PS7_UART_1_DEVICE_ID 1
+#define XPAR_PS7_UART_1_BASEADDR 0xE0001000
+#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF
+#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 100000000
+#define XPAR_PS7_UART_1_HAS_MODEM 0
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_UART_0 */
+#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_0_DEVICE_ID
+#define XPAR_XUARTPS_0_BASEADDR 0xE0000000
+#define XPAR_XUARTPS_0_HIGHADDR 0xE0000FFF
+#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 100000000
+#define XPAR_XUARTPS_0_HAS_MODEM 0
+
+/* Canonical definitions for peripheral PS7_UART_1 */
+#define XPAR_XUARTPS_1_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID
+#define XPAR_XUARTPS_1_BASEADDR 0xE0001000
+#define XPAR_XUARTPS_1_HIGHADDR 0xE0001FFF
+#define XPAR_XUARTPS_1_UART_CLK_FREQ_HZ 100000000
+#define XPAR_XUARTPS_1_HAS_MODEM 0
+
+
+/******************************************************************/
+
+/* Definitions for driver USBPS */
+#define XPAR_XUSBPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_USB_0 */
+#define XPAR_PS7_USB_0_DEVICE_ID 0
+#define XPAR_PS7_USB_0_BASEADDR 0xE0002000
+#define XPAR_PS7_USB_0_HIGHADDR 0xE0002FFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_USB_0 */
+#define XPAR_XUSBPS_0_DEVICE_ID XPAR_PS7_USB_0_DEVICE_ID
+#define XPAR_XUSBPS_0_BASEADDR 0xE0002000
+#define XPAR_XUSBPS_0_HIGHADDR 0xE0002FFF
+
+
+/******************************************************************/
+
+/* Definitions for driver XADCPS */
+#define XPAR_XADCPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_XADC_0 */
+#define XPAR_PS7_XADC_0_DEVICE_ID 0
+#define XPAR_PS7_XADC_0_BASEADDR 0xF8007100
+#define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_XADC_0 */
+#define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID
+#define XPAR_XADCPS_0_BASEADDR 0xF8007100
+#define XPAR_XADCPS_0_HIGHADDR 0xF8007120
+
+
+/******************************************************************/
+
+#endif  /* end of protection macro */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xparameters_ps.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xparameters_ps.h
new file mode 100644
index 0000000000000000000000000000000000000000..ea0d2bcde03758e67891424f21de0a56fc582b72
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xparameters_ps.h
@@ -0,0 +1,333 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xparameters_ps.h
+*
+* This file contains the address definitions for the hard peripherals
+* attached to the ARM Cortex A9 core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 02/01/10 Initial version
+* 3.04a sdm     02/02/12 Removed some of the defines as they are being generated through
+*                        driver tcl
+* 5.0	pkp		01/16/15 Added interrupt ID definition of ttc for TEST APP
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XPARAMETERS_PS_H_
+#define _XPARAMETERS_PS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock
+ */
+
+/* Canonical definitions for DDR MEMORY */
+#define XPAR_DDR_MEM_BASEADDR		0x00000000U
+#define XPAR_DDR_MEM_HIGHADDR		0x3FFFFFFFU
+
+/* Canonical definitions for Interrupts  */
+#define XPAR_XUARTPS_0_INTR		XPS_UART0_INT_ID
+#define XPAR_XUARTPS_1_INTR		XPS_UART1_INT_ID
+#define XPAR_XUSBPS_0_INTR		XPS_USB0_INT_ID
+#define XPAR_XUSBPS_1_INTR		XPS_USB1_INT_ID
+#define XPAR_XIICPS_0_INTR		XPS_I2C0_INT_ID
+#define XPAR_XIICPS_1_INTR		XPS_I2C1_INT_ID
+#define XPAR_XSPIPS_0_INTR		XPS_SPI0_INT_ID
+#define XPAR_XSPIPS_1_INTR		XPS_SPI1_INT_ID
+#define XPAR_XCANPS_0_INTR		XPS_CAN0_INT_ID
+#define XPAR_XCANPS_1_INTR		XPS_CAN1_INT_ID
+#define XPAR_XGPIOPS_0_INTR		XPS_GPIO_INT_ID
+#define XPAR_XEMACPS_0_INTR		XPS_GEM0_INT_ID
+#define XPAR_XEMACPS_0_WAKE_INTR	XPS_GEM0_WAKE_INT_ID
+#define XPAR_XEMACPS_1_INTR		XPS_GEM1_INT_ID
+#define XPAR_XEMACPS_1_WAKE_INTR	XPS_GEM1_WAKE_INT_ID
+#define XPAR_XSDIOPS_0_INTR		XPS_SDIO0_INT_ID
+#define XPAR_XQSPIPS_0_INTR		XPS_QSPI_INT_ID
+#define XPAR_XSDIOPS_1_INTR		XPS_SDIO1_INT_ID
+#define XPAR_XWDTPS_0_INTR		XPS_WDT_INT_ID
+#define XPAR_XDCFG_0_INTR		XPS_DVC_INT_ID
+#define XPAR_SCUTIMER_INTR		XPS_SCU_TMR_INT_ID
+#define XPAR_SCUWDT_INTR		XPS_SCU_WDT_INT_ID
+#define XPAR_XTTCPS_0_INTR		XPS_TTC0_0_INT_ID
+#define XPAR_XTTCPS_1_INTR		XPS_TTC0_1_INT_ID
+#define XPAR_XTTCPS_2_INTR		XPS_TTC0_2_INT_ID
+#define XPAR_XTTCPS_3_INTR		XPS_TTC1_0_INT_ID
+#define XPAR_XTTCPS_4_INTR		XPS_TTC1_1_INT_ID
+#define XPAR_XTTCPS_5_INTR		XPS_TTC1_2_INT_ID
+#define XPAR_XDMAPS_0_FAULT_INTR	XPS_DMA0_ABORT_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_0	XPS_DMA0_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_1	XPS_DMA1_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_2	XPS_DMA2_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_3	XPS_DMA3_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_4	XPS_DMA4_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_5	XPS_DMA5_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_6	XPS_DMA6_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_7	XPS_DMA7_INT_ID
+
+
+#define XPAR_XQSPIPS_0_LINEAR_BASEADDR	XPS_QSPI_LINEAR_BASEADDR
+#define XPAR_XPARPORTPS_CTRL_BASEADDR	XPS_PARPORT_CRTL_BASEADDR
+
+
+
+/* Canonical definitions for DMAC */
+
+
+/* Canonical definitions for WDT */
+
+/* Canonical definitions for SLCR */
+#define XPAR_XSLCR_NUM_INSTANCES	1U
+#define XPAR_XSLCR_0_DEVICE_ID		0U
+#define XPAR_XSLCR_0_BASEADDR		XPS_SYS_CTRL_BASEADDR
+
+/* Canonical definitions for SCU GIC */
+#define XPAR_SCUGIC_NUM_INSTANCES	1U
+#define XPAR_SCUGIC_SINGLE_DEVICE_ID	0U
+#define XPAR_SCUGIC_CPU_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00000100U)
+#define XPAR_SCUGIC_DIST_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00001000U)
+#define XPAR_SCUGIC_ACK_BEFORE		0U
+
+/* Canonical definitions for Global Timer */
+#define XPAR_GLOBAL_TMR_NUM_INSTANCES	1U
+#define XPAR_GLOBAL_TMR_DEVICE_ID	0U
+#define XPAR_GLOBAL_TMR_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00000200U)
+#define XPAR_GLOBAL_TMR_INTR		XPS_GLOBAL_TMR_INT_ID
+
+
+/* Xilinx Parallel Flash Library (XilFlash) User Settings */
+#define XPAR_AXI_EMC
+
+
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock. These have been put for bacwards compatibilty
+ */
+
+#define XPS_PERIPHERAL_BASEADDR		0xE0000000U
+#define XPS_UART0_BASEADDR		0xE0000000U
+#define XPS_UART1_BASEADDR		0xE0001000U
+#define XPS_USB0_BASEADDR		0xE0002000U
+#define XPS_USB1_BASEADDR		0xE0003000U
+#define XPS_I2C0_BASEADDR		0xE0004000U
+#define XPS_I2C1_BASEADDR		0xE0005000U
+#define XPS_SPI0_BASEADDR		0xE0006000U
+#define XPS_SPI1_BASEADDR		0xE0007000U
+#define XPS_CAN0_BASEADDR		0xE0008000U
+#define XPS_CAN1_BASEADDR		0xE0009000U
+#define XPS_GPIO_BASEADDR		0xE000A000U
+#define XPS_GEM0_BASEADDR		0xE000B000U
+#define XPS_GEM1_BASEADDR		0xE000C000U
+#define XPS_QSPI_BASEADDR		0xE000D000U
+#define XPS_PARPORT_CRTL_BASEADDR	0xE000E000U
+#define XPS_SDIO0_BASEADDR		0xE0100000U
+#define XPS_SDIO1_BASEADDR		0xE0101000U
+#define XPS_IOU_BUS_CFG_BASEADDR	0xE0200000U
+#define XPS_NAND_BASEADDR		0xE1000000U
+#define XPS_PARPORT0_BASEADDR		0xE2000000U
+#define XPS_PARPORT1_BASEADDR		0xE4000000U
+#define XPS_QSPI_LINEAR_BASEADDR	0xFC000000U
+#define XPS_SYS_CTRL_BASEADDR		0xF8000000U	/* AKA SLCR */
+#define XPS_TTC0_BASEADDR		0xF8001000U
+#define XPS_TTC1_BASEADDR		0xF8002000U
+#define XPS_DMAC0_SEC_BASEADDR		0xF8003000U
+#define XPS_DMAC0_NON_SEC_BASEADDR	0xF8004000U
+#define XPS_WDT_BASEADDR		0xF8005000U
+#define XPS_DDR_CTRL_BASEADDR		0xF8006000U
+#define XPS_DEV_CFG_APB_BASEADDR	0xF8007000U
+#define XPS_AFI0_BASEADDR		0xF8008000U
+#define XPS_AFI1_BASEADDR		0xF8009000U
+#define XPS_AFI2_BASEADDR		0xF800A000U
+#define XPS_AFI3_BASEADDR		0xF800B000U
+#define XPS_OCM_BASEADDR		0xF800C000U
+#define XPS_EFUSE_BASEADDR		0xF800D000U
+#define XPS_CORESIGHT_BASEADDR		0xF8800000U
+#define XPS_TOP_BUS_CFG_BASEADDR	0xF8900000U
+#define XPS_SCU_PERIPH_BASE		0xF8F00000U
+#define XPS_L2CC_BASEADDR		0xF8F02000U
+#define XPS_SAM_RAM_BASEADDR		0xFFFC0000U
+#define XPS_FPGA_AXI_S0_BASEADDR	0x40000000U
+#define XPS_FPGA_AXI_S1_BASEADDR	0x80000000U
+#define XPS_IOU_S_SWITCH_BASEADDR	0xE0000000U
+#define XPS_PERIPH_APB_BASEADDR		0xF8000000U
+
+/* Shared Peripheral Interrupts (SPI) */
+#define XPS_CORE_PARITY0_INT_ID		32U
+#define XPS_CORE_PARITY1_INT_ID		33U
+#define XPS_L2CC_INT_ID			34U
+#define XPS_OCMINTR_INT_ID		35U
+#define XPS_ECC_INT_ID			36U
+#define XPS_PMU0_INT_ID			37U
+#define XPS_PMU1_INT_ID			38U
+#define XPS_SYSMON_INT_ID		39U
+#define XPS_DVC_INT_ID			40U
+#define XPS_WDT_INT_ID			41U
+#define XPS_TTC0_0_INT_ID		42U
+#define XPS_TTC0_1_INT_ID		43U
+#define XPS_TTC0_2_INT_ID 		44U
+#define XPS_DMA0_ABORT_INT_ID		45U
+#define XPS_DMA0_INT_ID			46U
+#define XPS_DMA1_INT_ID			47U
+#define XPS_DMA2_INT_ID			48U
+#define XPS_DMA3_INT_ID			49U
+#define XPS_SMC_INT_ID			50U
+#define XPS_QSPI_INT_ID			51U
+#define XPS_GPIO_INT_ID			52U
+#define XPS_USB0_INT_ID			53U
+#define XPS_GEM0_INT_ID			54U
+#define XPS_GEM0_WAKE_INT_ID		55U
+#define XPS_SDIO0_INT_ID		56U
+#define XPS_I2C0_INT_ID			57U
+#define XPS_SPI0_INT_ID			58U
+#define XPS_UART0_INT_ID		59U
+#define XPS_CAN0_INT_ID			60U
+#define XPS_FPGA0_INT_ID		61U
+#define XPS_FPGA1_INT_ID		62U
+#define XPS_FPGA2_INT_ID		63U
+#define XPS_FPGA3_INT_ID		64U
+#define XPS_FPGA4_INT_ID		65U
+#define XPS_FPGA5_INT_ID		66U
+#define XPS_FPGA6_INT_ID		67U
+#define XPS_FPGA7_INT_ID		68U
+#define XPS_TTC1_0_INT_ID		69U
+#define XPS_TTC1_1_INT_ID		70U
+#define XPS_TTC1_2_INT_ID		71U
+#define XPS_DMA4_INT_ID			72U
+#define XPS_DMA5_INT_ID			73U
+#define XPS_DMA6_INT_ID			74U
+#define XPS_DMA7_INT_ID			75U
+#define XPS_USB1_INT_ID			76U
+#define XPS_GEM1_INT_ID			77U
+#define XPS_GEM1_WAKE_INT_ID		78U
+#define XPS_SDIO1_INT_ID		79U
+#define XPS_I2C1_INT_ID			80U
+#define XPS_SPI1_INT_ID			81U
+#define XPS_UART1_INT_ID		82U
+#define XPS_CAN1_INT_ID			83U
+#define XPS_FPGA8_INT_ID		84U
+#define XPS_FPGA9_INT_ID		85U
+#define XPS_FPGA10_INT_ID		86U
+#define XPS_FPGA11_INT_ID		87U
+#define XPS_FPGA12_INT_ID		88U
+#define XPS_FPGA13_INT_ID		89U
+#define XPS_FPGA14_INT_ID		90U
+#define XPS_FPGA15_INT_ID		91U
+
+/* Private Peripheral Interrupts (PPI) */
+#define XPS_GLOBAL_TMR_INT_ID		27U	/* SCU Global Timer interrupt */
+#define XPS_FIQ_INT_ID			28U	/* FIQ from FPGA fabric */
+#define XPS_SCU_TMR_INT_ID		29U	/* SCU Private Timer interrupt */
+#define XPS_SCU_WDT_INT_ID		30U	/* SCU Private WDT interrupt */
+#define XPS_IRQ_INT_ID			31U	/* IRQ from FPGA fabric */
+
+
+/* REDEFINES for TEST APP */
+/* Definitions for UART */
+#define XPAR_PS7_UART_0_INTR		XPS_UART0_INT_ID
+#define XPAR_PS7_UART_1_INTR		XPS_UART1_INT_ID
+#define XPAR_PS7_USB_0_INTR		XPS_USB0_INT_ID
+#define XPAR_PS7_USB_1_INTR		XPS_USB1_INT_ID
+#define XPAR_PS7_I2C_0_INTR		XPS_I2C0_INT_ID
+#define XPAR_PS7_I2C_1_INTR		XPS_I2C1_INT_ID
+#define XPAR_PS7_SPI_0_INTR		XPS_SPI0_INT_ID
+#define XPAR_PS7_SPI_1_INTR		XPS_SPI1_INT_ID
+#define XPAR_PS7_CAN_0_INTR		XPS_CAN0_INT_ID
+#define XPAR_PS7_CAN_1_INTR		XPS_CAN1_INT_ID
+#define XPAR_PS7_GPIO_0_INTR		XPS_GPIO_INT_ID
+#define XPAR_PS7_ETHERNET_0_INTR	XPS_GEM0_INT_ID
+#define XPAR_PS7_ETHERNET_0_WAKE_INTR	XPS_GEM0_WAKE_INT_ID
+#define XPAR_PS7_ETHERNET_1_INTR	XPS_GEM1_INT_ID
+#define XPAR_PS7_ETHERNET_1_WAKE_INTR	XPS_GEM1_WAKE_INT_ID
+#define XPAR_PS7_QSPI_0_INTR		XPS_QSPI_INT_ID
+#define XPAR_PS7_WDT_0_INTR		XPS_WDT_INT_ID
+#define XPAR_PS7_SCUWDT_0_INTR		XPS_SCU_WDT_INT_ID
+#define XPAR_PS7_SCUTIMER_0_INTR	XPS_SCU_TMR_INT_ID
+#define XPAR_PS7_XADC_0_INTR		XPS_SYSMON_INT_ID
+#define XPAR_PS7_TTC_0_INTR         XPS_TTC0_0_INT_ID
+#define XPAR_PS7_TTC_1_INTR         XPS_TTC0_1_INT_ID
+#define XPAR_PS7_TTC_2_INTR         XPS_TTC0_2_INT_ID
+#define XPAR_PS7_TTC_3_INTR         XPS_TTC1_0_INT_ID
+#define XPAR_PS7_TTC_4_INTR         XPS_TTC1_1_INT_ID
+#define XPAR_PS7_TTC_5_INTR         XPS_TTC1_2_INT_ID
+
+#define XPAR_XADCPS_INT_ID		XPS_SYSMON_INT_ID
+
+/* For backwards compatibilty */
+#define XPAR_XUARTPS_0_CLOCK_HZ		XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
+#define XPAR_XUARTPS_1_CLOCK_HZ		XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
+#define XPAR_XTTCPS_0_CLOCK_HZ		XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_1_CLOCK_HZ		XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_2_CLOCK_HZ		XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_3_CLOCK_HZ		XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_4_CLOCK_HZ		XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_5_CLOCK_HZ		XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
+#define XPAR_XIICPS_0_CLOCK_HZ		XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
+#define XPAR_XIICPS_1_CLOCK_HZ		XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
+
+#define XPAR_XQSPIPS_0_CLOCK_HZ		XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
+
+#ifdef XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+#endif
+
+#ifdef XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
+#endif
+
+#define XPAR_SCUTIMER_DEVICE_ID		0U
+#define XPAR_SCUWDT_DEVICE_ID		0U
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xplatform_info.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xplatform_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..27c0b58510fb77da17a9e7d2727c7ef27c3ecad5
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xplatform_info.h
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xplatform_info.h
+*
+* @addtogroup common_platform_info APIs to Get Platform Information
+*
+* The xplatform_info.h file contains definitions for various available Xilinx&reg;
+* platforms. Also, it contains prototype of APIs, which can be used to get the
+* platform information.
+*
+* @{
+******************************************************************************/
+
+#ifndef XPLATFORM_INFO_H		/* prevent circular inclusions */
+#define XPLATFORM_INFO_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XPAR_CSU_BASEADDR 0xFFCA0000U
+#define	XPAR_CSU_VER_OFFSET 0x00000044U
+
+#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
+#define XPLAT_ZYNQ_ULTRA_MP 0x1
+#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2
+#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3
+#define XPLAT_ZYNQ 0x4
+#define XPLAT_MICROBLAZE 0x5
+
+#define XPS_VERSION_1 0x0
+#define XPS_VERSION_2 0x1
+
+#define XPLAT_INFO_MASK (0xF)
+#define XPS_VERSION_INFO_MASK (0xF)
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+u32 XGetPlatform_Info();
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGetPSVersion_Info();
+#endif
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGet_Zynq_UltraMp_Platform_info();
+#endif
+/************************** Function Prototypes ******************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_platform_info".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xpm_counter.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xpm_counter.h
new file mode 100644
index 0000000000000000000000000000000000000000..45f091982497d96d757ce80559712dbd227905e6
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xpm_counter.h
@@ -0,0 +1,575 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpm_counter.h
+*
+* @addtogroup a9_event_counter_apis Cortex A9 Event Counters Functions
+*
+* Cortex A9 event counter functions can be utilized to configure and control
+* the Cortex-A9 performance monitor events.
+*
+* Cortex-A9 performance monitor has six event counters which can be used to
+* count a variety of events described in Coretx-A9 TRM. xpm_counter.h defines
+* configurations XPM_CNTRCFGx which can be used to program the event counters
+* to count a set of events.
+*
+* @note
+* It doesn't handle the Cortex-A9 cycle counter, as the cycle counter is
+* being used for time keeping.
+*
+* @{
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XPMCOUNTER_H /* prevent circular inclusions */
+#define XPMCOUNTER_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include <stdint.h>
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/* Number of performance counters */
+#define XPM_CTRCOUNT 6U
+
+/* The following constants define the Cortex-A9 Performance Monitor Events */
+
+/*
+ * Software increment. The register is incremented only on writes to the
+ * Software Increment Register
+ */
+#define XPM_EVENT_SOFTINCR 0x00U
+
+/*
+ * Instruction fetch that causes a refill at (at least) the lowest level(s) of
+ * instruction or unified cache. Includes the speculative linefills in the
+ * count
+ */
+#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U
+
+/*
+ * Instruction fetch that causes a TLB refill at (at least) the lowest level of
+ * TLB. Includes the speculative requests in the count
+ */
+#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U
+
+/*
+ * Data read or write operation that causes a refill at (at least) the lowest
+ * level(s)of data or unified cache. Counts the number of allocations performed
+ * in the Data Cache due to a read or a write
+ */
+#define XPM_EVENT_DATA_CACHEREFILL 0x03U
+
+/*
+ * Data read or write operation that causes a cache access at (at least) the
+ * lowest level(s) of data or unified cache. This includes speculative reads
+ */
+#define XPM_EVENT_DATA_CACHEACCESS 0x04U
+
+/*
+ * Data read or write operation that causes a TLB refill at (at least) the
+ * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI,
+ * CP15 Cache operation by MVA and CP15 VA to PA operations
+ */
+#define XPM_EVENT_DATA_TLBREFILL 0x05U
+
+/*
+ * Data read architecturally executed. Counts the number of data read
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted LDR/LDM, as well as the reads due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_READS 0x06U
+
+/*
+ * Data write architecturally executed. Counts the number of data write
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted STR/STM, as well as the writes due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_WRITE 0x07U
+
+/* Exception taken. Counts the number of exceptions architecturally taken.*/
+#define XPM_EVENT_EXCEPTION 0x09U
+
+/* Exception return architecturally executed.*/
+#define XPM_EVENT_EXCEPRETURN 0x0AU
+
+/*
+ * Change to ContextID retired. Counts the number of instructions
+ * architecturally executed writing into the ContextID Register
+ */
+#define XPM_EVENT_CHANGECONTEXT 0x0BU
+
+/*
+ * Software change of PC, except by an exception, architecturally executed.
+ * Count the number of PC changes architecturally executed, excluding the PC
+ * changes due to taken exceptions
+ */
+#define XPM_EVENT_SW_CHANGEPC 0x0CU
+
+/*
+ * Immediate branch architecturally executed (taken or not taken). This includes
+ * the branches which are flushed due to a previous load/store which aborts
+ * late
+ */
+#define XPM_EVENT_IMMEDBRANCH 0x0DU
+
+/*
+ * Unaligned access architecturally executed. Counts the number of aborted
+ * unaligned accessed architecturally executed, and the number of not-aborted
+ * unaligned accesses, including the speculative ones
+ */
+#define XPM_EVENT_UNALIGNEDACCESS 0x0FU
+
+/*
+ * Branch mispredicted/not predicted. Counts the number of mispredicted or
+ * not-predicted branches executed. This includes the branches which are flushed
+ * due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHMISS 0x10U
+
+/*
+ * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This
+ * event is not exported on the PMUEVENT bus
+ */
+#define XPM_EVENT_CLOCKCYCLES 0x11U
+
+/*
+ * Branches or other change in program flow that could have been predicted by
+ * the branch prediction resources of the processor. This includes the branches
+ * which are flushed due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHPREDICT 0x12U
+
+/*
+ * Java bytecode execute. Counts the number of Java bytecodes being decoded,
+ * including speculative ones
+ */
+#define XPM_EVENT_JAVABYTECODE 0x40U
+
+/*
+ * Software Java bytecode executed. Counts the number of software java bytecodes
+ * being decoded, including speculative ones
+ */
+#define XPM_EVENT_SWJAVABYTECODE 0x41U
+
+/*
+ * Jazelle backward branches executed. Counts the number of Jazelle taken
+ * branches being executed. This includes the branches which are flushed due
+ * to a previous load/store which aborts late
+ */
+#define XPM_EVENT_JAVABACKBRANCH 0x42U
+
+/*
+ * Coherent linefill miss Counts the number of coherent linefill requests
+ * performed by the Cortex-A9 processor which also miss in all the other
+ * Cortex-A9 processors, meaning that the request is sent to the external
+ * memory
+ */
+#define XPM_EVENT_COHERLINEMISS 0x50U
+
+/*
+ * Coherent linefill hit. Counts the number of coherent linefill requests
+ * performed by the Cortex-A9 processor which hit in another Cortex-A9
+ * processor, meaning that the linefill data is fetched directly from the
+ * relevant Cortex-A9 cache
+ */
+#define XPM_EVENT_COHERLINEHIT 0x51U
+
+/*
+ * Instruction cache dependent stall cycles. Counts the number of cycles where
+ * the processor is ready to accept new instructions, but does not receive any
+ * due to the instruction side not being able to provide any and the
+ * instruction cache is currently performing at least one linefill
+ */
+#define XPM_EVENT_INSTRSTALL 0x60U
+
+/*
+ * Data cache dependent stall cycles. Counts the number of cycles where the core
+ * has some instructions that it cannot issue to any pipeline, and the Load
+ * Store unit has at least one pending linefill request, and no pending
+ */
+#define XPM_EVENT_DATASTALL 0x61U
+
+/*
+ * Main TLB miss stall cycles. Counts the number of cycles where the processor
+ * is stalled waiting for the completion of translation table walks from the
+ * main TLB. The processor stalls can be due to the instruction side not being
+ * able to provide the instructions, or to the data side not being able to
+ * provide the necessary data, due to them waiting for the main TLB translation
+ * table walk to complete
+ */
+#define XPM_EVENT_MAINTLBSTALL 0x62U
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * passed
+ */
+#define XPM_EVENT_STREXPASS 0x63U
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * failed
+ */
+#define XPM_EVENT_STREXFAIL 0x64U
+
+/*
+ * Data eviction. Counts the number of eviction requests due to a linefill in
+ * the data cache
+ */
+#define XPM_EVENT_DATAEVICT 0x65U
+
+/*
+ * Counts the number of cycles where the issue stage does not dispatch any
+ * instruction because it is empty or cannot dispatch any instructions
+ */
+#define XPM_EVENT_NODISPATCH 0x66U
+
+/*
+ * Counts the number of cycles where the issue stage is empty
+ */
+#define XPM_EVENT_ISSUEEMPTY 0x67U
+
+/*
+ * Counts the number of instructions going through the Register Renaming stage.
+ * This number is an approximate number of the total number of instructions
+ * speculatively executed, and even more approximate of the total number of
+ * instructions architecturally executed. The approximation depends mainly on
+ * the branch misprediction rate.
+ * The renaming stage can handle two instructions in the same cycle so the event
+ * is two bits long:
+ *    - b00 no instructions renamed
+ *    - b01 one instruction renamed
+ *    - b10 two instructions renamed
+ */
+#define XPM_EVENT_INSTRRENAME 0x68U
+
+/*
+ * Counts the number of procedure returns whose condition codes do not fail,
+ * excluding all returns from exception. This count includes procedure returns
+ * which are flushed due to a previous load/store which aborts late.
+ * Only the following instructions are reported:
+ * - BX R14
+ * - MOV PC LR
+ * - POP {..,pc}
+ * - LDR pc,[sp],#offset
+ * The following instructions are not reported:
+ * - LDMIA R9!,{..,PC} (ThumbEE state only)
+ * - LDR PC,[R9],#offset (ThumbEE state only)
+ * - BX R0 (Rm != R14)
+ * - MOV PC,R0 (Rm != R14)
+ * - LDM SP,{...,PC} (writeback not specified)
+ * - LDR PC,[SP,#offset] (wrong addressing mode)
+ */
+#define XPM_EVENT_PREDICTFUNCRET 0x6EU
+
+/*
+ * Counts the number of instructions being executed in the main execution
+ * pipeline of the processor, the multiply pipeline and arithmetic logic unit
+ * pipeline. The counted instructions are still speculative
+ */
+#define XPM_EVENT_MAINEXEC 0x70U
+
+/*
+ * Counts the number of instructions being executed in the processor second
+ * execution pipeline (ALU). The counted instructions are still speculative
+ */
+#define XPM_EVENT_SECEXEC 0x71U
+
+/*
+ * Counts the number of instructions being executed in the Load/Store unit. The
+ * counted instructions are still speculative
+ */
+#define XPM_EVENT_LDRSTR 0x72U
+
+/*
+ * Counts the number of Floating-point instructions going through the Register
+ * Rename stage. Instructions are still speculative in this stage.
+ *Two floating-point instructions can be renamed in the same cycle so the event
+ * is two bitslong:
+ *0b00 no floating-point instruction renamed
+ *0b01 one floating-point instruction renamed
+ *0b10 two floating-point instructions renamed
+ */
+#define XPM_EVENT_FLOATRENAME 0x73U
+
+/*
+ * Counts the number of Neon instructions going through the Register Rename
+ * stage.Instructions are still speculative in this stage.
+ * Two NEON instructions can be renamed in the same cycle so the event is two
+ * bits long:
+ *0b00 no NEON instruction renamed
+ *0b01 one NEON instruction renamed
+ *0b10 two NEON instructions renamed
+ */
+#define XPM_EVENT_NEONRENAME 0x74U
+
+/*
+ * Counts the number of cycles where the processor is stalled because PLD slots
+ * are all full
+ */
+#define XPM_EVENT_PLDSTALL 0x80U
+
+/*
+ * Counts the number of cycles when the processor is stalled and the data side
+ * is stalled too because it is full and executing writes to the external
+ * memory
+ */
+#define XPM_EVENT_WRITESTALL 0x81U
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the instruction side
+ */
+#define XPM_EVENT_INSTRTLBSTALL 0x82U
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the data side
+ */
+#define XPM_EVENT_DATATLBSTALL 0x83U
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the instruction
+ * side. This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_INSTR_uTLBSTALL 0x84U
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the data side.
+ * This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_DATA_uTLBSTALL 0x85U
+
+/*
+ * Counts the number of stall cycles because of the execution of a DMB memory
+ * barrier. This includes all DMB instructions being executed, even
+ * speculatively
+ */
+#define XPM_EVENT_DMB_STALL 0x86U
+
+/*
+ * Counts the number of cycles during which the integer core clock is enabled
+ */
+#define XPM_EVENT_INT_CLKEN 0x8AU
+
+/*
+ * Counts the number of cycles during which the Data Engine clock is enabled
+ */
+#define XPM_EVENT_DE_CLKEN 0x8BU
+
+/*
+ * Counts the number of ISB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRISB 0x90U
+
+/*
+ * Counts the number of DSB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRDSB 0x91U
+
+/*
+ * Counts the number of DMB instructions speculatively executed
+ */
+#define XPM_EVENT_INSTRDMB 0x92U
+
+/*
+ * Counts the number of external interrupts executed by the processor
+ */
+#define XPM_EVENT_EXTINT 0x93U
+
+/*
+ * PLE cache line request completed
+ */
+#define XPM_EVENT_PLE_LRC 0xA0U
+
+/*
+ * PLE cache line request skipped
+ */
+#define XPM_EVENT_PLE_LRS 0xA1U
+
+/*
+ * PLE FIFO flush
+ */
+#define XPM_EVENT_PLE_FLUSH 0xA2U
+
+/*
+ * PLE request complete
+ */
+#define XPM_EVENT_PLE_CMPL 0xA3U
+
+/*
+ * PLE FIFO overflow
+ */
+#define XPM_EVENT_PLE_OVFL 0xA4U
+
+/*
+ * PLE request programmed
+ */
+#define XPM_EVENT_PLE_PROG 0xA5U
+
+/*
+ * The following constants define the configurations for Cortex-A9 Performance
+ * Monitor Events. Each configuration configures the event counters for a set
+ * of events.
+ * -----------------------------------------------
+ * Config		PmCtr0... PmCtr5
+ * -----------------------------------------------
+ * XPM_CNTRCFG1		{ XPM_EVENT_SOFTINCR,
+ *			  XPM_EVENT_INSRFETCH_CACHEREFILL,
+ *			  XPM_EVENT_INSTRFECT_TLBREFILL,
+ *			  XPM_EVENT_DATA_CACHEREFILL,
+ *			  XPM_EVENT_DATA_CACHEACCESS,
+ *			  XPM_EVENT_DATA_TLBREFILL }
+ *
+ * XPM_CNTRCFG2		{ XPM_EVENT_DATA_READS,
+ *			  XPM_EVENT_DATA_WRITE,
+ *			  XPM_EVENT_EXCEPTION,
+ *			  XPM_EVENT_EXCEPRETURN,
+ *			  XPM_EVENT_CHANGECONTEXT,
+ *			  XPM_EVENT_SW_CHANGEPC }
+ *
+ * XPM_CNTRCFG3		{ XPM_EVENT_IMMEDBRANCH,
+ *			  XPM_EVENT_UNALIGNEDACCESS,
+ *			  XPM_EVENT_BRANCHMISS,
+ *			  XPM_EVENT_CLOCKCYCLES,
+ *			  XPM_EVENT_BRANCHPREDICT,
+ *			  XPM_EVENT_JAVABYTECODE }
+ *
+ * XPM_CNTRCFG4		{ XPM_EVENT_SWJAVABYTECODE,
+ *			  XPM_EVENT_JAVABACKBRANCH,
+ *			  XPM_EVENT_COHERLINEMISS,
+ *			  XPM_EVENT_COHERLINEHIT,
+ *			  XPM_EVENT_INSTRSTALL,
+ *			  XPM_EVENT_DATASTALL }
+ *
+ * XPM_CNTRCFG5		{ XPM_EVENT_MAINTLBSTALL,
+ *			  XPM_EVENT_STREXPASS,
+ *			  XPM_EVENT_STREXFAIL,
+ *			  XPM_EVENT_DATAEVICT,
+ *			  XPM_EVENT_NODISPATCH,
+ *			  XPM_EVENT_ISSUEEMPTY }
+ *
+ * XPM_CNTRCFG6		{ XPM_EVENT_INSTRRENAME,
+ *			  XPM_EVENT_PREDICTFUNCRET,
+ *			  XPM_EVENT_MAINEXEC,
+ *			  XPM_EVENT_SECEXEC,
+ *			  XPM_EVENT_LDRSTR,
+ *			  XPM_EVENT_FLOATRENAME }
+ *
+ * XPM_CNTRCFG7		{ XPM_EVENT_NEONRENAME,
+ *			  XPM_EVENT_PLDSTALL,
+ *			  XPM_EVENT_WRITESTALL,
+ *			  XPM_EVENT_INSTRTLBSTALL,
+ *			  XPM_EVENT_DATATLBSTALL,
+ *			  XPM_EVENT_INSTR_uTLBSTALL }
+ *
+ * XPM_CNTRCFG8		{ XPM_EVENT_DATA_uTLBSTALL,
+ *			  XPM_EVENT_DMB_STALL,
+ *			  XPM_EVENT_INT_CLKEN,
+ *			  XPM_EVENT_DE_CLKEN,
+ *			  XPM_EVENT_INSTRISB,
+ *			  XPM_EVENT_INSTRDSB }
+ *
+ * XPM_CNTRCFG9		{ XPM_EVENT_INSTRDMB,
+ *			  XPM_EVENT_EXTINT,
+ *			  XPM_EVENT_PLE_LRC,
+ *			  XPM_EVENT_PLE_LRS,
+ *			  XPM_EVENT_PLE_FLUSH,
+ *			  XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG10	{ XPM_EVENT_PLE_OVFL,
+ *			  XPM_EVENT_PLE_PROG,
+ *			  XPM_EVENT_PLE_LRC,
+ *			  XPM_EVENT_PLE_LRS,
+ *			  XPM_EVENT_PLE_FLUSH,
+ *			  XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG11	{ XPM_EVENT_DATASTALL,
+ *			  XPM_EVENT_INSRFETCH_CACHEREFILL,
+ *			  XPM_EVENT_INSTRFECT_TLBREFILL,
+ *			  XPM_EVENT_DATA_CACHEREFILL,
+ *			  XPM_EVENT_DATA_CACHEACCESS,
+ *			  XPM_EVENT_DATA_TLBREFILL }
+ */
+#define XPM_CNTRCFG1	0
+#define XPM_CNTRCFG2	1
+#define XPM_CNTRCFG3	2
+#define XPM_CNTRCFG4	3
+#define XPM_CNTRCFG5	4
+#define XPM_CNTRCFG6	5
+#define XPM_CNTRCFG7	6
+#define XPM_CNTRCFG8	7
+#define XPM_CNTRCFG9	8
+#define XPM_CNTRCFG10	9
+#define XPM_CNTRCFG11	10
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/* Interface fuctions to access perfromance counters from abstraction layer */
+void Xpm_SetEvents(s32 PmcrCfg);
+void Xpm_GetEventCounters(u32 *PmCtrValue);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_event_counter_apis".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xpseudo_asm.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xpseudo_asm.h
new file mode 100644
index 0000000000000000000000000000000000000000..4ad9e5d73cf6aa041462b24325df210f40a23bd4
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xpseudo_asm.h
@@ -0,0 +1,77 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm.h
+*
+* @addtogroup a9_specific Cortex A9 Processor Specific Include Files
+*
+* The xpseudo_asm.h includes xreg_cortexa9.h and xpseudo_asm_gcc.h.
+*
+* The xreg_cortexa9.h file contains definitions for inline assembler code.
+* It provides inline definitions for Cortex A9 GPRs, SPRs, MPE registers,
+* co-processor registers and Debug registers.
+*
+* The xpseudo_asm_gcc.h contains the definitions for the most often used inline
+* assembler instructions, available as macros. These can be very useful for
+* tasks such as setting or getting special purpose registers, synchronization,
+* or cache manipulation etc. These inline assembler instructions can be used
+* from drivers and user applications written in C.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  10/18/09 First release
+* 3.04a sdm  01/02/12 Remove redundant dsb in mcr instruction.
+* </pre>
+*
+******************************************************************************/
+#ifndef XPSEUDO_ASM_H
+#define XPSEUDO_ASM_H
+
+#include "xreg_cortexa9.h"
+#ifdef __GNUC__
+ #include "xpseudo_asm_gcc.h"
+#elif defined (__ICCARM__)
+ #include "xpseudo_asm_iccarm.h"
+#else
+ #include "xpseudo_asm_rvct.h"
+#endif
+
+#endif /* XPSEUDO_ASM_H */
+/**
+* @} End of "addtogroup a9_specific".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xpseudo_asm_gcc.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xpseudo_asm_gcc.h
new file mode 100644
index 0000000000000000000000000000000000000000..1b67263940395d2ba4ce4fed0cc00c3327d9a44a
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xpseudo_asm_gcc.h
@@ -0,0 +1,249 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm_gcc.h
+*
+* This header file contains macros for using inline assembler code. It is
+* written specifically for the GNU compiler.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp		 05/21/14 First release
+* 6.0   mus      07/27/16 Consolidated file for a53,a9 and r5 processors
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XPSEUDO_ASM_GCC_H  /* prevent circular inclusions */
+#define XPSEUDO_ASM_GCC_H  /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/* necessary for pre-processor */
+#define stringify(s)	tostring(s)
+#define tostring(s)	#s
+
+#if defined (__aarch64__)
+/* pseudo assembler instructions */
+#define mfcpsr()	({u32 rval = 0U; \
+			   asm volatile("mrs %0,  DAIF" : "=r" (rval));\
+			  rval;\
+			 })
+
+#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v))
+
+#define cpsiei()	//__asm__ __volatile__("cpsie	i\n")
+#define cpsidi()	//__asm__ __volatile__("cpsid	i\n")
+
+#define cpsief()	//__asm__ __volatile__("cpsie	f\n")
+#define cpsidf()	//__asm__ __volatile__("cpsid	f\n")
+
+
+
+#define mtgpr(rn, v)	/*__asm__ __volatile__(\
+			  "mov r" stringify(rn) ", %0 \n"\
+			  : : "r" (v)\
+			)*/
+
+#define mfgpr(rn)	/*({u32 rval; \
+			  __asm__ __volatile__(\
+			    "mov %0,r" stringify(rn) "\n"\
+			    : "=r" (rval)\
+			  );\
+			  rval;\
+			 })*/
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb sy")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__("dsb sy")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__("dmb sy")
+
+
+/* Memory Operations */
+#define ldr(adr)	({u64 rval; \
+			  __asm__ __volatile__(\
+			    "ldr	%0,[%1]"\
+			    : "=r" (rval) : "r" (adr)\
+			  );\
+			  rval;\
+			 })
+
+#else
+
+/* pseudo assembler instructions */
+#define mfcpsr()	({u32 rval = 0U; \
+			  __asm__ __volatile__(\
+			    "mrs	%0, cpsr\n"\
+			    : "=r" (rval)\
+			  );\
+			  rval;\
+			 })
+
+#define mtcpsr(v)	__asm__ __volatile__(\
+			  "msr	cpsr,%0\n"\
+			  : : "r" (v)\
+			)
+
+#define cpsiei()	__asm__ __volatile__("cpsie	i\n")
+#define cpsidi()	__asm__ __volatile__("cpsid	i\n")
+
+#define cpsief()	__asm__ __volatile__("cpsie	f\n")
+#define cpsidf()	__asm__ __volatile__("cpsid	f\n")
+
+
+
+#define mtgpr(rn, v)	__asm__ __volatile__(\
+			  "mov r" stringify(rn) ", %0 \n"\
+			  : : "r" (v)\
+			)
+
+#define mfgpr(rn)	({u32 rval; \
+			  __asm__ __volatile__(\
+			    "mov %0,r" stringify(rn) "\n"\
+			    : "=r" (rval)\
+			  );\
+			  rval;\
+			 })
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
+
+
+/* Memory Operations */
+#define ldr(adr)	({u32 rval; \
+			  __asm__ __volatile__(\
+			    "ldr	%0,[%1]"\
+			    : "=r" (rval) : "r" (adr)\
+			  );\
+			  rval;\
+			 })
+
+#endif
+
+#define ldrb(adr)	({u8 rval; \
+			  __asm__ __volatile__(\
+			    "ldrb	%0,[%1]"\
+			    : "=r" (rval) : "r" (adr)\
+			  );\
+			  rval;\
+			 })
+
+#define str(adr, val)	__asm__ __volatile__(\
+			  "str	%0,[%1]\n"\
+			  : : "r" (val), "r" (adr)\
+			)
+
+#define strb(adr, val)	__asm__ __volatile__(\
+			  "strb	%0,[%1]\n"\
+			  : : "r" (val), "r" (adr)\
+			)
+
+/* Count leading zeroes (clz) */
+#define clz(arg)	({u8 rval; \
+			  __asm__ __volatile__(\
+			    "clz	%0,%1"\
+			    : "=r" (rval) : "r" (arg)\
+			  );\
+			  rval;\
+			 })
+
+#if defined (__aarch64__)
+#define mtcpdc(reg,val)	__asm__ __volatile__("dc " #reg ",%0"  : : "r" (val))
+#define mtcpic(reg,val)	__asm__ __volatile__("ic " #reg ",%0"  : : "r" (val))
+
+#define mtcpicall(reg)	__asm__ __volatile__("ic " #reg)
+#define mtcptlbi(reg)	__asm__ __volatile__("tlbi " #reg)
+#define mtcpat(reg,val)	__asm__ __volatile__("at " #reg ",%0"  : : "r" (val))
+/* CP15 operations */
+#define mfcp(reg)	({u64 rval = 0U;\
+			__asm__ __volatile__("mrs	%0, " #reg : "=r" (rval));\
+			rval;\
+			})
+
+#define mtcp(reg,val)	__asm__ __volatile__("msr " #reg ",%0"  : : "r" (val))
+
+#else
+/* CP15 operations */
+#define mtcp(rn, v)	__asm__ __volatile__(\
+			 "mcr " rn "\n"\
+			 : : "r" (v)\
+			);
+
+#define mfcp(rn)	({u32 rval = 0U; \
+			 __asm__ __volatile__(\
+			   "mrc " rn "\n"\
+			   : "=r" (rval)\
+			 );\
+			 rval;\
+			 })
+#endif
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XPSEUDO_ASM_GCC_H */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xqspips.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xqspips.h
new file mode 100644
index 0000000000000000000000000000000000000000..671f3f636e7a1031268756757e9bfa538d547e85
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xqspips.h
@@ -0,0 +1,793 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips.h
+* @addtogroup qspips_v3_2
+* @{
+* @details
+*
+* This file contains the implementation of the XQspiPs driver. It supports only
+* master mode. User documentation for the driver functions is contained in this
+* file in the form of comment blocks at the front of each function.
+*
+* A QSPI device connects to an QSPI bus through a 4-wire serial interface.
+* The QSPI bus is a full-duplex, synchronous bus that facilitates communication
+* between one master and one slave. The device is always full-duplex,
+* which means that for every byte sent, one is received, and vice-versa.
+* The master controls the clock, so it can regulate when it wants to
+* send or receive data. The slave is under control of the master, it must
+* respond quickly since it has no control of the clock and must send/receive
+* data as fast or as slow as the master does.
+*
+* <b> Linear Mode </b>
+* The Linear Quad-SPI Controller extends the existing Quad-SPI Controller�s
+* functionality by adding a linear addressing scheme that allows the SPI flash
+* memory subsystem to behave like a typical ROM device.  The new feature hides
+* the normal SPI protocol from a master reading from the SPI flash memory. The
+* feature improves both the user friendliness and the overall read memory
+* throughput over that of the current Quad-SPI Controller by lessening the
+* amount of software overheads required and by the use of the faster AXI
+* interface.
+*
+* <b>Initialization & Configuration</b>
+*
+* The XQspiPs_Config structure is used by the driver to configure itself. This
+* configuration structure is typically created by the tool-chain based on HW
+* build properties.
+*
+* To support multiple runtime loading and initialization strategies employed by
+* various operating systems, the driver instance can be initialized in the
+* following way:
+*	- XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find
+*	  static configuration structure defined in xqspips_g.c. This is setup
+*	  by the tools. For some operating systems the config structure will be
+*	  initialized by the software and this call is not needed.
+*	- XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+*	  configuration structure provided by the caller. If running in a system
+*	  with address translation, the provided virtual memory base address
+*	  replaces the physical address present in the configuration structure.
+*
+* <b>Multiple Masters</b>
+*
+* More than one master can exist, but arbitration is the responsibility of
+* the higher layer software. The device driver does not perform any type of
+* arbitration.
+*
+* <b>Modes of Operation</b>
+*
+* There are four modes to perform a data transfer and the selection of a mode
+* is based on Chip Select(CS) and Start. These two options individually, can
+* be controlled either by software(Manual) or hardware(Auto).
+* - Auto CS: Chip select is automatically asserted as soon as the first word
+*	     is written into the TXFIFO and de asserted when the TXFIFO becomes
+*	     empty
+* - Manual CS: Software must assert and de assert CS.
+* - Auto Start: Data transmission starts as soon as there is data in the
+*		TXFIFO and stalls when the TXFIFO is empty
+* - Manual Start: Software must start data transmission at the beginning of
+*		  the transaction or whenever the TXFIFO has become empty
+*
+* The preferred combination is Manual CS and Auto Start.
+* In this combination, the software asserts CS before loading any data into
+* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it
+* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the
+* data is available. If no further data, software disables CS.
+*
+* Risks/challenges of other combinations:
+* - Manual CS and Manual Start: Manual Start bit should be set after each
+*   TXFIFO write otherwise there could be a race condition where the TXFIFO
+*   becomes empty before the new word is written. In that case the
+*   transmission stops.
+* - Auto CS with Manual or Auto Start: It is very difficult for software to
+*   keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted.
+*   This results in a single transaction to be split into multiple pieces each
+*   with its own chip select. This will result in garbage data to be sent.
+*
+* <b>Interrupts</b>
+*
+* The user must connect the interrupt handler of the driver,
+* XQspiPs_InterruptHandler, to an interrupt system such that it will be
+* called when an interrupt occurs. This function does not save and restore
+* the processor context such that the user must provide this processing.
+*
+* The driver handles the following interrupts:
+* - Data Transmit Register/FIFO Underflow
+* - Data Receive Register/FIFO Not Empty
+* - Data Transmit Register/FIFO Overwater
+* - Data Receive Register/FIFO Overrun
+*
+* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the
+* QSPI device has transmitted the data available to transmit, and now its data
+* register and FIFO is ready to accept more data. The driver uses this
+* interrupt to indicate progress while sending data.  The driver may have
+* more data to send, in which case the data transmit register and FIFO is
+* filled for subsequent transmission. When this interrupt arrives and all
+* the data has been sent, the driver invokes the status callback with a
+* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that
+* all data has been sent.
+*
+* The Data Transmit Register/FIFO Underflow interrupt -- indicates that,
+* as slave, the QSPI device was required to transmit but there was no data
+* available to transmit in the transmit register (or FIFO). This may not
+* be an error if the master is not expecting data. But in the case where
+* the master is expecting data, this serves as a notification of such a
+* condition. The driver reports this condition to the upper layer
+* software through the status handler.
+*
+* The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI
+* device received data and subsequently dropped the data because the data
+* receive register and FIFO was full. The driver reports this condition to the
+* upper layer software through the status handler. This likely indicates a
+* problem with the higher layer protocol, or a problem with the slave
+* performance.
+*
+*
+* <b>Polled Operation</b>
+*
+* Transfer in polled mode is supported through a separate interface function
+* XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode,
+* this function blocks until all data has been sent/received.
+*
+* <b>Device Busy</b>
+*
+* Some operations are disallowed when the device is busy. The driver tracks
+* whether a device is busy. The device is considered busy when a data transfer
+* request is outstanding, and is considered not busy only when that transfer
+* completes (or is aborted with a mode fault error).
+*
+* <b>Device Configuration</b>
+*
+* The device can be configured in various ways during the FPGA implementation
+* process. Configuration parameters are stored in the xqspips_g.c file or
+* passed in via XQspiPs_CfgInitialize(). A table is defined where each entry
+* contains configuration information for an QSPI device, including the base
+* address for the device.
+*
+* <b>RTOS Independence</b>
+*
+* This driver is intended to be RTOS and processor independent.  It works with
+* physical addresses only.  Any needs for dynamic memory management, threads or
+* thread mutual exclusion, virtual memory, or cache control must be satisfied
+* by the layer above this driver.
+*
+* NOTE: This driver was always tested with endianess set to little-endian.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a sdm 11/25/10 First release, based on the PS SPI driver...
+* 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters
+*		     in xparameters.h
+* 2.00a kka 07/25/12 Added a few register defines for CR 670297
+* 		     Removed code related to mode fault for CR 671468
+*		     The XQspiPs_SetSlaveSelect has been modified to remove
+*		     the argument of the slave select as the QSPI controller
+*		     only supports one slave.
+* 		     XQspiPs_GetSlaveSelect API has been removed
+* 		     Added a flag ShiftReadData to the instance structure
+*.		     and is used in the XQspiPs_GetReadData API.
+*		     The ShiftReadData Flag indicates whether the data
+*		     read from the Rx FIFO needs to be shifted
+*		     in cases where the data is less than 4  bytes
+* 		     Removed the selection for the following options:
+*		     Master mode (XQSPIPS_MASTER_OPTION) and
+*		     Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
+*		     as the QSPI driver supports the Master mode
+*		     and Flash Interface mode and doesnot support
+*		     Slave mode or the legacy mode.
+*		     Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
+*		     APIs so that the last argument (IsInst) specifying whether
+*		     it is instruction or data has been removed. The first byte
+*		     in the SendBufPtr argument of these APIs specify the
+*		     instruction to be sent to the Flash Device.
+*		     This version of the driver fixes CRs 670197/663787/
+*		     670297/671468.
+* 		     Added the option for setting the Holdb_dr bit in the
+*		     configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
+*		     is the option to be used for setting this bit in the
+*		     configuration register.
+*		     The XQspiPs_PolledTransfer function has been updated
+*		     to fill the data to fifo depth.
+* 2.01a sg  02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
+*		     Added macros for Set/Get Rx Watermark. Changed QSPI
+*		     Enable/Disable macro argument from BaseAddress to
+*		     Instance Pointer. Added DelayNss argument to SetDelays
+*		     and GetDelays API's.
+*		     Created macros XQspiPs_IsManualStart and
+*		     XQspiPs_IsManualChipSelect.
+*		     Changed QSPI transfer logic for polled and interrupt
+*		     modes to be based on filled tx fifo count and receive
+*		     based on it. RXNEMPTY interrupt is not used.
+*		     Added assertions to XQspiPs_LqspiRead function.
+*		     SetDelays and GetDelays API's include DelayNss parameter.
+*		     Added defines for DelayNss,Rx Watermark,Interrupts
+*		     which need write to clear. Removed Read zeros mask from
+*		     LQSPI Config register. Renamed Fixed burst error to
+*		     data FSM error in  LQSPI Status register.
+*
+* 2.02a hk  05/07/13 Added ConnectionMode to config structure.
+*			 Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel
+*			 Added enable and disable to the XQspiPs_LqspiRead() function
+*			 Removed XQspi_Reset() in Set_Options() function when
+*			 LQSPI_MODE_OPTION is set.
+*            Added instructions for bank selection, die erase and
+*            flag status register to the flash instruction table
+*            Handling for instructions not in flash instruction
+*			 table added. Checking for Tx FIFO empty when switching from
+*			 TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
+*            byte count 3 (spansion), instruction size and TXD register
+*			 changed accordingly. CR# 712502 and 703869.
+*            Added prefix to constant definitions for ConnectionMode
+*            Added (#ifdef linear base address) in the Linear read function.
+*            Changed  XPAR_XQSPIPS_0_LINEAR_BASEADDR to
+*            XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
+*            XQspiPs_LqspiRead function. Fix for CR#718141.
+*
+* 2.03a hk  09/17/13 Modified polled and interrupt transfers to make use of
+*                    thresholds. This is to improve performance.
+*                    Added API's for QSPI reset and
+*                    linear mode initialization for boot.
+*                    Added RX and TX threshold reset to one in XQspiPs_Abort.
+*                    Added RX threshold reset(1) after transfer in polled and
+*                    interrupt transfers. Made changes to make sure threshold
+*                    change is done only when no transfer is in progress.
+*                    Updated linear init API for parallel and stacked modes.
+*                    CR#737760.
+* 3.1   hk  08/13/14 When writing to the configuration register, set/reset
+*                    required bits leaving reserved bits untouched. CR# 796813.
+* 3.2	sk	02/05/15 Add SLCR reset in abort function as a workaround because
+* 					 controller does not update FIFO status flags as expected
+* 					 when thresholds are used.
+* 3.3   sk  11/07/15 Modified the API prototypes according to MISRAC standards
+*                    to remove compilation warnings. CR# 868893.
+*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+*                    generation.
+*
+* </pre>
+*
+******************************************************************************/
+#ifndef XQSPIPS_H		/* prevent circular inclusions */
+#define XQSPIPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xqspips_hw.h"
+#include <string.h>
+
+/************************** Constant Definitions *****************************/
+
+/** @name Configuration options
+ *
+ * The following options are supported to enable/disable certain features of
+ * an QSPI device.  Each of the options is a bit mask, so more than one may be
+ * specified.
+ *
+ *
+ * The <b>Active Low Clock option</b> configures the device's clock polarity.
+ * Setting this option means the clock is active low and the SCK signal idles
+ * high. By default, the clock is active high and SCK idles low.
+ *
+ * The <b>Clock Phase option</b> configures the QSPI device for one of two
+ * transfer formats.  A clock phase of 0, the default, means data is valid on
+ * the first SCK edge (rising or falling) after the slave select (SS) signal
+ * has been asserted. A clock phase of 1 means data is valid on the second SCK
+ * edge (rising or falling) after SS has been asserted.
+ *
+ *
+ * The <b>QSPI Force Slave Select option</b> is used to enable manual control of
+ * the slave select signal.
+ * 0: The SPI_SS signal is controlled by the QSPI controller during
+ * transfers. (Default)
+ * 1: The SPI_SS signal is forced active (driven low) regardless of any
+ * transfers in progress.
+ *
+ * NOTE: The driver will handle setting and clearing the Slave Select when
+ * the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the
+ * QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the
+ * processor cannot empty and refill the FIFOs before the TX FIFO is empty
+ * When the QSPI hardware is controlling the Slave Select signals, this
+ * will cause slave to be de-selected and terminate the transfer.
+ *
+ * The <b>Manual Start option</b> is used to enable manual control of
+ * the Start command to perform data transfer.
+ * 0: The Start command is controlled by the QSPI controller during
+ * transfers(Default). Data transmission starts as soon as there is data in
+ * the TXFIFO and stalls when the TXFIFO is empty
+ * 1: The Start command must be issued by software to perform data transfer.
+ * Bit 15 of Configuration register is used to issue Start command. This bit
+ * must be set whenever TXFIFO is filled with new data.
+ *
+ * NOTE: The driver will set the Manual Start Enable bit in Configuration
+ * Register, if Manual Start option is selected. Software will issue
+ * Manual Start command whenever TXFIFO is filled with data. When there is
+ * no further data, driver will clear the Manual Start Enable bit.
+ *
+ * @{
+ */
+#define XQSPIPS_CLK_ACTIVE_LOW_OPTION	0x2  /**< Active Low Clock option */
+#define XQSPIPS_CLK_PHASE_1_OPTION	0x4  /**< Clock Phase one option */
+#define XQSPIPS_FORCE_SSELECT_OPTION	0x10 /**< Force Slave Select */
+#define XQSPIPS_MANUAL_START_OPTION	0x20 /**< Manual Start enable */
+#define XQSPIPS_LQSPI_MODE_OPTION	0x80 /**< Linear QPSI mode */
+#define XQSPIPS_HOLD_B_DRIVE_OPTION	0x100 /**< Drive HOLD_B Pin */
+/*@}*/
+
+
+/** @name QSPI Clock Prescaler options
+ * The QSPI Clock Prescaler Configuration bits are used to program master mode
+ * bit rate. The bit rate can be programmed in divide-by-two decrements from
+ * pclk/2 to pclk/256.
+ *
+ * @{
+ */
+#define XQSPIPS_CLK_PRESCALE_2		0x00 /**< PCLK/2 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_4		0x01 /**< PCLK/4 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_8		0x02 /**< PCLK/8 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_16		0x03 /**< PCLK/16 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_32		0x04 /**< PCLK/32 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_64		0x05 /**< PCLK/64 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_128	0x06 /**< PCLK/128 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_256	0x07 /**< PCLK/256 Prescaler */
+
+/*@}*/
+
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that are passed to
+ * a handler from the driver.  These constants are not bit masks such that
+ * only one will be passed at a time to the handler.
+ *
+ * @{
+ */
+#define XQSPIPS_EVENT_TRANSFER_DONE	2 /**< Transfer done */
+#define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */
+#define XQSPIPS_EVENT_RECEIVE_OVERRUN	4 /**< Receive data loss because
+						RX FIFO full */
+/*@}*/
+
+/** @name Flash commands
+ *
+ * The following constants define most of the commands supported by flash
+ * devices. Users can add more commands supported by the flash devices
+ *
+ * @{
+ */
+#define	XQSPIPS_FLASH_OPCODE_WRSR	0x01 /* Write status register */
+#define	XQSPIPS_FLASH_OPCODE_PP		0x02 /* Page program */
+#define	XQSPIPS_FLASH_OPCODE_NORM_READ	0x03 /* Normal read data bytes */
+#define	XQSPIPS_FLASH_OPCODE_WRDS	0x04 /* Write disable */
+#define	XQSPIPS_FLASH_OPCODE_RDSR1	0x05 /* Read status register 1 */
+#define	XQSPIPS_FLASH_OPCODE_WREN	0x06 /* Write enable */
+#define	XQSPIPS_FLASH_OPCODE_FAST_READ	0x0B /* Fast read data bytes */
+#define	XQSPIPS_FLASH_OPCODE_BE_4K	0x20 /* Erase 4KiB block */
+#define	XQSPIPS_FLASH_OPCODE_RDSR2	0x35 /* Read status register 2 */
+#define	XQSPIPS_FLASH_OPCODE_DUAL_READ	0x3B /* Dual read data bytes */
+#define	XQSPIPS_FLASH_OPCODE_BE_32K	0x52 /* Erase 32KiB block */
+#define	XQSPIPS_FLASH_OPCODE_QUAD_READ	0x6B /* Quad read data bytes */
+#define	XQSPIPS_FLASH_OPCODE_ERASE_SUS	0x75 /* Erase suspend */
+#define	XQSPIPS_FLASH_OPCODE_ERASE_RES	0x7A /* Erase resume */
+#define	XQSPIPS_FLASH_OPCODE_RDID	0x9F /* Read JEDEC ID */
+#define	XQSPIPS_FLASH_OPCODE_BE		0xC7 /* Erase whole flash block */
+#define	XQSPIPS_FLASH_OPCODE_SE		0xD8 /* Sector erase (usually 64KB)*/
+#define XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */
+#define XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */
+#define XQSPIPS_FLASH_OPCODE_BRWR	0x17 /* Bank Register Write */
+#define XQSPIPS_FLASH_OPCODE_BRRD	0x16 /* Bank Register Read */
+/* Extende Address Register Write - Micron's equivalent of Bank Register */
+#define XQSPIPS_FLASH_OPCODE_EARWR	0xC5
+/* Extende Address Register Read - Micron's equivalent of Bank Register */
+#define XQSPIPS_FLASH_OPCODE_EARRD	0xC8
+#define XQSPIPS_FLASH_OPCODE_DIE_ERASE	0xC4
+#define XQSPIPS_FLASH_OPCODE_READ_FLAG_SR	0x70
+#define XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR	0x50
+#define XQSPIPS_FLASH_OPCODE_READ_LOCK_REG	0xE8	/* Lock register Read */
+#define XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG	0xE5	/* Lock Register Write */
+
+/*@}*/
+
+/** @name Instruction size
+ *
+ * The following constants define numbers 1 to 4.
+ * Used to identify whether TXD0,1,2 or 3 is to be used.
+ *
+ * @{
+ */
+#define XQSPIPS_SIZE_ONE 	1
+#define XQSPIPS_SIZE_TWO 	2
+#define XQSPIPS_SIZE_THREE 	3
+#define XQSPIPS_SIZE_FOUR 	4
+
+/*@}*/
+
+/** @name ConnectionMode
+ *
+ * The following constants are the possible values of ConnectionMode in
+ * Config structure.
+ *
+ * @{
+ */
+#define XQSPIPS_CONNECTION_MODE_SINGLE		0
+#define XQSPIPS_CONNECTION_MODE_STACKED		1
+#define XQSPIPS_CONNECTION_MODE_PARALLEL	2
+
+/*@}*/
+
+/** @name FIFO threshold value
+ *
+ * This is the Rx FIFO threshold (in words) that was found to be most
+ * optimal in terms of performance
+ *
+ * @{
+ */
+#define XQSPIPS_RXFIFO_THRESHOLD_OPT		32
+
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+/**
+ * The handler data type allows the user to define a callback function to
+ * handle the asynchronous processing for the QSPI device.  The application
+ * using this driver is expected to define a handler of this type to support
+ * interrupt driven mode.  The handler executes in an interrupt context, so
+ * only minimal processing should be performed.
+ *
+ * @param	CallBackRef is the callback reference passed in by the upper
+ *		layer when setting the callback functions, and passed back to
+ *		the upper layer when the callback is invoked. Its type is
+ *		not important to the driver, so it is a void pointer.
+ * @param 	StatusEvent holds one or more status events that have occurred.
+ *		See the XQspiPs_SetStatusHandler() for details on the status
+ *		events that can be passed in the callback.
+ * @param	ByteCount indicates how many bytes of data were successfully
+ *		transferred.  This may be less than the number of bytes
+ *		requested if the status event indicates an error.
+ */
+typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
+					unsigned ByteCount);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID  of device */
+	u32 BaseAddress;	/**< Base address of the device */
+	u32 InputClockHz;	/**< Input clock frequency */
+	u8  ConnectionMode; /**< Single, Stacked and Parallel mode */
+} XQspiPs_Config;
+
+/**
+ * The XQspiPs driver instance data. The user is required to allocate a
+ * variable of this type for every QSPI device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XQspiPs_Config Config;	 /**< Configuration structure */
+	u32 IsReady;		 /**< Device is initialized and ready */
+
+	u8 *SendBufferPtr;	 /**< Buffer to send (state) */
+	u8 *RecvBufferPtr;	 /**< Buffer to receive (state) */
+	int RequestedBytes;	 /**< Number of bytes to transfer (state) */
+	int RemainingBytes;	 /**< Number of bytes left to transfer(state) */
+	u32 IsBusy;		 /**< A transfer is in progress (state) */
+	XQspiPs_StatusHandler StatusHandler;
+	void *StatusRef;  	 /**< Callback reference for status handler */
+	u32 ShiftReadData;	 /**<  Flag to indicate whether the data
+				   *   read from the Rx FIFO needs to be shifted
+				   *   in cases where the data is less than 4
+				   *   bytes
+				   */
+} XQspiPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/*
+*
+* Check in OptionsTable if Manual Start Option is enabled or disabled.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+*		- TRUE if option is set
+*		- FALSE if option is not set
+*
+* @note		C-Style signature:
+*		u8 XQspiPs_IsManualStart(XQspiPs *InstancePtr);
+*
+*****************************************************************************/
+#define XQspiPs_IsManualStart(InstancePtr) \
+	((XQspiPs_GetOptions(InstancePtr) & \
+	  XQSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE)
+
+/****************************************************************************/
+/*
+*
+* Check in OptionsTable if Manual Chip Select Option is enabled or disabled.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+*
+* @return
+*		- TRUE if option is set
+*		- FALSE if option is not set
+*
+* @note		C-Style signature:
+*		u8 XQspiPs_IsManualChipSelect(XQspiPs *InstancePtr);
+*
+*****************************************************************************/
+#define XQspiPs_IsManualChipSelect(InstancePtr) \
+	((XQspiPs_GetOptions(InstancePtr) & \
+	  XQSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the slave idle count register.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	RegisterValue is the value to be written, valid values are
+*		0-255.
+*
+* @return	None
+*
+* @note
+* C-Style signature:
+*	void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr, u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue)	\
+	XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + 	\
+			XQSPIPS_SICR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the slave idle count register. Use the XQSPIPS_SICR_*
+* constants defined in xqspips_hw.h to interpret the bit-mask returned.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	An 8-bit value representing Slave Idle Count.
+*
+* @note		C-Style signature:
+*		u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetSlaveIdle(InstancePtr)				\
+	XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + 		\
+	XQSPIPS_SICR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the transmit FIFO watermark register.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	RegisterValue is the value to be written, valid values are 1-63.
+*
+* @return	None.
+*
+* @note
+* C-Style signature:
+*	void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr, u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue)		\
+	XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + 		\
+			XQSPIPS_TXWR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the transmit FIFO watermark register.
+* Valid values are in the range 1-63.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	A 6-bit value representing Tx Watermark level.
+*
+* @note		C-Style signature:
+*		u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetTXWatermark(InstancePtr)				\
+	XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the receive FIFO watermark register.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	RegisterValue is the value to be written, valid values are 1-63.
+*
+* @return	None.
+*
+* @note
+* C-Style signature:
+*	void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr, u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue)		\
+	XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + 		\
+			XQSPIPS_RXWR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the receive FIFO watermark register.
+* Valid values are in the range 1-63.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	A 6-bit value representing Rx Watermark level.
+*
+* @note		C-Style signature:
+*		u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetRXWatermark(InstancePtr)				\
+	XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Enable the device and uninhibit master transactions.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XQspiPs_Enable(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_Enable(InstancePtr)					\
+	XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \
+			XQSPIPS_ER_ENABLE_MASK)
+
+/****************************************************************************/
+/**
+*
+* Disable the device.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XQspiPs_Disable(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_Disable(InstancePtr)					\
+	XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the Linear QSPI Configuration register.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	RegisterValue is the value to be written to the Linear QSPI
+*		configuration register.
+*
+* @return	None.
+*
+* @note
+* C-Style signature:
+*	void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr,
+*					u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue)		\
+	XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) +		\
+			XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the Linear QSPI Configuration register.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	A 32-bit value representing the contents of the LQSPI Config
+*		register.
+*
+* @note		C-Style signature:
+*		u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetLqspiConfigReg(InstancePtr)				\
+	XQspiPs_In32((InstancePtr->Config.BaseAddress) +		\
+			XQSPIPS_LQSPI_CR_OFFSET)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization function, implemented in xqspips_sinit.c
+ */
+XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Functions implemented in xqspips.c
+ */
+int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config * Config,
+			   u32 EffectiveAddr);
+void XQspiPs_Reset(XQspiPs *InstancePtr);
+void XQspiPs_Abort(XQspiPs *InstancePtr);
+
+s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
+		      u32 ByteCount);
+s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
+			    u8 *RecvBufPtr, u32 ByteCount);
+int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
+			u32 Address, unsigned ByteCount);
+
+int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr);
+
+void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
+				XQspiPs_StatusHandler FuncPtr);
+void XQspiPs_InterruptHandler(void *InstancePtr);
+
+/*
+ * Functions for selftest, in xqspips_selftest.c
+ */
+int XQspiPs_SelfTest(XQspiPs *InstancePtr);
+
+/*
+ * Functions for options, in xqspips_options.c
+ */
+s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options);
+u32 XQspiPs_GetOptions(XQspiPs *InstancePtr);
+
+s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler);
+u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr);
+
+int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
+			 u8 DelayAfter, u8 DelayInit);
+void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
+			 u8 *DelayAfter, u8 *DelayInit);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xqspips_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xqspips_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..404afed94f5afd468b74b5ea3e1ffa994357edab
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xqspips_hw.h
@@ -0,0 +1,423 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_hw.h
+* @addtogroup qspips_v3_2
+* @{
+*
+* This header file contains the identifiers and basic HW access driver
+* functions (or  macros) that can be used to access the device. Other driver
+* functions are defined in xqspips.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00  sdm 11/25/10 First release
+* 2.00a ka  07/25/12 Added a few register defines for CR 670297
+*		     and removed some defines of reserved fields for
+*		     CR 671468
+*		     Added define XQSPIPS_CR_HOLD_B_MASK for Holdb_dr
+*		     bit in Configuration register.
+* 2.01a sg  02/03/13 Added defines for DelayNss,Rx Watermark,Interrupts
+*		     which need write to clear. Removed Read zeros mask from
+*		     LQSPI Config register.
+* 2.03a hk  08/22/13 Added prototypes of API's for QSPI reset and
+*                    linear mode initialization for boot. Added related
+*                    constant definitions.
+* 3.1   hk  08/13/14 Changed definition of CR reset value masks to set/reset
+*                    required bits leaving reserved bits untouched. CR# 796813.
+* 3.2	sk	02/05/15 Add SLCR reset in abort function as a workaround because
+* 					 controller does not update FIFO status flags as expected
+* 					 when thresholds are used.
+*
+* </pre>
+*
+******************************************************************************/
+#ifndef XQSPIPS_HW_H		/* prevent circular inclusions */
+#define XQSPIPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of an QSPI device.
+ * @{
+ */
+#define XQSPIPS_CR_OFFSET	 	0x00 /**< Configuration Register */
+#define XQSPIPS_SR_OFFSET	 	0x04 /**< Interrupt Status */
+#define XQSPIPS_IER_OFFSET	 	0x08 /**< Interrupt Enable */
+#define XQSPIPS_IDR_OFFSET	 	0x0c /**< Interrupt Disable */
+#define XQSPIPS_IMR_OFFSET	 	0x10 /**< Interrupt Enabled Mask */
+#define XQSPIPS_ER_OFFSET	 	0x14 /**< Enable/Disable Register */
+#define XQSPIPS_DR_OFFSET	 	0x18 /**< Delay Register */
+#define XQSPIPS_TXD_00_OFFSET	 	0x1C /**< Transmit 4-byte inst/data */
+#define XQSPIPS_RXD_OFFSET	 	0x20 /**< Data Receive Register */
+#define XQSPIPS_SICR_OFFSET	 	0x24 /**< Slave Idle Count */
+#define XQSPIPS_TXWR_OFFSET	 	0x28 /**< Transmit FIFO Watermark */
+#define XQSPIPS_RXWR_OFFSET	 	0x2C /**< Receive FIFO Watermark */
+#define XQSPIPS_GPIO_OFFSET	 	0x30 /**< GPIO Register */
+#define XQSPIPS_LPBK_DLY_ADJ_OFFSET	0x38 /**< Loopback Delay Adjust Reg */
+#define XQSPIPS_TXD_01_OFFSET	 	0x80 /**< Transmit 1-byte inst */
+#define XQSPIPS_TXD_10_OFFSET	 	0x84 /**< Transmit 2-byte inst */
+#define XQSPIPS_TXD_11_OFFSET	 	0x88 /**< Transmit 3-byte inst */
+#define XQSPIPS_LQSPI_CR_OFFSET  	0xA0 /**< Linear QSPI config register */
+#define XQSPIPS_LQSPI_SR_OFFSET  	0xA4 /**< Linear QSPI status register */
+#define XQSPIPS_MOD_ID_OFFSET  		0xFC /**< Module ID register */
+
+/* @} */
+
+/** @name Configuration Register
+ *
+ * This register contains various control bits that
+ * affect the operation of the QSPI device. Read/Write.
+ * @{
+ */
+
+#define XQSPIPS_CR_IFMODE_MASK    0x80000000 /**< Flash mem interface mode */
+#define XQSPIPS_CR_ENDIAN_MASK    0x04000000 /**< Tx/Rx FIFO endianness */
+#define XQSPIPS_CR_MANSTRT_MASK   0x00010000 /**< Manual Transmission Start */
+#define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start
+						   Enable */
+#define XQSPIPS_CR_SSFORCE_MASK   0x00004000 /**< Force Slave Select */
+#define XQSPIPS_CR_SSCTRL_MASK    0x00000400 /**< Slave Select Decode */
+#define XQSPIPS_CR_SSCTRL_SHIFT   10	      /**< Slave Select Decode shift */
+#define XQSPIPS_CR_DATA_SZ_MASK   0x000000C0 /**< Size of word to be
+						   transferred */
+#define XQSPIPS_CR_PRESC_MASK     0x00000038 /**< Prescaler Setting */
+#define XQSPIPS_CR_PRESC_SHIFT    3	      /**< Prescaler shift */
+#define XQSPIPS_CR_PRESC_MAXIMUM  0x07	      /**< Prescaler maximum value */
+
+#define XQSPIPS_CR_CPHA_MASK      0x00000004 /**< Phase Configuration */
+#define XQSPIPS_CR_CPOL_MASK      0x00000002 /**< Polarity Configuration */
+
+#define XQSPIPS_CR_MSTREN_MASK    0x00000001 /**< Master Mode Enable */
+
+#define XQSPIPS_CR_HOLD_B_MASK    0x00080000 /**< HOLD_B Pin Drive Enable */
+
+#define XQSPIPS_CR_REF_CLK_MASK   0x00000100 /**< Ref clk bit - should be 0 */
+
+/* Deselect the Slave select line and set the transfer size to 32 at reset */
+#define XQSPIPS_CR_RESET_MASK_SET  XQSPIPS_CR_IFMODE_MASK | \
+				   XQSPIPS_CR_SSCTRL_MASK | \
+				   XQSPIPS_CR_DATA_SZ_MASK | \
+				   XQSPIPS_CR_MSTREN_MASK | \
+				   XQSPIPS_CR_SSFORCE_MASK | \
+				   XQSPIPS_CR_HOLD_B_MASK
+#define XQSPIPS_CR_RESET_MASK_CLR  XQSPIPS_CR_CPOL_MASK | \
+				   XQSPIPS_CR_CPHA_MASK | \
+				   XQSPIPS_CR_PRESC_MASK | \
+				   XQSPIPS_CR_MANSTRTEN_MASK | \
+				   XQSPIPS_CR_MANSTRT_MASK | \
+				   XQSPIPS_CR_ENDIAN_MASK | \
+				   XQSPIPS_CR_REF_CLK_MASK
+/* @} */
+
+
+/** @name QSPI Interrupt Registers
+ *
+ * <b>QSPI Status Register</b>
+ *
+ * This register holds the interrupt status flags for an QSPI device. Some
+ * of the flags are level triggered, which means that they are set as long
+ * as the interrupt condition exists. Other flags are edge triggered,
+ * which means they are set once the interrupt condition occurs and remain
+ * set until they are cleared by software. The interrupts are cleared by
+ * writing a '1' to the interrupt bit position in the Status Register.
+ * Read/Write.
+ *
+ * <b>QSPI Interrupt Enable Register</b>
+ *
+ * This register is used to enable chosen interrupts for an QSPI device.
+ * Writing a '1' to a bit in this register sets the corresponding bit in the
+ * QSPI Interrupt Mask register.  Write only.
+ *
+ * <b>QSPI Interrupt Disable Register </b>
+ *
+ * This register is used to disable chosen interrupts for an QSPI device.
+ * Writing a '1' to a bit in this register clears the corresponding bit in the
+ * QSPI Interrupt Mask register. Write only.
+ *
+ * <b>QSPI Interrupt Mask Register</b>
+ *
+ * This register shows the enabled/disabled interrupts of an QSPI device.
+ * Read only.
+ *
+ * All four registers have the same bit definitions. They are only defined once
+ * for each of the Interrupt Enable Register, Interrupt Disable Register,
+ * Interrupt Mask Register, and Channel Interrupt Status Register
+ * @{
+ */
+
+#define XQSPIPS_IXR_TXUF_MASK	   0x00000040  /**< QSPI Tx FIFO Underflow */
+#define XQSPIPS_IXR_RXFULL_MASK    0x00000020  /**< QSPI Rx FIFO Full */
+#define XQSPIPS_IXR_RXNEMPTY_MASK  0x00000010  /**< QSPI Rx FIFO Not Empty */
+#define XQSPIPS_IXR_TXFULL_MASK    0x00000008  /**< QSPI Tx FIFO Full */
+#define XQSPIPS_IXR_TXOW_MASK	   0x00000004  /**< QSPI Tx FIFO Overwater */
+#define XQSPIPS_IXR_RXOVR_MASK	   0x00000001  /**< QSPI Rx FIFO Overrun */
+#define XQSPIPS_IXR_DFLT_MASK	   0x00000025  /**< QSPI default interrupts
+						    mask */
+#define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041  /**< Interrupts which
+						    need write to clear */
+#define XQSPIPS_ISR_RESET_STATE    0x00000004  /**< Default to tx/rx empty */
+#define XQSPIPS_IXR_DISABLE_ALL    0x0000007D  /**< Disable all interrupts */
+/* @} */
+
+
+/** @name Enable Register
+ *
+ * This register is used to enable or disable an QSPI device.
+ * Read/Write
+ * @{
+ */
+#define XQSPIPS_ER_ENABLE_MASK    0x00000001 /**< QSPI Enable Bit Mask */
+/* @} */
+
+
+/** @name Delay Register
+ *
+ * This register is used to program timing delays in
+ * slave mode. Read/Write
+ * @{
+ */
+#define XQSPIPS_DR_NSS_MASK	0xFF000000 /**< Delay to de-assert slave select
+						between two words mask */
+#define XQSPIPS_DR_NSS_SHIFT	24	   /**< Delay to de-assert slave select
+						between two words shift */
+#define XQSPIPS_DR_BTWN_MASK	0x00FF0000 /**< Delay Between Transfers
+						mask */
+#define XQSPIPS_DR_BTWN_SHIFT	16	   /**< Delay Between Transfers shift */
+#define XQSPIPS_DR_AFTER_MASK	0x0000FF00 /**< Delay After Transfers mask */
+#define XQSPIPS_DR_AFTER_SHIFT	8 	   /**< Delay After Transfers shift */
+#define XQSPIPS_DR_INIT_MASK	0x000000FF /**< Delay Initially mask */
+/* @} */
+
+/** @name Slave Idle Count Registers
+ *
+ * This register defines the number of pclk cycles the slave waits for a the
+ * QSPI clock to become stable in quiescent state before it can detect the start
+ * of the next transfer in CPHA = 1 mode.
+ * Read/Write
+ *
+ * @{
+ */
+#define XQSPIPS_SICR_MASK	0x000000FF /**< Slave Idle Count Mask */
+/* @} */
+
+
+/** @name Transmit FIFO Watermark Register
+ *
+ * This register defines the watermark setting for the Transmit FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_TXWR_MASK           0x0000003F /**< Transmit Watermark Mask */
+#define XQSPIPS_TXWR_RESET_VALUE    0x00000001 /**< Transmit Watermark
+						  * register reset value */
+
+/* @} */
+
+/** @name Receive FIFO Watermark Register
+ *
+ * This register defines the watermark setting for the Receive FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_RXWR_MASK	    0x0000003F /**< Receive Watermark Mask */
+#define XQSPIPS_RXWR_RESET_VALUE    0x00000001 /**< Receive Watermark
+						  * register reset value */
+
+/* @} */
+
+/** @name FIFO Depth
+ *
+ * This macro provides the depth of transmit FIFO and receive FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_FIFO_DEPTH	63	/**< FIFO depth (words) */
+/* @} */
+
+
+/** @name Linear QSPI Configuration Register
+ *
+ * This register contains various control bits that
+ * affect the operation of the Linear QSPI controller. Read/Write.
+ *
+ * @{
+ */
+#define XQSPIPS_LQSPI_CR_LINEAR_MASK	 0x80000000 /**< LQSPI mode enable */
+#define XQSPIPS_LQSPI_CR_TWO_MEM_MASK	 0x40000000 /**< Both memories or one */
+#define XQSPIPS_LQSPI_CR_SEP_BUS_MASK	 0x20000000 /**< Seperate memory bus */
+#define XQSPIPS_LQSPI_CR_U_PAGE_MASK	 0x10000000 /**< Upper memory page */
+#define XQSPIPS_LQSPI_CR_MODE_EN_MASK	 0x02000000 /**< Enable mode bits */
+#define XQSPIPS_LQSPI_CR_MODE_ON_MASK	 0x01000000 /**< Mode on */
+#define XQSPIPS_LQSPI_CR_MODE_BITS_MASK  0x00FF0000 /**< Mode value for dual I/O
+							 or quad I/O */
+#define XQSPIPS_LQSPI_CR_DUMMY_MASK	 0x00000700 /**< Number of dummy bytes
+							 between addr and return
+							 read data */
+#define XQSPIPS_LQSPI_CR_INST_MASK	 0x000000FF /**< Read instr code */
+#define XQSPIPS_LQSPI_CR_RST_STATE	 0x8000016B /**< Default CR value */
+/* @} */
+
+/** @name Linear QSPI Status Register
+ *
+ * This register contains various status bits of the Linear QSPI controller.
+ * Read/Write.
+ *
+ * @{
+ */
+#define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK	  0x00000004 /**< AXI Data FSM Error
+							  received */
+#define XQSPIPS_LQSPI_SR_WR_RECVD_MASK	  0x00000002 /**< AXI write command
+							  received */
+/* @} */
+
+
+/** @name Loopback Delay Adjust Register
+ *
+ * This register contains various bit masks of Loopback Delay Adjust Register.
+ *
+ * @{
+ */
+
+#define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 /**< Loopback Bit */
+
+/* @} */
+
+
+/** @name SLCR Register
+ *
+ * Register offsets from SLCR base address.
+ *
+ * @{
+ */
+
+#define SLCR_LOCK 0x00000004 /**< SLCR Write Protection Lock */
+#define SLCR_UNLOCK 0x00000008 /**< SLCR Write Protection Unlock */
+#define LQSPI_RST_CTRL 0x00000230 /**< Quad SPI Software Reset Control */
+#define SLCR_LOCKSTA 0x0000000C /**< SLCR Write Protection status */
+
+/* @} */
+
+
+/** @name SLCR Register
+ *
+ * Bit Masks of above SLCR Registers .
+ *
+ * @{
+ */
+
+#ifndef XPAR_XSLCR_0_BASEADDR
+#define XPAR_XSLCR_0_BASEADDR 0xF8000000
+#endif
+#define SLCR_LOCK_MASK 0x767B /**< Write Protection Lock mask*/
+#define SLCR_UNLOCK_MASK 0xDF0D /**< SLCR Write Protection Unlock */
+#define LQSPI_RST_CTRL_MASK 0x3 /**< Quad SPI Software Reset Control */
+
+/* @} */
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XQspiPs_In32 Xil_In32
+#define XQspiPs_Out32 Xil_Out32
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XQspiPs_ReadReg(BaseAddress, RegOffset) \
+	XQspiPs_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u32 RegisterValue)
+*
+******************************************************************************/
+#define XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+	XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Functions implemented in xqspips_hw.c
+ */
+void XQspiPs_ResetHw(u32 BaseAddress);
+void XQspiPs_LinearInit(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xreg_cortexa9.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xreg_cortexa9.h
new file mode 100644
index 0000000000000000000000000000000000000000..dc9a4ebd2c36ac3f03ad6816b05610129a6a7943
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xreg_cortexa9.h
@@ -0,0 +1,591 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xreg_cortexa9.h
+*
+* This header file contains definitions for using inline assembler code. It is
+* written specifically for the GNU, ARMCC compiler.
+*
+* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along
+* with the positions of the bits within the registers.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  10/20/09 First release
+* </pre>
+*
+******************************************************************************/
+#ifndef XREG_CORTEXA9_H
+#define XREG_CORTEXA9_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* GPRs */
+#define XREG_GPR0				r0
+#define XREG_GPR1				r1
+#define XREG_GPR2				r2
+#define XREG_GPR3				r3
+#define XREG_GPR4				r4
+#define XREG_GPR5				r5
+#define XREG_GPR6				r6
+#define XREG_GPR7				r7
+#define XREG_GPR8				r8
+#define XREG_GPR9				r9
+#define XREG_GPR10				r10
+#define XREG_GPR11				r11
+#define XREG_GPR12				r12
+#define XREG_GPR13				r13
+#define XREG_GPR14				r14
+#define XREG_GPR15				r15
+#define XREG_CPSR				cpsr
+
+/* Coprocessor number defines */
+#define XREG_CP0				0
+#define XREG_CP1				1
+#define XREG_CP2				2
+#define XREG_CP3				3
+#define XREG_CP4				4
+#define XREG_CP5				5
+#define XREG_CP6				6
+#define XREG_CP7				7
+#define XREG_CP8				8
+#define XREG_CP9				9
+#define XREG_CP10				10
+#define XREG_CP11				11
+#define XREG_CP12				12
+#define XREG_CP13				13
+#define XREG_CP14				14
+#define XREG_CP15				15
+
+/* Coprocessor control register defines */
+#define XREG_CR0				cr0
+#define XREG_CR1				cr1
+#define XREG_CR2				cr2
+#define XREG_CR3				cr3
+#define XREG_CR4				cr4
+#define XREG_CR5				cr5
+#define XREG_CR6				cr6
+#define XREG_CR7				cr7
+#define XREG_CR8				cr8
+#define XREG_CR9				cr9
+#define XREG_CR10				cr10
+#define XREG_CR11				cr11
+#define XREG_CR12				cr12
+#define XREG_CR13				cr13
+#define XREG_CR14				cr14
+#define XREG_CR15				cr15
+
+/* Current Processor Status Register (CPSR) Bits */
+#define XREG_CPSR_THUMB_MODE			0x20
+#define XREG_CPSR_MODE_BITS			0x1F
+#define XREG_CPSR_SYSTEM_MODE			0x1F
+#define XREG_CPSR_UNDEFINED_MODE		0x1B
+#define XREG_CPSR_DATA_ABORT_MODE		0x17
+#define XREG_CPSR_SVC_MODE			0x13
+#define XREG_CPSR_IRQ_MODE			0x12
+#define XREG_CPSR_FIQ_MODE			0x11
+#define XREG_CPSR_USER_MODE			0x10
+
+#define XREG_CPSR_IRQ_ENABLE			0x80
+#define XREG_CPSR_FIQ_ENABLE			0x40
+
+#define XREG_CPSR_N_BIT				0x80000000
+#define XREG_CPSR_Z_BIT				0x40000000
+#define XREG_CPSR_C_BIT				0x20000000
+#define XREG_CPSR_V_BIT				0x10000000
+
+
+/* CP15 defines */
+#if defined (__GNUC__) || defined (__ICCARM__)
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID			"p15, 0, %0,  c0,  c0, 0"
+#define XREG_CP15_CACHE_TYPE			"p15, 0, %0,  c0,  c0, 1"
+#define XREG_CP15_TCM_TYPE			"p15, 0, %0,  c0,  c0, 2"
+#define XREG_CP15_TLB_TYPE			"p15, 0, %0,  c0,  c0, 3"
+#define XREG_CP15_MULTI_PROC_AFFINITY		"p15, 0, %0,  c0,  c0, 5"
+
+#define XREG_CP15_PROC_FEATURE_0		"p15, 0, %0,  c0,  c1, 0"
+#define XREG_CP15_PROC_FEATURE_1		"p15, 0, %0,  c0,  c1, 1"
+#define XREG_CP15_DEBUG_FEATURE_0		"p15, 0, %0,  c0,  c1, 2"
+#define XREG_CP15_MEMORY_FEATURE_0		"p15, 0, %0,  c0,  c1, 4"
+#define XREG_CP15_MEMORY_FEATURE_1		"p15, 0, %0,  c0,  c1, 5"
+#define XREG_CP15_MEMORY_FEATURE_2		"p15, 0, %0,  c0,  c1, 6"
+#define XREG_CP15_MEMORY_FEATURE_3		"p15, 0, %0,  c0,  c1, 7"
+
+#define XREG_CP15_INST_FEATURE_0		"p15, 0, %0,  c0,  c2, 0"
+#define XREG_CP15_INST_FEATURE_1		"p15, 0, %0,  c0,  c2, 1"
+#define XREG_CP15_INST_FEATURE_2		"p15, 0, %0,  c0,  c2, 2"
+#define XREG_CP15_INST_FEATURE_3		"p15, 0, %0,  c0,  c2, 3"
+#define XREG_CP15_INST_FEATURE_4		"p15, 0, %0,  c0,  c2, 4"
+
+#define XREG_CP15_CACHE_SIZE_ID			"p15, 1, %0,  c0,  c0, 0"
+#define XREG_CP15_CACHE_LEVEL_ID		"p15, 1, %0,  c0,  c0, 1"
+#define XREG_CP15_AUXILARY_ID			"p15, 1, %0,  c0,  c0, 7"
+
+#define XREG_CP15_CACHE_SIZE_SEL		"p15, 2, %0,  c0,  c0, 0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL			"p15, 0, %0,  c1,  c0, 0"
+#define XREG_CP15_AUX_CONTROL			"p15, 0, %0,  c1,  c0, 1"
+#define XREG_CP15_CP_ACCESS_CONTROL		"p15, 0, %0,  c1,  c0, 2"
+
+#define XREG_CP15_SECURE_CONFIG			"p15, 0, %0,  c1,  c1, 0"
+#define XREG_CP15_SECURE_DEBUG_ENABLE		"p15, 0, %0,  c1,  c1, 1"
+#define XREG_CP15_NS_ACCESS_CONTROL		"p15, 0, %0,  c1,  c1, 2"
+#define XREG_CP15_VIRTUAL_CONTROL		"p15, 0, %0,  c1,  c1, 3"
+
+#else /* RVCT */
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID			"cp15:0:c0:c0:0"
+#define XREG_CP15_CACHE_TYPE			"cp15:0:c0:c0:1"
+#define XREG_CP15_TCM_TYPE			"cp15:0:c0:c0:2"
+#define XREG_CP15_TLB_TYPE			"cp15:0:c0:c0:3"
+#define XREG_CP15_MULTI_PROC_AFFINITY		"cp15:0:c0:c0:5"
+
+#define XREG_CP15_PROC_FEATURE_0		"cp15:0:c0:c1:0"
+#define XREG_CP15_PROC_FEATURE_1		"cp15:0:c0:c1:1"
+#define XREG_CP15_DEBUG_FEATURE_0		"cp15:0:c0:c1:2"
+#define XREG_CP15_MEMORY_FEATURE_0		"cp15:0:c0:c1:4"
+#define XREG_CP15_MEMORY_FEATURE_1		"cp15:0:c0:c1:5"
+#define XREG_CP15_MEMORY_FEATURE_2		"cp15:0:c0:c1:6"
+#define XREG_CP15_MEMORY_FEATURE_3		"cp15:0:c0:c1:7"
+
+#define XREG_CP15_INST_FEATURE_0		"cp15:0:c0:c2:0"
+#define XREG_CP15_INST_FEATURE_1		"cp15:0:c0:c2:1"
+#define XREG_CP15_INST_FEATURE_2		"cp15:0:c0:c2:2"
+#define XREG_CP15_INST_FEATURE_3		"cp15:0:c0:c2:3"
+#define XREG_CP15_INST_FEATURE_4		"cp15:0:c0:c2:4"
+
+#define XREG_CP15_CACHE_SIZE_ID			"cp15:1:c0:c0:0"
+#define XREG_CP15_CACHE_LEVEL_ID		"cp15:1:c0:c0:1"
+#define XREG_CP15_AUXILARY_ID			"cp15:1:c0:c0:7"
+
+#define XREG_CP15_CACHE_SIZE_SEL		"cp15:2:c0:c0:0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL			"cp15:0:c1:c0:0"
+#define XREG_CP15_AUX_CONTROL			"cp15:0:c1:c0:1"
+#define XREG_CP15_CP_ACCESS_CONTROL		"cp15:0:c1:c0:2"
+
+#define XREG_CP15_SECURE_CONFIG			"cp15:0:c1:c1:0"
+#define XREG_CP15_SECURE_DEBUG_ENABLE		"cp15:0:c1:c1:1"
+#define XREG_CP15_NS_ACCESS_CONTROL		"cp15:0:c1:c1:2"
+#define XREG_CP15_VIRTUAL_CONTROL		"cp15:0:c1:c1:3"
+#endif
+
+/* XREG_CP15_CONTROL bit defines */
+#define XREG_CP15_CONTROL_TE_BIT		0x40000000U
+#define XREG_CP15_CONTROL_AFE_BIT		0x20000000U
+#define XREG_CP15_CONTROL_TRE_BIT		0x10000000U
+#define XREG_CP15_CONTROL_NMFI_BIT		0x08000000U
+#define XREG_CP15_CONTROL_EE_BIT		0x02000000U
+#define XREG_CP15_CONTROL_HA_BIT		0x00020000U
+#define XREG_CP15_CONTROL_RR_BIT		0x00004000U
+#define XREG_CP15_CONTROL_V_BIT			0x00002000U
+#define XREG_CP15_CONTROL_I_BIT			0x00001000U
+#define XREG_CP15_CONTROL_Z_BIT			0x00000800U
+#define XREG_CP15_CONTROL_SW_BIT		0x00000400U
+#define XREG_CP15_CONTROL_B_BIT			0x00000080U
+#define XREG_CP15_CONTROL_C_BIT			0x00000004U
+#define XREG_CP15_CONTROL_A_BIT			0x00000002U
+#define XREG_CP15_CONTROL_M_BIT			0x00000001U
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+/* C2 Register Defines */
+#define XREG_CP15_TTBR0				"p15, 0, %0,  c2,  c0, 0"
+#define XREG_CP15_TTBR1				"p15, 0, %0,  c2,  c0, 1"
+#define XREG_CP15_TTB_CONTROL			"p15, 0, %0,  c2,  c0, 2"
+
+/* C3 Register Defines */
+#define XREG_CP15_DOMAIN_ACCESS_CTRL		"p15, 0, %0,  c3,  c0, 0"
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS		"p15, 0, %0,  c5,  c0, 0"
+#define XREG_CP15_INST_FAULT_STATUS		"p15, 0, %0,  c5,  c0, 1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS		"p15, 0, %0,  c5,  c1, 0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS		"p15, 0, %0,  c5,  c1, 1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS		"p15, 0, %0,  c6,  c0, 0"
+#define XREG_CP15_INST_FAULT_ADDRESS		"p15, 0, %0,  c6,  c0, 2"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP				"p15, 0, %0,  c7,  c0, 4"
+
+#define XREG_CP15_INVAL_IC_POU_IS		"p15, 0, %0,  c7,  c1, 0"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_IS		"p15, 0, %0,  c7,  c1, 6"
+
+#define XREG_CP15_PHYS_ADDR			"p15, 0, %0,  c7,  c4, 0"
+
+#define XREG_CP15_INVAL_IC_POU			"p15, 0, %0,  c7,  c5, 0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU		"p15, 0, %0,  c7,  c5, 1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex A9.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER		"p15, 0, %0,  c7,  c5, 4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY		"p15, 0, %0,  c7,  c5, 6"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC		"p15, 0, %0,  c7,  c6, 1"
+#define XREG_CP15_INVAL_DC_LINE_SW		"p15, 0, %0,  c7,  c6, 2"
+
+#define XREG_CP15_VA_TO_PA_CURRENT_0		"p15, 0, %0,  c7,  c8, 0"
+#define XREG_CP15_VA_TO_PA_CURRENT_1		"p15, 0, %0,  c7,  c8, 1"
+#define XREG_CP15_VA_TO_PA_CURRENT_2		"p15, 0, %0,  c7,  c8, 2"
+#define XREG_CP15_VA_TO_PA_CURRENT_3		"p15, 0, %0,  c7,  c8, 3"
+
+#define XREG_CP15_VA_TO_PA_OTHER_0		"p15, 0, %0,  c7,  c8, 4"
+#define XREG_CP15_VA_TO_PA_OTHER_1		"p15, 0, %0,  c7,  c8, 5"
+#define XREG_CP15_VA_TO_PA_OTHER_2		"p15, 0, %0,  c7,  c8, 6"
+#define XREG_CP15_VA_TO_PA_OTHER_3		"p15, 0, %0,  c7,  c8, 7"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC		"p15, 0, %0,  c7, c10, 1"
+#define XREG_CP15_CLEAN_DC_LINE_SW		"p15, 0, %0,  c7, c10, 2"
+
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex A9.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER		"p15, 0, %0,  c7, c10, 4"
+#define XREG_CP15_DATA_MEMORY_BARRIER		"p15, 0, %0,  c7, c10, 5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU		"p15, 0, %0,  c7, c11, 1"
+
+#define XREG_CP15_NOP2				"p15, 0, %0,  c7, c13, 1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC	"p15, 0, %0,  c7, c14, 1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW	"p15, 0, %0,  c7, c14, 2"
+
+/* C8 Register Defines */
+#define XREG_CP15_INVAL_TLB_IS			"p15, 0, %0,  c8,  c3, 0"
+#define XREG_CP15_INVAL_TLB_MVA_IS		"p15, 0, %0,  c8,  c3, 1"
+#define XREG_CP15_INVAL_TLB_ASID_IS		"p15, 0, %0,  c8,  c3, 2"
+#define XREG_CP15_INVAL_TLB_MVA_ASID_IS		"p15, 0, %0,  c8,  c3, 3"
+
+#define XREG_CP15_INVAL_ITLB_UNLOCKED		"p15, 0, %0,  c8,  c5, 0"
+#define XREG_CP15_INVAL_ITLB_MVA		"p15, 0, %0,  c8,  c5, 1"
+#define XREG_CP15_INVAL_ITLB_ASID		"p15, 0, %0,  c8,  c5, 2"
+
+#define XREG_CP15_INVAL_DTLB_UNLOCKED		"p15, 0, %0,  c8,  c6, 0"
+#define XREG_CP15_INVAL_DTLB_MVA		"p15, 0, %0,  c8,  c6, 1"
+#define XREG_CP15_INVAL_DTLB_ASID		"p15, 0, %0,  c8,  c6, 2"
+
+#define XREG_CP15_INVAL_UTLB_UNLOCKED		"p15, 0, %0,  c8,  c7, 0"
+#define XREG_CP15_INVAL_UTLB_MVA		"p15, 0, %0,  c8,  c7, 1"
+#define XREG_CP15_INVAL_UTLB_ASID		"p15, 0, %0,  c8,  c7, 2"
+#define XREG_CP15_INVAL_UTLB_MVA_ASID		"p15, 0, %0,  c8,  c7, 3"
+
+/* C9 Register Defines */
+#define XREG_CP15_PERF_MONITOR_CTRL		"p15, 0, %0,  c9, c12, 0"
+#define XREG_CP15_COUNT_ENABLE_SET		"p15, 0, %0,  c9, c12, 1"
+#define XREG_CP15_COUNT_ENABLE_CLR		"p15, 0, %0,  c9, c12, 2"
+#define XREG_CP15_V_FLAG_STATUS			"p15, 0, %0,  c9, c12, 3"
+#define XREG_CP15_SW_INC			"p15, 0, %0,  c9, c12, 4"
+#define XREG_CP15_EVENT_CNTR_SEL		"p15, 0, %0,  c9, c12, 5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER		"p15, 0, %0,  c9, c13, 0"
+#define XREG_CP15_EVENT_TYPE_SEL		"p15, 0, %0,  c9, c13, 1"
+#define XREG_CP15_PERF_MONITOR_COUNT		"p15, 0, %0,  c9, c13, 2"
+
+#define XREG_CP15_USER_ENABLE			"p15, 0, %0,  c9, c14, 0"
+#define XREG_CP15_INTR_ENABLE_SET		"p15, 0, %0,  c9, c14, 1"
+#define XREG_CP15_INTR_ENABLE_CLR		"p15, 0, %0,  c9, c14, 2"
+
+/* C10 Register Defines */
+#define XREG_CP15_TLB_LOCKDWN			"p15, 0, %0, c10,  c0, 0"
+
+#define XREG_CP15_PRI_MEM_REMAP			"p15, 0, %0, c10,  c2, 0"
+#define XREG_CP15_NORM_MEM_REMAP		"p15, 0, %0, c10,  c2, 1"
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+#define XREG_CP15_VEC_BASE_ADDR			"p15, 0, %0, c12,  c0, 0"
+#define XREG_CP15_MONITOR_VEC_BASE_ADDR		"p15, 0, %0, c12,  c0, 1"
+
+#define XREG_CP15_INTERRUPT_STATUS		"p15, 0, %0, c12,  c1, 0"
+#define XREG_CP15_VIRTUALIZATION_INTR		"p15, 0, %0, c12,  c1, 1"
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID			"p15, 0, %0, c13,  c0, 1"
+#define USER_RW_THREAD_PID			"p15, 0, %0, c13,  c0, 2"
+#define USER_RO_THREAD_PID			"p15, 0, %0, c13,  c0, 3"
+#define USER_PRIV_THREAD_PID			"p15, 0, %0, c13,  c0, 4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_POWER_CTRL			"p15, 0, %0, c15,  c0, 0"
+#define XREG_CP15_CONFIG_BASE_ADDR		"p15, 4, %0, c15,  c0, 0"
+
+#define XREG_CP15_READ_TLB_ENTRY		"p15, 5, %0, c15,  c4, 2"
+#define XREG_CP15_WRITE_TLB_ENTRY		"p15, 5, %0, c15,  c4, 4"
+
+#define XREG_CP15_MAIN_TLB_VA			"p15, 5, %0, c15,  c5, 2"
+
+#define XREG_CP15_MAIN_TLB_PA			"p15, 5, %0, c15,  c6, 2"
+
+#define XREG_CP15_MAIN_TLB_ATTR			"p15, 5, %0, c15,  c7, 2"
+
+#else
+/* C2 Register Defines */
+#define XREG_CP15_TTBR0				"cp15:0:c2:c0:0"
+#define XREG_CP15_TTBR1				"cp15:0:c2:c0:1"
+#define XREG_CP15_TTB_CONTROL			"cp15:0:c2:c0:2"
+
+/* C3 Register Defines */
+#define XREG_CP15_DOMAIN_ACCESS_CTRL		"cp15:0:c3:c0:0"
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS		"cp15:0:c5:c0:0"
+#define XREG_CP15_INST_FAULT_STATUS		"cp15:0:c5:c0:1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS		"cp15:0:c5:c1:0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS		"cp15:0:c5:c1:1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS		"cp15:0:c6:c0:0"
+#define XREG_CP15_INST_FAULT_ADDRESS		"cp15:0:c6:c0:2"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP				"cp15:0:c7:c0:4"
+
+#define XREG_CP15_INVAL_IC_POU_IS		"cp15:0:c7:c1:0"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_IS		"cp15:0:c7:c1:6"
+
+#define XREG_CP15_PHYS_ADDR			"cp15:0:c7:c4:0"
+
+#define XREG_CP15_INVAL_IC_POU			"cp15:0:c7:c5:0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU		"cp15:0:c7:c5:1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex A9.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER		"cp15:0:c7:c5:4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY		"cp15:0:c7:c5:6"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC		"cp15:0:c7:c6:1"
+#define XREG_CP15_INVAL_DC_LINE_SW		"cp15:0:c7:c6:2"
+
+#define XREG_CP15_VA_TO_PA_CURRENT_0		"cp15:0:c7:c8:0"
+#define XREG_CP15_VA_TO_PA_CURRENT_1		"cp15:0:c7:c8:1"
+#define XREG_CP15_VA_TO_PA_CURRENT_2		"cp15:0:c7:c8:2"
+#define XREG_CP15_VA_TO_PA_CURRENT_3		"cp15:0:c7:c8:3"
+
+#define XREG_CP15_VA_TO_PA_OTHER_0		"cp15:0:c7:c8:4"
+#define XREG_CP15_VA_TO_PA_OTHER_1		"cp15:0:c7:c8:5"
+#define XREG_CP15_VA_TO_PA_OTHER_2		"cp15:0:c7:c8:6"
+#define XREG_CP15_VA_TO_PA_OTHER_3		"cp15:0:c7:c8:7"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC		"cp15:0:c7:c10:1"
+#define XREG_CP15_CLEAN_DC_LINE_SW		"cp15:0:c7:c10:2"
+
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex A9.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER		"cp15:0:c7:c10:4"
+#define XREG_CP15_DATA_MEMORY_BARRIER		"cp15:0:c7:c10:5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU		"cp15:0:c7:c11:1"
+
+#define XREG_CP15_NOP2				"cp15:0:c7:c13:1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC	"cp15:0:c7:c14:1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW	"cp15:0:c7:c14:2"
+
+/* C8 Register Defines */
+#define XREG_CP15_INVAL_TLB_IS			"cp15:0:c8:c3:0"
+#define XREG_CP15_INVAL_TLB_MVA_IS		"cp15:0:c8:c3:1"
+#define XREG_CP15_INVAL_TLB_ASID_IS		"cp15:0:c8:c3:2"
+#define XREG_CP15_INVAL_TLB_MVA_ASID_IS		"cp15:0:c8:c3:3"
+
+#define XREG_CP15_INVAL_ITLB_UNLOCKED		"cp15:0:c8:c5:0"
+#define XREG_CP15_INVAL_ITLB_MVA		"cp15:0:c8:c5:1"
+#define XREG_CP15_INVAL_ITLB_ASID		"cp15:0:c8:c5:2"
+
+#define XREG_CP15_INVAL_DTLB_UNLOCKED		"cp15:0:c8:c6:0"
+#define XREG_CP15_INVAL_DTLB_MVA		"cp15:0:c8:c6:1"
+#define XREG_CP15_INVAL_DTLB_ASID		"cp15:0:c8:c6:2"
+
+#define XREG_CP15_INVAL_UTLB_UNLOCKED		"cp15:0:c8:c7:0"
+#define XREG_CP15_INVAL_UTLB_MVA		"cp15:0:c8:c7:1"
+#define XREG_CP15_INVAL_UTLB_ASID		"cp15:0:c8:c7:2"
+#define XREG_CP15_INVAL_UTLB_MVA_ASID		"cp15:0:c8:c7:3"
+
+/* C9 Register Defines */
+#define XREG_CP15_PERF_MONITOR_CTRL		"cp15:0:c9:c12:0"
+#define XREG_CP15_COUNT_ENABLE_SET		"cp15:0:c9:c12:1"
+#define XREG_CP15_COUNT_ENABLE_CLR		"cp15:0:c9:c12:2"
+#define XREG_CP15_V_FLAG_STATUS			"cp15:0:c9:c12:3"
+#define XREG_CP15_SW_INC			"cp15:0:c9:c12:4"
+#define XREG_CP15_EVENT_CNTR_SEL		"cp15:0:c9:c12:5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER		"cp15:0:c9:c13:0"
+#define XREG_CP15_EVENT_TYPE_SEL		"cp15:0:c9:c13:1"
+#define XREG_CP15_PERF_MONITOR_COUNT		"cp15:0:c9:c13:2"
+
+#define XREG_CP15_USER_ENABLE			"cp15:0:c9:c14:0"
+#define XREG_CP15_INTR_ENABLE_SET		"cp15:0:c9:c14:1"
+#define XREG_CP15_INTR_ENABLE_CLR		"cp15:0:c9:c14:2"
+
+/* C10 Register Defines */
+#define XREG_CP15_TLB_LOCKDWN			"cp15:0:c10:c0:0"
+
+#define XREG_CP15_PRI_MEM_REMAP			"cp15:0:c10:c2:0"
+#define XREG_CP15_NORM_MEM_REMAP		"cp15:0:c10:c2:1"
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+#define XREG_CP15_VEC_BASE_ADDR			"cp15:0:c12:c0:0"
+#define XREG_CP15_MONITOR_VEC_BASE_ADDR		"cp15:0:c12:c0:1"
+
+#define XREG_CP15_INTERRUPT_STATUS		"cp15:0:c12:c1:0"
+#define XREG_CP15_VIRTUALIZATION_INTR		"cp15:0:c12:c1:1"
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID			"cp15:0:c13:c0:1"
+#define USER_RW_THREAD_PID			"cp15:0:c13:c0:2"
+#define USER_RO_THREAD_PID			"cp15:0:c13:c0:3"
+#define USER_PRIV_THREAD_PID			"cp15:0:c13:c0:4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_POWER_CTRL			"cp15:0:c15:c0:0"
+#define XREG_CP15_CONFIG_BASE_ADDR		"cp15:4:c15:c0:0"
+
+#define XREG_CP15_READ_TLB_ENTRY		"cp15:5:c15:c4:2"
+#define XREG_CP15_WRITE_TLB_ENTRY		"cp15:5:c15:c4:4"
+
+#define XREG_CP15_MAIN_TLB_VA			"cp15:5:c15:c5:2"
+
+#define XREG_CP15_MAIN_TLB_PA			"cp15:5:c15:c6:2"
+
+#define XREG_CP15_MAIN_TLB_ATTR			"cp15:5:c15:c7:2"
+#endif
+
+
+/* MPE register definitions */
+#define XREG_FPSID				c0
+#define XREG_FPSCR				c1
+#define XREG_MVFR1				c6
+#define XREG_MVFR0				c7
+#define XREG_FPEXC				c8
+#define XREG_FPINST				c9
+#define XREG_FPINST2				c10
+
+/* FPSID bits */
+#define XREG_FPSID_IMPLEMENTER_BIT	(24)
+#define XREG_FPSID_IMPLEMENTER_MASK	(0xFF << FPSID_IMPLEMENTER_BIT)
+#define XREG_FPSID_SOFTWARE		(1<<23)
+#define XREG_FPSID_ARCH_BIT		(16)
+#define XREG_FPSID_ARCH_MASK		(0xF  << FPSID_ARCH_BIT)
+#define XREG_FPSID_PART_BIT		(8)
+#define XREG_FPSID_PART_MASK		(0xFF << FPSID_PART_BIT)
+#define XREG_FPSID_VARIANT_BIT		(4)
+#define XREG_FPSID_VARIANT_MASK		(0xF  << FPSID_VARIANT_BIT)
+#define XREG_FPSID_REV_BIT		(0)
+#define XREG_FPSID_REV_MASK		(0xF  << FPSID_REV_BIT)
+
+/* FPSCR bits */
+#define XREG_FPSCR_N_BIT		(1 << 31)
+#define XREG_FPSCR_Z_BIT		(1 << 30)
+#define XREG_FPSCR_C_BIT		(1 << 29)
+#define XREG_FPSCR_V_BIT		(1 << 28)
+#define XREG_FPSCR_QC			(1 << 27)
+#define XREG_FPSCR_AHP			(1 << 26)
+#define XREG_FPSCR_DEFAULT_NAN		(1 << 25)
+#define XREG_FPSCR_FLUSHTOZERO		(1 << 24)
+#define XREG_FPSCR_ROUND_NEAREST	(0 << 22)
+#define XREG_FPSCR_ROUND_PLUSINF	(1 << 22)
+#define XREG_FPSCR_ROUND_MINUSINF	(2 << 22)
+#define XREG_FPSCR_ROUND_TOZERO		(3 << 22)
+#define XREG_FPSCR_RMODE_BIT		(22)
+#define XREG_FPSCR_RMODE_MASK		(3 << FPSCR_RMODE_BIT)
+#define XREG_FPSCR_STRIDE_BIT		(20)
+#define XREG_FPSCR_STRIDE_MASK		(3 << FPSCR_STRIDE_BIT)
+#define XREG_FPSCR_LENGTH_BIT		(16)
+#define XREG_FPSCR_LENGTH_MASK		(7 << FPSCR_LENGTH_BIT)
+#define XREG_FPSCR_IDC			(1 << 7)
+#define XREG_FPSCR_IXC			(1 << 4)
+#define XREG_FPSCR_UFC			(1 << 3)
+#define XREG_FPSCR_OFC			(1 << 2)
+#define XREG_FPSCR_DZC			(1 << 1)
+#define XREG_FPSCR_IOC			(1 << 0)
+
+/* MVFR0 bits */
+#define XREG_MVFR0_RMODE_BIT		(28)
+#define XREG_MVFR0_RMODE_MASK		(0xF << XREG_MVFR0_RMODE_BIT)
+#define XREG_MVFR0_SHORT_VEC_BIT	(24)
+#define XREG_MVFR0_SHORT_VEC_MASK	(0xF << XREG_MVFR0_SHORT_VEC_BIT)
+#define XREG_MVFR0_SQRT_BIT		(20)
+#define XREG_MVFR0_SQRT_MASK		(0xF << XREG_MVFR0_SQRT_BIT)
+#define XREG_MVFR0_DIVIDE_BIT		(16)
+#define XREG_MVFR0_DIVIDE_MASK		(0xF << XREG_MVFR0_DIVIDE_BIT)
+#define XREG_MVFR0_EXEC_TRAP_BIT	(12)
+#define XREG_MVFR0_EXEC_TRAP_MASK	(0xF << XREG_MVFR0_EXEC_TRAP_BIT)
+#define XREG_MVFR0_DP_BIT		(8)
+#define XREG_MVFR0_DP_MASK		(0xF << XREG_MVFR0_DP_BIT)
+#define XREG_MVFR0_SP_BIT		(4)
+#define XREG_MVFR0_SP_MASK		(0xF << XREG_MVFR0_SP_BIT)
+#define XREG_MVFR0_A_SIMD_BIT		(0)
+#define XREG_MVFR0_A_SIMD_MASK		(0xF << MVFR0_A_SIMD_BIT)
+
+/* FPEXC bits */
+#define XREG_FPEXC_EX			(1 << 31)
+#define XREG_FPEXC_EN			(1 << 30)
+#define XREG_FPEXC_DEX			(1 << 29)
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XREG_CORTEXA9_H */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscugic.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscugic.h
new file mode 100644
index 0000000000000000000000000000000000000000..fb6624239ffdb197717fda8864cbcf9d6385ca52
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscugic.h
@@ -0,0 +1,357 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic.h
+* @addtogroup scugic_v3_1
+* @{
+* @details
+*
+* The generic interrupt controller driver component.
+*
+* The interrupt controller driver uses the idea of priority for the various
+* handlers. Priority is an integer within the range of 1 and 31 inclusive with
+* default of 1 being the highest priority interrupt source. The priorities
+* of the various sources can be dynamically altered as needed through
+* hardware configuration.
+*
+* The generic interrupt controller supports the following
+* features:
+*
+*   - specific individual interrupt enabling/disabling
+*   - specific individual interrupt acknowledging
+*   - attaching specific callback function to handle interrupt source
+*   - assigning desired priority to interrupt source if default is not
+*     acceptable.
+*
+* Details about connecting the interrupt handler of the driver are contained
+* in the source file specific to interrupt processing, xscugic_intr.c.
+*
+* This driver is intended to be RTOS and processor independent.  It works with
+* physical addresses only.  Any needs for dynamic memory management, threads
+* or thread mutual exclusion, virtual memory, or cache control must be
+* satisfied by the layer above this driver.
+*
+* <b>Interrupt Vector Tables</b>
+*
+* The device ID of the interrupt controller device is used by the driver as a
+* direct index into the configuration data table. The user should populate the
+* vector table with handlers and callbacks at run-time using the
+* XScuGic_Connect() and XScuGic_Disconnect() functions.
+*
+* Each vector table entry corresponds to a device that can generate an
+* interrupt. Each entry contains an interrupt handler function and an
+* argument to be passed to the handler when an interrupt occurs.  The
+* user must use XScuGic_Connect() when the interrupt handler takes an
+* argument other than the base address.
+*
+* <b>Nested Interrupts Processing</b>
+*
+* Nested interrupts are not supported by this driver.
+*
+* NOTE:
+* The generic interrupt controller is not a part of the snoop control unit
+* as indicated by the prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a drg  01/19/00 First release
+* 1.01a sdm  11/09/11 The XScuGic and XScuGic_Config structures have changed.
+*		      The HandlerTable (of type XScuGic_VectorTableEntry) is
+*		      moved to XScuGic_Config structure from XScuGic structure.
+*
+*		      The "Config" entry in XScuGic structure is made as
+*		      pointer for better efficiency.
+*
+*		      A new file named as xscugic_hw.c is now added. It is
+*		      to implement low level driver routines without using
+*		      any xscugic instance pointer. They are useful when the
+*		      user wants to use xscugic through device id or
+*		      base address. The driver routines provided are explained
+*		      below.
+*		      XScuGic_DeviceInitialize that takes device id as
+*		      argument and initializes the device (without calling
+*		      XScuGic_CfgInitialize).
+*		      XScuGic_DeviceInterruptHandler that takes device id
+*		      as argument and calls appropriate handlers from the
+*		      HandlerTable.
+*		      XScuGic_RegisterHandler that registers a new handler
+*		      by taking xscugic hardware base address as argument.
+*		      LookupConfigByBaseAddress is used to return the
+*		      corresponding config structure from XScuGic_ConfigTable
+*		      based on the scugic base address passed.
+* 1.02a sdm  12/20/11 Removed AckBeforeService from the XScuGic_Config
+*		      structure.
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
+*		      *_hw.h
+*		      Added APIs
+*			- XScuGic_SetPriTrigTypeByDistAddr()
+*			- XScuGic_GetPriTrigTypeByDistAddr()
+*		      (CR 702687)
+*			Added support to direct interrupts to the appropriate CPU. Earlier
+*			  interrupts were directed to CPU1 (hard coded). Now depending
+*			  upon the CPU selected by the user (xparameters.h), interrupts
+*			  will be directed to the relevant CPU. This fixes CR 699688.
+* 1.04a hk   05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+*			  XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+*			  Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+*             XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+*			  This is fix for CR#705621.
+* 1.05a hk   06/26/13 Modified tcl to export external interrupts correctly to
+*                     xparameters.h. Fix for CR's 690505, 708928 & 719359.
+* 2.0   adk  12/10/13 Updated as per the New Tcl API's
+* 2.1   adk  25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.2   asa  02/29/16 Modified DistributorInit function for Zynq AMP case. The
+*			  distributor is left uninitialized for Zynq AMP. It is assumed
+*             that the distributor will be initialized by Linux master. However
+*             for CortexR5 case, the earlier code is left unchanged where the
+*             the interrupt processor target registers in the distributor is
+*             initialized with the corresponding CPU ID on which the application
+*             built over the scugic driver runs.
+*             These changes fix CR#937243.
+*
+* 3.4   asa  04/07/16 Created a new static function DoDistributorInit to simplify
+*            the flow and avoid code duplication. Changes are made for
+*            USE_AMP use case for R5. In a scenario (in R5 split mode) when
+*            one R5 is operating with A53 in open amp config and other
+*            R5 running baremetal app, the existing code
+*            had the potential to stop the whole AMP solution to work (if
+*            for some reason the R5 running the baremetal app tasked to
+*            initialize the Distributor hangs or crashes before initializing).
+*            Changes are made so that the R5 under AMP first checks if
+*            the distributor is enabled or not and if not, it does the
+*            standard Distributor initialization.
+*            This fixes the CR#952962.
+* 3.6   ms   01/23/17 Modified xil_printf statement in main function for all
+*                     examples to ensure that "Successfully ran" and "Failed"
+*                     strings are available in all examples. This is a fix
+*                     for CR-965028.
+*       kvn  02/17/17 Add support for changing GIC CPU master at run time.
+*       kvn  02/28/17 Make the CpuId as static variable and Added new
+*                     XScugiC_GetCpuId to access CpuId.
+*       ms   03/17/17 Added readme.txt file in examples folder for doxygen
+*                     generation.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XSCUGIC_H /* prevent circular inclusions */
+#define XSCUGIC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xil_io.h"
+#include "xscugic_hw.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+#define EFUSE_STATUS_OFFSET   0x10
+#define EFUSE_STATUS_CPU_MASK 0x80
+
+#if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
+#define ARMA9
+#endif
+/**************************** Type Definitions *******************************/
+
+/* The following data type defines each entry in an interrupt vector table.
+ * The callback reference is the base address of the interrupting device
+ * for the low level driver and an instance pointer for the high level driver.
+ */
+typedef struct
+{
+	Xil_InterruptHandler Handler;
+	void *CallBackRef;
+} XScuGic_VectorTableEntry;
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct
+{
+	u16 DeviceId;		/**< Unique ID  of device */
+	u32 CpuBaseAddress;	/**< CPU Interface Register base address */
+	u32 DistBaseAddress;	/**< Distributor Register base address */
+	XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**<
+				 Vector table of interrupt handlers */
+} XScuGic_Config;
+
+/**
+ * The XScuGic driver instance data. The user is required to allocate a
+ * variable of this type for every intc device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct
+{
+	XScuGic_Config *Config;  /**< Configuration table entry */
+	u32 IsReady;		 /**< Device is initialized and ready */
+	u32 UnhandledInterrupts; /**< Intc Statistics */
+} XScuGic;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Write the given CPU Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be written
+* @param    Data is the 32-bit value to write to the register
+*
+* @return   None.
+*
+* @note
+* C-style signature:
+*    void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \
+					((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given CPU Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be read
+*
+* @return   The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \
+	(XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Distributor Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be written
+* @param    Data is the 32-bit value to write to the register
+*
+* @return   None.
+*
+* @note
+* C-style signature:
+*    void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \
+					((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given Distributor Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be read
+*
+* @return   The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_DistReadReg(InstancePtr, RegOffset) \
+(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset)))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Required functions in xscugic.c
+ */
+
+s32  XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
+			Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id);
+
+void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id);
+void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id);
+
+s32  XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr,
+							u32 EffectiveAddr);
+
+s32  XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id);
+
+void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 *Priority, u8 *Trigger);
+void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 Priority, u8 Trigger);
+void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
+void XScuGic_Stop(XScuGic *InstancePtr);
+void XScuGic_SetCpuID(u32 CpuCoreId);
+u32 XScuGic_GetCpuID(void);
+/*
+ * Initialization functions in xscugic_sinit.c
+ */
+XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId);
+
+/*
+ * Interrupt functions in xscugic_intr.c
+ */
+void XScuGic_InterruptHandler(XScuGic *InstancePtr);
+
+/*
+ * Self-test functions in xscugic_selftest.c
+ */
+s32  XScuGic_SelfTest(XScuGic *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscugic_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscugic_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..5eaa633e342e275350e1e3faba7d964fffca01d3
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscugic_hw.h
@@ -0,0 +1,642 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_hw.h
+* @addtogroup scugic_v3_1
+* @{
+*
+* This header file contains identifiers and HW access functions (or
+* macros) that can be used to access the device.  The user should refer to the
+* hardware device specification for more details of the device operation.
+* The driver functions/APIs are defined in xscugic.h.
+*
+* This GIC device has two parts, a distributor and CPU interface(s). Each part
+* has separate register definition sections.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 1.01a sdm  11/09/11 "xil_exception.h" added as include.
+*		      Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
+*		      added to enable or disable interrupts based on
+*		      Distributor Register base address. Normally users use
+*		      XScuGic instance and call XScuGic_Enable or
+*		      XScuGic_Disable to enable/disable interrupts. These
+*		      new macros are provided when user does not want to
+*		      use an instance pointer but still wants to enable or
+*		      disable interrupts.
+*		      Function prototypes for functions (present in newly
+*		      added file xscugic_hw.c) are added.
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *_hw.c (CR
+*		      702687).
+* 1.04a hk   05/04/13 Fix for CR#705621. Moved function prototypes
+*		      XScuGic_SetPriTrigTypeByDistAddr and
+*         	      XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
+* 3.0	pkp  12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
+*		      Zynq Ultrascale Mp
+* 3.0   kvn  02/13/14 Modified code for MISRA-C:2012 compliance.
+* 3.2	pkp  11/09/15 Corrected the interrupt processsor target mask value
+*					  for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XSCUGIC_HW_H /* prevent circular inclusions */
+#define XSCUGIC_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The maximum number of interrupts supported by the hardware.
+ */
+#ifdef __ARM_NEON__
+#define XSCUGIC_MAX_NUM_INTR_INPUTS    	95U /* Maximum number of interrupt defined by Zynq */
+#else
+#define XSCUGIC_MAX_NUM_INTR_INPUTS    	195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */
+#endif
+
+/*
+ * The maximum priority value that can be used in the GIC.
+ */
+#define XSCUGIC_MAX_INTR_PRIO_VAL    	248U
+#define XSCUGIC_INTR_PRIO_MASK			0x000000F8U
+
+/** @name Distributor Interface Register Map
+ *
+ * Define the offsets from the base address for all Distributor registers of
+ * the interrupt controller, some registers may be reserved in the hardware
+ * device.
+ * @{
+ */
+#define XSCUGIC_DIST_EN_OFFSET		0x00000000U /**< Distributor Enable
+							Register */
+#define XSCUGIC_IC_TYPE_OFFSET		0x00000004U /**< Interrupt Controller
+							Type Register */
+#define XSCUGIC_DIST_IDENT_OFFSET	0x00000008U /**< Implementor ID
+							Register */
+#define XSCUGIC_SECURITY_OFFSET		0x00000080U /**< Interrupt Security
+							Register */
+#define XSCUGIC_ENABLE_SET_OFFSET	0x00000100U /**< Enable Set
+							Register */
+#define XSCUGIC_DISABLE_OFFSET		0x00000180U /**< Enable Clear Register */
+#define XSCUGIC_PENDING_SET_OFFSET	0x00000200U /**< Pending Set
+							Register */
+#define XSCUGIC_PENDING_CLR_OFFSET	0x00000280U /**< Pending Clear
+							Register */
+#define XSCUGIC_ACTIVE_OFFSET		0x00000300U /**< Active Status Register */
+#define XSCUGIC_PRIORITY_OFFSET		0x00000400U /**< Priority Level Register */
+#define XSCUGIC_SPI_TARGET_OFFSET	0x00000800U /**< SPI Target
+							Register 0x800-0x8FB */
+#define XSCUGIC_INT_CFG_OFFSET		0x00000C00U /**< Interrupt Configuration
+							Register 0xC00-0xCFC */
+#define XSCUGIC_PPI_STAT_OFFSET		0x00000D00U /**< PPI Status Register */
+#define XSCUGIC_SPI_STAT_OFFSET		0x00000D04U /**< SPI Status Register
+							0xd04-0xd7C */
+#define XSCUGIC_AHB_CONFIG_OFFSET	0x00000D80U /**< AHB Configuration
+							Register */
+#define XSCUGIC_SFI_TRIG_OFFSET		0x00000F00U /**< Software Triggered
+							Interrupt Register */
+#define XSCUGIC_PERPHID_OFFSET		0x00000FD0U /**< Peripheral ID Reg */
+#define XSCUGIC_PCELLID_OFFSET		0x00000FF0U /**< Pcell ID Register */
+/* @} */
+
+/** @name  Distributor Enable Register
+ * Controls if the distributor response to external interrupt inputs.
+ * @{
+ */
+#define XSCUGIC_EN_INT_MASK		0x00000001U /**< Interrupt In Enable */
+/* @} */
+
+/** @name  Interrupt Controller Type Register
+ * @{
+ */
+#define XSCUGIC_LSPI_MASK	0x0000F800U /**< Number of Lockable
+						Shared Peripheral
+						Interrupts*/
+#define XSCUGIC_DOMAIN_MASK	0x00000400U /**< Number os Security domains*/
+#define XSCUGIC_CPU_NUM_MASK	0x000000E0U /**< Number of CPU Interfaces */
+#define XSCUGIC_NUM_INT_MASK	0x0000001FU /**< Number of Interrupt IDs */
+/* @} */
+
+/** @name  Implementor ID Register
+ * Implementor and revision information.
+ * @{
+ */
+#define XSCUGIC_REV_MASK	0x00FFF000U /**< Revision Number */
+#define XSCUGIC_IMPL_MASK	0x00000FFFU /**< Implementor */
+/* @} */
+
+/** @name  Interrupt Security Registers
+ * Each bit controls the security level of an interrupt, either secure or non
+ * secure. These registers can only be accessed using secure read and write.
+ * There are registers for each of the CPU interfaces at offset 0x080.  A
+ * register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x084.
+ * @{
+ */
+#define XSCUGIC_INT_NS_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Enable Set Register
+ * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
+ * bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x100. With up
+ * to 8 registers aliased to the same address. A register set for the SPI
+ * interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x104.
+ * @{
+ */
+#define XSCUGIC_INT_EN_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Enable Clear Register
+ * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
+ * sets the corresponding bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x180. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x184.
+ * @{
+ */
+#define XSCUGIC_INT_CLR_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Pending Set Register
+ * Each bit controls the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
+ * an interrupt to the pending state.
+ * There are registers for each of the CPU interfaces at offset 0x200. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x204.
+ * @{
+ */
+#define XSCUGIC_PEND_SET_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Pending Clear Register
+ * Each bit can clear the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
+ * clears the pending state of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x280. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x284.
+ * @{
+ */
+#define XSCUGIC_PEND_CLR_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Active Status Register
+ * Each bit provides the Active status of an interrupt, a
+ * 0 is not Active, a 1 is Active. This is a read only register.
+ * There are registers for each of the CPU interfaces at offset 0x300. With up
+ * to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x380.
+ * @{
+ */
+#define XSCUGIC_ACTIVE_MASK	0x00000001U /**< Each bit corresponds to an
+					      INT_ID */
+/* @} */
+
+/** @name  Priority Level Register
+ * Each byte in a Priority Level Register sets the priority level of an
+ * interrupt. Reading the register provides the priority level of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x400 through
+ * 0x41C. With up to 8 registers aliased to each address.
+ * 0 is highest priority, 0xFF is lowest.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x420.
+ * @{
+ */
+#define XSCUGIC_PRIORITY_MASK	0x000000FFU /**< Each Byte corresponds to an
+						INT_ID */
+#define XSCUGIC_PRIORITY_MAX	0x000000FFU /**< Highest value of a priority
+						actually the lowest priority*/
+/* @} */
+
+/** @name  SPI Target Register 0x800-0x8FB
+ * Each byte references a separate SPI and programs which of the up to 8 CPU
+ * interfaces are sent a Pending interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x800 through
+ * 0x81C. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x820.
+ *
+ * This driver does not support multiple CPU interfaces. These are included
+ * for complete documentation.
+ * @{
+ */
+#define XSCUGIC_SPI_CPU7_MASK	0x00000080U /**< CPU 7 Mask*/
+#define XSCUGIC_SPI_CPU6_MASK	0x00000040U /**< CPU 6 Mask*/
+#define XSCUGIC_SPI_CPU5_MASK	0x00000020U /**< CPU 5 Mask*/
+#define XSCUGIC_SPI_CPU4_MASK	0x00000010U /**< CPU 4 Mask*/
+#define XSCUGIC_SPI_CPU3_MASK	0x00000008U /**< CPU 3 Mask*/
+#define XSCUGIC_SPI_CPU2_MASK	0x00000004U /**< CPU 2 Mask*/
+#define XSCUGIC_SPI_CPU1_MASK	0x00000002U /**< CPU 1 Mask*/
+#define XSCUGIC_SPI_CPU0_MASK	0x00000001U /**< CPU 0 Mask*/
+/* @} */
+
+/** @name  Interrupt Configuration Register 0xC00-0xCFC
+ * The interrupt configuration registers program an SFI to be active HIGH level
+ * sensitive or rising edge sensitive.
+ * Each bit pair describes the configuration for an INT_ID.
+ * SFI    Read Only    b10 always
+ * PPI    Read Only    depending on how the PPIs are configured.
+ *                    b01    Active HIGH level sensitive
+ *                    b11 Rising edge sensitive
+ * SPI                LSB is read only.
+ *                    b01    Active HIGH level sensitive
+ *                    b11 Rising edge sensitive/
+ * There are registers for each of the CPU interfaces at offset 0xC00 through
+ * 0xC04. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0xC08.
+ * @{
+ */
+#define XSCUGIC_INT_CFG_MASK    0x00000003U    /**< */
+/* @} */
+
+/** @name  PPI Status Register
+ * Enables an external AMBA master to access the status of the PPI inputs.
+ * A CPU can only read the status of its local PPI signals and cannot read the
+ * status for other CPUs.
+ * This register is aliased for each CPU interface.
+ * @{
+ */
+#define XSCUGIC_PPI_C15_MASK	0x00008000U    /**< PPI Status */
+#define XSCUGIC_PPI_C14_MASK	0x00004000U    /**< PPI Status */
+#define XSCUGIC_PPI_C13_MASK	0x00002000U    /**< PPI Status */
+#define XSCUGIC_PPI_C12_MASK	0x00001000U    /**< PPI Status */
+#define XSCUGIC_PPI_C11_MASK	0x00000800U    /**< PPI Status */
+#define XSCUGIC_PPI_C10_MASK	0x00000400U    /**< PPI Status */
+#define XSCUGIC_PPI_C09_MASK	0x00000200U    /**< PPI Status */
+#define XSCUGIC_PPI_C08_MASK	0x00000100U    /**< PPI Status */
+#define XSCUGIC_PPI_C07_MASK	0x00000080U    /**< PPI Status */
+#define XSCUGIC_PPI_C06_MASK	0x00000040U    /**< PPI Status */
+#define XSCUGIC_PPI_C05_MASK	0x00000020U    /**< PPI Status */
+#define XSCUGIC_PPI_C04_MASK	0x00000010U    /**< PPI Status */
+#define XSCUGIC_PPI_C03_MASK	0x00000008U    /**< PPI Status */
+#define XSCUGIC_PPI_C02_MASK	0x00000004U    /**< PPI Status */
+#define XSCUGIC_PPI_C01_MASK	0x00000002U    /**< PPI Status */
+#define XSCUGIC_PPI_C00_MASK	0x00000001U    /**< PPI Status */
+/* @} */
+
+/** @name  SPI Status Register 0xd04-0xd7C
+ * Enables an external AMBA master to access the status of the SPI inputs.
+ * There are up to 63 registers if the maximum number of SPI inputs are
+ * configured.
+ * @{
+ */
+#define XSCUGIC_SPI_N_MASK    0x00000001U    /**< Each bit corresponds to an SPI
+					     input */
+/* @} */
+
+/** @name  AHB Configuration Register
+ * Provides the status of the CFGBIGEND input signal and allows the endianess
+ * of the GIC to be set.
+ * @{
+ */
+#define XSCUGIC_AHB_END_MASK       0x00000004U    /**< 0-GIC uses little Endian,
+                                                  1-GIC uses Big Endian */
+#define XSCUGIC_AHB_ENDOVR_MASK    0x00000002U    /**< 0-Uses CFGBIGEND control,
+                                                  1-use the AHB_END bit */
+#define XSCUGIC_AHB_TIE_OFF_MASK   0x00000001U    /**< State of CFGBIGEND */
+
+/* @} */
+
+/** @name  Software Triggered Interrupt Register
+ * Controls issueing of software interrupts.
+ * @{
+ */
+#define XSCUGIC_SFI_SELFTRIG_MASK	0x02010000U
+#define XSCUGIC_SFI_TRIG_TRGFILT_MASK    0x03000000U    /**< Target List filter
+                                                            b00-Use the target List
+                                                            b01-All CPUs except requester
+                                                            b10-To Requester
+                                                            b11-reserved */
+#define XSCUGIC_SFI_TRIG_CPU_MASK	0x00FF0000U    /**< CPU Target list */
+#define XSCUGIC_SFI_TRIG_SATT_MASK	0x00008000U    /**< 0= Use a secure interrupt */
+#define XSCUGIC_SFI_TRIG_INTID_MASK	0x0000000FU    /**< Set to the INTID
+                                                        signaled to the CPU*/
+/* @} */
+
+/** @name CPU Interface Register Map
+ *
+ * Define the offsets from the base address for all CPU registers of the
+ * interrupt controller, some registers may be reserved in the hardware device.
+ * @{
+ */
+#define XSCUGIC_CONTROL_OFFSET		0x00000000U /**< CPU Interface Control
+							Register */
+#define XSCUGIC_CPU_PRIOR_OFFSET	0x00000004U /**< Priority Mask Reg */
+#define XSCUGIC_BIN_PT_OFFSET		0x00000008U /**< Binary Point Register */
+#define XSCUGIC_INT_ACK_OFFSET		0x0000000CU /**< Interrupt ACK Reg */
+#define XSCUGIC_EOI_OFFSET		0x00000010U /**< End of Interrupt Reg */
+#define XSCUGIC_RUN_PRIOR_OFFSET	0x00000014U /**< Running Priority Reg */
+#define XSCUGIC_HI_PEND_OFFSET		0x00000018U /**< Highest Pending Interrupt
+							Register */
+#define XSCUGIC_ALIAS_BIN_PT_OFFSET	0x0000001CU /**< Aliased non-Secure
+						        Binary Point Register */
+
+/**<  0x00000020 to 0x00000FBC are reserved and should not be read or written
+ * to. */
+/* @} */
+
+
+/** @name Control Register
+ * CPU Interface Control register definitions
+ * All bits are defined here although some are not available in the non-secure
+ * mode.
+ * @{
+ */
+#define XSCUGIC_CNTR_SBPR_MASK	0x00000010U    /**< Secure Binary Pointer,
+                                                 0=separate registers,
+                                                 1=both use bin_pt_s */
+#define XSCUGIC_CNTR_FIQEN_MASK	0x00000008U    /**< Use nFIQ_C for secure
+                                                  interrupts,
+                                                  0= use IRQ for both,
+                                                  1=Use FIQ for secure, IRQ for non*/
+#define XSCUGIC_CNTR_ACKCTL_MASK	0x00000004U    /**< Ack control for secure or non secure */
+#define XSCUGIC_CNTR_EN_NS_MASK		0x00000002U    /**< Non Secure enable */
+#define XSCUGIC_CNTR_EN_S_MASK		0x00000001U    /**< Secure enable, 0=Disabled, 1=Enabled */
+/* @} */
+
+/** @name Priority Mask Register
+ * Priority Mask register definitions
+ * The CPU interface does not send interrupt if the level of the interrupt is
+ * lower than the level of the register.
+ * @{
+ */
+/*#define XSCUGIC_PRIORITY_MASK		0x000000FFU*/   /**< All interrupts */
+/* @} */
+
+/** @name Binary Point Register
+ * Binary Point register definitions
+ * @{
+ */
+
+#define XSCUGIC_BIN_PT_MASK	0x00000007U  /**< Binary point mask value
+						Value  Secure  Non-secure
+						b000    0xFE    0xFF
+						b001    0xFC    0xFE
+						b010    0xF8    0xFC
+						b011    0xF0    0xF8
+						b100    0xE0    0xF0
+						b101    0xC0    0xE0
+						b110    0x80    0xC0
+						b111    0x00    0x80
+						*/
+/*@}*/
+
+/** @name Interrupt Acknowledge Register
+ * Interrupt Acknowledge register definitions
+ * Identifies the current Pending interrupt, and the CPU ID for software
+ * interrupts.
+ */
+#define XSCUGIC_ACK_INTID_MASK		0x000003FFU /**< Interrupt ID */
+#define XSCUGIC_CPUID_MASK		0x00000C00U /**< CPU ID */
+/* @} */
+
+/** @name End of Interrupt Register
+ * End of Interrupt register definitions
+ * Allows the CPU to signal the GIC when it completes an interrupt service
+ * routine.
+ */
+#define XSCUGIC_EOI_INTID_MASK		0x000003FFU /**< Interrupt ID */
+
+/* @} */
+
+/** @name Running Priority Register
+ * Running Priority register definitions
+ * Identifies the interrupt priority level of the highest priority active
+ * interrupt.
+ */
+#define XSCUGIC_RUN_PRIORITY_MASK	0x000000FFU    /**< Interrupt Priority */
+/* @} */
+
+/*
+ * Highest Pending Interrupt register definitions
+ * Identifies the interrupt priority of the highest priority pending interupt
+ */
+#define XSCUGIC_PEND_INTID_MASK		0x000003FFU /**< Pending Interrupt ID */
+/*#define XSCUGIC_CPUID_MASK		0x00000C00U */	 /**< CPU ID */
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Configuration Register offset for an interrupt id.
+*
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
+	((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Priority Register offset for an interrupt id.
+*
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
+	((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the SPI Target Register offset for an interrupt id.
+*
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
+	((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Clear-Enable Register offset for an interrupt ID
+*
+* @param	Register is the register offset for the clear/enable bank.
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \
+		((Register) + (((InterruptID)/32U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the given Intc register.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_ReadReg(BaseAddress, RegOffset) \
+	(Xil_In32((BaseAddress) + (RegOffset)))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given Intc register.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note
+* C-style signature:
+*    void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
+	(Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data))))
+
+
+/****************************************************************************/
+/**
+*
+* Enable specific interrupt(s) in the interrupt controller.
+*
+* @param	DistBaseAddress is the Distributor Register base address of the
+*		device
+* @param	Int_Id is the ID of the interrupt source and should be in the
+*		range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id)
+*
+*****************************************************************************/
+#define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \
+	XScuGic_WriteReg((DistBaseAddress), \
+			 XSCUGIC_ENABLE_SET_OFFSET + (((Int_Id) / 32U) * 4U), \
+			 (0x00000001U << ((Int_Id) % 32U)))
+
+/****************************************************************************/
+/**
+*
+* Disable specific interrupt(s) in the interrupt controller.
+*
+* @param	DistBaseAddress is the Distributor Register base address of the
+*		device
+* @param	Int_Id is the ID of the interrupt source and should be in the
+*		range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id)
+*
+*****************************************************************************/
+#define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \
+	XScuGic_WriteReg((DistBaseAddress), \
+			 XSCUGIC_DISABLE_OFFSET + (((Int_Id) / 32U) * 4U), \
+			 (0x00000001U << ((Int_Id) % 32U)))
+
+
+/************************** Function Prototypes ******************************/
+
+void XScuGic_DeviceInterruptHandler(void *DeviceId);
+s32  XScuGic_DeviceInitialize(u32 DeviceId);
+void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
+			     Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+                                        u8 Priority, u8 Trigger);
+void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+					u8 *Priority, u8 *Trigger);
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscutimer.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscutimer.h
new file mode 100644
index 0000000000000000000000000000000000000000..ea4ba79de086a74eb57b0ab5c22fe3441ee3ce1e
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscutimer.h
@@ -0,0 +1,368 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer.h
+* @addtogroup scutimer_v2_1
+* @{
+* @details
+*
+* The timer driver supports the Cortex A9 private timer.
+*
+* The timer driver supports the following features:
+* - Normal mode and Auto reload mode
+* - Interrupts (Interrupt handler is not provided in this driver. Application
+* 		has to register it's own handler)
+*
+* <b> Initialization and Configuration </b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Timer.
+*
+* XScuTimer_CfgInitialize() API is used to initialize the Timer. The
+* user needs to first call the XScuTimer_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to
+* the XScuTimer_CfgInitialize() API.
+*
+* <b> Interrupts </b>
+*
+* The Timer hardware supports interrupts.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* Timer in interrupt mode.
+*
+* <b> Virtual Memory </b>
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+* <b> Threads </b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* <b> Asserts </b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* <b> Building the driver </b>
+*
+* The XScuTimer driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* <br><br>
+*
+* NOTE:
+* The timer is not a part of the snoop control unit as indicated by the
+* prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm  03/10/10 First release
+* 1.02a sg  07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+*                    generation.
+* </pre>
+*
+******************************************************************************/
+#ifndef XSCUTIMER_H		/* prevent circular inclusions */
+#define XSCUTIMER_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xscutimer_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;	/**< Unique ID of device */
+	u32 BaseAddr;	/**< Base address of the device */
+} XScuTimer_Config;
+
+/**
+ * The XScuTimer driver instance data. The user is required to allocate a
+ * variable of this type for every timer device in the system.
+ * A pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+	XScuTimer_Config Config; /**< Hardware Configuration */
+	u32 IsReady;		/**< Device is initialized and ready */
+	u32 IsStarted;		/**< Device timer is running */
+} XScuTimer;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Check if the timer has expired.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return
+*		- TRUE if the timer has expired.
+*		- FALSE if the timer has not expired.
+*
+* @note		C-style signature:
+*		int XScuTimer_IsExpired(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_IsExpired(InstancePtr) \
+	((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+				XSCUTIMER_ISR_OFFSET) & \
+				XSCUTIMER_ISR_EVENT_FLAG_MASK) == \
+				XSCUTIMER_ISR_EVENT_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* Re-start the timer. This macro will read the timer load register
+* and writes the same value to load register to update the counter register.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_RestartTimer(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_RestartTimer(InstancePtr)				\
+	XScuTimer_LoadTimer((InstancePtr),				\
+		XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+					XSCUTIMER_LOAD_OFFSET))
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+* @param	Value is the count to be loaded in to the load register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_LoadTimer(XScuTimer *InstancePtr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_LoadTimer(InstancePtr, Value)				\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value. It can be called at any
+* time.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	Contents of the timer counter register.
+*
+* @note		C-style signature:
+		u32 XScuTimer_GetCounterValue(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_GetCounterValue(InstancePtr)				\
+	XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,		\
+				XSCUTIMER_COUNTER_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Enable auto-reload mode.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_EnableAutoReload(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_EnableAutoReload(InstancePtr)				\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_CONTROL_OFFSET,			\
+			(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+				XSCUTIMER_CONTROL_OFFSET) |		 \
+				XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable auto-reload mode.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_DisableAutoReload(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_DisableAutoReload(InstancePtr)			\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_CONTROL_OFFSET,			\
+			(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+				XSCUTIMER_CONTROL_OFFSET) &		\
+				~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Enable the Timer interrupt.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_EnableInterrupt(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_EnableInterrupt(InstancePtr)				\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_CONTROL_OFFSET,			\
+			(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+					XSCUTIMER_CONTROL_OFFSET) |	\
+					XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable the Timer interrupt.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_DisableInterrupt(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_DisableInterrupt(InstancePtr)				\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_CONTROL_OFFSET,			\
+			(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+				XSCUTIMER_CONTROL_OFFSET) &		\
+				~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)))
+
+/*****************************************************************************/
+/**
+*
+* This function reads the interrupt status.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_GetInterruptStatus(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_GetInterruptStatus(InstancePtr)			\
+	XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_ISR_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears the interrupt status.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_ClearInterruptStatus(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_ClearInterruptStatus(InstancePtr)			\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+		XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xscutimer_sinit.c
+ */
+XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xscutimer_selftest.c
+ */
+s32 XScuTimer_SelfTest(XScuTimer *InstancePtr);
+
+/*
+ * Interface functions in xscutimer.c
+ */
+s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
+			    XScuTimer_Config *ConfigPtr, u32 EffectiveAddress);
+void XScuTimer_Start(XScuTimer *InstancePtr);
+void XScuTimer_Stop(XScuTimer *InstancePtr);
+void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue);
+u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscutimer_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscutimer_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..ac7b42934796aa41e49adfc510057e951e0b2e0d
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscutimer_hw.h
@@ -0,0 +1,287 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer_hw.h
+* @addtogroup scutimer_v2_1
+* @{
+*
+* This file contains the hardware interface to the Timer.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm  03/10/10 First release
+* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control
+*		     and interrupt registers
+* 1.02a  sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+#ifndef XSCUTIMER_HW_H		/* prevent circular inclusions */
+#define XSCUTIMER_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device
+ * @{
+ */
+
+#define XSCUTIMER_LOAD_OFFSET		0x00U /**< Timer Load Register */
+#define XSCUTIMER_COUNTER_OFFSET	0x04U /**< Timer Counter Register */
+#define XSCUTIMER_CONTROL_OFFSET	0x08U /**< Timer Control Register */
+#define XSCUTIMER_ISR_OFFSET		0x0CU /**< Timer Interrupt
+						  Status Register */
+/* @} */
+
+/** @name Timer Control register
+ * This register bits control the prescaler, Intr enable,
+ * auto-reload and timer enable.
+ * @{
+ */
+
+#define XSCUTIMER_CONTROL_PRESCALER_MASK	0x0000FF00U /**< Prescaler */
+#define XSCUTIMER_CONTROL_PRESCALER_SHIFT	8U
+#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK	0x00000004U /**< Intr enable */
+#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK	0x00000002U /**< Auto-reload */
+#define XSCUTIMER_CONTROL_ENABLE_MASK		0x00000001U /**< Timer enable */
+/* @} */
+
+/** @name Interrupt Status register
+ * This register indicates the Timer counter register has reached zero.
+ * @{
+ */
+
+#define XSCUTIMER_ISR_EVENT_FLAG_MASK		0x00000001U /**< Event flag */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+* @param	Value is the count to be loaded in to the load register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetLoadReg(BaseAddr, Value)				\
+	XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer load register value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+*
+* @return	Contents of the timer load register.
+*
+* @note		C-style signature:
+*		u32 XScuTimer_GetLoadReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetLoadReg(BaseAddr)					\
+	XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer counter register.
+*
+* @param	BaseAddr is the base address of the scu timer.
+* @param	Value is the count to be loaded in to the counter register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetCounterReg(BaseAddr, Value)			\
+	XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+*
+* @return	Contents of the timer counter register.
+*
+* @note		C-style signature:
+		u32 XScuTimer_GetCounterReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetCounterReg(BaseAddr)				\
+	XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+* @param	Value is the count to be loaded in to the load register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetControlReg(BaseAddr, Value)			\
+	XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer load register value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+*
+* @return	Contents of the timer load register.
+*
+* @note		C-style signature:
+		u32 XScuTimer_GetControlReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetControlReg(BaseAddr)				\
+	XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer counter register.
+*
+* @param	BaseAddr is the base address of the scu timer.
+* @param	Value is the count to be loaded in to the counter register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetIntrReg(BaseAddr, Value)				\
+	XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+*
+* @return	Contents of the timer counter register.
+*
+* @note		C-style signature:
+		u32 XScuTimer_GetIntrReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetIntrReg(BaseAddr)					\
+	XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Read from the given Timer register.
+*
+* @param	BaseAddr is the base address of the device
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note		C-style signature:
+*		u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuTimer_ReadReg(BaseAddr, RegOffset)		\
+	Xil_In32((BaseAddr) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write to the given Timer register.
+*
+* @param	BaseAddr is the base address of the device
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data)	\
+	Xil_Out32((BaseAddr) + (RegOffset), (Data))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscuwdt.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscuwdt.h
new file mode 100644
index 0000000000000000000000000000000000000000..372bbc3439aadbb94cf3fe04b97535757d4d1107
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscuwdt.h
@@ -0,0 +1,383 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt.h
+* @addtogroup scuwdt_v2_1
+* @{
+* @details
+*
+* The Xilinx SCU watchdog timer driver (XScuWdt) supports the Xilinx SCU private
+* watchdog timer hardware.
+*
+* The XScuWdt driver supports the following features:
+* - Watchdog mode
+* - Timer mode
+* - Auto reload (timer mode only)
+*
+* The watchdog counter register is a down counter and starts decrementing when
+* the watchdog is started.
+* In watchdog mode, when the counter reaches 0, the Reset flag is set in the
+* Reset status register and the WDRESETREQ pin is asserted, causing a system
+* reset. The Reset flag is not reset by normal processor reset and is cleared
+* when written with a value of 1. This enables the user to differentiate a
+* normal reset and a reset caused by watchdog time-out. The user needs to call
+* XScuWdt_RestartWdt() periodically, to avoid the watchdog from being timed-out.
+*
+* The IsWdtExpired function can be used to check if the watchdog was the cause
+* of the last reset. In this situation, call Initialize then call IsWdtExpired.
+* If the result is true, watchdog timeout caused the last system reset. The
+* application then needs to clear the Reset flag.
+*
+* In timer mode, when the counter reaches 0, the Event flag is set in the
+* Interrupt status register and if interrupts are enabled, interrupt ID 30 is
+* set as pending in the interrupt distributor. The IsTimerExpired function
+* is used to check if the watchdog counter has decremented to 0 in timer mode.
+* If auto-reload mode is enabled, the Counter register is automatically reloaded
+* from the Load register.
+*
+* <b> Initialization and Configuration </b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Watchdog Timer.
+*
+* XScuWdt_CfgInitialize() API is used to initialize the Watchdog Timer. The
+* user needs to first call the XScuWdt_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to
+* the XScuWdt_CfgInitialize() API.
+*
+* <b>Interrupts</b>
+*
+* The SCU Watchdog Timer supports interrupts in Timer mode.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* Timer in interrupt mode.
+*
+* <b> Virtual Memory </b>
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+* <b> Threads </b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* <b> Asserts </b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* <b> Building the driver </b>
+*
+* The XScuWdt driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* <br><br>
+*
+* NOTE:
+* The watchdog timer is not a part of the snoop control unit as indicated
+* by the prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.02a  sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+*                    generation.
+* </pre>
+*
+******************************************************************************/
+#ifndef XSCUWDT_H		/* prevent circular inclusions */
+#define XSCUWDT_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xscuwdt_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID of device */
+	u32 BaseAddr;		/**< Base address of the device */
+} XScuWdt_Config;
+
+/**
+ * The XScuWdt driver instance data. The user is required to allocate a
+ * variable of this type for every watchdog/timer device in the system.
+ * A pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+	XScuWdt_Config Config;/**< Hardware Configuration */
+	u32 IsReady;		/**< Device is initialized and ready */
+	u32 IsStarted;		/**< Device watchdog timer is running */
+} XScuWdt;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/****************************************************************************/
+/**
+*
+* This function is used to check if the watchdog has timed-out and the last
+* reset was caused by the watchdog reset.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+*		- TRUE if the watchdog has expired.
+*		- FALSE if the watchdog has not expired.
+*
+* @note		C-style signature:
+*		int XScuWdt_IsWdtExpired(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_IsWdtExpired(InstancePtr)				\
+	((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,		\
+			  XSCUWDT_RST_STS_OFFSET) &			\
+	 XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* This function is used to check if the watchdog counter has reached 0 in timer
+* mode.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+*		- TRUE if the watchdog has expired.
+*		- FALSE if the watchdog has not expired.
+*
+* @note		C-style signature:
+*		int XScuWdt_IsTimerExpired(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_IsTimerExpired(InstancePtr)				\
+	((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,		\
+			  XSCUWDT_ISR_OFFSET) &				\
+	 XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* Re-start the watchdog timer. This macro will read the watchdog load register
+* and write the same value to load register to update the counter register.
+* An application needs to call this function periodically to keep the watchdog
+* from asserting the WDRESETREQ reset request output pin.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_RestartWdt(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_RestartWdt(InstancePtr)					 \
+	XScuWdt_LoadWdt((InstancePtr),					 \
+			(XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+					 XSCUWDT_LOAD_OFFSET)))
+
+/****************************************************************************/
+/**
+*
+* Write to the watchdog timer load register. This will also update the
+* watchdog counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+* @param	Value is the value to be written to the Watchdog Load register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_LoadWdt(XScuWdt *InstancePtr, u32 Value)
+*
+******************************************************************************/
+#define XScuWdt_LoadWdt(InstancePtr, Value)				\
+	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUWDT_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Put the watchdog timer in Watchdog mode by setting the WD mode bit of the
+* Watchdog control register.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_SetWdMode(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_SetWdMode(InstancePtr)					  \
+	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		  \
+			 XSCUWDT_CONTROL_OFFSET,			  \
+			 (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+			  XSCUWDT_CONTROL_OFFSET) |			  \
+			  (XSCUWDT_CONTROL_WD_MODE_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Put the watchdog timer in Timer mode by writing 0x12345678 and 0x87654321
+* successively to the Watchdog Disable Register.
+* The software must write 0x12345678 and 0x87654321 successively to the
+* Watchdog Disable Register so that the watchdog mode bit in the Watchdog
+* Control Register is set to zero.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_SetTimerMode(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_SetTimerMode(InstancePtr)				\
+{									\
+	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUWDT_DISABLE_OFFSET,				\
+			XSCUWDT_DISABLE_VALUE1);			\
+	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUWDT_DISABLE_OFFSET,				\
+			XSCUWDT_DISABLE_VALUE2);			\
+}
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the watchdog control register.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	Contents of the watchdog control register.
+*
+* @note		C-style signature:
+		u32 XScuWdt_GetControlReg(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_GetControlReg(InstancePtr)				\
+	XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,			\
+			XSCUWDT_CONTROL_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the watchdog control register.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+* @param	ControlReg is the value to be written to the watchdog control
+*		register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+		void XScuWdt_SetControlReg(XScuWdt *InstancePtr, u32 ControlReg)
+*
+******************************************************************************/
+#define XScuWdt_SetControlReg(InstancePtr, ControlReg)			\
+	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			 XSCUWDT_CONTROL_OFFSET, (ControlReg))
+
+/****************************************************************************/
+/**
+*
+* Enable auto-reload mode.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_EnableAutoReload(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_EnableAutoReload(InstancePtr)				\
+	XScuWdt_SetControlReg((InstancePtr),				\
+			      (XScuWdt_GetControlReg(InstancePtr) |	\
+			      XSCUWDT_CONTROL_AUTO_RELOAD_MASK))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xscuwdt_sinit.c.
+ */
+XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xscuwdt_selftest.c
+ */
+s32 XScuWdt_SelfTest(XScuWdt *InstancePtr);
+
+/*
+ * Interface functions in xscuwdt.c
+ */
+s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
+			  XScuWdt_Config *ConfigPtr, u32 EffectiveAddress);
+
+void XScuWdt_Start(XScuWdt *InstancePtr);
+
+void XScuWdt_Stop(XScuWdt *InstancePtr);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscuwdt_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscuwdt_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..2067d3a531870de0fe1851b65a2f653f58aa73f8
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xscuwdt_hw.h
@@ -0,0 +1,182 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt_hw.h
+* @addtogroup scuwdt_v2_1
+* @{
+*
+* This file contains the hardware interface to the Xilinx SCU private Watch Dog
+* Timer (XSCUWDT).
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.01a bss 02/27/12 Updated the register offsets to start at 0x0 instead
+*                    of 0x20 as the base address obtained from the tools
+*		     starts at 0x20.
+* 1.02a  sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+#ifndef XSCUWDT_HW_H		/* prevent circular inclusions */
+#define XSCUWDT_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device. The WDT registers start at
+ * an offset 0x20
+ * @{
+ */
+
+#define XSCUWDT_LOAD_OFFSET	0x00U /**< Watchdog Load Register */
+#define XSCUWDT_COUNTER_OFFSET	0x04U /**< Watchdog Counter Register */
+#define XSCUWDT_CONTROL_OFFSET	0x08U /**< Watchdog Control Register */
+#define XSCUWDT_ISR_OFFSET	0x0CU /**< Watchdog Interrupt Status Register */
+#define XSCUWDT_RST_STS_OFFSET	0x10U /**< Watchdog Reset Status Register */
+#define XSCUWDT_DISABLE_OFFSET	0x14U /**< Watchdog Disable Register */
+/* @} */
+
+/** @name Watchdog Control register
+ * This register bits control the prescaler, WD/Timer mode, Intr enable,
+ * auto-reload, watchdog enable.
+ * @{
+ */
+
+#define XSCUWDT_CONTROL_PRESCALER_MASK	 0x0000FF00U /**< Prescaler */
+#define XSCUWDT_CONTROL_PRESCALER_SHIFT	 8U
+#define XSCUWDT_CONTROL_WD_MODE_MASK	 0x00000008U /**< Watchdog/Timer mode */
+#define XSCUWDT_CONTROL_IT_ENABLE_MASK	 0x00000004U /**< Intr enable (in
+							 timer mode) */
+#define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload (in
+							 timer mode) */
+#define XSCUWDT_CONTROL_WD_ENABLE_MASK	 0x00000001U /**< Watchdog enable */
+/* @} */
+
+/** @name Interrupt Status register
+ * This register indicates the Counter register has reached zero in Counter
+ * mode.
+ * @{
+ */
+
+#define XSCUWDT_ISR_EVENT_FLAG_MASK	0x00000001U /**< Event flag */
+/*@}*/
+
+/** @name Reset Status register
+ * This register indicates the Counter register has reached zero in Watchdog
+ * mode and a reset request is sent.
+ * @{
+ */
+
+#define XSCUWDT_RST_STS_RESET_FLAG_MASK	0x00000001U /**< Time out occured */
+/*@}*/
+
+/** @name Disable register
+ * This register is used to switch from watchdog mode to timer mode.
+ * The software must write 0x12345678 and 0x87654321 successively to the
+ * Watchdog Disable Register so that the watchdog mode bit in the Watchdog
+ * Control Register is set to zero.
+ * @{
+ */
+#define XSCUWDT_DISABLE_VALUE1		0x12345678U /**< Watchdog mode disable
+							value 1 */
+#define XSCUWDT_DISABLE_VALUE2		0x87654321U /**< Watchdog mode disable
+							value 2 */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param	BaseAddr is the base address of the device
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note		C-style signature:
+*		u32 XScuWdt_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuWdt_ReadReg(BaseAddr, RegOffset)		\
+	Xil_In32((BaseAddr) + ((u32)RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param	BaseAddr is the base address of the device
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuWdt_WriteReg(BaseAddr, RegOffset, Data)	\
+	Xil_Out32((BaseAddr) + ((u32)RegOffset), ((u32)Data))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xsdps.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xsdps.h
new file mode 100644
index 0000000000000000000000000000000000000000..9e475207daa03784e2c9d030ca0bf7cc45f50c36
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xsdps.h
@@ -0,0 +1,263 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps.h
+* @addtogroup sdps_v2_5
+* @{
+* @details
+*
+* This file contains the implementation of XSdPs driver.
+* This driver is used initialize read from and write to the SD card.
+* Features such as switching bus width to 4-bit and switching to high speed,
+* changing clock frequency, block size etc. are supported.
+* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however
+* is done using 1-bit bus width and 400KHz clock frequency.
+* SD commands are classified as broadcast and addressed. Commands can be
+* those with response only (using only command line) or
+* response + data (using command and data lines).
+* Only one command can be sent at a time. During a data transfer however,
+* when dsta lines are in use, certain commands (which use only the command
+* line) can be sent, most often to obtain status.
+* This driver does not support multi card slots at present.
+*
+* Intialization:
+* This includes initialization on the host controller side to select
+* clock frequency, bus power and default transfer related parameters.
+* The default voltage is 3.3V.
+* On the SD card side, the initialization and identification state diagram is
+* implemented. This resets the card, gives it a unique address/ID and
+* identifies key card related specifications.
+*
+* Data transfer:
+* The SD card is put in tranfer state to read from or write to it.
+* The default block size is 512 bytes and if supported,
+* default bus width is 4-bit and bus speed is High speed.
+* The read and write functions are implemented in polled mode using ADMA2.
+*
+* At any point, when key parameters such as block size or
+* clock/speed or bus width are modified, this driver takes care of
+* maintaining the same selection on host and card.
+* All error bits in host controller are monitored by the driver and in the
+* event one of them is set, driver will clear the interrupt status and
+* communicate failure to the upper layer.
+*
+* File system use:
+* This driver can be used with xilffs library to read and write files to SD.
+* (Please refer to procedure in diskio.c). The file system read/write example
+* in polled mode can used for reference.
+*
+* There is no example for using SD driver without file system at present.
+* However, the driver can be used without the file system. The glue layer
+* in filesytem can be used as reference for the same. The block count
+* passed to the read/write function in one call is limited by the ADMA2
+* descriptor table and hence care will have to be taken to call read/write
+* API's in a loop for large file sizes.
+*
+* Interrupt mode is not supported because it offers no improvement when used
+* with file system.
+*
+* eMMC support:
+* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK.
+* The features of eMMC supported by the driver will depend on those supported
+* by the host controller. The current driver supports read/write on eMMC card
+* using 4-bit and high speed mode currently.
+*
+* Features not supported include - card write protect, password setting,
+* lock/unlock, interrupts, SDMA mode, programmed I/O mode and
+* 64-bit addressed ADMA2, erase/pre-erase commands.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.0   hk      03/07/14 Version number revised.
+* 2.1   hk     04/18/14 Increase sleep for eMMC switch command.
+*                       Add sleep for microblaze designs. CR# 781117.
+* 2.2   hk     07/28/14 Make changes to enable use of data cache.
+* 2.3   sk     09/23/14 Send command for relative card address
+*                       when re-initialization is done.CR# 819614.
+*						Use XSdPs_Change_ClkFreq API whenever changing
+*						clock.CR# 816586.
+* 2.4	sk	   12/04/14 Added support for micro SD without
+* 						WP/CD. CR# 810655.
+*						Checked for DAT Inhibit mask instead of CMD
+* 						Inhibit mask in Cmd Transfer API.
+*						Added Support for SD Card v1.0
+* 2.5 	sg		07/09/15 Added SD 3.0 features
+*       kvn     07/15/15 Modified the code according to MISRAC-2012.
+* 2.6   sk     10/12/15 Added support for SD card v1.0 CR# 840601.
+* 2.7   sk     11/24/15 Considered the slot type befoe checking CD/WP pins.
+*       sk     12/10/15 Added support for MMC cards.
+*              01/08/16 Added workaround for issue in auto tuning mode
+*                       of SDR50, SDR104 and HS200.
+*       sk     02/16/16 Corrected the Tuning logic.
+*       sk     03/01/16 Removed Bus Width check for eMMC. CR# 938311.
+* 2.8   sk     04/20/16 Added new workaround for auto tuning.
+*              05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
+* 3.0   sk     06/09/16 Added support for mkfs to calculate sector count.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/07/16 Used usleep API for both arm and microblaze.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+*       sk     08/13/16 Removed sleep.h from xsdps.h as a temporary fix for
+*                       CR#956899.
+* 3.1   mi     09/07/16 Removed compilation warnings with extra compiler flags.
+*       sk     10/13/16 Reduced the delay during power cycle to 1ms as per spec
+*       sk     10/19/16 Used emmc_hwreset pin to reset eMMC.
+*       sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+*       sk     11/16/16 Issue DLL reset at 31 iteration to load new zero value.
+* 3.2   sk     11/30/16 Modified the voltage switching sequence as per spec.
+*       sk     02/01/17 Added HSD and DDR mode support for eMMC.
+*       sk     02/01/17 Consider bus width parameter from design for switching
+*       vns    02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
+*       sk     03/20/17 Add support for EL1 non-secure mode.
+*
+* </pre>
+*
+******************************************************************************/
+
+
+#ifndef SDPS_H_
+#define SDPS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_printf.h"
+#include "xil_cache.h"
+#include "xstatus.h"
+#include "xsdps_hw.h"
+#include <string.h>
+
+/************************** Constant Definitions *****************************/
+
+#define XSDPS_CT_ERROR	0x2U	/**< Command timeout flag */
+#define MAX_TUNING_COUNT	40U		/**< Maximum Tuning count */
+
+/**************************** Type Definitions *******************************/
+
+typedef void (*XSdPs_ConfigTap) (u32 Bank, u32 DeviceId, u32 CardType);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;			/**< Unique ID  of device */
+	u32 BaseAddress;		/**< Base address of the device */
+	u32 InputClockHz;		/**< Input clock frequency */
+	u32 CardDetect;			/**< Card Detect */
+	u32 WriteProtect;			/**< Write Protect */
+	u32 BusWidth;			/**< Bus Width */
+	u32 BankNumber;			/**< MIO Bank selection for SD */
+	u32 HasEMIO;			/**< If SD is connected to EMIO */
+} XSdPs_Config;
+
+/* ADMA2 descriptor table */
+typedef struct {
+	u16 Attribute;		/**< Attributes of descriptor */
+	u16 Length;		/**< Length of current dma transfer */
+	u32 Address;		/**< Address of current dma transfer */
+} XSdPs_Adma2Descriptor;
+
+/**
+ * The XSdPs driver instance data. The user is required to allocate a
+ * variable of this type for every SD device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XSdPs_Config Config;	/**< Configuration structure */
+	u32 IsReady;		/**< Device is initialized and ready */
+	u32 Host_Caps;		/**< Capabilities of host controller */
+	u32 Host_CapsExt;	/**< Extended Capabilities */
+	u32 HCS;		/**< High capacity support in card */
+	u8  CardType;		/**< Type of card - SD/MMC/eMMC */
+	u8  Card_Version;	/**< Card version */
+	u8  HC_Version;		/**< Host controller version */
+	u8  BusWidth;		/**< Current operating bus width */
+	u32 BusSpeed;		/**< Current operating bus speed */
+	u8  Switch1v8;		/**< 1.8V Switch support */
+	u32 CardID[4];		/**< Card ID Register */
+	u32 RelCardAddr;	/**< Relative Card Address */
+	u32 CardSpecData[4];	/**< Card Specific Data Register */
+	u32 SectorCount;		/**< Sector Count */
+	u32 SdCardConfig;	/**< Sd Card Configuration Register */
+	u32 Mode;			/**< Bus Speed Mode */
+	XSdPs_ConfigTap Config_TapDelay;	/**< Configuring the tap delays */
+	/**< ADMA Descriptors */
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+	XSdPs_Adma2Descriptor Adma2_DescrTbl[32];
+#pragma data_alignment = 4
+#else
+	XSdPs_Adma2Descriptor Adma2_DescrTbl[32] __attribute__ ((aligned(32)));
+#endif
+} XSdPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId);
+s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
+				u32 EffectiveAddr);
+s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
+s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);
+s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize);
+s32 XSdPs_Select_Card (XSdPs *InstancePtr);
+s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq);
+s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr);
+s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr);
+s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR);
+s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff);
+s32 XSdPs_Pullup(XSdPs *InstancePtr);
+s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_CardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff);
+s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg);
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff);
+void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_H_ */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xsdps_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xsdps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..6bb6c2a616ca3bcc38a0270f58b558870f172b5b
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xsdps_hw.h
@@ -0,0 +1,1249 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_hw.h
+* @addtogroup sdps_v2_5
+* @{
+*
+* This header file contains the identifiers and basic HW access driver
+* functions (or  macros) that can be used to access the device. Other driver
+* functions are defined in xsdps.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.5 	sg	   07/09/15 Added SD 3.0 features
+*       kvn    07/15/15 Modified the code according to MISRAC-2012.
+* 2.7   sk     12/10/15 Added support for MMC cards.
+*       sk     03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
+* 2.8   sk     04/20/16 Added new workaround for auto tuning.
+* 3.0   sk     06/09/16 Added support for mkfs to calculate sector count.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+* 3.1   sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* 3.2   sk     03/20/17 Add support for EL1 non-secure mode.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef SD_HW_H_
+#define SD_HW_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of an SD device.
+ * @{
+ */
+
+#define XSDPS_SDMA_SYS_ADDR_OFFSET	0x00U	/**< SDMA System Address
+							Register */
+#define XSDPS_SDMA_SYS_ADDR_LO_OFFSET	XSDPS_SDMA_SYS_ADDR_OFFSET
+						/**< SDMA System Address
+							Low Register */
+#define XSDPS_ARGMT2_LO_OFFSET		0x00U	/**< Argument2 Low Register */
+#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET	0x02U	/**< SDMA System Address
+							High Register */
+#define XSDPS_ARGMT2_HI_OFFSET		0x02U	/**< Argument2 High Register */
+
+#define XSDPS_BLK_SIZE_OFFSET		0x04U	/**< Block Size Register */
+#define XSDPS_BLK_CNT_OFFSET		0x06U	/**< Block Count Register */
+#define XSDPS_ARGMT_OFFSET		0x08U	/**< Argument Register */
+#define XSDPS_ARGMT1_LO_OFFSET		XSDPS_ARGMT_OFFSET
+						/**< Argument1 Register */
+#define XSDPS_ARGMT1_HI_OFFSET		0x0AU	/**< Argument1 Register */
+
+#define XSDPS_XFER_MODE_OFFSET		0x0CU	/**< Transfer Mode Register */
+#define XSDPS_CMD_OFFSET		0x0EU	/**< Command Register */
+#define XSDPS_RESP0_OFFSET		0x10U	/**< Response0 Register */
+#define XSDPS_RESP1_OFFSET		0x14U	/**< Response1 Register */
+#define XSDPS_RESP2_OFFSET		0x18U	/**< Response2 Register */
+#define XSDPS_RESP3_OFFSET		0x1CU	/**< Response3 Register */
+#define XSDPS_BUF_DAT_PORT_OFFSET	0x20U	/**< Buffer Data Port */
+#define XSDPS_PRES_STATE_OFFSET		0x24U	/**< Present State */
+#define XSDPS_HOST_CTRL1_OFFSET		0x28U	/**< Host Control 1 */
+#define XSDPS_POWER_CTRL_OFFSET		0x29U	/**< Power Control */
+#define XSDPS_BLK_GAP_CTRL_OFFSET	0x2AU	/**< Block Gap Control */
+#define XSDPS_WAKE_UP_CTRL_OFFSET	0x2BU	/**< Wake Up Control */
+#define XSDPS_CLK_CTRL_OFFSET		0x2CU	/**< Clock Control */
+#define XSDPS_TIMEOUT_CTRL_OFFSET	0x2EU	/**< Timeout Control */
+#define XSDPS_SW_RST_OFFSET		0x2FU	/**< Software Reset */
+#define XSDPS_NORM_INTR_STS_OFFSET 	0x30U	/**< Normal Interrupt
+							Status Register */
+#define XSDPS_ERR_INTR_STS_OFFSET 	0x32U	/**< Error Interrupt
+							Status Register */
+#define XSDPS_NORM_INTR_STS_EN_OFFSET	0x34U	/**< Normal Interrupt
+						Status Enable Register */
+#define XSDPS_ERR_INTR_STS_EN_OFFSET	0x36U	/**< Error Interrupt
+						Status Enable Register */
+#define XSDPS_NORM_INTR_SIG_EN_OFFSET	0x38U	/**< Normal Interrupt
+						Signal Enable Register */
+#define XSDPS_ERR_INTR_SIG_EN_OFFSET	0x3AU	/**< Error Interrupt
+						Signal Enable Register */
+
+#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET	0x3CU	/**< Auto CMD12 Error Status
+							Register */
+#define XSDPS_HOST_CTRL2_OFFSET		0x3EU	/**< Host Control2 Register */
+#define XSDPS_CAPS_OFFSET 		0x40U	/**< Capabilities Register */
+#define XSDPS_CAPS_EXT_OFFSET 		0x44U	/**< Capabilities Extended */
+#define XSDPS_MAX_CURR_CAPS_OFFSET	0x48U	/**< Maximum Current
+						Capabilities Register */
+#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET	0x4CU	/**< Maximum Current
+						Capabilities Ext Register */
+#define XSDPS_FE_ERR_INT_STS_OFFSET	0x52U	/**< Force Event for
+						Error Interrupt Status */
+#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET	0x50U	/**< Auto CM12 Error Interrupt
+							Status Register */
+#define XSDPS_ADMA_ERR_STS_OFFSET	0x54U	/**< ADMA Error Status
+							Register */
+#define XSDPS_ADMA_SAR_OFFSET		0x58U	/**< ADMA System Address
+							Register */
+#define XSDPS_ADMA_SAR_EXT_OFFSET	0x5CU	/**< ADMA System Address
+							Extended Register */
+#define XSDPS_PRE_VAL_1_OFFSET		0x60U	/**< Preset Value Register */
+#define XSDPS_PRE_VAL_2_OFFSET		0x64U	/**< Preset Value Register */
+#define XSDPS_PRE_VAL_3_OFFSET		0x68U	/**< Preset Value Register */
+#define XSDPS_PRE_VAL_4_OFFSET		0x6CU	/**< Preset Value Register */
+#define XSDPS_BOOT_TOUT_CTRL_OFFSET	0x70U	/**< Boot timeout control
+							register */
+
+#define XSDPS_SHARED_BUS_CTRL_OFFSET	0xE0U	/**< Shared Bus Control
+							Register */
+#define XSDPS_SLOT_INTR_STS_OFFSET	0xFCU	/**< Slot Interrupt Status
+							Register */
+#define XSDPS_HOST_CTRL_VER_OFFSET	0xFEU	/**< Host Controller Version
+							Register */
+
+/* @} */
+
+/** @name Control Register - Host control, Power control,
+ * 			Block Gap control and Wakeup control
+ *
+ * This register contains bits for various configuration options of
+ * the SD host controller. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XSDPS_HC_LED_MASK		0x00000001U /**< LED Control */
+#define XSDPS_HC_WIDTH_MASK		0x00000002U /**< Bus width */
+#define XSDPS_HC_BUS_WIDTH_4		0x00000002U
+#define XSDPS_HC_SPEED_MASK		0x00000004U /**< High Speed */
+#define XSDPS_HC_DMA_MASK		0x00000018U /**< DMA Mode Select */
+#define XSDPS_HC_DMA_SDMA_MASK		0x00000000U /**< SDMA Mode */
+#define XSDPS_HC_DMA_ADMA1_MASK		0x00000008U /**< ADMA1 Mode */
+#define XSDPS_HC_DMA_ADMA2_32_MASK	0x00000010U /**< ADMA2 Mode - 32 bit */
+#define XSDPS_HC_DMA_ADMA2_64_MASK	0x00000018U /**< ADMA2 Mode - 64 bit */
+#define XSDPS_HC_EXT_BUS_WIDTH		0x00000020U /**< Bus width - 8 bit */
+#define XSDPS_HC_CARD_DET_TL_MASK	0x00000040U /**< Card Detect Tst Lvl */
+#define XSDPS_HC_CARD_DET_SD_MASK	0x00000080U /**< Card Detect Sig Det */
+
+#define XSDPS_PC_BUS_PWR_MASK		0x00000001U /**< Bus Power Control */
+#define XSDPS_PC_BUS_VSEL_MASK		0x0000000EU /**< Bus Voltage Select */
+#define XSDPS_PC_BUS_VSEL_3V3_MASK	0x0000000EU /**< Bus Voltage 3.3V */
+#define XSDPS_PC_BUS_VSEL_3V0_MASK	0x0000000CU /**< Bus Voltage 3.0V */
+#define XSDPS_PC_BUS_VSEL_1V8_MASK	0x0000000AU /**< Bus Voltage 1.8V */
+#define XSDPS_PC_EMMC_HW_RST_MASK	0x00000010U /**< HW reset for eMMC */
+
+#define XSDPS_BGC_STP_REQ_MASK		0x00000001U /**< Block Gap Stop Req */
+#define XSDPS_BGC_CNT_REQ_MASK		0x00000002U /**< Block Gap Cont Req */
+#define XSDPS_BGC_RWC_MASK		0x00000004U /**< Block Gap Rd Wait */
+#define XSDPS_BGC_INTR_MASK		0x00000008U /**< Block Gap Intr */
+#define XSDPS_BGC_SPI_MODE_MASK		0x00000010U /**< Block Gap SPI Mode */
+#define XSDPS_BGC_BOOT_EN_MASK		0x00000020U /**< Block Gap Boot Enb */
+#define XSDPS_BGC_ALT_BOOT_EN_MASK	0x00000040U /**< Block Gap Alt BootEn */
+#define XSDPS_BGC_BOOT_ACK_MASK		0x00000080U /**< Block Gap Boot Ack */
+
+#define XSDPS_WC_WUP_ON_INTR_MASK	0x00000001U /**< Wakeup Card Intr */
+#define XSDPS_WC_WUP_ON_INSRT_MASK	0x00000002U /**< Wakeup Card Insert */
+#define XSDPS_WC_WUP_ON_REM_MASK	0x00000004U /**< Wakeup Card Removal */
+
+/* @} */
+
+/** @name Control Register - Clock control, Timeout control & Software reset
+ *
+ * This register contains bits for configuration options of clock, timeout and
+ * software reset.
+ * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits.
+ * @{
+ */
+
+#define XSDPS_CC_INT_CLK_EN_MASK		0x00000001U
+#define XSDPS_CC_INT_CLK_STABLE_MASK	0x00000002U
+#define XSDPS_CC_SD_CLK_EN_MASK			0x00000004U
+#define XSDPS_CC_SD_CLK_GEN_SEL_MASK		0x00000020U
+#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK	0x000000C0U
+#define XSDPS_CC_SDCLK_FREQ_SEL_MASK		0x0000FF00U
+#define XSDPS_CC_SDCLK_FREQ_D256_MASK		0x00008000U
+#define XSDPS_CC_SDCLK_FREQ_D128_MASK		0x00004000U
+#define XSDPS_CC_SDCLK_FREQ_D64_MASK		0x00002000U
+#define XSDPS_CC_SDCLK_FREQ_D32_MASK		0x00001000U
+#define XSDPS_CC_SDCLK_FREQ_D16_MASK		0x00000800U
+#define XSDPS_CC_SDCLK_FREQ_D8_MASK		0x00000400U
+#define XSDPS_CC_SDCLK_FREQ_D4_MASK		0x00000200U
+#define XSDPS_CC_SDCLK_FREQ_D2_MASK		0x00000100U
+#define XSDPS_CC_SDCLK_FREQ_BASE_MASK	0x00000000U
+#define XSDPS_CC_MAX_DIV_CNT			256U
+#define XSDPS_CC_EXT_MAX_DIV_CNT		2046U
+#define XSDPS_CC_EXT_DIV_SHIFT			6U
+
+#define XSDPS_TC_CNTR_VAL_MASK			0x0000000FU
+
+#define XSDPS_SWRST_ALL_MASK			0x00000001U
+#define XSDPS_SWRST_CMD_LINE_MASK		0x00000002U
+#define XSDPS_SWRST_DAT_LINE_MASK		0x00000004U
+
+#define XSDPS_CC_MAX_NUM_OF_DIV		9U
+#define XSDPS_CC_DIV_SHIFT		8U
+
+/* @} */
+
+/** @name SD Interrupt Registers
+ *
+ * <b> Normal and Error Interrupt Status Register </b>
+ * This register shows the normal and error interrupt status.
+ * Status enable register affects reads of this register.
+ * If Signal enable register is set and the corresponding status bit is set,
+ * interrupt is generated.
+ * Write to clear except
+ * Error_interrupt and Card_Interrupt bits - Read only
+ *
+ * <b> Normal and Error Interrupt Status Enable Register </b>
+ * Setting this register bits enables Interrupt status.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ * <b> Normal and Error Interrupt Signal Enable Register </b>
+ * This register is used to select which interrupt status is
+ * indicated to the Host System as the interrupt.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ * All three registers have same bit definitions
+ * @{
+ */
+
+#define XSDPS_INTR_CC_MASK		0x00000001U /**< Command Complete */
+#define XSDPS_INTR_TC_MASK		0x00000002U /**< Transfer Complete */
+#define XSDPS_INTR_BGE_MASK		0x00000004U /**< Block Gap Event */
+#define XSDPS_INTR_DMA_MASK		0x00000008U /**< DMA Interrupt */
+#define XSDPS_INTR_BWR_MASK		0x00000010U /**< Buffer Write Ready */
+#define XSDPS_INTR_BRR_MASK		0x00000020U /**< Buffer Read Ready */
+#define XSDPS_INTR_CARD_INSRT_MASK	0x00000040U /**< Card Insert */
+#define XSDPS_INTR_CARD_REM_MASK	0x00000080U /**< Card Remove */
+#define XSDPS_INTR_CARD_MASK		0x00000100U /**< Card Interrupt */
+#define XSDPS_INTR_INT_A_MASK		0x00000200U /**< INT A Interrupt */
+#define XSDPS_INTR_INT_B_MASK		0x00000400U /**< INT B Interrupt */
+#define XSDPS_INTR_INT_C_MASK		0x00000800U /**< INT C Interrupt */
+#define XSDPS_INTR_RE_TUNING_MASK	0x00001000U /**< Re-Tuning Interrupt */
+#define XSDPS_INTR_BOOT_ACK_RECV_MASK	0x00002000U /**< Boot Ack Recv
+							Interrupt */
+#define XSDPS_INTR_BOOT_TERM_MASK	0x00004000U /**< Boot Terminate
+							Interrupt */
+#define XSDPS_INTR_ERR_MASK		0x00008000U /**< Error Interrupt */
+#define XSDPS_NORM_INTR_ALL_MASK	0x0000FFFFU
+
+#define XSDPS_INTR_ERR_CT_MASK		0x00000001U /**< Command Timeout
+							Error */
+#define XSDPS_INTR_ERR_CCRC_MASK	0x00000002U /**< Command CRC Error */
+#define XSDPS_INTR_ERR_CEB_MASK		0x00000004U /**< Command End Bit
+							Error */
+#define XSDPS_INTR_ERR_CI_MASK		0x00000008U /**< Command Index Error */
+#define XSDPS_INTR_ERR_DT_MASK		0x00000010U /**< Data Timeout Error */
+#define XSDPS_INTR_ERR_DCRC_MASK	0x00000020U /**< Data CRC Error */
+#define XSDPS_INTR_ERR_DEB_MASK		0x00000040U /**< Data End Bit Error */
+#define XSDPS_INTR_ERR_CUR_LMT_MASK	0x00000080U /**< Current Limit Error */
+#define XSDPS_INTR_ERR_AUTO_CMD12_MASK	0x00000100U /**< Auto CMD12 Error */
+#define XSDPS_INTR_ERR_ADMA_MASK	0x00000200U /**< ADMA Error */
+#define XSDPS_INTR_ERR_TR_MASK		0x00001000U /**< Tuning Error */
+#define XSDPS_INTR_VEND_SPF_ERR_MASK	0x0000E000U /**< Vendor Specific
+							Error */
+#define XSDPS_ERROR_INTR_ALL_MASK	0x0000F3FFU /**< Mask for error bits */
+/* @} */
+
+/** @name Block Size and Block Count Register
+ *
+ * This register contains the block count for current transfer,
+ * block size and SDMA buffer size.
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_MASK		0x00000FFFU /**< Transfer Block Size */
+#define XSDPS_SDMA_BUFF_SIZE_MASK	0x00007000U /**< Host SDMA Buffer Size */
+#define XSDPS_BLK_SIZE_1024		0x400U
+#define XSDPS_BLK_SIZE_2048		0x800U
+#define XSDPS_BLK_CNT_MASK		0x0000FFFFU /**< Block Count for
+								Current Transfer */
+
+/* @} */
+
+/** @name Transfer Mode and Command Register
+ *
+ * The Transfer Mode register is used to control the data transfers and
+ * Command register is used for command generation
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_TM_DMA_EN_MASK		0x00000001U /**< DMA Enable */
+#define XSDPS_TM_BLK_CNT_EN_MASK	0x00000002U /**< Block Count Enable */
+#define XSDPS_TM_AUTO_CMD12_EN_MASK	0x00000004U /**< Auto CMD12 Enable */
+#define XSDPS_TM_DAT_DIR_SEL_MASK	0x00000010U /**< Data Transfer
+							Direction Select */
+#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK	0x00000020U /**< Multi/Single
+							Block Select */
+
+#define XSDPS_CMD_RESP_SEL_MASK		0x00000003U /**< Response Type
+							Select */
+#define XSDPS_CMD_RESP_NONE_MASK	0x00000000U /**< No Response */
+#define XSDPS_CMD_RESP_L136_MASK	0x00000001U /**< Response length 138 */
+#define XSDPS_CMD_RESP_L48_MASK		0x00000002U /**< Response length 48 */
+#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK	0x00000003U /**< Response length 48 &
+							check busy after
+							response */
+#define XSDPS_CMD_CRC_CHK_EN_MASK	0x00000008U /**< Command CRC Check
+							Enable */
+#define XSDPS_CMD_INX_CHK_EN_MASK	0x00000010U /**< Command Index Check
+							Enable */
+#define XSDPS_DAT_PRESENT_SEL_MASK	0x00000020U /**< Data Present Select */
+#define XSDPS_CMD_TYPE_MASK		0x000000C0U /**< Command Type */
+#define XSDPS_CMD_TYPE_NORM_MASK	0x00000000U /**< CMD Type - Normal */
+#define XSDPS_CMD_TYPE_SUSPEND_MASK	0x00000040U /**< CMD Type - Suspend */
+#define XSDPS_CMD_TYPE_RESUME_MASK	0x00000080U /**< CMD Type - Resume */
+#define XSDPS_CMD_TYPE_ABORT_MASK	0x000000C0U /**< CMD Type - Abort */
+#define XSDPS_CMD_MASK			0x00003F00U /**< Command Index Mask -
+							Set to CMD0-63,
+							AMCD0-63 */
+
+/* @} */
+
+/** @name Auto CMD Error Status Register
+ *
+ * This register is read only register which contains
+ * information about the error status of Auto CMD 12 and 23.
+ * Read Only
+ * @{
+ */
+#define XSDPS_AUTO_CMD12_NT_EX_MASK	0x0001U /**< Auto CMD12 Not
+							executed */
+#define XSDPS_AUTO_CMD_TOUT_MASK	0x0002U /**< Auto CMD Timeout
+							Error */
+#define XSDPS_AUTO_CMD_CRC_MASK		0x0004U /**< Auto CMD CRC Error */
+#define XSDPS_AUTO_CMD_EB_MASK		0x0008U /**< Auto CMD End Bit
+							Error */
+#define XSDPS_AUTO_CMD_IND_MASK		0x0010U /**< Auto CMD Index Error */
+#define XSDPS_AUTO_CMD_CNI_ERR_MASK	0x0080U /**< Command not issued by
+							Auto CMD12 Error */
+/* @} */
+
+/** @name Host Control2 Register
+ *
+ * This register contains extended configuration bits.
+ * Read Write
+ * @{
+ */
+#define XSDPS_HC2_UHS_MODE_MASK		0x0007U /**< UHS Mode select bits */
+#define XSDPS_HC2_UHS_MODE_SDR12_MASK	0x0000U /**< SDR12 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR25_MASK	0x0001U /**< SDR25 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR50_MASK	0x0002U /**< SDR50 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR104_MASK	0x0003U /**< SDR104 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_DDR50_MASK	0x0004U /**< DDR50 UHS Mode */
+#define XSDPS_HC2_1V8_EN_MASK		0x0008U /**< 1.8V Signal Enable */
+#define XSDPS_HC2_DRV_STR_SEL_MASK	0x0030U /**< Driver Strength
+							Selection */
+#define XSDPS_HC2_DRV_STR_B_MASK	0x0000U /**< Driver Strength B */
+#define XSDPS_HC2_DRV_STR_A_MASK	0x0010U /**< Driver Strength A */
+#define XSDPS_HC2_DRV_STR_C_MASK	0x0020U /**< Driver Strength C */
+#define XSDPS_HC2_DRV_STR_D_MASK	0x0030U /**< Driver Strength D */
+#define XSDPS_HC2_EXEC_TNG_MASK		0x0040U /**< Execute Tuning */
+#define XSDPS_HC2_SAMP_CLK_SEL_MASK	0x0080U /**< Sampling Clock
+							Selection */
+#define XSDPS_HC2_ASYNC_INTR_EN_MASK	0x4000U /**< Asynchronous Interrupt
+							Enable */
+#define XSDPS_HC2_PRE_VAL_EN_MASK	0x8000U /**< Preset Value Enable */
+
+/* @} */
+
+/** @name Capabilities Register
+ *
+ * Capabilities register is a read only register which contains
+ * information about the host controller.
+ * Sufficient if read once after power on.
+ * Read Only
+ * @{
+ */
+#define XSDPS_CAP_TOUT_CLK_FREQ_MASK	0x0000003FU /**< Timeout clock freq
+							select */
+#define XSDPS_CAP_TOUT_CLK_UNIT_MASK	0x00000080U /**< Timeout clock unit -
+							MHz/KHz */
+#define XSDPS_CAP_MAX_BLK_LEN_MASK	0x00030000U /**< Max block length */
+#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK	0x00000000U /**< Max block 512 bytes */
+#define XSDPS_CAP_MAX_BL_LN_1024_MASK	0x00010000U /**< Max block 1024 bytes */
+#define XSDPS_CAP_MAX_BL_LN_2048_MASK	0x00020000U /**< Max block 2048 bytes */
+#define XSDPS_CAP_MAX_BL_LN_4096_MASK	0x00030000U /**< Max block 4096 bytes */
+
+#define XSDPS_CAP_EXT_MEDIA_BUS_MASK	0x00040000U /**< Extended media bus */
+#define XSDPS_CAP_ADMA2_MASK		0x00080000U /**< ADMA2 support */
+#define XSDPS_CAP_HIGH_SPEED_MASK	0x00200000U /**< High speed support */
+#define XSDPS_CAP_SDMA_MASK		0x00400000U /**< SDMA support */
+#define XSDPS_CAP_SUSP_RESUME_MASK	0x00800000U /**< Suspend/Resume
+							support */
+#define XSDPS_CAP_VOLT_3V3_MASK		0x01000000U /**< 3.3V support */
+#define XSDPS_CAP_VOLT_3V0_MASK		0x02000000U /**< 3.0V support */
+#define XSDPS_CAP_VOLT_1V8_MASK		0x04000000U /**< 1.8V support */
+
+#define XSDPS_CAP_SYS_BUS_64_MASK	0x10000000U /**< 64 bit system bus
+							support */
+/* Spec 2.0 */
+#define XSDPS_CAP_INTR_MODE_MASK	0x08000000U /**< Interrupt mode
+							support */
+#define XSDPS_CAP_SPI_MODE_MASK		0x20000000U /**< SPI mode */
+#define XSDPS_CAP_SPI_BLOCK_MODE_MASK	0x40000000U /**< SPI block mode */
+
+
+/* Spec 3.0 */
+#define XSDPS_CAPS_ASYNC_INTR_MASK	0x20000000U /**< Async Interrupt
+							support */
+#define XSDPS_CAPS_SLOT_TYPE_MASK	0xC0000000U /**< Slot Type */
+#define XSDPS_CAPS_REM_CARD			0x00000000U /**< Removable Slot */
+#define XSDPS_CAPS_EMB_SLOT			0x40000000U /**< Embedded Slot */
+#define XSDPS_CAPS_SHR_BUS			0x80000000U /**< Shared Bus Slot */
+
+#define XSDPS_ECAPS_SDR50_MASK		0x00000001U /**< SDR50 Mode support */
+#define XSDPS_ECAPS_SDR104_MASK		0x00000002U /**< SDR104 Mode support */
+#define XSDPS_ECAPS_DDR50_MASK		0x00000004U /**< DDR50 Mode support */
+#define XSDPS_ECAPS_DRV_TYPE_A_MASK	0x00000010U /**< DriverType A support */
+#define XSDPS_ECAPS_DRV_TYPE_C_MASK	0x00000020U /**< DriverType C support */
+#define XSDPS_ECAPS_DRV_TYPE_D_MASK	0x00000040U /**< DriverType D support */
+#define XSDPS_ECAPS_TMR_CNT_MASK	0x00000F00U /**< Timer Count for
+							Re-tuning */
+#define XSDPS_ECAPS_USE_TNG_SDR50_MASK	0x00002000U /**< SDR50 Mode needs
+							tuning */
+#define XSDPS_ECAPS_RE_TNG_MODES_MASK	0x0000C000U /**< Re-tuning modes
+							support */
+#define XSDPS_ECAPS_RE_TNG_MODE1_MASK	0x00000000U /**< Re-tuning mode 1 */
+#define XSDPS_ECAPS_RE_TNG_MODE2_MASK	0x00004000U /**< Re-tuning mode 2 */
+#define XSDPS_ECAPS_RE_TNG_MODE3_MASK	0x00008000U /**< Re-tuning mode 3 */
+#define XSDPS_ECAPS_CLK_MULT_MASK	0x00FF0000U /**< Clock Multiplier value
+							for Programmable clock
+							mode */
+#define XSDPS_ECAPS_SPI_MODE_MASK	0x01000000U /**< SPI mode */
+#define XSDPS_ECAPS_SPI_BLK_MODE_MASK	0x02000000U /**< SPI block mode */
+
+/* @} */
+
+/** @name Present State Register
+ *
+ * Gives the current status of the host controller
+ * Read Only
+ * @{
+ */
+
+#define XSDPS_PSR_INHIBIT_CMD_MASK	0x00000001U /**< Command inhibit - CMD */
+#define XSDPS_PSR_INHIBIT_DAT_MASK	0x00000002U /**< Command Inhibit - DAT */
+#define XSDPS_PSR_DAT_ACTIVE_MASK	0x00000004U /**< DAT line active */
+#define XSDPS_PSR_RE_TUNING_REQ_MASK	0x00000008U /**< Re-tuning request */
+#define XSDPS_PSR_WR_ACTIVE_MASK	0x00000100U /**< Write transfer active */
+#define XSDPS_PSR_RD_ACTIVE_MASK	0x00000200U /**< Read transfer active */
+#define XSDPS_PSR_BUFF_WR_EN_MASK	0x00000400U /**< Buffer write enable */
+#define XSDPS_PSR_BUFF_RD_EN_MASK	0x00000800U /**< Buffer read enable */
+#define XSDPS_PSR_CARD_INSRT_MASK	0x00010000U /**< Card inserted */
+#define XSDPS_PSR_CARD_STABLE_MASK	0x00020000U /**< Card state stable */
+#define XSDPS_PSR_CARD_DPL_MASK		0x00040000U /**< Card detect pin level */
+#define XSDPS_PSR_WPS_PL_MASK		0x00080000U /**< Write protect switch
+								pin level */
+#define XSDPS_PSR_DAT30_SG_LVL_MASK	0x00F00000U /**< Data 3:0 signal lvl */
+#define XSDPS_PSR_CMD_SG_LVL_MASK	0x01000000U /**< Cmd Line signal lvl */
+#define XSDPS_PSR_DAT74_SG_LVL_MASK	0x1E000000U /**< Data 7:4 signal lvl */
+
+/* @} */
+
+/** @name Maximum Current Capablities Register
+ *
+ * This register is read only register which contains
+ * information about current capabilities at each voltage levels.
+ * Read Only
+ * @{
+ */
+#define XSDPS_MAX_CUR_CAPS_1V8_MASK	0x00000F00U /**< Maximum Current
+							Capability at 1.8V */
+#define XSDPS_MAX_CUR_CAPS_3V0_MASK	0x000000F0U /**< Maximum Current
+							Capability at 3.0V */
+#define XSDPS_MAX_CUR_CAPS_3V3_MASK	0x0000000FU /**< Maximum Current
+							Capability at 3.3V */
+/* @} */
+
+
+/** @name Force Event for Auto CMD Error Status Register
+ *
+ * This register is write only register which contains
+ * control bits to generate events for Auto CMD error status.
+ * Write Only
+ * @{
+ */
+#define XSDPS_FE_AUTO_CMD12_NT_EX_MASK	0x0001U /**< Auto CMD12 Not
+							executed */
+#define XSDPS_FE_AUTO_CMD_TOUT_MASK	0x0002U /**< Auto CMD Timeout
+							Error */
+#define XSDPS_FE_AUTO_CMD_CRC_MASK	0x0004U /**< Auto CMD CRC Error */
+#define XSDPS_FE_AUTO_CMD_EB_MASK	0x0008U /**< Auto CMD End Bit
+							Error */
+#define XSDPS_FE_AUTO_CMD_IND_MASK	0x0010U /**< Auto CMD Index Error */
+#define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK	0x0080U /**< Command not issued by
+							Auto CMD12 Error */
+/* @} */
+
+
+
+/** @name Force Event for Error Interrupt Status Register
+ *
+ * This register is write only register which contains
+ * control bits to generate events of error interrupt status register.
+ * Write Only
+ * @{
+ */
+#define XSDPS_FE_INTR_ERR_CT_MASK	0x0001U /**< Command Timeout
+							Error */
+#define XSDPS_FE_INTR_ERR_CCRC_MASK	0x0002U /**< Command CRC Error */
+#define XSDPS_FE_INTR_ERR_CEB_MASK	0x0004U /**< Command End Bit
+							Error */
+#define XSDPS_FE_INTR_ERR_CI_MASK	0x0008U /**< Command Index Error */
+#define XSDPS_FE_INTR_ERR_DT_MASK	0x0010U /**< Data Timeout Error */
+#define XSDPS_FE_INTR_ERR_DCRC_MASK	0x0020U /**< Data CRC Error */
+#define XSDPS_FE_INTR_ERR_DEB_MASK	0x0040U /**< Data End Bit Error */
+#define XSDPS_FE_INTR_ERR_CUR_LMT_MASK	0x0080U /**< Current Limit Error */
+#define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK	0x0100U /**< Auto CMD Error */
+#define XSDPS_FE_INTR_ERR_ADMA_MASK	0x0200U /**< ADMA Error */
+#define XSDPS_FE_INTR_ERR_TR_MASK	0x1000U /**< Target Reponse */
+#define XSDPS_FE_INTR_VEND_SPF_ERR_MASK	0xE000U /**< Vendor Specific
+							Error */
+
+/* @} */
+
+/** @name ADMA Error Status Register
+ *
+ * This register is read only register which contains
+ * status information about ADMA errors.
+ * Read Only
+ * @{
+ */
+#define XSDPS_ADMA_ERR_MM_LEN_MASK	0x04U /**< ADMA Length Mismatch
+							Error */
+#define XSDPS_ADMA_ERR_STATE_MASK	0x03U /**< ADMA Error State */
+#define XSDPS_ADMA_ERR_STATE_STOP_MASK	0x00U /**< ADMA Error State
+							STOP */
+#define XSDPS_ADMA_ERR_STATE_FDS_MASK	0x01U /**< ADMA Error State
+							FDS */
+#define XSDPS_ADMA_ERR_STATE_TFR_MASK	0x03U /**< ADMA Error State
+							TFR */
+/* @} */
+
+/** @name Preset Values Register
+ *
+ * This register is read only register which contains
+ * preset values for each of speed modes.
+ * Read Only
+ * @{
+ */
+#define XSDPS_PRE_VAL_SDCLK_FSEL_MASK	0x03FFU /**< SDCLK Frequency
+							Select Value */
+#define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK	0x0400U /**< Clock Generator
+							Mode Select */
+#define XSDPS_PRE_VAL_DRV_STR_SEL_MASK	0xC000U /**< Driver Strength
+							Select Value */
+
+/* @} */
+
+/** @name Slot Interrupt Status Register
+ *
+ * This register is read only register which contains
+ * interrupt slot signal for each slot.
+ * Read Only
+ * @{
+ */
+#define XSDPS_SLOT_INTR_STS_INT_MASK	0x0007U /**< Interrupt Signal
+							mask */
+
+/* @} */
+
+/** @name Host Controller Version Register
+ *
+ * This register is read only register which contains
+ * Host Controller and Vendor Specific version.
+ * Read Only
+ * @{
+ */
+#define XSDPS_HC_VENDOR_VER		0xFF00U /**< Vendor
+							Specification
+							version mask */
+#define XSDPS_HC_SPEC_VER_MASK		0x00FFU /**< Host
+							Specification
+							version mask */
+#define XSDPS_HC_SPEC_V3		0x0002U
+#define XSDPS_HC_SPEC_V2		0x0001U
+#define XSDPS_HC_SPEC_V1		0x0000U
+
+/** @name Block size mask for 512 bytes
+ *
+ * Block size mask for 512 bytes - This is the default block size.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_512_MASK	0x200U
+
+/* @} */
+
+/** @name Commands
+ *
+ * Constant definitions for commands and response related to SD
+ * @{
+ */
+
+#define XSDPS_APP_CMD_PREFIX	 0x8000U
+#define CMD0	 0x0000U
+#define CMD1	 0x0100U
+#define CMD2	 0x0200U
+#define CMD3	 0x0300U
+#define CMD4	 0x0400U
+#define CMD5	 0x0500U
+#define CMD6	 0x0600U
+#define ACMD6	(XSDPS_APP_CMD_PREFIX + 0x0600U)
+#define CMD7	 0x0700U
+#define CMD8	 0x0800U
+#define CMD9	 0x0900U
+#define CMD10	 0x0A00U
+#define CMD11	 0x0B00U
+#define CMD12	 0x0C00U
+#define ACMD13	 (XSDPS_APP_CMD_PREFIX + 0x0D00U)
+#define CMD16	 0x1000U
+#define CMD17	 0x1100U
+#define CMD18	 0x1200U
+#define CMD19	 0x1300U
+#define CMD21	 0x1500U
+#define CMD23	 0x1700U
+#define ACMD23	 (XSDPS_APP_CMD_PREFIX + 0x1700U)
+#define CMD24	 0x1800U
+#define CMD25	 0x1900U
+#define CMD41	 0x2900U
+#define ACMD41	 (XSDPS_APP_CMD_PREFIX + 0x2900U)
+#define ACMD42	 (XSDPS_APP_CMD_PREFIX + 0x2A00U)
+#define ACMD51	 (XSDPS_APP_CMD_PREFIX + 0x3300U)
+#define CMD52	 0x3400U
+#define CMD55	 0x3700U
+#define CMD58	 0x3A00U
+
+#define RESP_NONE	(u32)XSDPS_CMD_RESP_NONE_MASK
+#define RESP_R1		(u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \
+			(u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R1B	(u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+			(u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R2		(u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK
+#define RESP_R3		(u32)XSDPS_CMD_RESP_L48_MASK
+
+#define RESP_R6		(u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+			(u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+/* @} */
+
+/* Card Interface Conditions Definitions */
+#define XSDPS_CIC_CHK_PATTERN	0xAAU
+#define XSDPS_CIC_VOLT_MASK	(0xFU<<8)
+#define XSDPS_CIC_VOLT_2V7_3V6	(1U<<8)
+#define XSDPS_CIC_VOLT_LOW	(1U<<9)
+
+/* Operation Conditions Register Definitions */
+#define XSDPS_OCR_PWRUP_STS	(1U<<31)
+#define XSDPS_OCR_CC_STS	(1U<<30)
+#define XSDPS_OCR_S18		(1U<<24)
+#define XSDPS_OCR_3V5_3V6	(1U<<23)
+#define XSDPS_OCR_3V4_3V5	(1U<<22)
+#define XSDPS_OCR_3V3_3V4	(1U<<21)
+#define XSDPS_OCR_3V2_3V3	(1U<<20)
+#define XSDPS_OCR_3V1_3V2	(1U<<19)
+#define XSDPS_OCR_3V0_3V1	(1U<<18)
+#define XSDPS_OCR_2V9_3V0	(1U<<17)
+#define XSDPS_OCR_2V8_2V9	(1U<<16)
+#define XSDPS_OCR_2V7_2V8	(1U<<15)
+#define XSDPS_OCR_1V7_1V95	(1U<<7)
+#define XSDPS_OCR_HIGH_VOL	0x00FF8000U
+#define XSDPS_OCR_LOW_VOL	0x00000080U
+
+/* SD Card Configuration Register Definitions */
+#define XSDPS_SCR_REG_LEN		8U
+#define XSDPS_SCR_STRUCT_MASK		(0xFU<<28)
+#define XSDPS_SCR_SPEC_MASK		(0xFU<<24)
+#define XSDPS_SCR_SPEC_1V0		0U
+#define XSDPS_SCR_SPEC_1V1		(1U<<24)
+#define XSDPS_SCR_SPEC_2V0_3V0		(2U<<24)
+#define XSDPS_SCR_MEM_VAL_AF_ERASE	(1U<<23)
+#define XSDPS_SCR_SEC_SUPP_MASK		(7U<<20)
+#define XSDPS_SCR_SEC_SUPP_NONE		0U
+#define XSDPS_SCR_SEC_SUPP_1V1		(2U<<20)
+#define XSDPS_SCR_SEC_SUPP_2V0		(3U<<20)
+#define XSDPS_SCR_SEC_SUPP_3V0		(4U<<20)
+#define XSDPS_SCR_BUS_WIDTH_MASK	(0xFU<<16)
+#define XSDPS_SCR_BUS_WIDTH_1		(1U<<16)
+#define XSDPS_SCR_BUS_WIDTH_4		(4U<<16)
+#define XSDPS_SCR_SPEC3_MASK		(1U<<12)
+#define XSDPS_SCR_SPEC3_2V0		0U
+#define XSDPS_SCR_SPEC3_3V0		(1U<<12)
+#define XSDPS_SCR_CMD_SUPP_MASK		0x3U
+#define XSDPS_SCR_CMD23_SUPP		(1U<<1)
+#define XSDPS_SCR_CMD20_SUPP		(1U<<0)
+
+/* Card Status Register Definitions */
+#define XSDPS_CD_STS_OUT_OF_RANGE	(1U<<31)
+#define XSDPS_CD_STS_ADDR_ERR		(1U<<30)
+#define XSDPS_CD_STS_BLK_LEN_ERR	(1U<<29)
+#define XSDPS_CD_STS_ER_SEQ_ERR		(1U<<28)
+#define XSDPS_CD_STS_ER_PRM_ERR		(1U<<27)
+#define XSDPS_CD_STS_WP_VIO		(1U<<26)
+#define XSDPS_CD_STS_IS_LOCKED		(1U<<25)
+#define XSDPS_CD_STS_LOCK_UNLOCK_FAIL	(1U<<24)
+#define XSDPS_CD_STS_CMD_CRC_ERR	(1U<<23)
+#define XSDPS_CD_STS_ILGL_CMD		(1U<<22)
+#define XSDPS_CD_STS_CARD_ECC_FAIL	(1U<<21)
+#define XSDPS_CD_STS_CC_ERR		(1U<<20)
+#define XSDPS_CD_STS_ERR		(1U<<19)
+#define XSDPS_CD_STS_CSD_OVRWR		(1U<<16)
+#define XSDPS_CD_STS_WP_ER_SKIP		(1U<<15)
+#define XSDPS_CD_STS_CARD_ECC_DIS	(1U<<14)
+#define XSDPS_CD_STS_ER_RST		(1U<<13)
+#define XSDPS_CD_STS_CUR_STATE		(0xFU<<9)
+#define XSDPS_CD_STS_RDY_FOR_DATA	(1U<<8)
+#define XSDPS_CD_STS_APP_CMD		(1U<<5)
+#define XSDPS_CD_STS_AKE_SEQ_ERR	(1U<<2)
+
+/* Switch Function Definitions CMD6 */
+#define XSDPS_SWITCH_SD_RESP_LEN	64U
+
+#define XSDPS_SWITCH_FUNC_SWITCH	(1U<<31)
+#define XSDPS_SWITCH_FUNC_CHECK		0U
+
+#define XSDPS_MODE_FUNC_GRP1		1U
+#define XSDPS_MODE_FUNC_GRP2		2U
+#define XSDPS_MODE_FUNC_GRP3		3U
+#define XSDPS_MODE_FUNC_GRP4		4U
+#define XSDPS_MODE_FUNC_GRP5		5U
+#define XSDPS_MODE_FUNC_GRP6		6U
+
+#define XSDPS_FUNC_GRP_DEF_VAL		0xFU
+#define XSDPS_FUNC_ALL_GRP_DEF_VAL	0xFFFFFFU
+
+#define XSDPS_ACC_MODE_DEF_SDR12	0U
+#define XSDPS_ACC_MODE_HS_SDR25		1U
+#define XSDPS_ACC_MODE_SDR50		2U
+#define XSDPS_ACC_MODE_SDR104		3U
+#define XSDPS_ACC_MODE_DDR50		4U
+
+#define XSDPS_CMD_SYS_ARG_SHIFT		4U
+#define XSDPS_CMD_SYS_DEF		0U
+#define XSDPS_CMD_SYS_eC		1U
+#define XSDPS_CMD_SYS_OTP		3U
+#define XSDPS_CMD_SYS_ASSD		4U
+#define XSDPS_CMD_SYS_VEND		5U
+
+#define XSDPS_DRV_TYPE_ARG_SHIFT	8U
+#define XSDPS_DRV_TYPE_B		0U
+#define XSDPS_DRV_TYPE_A		1U
+#define XSDPS_DRV_TYPE_C		2U
+#define XSDPS_DRV_TYPE_D		3U
+
+#define XSDPS_CUR_LIM_ARG_SHIFT		12U
+#define XSDPS_CUR_LIM_200		0U
+#define XSDPS_CUR_LIM_400		1U
+#define XSDPS_CUR_LIM_600		2U
+#define XSDPS_CUR_LIM_800		3U
+
+#define CSD_SPEC_VER_MASK		0x3C0000U
+#define READ_BLK_LEN_MASK		0x00000F00U
+#define C_SIZE_MULT_MASK		0x00000380U
+#define C_SIZE_LOWER_MASK		0xFFC00000U
+#define C_SIZE_UPPER_MASK		0x00000003U
+#define CSD_STRUCT_MASK			0x00C00000U
+#define CSD_V2_C_SIZE_MASK		0x3FFFFF00U
+
+/* EXT_CSD field definitions */
+#define XSDPS_EXT_CSD_SIZE		512U
+
+#define EXT_CSD_WR_REL_PARAM_EN		(1U<<2)
+
+#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS    (0x40U)
+#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS   (0x10U)
+#define EXT_CSD_BOOT_WP_B_PERM_WP_EN    (0x04U)
+#define EXT_CSD_BOOT_WP_B_PWR_WP_EN     (0x01U)
+
+#define EXT_CSD_PART_CONFIG_ACC_MASK    (0x7U)
+#define EXT_CSD_PART_CONFIG_ACC_BOOT0   (0x1U)
+#define EXT_CSD_PART_CONFIG_ACC_RPMB    (0x3U)
+#define EXT_CSD_PART_CONFIG_ACC_GP0     (0x4U)
+
+#define EXT_CSD_PART_SUPPORT_PART_EN    (0x1U)
+
+#define EXT_CSD_CMD_SET_NORMAL          (1U<<0)
+#define EXT_CSD_CMD_SET_SECURE          (1U<<1)
+#define EXT_CSD_CMD_SET_CPSECURE        (1U<<2)
+
+#define EXT_CSD_CARD_TYPE_26    	(1U<<0)  /* Card can run at 26MHz */
+#define EXT_CSD_CARD_TYPE_52    	(1U<<1)  /* Card can run at 52MHz */
+#define EXT_CSD_CARD_TYPE_MASK  	0x3FU    /* Mask out reserved bits */
+#define EXT_CSD_CARD_TYPE_DDR_1_8V	(1U<<2)   /* Card can run at 52MHz */
+                                             /* DDR mode @1.8V or 3V I/O */
+#define EXT_CSD_CARD_TYPE_DDR_1_2V	(1U<<3)   /* Card can run at 52MHz */
+                                             /* DDR mode @1.2V I/O */
+#define EXT_CSD_CARD_TYPE_DDR_52	(EXT_CSD_CARD_TYPE_DDR_1_8V  \
+                                        | EXT_CSD_CARD_TYPE_DDR_1_2V)
+#define EXT_CSD_CARD_TYPE_SDR_1_8V      (1U<<4)  /* Card can run at 200MHz */
+#define EXT_CSD_CARD_TYPE_SDR_1_2V      (1U<<5)  /* Card can run at 200MHz */
+                                                /* SDR mode @1.2V I/O */
+#define EXT_CSD_BUS_WIDTH_BYTE			183U
+#define EXT_CSD_BUS_WIDTH_1_BIT			0U	/* Card is in 1 bit mode */
+#define EXT_CSD_BUS_WIDTH_4_BIT			1U	/* Card is in 4 bit mode */
+#define EXT_CSD_BUS_WIDTH_8_BIT			2U	/* Card is in 8 bit mode */
+#define EXT_CSD_BUS_WIDTH_DDR_4_BIT		5U	/* Card is in 4 bit DDR mode */
+#define EXT_CSD_BUS_WIDTH_DDR_8_BIT		6U	/* Card is in 8 bit DDR mode */
+
+#define EXT_CSD_HS_TIMING_BYTE		185U
+#define EXT_CSD_HS_TIMING_DEF		0U
+#define EXT_CSD_HS_TIMING_HIGH		1U	/* Card is in high speed mode */
+#define EXT_CSD_HS_TIMING_HS200		2U	/* Card is in HS200 mode */
+
+#define EXT_CSD_RST_N_FUN_BYTE		162U
+#define EXT_CSD_RST_N_FUN_TEMP_DIS	0U	/* RST_n signal is temporarily disabled */
+#define EXT_CSD_RST_N_FUN_PERM_EN	1U	/* RST_n signal is permanently enabled */
+#define EXT_CSD_RST_N_FUN_PERM_DIS	2U	/* RST_n signal is permanently disabled */
+
+#define XSDPS_EXT_CSD_CMD_SET		0U
+#define XSDPS_EXT_CSD_SET_BITS		1U
+#define XSDPS_EXT_CSD_CLR_BITS		2U
+#define XSDPS_EXT_CSD_WRITE_BYTE	3U
+
+#define XSDPS_MMC_DEF_SPEED_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					| ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+					| ((u32)EXT_CSD_HS_TIMING_DEF << 8))
+
+#define XSDPS_MMC_HIGH_SPEED_ARG	(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+					 | ((u32)EXT_CSD_HS_TIMING_HIGH << 8))
+
+#define XSDPS_MMC_HS200_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+					 | ((u32)EXT_CSD_HS_TIMING_HS200 << 8))
+
+#define XSDPS_MMC_1_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WITH_1_BIT << 8))
+
+#define XSDPS_MMC_4_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8))
+
+#define XSDPS_MMC_8_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8))
+
+#define XSDPS_MMC_DDR_4_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8))
+
+#define XSDPS_MMC_DDR_8_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8))
+
+#define XSDPS_MMC_RST_FUN_EN_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \
+					 | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8))
+
+#define XSDPS_MMC_DELAY_FOR_SWITCH	1000U
+
+/* @} */
+
+/* @400KHz, in usec */
+#define XSDPS_74CLK_DELAY	2960U
+#define XSDPS_100CLK_DELAY	4000U
+#define XSDPS_INIT_DELAY	10000U
+
+#define XSDPS_DEF_VOLT_LVL	XSDPS_PC_BUS_VSEL_3V0_MASK
+#define XSDPS_CARD_DEF_ADDR	0x1234U
+
+#define XSDPS_CARD_SD		1U
+#define XSDPS_CARD_MMC		2U
+#define XSDPS_CARD_SDIO		3U
+#define XSDPS_CARD_SDCOMBO	4U
+#define XSDPS_CHIP_EMMC		5U
+
+
+/** @name ADMA2 Descriptor related definitions
+ *
+ * ADMA2 Descriptor related definitions
+ * @{
+ */
+
+#define XSDPS_DESC_MAX_LENGTH 65536U
+
+#define XSDPS_DESC_VALID     	(0x1U << 0)
+#define XSDPS_DESC_END       	(0x1U << 1)
+#define XSDPS_DESC_INT       	(0x1U << 2)
+#define XSDPS_DESC_TRAN  	(0x2U << 4)
+
+/* @} */
+
+/* For changing clock frequencies */
+#define XSDPS_CLK_400_KHZ		400000U		/**< 400 KHZ */
+#define XSDPS_CLK_50_MHZ		50000000U	/**< 50 MHZ */
+#define XSDPS_CLK_52_MHZ		52000000U	/**< 52 MHZ */
+#define XSDPS_SD_VER_1_0		0x1U		/**< SD ver 1 */
+#define XSDPS_SD_VER_2_0		0x2U		/**< SD ver 2 */
+#define XSDPS_SCR_BLKCNT	1U
+#define XSDPS_SCR_BLKSIZE	8U
+#define XSDPS_1_BIT_WIDTH	0x1U
+#define XSDPS_4_BIT_WIDTH	0x2U
+#define XSDPS_8_BIT_WIDTH	0x3U
+#define XSDPS_UHS_SPEED_MODE_SDR12	0x0U
+#define XSDPS_UHS_SPEED_MODE_SDR25	0x1U
+#define XSDPS_UHS_SPEED_MODE_SDR50	0x2U
+#define XSDPS_UHS_SPEED_MODE_SDR104	0x3U
+#define XSDPS_UHS_SPEED_MODE_DDR50	0x4U
+#define XSDPS_HIGH_SPEED_MODE		0x5U
+#define XSDPS_DEFAULT_SPEED_MODE	0x6U
+#define XSDPS_HS200_MODE			0x7U
+#define XSDPS_DDR52_MODE			0x4U
+#define XSDPS_SWITCH_CMD_BLKCNT		1U
+#define XSDPS_SWITCH_CMD_BLKSIZE	64U
+#define XSDPS_SWITCH_CMD_HS_GET		0x00FFFFF0U
+#define XSDPS_SWITCH_CMD_HS_SET		0x80FFFFF1U
+#define XSDPS_SWITCH_CMD_SDR12_SET		0x80FFFFF0U
+#define XSDPS_SWITCH_CMD_SDR25_SET		0x80FFFFF1U
+#define XSDPS_SWITCH_CMD_SDR50_SET		0x80FFFFF2U
+#define XSDPS_SWITCH_CMD_SDR104_SET		0x80FFFFF3U
+#define XSDPS_SWITCH_CMD_DDR50_SET		0x80FFFFF4U
+#define XSDPS_EXT_CSD_CMD_BLKCNT	1U
+#define XSDPS_EXT_CSD_CMD_BLKSIZE	512U
+#define XSDPS_TUNING_CMD_BLKCNT		1U
+#define XSDPS_TUNING_CMD_BLKSIZE	64U
+
+#define XSDPS_HIGH_SPEED_MAX_CLK	50000000U
+#define XSDPS_UHS_SDR104_MAX_CLK	208000000U
+#define XSDPS_UHS_SDR50_MAX_CLK		100000000U
+#define XSDPS_UHS_DDR50_MAX_CLK		50000000U
+#define XSDPS_UHS_SDR25_MAX_CLK		50000000U
+#define XSDPS_UHS_SDR12_MAX_CLK		25000000U
+
+#define SD_DRIVER_TYPE_B	0x01U
+#define SD_DRIVER_TYPE_A	0x02U
+#define SD_DRIVER_TYPE_C	0x04U
+#define SD_DRIVER_TYPE_D	0x08U
+#define SD_SET_CURRENT_LIMIT_200	0U
+#define SD_SET_CURRENT_LIMIT_400	1U
+#define SD_SET_CURRENT_LIMIT_600	2U
+#define SD_SET_CURRENT_LIMIT_800	3U
+
+#define SD_MAX_CURRENT_200	(1U << SD_SET_CURRENT_LIMIT_200)
+#define SD_MAX_CURRENT_400	(1U << SD_SET_CURRENT_LIMIT_400)
+#define SD_MAX_CURRENT_600	(1U << SD_SET_CURRENT_LIMIT_600)
+#define SD_MAX_CURRENT_800	(1U << SD_SET_CURRENT_LIMIT_800)
+
+#define XSDPS_SD_SDR12_MAX_CLK	25000000U
+#define XSDPS_SD_SDR25_MAX_CLK	50000000U
+#define XSDPS_SD_SDR50_MAX_CLK	100000000U
+#define XSDPS_SD_DDR50_MAX_CLK	50000000U
+#define XSDPS_SD_SDR104_MAX_CLK	208000000U
+#define XSDPS_MMC_HS200_MAX_CLK	200000000U
+#define XSDPS_MMC_HSD_MAX_CLK	52000000U
+#define XSDPS_MMC_DDR_MAX_CLK	52000000U
+
+#define XSDPS_CARD_STATE_IDLE		0U
+#define XSDPS_CARD_STATE_RDY		1U
+#define XSDPS_CARD_STATE_IDEN		2U
+#define XSDPS_CARD_STATE_STBY		3U
+#define XSDPS_CARD_STATE_TRAN		4U
+#define XSDPS_CARD_STATE_DATA		5U
+#define XSDPS_CARD_STATE_RCV		6U
+#define XSDPS_CARD_STATE_PROG		7U
+#define XSDPS_CARD_STATE_DIS		8U
+#define XSDPS_CARD_STATE_BTST		9U
+#define XSDPS_CARD_STATE_SLP		10U
+
+#define XSDPS_SLOT_REM			0U
+#define XSDPS_SLOT_EMB			1U
+
+#define XSDPS_WIDTH_8		8U
+#define XSDPS_WIDTH_4		4U
+
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+#define SD0_ITAPDLY_SEL_MASK		0x000000FFU
+#define SD0_OTAPDLY_SEL_MASK		0x0000003FU
+#define SD1_ITAPDLY_SEL_MASK		0x00FF0000U
+#define SD1_OTAPDLY_SEL_MASK		0x003F0000U
+#define SD_DLL_CTRL 				0x00000358U
+#define SD_ITAPDLY					0x00000314U
+#define SD_OTAPDLY					0x00000318U
+#define SD0_DLL_RST					0x00000004U
+#define SD1_DLL_RST					0x00040000U
+#define SD0_ITAPCHGWIN				0x00000200U
+#define SD0_ITAPDLYENA				0x00000100U
+#define SD0_OTAPDLYENA				0x00000040U
+#define SD1_ITAPCHGWIN				0x02000000U
+#define SD1_ITAPDLYENA				0x01000000U
+#define SD1_OTAPDLYENA				0x00400000U
+
+#define SD0_OTAPDLYSEL_HS200_B0		0x00000003U
+#define SD0_OTAPDLYSEL_HS200_B2		0x00000002U
+#define SD0_ITAPDLYSEL_SD50			0x00000014U
+#define SD0_OTAPDLYSEL_SD50			0x00000003U
+#define SD0_ITAPDLYSEL_SD_DDR50		0x0000003DU
+#define SD0_ITAPDLYSEL_EMMC_DDR50	0x00000012U
+#define SD0_OTAPDLYSEL_SD_DDR50		0x00000004U
+#define SD0_OTAPDLYSEL_EMMC_DDR50	0x00000006U
+#define SD0_ITAPDLYSEL_HSD			0x00000015U
+#define SD0_OTAPDLYSEL_SD_HSD		0x00000005U
+#define SD0_OTAPDLYSEL_EMMC_HSD		0x00000006U
+
+#define SD1_OTAPDLYSEL_HS200_B0		0x00030000U
+#define SD1_OTAPDLYSEL_HS200_B2		0x00020000U
+#define SD1_ITAPDLYSEL_SD50			0x00140000U
+#define SD1_OTAPDLYSEL_SD50			0x00030000U
+#define SD1_ITAPDLYSEL_SD_DDR50		0x003D0000U
+#define SD1_ITAPDLYSEL_EMMC_DDR50	0x00120000U
+#define SD1_OTAPDLYSEL_SD_DDR50		0x00040000U
+#define SD1_OTAPDLYSEL_EMMC_DDR50	0x00060000U
+#define SD1_ITAPDLYSEL_HSD			0x00150000U
+#define SD1_OTAPDLYSEL_SD_HSD		0x00050000U
+#define SD1_OTAPDLYSEL_EMMC_HSD		0x00060000U
+
+#endif
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define XSdPs_In64 Xil_In64
+#define XSdPs_Out64 Xil_Out64
+
+#define XSdPs_In32 Xil_In32
+#define XSdPs_Out32 Xil_Out32
+
+#define XSdPs_In16 Xil_In16
+#define XSdPs_Out16 Xil_Out16
+
+#define XSdPs_In8 Xil_In8
+#define XSdPs_Out8 Xil_Out8
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg64(InstancePtr, RegOffset) \
+	XSdPs_In64((InstancePtr->Config.BaseAddress) + RegOffset)
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset,
+*		u64 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \
+	XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \
+		(RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg(BaseAddress, RegOffset) \
+	XSdPs_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u32 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+	XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg16(BaseAddress, RegOffset) \
+	XSdPs_In16((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u16 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg16(BaseAddress, RegOffset, RegisterValue) \
+	XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg8(BaseAddress, RegOffset) \
+	XSdPs_In8((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u8 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg8(BaseAddress, RegOffset, RegisterValue) \
+	XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue))
+
+/***************************************************************************/
+/**
+* Macro to get present status register
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u8 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_GetPresentStatusReg(BaseAddress) \
+		XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_HW_H_ */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xstatus.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xstatus.h
new file mode 100644
index 0000000000000000000000000000000000000000..993747588d94aa9364dfacd1f14cd5970331d66a
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xstatus.h
@@ -0,0 +1,535 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xstatus.h
+*
+* @addtogroup common_status_codes Xilinx&reg; software status codes
+*
+* The xstatus.h file contains the Xilinx&reg; software status codes.These codes are
+* used throughout the Xilinx device drivers.
+*
+* @{
+******************************************************************************/
+
+#ifndef XSTATUS_H		/* prevent circular inclusions */
+#define XSTATUS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/*********************** Common statuses 0 - 500 *****************************/
+/**
+@name Common Status Codes for All Device Drivers
+@{
+*/
+#define XST_SUCCESS                     0L
+#define XST_FAILURE                     1L
+#define XST_DEVICE_NOT_FOUND            2L
+#define XST_DEVICE_BLOCK_NOT_FOUND      3L
+#define XST_INVALID_VERSION             4L
+#define XST_DEVICE_IS_STARTED           5L
+#define XST_DEVICE_IS_STOPPED           6L
+#define XST_FIFO_ERROR                  7L	/*!< An error occurred during an
+						   operation with a FIFO such as
+						   an underrun or overrun, this
+						   error requires the device to
+						   be reset */
+#define XST_RESET_ERROR                 8L	/*!< An error occurred which requires
+						   the device to be reset */
+#define XST_DMA_ERROR                   9L	/*!< A DMA error occurred, this error
+						   typically requires the device
+						   using the DMA to be reset */
+#define XST_NOT_POLLED                  10L	/*!< The device is not configured for
+						   polled mode operation */
+#define XST_FIFO_NO_ROOM                11L	/*!< A FIFO did not have room to put
+						   the specified data into */
+#define XST_BUFFER_TOO_SMALL            12L	/*!< The buffer is not large enough
+						   to hold the expected data */
+#define XST_NO_DATA                     13L	/*!< There was no data available */
+#define XST_REGISTER_ERROR              14L	/*!< A register did not contain the
+						   expected value */
+#define XST_INVALID_PARAM               15L	/*!< An invalid parameter was passed
+						   into the function */
+#define XST_NOT_SGDMA                   16L	/*!< The device is not configured for
+						   scatter-gather DMA operation */
+#define XST_LOOPBACK_ERROR              17L	/*!< A loopback test failed */
+#define XST_NO_CALLBACK                 18L	/*!< A callback has not yet been
+						   registered */
+#define XST_NO_FEATURE                  19L	/*!< Device is not configured with
+						   the requested feature */
+#define XST_NOT_INTERRUPT               20L	/*!< Device is not configured for
+						   interrupt mode operation */
+#define XST_DEVICE_BUSY                 21L	/*!< Device is busy */
+#define XST_ERROR_COUNT_MAX             22L	/*!< The error counters of a device
+						   have maxed out */
+#define XST_IS_STARTED                  23L	/*!< Used when part of device is
+						   already started i.e.
+						   sub channel */
+#define XST_IS_STOPPED                  24L	/*!< Used when part of device is
+						   already stopped i.e.
+						   sub channel */
+#define XST_DATA_LOST                   26L	/*!< Driver defined error */
+#define XST_RECV_ERROR                  27L	/*!< Generic receive error */
+#define XST_SEND_ERROR                  28L	/*!< Generic transmit error */
+#define XST_NOT_ENABLED                 29L	/*!< A requested service is not
+						   available because it has not
+						   been enabled */
+/** @} */
+/***************** Utility Component statuses 401 - 500  *********************/
+/**
+@name Utility Component Status Codes 401 - 500
+@{
+*/
+#define XST_MEMTEST_FAILED              401L	/*!< Memory test failed */
+
+/** @} */
+/***************** Common Components statuses 501 - 1000 *********************/
+/**
+@name Packet Fifo Status Codes 501 - 510
+@{
+*/
+/********************* Packet Fifo statuses 501 - 510 ************************/
+
+#define XST_PFIFO_LACK_OF_DATA          501L	/*!< Not enough data in FIFO   */
+#define XST_PFIFO_NO_ROOM               502L	/*!< Not enough room in FIFO   */
+#define XST_PFIFO_BAD_REG_VALUE         503L	/*!< Self test, a register value
+						   was invalid after reset */
+#define XST_PFIFO_ERROR                 504L	/*!< Generic packet FIFO error */
+#define XST_PFIFO_DEADLOCK              505L	/*!< Packet FIFO is reporting
+						 * empty and full simultaneously
+						 */
+/** @} */
+/**
+@name DMA Status Codes 511 - 530
+@{
+*/
+/************************** DMA statuses 511 - 530 ***************************/
+
+#define XST_DMA_TRANSFER_ERROR          511L	/*!< Self test, DMA transfer
+						   failed */
+#define XST_DMA_RESET_REGISTER_ERROR    512L	/*!< Self test, a register value
+						   was invalid after reset */
+#define XST_DMA_SG_LIST_EMPTY           513L	/*!< Scatter gather list contains
+						   no buffer descriptors ready
+						   to be processed */
+#define XST_DMA_SG_IS_STARTED           514L	/*!< Scatter gather not stopped */
+#define XST_DMA_SG_IS_STOPPED           515L	/*!< Scatter gather not running */
+#define XST_DMA_SG_LIST_FULL            517L	/*!< All the buffer desciptors of
+						   the scatter gather list are
+						   being used */
+#define XST_DMA_SG_BD_LOCKED            518L	/*!< The scatter gather buffer
+						   descriptor which is to be
+						   copied over in the scatter
+						   list is locked */
+#define XST_DMA_SG_NOTHING_TO_COMMIT    519L	/*!< No buffer descriptors have been
+						   put into the scatter gather
+						   list to be commited */
+#define XST_DMA_SG_COUNT_EXCEEDED       521L	/*!< The packet count threshold
+						   specified was larger than the
+						   total # of buffer descriptors
+						   in the scatter gather list */
+#define XST_DMA_SG_LIST_EXISTS          522L	/*!< The scatter gather list has
+						   already been created */
+#define XST_DMA_SG_NO_LIST              523L	/*!< No scatter gather list has
+						   been created */
+#define XST_DMA_SG_BD_NOT_COMMITTED     524L	/*!< The buffer descriptor which was
+						   being started was not committed
+						   to the list */
+#define XST_DMA_SG_NO_DATA              525L	/*!< The buffer descriptor to start
+						   has already been used by the
+						   hardware so it can't be reused
+						 */
+#define XST_DMA_SG_LIST_ERROR           526L	/*!< General purpose list access
+						   error */
+#define XST_DMA_BD_ERROR                527L	/*!< General buffer descriptor
+						   error */
+/** @} */
+/**
+@name IPIF Status Codes Codes 531 - 550
+@{
+*/
+/************************** IPIF statuses 531 - 550 ***************************/
+
+#define XST_IPIF_REG_WIDTH_ERROR        531L	/*!< An invalid register width
+						   was passed into the function */
+#define XST_IPIF_RESET_REGISTER_ERROR   532L	/*!< The value of a register at
+						   reset was not valid */
+#define XST_IPIF_DEVICE_STATUS_ERROR    533L	/*!< A write to the device interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_DEVICE_ACK_ERROR       534L	/*!< The device interrupt status
+						   register did not reset when
+						   acked */
+#define XST_IPIF_DEVICE_ENABLE_ERROR    535L	/*!< The device interrupt enable
+						   register was not updated when
+						   other registers changed */
+#define XST_IPIF_IP_STATUS_ERROR        536L	/*!< A write to the IP interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_IP_ACK_ERROR           537L	/*!< The IP interrupt status register
+						   did not reset when acked */
+#define XST_IPIF_IP_ENABLE_ERROR        538L	/*!< IP interrupt enable register was
+						   not updated correctly when other
+						   registers changed */
+#define XST_IPIF_DEVICE_PENDING_ERROR   539L	/*!< The device interrupt pending
+						   register did not indicate the
+						   expected value */
+#define XST_IPIF_DEVICE_ID_ERROR        540L	/*!< The device interrupt ID register
+						   did not indicate the expected
+						   value */
+#define XST_IPIF_ERROR                  541L	/*!< Generic ipif error */
+/** @} */
+
+/****************** Device specific statuses 1001 - 4095 *********************/
+/**
+@name Ethernet Status Codes 1001 - 1050
+@{
+*/
+/********************* Ethernet statuses 1001 - 1050 *************************/
+
+#define XST_EMAC_MEMORY_SIZE_ERROR  1001L	/*!< Memory space is not big enough
+						 * to hold the minimum number of
+						 * buffers or descriptors */
+#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L	/*!< Memory allocation failed */
+#define XST_EMAC_MII_READ_ERROR     1003L	/*!< MII read error */
+#define XST_EMAC_MII_BUSY           1004L	/*!< An MII operation is in progress */
+#define XST_EMAC_OUT_OF_BUFFERS     1005L	/*!< Driver is out of buffers */
+#define XST_EMAC_PARSE_ERROR        1006L	/*!< Invalid driver init string */
+#define XST_EMAC_COLLISION_ERROR    1007L	/*!< Excess deferral or late
+						 * collision on polled send */
+/** @} */
+/**
+@name UART Status Codes 1051 - 1075
+@{
+*/
+/*********************** UART statuses 1051 - 1075 ***************************/
+#define XST_UART
+
+#define XST_UART_INIT_ERROR         1051L
+#define XST_UART_START_ERROR        1052L
+#define XST_UART_CONFIG_ERROR       1053L
+#define XST_UART_TEST_FAIL          1054L
+#define XST_UART_BAUD_ERROR         1055L
+#define XST_UART_BAUD_RANGE         1056L
+
+/** @} */
+/**
+@name IIC Status Codes 1076 - 1100
+@{
+*/
+/************************ IIC statuses 1076 - 1100 ***************************/
+
+#define XST_IIC_SELFTEST_FAILED         1076	/*!< self test failed            */
+#define XST_IIC_BUS_BUSY                1077	/*!< bus found busy              */
+#define XST_IIC_GENERAL_CALL_ADDRESS    1078	/*!< mastersend attempted with   */
+					     /* general call address        */
+#define XST_IIC_STAND_REG_RESET_ERROR   1079	/*!< A non parameterizable reg   */
+					     /* value after reset not valid */
+#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080	/*!< Tx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081	/*!< Rx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_TBA_REG_RESET_ERROR     1082	/*!< 10 bit addr incl in design  */
+					     /* value after reset not valid */
+#define XST_IIC_CR_READBACK_ERROR       1083	/*!< Read of the control register */
+					     /* didn't return value written */
+#define XST_IIC_DTR_READBACK_ERROR      1084	/*!< Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_DRR_READBACK_ERROR      1085	/*!< Read of the data Receive reg */
+					     /* didn't return value written */
+#define XST_IIC_ADR_READBACK_ERROR      1086	/*!< Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_TBA_READBACK_ERROR      1087	/*!< Read of the 10 bit addr reg */
+					     /* didn't return written value */
+#define XST_IIC_NOT_SLAVE               1088	/*!< The device isn't a slave    */
+/** @} */
+/**
+@name ATMC Status Codes 1101 - 1125
+@{
+*/
+/*********************** ATMC statuses 1101 - 1125 ***************************/
+
+#define XST_ATMC_ERROR_COUNT_MAX    1101L	/*!< the error counters in the ATM
+						   controller hit the max value
+						   which requires the statistics
+						   to be cleared */
+/** @} */
+/**
+@name Flash Status Codes 1126 - 1150
+@{
+*/
+/*********************** Flash statuses 1126 - 1150 **************************/
+
+#define XST_FLASH_BUSY                1126L	/*!< Flash is erasing or programming
+						 */
+#define XST_FLASH_READY               1127L	/*!< Flash is ready for commands */
+#define XST_FLASH_ERROR               1128L	/*!< Flash had detected an internal
+						   error. Use XFlash_DeviceControl
+						   to retrieve device specific codes
+						 */
+#define XST_FLASH_ERASE_SUSPENDED     1129L	/*!< Flash is in suspended erase state
+						 */
+#define XST_FLASH_WRITE_SUSPENDED     1130L	/*!< Flash is in suspended write state
+						 */
+#define XST_FLASH_PART_NOT_SUPPORTED  1131L	/*!< Flash type not supported by
+						   driver */
+#define XST_FLASH_NOT_SUPPORTED       1132L	/*!< Operation not supported */
+#define XST_FLASH_TOO_MANY_REGIONS    1133L	/*!< Too many erase regions */
+#define XST_FLASH_TIMEOUT_ERROR       1134L	/*!< Programming or erase operation
+						   aborted due to a timeout */
+#define XST_FLASH_ADDRESS_ERROR       1135L	/*!< Accessed flash outside its
+						   addressible range */
+#define XST_FLASH_ALIGNMENT_ERROR     1136L	/*!< Write alignment error */
+#define XST_FLASH_BLOCKING_CALL_ERROR 1137L	/*!< Couldn't return immediately from
+						   write/erase function with
+						   XFL_NON_BLOCKING_WRITE/ERASE
+						   option cleared */
+#define XST_FLASH_CFI_QUERY_ERROR     1138L	/*!< Failed to query the device */
+/** @} */
+/**
+@name SPI Status Codes 1151 - 1175
+@{
+*/
+/*********************** SPI statuses 1151 - 1175 ****************************/
+
+#define XST_SPI_MODE_FAULT          1151	/*!< master was selected as slave */
+#define XST_SPI_TRANSFER_DONE       1152	/*!< data transfer is complete */
+#define XST_SPI_TRANSMIT_UNDERRUN   1153	/*!< slave underruns transmit register */
+#define XST_SPI_RECEIVE_OVERRUN     1154	/*!< device overruns receive register */
+#define XST_SPI_NO_SLAVE            1155	/*!< no slave has been selected yet */
+#define XST_SPI_TOO_MANY_SLAVES     1156	/*!< more than one slave is being
+						 * selected */
+#define XST_SPI_NOT_MASTER          1157	/*!< operation is valid only as master */
+#define XST_SPI_SLAVE_ONLY          1158	/*!< device is configured as slave-only
+						 */
+#define XST_SPI_SLAVE_MODE_FAULT    1159	/*!< slave was selected while disabled */
+#define XST_SPI_SLAVE_MODE          1160	/*!< device has been addressed as slave */
+#define XST_SPI_RECEIVE_NOT_EMPTY   1161	/*!< device received data in slave mode */
+
+#define XST_SPI_COMMAND_ERROR       1162	/*!< unrecognised command - qspi only */
+#define XST_SPI_POLL_DONE           1163        /*!< controller completed polling the
+						   device for status */
+/** @} */
+/**
+@name OPB Arbiter Status Codes 1176 - 1200
+@{
+*/
+/********************** OPB Arbiter statuses 1176 - 1200 *********************/
+
+#define XST_OPBARB_INVALID_PRIORITY  1176	/*!< the priority registers have either
+						 * one master assigned to two or more
+						 * priorities, or one master not
+						 * assigned to any priority
+						 */
+#define XST_OPBARB_NOT_SUSPENDED     1177	/*!< an attempt was made to modify the
+						 * priority levels without first
+						 * suspending the use of priority
+						 * levels
+						 */
+#define XST_OPBARB_PARK_NOT_ENABLED  1178	/*!< bus parking by id was enabled but
+						 * bus parking was not enabled
+						 */
+#define XST_OPBARB_NOT_FIXED_PRIORITY 1179	/*!< the arbiter must be in fixed
+						 * priority mode to allow the
+						 * priorities to be changed
+						 */
+/** @} */
+/**
+@name INTC Status Codes 1201 - 1225
+@{
+*/
+/************************ Intc statuses 1201 - 1225 **************************/
+
+#define XST_INTC_FAIL_SELFTEST      1201	/*!< self test failed */
+#define XST_INTC_CONNECT_ERROR      1202	/*!< interrupt already in use */
+/** @} */
+/**
+@name TmrCtr Status Codes 1226 - 1250
+@{
+*/
+/********************** TmrCtr statuses 1226 - 1250 **************************/
+
+#define XST_TMRCTR_TIMER_FAILED     1226	/*!< self test failed */
+/** @} */
+/**
+@name WdtTb Status Codes 1251 - 1275
+@{
+*/
+/********************** WdtTb statuses 1251 - 1275 ***************************/
+
+#define XST_WDTTB_TIMER_FAILED      1251L
+/** @} */
+/**
+@name PlbArb status Codes 1276 - 1300
+@{
+*/
+/********************** PlbArb statuses 1276 - 1300 **************************/
+
+#define XST_PLBARB_FAIL_SELFTEST    1276L
+/** @} */
+/**
+@name Plb2Opb Status Codes 1301 - 1325
+@{
+*/
+/********************** Plb2Opb statuses 1301 - 1325 *************************/
+
+#define XST_PLB2OPB_FAIL_SELFTEST   1301L
+/** @} */
+/**
+@name Opb2Plb Status 1326 - 1350
+@{
+*/
+/********************** Opb2Plb statuses 1326 - 1350 *************************/
+
+#define XST_OPB2PLB_FAIL_SELFTEST   1326L
+/** @} */
+/**
+@name SysAce Status Codes 1351 - 1360
+@{
+*/
+/********************** SysAce statuses 1351 - 1360 **************************/
+
+#define XST_SYSACE_NO_LOCK          1351L	/*!< No MPU lock has been granted */
+/** @} */
+/**
+@name PCI Bridge Status Codes 1361 - 1375
+@{
+*/
+/********************** PCI Bridge statuses 1361 - 1375 **********************/
+
+#define XST_PCI_INVALID_ADDRESS     1361L
+/** @} */
+/**
+@name FlexRay Constants 1400 - 1409
+@{
+*/
+/********************** FlexRay constants 1400 - 1409 *************************/
+
+#define XST_FR_TX_ERROR			1400
+#define XST_FR_TX_BUSY			1401
+#define XST_FR_BUF_LOCKED		1402
+#define XST_FR_NO_BUF			1403
+/** @} */
+/**
+@name USB constants 1410 - 1420
+@{
+*/
+/****************** USB constants 1410 - 1420  *******************************/
+
+#define XST_USB_ALREADY_CONFIGURED	1410
+#define XST_USB_BUF_ALIGN_ERROR		1411
+#define XST_USB_NO_DESC_AVAILABLE	1412
+#define XST_USB_BUF_TOO_BIG		1413
+#define XST_USB_NO_BUF			1414
+/** @} */
+/**
+@name HWICAP constants 1421 - 1429
+@{
+*/
+/****************** HWICAP constants 1421 - 1429  *****************************/
+
+#define XST_HWICAP_WRITE_DONE		1421
+
+/** @} */
+/**
+@name AXI VDMA constants 1430 - 1440
+@{
+*/
+/****************** AXI VDMA constants 1430 - 1440  *****************************/
+
+#define XST_VDMA_MISMATCH_ERROR		1430
+/** @} */
+/**
+@name NAND Flash Status Codes 1441 - 1459
+@{
+*/
+/*********************** NAND Flash statuses 1441 - 1459  *********************/
+
+#define XST_NAND_BUSY			1441L	/*!< Flash is erasing or
+						 * programming
+						 */
+#define XST_NAND_READY			1442L	/*!< Flash is ready for commands
+						 */
+#define XST_NAND_ERROR			1443L	/*!< Flash had detected an
+						 * internal error.
+						 */
+#define XST_NAND_PART_NOT_SUPPORTED	1444L	/*!< Flash type not supported by
+						 * driver
+						 */
+#define XST_NAND_OPT_NOT_SUPPORTED	1445L	/*!< Operation not supported
+						 */
+#define XST_NAND_TIMEOUT_ERROR		1446L	/*!< Programming or erase
+						 * operation aborted due to a
+						 * timeout
+						 */
+#define XST_NAND_ADDRESS_ERROR		1447L	/*!< Accessed flash outside its
+						 * addressible range
+						 */
+#define XST_NAND_ALIGNMENT_ERROR	1448L	/*!< Write alignment error
+						 */
+#define XST_NAND_PARAM_PAGE_ERROR	1449L	/*!< Failed to read parameter
+						 * page of the device
+						 */
+#define XST_NAND_CACHE_ERROR		1450L	/*!< Flash page buffer error
+						 */
+
+#define XST_NAND_WRITE_PROTECTED	1451L	/*!< Flash is write protected
+						 */
+/** @} */
+
+/**************************** Type Definitions *******************************/
+
+typedef s32 XStatus;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_status_codes".
+*/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xtime_l.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xtime_l.h
new file mode 100644
index 0000000000000000000000000000000000000000..f939d84f616b72fffe1b7b097c01129243b177ed
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xtime_l.h
@@ -0,0 +1,96 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xtime_l.h
+* @addtogroup a9_time_apis Cortex A9 Time Functions
+*
+* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This
+* counter increases by one at every two processor cycles. These functions can
+* be used to get/set time in the global timer.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.06a sgd    05/15/12 Upadted get/set time functions to make use Global Timer
+* 3.06a asa    06/17/12 Reverted back the changes to make use Global Timer.
+* 3.07a sgd    07/05/12 Upadted get/set time functions to make use Global Timer
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XTIME_H /* prevent circular inclusions */
+#define XTIME_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xparameters.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+typedef u64 XTime;
+
+/************************** Constant Definitions *****************************/
+#define GLOBAL_TMR_BASEADDR               XPAR_GLOBAL_TMR_BASEADDR
+#define GTIMER_COUNTER_LOWER_OFFSET       0x00U
+#define GTIMER_COUNTER_UPPER_OFFSET       0x04U
+#define GTIMER_CONTROL_OFFSET             0x08U
+
+
+/* Global Timer is always clocked at half of the CPU frequency */
+#define COUNTS_PER_SECOND          (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2)
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void XTime_SetTime(XTime Xtime_Global);
+void XTime_GetTime(XTime *Xtime_Global);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XTIME_H */
+/**
+* @} End of "addtogroup a9_time_apis".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xttcps.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xttcps.h
new file mode 100644
index 0000000000000000000000000000000000000000..bae9d28fecb14a37e90091fc0b5a359ea2b57fa8
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xttcps.h
@@ -0,0 +1,466 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps.h
+* @addtogroup ttcps_v3_0
+* @{
+* @details
+*
+* This is the driver for one 16-bit timer counter in the Triple Timer Counter
+* (TTC) module in the Ps block.
+*
+* The TTC module provides three independent timer/counter modules that can each
+* be clocked using either the system clock (pclk) or an externally driven
+* clock (ext_clk). In addition, each counter can independently prescale its
+* selected clock input (divided by 2 to 65536). Counters can be set to
+* decrement or increment.
+*
+* Each of the counters can be programmed to generate interrupt pulses:
+*	. At a regular, predefined period, that is on a timed interval
+*	. When the counter registers overflow
+* 	. When the count matches any one of the three 'match' registers
+*
+* Therefore, up to six different events can trigger a timer interrupt: three
+* match interrupts, an overflow interrupt, an interval interrupt and an event
+* timer interrupt. Note that the overflow interrupt and the interval interrupt
+* are mutually exclusive.
+*
+* <b>Initialization & Configuration</b>
+*
+* An XTtcPs_Config structure is used to configure a driver instance.
+* Information in the XTtcPs_Config structure is the hardware properties
+* about the device.
+*
+* A driver instance is initialized through
+* XTtcPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr). Where CfgPtr
+* is a pointer to the XTtcPs_Config structure, it can be looked up statically
+* through XTtcPs_LookupConfig(DeviceID), or passed in by the caller. The
+* EffectiveAddr can be the static base address of the device or virtual
+* mapped address if address translation is supported.
+*
+* <b>Interrupts</b>
+*
+* Interrupt handler is not provided by the driver, as handling of interrupt
+* is application specific.
+*
+* @note
+* The default setting for a timer/counter is:
+*  - Overflow Mode
+*  - Internal clock (pclk) selected
+*  - Counter disabled
+*  - All Interrupts disabled
+*  - Output waveforms disabled
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -----------------------------------------------------
+* 1.00a drg/jz 01/20/10 First release..
+* 2.0   adk    12/10/13 Updated as per the New Tcl API's
+* 3.0	pkp    12/09/14 Added support for Zynq Ultrascale Mp.Also code
+*			modified for MISRA-C:2012 compliance.
+* 3.2   mus    10/28/16 Modified XTtcPs_GetCounterValue and XTtcPs_SetInterval
+*                       macros to return 32 bit values for zynq ultrascale+mpsoc
+*       ms   01/23/17 Modified xil_printf statement in main function for all
+*                     examples to ensure that "Successfully ran" and "Failed"
+*                     strings are available in all examples. This is a fix
+*                     for CR-965028.
+*       ms   03/17/17 Added readme.txt file in examples folder for doxygen
+*                     generation.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XTTCPS_H		/* prevent circular inclusions */
+#define XTTCPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xttcps_hw.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+/*
+ * Flag for a9 processor
+ */
+ #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
+ #define ARMA9
+ #endif
+
+/*
+ * Maximum Value for interval counter
+ */
+ #if defined(ARMA9)
+ #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFU
+ #else
+ #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFFFFFU
+ #endif
+
+/** @name Configuration options
+ *
+ * Options for the device. Each of the options is bit field, so more than one
+ * options can be specified.
+ *
+ * @{
+ */
+#define XTTCPS_OPTION_EXTERNAL_CLK	0x00000001U 	/**< External clock source */
+#define XTTCPS_OPTION_CLK_EDGE_NEG	0x00000002U	/**< Clock on trailing edge for
+						     external clock*/
+#define XTTCPS_OPTION_INTERVAL_MODE	0x00000004U	/**< Interval mode */
+#define XTTCPS_OPTION_DECREMENT		0x00000008U	/**< Decrement the counter */
+#define XTTCPS_OPTION_MATCH_MODE	0x00000010U	/**< Match mode */
+#define XTTCPS_OPTION_WAVE_DISABLE	0x00000020U 	/**< No waveform output */
+#define XTTCPS_OPTION_WAVE_POLARITY	0x00000040U	/**< Waveform polarity */
+/*@}*/
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;	  /**< Unique ID for device */
+	u32 BaseAddress;  /**< Base address for device */
+	u32 InputClockHz; /**< Input clock frequency */
+} XTtcPs_Config;
+
+/**
+ * The XTtcPs driver instance data. The user is required to allocate a
+ * variable of this type for each PS timer/counter device in the system. A
+ * pointer to a variable of this type is then passed to various driver API
+ * functions.
+ */
+typedef struct {
+	XTtcPs_Config Config;	/**< Configuration structure */
+	u32 IsReady;		/**< Device is initialized and ready */
+} XTtcPs;
+
+/**
+ * This typedef contains interval count
+ */
+#if defined(ARMA9)
+typedef u16 XInterval;
+#else
+typedef u32 XInterval;
+#endif
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*
+ * Internal helper macros
+ */
+#define InstReadReg(InstancePtr, RegOffset) \
+    (Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset)))
+
+#define InstWriteReg(InstancePtr, RegOffset, Data) \
+    (Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset), (u32)(Data)))
+
+/*****************************************************************************/
+/**
+*
+* This function starts the counter/timer without resetting the counter value.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	None
+*
+* @note		C-style signature:
+*		void XTtcPs_Start(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_Start(InstancePtr)	\
+		InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET,	\
+		(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) &	\
+		 ~XTTCPS_CNT_CNTRL_DIS_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function stops the counter/timer. This macro may be called at any time
+* to stop the counter. The counter holds the last value until it is reset,
+* restarted or enabled.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	None
+*
+* @note		C-style signature:
+*		void XTtcPs_Stop(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_Stop(InstancePtr)		\
+		InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET,	\
+		(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) |	\
+		 XTTCPS_CNT_CNTRL_DIS_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function checks whether the timer counter has already started.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance
+*
+* @return	Non-zero if the device has started, '0' otherwise.
+*
+* @note		C-style signature:
+*		int XTtcPs_IsStarted(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_IsStarted(InstancePtr) \
+     ((InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
+       XTTCPS_CNT_CNTRL_DIS_MASK) == 0U)
+
+/*****************************************************************************/
+/**
+*
+* This function returns the current 16-bit counter value. It may be called at
+* any time.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	zynq:16 bit counter value.
+*           zynq ultrascale+mpsoc:32 bit counter value.
+*
+* @note		C-style signature:
+*		zynq: u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
+*       zynq ultrascale+mpsoc: u32 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#if defined(ARMA9)
+/*
+ * ttc supports 16 bit counter for zynq
+ */
+#define XTtcPs_GetCounterValue(InstancePtr) \
+		(u16)InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
+#else
+/*
+ * ttc supports 32 bit counter for zynq ultrascale+mpsoc
+ */
+#define XTtcPs_GetCounterValue(InstancePtr) \
+               InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This function sets the interval value to be used in interval mode.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	Value is the 16-bit value to be set in the interval register.
+*
+* @return	None
+*
+* @note		C-style signature:
+*		void XTtcPs_SetInterval(XTtcPs *InstancePtr, u16 Value)
+*
+****************************************************************************/
+#define XTtcPs_SetInterval(InstancePtr, Value)	\
+		InstWriteReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET, (Value))
+
+/*****************************************************************************/
+/**
+*
+* This function gets the interval value from the interval register.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	zynq:16 bit interval value.
+*           zynq ultrascale+mpsoc:32 bit interval value.
+*
+* @note		C-style signature:
+*		zynq: u16 XTtcPs_GetInterval(XTtcPs *InstancePtr)
+*       zynq ultrascale+mpsoc: u32 XTtcPs_GetInterval(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#if defined(ARMA9)
+/*
+ * ttc supports 16 bit interval counter for zynq
+ */
+#define XTtcPs_GetInterval(InstancePtr) \
+		(u16)InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
+#else
+/*
+ * ttc supports 32 bit interval counter for zynq ultrascale+mpsoc
+ */
+#define XTtcPs_GetInterval(InstancePtr) \
+		InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
+#endif
+/*****************************************************************************/
+/**
+*
+* This macro resets the count register. It may be called at any time. The
+* counter is reset to either 0 or 0xFFFF, or the interval value, depending on
+* the increment/decrement mode. The state of the counter, as started or
+* stopped, is not affected by calling reset.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	None
+*
+* @note		C-style signature:
+*		void XTtcPs_ResetCounterValue(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_ResetCounterValue(InstancePtr) \
+		InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET,	\
+		(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
+		 (u32)XTTCPS_CNT_CNTRL_RST_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function enables the interrupts.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	InterruptMask defines which interrupt should be enabled.
+*		Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+*		This is a bit mask, all set bits will be enabled, cleared bits
+*		will not be disabled.
+*
+* @return	None.
+*
+* @note
+* C-style signature:
+*	void XTtcPs_EnableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_EnableInterrupts(InstancePtr, InterruptMask)		\
+		InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET,		\
+		(InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) |	\
+		 (InterruptMask)))
+
+/*****************************************************************************/
+/**
+*
+* This function disables the interrupts.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	InterruptMask defines which interrupt should be disabled.
+*		Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+*		This is a bit mask, all set bits will be disabled, cleared bits
+*		will not be disabled.
+*
+* @return	None.
+*
+* @note
+* C-style signature:
+*	void XTtcPs_DisableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_DisableInterrupts(InstancePtr, InterruptMask) \
+		InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET,	\
+		(InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) &	\
+		 ~(InterruptMask)))
+
+/*****************************************************************************/
+/**
+*
+* This function reads the interrupt status.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		u32 XTtcPs_GetInterruptStatus(XTtcPs *InstancePtr)
+*
+******************************************************************************/
+#define XTtcPs_GetInterruptStatus(InstancePtr)	 \
+		InstReadReg((InstancePtr), XTTCPS_ISR_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears the interrupt status.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	InterruptMask defines which interrupt should be cleared.
+*		Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+*		This is a bit mask, all set bits will be cleared, cleared bits
+*		will not be cleared.
+*
+* @return	None.
+*
+* @note
+* C-style signature:
+*	void XTtcPs_ClearInterruptStatus(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_ClearInterruptStatus(InstancePtr, InterruptMask) \
+		InstWriteReg((InstancePtr), XTTCPS_ISR_OFFSET, \
+		 (InterruptMask))
+
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization functions in xttcps_sinit.c
+ */
+XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Required functions, in xttcps.c
+ */
+s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr,
+         XTtcPs_Config * ConfigPtr, u32 EffectiveAddr);
+
+void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value);
+u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex);
+
+void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue);
+u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr);
+
+void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
+        XInterval *Interval, u8 *Prescaler);
+
+/*
+ * Functions for options, in file xttcps_options.c
+ */
+s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options);
+u32 XTtcPs_GetOptions(XTtcPs *InstancePtr);
+
+/*
+ * Function for self-test, in file xttcps_selftest.c
+ */
+s32 XTtcPs_SelfTest(XTtcPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xttcps_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xttcps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..af78bcd67c8d606674a4d268a62f1a60ada41ebc
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xttcps_hw.h
@@ -0,0 +1,212 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_hw.h
+* @addtogroup ttcps_v3_0
+* @{
+*
+* This file defines the hardware interface to one of the three timer counters
+* in the Ps block.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -------------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XTTCPS_HW_H		/* prevent circular inclusions */
+#define XTTCPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of the device.
+ *
+ * @{
+ */
+#define XTTCPS_CLK_CNTRL_OFFSET		0x00000000U  /**< Clock Control Register */
+#define XTTCPS_CNT_CNTRL_OFFSET		0x0000000CU  /**< Counter Control Register*/
+#define XTTCPS_COUNT_VALUE_OFFSET	0x00000018U  /**< Current Counter Value */
+#define XTTCPS_INTERVAL_VAL_OFFSET	0x00000024U  /**< Interval Count Value */
+#define XTTCPS_MATCH_0_OFFSET		0x00000030U  /**< Match 1 value */
+#define XTTCPS_MATCH_1_OFFSET		0x0000003CU  /**< Match 2 value */
+#define XTTCPS_MATCH_2_OFFSET		0x00000048U  /**< Match 3 value */
+#define XTTCPS_ISR_OFFSET			0x00000054U  /**< Interrupt Status Register */
+#define XTTCPS_IER_OFFSET			0x00000060U  /**< Interrupt Enable Register */
+/* @} */
+
+/** @name Clock Control Register
+ * Clock Control Register definitions
+ * @{
+ */
+#define XTTCPS_CLK_CNTRL_PS_EN_MASK		0x00000001U  /**< Prescale enable */
+#define XTTCPS_CLK_CNTRL_PS_VAL_MASK	0x0000001EU  /**< Prescale value */
+#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT			 1U  /**< Prescale shift */
+#define XTTCPS_CLK_CNTRL_PS_DISABLE				16U  /**< Prescale disable */
+#define XTTCPS_CLK_CNTRL_SRC_MASK		0x00000020U  /**< Clock source */
+#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK	0x00000040U  /**< External Clock edge */
+/* @} */
+
+/** @name Counter Control Register
+ * Counter Control Register definitions
+ * @{
+ */
+#define XTTCPS_CNT_CNTRL_DIS_MASK		0x00000001U /**< Disable the counter */
+#define XTTCPS_CNT_CNTRL_INT_MASK		0x00000002U /**< Interval mode */
+#define XTTCPS_CNT_CNTRL_DECR_MASK		0x00000004U /**< Decrement mode */
+#define XTTCPS_CNT_CNTRL_MATCH_MASK		0x00000008U /**< Match mode */
+#define XTTCPS_CNT_CNTRL_RST_MASK		0x00000010U /**< Reset counter */
+#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK	0x00000020U /**< Enable waveform */
+#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK	0x00000040U /**< Waveform polarity */
+#define XTTCPS_CNT_CNTRL_RESET_VALUE	0x00000021U /**< Reset value */
+/* @} */
+
+/** @name Current Counter Value Register
+ * Current Counter Value Register definitions
+ * @{
+ */
+#define XTTCPS_COUNT_VALUE_MASK		0x0000FFFFU /**< 16-bit counter value */
+/* @} */
+
+/** @name Interval Value Register
+ * Interval Value Register is the maximum value the counter will count up or
+ * down to.
+ * @{
+ */
+#define XTTCPS_INTERVAL_VAL_MASK	0x0000FFFFU /**< 16-bit Interval value*/
+/* @} */
+
+/** @name Match Registers
+ * Definitions for Match registers, each timer counter has three match
+ * registers.
+ * @{
+ */
+#define XTTCPS_MATCH_MASK		0x0000FFFFU /**< 16-bit Match value */
+#define XTTCPS_NUM_MATCH_REG			 3U /**< Num of Match reg */
+/* @} */
+
+/** @name Interrupt Registers
+ * Following register bit mask is for all interrupt registers.
+ *
+ * @{
+ */
+#define XTTCPS_IXR_INTERVAL_MASK	0x00000001U  /**< Interval Interrupt */
+#define XTTCPS_IXR_MATCH_0_MASK		0x00000002U  /**< Match 1 Interrupt */
+#define XTTCPS_IXR_MATCH_1_MASK		0x00000004U  /**< Match 2 Interrupt */
+#define XTTCPS_IXR_MATCH_2_MASK		0x00000008U  /**< Match 3 Interrupt */
+#define XTTCPS_IXR_CNT_OVR_MASK		0x00000010U  /**< Counter Overflow */
+#define XTTCPS_IXR_ALL_MASK			0x0000001FU  /**< All valid Interrupts */
+/* @} */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given Timer Counter register.
+*
+* @param	BaseAddress is the base address of the timer counter device.
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note		C-style signature:
+*		u32 XTtcPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XTtcPs_ReadReg(BaseAddress, RegOffset) \
+    (Xil_In32((BaseAddress) + (u32)(RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Timer Counter register.
+*
+* @param	BaseAddress is the base address of the timer counter device.
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XTtcPs_WriteReg(XTtcPs BaseAddress, u32 RegOffset,
+*		u32 Data)
+*
+*****************************************************************************/
+#define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \
+    (Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)))
+
+/****************************************************************************/
+/**
+*
+* Calculate a match register offset using the Match Register index.
+*
+* @param	MatchIndex is the 0-2 value of the match register
+*
+* @return	MATCH_N_OFFSET.
+*
+* @note		C-style signature:
+*		u32 XTtcPs_Match_N_Offset(u8 MatchIndex)
+*
+*****************************************************************************/
+#define XTtcPs_Match_N_Offset(MatchIndex) \
+		((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex)))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xuartps.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xuartps.h
new file mode 100644
index 0000000000000000000000000000000000000000..a5155940e6809d9ff6ae853a776e31686b604376
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xuartps.h
@@ -0,0 +1,518 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps.h
+* @addtogroup uartps_v3_1
+* @{
+* @details
+*
+* This driver supports the following features:
+*
+* - Dynamic data format (baud rate, data bits, stop bits, parity)
+* - Polled mode
+* - Interrupt driven mode
+* - Transmit and receive FIFOs (32 byte FIFO depth)
+* - Access to the external modem control lines
+*
+* <b>Initialization & Configuration</b>
+*
+* The XUartPs_Config structure is used by the driver to configure itself.
+* Fields inside this structure are properties of XUartPs based on its hardware
+* build.
+*
+* To support multiple runtime loading and initialization strategies employed
+* by various operating systems, the driver instance can be initialized in the
+* following way:
+*
+*   - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+*	 configuration structure provided by the caller. If running in a system
+*	 with address translation, the parameter EffectiveAddr should be the
+* 	  virtual address.
+*
+* <b>Baud Rate</b>
+*
+* The UART has an internal baud rate generator, which furnishes the baud rate
+* clock for both the receiver and the transmitter. Ther input clock frequency
+* can be either the master clock or the master clock divided by 8, configured
+* through the mode register.
+*
+* Accompanied with the baud rate divider register, the baud rate is determined
+* by:
+* <pre>
+*	baud_rate = input_clock / (bgen * (bdiv + 1)
+* </pre>
+* where bgen is the value of the baud rate generator, and bdiv is the value of
+* baud rate divider.
+*
+* <b>Interrupts</b>
+*
+* The FIFOs are not flushed when the driver is initialized, but a function is
+* provided to allow the user to reset the FIFOs if desired.
+*
+* The driver defaults to no interrupts at initialization such that interrupts
+* must be enabled if desired. An interrupt is generated for one of the
+* following conditions.
+*
+* - A change in the modem signals
+* - Data in the receive FIFO for a configuable time without receiver activity
+* - A parity error
+* - A framing error
+* - An overrun error
+* - Transmit FIFO is full
+* - Transmit FIFO is empty
+* - Receive FIFO is full
+* - Receive FIFO is empty
+* - Data in the receive FIFO equal to the receive threshold
+*
+* The application can control which interrupts are enabled using the
+* XUartPs_SetInterruptMask() function.
+*
+* In order to use interrupts, it is necessary for the user to connect the
+* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt
+* system of the application. A separate handler should be provided by the
+* application to communicate with the interrupt system, and conduct
+* application specific interrupt handling. An application registers its own
+* handler through the XUartPs_SetHandler() function.
+*
+* <b>Data Transfer</b>
+*
+* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the
+* driver to allow data to be sent and received. They can be used in either
+* polled or interrupt mode.
+*
+* @note
+*
+* The default configuration for the UART after initialization is:
+*
+* - 9,600 bps or XPAR_DFT_BAUDRATE if defined
+* - 8 data bits
+* - 1 stop bit
+* - no parity
+* - FIFO's are enabled with a receive threshold of 8 bytes
+* - The RX timeout is enabled with a timeout of 1 (4 char times)
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00a	drg/jz 01/12/10 First Release
+* 1.00a sdm    09/27/11 Fixed compiler warnings and also a bug
+*		        in XUartPs_SetFlowDelay where the value was not
+*			being written to the register.
+* 1.01a sdm    12/20/11 Removed the InputClockHz parameter from the XUartPs
+*			instance structure and the driver is updated to use
+*			InputClockHz parameter from the XUartPs_Config config
+*			structure.
+*			Added a parameter to XUartPs_Config structure which
+*			specifies whether the user has selected Modem pins
+*			to be connected to MIO or FMIO.
+*			Added the tcl file to generate the xparameters.h
+* 1.02a sg     05/16/12	Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
+* 1.03a sg     07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
+*			with the correct values for CR 666724
+* 			Added defines for XUARTPS_IXR_TOVR,  XUARTPS_IXR_TNFUL
+*			and XUARTPS_IXR_TTRIG.
+*			Modified the name of these defines
+*			XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+*			XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+*			XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+*			XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk     08/22/13 Added API for uart reset and related
+*			constant definitions.
+* 2.0   hk      03/07/14 Version number revised.
+* 2.1   hk     04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
+* 2.2   hk     06/23/14 SW reset of RX and TX should be done when changing
+*                       baud rate. CR# 804281.
+* 3.0   vm     12/09/14 Modified source code according to misrac guideline.
+*			Support for Zynq Ultrascale Mp added.
+* 3.1	kvn    04/10/15 Modified code for latest RTL changes. Also added
+*						platform variable in driver instance structure.
+* 3.1   adk   14/03/16  Include interrupt examples in the peripheral test when
+*			uart is connected to a valid interrupt controller CR#946803.
+* 3.2   rk     07/20/16 Modified the logic for transmission break bit set
+* 3.4   ms     01/23/17 Added xil_printf statement in main function for all
+*                       examples to ensure that "Successfully ran" and "Failed"
+*                       strings are available in all examples. This is a fix
+*                       for CR-965028.
+*       ms     03/17/17 Added readme.txt file in examples folder for doxygen
+*                       generation.
+*
+* </pre>
+*
+*****************************************************************************/
+
+#ifndef XUARTPS_H		/* prevent circular inclusions */
+#define XUARTPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xuartps_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants indicate the max and min baud rates and these
+ * numbers are based only on the testing that has been done. The hardware
+ * is capable of other baud rates.
+ */
+#define XUARTPS_MAX_RATE	 921600U
+#define XUARTPS_MIN_RATE	 110U
+
+#define XUARTPS_DFT_BAUDRATE  115200U   /* Default baud rate */
+
+/** @name Configuration options
+ * @{
+ */
+/**
+ * These constants specify the options that may be set or retrieved
+ * with the driver, each is a unique bit mask such that multiple options
+ * may be specified.  These constants indicate the available options
+ * in active state.
+ *
+ */
+
+#define XUARTPS_OPTION_SET_BREAK	0x0080U /**< Starts break transmission */
+#define XUARTPS_OPTION_STOP_BREAK	0x0040U /**< Stops break transmission */
+#define XUARTPS_OPTION_RESET_TMOUT	0x0020U /**< Reset the receive timeout */
+#define XUARTPS_OPTION_RESET_TX		0x0010U /**< Reset the transmitter */
+#define XUARTPS_OPTION_RESET_RX		0x0008U /**< Reset the receiver */
+#define XUARTPS_OPTION_ASSERT_RTS	0x0004U /**< Assert the RTS bit */
+#define XUARTPS_OPTION_ASSERT_DTR	0x0002U /**< Assert the DTR bit */
+#define XUARTPS_OPTION_SET_FCM		0x0001U /**< Turn on flow control mode */
+/*@}*/
+
+
+/** @name Channel Operational Mode
+ *
+ * The UART can operate in one of four modes: Normal, Local Loopback, Remote
+ * Loopback, or automatic echo.
+ *
+ * @{
+ */
+
+#define XUARTPS_OPER_MODE_NORMAL		(u8)0x00U	/**< Normal Mode */
+#define XUARTPS_OPER_MODE_AUTO_ECHO		(u8)0x01U	/**< Auto Echo Mode */
+#define XUARTPS_OPER_MODE_LOCAL_LOOP	(u8)0x02U	/**< Local Loopback Mode */
+#define XUARTPS_OPER_MODE_REMOTE_LOOP	(u8)0x03U	/**< Remote Loopback Mode */
+
+/* @} */
+
+/** @name Data format values
+ *
+ * These constants specify the data format that the driver supports.
+ * The data format includes the number of data bits, the number of stop
+ * bits and parity.
+ *
+ * @{
+ */
+#define XUARTPS_FORMAT_8_BITS		0U /**< 8 data bits */
+#define XUARTPS_FORMAT_7_BITS		2U /**< 7 data bits */
+#define XUARTPS_FORMAT_6_BITS		3U /**< 6 data bits */
+
+#define XUARTPS_FORMAT_NO_PARITY	4U /**< No parity */
+#define XUARTPS_FORMAT_MARK_PARITY	3U /**< Mark parity */
+#define XUARTPS_FORMAT_SPACE_PARITY	2U /**< parity */
+#define XUARTPS_FORMAT_ODD_PARITY	1U /**< Odd parity */
+#define XUARTPS_FORMAT_EVEN_PARITY	0U /**< Even parity */
+
+#define XUARTPS_FORMAT_2_STOP_BIT	2U /**< 2 stop bits */
+#define XUARTPS_FORMAT_1_5_STOP_BIT	1U /**< 1.5 stop bits */
+#define XUARTPS_FORMAT_1_STOP_BIT	0U /**< 1 stop bit */
+/*@}*/
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that an application can handle
+ * using its specific handler function. Note that these constants are not bit
+ * mask, so only one event can be passed to an application at a time.
+ *
+ * @{
+ */
+#define XUARTPS_EVENT_RECV_DATA			1U /**< Data receiving done */
+#define XUARTPS_EVENT_RECV_TOUT			2U /**< A receive timeout occurred */
+#define XUARTPS_EVENT_SENT_DATA			3U /**< Data transmission done */
+#define XUARTPS_EVENT_RECV_ERROR		4U /**< A receive error detected */
+#define XUARTPS_EVENT_MODEM				5U /**< Modem status changed */
+#define XUARTPS_EVENT_PARE_FRAME_BRKE	6U /**< A receive parity, frame, break
+											 *	error detected */
+#define XUARTPS_EVENT_RECV_ORERR		7U /**< A receive overrun error detected */
+/*@}*/
+
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;	 /**< Unique ID  of device */
+	u32 BaseAddress; /**< Base address of device (IPIF) */
+	u32 InputClockHz;/**< Input clock frequency */
+	s32 ModemPinsConnected; /** Specifies whether modem pins are connected
+				 *  to MIO or FMIO */
+} XUartPs_Config;
+
+/* Keep track of state information about a data buffer in the interrupt mode. */
+typedef struct {
+	u8 *NextBytePtr;
+	u32 RequestedBytes;
+	u32 RemainingBytes;
+} XUartPsBuffer;
+
+/**
+ * Keep track of data format setting of a device.
+ */
+typedef struct {
+	u32 BaudRate;	/**< In bps, ie 1200 */
+	u32 DataBits;	/**< Number of data bits */
+	u32 Parity;		/**< Parity */
+	u8 StopBits;	/**< Number of stop bits */
+} XUartPsFormat;
+
+/******************************************************************************/
+/**
+ * This data type defines a handler that an application defines to communicate
+ * with interrupt system to retrieve state information about an application.
+ *
+ * @param	CallBackRef is a callback reference passed in by the upper layer
+ *		when setting the handler, and is passed back to the upper layer
+ *		when the handler is called. It is used to find the device driver
+ *		instance.
+ * @param	Event contains one of the event constants indicating events that
+ *		have occurred.
+ * @param	EventData contains the number of bytes sent or received at the
+ *		time of the call for send and receive events and contains the
+ *		modem status for modem events.
+ *
+ ******************************************************************************/
+typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event,
+				  u32 EventData);
+
+/**
+ * The XUartPs driver instance data structure. A pointer to an instance data
+ * structure is passed around by functions to refer to a specific driver
+ * instance.
+ */
+typedef struct {
+	XUartPs_Config Config;	/* Configuration data structure */
+	u32 InputClockHz;	/* Input clock frequency */
+	u32 IsReady;		/* Device is initialized and ready */
+	u32 BaudRate;		/* Current baud rate */
+
+	XUartPsBuffer SendBuffer;
+	XUartPsBuffer ReceiveBuffer;
+
+	XUartPs_Handler Handler;
+	void *CallBackRef;	/* Callback reference for event handler */
+	u32 Platform;
+	u8 is_rxbs_error;
+} XUartPs;
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Get the UART Channel Status Register.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetChannelStatus(InstancePtr)   \
+	Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET)
+
+/****************************************************************************/
+/**
+* Get the UART Mode Control Register.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_GetControl(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetModeControl(InstancePtr)  \
+	Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET)
+
+/****************************************************************************/
+/**
+* Set the UART Mode Control Register.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*	void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \
+   Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \
+			(u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Enable the transmitter and receiver of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XUartPs_EnableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_EnableUart(InstancePtr) \
+   Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
+	  ((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \
+	  (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN)))
+
+/****************************************************************************/
+/**
+* Disable the transmitter and receiver of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XUartPs_DisableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_DisableUart(InstancePtr) \
+   Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
+	  (((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \
+	  (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS)))
+
+/****************************************************************************/
+/**
+* Determine if the transmitter FIFO is empty.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*		- TRUE if a byte can be sent
+*		- FALSE if the Transmitter Fifo is not empty
+*
+* @note		C-Style signature:
+*		u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitEmpty(InstancePtr)				\
+	((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \
+	 (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY)
+
+
+/************************** Function Prototypes *****************************/
+
+/* Static lookup function implemented in xuartps_sinit.c */
+XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId);
+
+/* Interface functions implemented in xuartps.c */
+s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
+				  XUartPs_Config * Config, u32 EffectiveAddr);
+
+u32 XUartPs_Send(XUartPs *InstancePtr,u8 *BufferPtr,
+			   u32 NumBytes);
+
+u32 XUartPs_Recv(XUartPs *InstancePtr,u8 *BufferPtr,
+			   u32 NumBytes);
+
+s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate);
+
+/* Options functions in xuartps_options.c */
+void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options);
+
+u16 XUartPs_GetOptions(XUartPs *InstancePtr);
+
+void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel);
+
+u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr);
+
+u16 XUartPs_GetModemStatus(XUartPs *InstancePtr);
+
+u32 XUartPs_IsSending(XUartPs *InstancePtr);
+
+u8 XUartPs_GetOperMode(XUartPs *InstancePtr);
+
+void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode);
+
+u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr);
+
+void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue);
+
+u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr);
+
+void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout);
+
+s32 XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
+
+void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
+
+/* interrupt functions in xuartps_intr.c */
+u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr);
+
+void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask);
+
+void XUartPs_InterruptHandler(XUartPs *InstancePtr);
+
+void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
+			 void *CallBackRef);
+
+/* self-test functions in xuartps_selftest.c */
+s32 XUartPs_SelfTest(XUartPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xuartps_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xuartps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..9f5f0b70010d82f4f26a161084a3d48d46504a3e
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xuartps_hw.h
@@ -0,0 +1,449 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xuartps_hw.h
+* @addtogroup uartps_v3_1
+* @{
+*
+* This header file contains the hardware interface of an XUartPs device.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	drg/jz 01/12/10 First Release
+* 1.03a sg     09/04/12 Added defines for XUARTPS_IXR_TOVR,  XUARTPS_IXR_TNFUL
+*			and XUARTPS_IXR_TTRIG.
+*			Modified the names of these defines
+*			XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+*			XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+*			XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+*			XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk     08/22/13 Added prototype for uart reset and related
+*			constant definitions.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn    04/10/15 Modified code for latest RTL changes.
+*
+* </pre>
+*
+******************************************************************************/
+#ifndef XUARTPS_HW_H		/* prevent circular inclusions */
+#define XUARTPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the UART.
+ * @{
+ */
+#define XUARTPS_CR_OFFSET		0x0000U  /**< Control Register [8:0] */
+#define XUARTPS_MR_OFFSET		0x0004U  /**< Mode Register [9:0] */
+#define XUARTPS_IER_OFFSET		0x0008U  /**< Interrupt Enable [12:0] */
+#define XUARTPS_IDR_OFFSET		0x000CU  /**< Interrupt Disable [12:0] */
+#define XUARTPS_IMR_OFFSET		0x0010U  /**< Interrupt Mask [12:0] */
+#define XUARTPS_ISR_OFFSET		0x0014U  /**< Interrupt Status [12:0]*/
+#define XUARTPS_BAUDGEN_OFFSET	0x0018U  /**< Baud Rate Generator [15:0] */
+#define XUARTPS_RXTOUT_OFFSET	0x001CU  /**< RX Timeout [7:0] */
+#define XUARTPS_RXWM_OFFSET		0x0020U  /**< RX FIFO Trigger Level [5:0] */
+#define XUARTPS_MODEMCR_OFFSET	0x0024U  /**< Modem Control [5:0] */
+#define XUARTPS_MODEMSR_OFFSET	0x0028U  /**< Modem Status [8:0] */
+#define XUARTPS_SR_OFFSET		0x002CU  /**< Channel Status [14:0] */
+#define XUARTPS_FIFO_OFFSET		0x0030U  /**< FIFO [7:0] */
+#define XUARTPS_BAUDDIV_OFFSET	0x0034U  /**< Baud Rate Divider [7:0] */
+#define XUARTPS_FLOWDEL_OFFSET	0x0038U  /**< Flow Delay [5:0] */
+#define XUARTPS_TXWM_OFFSET		0x0044U  /**< TX FIFO Trigger Level [5:0] */
+#define XUARTPS_RXBS_OFFSET		0x0048U  /**< RX FIFO Byte Status [11:0] */
+/* @} */
+
+/** @name Control Register
+ *
+ * The Control register (CR) controls the major functions of the device.
+ *
+ * Control Register Bit Definition
+ */
+
+#define XUARTPS_CR_STOPBRK	0x00000100U  /**< Stop transmission of break */
+#define XUARTPS_CR_STARTBRK	0x00000080U  /**< Set break */
+#define XUARTPS_CR_TORST	0x00000040U  /**< RX timeout counter restart */
+#define XUARTPS_CR_TX_DIS	0x00000020U  /**< TX disabled. */
+#define XUARTPS_CR_TX_EN	0x00000010U  /**< TX enabled */
+#define XUARTPS_CR_RX_DIS	0x00000008U  /**< RX disabled. */
+#define XUARTPS_CR_RX_EN	0x00000004U  /**< RX enabled */
+#define XUARTPS_CR_EN_DIS_MASK	0x0000003CU  /**< Enable/disable Mask */
+#define XUARTPS_CR_TXRST	0x00000002U  /**< TX logic reset */
+#define XUARTPS_CR_RXRST	0x00000001U  /**< RX logic reset */
+/* @}*/
+
+
+/** @name Mode Register
+ *
+ * The mode register (MR) defines the mode of transfer as well as the data
+ * format. If this register is modified during transmission or reception,
+ * data validity cannot be guaranteed.
+ *
+ * Mode Register Bit Definition
+ * @{
+ */
+#define XUARTPS_MR_CCLK				0x00000400U /**< Input clock selection */
+#define XUARTPS_MR_CHMODE_R_LOOP	0x00000300U /**< Remote loopback mode */
+#define XUARTPS_MR_CHMODE_L_LOOP	0x00000200U /**< Local loopback mode */
+#define XUARTPS_MR_CHMODE_ECHO		0x00000100U /**< Auto echo mode */
+#define XUARTPS_MR_CHMODE_NORM		0x00000000U /**< Normal mode */
+#define XUARTPS_MR_CHMODE_SHIFT				8U  /**< Mode shift */
+#define XUARTPS_MR_CHMODE_MASK		0x00000300U /**< Mode mask */
+#define XUARTPS_MR_STOPMODE_2_BIT	0x00000080U /**< 2 stop bits */
+#define XUARTPS_MR_STOPMODE_1_5_BIT	0x00000040U /**< 1.5 stop bits */
+#define XUARTPS_MR_STOPMODE_1_BIT	0x00000000U /**< 1 stop bit */
+#define XUARTPS_MR_STOPMODE_SHIFT			6U  /**< Stop bits shift */
+#define XUARTPS_MR_STOPMODE_MASK	0x000000A0U /**< Stop bits mask */
+#define XUARTPS_MR_PARITY_NONE		0x00000020U /**< No parity mode */
+#define XUARTPS_MR_PARITY_MARK		0x00000018U /**< Mark parity mode */
+#define XUARTPS_MR_PARITY_SPACE		0x00000010U /**< Space parity mode */
+#define XUARTPS_MR_PARITY_ODD		0x00000008U /**< Odd parity mode */
+#define XUARTPS_MR_PARITY_EVEN		0x00000000U /**< Even parity mode */
+#define XUARTPS_MR_PARITY_SHIFT				3U  /**< Parity setting shift */
+#define XUARTPS_MR_PARITY_MASK		0x00000038U /**< Parity mask */
+#define XUARTPS_MR_CHARLEN_6_BIT	0x00000006U /**< 6 bits data */
+#define XUARTPS_MR_CHARLEN_7_BIT	0x00000004U /**< 7 bits data */
+#define XUARTPS_MR_CHARLEN_8_BIT	0x00000000U /**< 8 bits data */
+#define XUARTPS_MR_CHARLEN_SHIFT			1U  /**< Data Length shift */
+#define XUARTPS_MR_CHARLEN_MASK		0x00000006U /**< Data length mask */
+#define XUARTPS_MR_CLKSEL			0x00000001U /**< Input clock selection */
+/* @} */
+
+
+/** @name Interrupt Registers
+ *
+ * Interrupt control logic uses the interrupt enable register (IER) and the
+ * interrupt disable register (IDR) to set the value of the bits in the
+ * interrupt mask register (IMR). The IMR determines whether to pass an
+ * interrupt to the interrupt status register (ISR).
+ * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
+ * interrupt. IMR and ISR are read only, and IER and IDR are write only.
+ * Reading either IER or IDR returns 0x00.
+ *
+ * All four registers have the same bit definitions.
+ *
+ * @{
+ */
+#define XUARTPS_IXR_RBRK	0x00002000U /**< Rx FIFO break detect interrupt */
+#define XUARTPS_IXR_TOVR	0x00001000U /**< Tx FIFO Overflow interrupt */
+#define XUARTPS_IXR_TNFUL	0x00000800U /**< Tx FIFO Nearly Full interrupt */
+#define XUARTPS_IXR_TTRIG	0x00000400U /**< Tx Trig interrupt */
+#define XUARTPS_IXR_DMS		0x00000200U /**< Modem status change interrupt */
+#define XUARTPS_IXR_TOUT	0x00000100U /**< Timeout error interrupt */
+#define XUARTPS_IXR_PARITY 	0x00000080U /**< Parity error interrupt */
+#define XUARTPS_IXR_FRAMING	0x00000040U /**< Framing error interrupt */
+#define XUARTPS_IXR_OVER	0x00000020U /**< Overrun error interrupt */
+#define XUARTPS_IXR_TXFULL 	0x00000010U /**< TX FIFO full interrupt. */
+#define XUARTPS_IXR_TXEMPTY	0x00000008U /**< TX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXFULL 	0x00000004U /**< RX FIFO full interrupt. */
+#define XUARTPS_IXR_RXEMPTY	0x00000002U /**< RX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXOVR  	0x00000001U /**< RX FIFO trigger interrupt. */
+#define XUARTPS_IXR_MASK	0x00003FFFU /**< Valid bit mask */
+/* @} */
+
+
+/** @name Baud Rate Generator Register
+ *
+ * The baud rate generator control register (BRGR) is a 16 bit register that
+ * controls the receiver bit sample clock and baud rate.
+ * Valid values are 1 - 65535.
+ *
+ * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
+ * in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDGEN_DISABLE		0x00000000U /**< Disable clock */
+#define XUARTPS_BAUDGEN_MASK		0x0000FFFFU /**< Valid bits mask */
+#define XUARTPS_BAUDGEN_RESET_VAL	0x0000028BU /**< Reset value */
+
+/** @name Baud Divisor Rate register
+ *
+ * The baud rate divider register (BDIV) controls how much the bit sample
+ * rate is divided by. It sets the baud rate.
+ * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
+ *
+ * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
+ * the MR_CCLK bit in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDDIV_MASK        0x000000FFU	/**< 8 bit baud divider mask */
+#define XUARTPS_BAUDDIV_RESET_VAL   0x0000000FU	/**< Reset value */
+/* @} */
+
+
+/** @name Receiver Timeout Register
+ *
+ * Use the receiver timeout register (RTR) to detect an idle condition on
+ * the receiver data line.
+ *
+ * @{
+ */
+#define XUARTPS_RXTOUT_DISABLE		0x00000000U  /**< Disable time out */
+#define XUARTPS_RXTOUT_MASK			0x000000FFU  /**< Valid bits mask */
+
+/** @name Receiver FIFO Trigger Level Register
+ *
+ * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
+ * which the RX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_RXWM_DISABLE	0x00000000U  /**< Disable RX trigger interrupt */
+#define XUARTPS_RXWM_MASK		0x0000003FU  /**< Valid bits mask */
+#define XUARTPS_RXWM_RESET_VAL	0x00000020U  /**< Reset value */
+/* @} */
+
+/** @name Transmit FIFO Trigger Level Register
+ *
+ * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
+ * which the TX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_TXWM_MASK		0x0000003FU  /**< Valid bits mask */
+#define XUARTPS_TXWM_RESET_VAL	0x00000020U  /**< Reset value */
+/* @} */
+
+/** @name Modem Control Register
+ *
+ * This register (MODEMCR) controls the interface with the modem or data set,
+ * or a peripheral device emulating a modem.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMCR_FCM	0x00000010U  /**< Flow control mode */
+#define XUARTPS_MODEMCR_RTS	0x00000002U  /**< Request to send */
+#define XUARTPS_MODEMCR_DTR	0x00000001U  /**< Data terminal ready */
+/* @} */
+
+/** @name Modem Status Register
+ *
+ * This register (MODEMSR) indicates the current state of the control lines
+ * from a modem, or another peripheral device, to the CPU. In addition, four
+ * bits of the modem status register provide change information. These bits
+ * are set to a logic 1 whenever a control input from the modem changes state.
+ *
+ * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
+ * status interrupt is generated and this is reflected in the modem status
+ * register.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMSR_FCMS	0x00000100U  /**< Flow control mode (FCMS) */
+#define XUARTPS_MODEMSR_DCD		0x00000080U  /**< Complement of DCD input */
+#define XUARTPS_MODEMSR_RI		0x00000040U  /**< Complement of RI input */
+#define XUARTPS_MODEMSR_DSR		0x00000020U  /**< Complement of DSR input */
+#define XUARTPS_MODEMSR_CTS		0x00000010U  /**< Complement of CTS input */
+#define XUARTPS_MODEMSR_DDCD	0x00000008U  /**< Delta DCD indicator */
+#define XUARTPS_MODEMSR_TERI  0x00000004U  /**< Trailing Edge Ring Indicator */
+#define XUARTPS_MODEMSR_DDSR	0x00000002U  /**< Change of DSR */
+#define XUARTPS_MODEMSR_DCTS	0x00000001U  /**< Change of CTS */
+/* @} */
+
+/** @name Channel Status Register
+ *
+ * The channel status register (CSR) is provided to enable the control logic
+ * to monitor the status of bits in the channel interrupt status register,
+ * even if these are masked out by the interrupt mask register.
+ *
+ * @{
+ */
+#define XUARTPS_SR_TNFUL	0x00004000U /**< TX FIFO Nearly Full Status */
+#define XUARTPS_SR_TTRIG	0x00002000U /**< TX FIFO Trigger Status */
+#define XUARTPS_SR_FLOWDEL	0x00001000U /**< RX FIFO fill over flow delay */
+#define XUARTPS_SR_TACTIVE	0x00000800U /**< TX active */
+#define XUARTPS_SR_RACTIVE	0x00000400U /**< RX active */
+#define XUARTPS_SR_TXFULL	0x00000010U /**< TX FIFO full */
+#define XUARTPS_SR_TXEMPTY	0x00000008U /**< TX FIFO empty */
+#define XUARTPS_SR_RXFULL	0x00000004U /**< RX FIFO full */
+#define XUARTPS_SR_RXEMPTY	0x00000002U /**< RX FIFO empty */
+#define XUARTPS_SR_RXOVR	0x00000001U /**< RX FIFO fill over trigger */
+/* @} */
+
+/** @name Flow Delay Register
+ *
+ * Operation of the flow delay register (FLOWDEL) is very similar to the
+ * receive FIFO trigger register. An internal trigger signal activates when the
+ * FIFO is filled to the level set by this register. This trigger will not
+ * cause an interrupt, although it can be read through the channel status
+ * register. In hardware flow control mode, RTS is deactivated when the trigger
+ * becomes active. RTS only resets when the FIFO level is four less than the
+ * level of the flow delay trigger and the flow delay trigger is not activated.
+ * A value less than 4 disables the flow delay.
+ * @{
+ */
+#define XUARTPS_FLOWDEL_MASK	XUARTPS_RXWM_MASK	/**< Valid bit mask */
+/* @} */
+
+/** @name Receiver FIFO Byte Status Register
+ *
+ * The Receiver FIFO Status register is used to have a continuous
+ * monitoring of the raw unmasked byte status information. The register
+ * contains frame, parity and break status information for the top
+ * four bytes in the RX FIFO.
+ *
+ * Receiver FIFO Byte Status Register Bit Definition
+ * @{
+ */
+#define XUARTPS_RXBS_BYTE3_BRKE		0x00000800U /**< Byte3 Break Error */
+#define XUARTPS_RXBS_BYTE3_FRME		0x00000400U /**< Byte3 Frame Error */
+#define XUARTPS_RXBS_BYTE3_PARE		0x00000200U /**< Byte3 Parity Error */
+#define XUARTPS_RXBS_BYTE2_BRKE		0x00000100U /**< Byte2 Break Error */
+#define XUARTPS_RXBS_BYTE2_FRME		0x00000080U /**< Byte2 Frame Error */
+#define XUARTPS_RXBS_BYTE2_PARE		0x00000040U /**< Byte2 Parity Error */
+#define XUARTPS_RXBS_BYTE1_BRKE		0x00000020U /**< Byte1 Break Error */
+#define XUARTPS_RXBS_BYTE1_FRME		0x00000010U /**< Byte1 Frame Error */
+#define XUARTPS_RXBS_BYTE1_PARE		0x00000008U /**< Byte1 Parity Error */
+#define XUARTPS_RXBS_BYTE0_BRKE		0x00000004U /**< Byte0 Break Error */
+#define XUARTPS_RXBS_BYTE0_FRME		0x00000002U /**< Byte0 Frame Error */
+#define XUARTPS_RXBS_BYTE0_PARE		0x00000001U /**< Byte0 Parity Error */
+#define XUARTPS_RXBS_MASK		0x00000007U /**< 3 bit RX byte status mask */
+/* @} */
+
+
+/*
+ * Defines for backwards compatabilty, will be removed
+ * in the next version of the driver
+ */
+#define XUARTPS_MEDEMSR_DCDX  XUARTPS_MODEMSR_DDCD
+#define XUARTPS_MEDEMSR_RIX   XUARTPS_MODEMSR_TERI
+#define XUARTPS_MEDEMSR_DSRX  XUARTPS_MODEMSR_DDSR
+#define	XUARTPS_MEDEMSR_CTSX  XUARTPS_MODEMSR_DCTS
+
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+* Read a UART register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the base address of the
+*		device.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset)
+*
+******************************************************************************/
+#define XUartPs_ReadReg(BaseAddress, RegOffset) \
+	Xil_In32((BaseAddress) + (u32)(RegOffset))
+
+/***************************************************************************/
+/**
+* Write a UART register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the base address of the
+*		device.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XUartPs_WriteReg(u32 BaseAddress, int RegOffset,
+*						   u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+	Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Determine if there is receive data in the receiver and/or FIFO.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	TRUE if there is receive data, FALSE otherwise.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_IsReceiveData(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsReceiveData(BaseAddress)			 \
+	!((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & 	\
+	(u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY)
+
+/****************************************************************************/
+/**
+* Determine if a byte of data can be sent with the transmitter.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	TRUE if the TX FIFO is full, FALSE if a byte can be put in the
+*		FIFO.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_IsTransmitFull(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitFull(BaseAddress)			 \
+	((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & 	\
+	 (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL)
+
+/************************** Function Prototypes ******************************/
+
+void XUartPs_SendByte(u32 BaseAddress, u8 Data);
+
+u8 XUartPs_RecvByte(u32 BaseAddress);
+
+void XUartPs_ResetHw(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xusbps.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xusbps.h
new file mode 100644
index 0000000000000000000000000000000000000000..4a4492cdc0af2d44d7063f4e04986b750d9a54c8
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xusbps.h
@@ -0,0 +1,1096 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal 
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xusbps.h
+* @addtogroup usbps_v2_2
+* @{
+* @details
+ *
+ * This file contains the implementation of the XUsbPs driver. It is the
+ * driver for an USB controller in DEVICE or HOST mode.
+ *
+ * <h2>Introduction</h2>
+ *
+ * The Spartan-3AF Embedded Peripheral Block contains a USB controller for
+ * communication with serial peripherals or hosts. The USB controller supports
+ * Host, Device and On the Go (OTG) applications.
+ *
+ * <h2>USB Controller Features</h2>
+ *
+ * - Supports Low Speed USB 1.1 (1.5Mbps), Full Speed USB 1.1 (12Mbps), and
+ *   High Speed USB 2.0 (480Mbps) data speeds
+ * - Supports Device, Host and OTG operational modes
+ * - ULPI transceiver interface for USB 2.0 operation
+ * - Integrated USB Full and Low speed serial transceiver interfaces for lowest
+ *   cost connections
+ *
+ * <h2>Initialization & Configuration</h2>
+ *
+ * The configuration of the USB driver happens in multiple stages:
+ *
+ * - (a) Configuration of the basic parameters:
+ *   In this stage the basic parameters for the driver are configured,
+ *   including the base address and the controller ID.
+ *
+ * - (b) Configuration of the DEVICE endpoints (if applicable):
+ *   If DEVICE mode is desired, the endpoints of the controller need to be
+ *   configured using the XUsbPs_DeviceConfig data structure. Once the
+ *   endpoint configuration is set up in the data structure, The user then
+ *   needs to allocate the required amount of DMAable memory and
+ *   finalize the configuration of the XUsbPs_DeviceConfig data structure,
+ *   e.g. setting the DMAMemVirt and DMAMemPhys members.
+ *
+ * - (c) Configuration of the DEVICE modes:
+ *   In the second stage the parameters for DEVICE are configured.
+ *   The caller only needs to configure the modes that are
+ *   actually used. Configuration is done with the:
+ *   	XUsbPs_ConfigureDevice()
+ * Configuration parameters are defined and passed
+ *   into these functions using the:
+ *      XUsbPs_DeviceConfig data structures.
+ *
+ *
+ * <h2>USB Device Endpoints</h2>
+ *
+ * The USB core supports up to 4 endpoints. Each endpoint has two directions,
+ * an OUT (RX) and an IN (TX) direction. Note that the direction is viewed from
+ * the host's perspective. Endpoint 0 defaults to be the control endpoint and
+ * does not need to be set up. Other endpoints need to be configured and set up
+ * depending on the application. Only endpoints that are actuelly used by the
+ * application need to be initialized.
+ * See the example code (xusbps_intr_example.c) for more information.
+ *
+ *
+ * <h2>Interrupt Handling</h2>
+ *
+ * The USB core uses one interrupt line to report interrupts to the CPU.
+ * Interrupts are handled by the driver's interrupt handler function
+ * XUsbPs_IntrHandler().
+ * It has to be registered with the OS's interrupt subsystem. The driver's
+ * interrupt handler divides incoming interrupts into two categories:
+ *
+ *  - General device interrupts
+ *  - Endopint related interrupts
+ *
+ * The user (typically the adapter layer) can register general interrupt
+ * handler fucntions and endpoint specific interrupt handler functions with the
+ * driver to receive those interrupts by calling the
+ *    XUsbPs_IntrSetHandler()
+ * and
+ *    XUsbPs_EpSetHandler()
+ * functions respectively. Calling these functions with a NULL pointer as the
+ * argument for the function pointer will "clear" the handler function.
+ *
+ * The user can register one handler function for the generic interrupts and
+ * two handler functions for each endpoint, one for the RX (OUT) and one for
+ * the TX (IN) direction. For some applications it may be useful to register a
+ * single endpoint handler function for muliple endpoints/directions.
+ *
+ * When a callback function is called by the driver, parameters identifying the
+ * type of the interrupt will be passed into the handler functions. For general
+ * interrupts the interrupt mask will be passed into the handler function. For
+ * endpoint interrupts the parameters include the number of the endpoint, the
+ * direction (OUT/IN) and the type of the interrupt.
+ *
+ *
+ * <h2>Data buffer handling</h2>
+ *
+ * Data buffers are sent to and received from endpoint using the
+ *    XUsbPs_EpBufferSend(), XUsbPs_EpBufferSendWithZLT()
+ * and
+ *    XUsbPs_EpBufferReceive()
+ * functions.
+ *
+ * User data buffer size is limited to 16 Kbytes. If the user wants to send a
+ * data buffer that is bigger than this limit it needs to break down the data
+ * buffer into multiple fragments and send the fragments individually.
+ *
+ * From the controller perspective Data buffers can be aligned at any boundary.
+ * if the buffers are from cache region then the buffer and buffer size should
+ * be aligned to cache line aligned
+ *
+ *
+ * <h3>Zero copy</h3>
+ *
+ * The driver uses a zero copy mechanism which imposes certain restrictions to
+ * the way the user can handle the data buffers.
+ *
+ * One restriction is that the user needs to release a buffer after it is done
+ * processing the data in the buffer.
+ *
+ * Similarly, when the user sends a data buffer it MUST not re-use the buffer
+ * until it is notified by the driver that the buffer has been transmitted. The
+ * driver will notify the user via the registered endpoint interrupt handling
+ * function by sending a XUSBPS_EP_EVENT_DATA_TX event.
+ *
+ *
+ * <h2>DMA</h2>
+ *
+ * The driver uses DMA internally to move data from/to memory. This behaviour
+ * is transparent to the user. Keeping the DMA handling hidden from the user
+ * has the advantage that the same API can be used with USB cores that do not
+ * support DMA.
+ *
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- ----------------------------------------------------------
+ * 1.00a wgr  10/10/10 First release
+ * 1.02a wgr  05/16/12 Removed comments as they are showing up in SDK
+ *		       Tabs for CR 657898
+ * 1.03a nm   09/21/12 Fixed CR#678977. Added proper sequence for setup packet
+ *                    handling.
+ * 1.04a nm   10/23/12 Fixed CR# 679106.
+ *	      11/02/12 Fixed CR# 683931. Mult bits are set properly in dQH.
+ * 2.00a kpc 04/03/14 Fixed CR#777763. Corrected the setup tripwire macro val.
+ * 2.1   kpc 04/28/14 Removed unused function prototypes
+ * 2.2   kpc 08/23/14 Exported XUsbPs_DeviceReset API as global for calling in
+ *                    code coverage tests.
+ * 2.3   kpc 02/19/14 Fixed CR#873972, CR#873974. Corrected the logic for proper
+ *                    moving of dTD Head/Tail Pointers. Invalidate the cache
+ *                    after buffer receive in Endpoint Buffer Handler.
+ * 2.4   sg  04/26/16 Fixed CR#949693, Corrected the logic for EP flush
+ *       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+ *                    generation.
+ * </pre>
+ *
+ ******************************************************************************/
+
+#ifndef XUSBPS_H
+#define XUSBPS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xusbps_hw.h"
+#include "xil_types.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+/**
+ * @name System hang prevention Timeout counter value.
+ *
+ * This value is used throughout the code to initialize a Timeout counter that
+ * is used when hard polling a register. The ides is to initialize the Timeout
+ * counter to a value that is longer than any expected Timeout but short enough
+ * so the system will continue to work and report an error while the user is
+ * still paying attention. A reasonable Timeout time would be about 10 seconds.
+ * The XUSBPS_TIMEOUT_COUNTER value should be chosen so a polling loop would
+ * run about 10 seconds before a Timeout is detected. For example:
+ *
+ * 	int Timeout = XUSBPS_TIMEOUT_COUNTER;
+ *	while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ *				XUSBPS_CMD_OFFSET) &
+ *				XUSBPS_CMD_RST_MASK) && --Timeout) {
+ *		;
+ *	}
+ *	if (0 == Timeout) {
+ *		return XST_FAILURE;
+ *	}
+ *
+ */
+#define XUSBPS_TIMEOUT_COUNTER		1000000
+
+
+/**
+ * @name Endpoint Direction (bitmask)
+ * Definitions to be used with Endpoint related function that require a
+ * 'Direction' parameter.
+ *
+ * NOTE:
+ *   The direction is always defined from the perspective of the HOST! This
+ *   means that an IN endpoint on the controller is used for sending data while
+ *   the OUT endpoint on the controller is used for receiving data.
+ * @{
+ */
+#define XUSBPS_EP_DIRECTION_IN		0x01 /**< Endpoint direction IN. */
+#define XUSBPS_EP_DIRECTION_OUT		0x02 /**< Endpoint direction OUT. */
+/* @} */
+
+
+/**
+ * @name Endpoint Type
+ * Definitions to be used with Endpoint related functions that require a 'Type'
+ * parameter.
+ * @{
+ */
+#define XUSBPS_EP_TYPE_NONE		0 /**< Endpoint is not used. */
+#define XUSBPS_EP_TYPE_CONTROL		1 /**< Endpoint for Control Transfers */
+#define XUSBPS_EP_TYPE_ISOCHRONOUS 	2 /**< Endpoint for isochronous data */
+#define XUSBPS_EP_TYPE_BULK		3 /**< Endpoint for BULK Transfers. */
+#define XUSBPS_EP_TYPE_INTERRUPT	4 /**< Endpoint for interrupt Transfers */
+/* @} */
+
+/**
+ * Endpoint Max Packet Length in DeviceConfig is a coded value, ch9.6.6.
+ *
+ * @{
+ */
+#define ENDPOINT_MAXP_LENGTH		0x400
+#define ENDPOINT_MAXP_MULT_MASK		0xC00
+#define ENDPOINT_MAXP_MULT_SHIFT	10
+/* @} */
+
+/**
+ * @name Field names for status retrieval
+ * Definitions for the XUsbPs_GetStatus() function call 'StatusType'
+ * parameter.
+ * @{
+ */
+#define XUSBPS_EP_STS_ADDRESS		1 /**< Address of controller. */
+#define XUSBPS_EP_STS_CONTROLLER_STATE	2 /**< Current controller state. */
+/* @} */
+
+
+
+/**
+ * @name USB Default alternate setting
+ *
+ * @{
+ */
+#define XUSBPS_DEFAULT_ALT_SETTING	0 /**< The default alternate setting is 0 */
+/* @} */
+
+/**
+ * @name Endpoint event types
+ * Definitions that are used to identify events that occur on endpoints. Passed
+ * to the endpoint event handler functions registered with
+ * XUsbPs_EpSetHandler().
+ * @{
+ */
+#define XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED	0x01
+			/**< Setup data has been received on the enpoint. */
+#define XUSBPS_EP_EVENT_DATA_RX		0x02
+			/**< Data frame has been received on the endpoint. */
+#define XUSBPS_EP_EVENT_DATA_TX		0x03
+			/**< Data frame has been sent on the endpoint. */
+/* @} */
+
+
+/*
+ * Maximum packet size for endpoint, 1024
+ * @{
+ */
+#define XUSBPS_MAX_PACKET_SIZE		1024
+				/**< Maximum value can be put into the queue head */
+/* @} */
+/**************************** Type Definitions *******************************/
+
+/******************************************************************************
+ * This data type defines the callback function to be used for Endpoint
+ * handlers.
+ *
+ * @param	CallBackRef is the Callback reference passed in by the upper
+ *		layer when setting the handler, and is passed back to the upper
+ *		layer when the handler is called.
+ * @param	EpNum is the Number of the endpoint that caused the event.
+ * @param	EventType is the type of the event that occured on the endpoint.
+ * @param	Data is a pointer to user data pointer specified when callback
+ *		was registered.
+ */
+typedef void (*XUsbPs_EpHandlerFunc)(void *CallBackRef,
+				      u8 EpNum, u8 EventType, void *Data);
+
+
+/******************************************************************************
+ * This data type defines the callback function to be used for the general
+ * interrupt handler.
+ *
+ * @param	CallBackRef is the Callback reference passed in by the upper
+ *		layer when setting the handler, and is passed back to the upper
+ *		layer when the handler is called.
+ * @param	IrqMask is the Content of the interrupt status register. This
+ *		value can be used by the callback function to distinguish the
+ *		individual interrupt types.
+ */
+typedef void (*XUsbPs_IntrHandlerFunc)(void *CallBackRef, u32 IrqMask);
+
+
+/******************************************************************************/
+
+/* The following type definitions are used for referencing Queue Heads and
+ * Transfer Descriptors. The structures themselves are not used, however, the
+ * types are used in the API to avoid using (void *) pointers.
+ */
+typedef u8	XUsbPs_dQH[XUSBPS_dQH_ALIGN];
+typedef u8	XUsbPs_dTD[XUSBPS_dTD_ALIGN];
+
+
+/**
+ * The following data structures are used internally by the L0/L1 driver.
+ * Their contents MUST NOT be changed by the upper layers.
+ */
+
+/**
+ * The following data structure represents OUT endpoint.
+ */
+typedef struct {
+	XUsbPs_dQH	*dQH;
+		/**< Pointer to the Queue Head structure of the endpoint. */
+
+	XUsbPs_dTD	*dTDs;
+		/**< Pointer to the first dTD of the dTD list for this
+		 * endpoint. */
+
+	XUsbPs_dTD	*dTDCurr;
+		/**< Buffer to the currently processed descriptor. */
+
+	u8	*dTDBufs;
+		/**< Pointer to the first buffer of the buffer list for this
+		 * endpoint. */
+
+	XUsbPs_EpHandlerFunc	HandlerFunc;
+		/**< Handler function for this endpoint. */
+	void			*HandlerRef;
+		/**< User data reference for the handler. */
+} XUsbPs_EpOut;
+
+
+/**
+ * The following data structure represents IN endpoint.
+ */
+typedef struct {
+	XUsbPs_dQH	*dQH;
+		/**< Pointer to the Queue Head structure of the endpoint. */
+
+	XUsbPs_dTD	*dTDs;
+		/**< List of pointers to the Transfer Descriptors of the
+		 * endpoint. */
+
+	XUsbPs_dTD	*dTDHead;
+		/**< Buffer to the next available descriptor in the list. */
+
+	XUsbPs_dTD	*dTDTail;
+		/**< Buffer to the last unsent descriptor in the list*/
+
+	XUsbPs_EpHandlerFunc	HandlerFunc;
+		/**< Handler function for this endpoint. */
+	void			*HandlerRef;
+		/**< User data reference for the handler. */
+} XUsbPs_EpIn;
+
+
+/**
+ * The following data structure represents an endpoint used internally
+ * by the L0/L1 driver.
+ */
+typedef struct {
+	/* Each endpoint has an OUT and an IN component.
+	 */
+	XUsbPs_EpOut	Out;	/**< OUT endpoint structure */
+	XUsbPs_EpIn	In;	/**< IN endpoint structure */
+} XUsbPs_Endpoint;
+
+
+
+/**
+ * The following structure is used by the user to receive Setup Data from an
+ * endpoint. Using this structure simplifies the process of interpreting the
+ * setup data in the core's data fields.
+ *
+ * The naming scheme for the members of this structure is different from the
+ * naming scheme found elsewhere in the code. The members of this structure are
+ * defined in the Chapter 9 USB reference guide. Using this naming scheme makes
+ * it easier for people familiar with the standard to read the code.
+ */
+typedef struct {
+	u8  bmRequestType;	/**< bmRequestType in setup data */
+	u8  bRequest;		/**< bRequest in setup data */
+	u16 wValue;		/**< wValue in setup data */
+	u16 wIndex;		/**< wIndex in setup data */
+	u16 wLength;		/**< wLength in setup data */
+}
+XUsbPs_SetupData;
+
+
+/**
+ * Data structures used to configure endpoints.
+ */
+typedef struct {
+	u32	Type;
+		/**< Endpoint type:
+			- XUSBPS_EP_TYPE_CONTROL
+			- XUSBPS_EP_TYPE_ISOCHRONOUS
+			- XUSBPS_EP_TYPE_BULK
+			- XUSBPS_EP_TYPE_INTERRUPT */
+
+	u32	NumBufs;
+		/**< Number of buffers to be handled by this endpoint. */
+	u32	BufSize;
+		/**< Buffer size. Only relevant for OUT (receive) Endpoints. */
+
+	u16	MaxPacketSize;
+		/**< Maximum packet size for this endpoint. This number will
+		 * define the maximum number of bytes sent on the wire per
+		 * transaction. Range: 0..1024 */
+} XUsbPs_EpSetup;
+
+
+/**
+ * Endpoint configuration structure.
+ */
+typedef struct {
+	XUsbPs_EpSetup		Out; /**< OUT component of endpoint. */
+	XUsbPs_EpSetup		In;  /**< IN component of endpoint. */
+} XUsbPs_EpConfig;
+
+
+/**
+ * The XUsbPs_DeviceConfig structure contains the configuration information to
+ * configure the USB controller for DEVICE mode. This data structure is used
+ * with the XUsbPs_ConfigureDevice() function call.
+ */
+typedef struct {
+	u8  NumEndpoints;	/**< Number of Endpoints for the controller.
+				  This number depends on the runtime
+				  configuration of driver. The driver may
+				  configure fewer endpoints than are available
+				  in the core. */
+
+	XUsbPs_EpConfig	EpCfg[XUSBPS_MAX_ENDPOINTS];
+				/**< List of endpoint configurations. */
+
+
+	u32 DMAMemPhys;		/**< Physical base address of DMAable memory
+				  allocated for the driver. */
+
+	/* The following members are used internally by the L0/L1 driver.  They
+	 * MUST NOT be accesses and/or modified in any way by the upper layers.
+	 *
+	 * The reason for having these members is that we generally try to
+	 * avoid allocating memory in the L0/L1 driver as we want to be OS
+	 * independent. In order to avoid allocating memory for this data
+	 * structure wihin L0/L1 we put it into the XUsbPs_DeviceConfig
+	 * structure which is allocated by the caller.
+	 */
+	XUsbPs_Endpoint	Ep[XUSBPS_MAX_ENDPOINTS];
+				/**< List of endpoint metadata structures. */
+
+	u32 PhysAligned;	/**< 64 byte aligned base address of the DMA
+				   memory block. Will be computed and set by
+				   the L0/L1 driver. */
+} XUsbPs_DeviceConfig;
+
+
+/**
+ * The XUsbPs_Config structure contains configuration information for the USB
+ * controller.
+ *
+ * This structure only contains the basic configuration for the controller. The
+ * caller also needs to initialize the controller for the DEVICE mode
+ * using the XUsbPs_DeviceConfig data structures with the
+ * XUsbPs_ConfigureDevice() function call
+ */
+typedef struct {
+	u16 DeviceID;		/**< Unique ID of controller. */
+	u32 BaseAddress;	/**< Core register base address. */
+} XUsbPs_Config;
+
+
+/**
+ * The XUsbPs driver instance data. The user is required to allocate a
+ * variable of this type for every USB controller in the system. A pointer to a
+ * variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XUsbPs_Config Config;	/**< Configuration structure */
+
+	int CurrentAltSetting;	/**< Current alternative setting of interface */
+
+	void *UserDataPtr;	/**< Data pointer to be used by upper layers to
+				  store application dependent data structures.
+				  The upper layers are responsible to allocated
+				  and free the memory. The driver will not
+				  mofidy this data pointer. */
+
+	/**
+	 * The following structures hold the configuration for DEVICE mode
+	 * of the controller. They are initialized using the
+	 * XUsbPs_ConfigureDevice() function call.
+	 */
+	XUsbPs_DeviceConfig	DeviceConfig;
+				/**< Configuration for the DEVICE mode. */
+
+	XUsbPs_IntrHandlerFunc	HandlerFunc;
+		/**< Handler function for the controller. */
+	void			*HandlerRef;
+		/**< User data reference for the handler. */
+	u32			HandlerMask;
+		/**< User interrupt mask. Defines which interrupts will cause
+		 * the callback to be called. */
+} XUsbPs;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/******************************************************************************
+ *
+ * USB CONTROLLER RELATED MACROS
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ * This macro returns the current frame number.
+ *
+ * @param	InstancePtr is a pointer to the XUsbPs instance of the
+ *		controller.
+ *
+ * @return	The current frame number.
+ *
+ * @note	C-style signature:
+ *		u32 XUsbPs_GetFrameNum(const XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_GetFrameNum(InstancePtr) \
+	XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, XUSBPS_FRAME_OFFSET)
+
+
+/*****************************************************************************/
+/**
+ * This macro starts the USB engine.
+ *
+ * @param	InstancePtr is a pointer to the XUsbPs instance of the
+ *		controller.
+ *
+ * @note	C-style signature:
+ * 		void XUsbPs_Start(XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_Start(InstancePtr) \
+	XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
+
+
+/*****************************************************************************/
+/**
+ * This macro stops the USB engine.
+ *
+ * @param	InstancePtr is a pointer to the XUsbPs instance of the
+ *		controller.
+ *
+ * @note	C-style signature:
+ * 		void XUsbPs_Stop(XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_Stop(InstancePtr) \
+	XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
+
+
+/*****************************************************************************/
+/**
+ * This macro forces the USB engine to be in Full Speed (FS) mode.
+ *
+ * @param	InstancePtr is a pointer to the XUsbPs instance of the
+ *		controller.
+ *
+ * @note	C-style signature:
+ * 		void XUsbPs_ForceFS(XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_ForceFS(InstancePtr)					\
+	XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET,		\
+ 		XUSBPS_PORTSCR_PFSC_MASK)
+
+
+/*****************************************************************************/
+/**
+ * This macro starts the USB Timer 0, with repeat option for period of
+ * one second.
+ *
+ * @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+ * @param	Interval is the interval for Timer0 to generate an interrupt
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_StartTimer0(XUsbPs *InstancePtr, u32 Interval)
+ *
+ ******************************************************************************/
+#define XUsbPs_StartTimer0(InstancePtr, Interval) 			\
+{									\
+	XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, 		\
+			XUSBPS_TIMER0_LD_OFFSET, (Interval));		\
+	XUsbPs_SetBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET,		\
+			XUSBPS_TIMER_RUN_MASK |			\
+			XUSBPS_TIMER_RESET_MASK |			\
+			XUSBPS_TIMER_REPEAT_MASK);			\
+}									\
+
+
+/*****************************************************************************/
+/**
+* This macro stops Timer 0.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note		C-style signature:
+*		void XUsbPs_StopTimer0(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_StopTimer0(InstancePtr) \
+	XUsbPs_ClrBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET,		\
+		XUSBPS_TIMER_RUN_MASK)
+
+
+/*****************************************************************************/
+/**
+* This macro reads Timer 0.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note		C-style signature:
+*		void XUsbPs_ReadTimer0(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_ReadTimer0(InstancePtr) 				\
+	XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress,		\
+			XUSBPS_TIMER0_CTL_OFFSET) & 			\
+					XUSBPS_TIMER_COUNTER_MASK
+
+
+/*****************************************************************************/
+/**
+* This macro force remote wakeup on host
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note		C-style signature:
+*  		void XUsbPs_RemoteWakeup(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_RemoteWakeup(InstancePtr) \
+	XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET,		 \
+			XUSBPS_PORTSCR_FPR_MASK)
+
+
+/******************************************************************************
+ *
+ * ENDPOINT RELATED MACROS
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+* This macro enables the given endpoint for the given direction.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	EpNum is number of the endpoint to enable.
+* @param	Dir is direction of the endpoint (bitfield):
+* 			- XUSBPS_EP_DIRECTION_OUT
+* 			- XUSBPS_EP_DIRECTION_IN
+*
+* @note		C-style signature:
+* 		void XUsbPs_EpEnable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpEnable(InstancePtr, EpNum, Dir) \
+	XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum),	 \
+	((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
+	((Dir) & XUSBPS_EP_DIRECTION_IN  ? XUSBPS_EPCR_TXE_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro disables the given endpoint for the given direction.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	EpNum is the number of the endpoint to disable.
+* @param	Dir is the direction of the endpoint (bitfield):
+* 		- XUSBPS_EP_DIRECTION_OUT
+* 		- XUSBPS_EP_DIRECTION_IN
+*
+* @note		C-style signature:
+* 		void XUsbPs_EpDisable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpDisable(InstancePtr, EpNum, Dir) \
+	XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum),		 \
+		((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
+		((Dir) & XUSBPS_EP_DIRECTION_IN  ? XUSBPS_EPCR_TXE_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro stalls the given endpoint for the given direction, and flush
+* the buffers.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	EpNum is number of the endpoint to stall.
+* @param	Dir is the direction of the endpoint (bitfield):
+* 			- XUSBPS_EP_DIRECTION_OUT
+* 			- XUSBPS_EP_DIRECTION_IN
+*
+* @note		C-style signature:
+*		void XUsbPs_EpStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpStall(InstancePtr, EpNum, Dir) \
+	XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum),	 \
+	((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
+	((Dir) & XUSBPS_EP_DIRECTION_IN  ? XUSBPS_EPCR_TXS_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro unstalls the given endpoint for the given direction.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	EpNum is the Number of the endpoint to unstall.
+* @param	Dir is the Direction of the endpoint (bitfield):
+* 		- XUSBPS_EP_DIRECTION_OUT
+* 		- XUSBPS_EP_DIRECTION_IN
+*
+* @note		C-style signature:
+* 		void XUsbPs_EpUnStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpUnStall(InstancePtr, EpNum, Dir) \
+	XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum),	 \
+	((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
+	((Dir) & XUSBPS_EP_DIRECTION_IN  ? XUSBPS_EPCR_TXS_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro flush an endpoint upon interface disable
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	EpNum is the number of the endpoint to flush.
+* @param	Dir is the direction of the endpoint (bitfield):
+* 			- XUSBPS_EP_DIRECTION_OUT
+* 			- XUSBPS_EP_DIRECTION_IN
+*
+* @note		C-style signature:
+*		void XUsbPs_EpFlush(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpFlush(InstancePtr, EpNum, Dir) \
+	XUsbPs_SetBits(InstancePtr, XUSBPS_EPFLUSH_OFFSET,	\
+		1 << (EpNum + ((Dir) & XUSBPS_EP_DIRECTION_OUT ?		\
+			XUSBPS_EPFLUSH_RX_SHIFT:XUSBPS_EPFLUSH_TX_SHIFT))) \
+
+/*****************************************************************************/
+/**
+* This macro enables the interrupts defined by the bit mask.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	IntrMask is the Bit mask of interrupts to be enabled.
+*
+* @note		C-style signature:
+*		void XUsbPs_IntrEnable(XUsbPs *InstancePtr, u32 IntrMask)
+*
+******************************************************************************/
+#define XUsbPs_IntrEnable(InstancePtr, IntrMask)	\
+		XUsbPs_SetBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
+
+
+/*****************************************************************************/
+/**
+* This function disables the interrupts defined by the bit mask.
+*
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	IntrMask is a Bit mask of interrupts to be disabled.
+*
+* @note		C-style signature:
+* 		void XUsbPs_IntrDisable(XUsbPs *InstancePtr, u32 IntrMask)
+*
+******************************************************************************/
+#define XUsbPs_IntrDisable(InstancePtr, IntrMask)	\
+		XUsbPs_ClrBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
+
+
+/*****************************************************************************/
+/**
+* This macro enables the endpoint NAK interrupts defined by the bit mask.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	NakIntrMask is the Bit mask of endpoint NAK interrupts to be
+*		enabled.
+* @note		C-style signature:
+* 		void XUsbPs_NakIntrEnable(XUsbPs *InstancePtr, u32 NakIntrMask)
+*
+******************************************************************************/
+#define XUsbPs_NakIntrEnable(InstancePtr, NakIntrMask)	\
+	XUsbPs_SetBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
+
+
+/*****************************************************************************/
+/**
+* This macro disables the endpoint NAK interrupts defined by the bit mask.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	NakIntrMask is a Bit mask of endpoint NAK interrupts to be
+*		disabled.
+*
+* @note
+* 	C-style signature:
+* 	void XUsbPs_NakIntrDisable(XUsbPs *InstancePtr, u32 NakIntrMask)
+*
+******************************************************************************/
+#define XUsbPs_NakIntrDisable(InstancePtr, NakIntrMask)	\
+	XUsbPs_ClrBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
+
+
+/*****************************************************************************/
+/**
+* This function clears the endpoint NAK interrupts status defined by the
+* bit mask.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	NakIntrMask is the Bit mask of endpoint NAK interrupts to be cleared.
+*
+* @note		C-style signature:
+* 		void XUsbPs_NakIntrClear(XUsbPs *InstancePtr, u32 NakIntrMask)
+*
+******************************************************************************/
+#define XUsbPs_NakIntrClear(InstancePtr, NakIntrMask)			\
+	XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress,		\
+				XUSBPS_EPNAKISR_OFFSET, NakIntrMask)
+
+
+
+/*****************************************************************************/
+/**
+* This macro sets the Interrupt Threshold value in the control register
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	Threshold is the Interrupt threshold to be set.
+* 		Allowed values:
+*			- XUSBPS_CMD_ITHRESHOLD_0 - Immediate interrupt
+*			- XUSBPS_CMD_ITHRESHOLD_1 - 1 Frame
+*			- XUSBPS_CMD_ITHRESHOLD_2 - 2 Frames
+*			- XUSBPS_CMD_ITHRESHOLD_4 - 4 Frames
+*			- XUSBPS_CMD_ITHRESHOLD_8 - 8 Frames
+*			- XUSBPS_CMD_ITHRESHOLD_16 - 16 Frames
+*			- XUSBPS_CMD_ITHRESHOLD_32 - 32 Frames
+*			- XUSBPS_CMD_ITHRESHOLD_64 - 64 Frames
+*
+* @note
+* 	C-style signature:
+*	void XUsbPs_SetIntrThreshold(XUsbPs *InstancePtr, u8 Threshold)
+*
+******************************************************************************/
+#define XUsbPs_SetIntrThreshold(InstancePtr, Threshold)		\
+		XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress,	\
+					XUSBPS_CMD_OFFSET, (Threshold))\
+
+
+/*****************************************************************************/
+/**
+* This macro sets the Tripwire bit in the USB command register.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note		C-style signature:
+*		void XUsbPs_SetTripwire(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_SetSetupTripwire(InstancePtr)				\
+		XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET,	\
+				XUSBPS_CMD_SUTW_MASK)
+
+
+/*****************************************************************************/
+/**
+* This macro clears the Tripwire bit in the USB command register.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note		C-style signature:
+*		void XUsbPs_ClrTripwire(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_ClrSetupTripwire(InstancePtr)				\
+		XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET,	\
+				XUSBPS_CMD_SUTW_MASK)
+
+
+/*****************************************************************************/
+/**
+* This macro checks if the Tripwire bit in the USB command register is set.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @return
+* 		- TRUE: The tripwire bit is still set.
+* 		- FALSE: The tripwire bit has been cleared.
+*
+* @note		C-style signature:
+*		int XUsbPs_TripwireIsSet(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_SetupTripwireIsSet(InstancePtr)				\
+		(XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, 	\
+				XUSBPS_CMD_OFFSET) &			\
+				XUSBPS_CMD_SUTW_MASK ? TRUE : FALSE)
+
+
+/******************************************************************************
+*
+* GENERAL REGISTER / BIT MANIPULATION MACROS
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* This macro sets the given bit mask in the register.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	RegOffset is the register offset to be written.
+* @param	Bits is the Bits to be set in the register
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XUsbPs_SetBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
+*
+*****************************************************************************/
+#define XUsbPs_SetBits(InstancePtr, RegOffset, Bits) \
+	XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset,	\
+		XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, 	\
+					RegOffset) | (Bits));
+
+
+/****************************************************************************/
+/**
+*
+* This macro clears the given bits in the register.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	RegOffset is the register offset to be written.
+* @param	Bits are the bits to be cleared in the register
+*
+* @return	None.
+*
+* @note
+* 	C-style signature:
+*	void XUsbPs_ClrBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
+*
+*****************************************************************************/
+#define XUsbPs_ClrBits(InstancePtr, RegOffset, Bits) \
+	XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset,	\
+		XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, 	\
+				RegOffset) & ~(Bits));
+
+
+/************************** Function Prototypes ******************************/
+
+/**
+ * Setup / Initialize functions.
+ *
+ * Implemented in file xusbps.c
+ */
+int XUsbPs_CfgInitialize(XUsbPs *InstancePtr,
+			  const XUsbPs_Config *ConfigPtr, u32 BaseAddress);
+
+int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr,
+				const XUsbPs_DeviceConfig *CfgPtr);
+
+/**
+ * Common functions used for DEVICE/HOST mode.
+ */
+int XUsbPs_Reset(XUsbPs *InstancePtr);
+
+void XUsbPs_DeviceReset(XUsbPs *InstancePtr);
+
+/**
+ * DEVICE mode specific functions.
+ */
+int XUsbPs_BusReset(XUsbPs *InstancePtr);
+int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address);
+
+
+/**
+ * Handling Suspend and Resume.
+ *
+ * Implemented in xusbps.c
+ */
+int XUsbPs_Suspend(const XUsbPs *InstancePtr);
+int XUsbPs_Resume(const XUsbPs *InstancePtr);
+int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr);
+
+
+/*
+ * Functions for managing Endpoints / Transfers
+ *
+ * Implemented in file xusbps_endpoint.c
+ */
+int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum,
+			const u8 *BufferPtr, u32 BufferLen);
+int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum,
+			const u8 *BufferPtr, u32 BufferLen);
+int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
+			u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle);
+void XUsbPs_EpBufferRelease(u32 Handle);
+
+int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
+			XUsbPs_EpHandlerFunc CallBackFunc,
+			void *CallBackRef);
+int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum,
+			XUsbPs_SetupData *SetupDataPtr);
+
+int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction);
+
+int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr,
+			int EpNum, unsigned short NewDirection, int DirectionChanged);
+
+/*
+ * Interrupt handling functions
+ *
+ * Implemented in file xusbps_intr.c
+ */
+void XUsbPs_IntrHandler(void *InstancePtr);
+
+int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr,
+			   XUsbPs_IntrHandlerFunc CallBackFunc,
+			   void *CallBackRef, u32 Mask);
+/*
+ * Helper functions for static configuration.
+ * Implemented in xusbps_sinit.c
+ */
+XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XUSBPS_H */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xusbps_endpoint.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xusbps_endpoint.h
new file mode 100644
index 0000000000000000000000000000000000000000..b8b9ad685823a1e0da09516bd39632b198ec74f3
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xusbps_endpoint.h
@@ -0,0 +1,515 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal 
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xusbps_endpoint.h
+* @addtogroup usbps_v2_2
+* @{
+ *
+ * This is an internal file containung the definitions for endpoints. It is
+ * included by the xusbps_endpoint.c which is implementing the endpoint
+ * functions and by xusbps_intr.c.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- --------------------------------------------------------
+ * 1.00a wgr  10/10/10 First release
+ * </pre>
+ *
+ ******************************************************************************/
+#ifndef XUSBPS_ENDPOINT_H
+#define XUSBPS_ENDPOINT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xusbps.h"
+#include "xil_types.h"
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+
+/**
+ * Endpoint Device Transfer Descriptor
+ *
+ * The dTD describes to the device controller the location and quantity of data
+ * to be sent/received for given transfer. The driver does not attempt to
+ * modify any field in an active dTD except the Next Link Pointer.
+ */
+#define XUSBPS_dTDNLP		0x00 /**< Pointer to the next descriptor */
+#define XUSBPS_dTDTOKEN	0x04 /**< Descriptor Token */
+#define XUSBPS_dTDBPTR0	0x08 /**< Buffer Pointer 0 */
+#define XUSBPS_dTDBPTR1	0x0C /**< Buffer Pointer 1 */
+#define XUSBPS_dTDBPTR2	0x10 /**< Buffer Pointer 2 */
+#define XUSBPS_dTDBPTR3	0x14 /**< Buffer Pointer 3 */
+#define XUSBPS_dTDBPTR4	0x18 /**< Buffer Pointer 4 */
+#define XUSBPS_dTDBPTR(n)	(XUSBPS_dTDBPTR0 + (n) * 0x04)
+#define XUSBPS_dTDRSRVD	0x1C /**< Reserved field */
+
+/* We use the reserved field in the dTD to store user data. */
+#define XUSBPS_dTDUSERDATA	XUSBPS_dTDRSRVD /**< Reserved field */
+
+
+/** @name dTD Next Link Pointer (dTDNLP) bit positions.
+ *  @{
+ */
+#define XUSBPS_dTDNLP_T_MASK		0x00000001
+				/**< USB dTD Next Link Pointer Terminate Bit */
+#define XUSBPS_dTDNLP_ADDR_MASK	0xFFFFFFE0
+				/**< USB dTD Next Link Pointer Address [31:5] */
+/* @} */
+
+
+/** @name dTD Token (dTDTOKEN) bit positions.
+ *  @{
+ */
+#define XUSBPS_dTDTOKEN_XERR_MASK	0x00000008 /**< dTD Transaction Error */
+#define XUSBPS_dTDTOKEN_BUFERR_MASK	0x00000020 /**< dTD Data Buffer Error */
+#define XUSBPS_dTDTOKEN_HALT_MASK	0x00000040 /**< dTD Halted Flag */
+#define XUSBPS_dTDTOKEN_ACTIVE_MASK	0x00000080 /**< dTD Active Bit */
+#define XUSBPS_dTDTOKEN_MULTO_MASK	0x00000C00 /**< Multiplier Override Field [1:0] */
+#define XUSBPS_dTDTOKEN_IOC_MASK	0x00008000 /**< Interrupt on Complete Bit */
+#define XUSBPS_dTDTOKEN_LEN_MASK	0x7FFF0000 /**< Transfer Length Field */
+/* @} */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ *
+ * IMPORTANT NOTE:
+ * ===============
+ *
+ * Many of the following macros modify Device Queue Head (dQH) data structures
+ * and Device Transfer Descriptor (dTD) data structures. Those structures can
+ * potentially reside in CACHED memory. Therefore, it's the callers
+ * responsibility to ensure cache coherency by using provided
+ *
+ * 	XUsbPs_dQHInvalidateCache()
+ * 	XUsbPs_dQHFlushCache()
+ * 	XUsbPs_dTDInvalidateCache()
+ * 	XUsbPs_dTDFlushCache()
+ *
+ * function calls.
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDInvalidateCache(dTDPtr) \
+		Xil_DCacheInvalidateRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
+
+#define XUsbPs_dTDFlushCache(dTDPtr) \
+		Xil_DCacheFlushRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
+
+#define XUsbPs_dQHInvalidateCache(dQHPtr) \
+		Xil_DCacheInvalidateRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
+
+#define XUsbPs_dQHFlushCache(dQHPtr) \
+		Xil_DCacheFlushRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Transfer Length for the given Transfer Descriptor.
+ *
+ * @param	dTDPtr is pointer to the dTD element.
+ * @param	Len is the length to be set. Range: 0..16384
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetTransferLen(dTDPtr, Len)				\
+		XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, 		\
+			(XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) &	\
+				~XUSBPS_dTDTOKEN_LEN_MASK) | ((Len) << 16))
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro gets the Next Link pointer of the given Transfer Descriptor.
+ *
+ * @param	dTDPtr is pointer to the dTD element.
+ *
+ * @return 	TransferLength field of the descriptor.
+ *
+ * @note	C-style signature:
+ *		u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDGetNLP(dTDPtr)					\
+		(XUsbPs_dTD *) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP)\
+					& XUSBPS_dTDNLP_ADDR_MASK))
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Next Link pointer of the given Transfer Descriptor.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ * @param	NLP is the Next Link Pointer
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetNLP(dTDPtr, NLP)					\
+		XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, 		\
+			(XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) &	\
+				~XUSBPS_dTDNLP_ADDR_MASK) |		\
+					((NLP) & XUSBPS_dTDNLP_ADDR_MASK))
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro gets the Transfer Length for the given Transfer Descriptor.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ *
+ * @return 	TransferLength field of the descriptor.
+ *
+ * @note	C-style signature:
+ *		u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDGetTransferLen(dTDPtr)				\
+		(u32) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) 	\
+				& XUSBPS_dTDTOKEN_LEN_MASK) >> 16)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Interrupt On Complete (IOC) bit for the given Transfer
+ * Descriptor.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dTDSetIOC(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetIOC(dTDPtr)					\
+		XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, 		\
+			XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) |	\
+						XUSBPS_dTDTOKEN_IOC_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Terminate bit for the given Transfer Descriptor.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dTDSetTerminate(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetTerminate(dTDPtr)				\
+		XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, 		\
+			XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) |	\
+						XUSBPS_dTDNLP_T_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro clears the Terminate bit for the given Transfer Descriptor.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dTDClrTerminate(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDClrTerminate(dTDPtr)				\
+		XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, 		\
+			XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) &	\
+						~XUSBPS_dTDNLP_T_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro checks if the given descriptor is active.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ *
+ * @return
+ * 		- TRUE: The buffer is active.
+ * 		- FALSE: The buffer is not active.
+ *
+ * @note	C-style signature:
+ *		int XUsbPs_dTDIsActive(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDIsActive(dTDPtr)					\
+		((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) &		\
+				XUSBPS_dTDTOKEN_ACTIVE_MASK) ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Active bit for the given Transfer Descriptor.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dTDSetActive(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetActive(dTDPtr)					\
+		XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, 		\
+			XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) |	\
+						XUSBPS_dTDTOKEN_ACTIVE_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro reads the content of a field in a Transfer Descriptor.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ * @param	Id is the field ID inside the dTD element to read.
+ *
+ * @note	C-style signature:
+ *		u32 XUsbPs_ReaddTD(u32 dTDPtr, u32 Id)
+ *
+ ******************************************************************************/
+#define XUsbPs_ReaddTD(dTDPtr, Id)	(*(u32 *)((u32)(dTDPtr) + (u32)(Id)))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro writes a value to a field in a Transfer Descriptor.
+ *
+ * @param	dTDPtr is pointer to the dTD element.
+ * @param	Id is the field ID inside the dTD element to read.
+ * @param	Val is the value to write to the field.
+ *
+ * @note	C-style signature:
+ *		u32 XUsbPs_WritedTD(u32 dTDPtr, u32 Id, u32 Val)
+ *
+ ******************************************************************************/
+#define XUsbPs_WritedTD(dTDPtr, Id, Val)	\
+			(*(u32 *) ((u32)(dTDPtr) + (u32)(Id)) = (u32)(Val))
+
+
+/******************************************************************************/
+/**
+ * Endpoint Device Queue Head
+ *
+ * Device queue heads are arranged in an array in a continuous area of memory
+ * pointed to by the ENDPOINTLISTADDR pointer. The device controller will index
+ * into this array based upon the endpoint number received from the USB bus.
+ * All information necessary to respond to transactions for all primed
+ * transfers is contained in this list so the Device Controller can readily
+ * respond to incoming requests without having to traverse a linked list.
+ *
+ * The device Endpoint Queue Head (dQH) is where all transfers are managed. The
+ * dQH is a 48-byte data structure, but must be aligned on a 64-byte boundary.
+ * During priming of an endpoint, the dTD (device transfer descriptor) is
+ * copied into the overlay area of the dQH, which starts at the nextTD pointer
+ * DWord and continues through the end of the buffer pointers DWords. After a
+ * transfer is complete, the dTD status DWord is updated in the dTD pointed to
+ * by the currentTD pointer. While a packet is in progress, the overlay area of
+ * the dQH is used as a staging area for the dTD so that the Device Controller
+ * can access needed information with little minimal latency.
+ *
+ * @note
+ *    Software must ensure that no interface data structure reachable by the
+ *    Device Controller spans a 4K-page boundary.  The first element of the
+ *    Endpoint Queue Head List must be aligned on a 4K boundary.
+ */
+#define XUSBPS_dQHCFG			0x00 /**< dQH Configuration */
+#define XUSBPS_dQHCPTR			0x04 /**< dQH Current dTD Pointer */
+#define XUSBPS_dQHdTDNLP		0x08 /**< dTD Next Link Ptr in dQH
+					       overlay */
+#define XUSBPS_dQHdTDTOKEN		0x0C /**< dTD Token in dQH overlay */
+#define XUSBPS_dQHSUB0			0x28 /**< USB dQH Setup Buffer 0 */
+#define XUSBPS_dQHSUB1			0x2C /**< USB dQH Setup Buffer 1 */
+
+
+/** @name dQH Configuration (dQHCFG) bit positions.
+ *  @{
+ */
+#define XUSBPS_dQHCFG_IOS_MASK		0x00008000
+					/**< USB dQH Interrupt on Setup Bit */
+#define XUSBPS_dQHCFG_MPL_MASK		0x07FF0000
+					/**< USB dQH Maximum Packet Length
+					 * Field [10:0] */
+#define XUSBPS_dQHCFG_MPL_SHIFT    16
+#define XUSBPS_dQHCFG_ZLT_MASK		0x20000000
+					/**< USB dQH Zero Length Termination
+					 * Select Bit */
+#define XUSBPS_dQHCFG_MULT_MASK		0xC0000000
+					/* USB dQH Number of Transactions Field
+					 * [1:0] */
+#define XUSBPS_dQHCFG_MULT_SHIFT       30
+/* @} */
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Maximum Packet Length field of the give Queue Head.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ * @param	Len is the length to be set.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dQHSetMaxPacketLen(u32 dQHPtr, u32 Len)
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHSetMaxPacketLen(dQHPtr, Len)			\
+		XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, 		\
+			(XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) &	\
+				~XUSBPS_dQHCFG_MPL_MASK) | ((Len) << 16))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Interrupt On Setup (IOS) bit for an endpoint.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dQHSetIOS(u32 dQHPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHSetIOS(dQHPtr)					\
+		XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, 		\
+			XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) |	\
+						XUSBPS_dQHCFG_IOS_MASK)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro clears the Interrupt On Setup (IOS) bit for an endpoint.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dQHClrIOS(u32 dQHPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHClrIOS(dQHPtr)					\
+		XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, 		\
+			XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) &	\
+						~XUSBPS_dQHCFG_IOS_MASK)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro enables Zero Length Termination for the endpoint.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dQHEnableZLT(u32 dQHPtr)
+ *
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHEnableZLT(dQHPtr)					\
+		XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, 		\
+			XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) &	\
+						~XUSBPS_dQHCFG_ZLT_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro disables Zero Length Termination for the endpoint.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dQHDisableZLT(u32 dQHPtr)
+ *
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHDisableZLT(dQHPtr)					\
+		XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, 		\
+			XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) |	\
+						XUSBPS_dQHCFG_ZLT_MASK)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro reads the content of a field in a Queue Head.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ * @param	Id is the Field ID inside the dQH element to read.
+ *
+ * @note	C-style signature:
+ *		u32 XUsbPs_ReaddQH(u32 dQHPtr, u32 Id)
+ *
+ ******************************************************************************/
+#define XUsbPs_ReaddQH(dQHPtr, Id)	(*(u32 *)((u32)(dQHPtr) + (u32) (Id)))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro writes a value to a field in a Queue Head.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ * @param	Id is the Field ID inside the dQH element to read.
+ * @param	Val is the Value to write to the field.
+ *
+ * @note	C-style signature:
+ *		u32 XUsbPs_WritedQH(u32 dQHPtr, u32 Id, u32 Val)
+ *
+ ******************************************************************************/
+#define XUsbPs_WritedQH(dQHPtr, Id, Val)	\
+			(*(u32 *) ((u32)(dQHPtr) + (u32)(Id)) = (u32)(Val))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XUSBPS_ENDPOINT_H */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xusbps_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xusbps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..792fbdde5ba93c34498461a15c3858bb9cc71098
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/include/xusbps_hw.h
@@ -0,0 +1,526 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal 
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xusbps_hw.h
+* @addtogroup usbps_v2_2
+* @{
+ *
+ * This header file contains identifiers and low-level driver functions (or
+ * macros) that can be used to access the device. High-level driver functions
+ * are defined in xusbps.h.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a wgr  10/10/10 First release
+ * 1.04a nm   10/23/12 Fixed CR# 679106.
+ * 1.05a kpc  07/03/13 Added XUsbPs_ResetHw function prototype
+ * 2.00a kpc  04/03/14 Fixed CR#777764. Corrected max endpoint vale and masks 
+ * </pre>
+ *
+ ******************************************************************************/
+#ifndef XUSBPS_HW_H
+#define XUSBPS_HW_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+
+#define XUSBPS_REG_SPACING		4
+
+/** @name Timer 0 Register offsets
+ *
+ * @{
+ */
+#define XUSBPS_TIMER0_LD_OFFSET	0x00000080
+#define XUSBPS_TIMER0_CTL_OFFSET	0x00000084
+/* @} */
+
+/** @name Timer Control Register bit mask
+ *
+ * @{
+ */
+#define XUSBPS_TIMER_RUN_MASK		0x80000000
+#define XUSBPS_TIMER_STOP_MASK		0x80000000
+#define XUSBPS_TIMER_RESET_MASK	0x40000000
+#define XUSBPS_TIMER_REPEAT_MASK	0x01000000
+/* @} */
+
+/** @name Timer Control Register bit mask
+ *
+ * @{
+ */
+#define XUSBPS_TIMER_COUNTER_MASK	0x00FFFFFF
+/* @} */
+
+/** @name Device Hardware Parameters
+ *
+ * @{
+ */
+#define XUSBPS_HWDEVICE_OFFSET		0x0000000C
+
+#define XUSBPS_EP_NUM_MASK		0x3E
+#define XUSBPS_EP_NUM_SHIFT		1
+/* @} */
+
+/** @name Capability Regsiter offsets
+ */
+#define XUSBPS_HCSPARAMS_OFFSET		0x00000104
+
+/** @name Operational Register offsets.
+ * Register comments are tagged with "H:" and "D:" for Host and Device modes,
+ * respectively.
+ * Tags are only present for registers that have a different meaning DEVICE and
+ * HOST modes. Most registers are only valid for either DEVICE or HOST mode.
+ * Those registers don't have tags.
+ * @{
+ */
+#define XUSBPS_CMD_OFFSET		0x00000140 /**< Configuration */
+#define XUSBPS_ISR_OFFSET		0x00000144 /**< Interrupt Status */
+#define XUSBPS_IER_OFFSET		0x00000148 /**< Interrupt Enable */
+#define XUSBPS_FRAME_OFFSET		0x0000014C /**< USB Frame Index */
+#define XUSBPS_LISTBASE_OFFSET		0x00000154 /**< H: Periodic List Base Address */
+#define XUSBPS_DEVICEADDR_OFFSET	0x00000154 /**< D: Device Address */
+#define XUSBPS_ASYNCLISTADDR_OFFSET	0x00000158 /**< H: Async List Address */
+#define XUSBPS_EPLISTADDR_OFFSET	0x00000158 /**< D: Endpoint List Addr */
+#define XUSBPS_TTCTRL_OFFSET		0x0000015C /**< TT Control */
+#define XUSBPS_BURSTSIZE_OFFSET	0x00000160 /**< Burst Size */
+#define XUSBPS_TXFILL_OFFSET		0x00000164 /**< Tx Fill Tuning */
+#define XUSBPS_ULPIVIEW_OFFSET		0x00000170 /**< ULPI Viewport */
+#define XUSBPS_EPNAKISR_OFFSET		0x00000178 /**< Endpoint NAK IRQ Status */
+#define XUSBPS_EPNAKIER_OFFSET		0x0000017C /**< Endpoint NAK IRQ Enable */
+#define XUSBPS_PORTSCR1_OFFSET		0x00000184 /**< Port Control/Status 1 */
+
+/* NOTE: The Port Control / Status Register index is 1-based. */
+#define XUSBPS_PORTSCRn_OFFSET(n)	\
+		(XUSBPS_PORTSCR1_OFFSET + (((n)-1) * XUSBPS_REG_SPACING))
+
+
+#define XUSBPS_OTGCSR_OFFSET	0x000001A4 /**< OTG Status and Control */
+#define XUSBPS_MODE_OFFSET	0x000001A8 /**< USB Mode */
+#define XUSBPS_EPSTAT_OFFSET	0x000001AC /**< Endpoint Setup Status */
+#define XUSBPS_EPPRIME_OFFSET	0x000001B0 /**< Endpoint Prime */
+#define XUSBPS_EPFLUSH_OFFSET	0x000001B4 /**< Endpoint Flush */
+#define XUSBPS_EPRDY_OFFSET	0x000001B8 /**< Endpoint Ready */
+#define XUSBPS_EPCOMPL_OFFSET	0x000001BC /**< Endpoint Complete */
+#define XUSBPS_EPCR0_OFFSET	0x000001C0 /**< Endpoint Control 0 */
+#define XUSBPS_EPCR1_OFFSET	0x000001C4 /**< Endpoint Control 1 */
+#define XUSBPS_EPCR2_OFFSET	0x000001C8 /**< Endpoint Control 2 */
+#define XUSBPS_EPCR3_OFFSET	0x000001CC /**< Endpoint Control 3 */
+#define XUSBPS_EPCR4_OFFSET	0x000001D0 /**< Endpoint Control 4 */
+
+#define XUSBPS_MAX_ENDPOINTS	12	   /**< Number of supported Endpoints in
+					     *  this core. */
+#define XUSBPS_EP_OUT_MASK	0x00000FFF /**< OUR (RX) endpoint mask */
+#define XUSBPS_EP_IN_MASK	0x0FFF0000 /**< IN (TX) endpoint mask */
+#define XUSBPS_EP_ALL_MASK	0x0FFF0FFF /**< Mask used for endpoint control
+					     *  registers */
+#define XUSBPS_EPCRn_OFFSET(n)	\
+		(XUSBPS_EPCR0_OFFSET + ((n) * XUSBPS_REG_SPACING))
+
+#define  XUSBPS_EPFLUSH_RX_SHIFT   0
+#define  XUSBPS_EPFLUSH_TX_SHIFT  16
+
+/* @} */
+
+
+
+/** @name Endpoint Control Register (EPCR) bit positions.
+ *  @{
+ */
+
+/* Definitions for TX Endpoint bits */
+#define XUSBPS_EPCR_TXT_CONTROL_MASK	0x00000000 /**< Control Endpoint - TX */
+#define XUSBPS_EPCR_TXT_ISO_MASK	0x00040000 /**< Isochronous. Endpoint */
+#define XUSBPS_EPCR_TXT_BULK_MASK	0x00080000 /**< Bulk Endpoint - TX */
+#define XUSBPS_EPCR_TXT_INTR_MASK	0x000C0000 /**< Interrupt Endpoint */
+#define XUSBPS_EPCR_TXS_MASK		0x00010000 /**< Stall TX endpoint */
+#define XUSBPS_EPCR_TXE_MASK		0x00800000 /**< Transmit enable  - TX */
+#define XUSBPS_EPCR_TXR_MASK		0x00400000 /**< Data Toggle Reset Bit */
+
+
+/* Definitions for RX Endpoint bits */
+#define XUSBPS_EPCR_RXT_CONTROL_MASK	0x00000000 /**< Control Endpoint - RX */
+#define XUSBPS_EPCR_RXT_ISO_MASK	0x00000004 /**< Isochronous Endpoint */
+#define XUSBPS_EPCR_RXT_BULK_MASK	0x00000008 /**< Bulk Endpoint - RX */
+#define XUSBPS_EPCR_RXT_INTR_MASK	0x0000000C /**< Interrupt Endpoint */
+#define XUSBPS_EPCR_RXS_MASK		0x00000001 /**< Stall RX endpoint. */
+#define XUSBPS_EPCR_RXE_MASK		0x00000080 /**< Transmit enable. - RX */
+#define XUSBPS_EPCR_RXR_MASK		0x00000040 /**< Data Toggle Reset Bit */
+/* @} */
+
+
+/** @name USB Command Register (CR) bit positions.
+ *  @{
+ */
+#define XUSBPS_CMD_RS_MASK	0x00000001 /**< Run/Stop */
+#define XUSBPS_CMD_RST_MASK	0x00000002 /**< Controller RESET */
+#define XUSBPS_CMD_FS01_MASK	0x0000000C /**< Frame List Size bit 0,1 */
+#define XUSBPS_CMD_PSE_MASK	0x00000010 /**< Periodic Sched Enable */
+#define XUSBPS_CMD_ASE_MASK	0x00000020 /**< Async Sched Enable */
+#define XUSBPS_CMD_IAA_MASK	0x00000040 /**< IRQ Async Advance Doorbell */
+#define XUSBPS_CMD_ASP_MASK	0x00000300 /**< Async Sched Park Mode Cnt */
+#define XUSBPS_CMD_ASPE_MASK	0x00000800 /**< Async Sched Park Mode Enbl */
+#define XUSBPS_CMD_SUTW_MASK	0x00002000 /**< Setup TripWire */
+#define XUSBPS_CMD_ATDTW_MASK	0x00004000 /**< Add dTD TripWire */
+#define XUSBPS_CMD_FS2_MASK	0x00008000 /**< Frame List Size bit 2 */
+#define XUSBPS_CMD_ITC_MASK	0x00FF0000 /**< IRQ Threshold Control */
+/* @} */
+
+
+/**
+ * @name Interrupt Threshold
+ * These definitions are used by software to set the maximum rate at which the
+ * USB controller will generate interrupt requests. The interrupt interval is
+ * given in number of micro-frames.
+ *
+ * USB defines a full-speed 1 ms frame time indicated by a Start Of Frame (SOF)
+ * packet each and every 1ms. USB also defines a high-speed micro-frame with a
+ * 125us frame time. For each micro-frame a SOF (Start Of Frame) packet is
+ * generated. Data is sent in between the SOF packets. The interrupt threshold
+ * defines how many micro-frames the controller waits before issuing an
+ * interrupt after data has been received.
+ *
+ * For a threshold of 0 the controller will issue an interrupt immediately
+ * after the last byte of the data has been received. For a threshold n>0 the
+ * controller will wait for n micro-frames before issuing an interrupt.
+ *
+ * Therefore, a setting of 8 micro-frames (default) means that the controller
+ * will issue at most 1 interrupt per millisecond.
+ *
+ * @{
+ */
+#define XUSBPS_CMD_ITHRESHOLD_0	0x00 /**< Immediate interrupt. */
+#define XUSBPS_CMD_ITHRESHOLD_1	0x01 /**< 1 micro-frame */
+#define XUSBPS_CMD_ITHRESHOLD_2	0x02 /**< 2 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_4	0x04 /**< 4 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_8	0x08 /**< 8 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_16	0x10 /**< 16 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_32	0x20 /**< 32 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_64	0x40 /**< 64 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_MAX	XUSBPS_CMD_ITHRESHOLD_64
+#define XUSBPS_CMD_ITHRESHOLD_DEFAULT	XUSBPS_CMD_ITHRESHOLD_8
+/* @} */
+
+
+
+/** @name USB Interrupt Status Register (ISR) / Interrupt Enable Register (IER)
+ * bit positions.
+ *  @{
+ */
+#define XUSBPS_IXR_UI_MASK	0x00000001 /**< USB Transaction Complete */
+#define XUSBPS_IXR_UE_MASK	0x00000002 /**< Transaction Error */
+#define XUSBPS_IXR_PC_MASK	0x00000004 /**< Port Change Detect */
+#define XUSBPS_IXR_FRE_MASK	0x00000008 /**< Frame List Rollover */
+#define XUSBPS_IXR_AA_MASK	0x00000020 /**< Async Advance */
+#define XUSBPS_IXR_UR_MASK	0x00000040 /**< RESET Received */
+#define XUSBPS_IXR_SR_MASK	0x00000080 /**< Start of Frame */
+#define XUSBPS_IXR_SLE_MASK	0x00000100 /**< Device Controller Suspend */
+#define XUSBPS_IXR_ULPI_MASK	0x00000400 /**< ULPI IRQ */
+#define XUSBPS_IXR_HCH_MASK	0x00001000 /**< Host Controller Halted
+						* Read Only */
+#define XUSBPS_IXR_RCL_MASK	0x00002000 /**< USB Reclamation  Read Only */
+#define XUSBPS_IXR_PS_MASK	0x00004000 /**< Periodic Sched Status
+						* Read Only */
+#define XUSBPS_IXR_AS_MASK	0x00008000 /**< Async Sched Status Read only */
+#define XUSBPS_IXR_NAK_MASK	0x00010000 /**< NAK IRQ */
+#define XUSBPS_IXR_UA_MASK	0x00040000 /**< USB Host Async IRQ */
+#define XUSBPS_IXR_UP_MASK	0x00080000 /**< USB Host Periodic IRQ */
+#define XUSBPS_IXR_TI0_MASK	0x01000000 /**< Timer 0 Interrupt */
+#define XUSBPS_IXR_TI1_MASK	0x02000000 /**< Timer 1 Interrupt */
+
+#define XUSBPS_IXR_ALL			(XUSBPS_IXR_UI_MASK	| \
+					 XUSBPS_IXR_UE_MASK		| \
+					 XUSBPS_IXR_PC_MASK	| \
+					 XUSBPS_IXR_FRE_MASK	| \
+					 XUSBPS_IXR_AA_MASK	| \
+					 XUSBPS_IXR_UR_MASK		| \
+					 XUSBPS_IXR_SR_MASK		| \
+					 XUSBPS_IXR_SLE_MASK	| \
+					 XUSBPS_IXR_ULPI_MASK		| \
+					 XUSBPS_IXR_HCH_MASK	| \
+					 XUSBPS_IXR_RCL_MASK	| \
+					 XUSBPS_IXR_PS_MASK | \
+					 XUSBPS_IXR_AS_MASK		| \
+					 XUSBPS_IXR_NAK_MASK		| \
+					 XUSBPS_IXR_UA_MASK	| \
+					 XUSBPS_IXR_UP_MASK | \
+					 XUSBPS_IXR_TI0_MASK | \
+					 XUSBPS_IXR_TI1_MASK)
+					/**< Mask for ALL IRQ types */
+/* @} */
+
+
+/** @name USB Mode Register (MODE) bit positions.
+ *  @{
+ */
+#define XUSBPS_MODE_CM_MASK		0x00000003 /**< Controller Mode Select */
+#define XUSBPS_MODE_CM_IDLE_MASK	0x00000000
+#define XUSBPS_MODE_CM_DEVICE_MASK	0x00000002
+#define XUSBPS_MODE_CM_HOST_MASK	0x00000003
+#define XUSBPS_MODE_ES_MASK		0x00000004 /**< USB Endian Select */
+#define XUSBPS_MODE_SLOM_MASK		0x00000008 /**< USB Setup Lockout Mode Disable */
+#define XUSBPS_MODE_SDIS_MASK		0x00000010
+#define XUSBPS_MODE_VALID_MASK		0x0000001F
+
+/* @} */
+
+
+/** @name USB Device Address Register (DEVICEADDR) bit positions.
+ *  @{
+ */
+#define XUSBPS_DEVICEADDR_DEVICEAADV_MASK	0x01000000
+					/**< Device Addr Auto Advance */
+#define XUSBPS_DEVICEADDR_ADDR_MASK		0xFE000000
+					/**< Device Address */
+#define XUSBPS_DEVICEADDR_ADDR_SHIFT		25
+					/**< Address shift */
+#define XUSBPS_DEVICEADDR_MAX			127
+					/**< Biggest allowed address */
+/* @} */
+
+/** @name USB TT Control Register (TTCTRL) bit positions.
+ *  @{
+ */
+#define XUSBPS_TTCTRL_HUBADDR_MASK	0x7F000000 /**< TT Hub Address */
+/* @} */
+
+
+/** @name USB Burst Size Register (BURSTSIZE) bit posisions.
+ *  @{
+ */
+#define XUSBPS_BURSTSIZE_RX_MASK	0x000000FF /**< RX Burst Length */
+#define XUSBPS_BURSTSIZE_TX_MASK	0x0000FF00 /**< TX Burst Length */
+/* @} */
+
+
+/** @name USB Tx Fill Tuning Register (TXFILL) bit positions.
+ *  @{
+ */
+#define XUSBPS_TXFILL_OVERHEAD_MASK	0x000000FF
+					/**< Scheduler Overhead */
+#define XUSBPS_TXFILL_HEALTH_MASK	0x00001F00
+					/**< Scheduler Health Cntr */
+#define XUSBPS_TXFILL_BURST_MASK	0x003F0000
+					/**< FIFO Burst Threshold */
+/* @} */
+
+
+/** @name USB ULPI Viewport Register (ULPIVIEW) bit positions.
+ *  @{
+ */
+#define XUSBPS_ULPIVIEW_DATWR_MASK	0x000000FF /**< ULPI Data Write */
+#define XUSBPS_ULPIVIEW_DATRD_MASK	0x0000FF00 /**< ULPI Data Read */
+#define XUSBPS_ULPIVIEW_ADDR_MASK	0x00FF0000 /**< ULPI Data Address */
+#define XUSBPS_ULPIVIEW_PORT_MASK	0x07000000 /**< ULPI Port Number */
+#define XUSBPS_ULPIVIEW_SS_MASK	0x08000000 /**< ULPI Synchronous State */
+#define XUSBPS_ULPIVIEW_RW_MASK	0x20000000 /**< ULPI Read/Write Control */
+#define XUSBPS_ULPIVIEW_RUN_MASK	0x40000000 /**< ULPI Run */
+#define XUSBPS_ULPIVIEW_WU_MASK	0x80000000 /**< ULPI Wakeup */
+/* @} */
+
+
+/** @name Port Status Control Register bit positions.
+ *  @{
+ */
+#define XUSBPS_PORTSCR_CCS_MASK  0x00000001 /**< Current Connect Status */
+#define XUSBPS_PORTSCR_CSC_MASK  0x00000002 /**< Connect Status Change */
+#define XUSBPS_PORTSCR_PE_MASK	  0x00000004 /**< Port Enable/Disable */
+#define XUSBPS_PORTSCR_PEC_MASK  0x00000008 /**< Port Enable/Disable Change */
+#define XUSBPS_PORTSCR_OCA_MASK  0x00000010 /**< Over-current Active */
+#define XUSBPS_PORTSCR_OCC_MASK  0x00000020 /**< Over-current Change */
+#define XUSBPS_PORTSCR_FPR_MASK  0x00000040 /**< Force Port Resume */
+#define XUSBPS_PORTSCR_SUSP_MASK 0x00000080 /**< Suspend */
+#define XUSBPS_PORTSCR_PR_MASK	  0x00000100 /**< Port Reset */
+#define XUSBPS_PORTSCR_HSP_MASK  0x00000200 /**< High Speed Port */
+#define XUSBPS_PORTSCR_LS_MASK	  0x00000C00 /**< Line Status */
+#define XUSBPS_PORTSCR_PP_MASK	  0x00001000 /**< Port Power */
+#define XUSBPS_PORTSCR_PO_MASK	  0x00002000 /**< Port Owner */
+#define XUSBPS_PORTSCR_PIC_MASK  0x0000C000 /**< Port Indicator Control */
+#define XUSBPS_PORTSCR_PTC_MASK  0x000F0000 /**< Port Test Control */
+#define XUSBPS_PORTSCR_WKCN_MASK 0x00100000 /**< Wake on Connect Enable */
+#define XUSBPS_PORTSCR_WKDS_MASK 0x00200000 /**< Wake on Disconnect Enable */
+#define XUSBPS_PORTSCR_WKOC_MASK 0x00400000 /**< Wake on Over-current Enable */
+#define XUSBPS_PORTSCR_PHCD_MASK 0x00800000 /**< PHY Low Power Suspend -
+						* Clock Disable */
+#define XUSBPS_PORTSCR_PFSC_MASK 0x01000000 /**< Port Force Full Speed
+						* Connect */
+#define XUSBPS_PORTSCR_PSPD_MASK 0x0C000000 /**< Port Speed */
+/* @} */
+
+
+/** @name On-The-Go Status Control Register (OTGCSR) bit positions.
+ *  @{
+ */
+#define XUSBPS_OTGSC_VD_MASK	 0x00000001 /**< VBus Discharge Bit */
+#define XUSBPS_OTGSC_VC_MASK	 0x00000002 /**< VBus Charge Bit */
+#define XUSBPS_OTGSC_HAAR_MASK	 0x00000004 /**< HW Assist Auto Reset
+				 		       *  Enable Bit */
+#define XUSBPS_OTGSC_OT_MASK	 0x00000008 /**< OTG Termination Bit */
+#define XUSBPS_OTGSC_DP_MASK	 0x00000010 /**< Data Pulsing Pull-up
+				 		       *  Enable Bit */
+#define XUSBPS_OTGSC_IDPU_MASK	 0x00000020 /**< ID Pull-up Enable Bit */
+#define XUSBPS_OTGSC_HADP_MASK	 0x00000040 /**< HW Assist Data Pulse
+							* Enable Bit */
+#define XUSBPS_OTGSC_HABA_MASK	 0x00000080 /**< USB Hardware Assist
+						       *  B Disconnect to A
+						       *  Connect Enable Bit */
+#define XUSBPS_OTGSC_ID_MASK	 0x00000100 /**< ID Status Flag */
+#define XUSBPS_OTGSC_AVV_MASK	 0x00000200 /**< USB A VBus Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_ASV_MASK	 0x00000400 /**< USB A Session Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_BSV_MASK	 0x00000800 /**< USB B Session Valid Status Flag */
+#define XUSBPS_OTGSC_BSE_MASK	 0x00001000 /**< USB B Session End Status Flag */
+#define XUSBPS_OTGSC_1MST_MASK	 0x00002000 /**< USB 1 Millisecond Timer Status Flag */
+#define XUSBPS_OTGSC_DPS_MASK	 0x00004000 /**< Data Pulse Status Flag */
+#define XUSBPS_OTGSC_IDIS_MASK	 0x00010000 /**< USB ID Interrupt Status Flag */
+#define XUSBPS_OTGSC_AVVIS_MASK 0x00020000 /**< USB A VBus Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_ASVIS_MASK 0x00040000 /**< USB A Session Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_BSVIS_MASK 0x00080000 /**< USB B Session Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_BSEIS_MASK 0x00100000 /**< USB B Session End Interrupt Status Flag */
+#define XUSBPS_OTGSC_1MSS_MASK	 0x00200000 /**< 1 Millisecond Timer Interrupt Status Flag */
+#define XUSBPS_OTGSC_DPIS_MASK	 0x00400000 /**< Data Pulse Interrupt Status Flag */
+#define XUSBPS_OTGSC_IDIE_MASK	 0x01000000 /**< ID Interrupt Enable Bit */
+#define XUSBPS_OTGSC_AVVIE_MASK 0x02000000 /**< USB A VBus Valid Interrupt Enable Bit */
+#define XUSBPS_OTGSC_ASVIE_MASK 0x04000000 /**< USB A Session Valid Interrupt Enable Bit */
+#define XUSBPS_OTGSC_BSVIE_MASK 0x08000000 /**< USB B Session Valid Interrupt Enable Bit */
+#define XUSBPS_OTGSC_BSEE_MASK	 0x10000000 /**< USB B Session End Interrupt Enable Bit */
+#define XUSBPS_OTGSC_1MSE_MASK	 0x20000000 /**< 1 Millisecond Timer
+						* Interrupt Enable Bit */
+#define XUSBPS_OTGSC_DPIE_MASK	 0x40000000 /**< Data Pulse Interrupt
+							* Enable Bit */
+
+#define XUSBPS_OTG_ISB_ALL	(XUSBPS_OTGSC_IDIS_MASK |\
+				XUSBPS_OTGSC_AVVIS_MASK | \
+				XUSBPS_OTGSC_ASVIS_MASK | \
+				XUSBPS_OTGSC_BSVIS_MASK | \
+				XUSBPS_OTGSC_BSEIS_MASK | \
+				XUSBPS_OTGSC_1MSS_MASK | \
+				XUSBPS_OTGSC_DPIS_MASK)
+				/** Mask for All IRQ status masks */
+
+#define XUSBPS_OTG_IEB_ALL	(XUSBPS_OTGSC_IDIE_MASK |\
+				XUSBPS_OTGSC_AVVIE_MASK | \
+				XUSBPS_OTGSC_ASVIE_MASK | \
+				XUSBPS_OTGSC_BSVIE_MASK | \
+				XUSBPS_OTGSC_BSEE_IEB_MASK | \
+				XUSBPS_OTGSC_1MSE_MASK | \
+				XUSBPS_OTGSC_DPIE_MASK)
+				/** Mask for All IRQ Enable masks */
+/* @} */
+
+
+/**< Alignment of the Device Queue Head List BASE. */
+#define XUSBPS_dQH_BASE_ALIGN		2048
+
+/**< Alignment of a Device Queue Head structure. */
+#define XUSBPS_dQH_ALIGN		64
+
+/**< Alignment of a Device Transfer Descriptor structure. */
+#define XUSBPS_dTD_ALIGN		32
+
+/**< Size of one RX buffer for a OUT Transfer Descriptor. */
+#define XUSBPS_dTD_BUF_SIZE		4096
+
+/**< Maximum size of one RX/TX buffer. */
+#define XUSBPS_dTD_BUF_MAX_SIZE	16*1024
+
+/**< Alignment requirement for Transfer Descriptor buffers. */
+#define XUSBPS_dTD_BUF_ALIGN		4096
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param	BaseAddress is the base address for the USB registers.
+* @param	RegOffset is the register offset to be read.
+*
+* @return	The 32-bit value of the register.
+*
+* @note		C-style signature:
+*		u32 XUsbPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XUsbPs_ReadReg(BaseAddress, RegOffset) \
+				Xil_In32(BaseAddress + (RegOffset))
+
+
+/****************************************************************************/
+/**
+*
+* This macro writes the given register.
+*
+* @param	BaseAddress is the the base address for the USB registers.
+* @param	RegOffset is the register offset to be written.
+* @param	Data is the the 32-bit value to write to the register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XUsbPs_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+ *****************************************************************************/
+#define XUsbPs_WriteReg(BaseAddress, RegOffset, Data) \
+				Xil_Out32(BaseAddress + (RegOffset), (Data))
+
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the USB PS interface
+ */
+void XUsbPs_ResetHw(u32 BaseAddress);
+/************************** Variable Definitions ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XUSBPS_L_H */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/Makefile b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..007162d8c2e9b11b94b26f6c2c791a9496f22d87
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner coresightps_dcc_comp_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling coresightps_dcc"
+
+coresightps_dcc_comp_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: coresightps_dcc_includes
+
+coresightps_dcc_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c
new file mode 100644
index 0000000000000000000000000000000000000000..cfa356cedeaba2b2f3f2e0df85f45c4f7ba3c7f9
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c
@@ -0,0 +1,188 @@
+/******************************************************************************
+*
+* Copyright (C) 2015-2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcoresightpsdcc.c
+* @addtogroup coresightps_dcc_v1_1
+* @{
+*
+* Functions in this file are the minimum required functions for the
+* XCoreSightPs driver.
+*
+* @note 	None.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date		Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00  kvn    02/14/15 First release
+* 1.1   kvn    06/12/15 Add support for Zynq Ultrascale+ MP.
+*       kvn    08/18/15 Modified Makefile according to compiler changes.
+* 1.2   kvn    10/09/15 Add support for IAR Compiler.
+* 1.3   asa    07/01/16 Made changes to ensure that the file does not compile
+*                       for MB BSPs. Instead it throws up a warning. This
+*                       fixes the CR#953056.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#ifdef __MICROBLAZE__
+#warning "The driver is supported only for ARM architecture"
+#else
+
+#include <xil_types.h>
+#include <xpseudo_asm.h>
+
+#ifdef __ICCARM__
+#define INLINE
+#else
+#define INLINE __inline
+#endif
+
+/* DCC Status Bits */
+#define XCORESIGHTPS_DCC_STATUS_RX (1 << 30)
+#define XCORESIGHTPS_DCC_STATUS_TX (1 << 29)
+
+static INLINE u32 XCoresightPs_DccGetStatus(void);
+
+/****************************************************************************/
+/**
+*
+* This functions sends a single byte using the DCC. It is blocking in that it
+* waits for the transmitter to become non-full before it writes the byte to
+* the transmit register.
+*
+* @param	BaseAddress is a dummy parameter to match the function proto
+*		of functions for other stdio devices.
+* @param	Data is the byte of data to send
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data)
+{
+	(void) BaseAddress;
+	while (XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_TX)
+	dsb();
+#ifdef __aarch64__
+	asm volatile ("msr dbgdtrtx_el0, %0" : : "r" (Data));
+#elif defined (__GNUC__) || defined (__ICCARM__)
+	asm volatile("mcr p14, 0, %0, c0, c5, 0"
+			: : "r" (Data));
+#else
+	{
+		volatile register u32 Reg __asm("cp14:0:c0:c5:0");
+		Reg = Data;
+	}
+#endif
+	isb();
+
+}
+
+/****************************************************************************/
+/**
+*
+* This functions receives a single byte using the DCC. It is blocking in that
+* it waits for the receiver to become non-empty before it reads from the
+* receive register.
+*
+* @param	BaseAddress is a dummy parameter to match the function proto
+*		of functions for other stdio devices.
+*
+* @return	The byte of data received.
+*
+* @note		None.
+*
+******************************************************************************/
+u8 XCoresightPs_DccRecvByte(u32 BaseAddress)
+{
+	u8 Data = 0U;
+	(void) BaseAddress;
+
+	while (!(XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_RX))
+		dsb();
+
+#ifdef __aarch64__
+	asm volatile ("mrs %0, dbgdtrrx_el0" : "=r" (Data));
+#elif defined (__GNUC__) || defined (__ICCARM__)
+	asm volatile("mrc p14, 0, %0, c0, c5, 0"
+			: "=r" (Data));
+#else
+	{
+		volatile register u32 Reg __asm("cp14:0:c0:c5:0");
+		Data = Reg;
+	}
+#endif
+	isb();
+
+	return Data;
+}
+
+
+/****************************************************************************/
+/**INLINE
+*
+* This functions read the status register of the DCC.
+*
+* @param	BaseAddress is the base address of the device
+*
+* @return	The contents of the Status Register.
+*
+* @note		None.
+*
+******************************************************************************/
+static INLINE u32 XCoresightPs_DccGetStatus(void)
+{
+	u32 Status = 0U;
+
+#ifdef __aarch64__
+	asm volatile ("mrs %0, mdccsr_el0" : "=r" (Status));
+#elif defined (__GNUC__) || defined (__ICCARM__)
+	asm volatile("mrc p14, 0, %0, c0, c1, 0"
+			: "=r" (Status) : : "cc");
+#else
+	{
+		volatile register u32 Reg __asm("cp14:0:c0:c1:0");
+		Status = Reg;
+	}
+#endif
+	return Status;
+#endif
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h
new file mode 100644
index 0000000000000000000000000000000000000000..a732b235d6839c79fb42039fc06a42785de2928d
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h
@@ -0,0 +1,74 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcoresightpsdcc.h
+* @addtogroup coresightps_dcc_v1_1
+* @{
+* @details
+*
+* CoreSight driver component.
+*
+* The coresight is a part of debug communication channel (DCC) group. Jtag UART
+* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an
+* ARM target in XSDB console before running the jtag terminal command. Using the
+* coresight driver component, the output stream can be directed to a log file.
+*
+* @note 	None.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date		Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00  kvn    02/14/15 First release
+* 1.1   kvn    06/12/15 Add support for Zynq Ultrascale+ MP.
+*       kvn    08/18/15 Modified Makefile according to compiler changes.
+* 1.3   asa    07/01/16 Made changes to ensure that the file does not compile
+*                       for MB BSPs. Instead it throws up a warning. This
+*                       fixes the CR#953056.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#ifndef __MICROBLAZE__
+#include <xil_types.h>
+
+void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
+
+u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
+#endif
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_4/src/Makefile b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_4/src/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..7ea505c104e84321c18a0440179f06eb02bd72c5
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_4/src/Makefile
@@ -0,0 +1,25 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I${INCLUDEDIR}
+
+OUTS = *.o
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+LIBSOURCES=*.c
+INCLUDEFILES=*.h
+
+libs:
+	echo "Compiling cpu_cortexa9"
+
+.PHONY: include
+include: 
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_4/src/xcpu_cortexa9.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_4/src/xcpu_cortexa9.h
new file mode 100644
index 0000000000000000000000000000000000000000..4d441e53e6691168cfba555258ab1eb54d6207ea
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_4/src/xcpu_cortexa9.h
@@ -0,0 +1,43 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xcpu_cortexa9.h
+* @addtogroup cpu_cortexa9_v2_1
+* @{
+* @details
+*
+* dummy file
+*
+******************************************************************************/
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/Makefile b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..7b191dd922735c60827f378f0b5e70c922db76c9
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xddrps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling ddrps"
+
+xddrps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xddrps_includes
+
+xddrps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h
new file mode 100644
index 0000000000000000000000000000000000000000..fe7adb066edcb52c1f8c35615e813ed23b1b11f6
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h
@@ -0,0 +1,66 @@
+/*******************************************************************************
+ *
+ * Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * Use of the Software is limited solely to applications:
+ * (a) running on a Xilinx device, or
+ * (b) that interact with a Xilinx device through a bus or interconnect.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+*******************************************************************************/
+/******************************************************************************/
+/**
+ *
+ * @file xddrps.h
+ * @addtogroup ddrps_v1_0
+ * @{
+ * @details
+ *
+ * The Xilinx DdrPs driver. This driver supports the Xilinx ddrps
+ * IP core.
+ *
+ * @note	None.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0	 nsk  08/06/15 First Release
+ * 1.0	 nsk  08/20/15 Updated define_addr_params in ddrps.tcl
+ *		       to support PBD Designs (CR #876857)
+ *
+ * </pre>
+ *
+*******************************************************************************/
+
+#ifndef XDDRPS_H_
+/* Prevent circular inclusions by using protection macros. */
+#define XDDRPS_H_
+
+/******************************* Include Files ********************************/
+
+
+#endif /* XDDRPS_H_ */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/Makefile b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..25ff740826e9f1dfe1de19d4602301ba9e400191
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xdevcfg_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling devcfg"
+
+xdevcfg_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xdevcfg_includes
+
+xdevcfg_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg.c
new file mode 100644
index 0000000000000000000000000000000000000000..dcb80303d2037f0ad0ef949559fe31fa0b05bb4e
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg.c
@@ -0,0 +1,945 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg.c
+* @addtogroup devcfg_v3_3
+* @{
+*
+* This file contains the implementation of the interface functions for XDcfg
+* driver. Refer to the header file xdevcfg.h for more detailed information.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.00a nm  05/31/12 Updated the driver for CR 660835 so that input length for
+*		     source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
+*		     APIs is words (32 bit) and not bytes.
+* 		     Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
+*		     to add information that 2 LSBs of the Source/Destination
+*		     address when equal to 2�b01 indicate the last DMA command
+*		     of an overall transfer.
+*		     Updated the XDcfg_Transfer function to use the
+*		     Destination Address passed to this API for secure transfers
+*		     instead of using 0xFFFFFFFF for CR 662197. This issue was
+*		     resulting in the failure of secure transfers of
+*		     non-bitstream images.
+* 2.01a nm  08/27/12 Updated the XDcfg_Transfer API to clear the
+*		     QUARTER_PCAP_RATE_EN bit in the control register for
+*		     non secure writes for CR 675543.
+* 2.02a nm  01/31/13 Fixed CR# 679335.
+* 		     Added Setting and Clearing the internal PCAP loopback.
+*		     Removed code for enabling/disabling AES engine as BootROM
+*		     locks down this setting.
+*		     Fixed CR# 681976.
+*		     Skip Checking the PCFG_INIT in case of non-secure DMA
+*		     loopback.
+*		     Fixed CR# 699558.
+*		     XDcfg_Transfer fails to transfer data in loopback mode.
+* 2.03a nm  04/19/13 Fixed CR# 703728.
+*		     Updated the register definitions as per the latest TRM
+*		     version UG585 (v1.4) November 16, 2012.
+* 3.0   kpc 21/02/14 Implemented new function XDcfg_ClearControlRegister
+* 3.2   sb  08/25/14 Fixed XDcfg_PcapReadback() function
+*		     updated driver code with != instead of ==,
+*		     while checking for Interrupt Status with DMA and
+*		     PCAP Done Mask
+*		     ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+*			XDCFG_INT_STS_OFFSET) &
+*			XDCFG_IXR_D_P_DONE_MASK) !=
+*			XDCFG_IXR_D_P_DONE_MASK);
+*
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Initialize the Device Config Interface driver. This function
+* must be called before other functions of the driver are called.
+*
+* @param	InstancePtr is a pointer to the XDcfg instance.
+* @param	ConfigPtr is the config structure.
+* @param	EffectiveAddress is the base address for the device. It could be
+*		a virtual address if address translation is supported in the
+*		system, otherwise it is the physical address.
+*
+* @return
+*		- XST_SUCCESS if initialization was successful.
+*		- XST_DEVICE_IS_STARTED if the device has already been started.
+*
+* @note		The very first APB access to the Device Configuration Interface
+*		block needs to be a write to the UNLOCK register with the value
+*		of 0x757BDF0D. This step is to be done once after reset, any
+*		other APB access has to come after this. The APB access is
+*		considered illegal if the step is not done or if it is done
+*		incorrectly. Furthermore, if any of efuse_sec_cfg[5:0] is high,
+*		the following additional actions would be carried out.
+*		In other words, if all bits are low, the following steps are not
+*		done.
+*			1. AES is disabled
+*			2. All APB writes disabled
+*			3. SoC debug fully enabled
+*
+******************************************************************************/
+int XDcfg_CfgInitialize(XDcfg *InstancePtr,
+			 XDcfg_Config *ConfigPtr, u32 EffectiveAddress)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * If the device is started, disallow the initialize and return a
+	 * status indicating it is started. This allows the user to stop the
+	 * device and reinitialize, but prevents a user from inadvertently
+	 * initializing.
+	 */
+	if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
+		return XST_DEVICE_IS_STARTED;
+	}
+
+	/*
+	 * Copy configuration into instance.
+	 */
+	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+
+	/*
+	 * Save the base address pointer such that the registers of the block
+	 * can be accessed and indicate it has not been started yet.
+	 */
+	InstancePtr->Config.BaseAddr = EffectiveAddress;
+	InstancePtr->IsStarted = 0;
+
+
+	/* Unlock the Device Configuration Interface */
+	XDcfg_Unlock(InstancePtr);
+
+	/*
+	 * Indicate the instance is ready to use, successfully initialized.
+	 */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* The functions enables the PCAP interface by setting the PCAP mode bit in the
+* control register.
+*
+* @param	InstancePtr is a pointer to the XDcfg instance.
+*
+* @return	None.
+*
+* @note		Enable FPGA programming	from PCAP interface. Enabling this bit
+*		disables all the external interfaces from programming of FPGA
+*		except for ICAP. The user needs to ensure that the FPGA is
+*		programmed through either PCAP or ICAP.
+*
+*****************************************************************************/
+void XDcfg_EnablePCAP(XDcfg *InstancePtr)
+{
+	u32 CtrlReg;
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+					XDCFG_CTRL_OFFSET);
+
+	XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+			(CtrlReg | XDCFG_CTRL_PCAP_MODE_MASK));
+
+}
+
+/****************************************************************************/
+/**
+*
+* The functions disables the PCAP interface by clearing the PCAP mode bit in
+* the control register.
+*
+* @param	InstancePtr is a pointer to the XDcfg instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XDcfg_DisablePCAP(XDcfg *InstancePtr)
+{
+	u32 CtrlReg;
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+					XDCFG_CTRL_OFFSET);
+
+	XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+			(CtrlReg & ( ~XDCFG_CTRL_PCAP_MODE_MASK)));
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the contents of the Control Register.
+*
+* @param	InstancePtr is a pointer to the XDcfg instance.
+* @param	Mask is the 32 bit mask data to be written to the Register.
+*		The mask definitions are defined in the xdevcfg_hw.h file.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask)
+{
+	u32 CtrlReg;
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+					XDCFG_CTRL_OFFSET);
+
+	XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+			(CtrlReg | Mask));
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function Clears the specified bit positions of the Control Register.
+*
+* @param	InstancePtr is a pointer to the XDcfg instance.
+* @param	Mask is the 32 bit value which holds the bit positions to be cleared.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask)
+{
+	u32 CtrlReg;
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+					XDCFG_CTRL_OFFSET);
+
+	XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
+			(CtrlReg & ~Mask));
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Control Register.
+*
+* @param	InstancePtr is a pointer to the XDcfg instance.
+*
+* @return	A 32-bit value representing the contents of the Control
+*		Register.
+*		Use the XDCFG_CTRL_*_MASK constants defined in xdevcfg_hw.h to
+*		interpret the returned value.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XDcfg_GetControlRegister(XDcfg *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Control Register and return the value.
+	 */
+	return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the contents of the Lock Register. These bits
+* can only be set to a 1. They will be cleared after a Power On Reset.
+*
+* @param	InstancePtr is a pointer to the XDcfg instance.
+* @param	Data is the 32 bit data to be written to the Register.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET, Data);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Lock Register.
+*
+* @param	InstancePtr is a pointer to the XDcfg instance.
+*
+* @return	A 32-bit value representing the contents of the Lock
+*		Register.
+*		Use the XDCFG_CR_*_MASK constants defined in xdevcfg_hw.h to
+*		interpret the returned value.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XDcfg_GetLockRegister(XDcfg *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Lock Register and return the value.
+	 */
+	return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the contents of the Configuration Register with the
+* given value.
+*
+* @param	InstancePtr is a pointer to the XDcfg instance.
+* @param	Data is the 32 bit data to be written to the Register.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET, Data);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Configuration Register with the
+* given value.
+*
+* @param	InstancePtr is a pointer to the XDcfg instance.
+*
+* @return	A 32-bit value representing the contents of the Config
+*		Register.
+*		Use the XDCFG_CFG_*_MASK constants defined in xdevcfg_hw.h to
+*		interpret the returned value.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the contents of the Status Register.
+*
+* @param	InstancePtr is a pointer to the XDcfg instance.
+* @param	Data is the 32 bit data to be written to the Register.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET, Data);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Status Register.
+*
+* @param	InstancePtr is a pointer to the XDcfg instance.
+*
+* @return	A 32-bit value representing the contents of the Status
+*		Register.
+*		Use the XDCFG_STATUS_*_MASK constants defined in
+*		xdevcfg_hw.h to interpret the returned value.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Status Register and return the value.
+	 */
+	return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the contents of the ROM Shadow Control Register.
+*
+* @param	InstancePtr is a pointer to the XDcfg instance.
+* @param	Data is the 32 bit data to be written to the Register.
+*
+* @return	None.
+*
+* @note		This register is can only be written and is used to control the
+*		RAM shadow of 32 bit 4K page ROM pages in user mode
+*
+*****************************************************************************/
+void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_ROM_SHADOW_OFFSET,
+				Data);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Software ID Register.
+*
+* @param	InstancePtr is a pointer to the XDcfg instance.
+*
+* @return	32 Bit boot software ID.
+*
+* @note		This register is locked for write once the system enters
+*		usermode. Hence API for reading the register only is provided.
+*
+*****************************************************************************/
+u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Software ID Register and return the value.
+	 */
+	return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_SW_ID_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the bit mask for the feature in Miscellaneous Control
+* Register.
+*
+* @param	InstancePtr is a pointer to the XDcfg instance.
+* @param	Mask is the bit-mask of the feature to be set.
+*
+* @return	None.
+*
+* @note		None
+*
+*****************************************************************************/
+void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask)
+{
+	u32 RegData;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+					XDCFG_MCTRL_OFFSET);
+
+	XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET,
+				(RegData | Mask));
+}
+
+/****************************************************************************/
+/**
+*
+* The function reads the contents of the Miscellaneous Control Register.
+*
+* @param	InstancePtr is a pointer to the XDcfg instance.
+*
+* @return	32 Bit boot software ID.
+*
+* @note		This register is locked for write once the system enters
+*		usermode. Hence API to reading the register only is provided.
+*
+*****************************************************************************/
+u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Miscellaneous Control Register and return the value.
+	 */
+	return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET);
+}
+
+/******************************************************************************/
+/**
+*
+* This function checks if DMA command queue is full.
+*
+* @param	InstancePtr is a pointer to the XDcfg instance.
+*
+* @return	XST_SUCCESS is the DMA is busy
+*		XST_FAILURE if the DMA is idle
+*
+* @note		The DMA queue has a depth of two.
+*
+****************************************************************************/
+u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr)
+{
+
+	u32 RegData;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Read the PCAP status register for DMA status */
+	RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+					XDCFG_STATUS_OFFSET);
+
+	if ((RegData & XDCFG_STATUS_DMA_CMD_Q_F_MASK) ==
+				XDCFG_STATUS_DMA_CMD_Q_F_MASK){
+		return XST_SUCCESS;
+	}
+
+	return XST_FAILURE;
+}
+
+/******************************************************************************/
+/**
+*
+* This function initiates the DMA transfer.
+*
+* @param	InstancePtr is a pointer to the XDcfg instance.
+* @param	SourcePtr contains a pointer to the source memory where the data
+*		is to be transferred from.
+* @param	SrcWordLength is the number of words (32 bit) to be transferred
+*		for the source transfer.
+* @param	DestPtr contains a pointer to the destination memory
+*		where the data is to be transferred to.
+* @param	DestWordLength is the number of words (32 bit) to be transferred
+*		for the Destination transfer.
+*
+* @return	None.
+*
+* @note		It is the responsibility of the caller function to ensure that
+*		correct values are passed to this function.
+*
+* 		The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination)
+*		address when equal to 2�b01 indicates the last DMA command of
+*		an overall transfer.
+*
+****************************************************************************/
+void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
+				u32 SrcWordLength, u32 DestWordLength)
+{
+
+	XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+				XDCFG_DMA_SRC_ADDR_OFFSET,
+				SourcePtr);
+
+	XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+				XDCFG_DMA_DEST_ADDR_OFFSET,
+				DestPtr);
+
+	XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+				XDCFG_DMA_SRC_LEN_OFFSET,
+				SrcWordLength);
+
+	XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+				XDCFG_DMA_DEST_LEN_OFFSET,
+				DestWordLength);
+}
+
+/******************************************************************************/
+/**
+*
+* This function Implements the DMA Read Command. This command is used to
+* transfer the image data from FPGA to the external memory.
+*
+* @param	InstancePtr is a pointer to the XDcfg instance.
+* @param	SourcePtr contains a pointer to the source memory where the data
+*		is to be transferred from.
+* @param	SrcWordLength is the number of words (32 bit) to be transferred
+*		for the source transfer.
+* @param	DestPtr contains a pointer to the destination memory
+*		where the data is to be transferred to.
+* @param	DestWordLength is the number of words (32 bit) to be transferred
+*		for the Destination transfer.
+*
+* @return	- XST_INVALID_PARAM if source address/length is invalid.
+*		- XST_SUCCESS if DMA transfer initiated properly.
+*
+* @note		None.
+*
+****************************************************************************/
+static u32 XDcfg_PcapReadback(XDcfg *InstancePtr, u32 SourcePtr,
+				u32 SrcWordLength, u32 DestPtr,
+				u32 DestWordLength)
+{
+	u32 IntrReg;
+
+	/*
+	 * Send READ Frame command to FPGA
+	 */
+	XDcfg_InitiateDma(InstancePtr, SourcePtr, XDCFG_DMA_INVALID_ADDRESS,
+				SrcWordLength, 0);
+
+	/*
+	 * Store the enabled interrupts to enable before the actual read
+	 * transfer is initiated and Disable all the interrupts temporarily.
+	 */
+	IntrReg = XDcfg_IntrGetEnabled(InstancePtr);
+	XDcfg_IntrDisable(InstancePtr, XDCFG_IXR_ALL_MASK);
+
+	/*
+	 * Wait till you get the DMA done for the read command sent
+	 */
+	 while ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+			XDCFG_INT_STS_OFFSET) &
+			XDCFG_IXR_D_P_DONE_MASK) !=
+			XDCFG_IXR_D_P_DONE_MASK);
+	/*
+	 * Enable the previously stored Interrupts .
+	 */
+	XDcfg_IntrEnable(InstancePtr, IntrReg);
+
+	/*
+	 * Initiate the DMA write command.
+	 */
+	XDcfg_InitiateDma(InstancePtr, XDCFG_DMA_INVALID_ADDRESS, (u32)DestPtr,
+				0, DestWordLength);
+
+	return XST_SUCCESS;
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function starts the DMA transfer. This function only starts the
+* operation and returns before the operation may be completed.
+* If the interrupt is enabled, an interrupt will be generated when the
+* operation is completed, otherwise it is necessary to poll the Status register
+* to determine when it is completed. It is the responsibility of the caller to
+* determine when the operation is completed by handling the generated interrupt
+* or polling the Status Register.
+*
+* @param	InstancePtr is a pointer to the XDcfg instance.
+* @param	SourcePtr contains a pointer to the source memory where the data
+*		is to be transferred from.
+* @param	SrcWordLength is the number of words (32 bit) to be transferred
+*		for the source transfer.
+* @param	DestPtr contains a pointer to the destination memory
+*		where the data is to be transferred to.
+* @param	DestWordLength is the number of words (32 bit) to be transferred
+*		for the Destination transfer.
+* @param	TransferType contains the type of PCAP transfer being requested.
+*		The definitions can be found in the xdevcfg.h file.
+* @return
+*		- XST_SUCCESS.if DMA transfer initiated successfully
+*		- XST_DEVICE_BUSY if DMA is busy
+*		- XST_INVALID_PARAM if invalid Source / Destination address
+*			is sent or an invalid Source / Destination length is
+*			sent
+*
+* @note		It is the responsibility of the caller to ensure that the cache
+*		is flushed and invalidated both before the DMA operation is
+*		started and after the DMA operation completes if the memory
+*		pointed to is  cached. The caller must also ensure that the
+*		pointers contain physical address rather than a virtual address
+*		if address translation is being used.
+*
+* 		The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination)
+*		address when equal to 2�b01 indicates the last DMA command of
+*		an overall transfer.
+*
+*****************************************************************************/
+u32 XDcfg_Transfer(XDcfg *InstancePtr,
+			void *SourcePtr, u32 SrcWordLength,
+			void *DestPtr, u32 DestWordLength,
+			u32 TransferType)
+{
+
+	u32 CtrlReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	if (XDcfg_IsDmaBusy(InstancePtr) == XST_SUCCESS) {
+		return XST_DEVICE_BUSY;
+	}
+
+	/*
+	 * Check whether the fabric is in initialized state
+	 */
+	if ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET)
+			& XDCFG_STATUS_PCFG_INIT_MASK) == 0) {
+		/*
+		 * We don't need to check PCFG_INIT to be high for
+		 * non-encrypted loopback transfers.
+		 */
+		if (TransferType != XDCFG_CONCURRENT_NONSEC_READ_WRITE) {
+			return XST_FAILURE;
+		}
+	}
+
+	if ((TransferType == XDCFG_SECURE_PCAP_WRITE) ||
+		(TransferType == XDCFG_NON_SECURE_PCAP_WRITE)) {
+
+		/* Check for valid source pointer and length */
+		if ((!SourcePtr) || (SrcWordLength == 0)) {
+			return XST_INVALID_PARAM;
+		}
+
+		/* Clear internal PCAP loopback */
+		CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+					XDCFG_MCTRL_OFFSET);
+		XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+				XDCFG_MCTRL_OFFSET, (CtrlReg &
+				~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
+
+		if (TransferType == XDCFG_NON_SECURE_PCAP_WRITE) {
+			/*
+			 * Clear QUARTER_PCAP_RATE_EN bit
+			 * so that the PCAP data is transmitted every clock
+			 */
+			CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+						XDCFG_CTRL_OFFSET);
+
+			XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+					XDCFG_CTRL_OFFSET, (CtrlReg &
+					  ~XDCFG_CTRL_PCAP_RATE_EN_MASK));
+
+		}
+		if (TransferType == XDCFG_SECURE_PCAP_WRITE) {
+			/*
+			 * AES engine handles only 8 bit data every clock cycle.
+			 * Hence, Encrypted PCAP data which is 32 bit data can
+			 * only be sent in every 4 clock cycles. Set the control
+			 * register QUARTER_PCAP_RATE_EN bit to achieve this
+			 * operation.
+			 */
+			XDcfg_SetControlRegister(InstancePtr,
+						XDCFG_CTRL_PCAP_RATE_EN_MASK);
+		}
+
+		XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr,
+				(u32)DestPtr, SrcWordLength, DestWordLength);
+
+	}
+
+	if (TransferType == XDCFG_PCAP_READBACK) {
+
+		if ((!DestPtr) || (DestWordLength == 0)) {
+
+			return XST_INVALID_PARAM;
+		}
+
+		/* Clear internal PCAP loopback */
+		CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+					XDCFG_MCTRL_OFFSET);
+		XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+				XDCFG_MCTRL_OFFSET, (CtrlReg &
+				~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
+
+		/*
+		 * For PCAP readback of FPGA configuration register or memory,
+		 * the read command is first sent (written) to the FPGA fabric
+		 * which responds by returning the required read data. Read data
+		 * from the FPGA is captured if pcap_radata_v is active.A DMA
+		 * read transfer is required to obtain the readback command,
+		 * which is then sent to the FPGA, followed by a DMA write
+		 * transfer to support this mode of operation.
+		 */
+		return XDcfg_PcapReadback(InstancePtr,
+					 (u32)SourcePtr, SrcWordLength,
+					 (u32)DestPtr, 	 DestWordLength);
+	}
+
+
+	if ((TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) ||
+		(TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE)) {
+
+		if ((!SourcePtr) || (SrcWordLength == 0) ||
+			(!DestPtr) || (DestWordLength == 0)) {
+			return XST_INVALID_PARAM;
+		}
+
+		if (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE) {
+			/* Enable internal PCAP loopback */
+			CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+					XDCFG_MCTRL_OFFSET);
+			XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+					XDCFG_MCTRL_OFFSET, (CtrlReg |
+					XDCFG_MCTRL_PCAP_LPBK_MASK));
+
+			/*
+			 * Clear QUARTER_PCAP_RATE_EN bit
+			 * so that the PCAP data is transmitted every clock
+			 */
+			CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+						XDCFG_CTRL_OFFSET);
+
+			XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+					XDCFG_CTRL_OFFSET, (CtrlReg &
+					  ~XDCFG_CTRL_PCAP_RATE_EN_MASK));
+
+		}
+		if (TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) {
+			/* Clear internal PCAP loopback */
+			CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+						XDCFG_MCTRL_OFFSET);
+			XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+					XDCFG_MCTRL_OFFSET, (CtrlReg &
+					~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
+
+			/*
+			 * Set the QUARTER_PCAP_RATE_EN bit
+			 * so that the PCAP data is transmitted every 4 clock
+			 * cycles, this is required for encrypted data.
+			 */
+			XDcfg_SetControlRegister(InstancePtr,
+					XDCFG_CTRL_PCAP_RATE_EN_MASK);
+		}
+
+		XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr,
+				(u32)DestPtr, SrcWordLength, DestWordLength);
+	}
+
+	return XST_SUCCESS;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg.h
new file mode 100644
index 0000000000000000000000000000000000000000..7fc1332a513a9181c17b712c7386a911657a61d4
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg.h
@@ -0,0 +1,399 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg.h
+* @addtogroup devcfg_v3_3
+* @{
+* @details
+*
+* The is the main header file for the Device Configuration Interface of the Zynq
+* device. The device configuration interface has three main functionality.
+*  1. AXI-PCAP
+*  2. Security Policy
+*  3. XADC
+* This current version of the driver supports only the AXI-PCAP and Security
+* Policy blocks. There is a separate driver for XADC.
+*
+* AXI-PCAP is used for download/upload an encrypted or decrypted bitstream.
+* DMA embedded in the AXI PCAP provides the master interface to
+* the Device configuration block for any DMA transfers. The data transfer can
+* take place between the Tx/RxFIFOs of AXI-PCAP and memory (on chip
+* RAM/DDR/peripheral memory).
+*
+* The current driver only supports the downloading the FPGA bitstream and
+* readback of the decrypted image (sort of loopback).
+* The driver does not know what information needs to be written to the FPGA to
+* readback FPGA configuration register or memory data. The application above the
+* driver should take care of creating the data that needs to be downloaded to
+* the FPGA so that the bitstream can be readback.
+* This driver also does not support the reading of the internal registers of the
+* PCAP. The driver has no knowledge of the PCAP internals.
+*
+* <b> Initialization and Configuration </b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Device Configuration device.
+*
+* XDcfg_CfgInitialize() API is used to initialize the Device Configuration
+* Interface. The user needs to first call the XDcfg_LookupConfig() API which
+* returns the Configuration structure pointer which is passed as a parameter to
+* the XDcfg_CfgInitialize() API.
+*
+* <b>Interrupts</b>
+* The Driver implements an interrupt handler to support the interrupts provided
+* by this interface.
+*
+* <b> Threads </b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* <b> Asserts </b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* <b> Building the driver </b>
+*
+* The XDcfg driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* <br><br>
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.00a nm  05/31/12 Updated the driver for CR 660835 so that input length for
+*		     source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
+*		     APIs is words (32 bit) and not bytes.
+* 		     Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
+*		     to add information that 2 LSBs of the Source/Destination
+*		     address when equal to 2�b01 indicate the last DMA command
+*		     of an overall transfer.
+*		     Destination Address passed to this API for secure transfers
+*		     instead of using 0xFFFFFFFF for CR 662197. This issue was
+*		     resulting in the failure of secure transfers of
+*		     non-bitstream images.
+* 2.01a nm  07/07/12 Updated the XDcfg_IntrClear function to directly
+*		     set the mask instead of oring it with the
+*		     value read from the interrupt status register
+* 		     Added defines for the PS Version bits,
+*	             removed the FIFO Flush bits from the
+*		     Miscellaneous Control Reg.
+*		     Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface
+*		     and XDcfg_SelectPcapInterface APIs for CR 643295
+*		     The user has to call the XDcfg_SelectIcapInterface API
+*		     for the PL reconfiguration using AXI HwIcap.
+*		     Updated the XDcfg_Transfer API to clear the
+*		     QUARTER_PCAP_RATE_EN bit in the control register for
+*		     non secure writes for CR 675543.
+* 2.02a nm  01/31/13 Fixed CR# 679335.
+* 		     Added Setting and Clearing the internal PCAP loopback.
+*		     Removed code for enabling/disabling AES engine as BootROM
+*		     locks down this setting.
+*		     Fixed CR# 681976.
+*		     Skip Checking the PCFG_INIT in case of non-secure DMA
+*		     loopback.
+*		     Fixed CR# 699558.
+*		     XDcfg_Transfer fails to transfer data in loopback mode.
+*		     Fixed CR# 701348.
+*                    Peripheral test fails with  Running
+* 		     DcfgSelfTestExample() in SECURE bootmode.
+* 2.03a nm  04/19/13 Fixed CR# 703728.
+*		     Updated the register definitions as per the latest TRM
+*		     version UG585 (v1.4) November 16, 2012.
+* 3.0   adk 10/12/13 Updated as per the New Tcl API's
+* 3.0   kpc 21/02/14 Added function prototype for XDcfg_ClearControlRegister
+* 3.2   sb  08/25/14 Fixed XDcfg_PcapReadback() function
+*		     updated driver code with != instead of ==,
+*		     while checking for Interrupt Status with DMA and
+*		     PCAP Done Mask
+*		     ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+*			XDCFG_INT_STS_OFFSET) &
+*			XDCFG_IXR_D_P_DONE_MASK) !=
+*			XDCFG_IXR_D_P_DONE_MASK);
+*		     A new example has been added to read back the
+*		     configuration registers from the PL region.
+*		     xdevcfg_reg_readback_example.c
+* 3.3   sk  04/06/15 Modified XDcfg_ReadMultiBootConfig Macro CR# 851335.
+*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+*                    generation.
+*
+* </pre>
+*
+******************************************************************************/
+#ifndef XDCFG_H		/* prevent circular inclusions */
+#define XDCFG_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg_hw.h"
+#include "xstatus.h"
+#include "xil_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/* Types of PCAP transfers */
+
+#define XDCFG_NON_SECURE_PCAP_WRITE		1
+#define XDCFG_SECURE_PCAP_WRITE			2
+#define XDCFG_PCAP_READBACK			3
+#define XDCFG_CONCURRENT_SECURE_READ_WRITE	4
+#define XDCFG_CONCURRENT_NONSEC_READ_WRITE	5
+
+
+/**************************** Type Definitions *******************************/
+/**
+* The handler data type allows the user to define a callback function to
+* respond to interrupt events in the system. This function is executed
+* in interrupt context, so amount of processing should be minimized.
+*
+* @param	CallBackRef is the callback reference passed in by the upper
+*		layer when setting the callback functions, and passed back to
+*		the upper layer when the callback is invoked. Its type is
+*		unimportant to the driver component, so it is a void pointer.
+* @param	Status is the Interrupt status of the XDcfg device.
+*/
+typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID of device */
+	u32 BaseAddr;		/**< Base address of the device */
+} XDcfg_Config;
+
+/**
+ * The XDcfg driver instance data.
+ */
+typedef struct {
+	XDcfg_Config Config;	/**< Hardware Configuration */
+	u32 IsReady;		/**< Device is initialized and ready */
+	u32 IsStarted;		/**< Device Configuration Interface
+				  * is running
+				  */
+	XDcfg_IntrHandler StatusHandler;  /* Event handler function */
+	void *CallBackRef;	/* Callback reference for event handler */
+} XDcfg;
+
+/****************************************************************************/
+/**
+*
+* Unlock the Device Config Interface block.
+*
+* @param	InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XDcfg_Unlock(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_Unlock(InstancePtr)					\
+	XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, 			\
+	XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA)
+
+
+
+/****************************************************************************/
+/**
+*
+* Get the version number of the PS from the Miscellaneous Control Register.
+*
+* @param	InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return	Version of the PS.
+*
+* @note		C-style signature:
+*		void XDcfg_GetPsVersion(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_GetPsVersion(InstancePtr)					\
+	((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, 		\
+			XDCFG_MCTRL_OFFSET)) & 				\
+			XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> 		\
+			XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
+
+
+
+/****************************************************************************/
+/**
+*
+* Read the multiboot config register value.
+*
+* @param	InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_ReadMultiBootConfig(InstancePtr)			\
+	XDcfg_ReadReg((InstancePtr)->Config.BaseAddr,  		\
+			XDCFG_MULTIBOOT_ADDR_OFFSET)
+
+
+/****************************************************************************/
+/**
+*
+* Selects ICAP interface for reconfiguration after the initial configuration
+* of the PL.
+*
+* @param	InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XDcfg_SelectIcapInterface(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_SelectIcapInterface(InstancePtr)				  \
+	XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET,   \
+	((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
+	& ( ~XDCFG_CTRL_PCAP_PR_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Selects PCAP interface for reconfiguration after the initial configuration
+* of the PL.
+*
+* @param	InstancePtr is a pointer to the instance of XDcfg driver.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XDcfg_SelectPcapInterface(XDcfg* InstancePtr)
+*
+*****************************************************************************/
+#define XDcfg_SelectPcapInterface(InstancePtr)				   \
+	XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET,    \
+	((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET))  \
+	| XDCFG_CTRL_PCAP_PR_MASK))
+
+
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xdevcfg_sinit.c.
+ */
+XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xdevcfg_selftest.c
+ */
+int XDcfg_SelfTest(XDcfg *InstancePtr);
+
+/*
+ * Interface functions in xdevcfg.c
+ */
+int XDcfg_CfgInitialize(XDcfg *InstancePtr,
+			 XDcfg_Config *ConfigPtr, u32 EffectiveAddress);
+
+void XDcfg_EnablePCAP(XDcfg *InstancePtr);
+
+void XDcfg_DisablePCAP(XDcfg *InstancePtr);
+
+void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_GetControlRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetLockRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data);
+
+u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr);
+
+void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr);
+
+u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr);
+
+void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
+				u32 SrcWordLength, u32 DestWordLength);
+
+u32 XDcfg_Transfer(XDcfg *InstancePtr,
+				void *SourcePtr, u32 SrcWordLength,
+				void *DestPtr, u32 DestWordLength,
+				u32 TransferType);
+
+/*
+ * Interrupt related function prototypes implemented in xdevcfg_intr.c
+ */
+void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask);
+
+u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr);
+
+u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr);
+
+void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask);
+
+void XDcfg_InterruptHandler(XDcfg *InstancePtr);
+
+void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
+				void *CallBackRef);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_g.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..938489f6b88c70335afcdc1818e113924a304681
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xdevcfg.h"
+
+/*
+* The configuration table for devices
+*/
+
+XDcfg_Config XDcfg_ConfigTable[] =
+{
+	{
+		XPAR_PS7_DEV_CFG_0_DEVICE_ID,
+		XPAR_PS7_DEV_CFG_0_BASEADDR
+	}
+};
+
+
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_hw.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_hw.c
new file mode 100644
index 0000000000000000000000000000000000000000..8a3095de33d9a5bc29aaec1ae993a87b9974fdbb
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_hw.c
@@ -0,0 +1,113 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg_hw.c
+* @addtogroup devcfg_v3_3
+* @{
+*
+* This file contains the implementation of the interface reset functionality
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 2.04a kpc 10/07/13 First release
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg_hw.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given devcfg interface by
+* configuring the appropriate control bits in the devcfg specifc registers
+* the devcfg reset squence involves the following steps
+*	Disable all the interuupts
+*	Clear the status
+*	Update relevant config registers with reset values
+*	Disbale the looopback mode and pcap rate enable
+*
+* @param   BaseAddress of the interface
+*
+* @return N/A
+*
+* @note
+* This function will not modify the slcr registers that are relavant for
+* devcfg controller
+******************************************************************************/
+void XDcfg_ResetHw(u32 BaseAddr)
+{
+	u32 Regval = 0;
+
+	/* Mask the interrupts  */
+	XDcfg_WriteReg(BaseAddr, XDCFG_INT_MASK_OFFSET,
+			XDCFG_IXR_ALL_MASK);
+	/* Clear the interuupt status */
+	Regval = XDcfg_ReadReg(BaseAddr, XDCFG_INT_STS_OFFSET);
+	XDcfg_WriteReg(BaseAddr, XDCFG_INT_STS_OFFSET, Regval);
+	/* Clear the source address register */
+	XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_ADDR_OFFSET, 0x0);
+	/* Clear the destination address register */
+	XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_ADDR_OFFSET, 0x0);
+	/* Clear the source length register */
+	XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_LEN_OFFSET, 0x0);
+	/* Clear the destination length register */
+	XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_LEN_OFFSET, 0x0);
+	/* Clear the loopback enable bit */
+	Regval = XDcfg_ReadReg(BaseAddr, XDCFG_MCTRL_OFFSET);
+	Regval = Regval & ~XDCFG_MCTRL_PCAP_LPBK_MASK;
+	XDcfg_WriteReg(BaseAddr, XDCFG_MCTRL_OFFSET, Regval);
+	/*Reset the configuration register to reset value */
+	XDcfg_WriteReg(BaseAddr, XDCFG_CFG_OFFSET,
+				XDCFG_CONFIG_RESET_VALUE);
+	/*Disable the PCAP rate enable bit */
+	Regval = XDcfg_ReadReg(BaseAddr, XDCFG_CTRL_OFFSET);
+	Regval = Regval & ~XDCFG_CTRL_PCAP_RATE_EN_MASK;
+	XDcfg_WriteReg(BaseAddr, XDCFG_CTRL_OFFSET, Regval);
+
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..c506ca59fc936b96086d96b074f85bee0959c104
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_hw.h
@@ -0,0 +1,395 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg_hw.h
+* @addtogroup devcfg_v3_3
+* @{
+*
+* This file contains the hardware interface to the Device Config Interface.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.01a nm  08/01/12 Added defines for the PS Version bits,
+*	             removed the FIFO Flush bits from the
+*		     Miscellaneous Control Reg
+* 2.03a nm  04/19/13 Fixed CR# 703728.
+*		     Updated the register definitions as per the latest TRM
+*		     version UG585 (v1.4) November 16, 2012.
+* 2.04a	kpc	10/07/13 Added function prototype.
+* 3.00a	kpc	25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
+* </pre>
+*
+******************************************************************************/
+#ifndef XDCFG_HW_H		/* prevent circular inclusions */
+#define XDCFG_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device
+ * @{
+ */
+
+#define XDCFG_CTRL_OFFSET		0x00 /**< Control Register */
+#define XDCFG_LOCK_OFFSET		0x04 /**< Lock Register */
+#define XDCFG_CFG_OFFSET		0x08 /**< Configuration Register */
+#define XDCFG_INT_STS_OFFSET		0x0C /**< Interrupt Status Register */
+#define XDCFG_INT_MASK_OFFSET		0x10 /**< Interrupt Mask Register */
+#define XDCFG_STATUS_OFFSET		0x14 /**< Status Register */
+#define XDCFG_DMA_SRC_ADDR_OFFSET	0x18 /**< DMA Source Address Register */
+#define XDCFG_DMA_DEST_ADDR_OFFSET	0x1C /**< DMA Destination Address Reg */
+#define XDCFG_DMA_SRC_LEN_OFFSET	0x20 /**< DMA Source Transfer Length */
+#define XDCFG_DMA_DEST_LEN_OFFSET	0x24 /**< DMA Destination Transfer */
+#define XDCFG_ROM_SHADOW_OFFSET		0x28 /**< DMA ROM Shadow Register */
+#define XDCFG_MULTIBOOT_ADDR_OFFSET	0x2C /**< Multi BootAddress Pointer */
+#define XDCFG_SW_ID_OFFSET		0x30 /**< Software ID Register */
+#define XDCFG_UNLOCK_OFFSET		0x34 /**< Unlock Register */
+#define XDCFG_MCTRL_OFFSET		0x80 /**< Miscellaneous Control Reg */
+
+/* @} */
+
+/** @name Control Register Bit definitions
+  * @{
+ */
+
+#define XDCFG_CTRL_FORCE_RST_MASK	0x80000000 /**< Force  into
+						     * Secure Reset
+						     */
+#define XDCFG_CTRL_PCFG_PROG_B_MASK	0x40000000 /**< Program signal to
+						     *  Reset FPGA
+						     */
+#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK	0x20000000 /**< Control PL POR timer */
+#define XDCFG_CTRL_PCAP_PR_MASK	  	0x08000000 /**< Enable PCAP for PR */
+#define XDCFG_CTRL_PCAP_MODE_MASK	0x04000000 /**< Enable PCAP */
+#define XDCFG_CTRL_PCAP_RATE_EN_MASK	0x02000000 /**< Enable PCAP send data
+						     *  to FPGA every 4 PCAP
+						     *  cycles
+						     */
+#define XDCFG_CTRL_MULTIBOOT_EN_MASK	0x01000000 /**< Multiboot Enable */
+#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK	0x00800000 /**< JTAG Chain Disable */
+#define XDCFG_CTRL_USER_MODE_MASK	0x00008000 /**< User Mode Mask */
+#define XDCFG_CTRL_PCFG_AES_FUSE_MASK	0x00001000 /**< AES key source */
+#define XDCFG_CTRL_PCFG_AES_EN_MASK	0x00000E00 /**< AES Enable Mask */
+#define XDCFG_CTRL_SEU_EN_MASK		0x00000100 /**< SEU Enable Mask */
+#define XDCFG_CTRL_SEC_EN_MASK		0x00000080 /**< Secure/Non Secure
+						     *  Status mask
+						     */
+#define XDCFG_CTRL_SPNIDEN_MASK		0x00000040 /**< Secure Non Invasive
+						     *  Debug Enable
+						     */
+#define XDCFG_CTRL_SPIDEN_MASK		0x00000020 /**< Secure Invasive
+						     *  Debug Enable
+						     */
+#define XDCFG_CTRL_NIDEN_MASK		0x00000010 /**< Non-Invasive Debug
+						     *  Enable
+						     */
+#define XDCFG_CTRL_DBGEN_MASK		0x00000008 /**< Invasive Debug
+						     *  Enable
+						     */
+#define XDCFG_CTRL_DAP_EN_MASK		0x00000007 /**< DAP Enable Mask */
+
+/* @} */
+
+/** @name Lock register bit definitions
+  * @{
+ */
+
+#define XDCFG_LOCK_AES_EFUSE_MASK	0x00000010 /**< Lock AES Efuse bit */
+#define XDCFG_LOCK_AES_EN_MASK		0x00000008 /**< Lock AES_EN update */
+#define XDCFG_LOCK_SEU_MASK		0x00000004 /**< Lock SEU_En update */
+#define XDCFG_LOCK_SEC_MASK		0x00000002 /**< Lock SEC_EN and
+						     *  USER_MODE
+						     */
+#define XDCFG_LOCK_DBG_MASK		0x00000001 /**< This bit locks
+						     *  security config
+						     *  including: DAP_En,
+						     *  DBGEN,,
+						     *  NIDEN, SPNIEN
+						     */
+/*@}*/
+
+
+
+/** @name Config Register Bit definitions
+  * @{
+ */
+#define XDCFG_CFG_RFIFO_TH_MASK	  	0x00000C00 /**< Read FIFO
+						     *  Threshold Mask
+						     */
+#define XDCFG_CFG_WFIFO_TH_MASK	  	0x00000300 /**< Write FIFO Threshold
+						     *  Mask
+						     */
+#define XDCFG_CFG_RCLK_EDGE_MASK	0x00000080 /**< Read data active
+						     *  clock edge
+						     */
+#define XDCFG_CFG_WCLK_EDGE_MASK	0x00000040 /**< Write data active
+						     *  clock edge
+						     */
+#define XDCFG_CFG_DISABLE_SRC_INC_MASK	0x00000020 /**< Disable Source address
+						     *  increment mask
+						     */
+#define XDCFG_CFG_DISABLE_DST_INC_MASK	0x00000010 /**< Disable Destination
+						     *  address increment
+						     *  mask
+						     */
+/* @} */
+
+
+/** @name Interrupt Status/Mask Register Bit definitions
+  * @{
+ */
+#define XDCFG_IXR_PSS_GTS_USR_B_MASK	0x80000000 /**< Tri-state IO during
+						     *  HIZ
+						     */
+#define XDCFG_IXR_PSS_FST_CFG_B_MASK	0x40000000 /**< First configuration
+						     *  done
+						     */
+#define XDCFG_IXR_PSS_GPWRDWN_B_MASK	0x20000000 /**< Global power down */
+#define XDCFG_IXR_PSS_GTS_CFG_B_MASK	0x10000000 /**< Tri-state IO during
+						     *  configuration
+						     */
+#define XDCFG_IXR_PSS_CFG_RESET_B_MASK	0x08000000 /**< PL configuration
+						     *  reset
+						     */
+#define XDCFG_IXR_AXI_WTO_MASK		0x00800000 /**< AXI Write Address
+						     *  or Data or response
+						     *  timeout
+						     */
+#define XDCFG_IXR_AXI_WERR_MASK		0x00400000 /**< AXI Write response
+						     *  error
+						     */
+#define XDCFG_IXR_AXI_RTO_MASK		0x00200000 /**< AXI Read Address or
+						     *  response timeout
+						     */
+#define XDCFG_IXR_AXI_RERR_MASK		0x00100000 /**< AXI Read response
+						     *  error
+						     */
+#define XDCFG_IXR_RX_FIFO_OV_MASK	0x00040000 /**< Rx FIFO Overflow */
+#define XDCFG_IXR_WR_FIFO_LVL_MASK	0x00020000 /**< Tx FIFO less than
+						     *  threshold */
+#define XDCFG_IXR_RD_FIFO_LVL_MASK	0x00010000 /**< Rx FIFO greater than
+						     *  threshold */
+#define XDCFG_IXR_DMA_CMD_ERR_MASK	0x00008000 /**< Illegal DMA command */
+#define XDCFG_IXR_DMA_Q_OV_MASK		0x00004000 /**< DMA command queue
+						     *  overflow
+						     */
+#define XDCFG_IXR_DMA_DONE_MASK		0x00002000 /**< DMA Command Done */
+#define XDCFG_IXR_D_P_DONE_MASK		0x00001000 /**< DMA and PCAP
+						     *  transfers Done
+						     */
+#define XDCFG_IXR_P2D_LEN_ERR_MASK	0x00000800 /**< PCAP to DMA transfer
+						     *  length error
+						     */
+#define XDCFG_IXR_PCFG_HMAC_ERR_MASK	0x00000040 /**< HMAC error mask */
+#define XDCFG_IXR_PCFG_SEU_ERR_MASK	0x00000020 /**< SEU Error mask */
+#define XDCFG_IXR_PCFG_POR_B_MASK	0x00000010 /**< FPGA POR mask */
+#define XDCFG_IXR_PCFG_CFG_RST_MASK	0x00000008 /**< FPGA Reset mask */
+#define XDCFG_IXR_PCFG_DONE_MASK	0x00000004 /**< Done Signal  Mask */
+#define XDCFG_IXR_PCFG_INIT_PE_MASK	0x00000002 /**< Detect Positive edge
+						     *  of Init Signal
+						     */
+#define XDCFG_IXR_PCFG_INIT_NE_MASK  	0x00000001 /**< Detect Negative edge
+						     *  of Init Signal
+						     */
+#define XDCFG_IXR_ERROR_FLAGS_MASK		(XDCFG_IXR_AXI_WTO_MASK | \
+						XDCFG_IXR_AXI_WERR_MASK | \
+						XDCFG_IXR_AXI_RTO_MASK |  \
+						XDCFG_IXR_AXI_RERR_MASK | \
+						XDCFG_IXR_RX_FIFO_OV_MASK | \
+						XDCFG_IXR_DMA_CMD_ERR_MASK |\
+						XDCFG_IXR_DMA_Q_OV_MASK |   \
+						XDCFG_IXR_P2D_LEN_ERR_MASK |\
+						XDCFG_IXR_PCFG_HMAC_ERR_MASK)
+
+
+#define XDCFG_IXR_ALL_MASK			0x00F7F8EF
+
+
+
+/* @} */
+
+
+/** @name Status Register Bit definitions
+  * @{
+ */
+#define XDCFG_STATUS_DMA_CMD_Q_F_MASK	0x80000000 /**< DMA command
+						     *  Queue full
+						     */
+#define XDCFG_STATUS_DMA_CMD_Q_E_MASK	0x40000000 /**< DMA command
+						     *  Queue empty
+						     */
+#define XDCFG_STATUS_DMA_DONE_CNT_MASK	0x30000000 /**< Number of
+						     *  completed DMA
+						     *  transfers
+						     */
+#define XDCFG_STATUS_RX_FIFO_LVL_MASK	0x01F000000 /**< Rx FIFO level */
+#define XDCFG_STATUS_TX_FIFO_LVL_MASK	0x0007F000  /**< Tx FIFO level */
+
+#define XDCFG_STATUS_PSS_GTS_USR_B	0x00000800  /**< Tri-state IO
+						      *  during HIZ
+						      */
+#define XDCFG_STATUS_PSS_FST_CFG_B	0x00000400  /**< First PL config
+						      *  done
+						      */
+#define XDCFG_STATUS_PSS_GPWRDWN_B	0x00000200  /**< Global power down */
+#define XDCFG_STATUS_PSS_GTS_CFG_B	0x00000100  /**< Tri-state IO during
+						      *  config
+						      */
+#define XDCFG_STATUS_SECURE_RST_MASK	0x00000080  /**< Secure Reset
+						      *  POR Status
+						      */
+#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 	0x00000040 /**< Illegal APB
+							     *  access
+							     */
+#define XDCFG_STATUS_PSS_CFG_RESET_B		0x00000020 /**< PL config
+							     *  reset status
+							     */
+#define XDCFG_STATUS_PCFG_INIT_MASK		0x00000010 /**< FPGA Init
+							     *  Status
+							     */
+#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK	0x00000008
+							   /**< BBRAM key
+							     *  disable
+							     */
+#define XDCFG_STATUS_EFUSE_SEC_EN_MASK		0x00000004 /**< Efuse Security
+							     *  Enable Status
+							     */
+#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK	0x00000002 /**< EFuse JTAG
+							     *  Disable
+							     *  status
+							     */
+/* @} */
+
+
+/** @name DMA Source/Destination Transfer Length Register Bit definitions
+ * @{
+ */
+#define XDCFG_DMA_LEN_MASK		0x7FFFFFF /**< Length Mask */
+/*@}*/
+
+
+
+
+/** @name Miscellaneous Control  Register Bit definitions
+  * @{
+ */
+#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK  0xF0000000 /**< PS Version Mask */
+#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28	     /**< PS Version Shift */
+#define XDCFG_MCTRL_PCAP_LPBK_MASK	  0x00000010 /**< PCAP loopback mask */
+/* @} */
+
+/** @name FIFO Threshold Bit definitions
+  * @{
+ */
+
+#define XDCFG_CFG_FIFO_QUARTER		0x0	 /**< Quarter empty */
+#define XDCFG_CFG_FIFO_HALF		0x1	 /**< Half empty */
+#define XDCFG_CFG_FIFO_3QUARTER		0x2	 /**< 3/4 empty */
+#define XDCFG_CFG_FIFO_EMPTY		0x4	 /**< Empty */
+/* @}*/
+
+
+/* Miscellaneous constant values */
+#define XDCFG_DMA_INVALID_ADDRESS	0xFFFFFFFF  /**< Invalid DMA address */
+#define XDCFG_UNLOCK_DATA		0x757BDF0D  /**< First APB access data*/
+#define XDCFG_BASE_ADDRESS		0xF8007000  /**< Device Config base
+						      * address
+						      */
+#define XDCFG_CONFIG_RESET_VALUE	0x508	/**< Config reg reset value */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param	BaseAddr is the base address of the device
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note		C-style signature:
+*		u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XDcfg_ReadReg(BaseAddr, RegOffset)		\
+	Xil_In32((BaseAddr) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write to the given register.
+*
+* @param	BaseAddr is the base address of the device
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XDcfg_WriteReg(BaseAddr, RegOffset, Data)	\
+	Xil_Out32((BaseAddr) + (RegOffset), (Data))
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the devcfg interface
+ */
+void XDcfg_ResetHw(u32 BaseAddr);
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_intr.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_intr.c
new file mode 100644
index 0000000000000000000000000000000000000000..55bbde2f04525ba680b5ee6350aff225c0143354
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_intr.c
@@ -0,0 +1,310 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg_intr.c
+* @addtogroup devcfg_v3_3
+* @{
+*
+* Contains the implementation of interrupt related functions of the XDcfg
+* driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.01a nm  07/07/12 Updated the XDcfg_IntrClear function to directly
+*		     set the mask instead of oring it with the
+*		     value read from the interrupt status register
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified interrupts in the device.
+*
+* @param	InstancePtr is a pointer to the XDcfg instance.
+* @param	Mask is the bit-mask of the interrupts to be enabled.
+*		Bit positions of 1 will be enabled. Bit positions of 0 will
+*		keep the previous setting. This mask is formed by OR'ing
+*		XDCFG_INT_* bits defined in xdevcfg_hw.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Enable the specified interrupts in the Interrupt Mask Register.
+	 */
+	RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+				    XDCFG_INT_MASK_OFFSET);
+	RegValue &= ~(Mask & XDCFG_IXR_ALL_MASK);
+	XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+				XDCFG_INT_MASK_OFFSET,
+				RegValue);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function disables the specified interrupts in the device.
+*
+* @param	InstancePtr is a pointer to the XDcfg instance.
+* @param	Mask is the bit-mask of the interrupts to be disabled.
+*		Bit positions of 1 will be disabled. Bit positions of 0 will
+*		keep the previous setting. This mask is formed by OR'ing
+*		XDCFG_INT_* bits defined in xdevcfg_hw.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Disable the specified interrupts in the Interrupt Mask Register.
+	 */
+	RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+				    XDCFG_INT_MASK_OFFSET);
+	RegValue |= (Mask & XDCFG_IXR_ALL_MASK);
+	XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+				XDCFG_INT_MASK_OFFSET,
+				RegValue);
+}
+/****************************************************************************/
+/**
+*
+* This function returns the enabled interrupts read from the Interrupt Mask
+* Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h
+* to interpret the returned value.
+*
+* @param	InstancePtr is a pointer to the XDcfg instance.
+*
+* @return	A 32-bit value representing the contents of the IMR.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Return the value read from the Interrupt Mask Register.
+	 */
+	return (~ XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+				XDCFG_INT_MASK_OFFSET));
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the interrupt status read from Interrupt Status
+* Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h
+* to interpret the returned value.
+*
+* @param	InstancePtr is a pointer to the XDcfg instance.
+*
+* @return	A 32-bit value representing the contents of the Interrupt
+*		Status register.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Return the value read from the Interrupt Status register.
+	 */
+	return XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+				XDCFG_INT_STS_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears the specified interrupts in the Interrupt Status
+* Register.
+*
+* @param	InstancePtr is a pointer to the XDcfg instance.
+* @param	Mask is the bit-mask of the interrupts to be cleared.
+*		Bit positions of 1 will be cleared. Bit positions of 0 will not
+* 		change the previous interrupt status. This mask is formed by
+* 		OR'ing XDCFG_INT_* bits which are defined in xdevcfg_hw.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+				XDCFG_INT_STS_OFFSET,
+				Mask);
+
+}
+
+/*****************************************************************************/
+/**
+* The interrupt handler for the Device Config Interface.
+*
+* Events are signaled to upper layer for proper handling.
+*
+*
+* @param	InstancePtr is a pointer to the XDcfg instance.
+*
+* @return	None.
+*
+* @note 	None.
+*
+****************************************************************************/
+void XDcfg_InterruptHandler(XDcfg *InstancePtr)
+{
+	u32 IntrStatusReg;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Interrupt status register.
+	 */
+	IntrStatusReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+					 XDCFG_INT_STS_OFFSET);
+
+	/*
+	 * Write the status back to clear the interrupts so that no
+	 * subsequent interrupts are missed while processing this interrupt.
+	 * This also does the DMA acknowledgment automatically.
+	 */
+	XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
+				XDCFG_INT_STS_OFFSET, IntrStatusReg);
+
+	/*
+	 * Signal application that there are events to handle.
+	 */
+	InstancePtr->StatusHandler(InstancePtr->CallBackRef,
+					   IntrStatusReg);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the handler that will be called when an event (interrupt)
+* occurs that needs application's attention.
+*
+* @param	InstancePtr is a pointer to the XDcfg instance
+* @param	CallBackFunc is the address of the callback function.
+* @param	CallBackRef is a user data item that will be passed to the
+*		callback function when it is invoked.
+*
+* @return	None.
+*
+* @note		None.
+*
+*
+*****************************************************************************/
+void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
+				void *CallBackRef)
+{
+	/*
+	 * Asserts validate the input arguments
+	 * CallBackRef not checked, no way to know what is valid
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(CallBackFunc != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->StatusHandler = (XDcfg_IntrHandler) CallBackFunc;
+	InstancePtr->CallBackRef = CallBackRef;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_selftest.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_selftest.c
new file mode 100644
index 0000000000000000000000000000000000000000..7159782e15045b1b598ac3e5728cf0a15d68f6c6
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_selftest.c
@@ -0,0 +1,114 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdevcfg_selftest.c
+* @addtogroup devcfg_v3_3
+* @{
+*
+* Contains diagnostic self-test functions for the XDcfg driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.02a nm  02/27/13 Fixed CR# 701348.
+*                    Peripheral test fails with  Running
+* 		     DcfgSelfTestExample() in SECURE bootmode.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Run a self-test on the Device Configuration Interface. This test does a
+* control register write and reads back the same value.
+*
+* @param	InstancePtr is a pointer to the XDcfg instance.
+*
+* @return
+*		- XST_SUCCESS if self-test was successful.
+*		- XST_FAILURE if fails.
+*
+* @note		None.
+*
+******************************************************************************/
+int XDcfg_SelfTest(XDcfg *InstancePtr)
+{
+	u32 OldCfgReg;
+	u32 CfgReg;
+	int Status = XST_SUCCESS;
+
+	/*
+	 * Assert to ensure the inputs are valid and the instance has been
+	 * initialized.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	OldCfgReg = XDcfg_GetControlRegister(InstancePtr);
+
+	XDcfg_SetControlRegister(InstancePtr, XDCFG_CTRL_NIDEN_MASK);
+
+	CfgReg = XDcfg_GetControlRegister(InstancePtr);
+
+	if ((CfgReg & XDCFG_CTRL_NIDEN_MASK) != XDCFG_CTRL_NIDEN_MASK) {
+
+		Status = XST_FAILURE;
+	}
+
+	/*
+	 * Restore the original values of the register
+	 */
+	XDcfg_SetControlRegister(InstancePtr, OldCfgReg);
+
+	return Status;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_sinit.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..d0d0e6d9966151bd81ede9c82e1deb2a48153ae7
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_sinit.c
@@ -0,0 +1,93 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xdevcfg_sinit.c
+* @addtogroup devcfg_v3_3
+* @{
+*
+* This file contains method for static initialization (compile-time) of the
+* driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdevcfg.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId is the unique device ID of the device being looked up.
+*
+* @return	A pointer to the configuration table entry corresponding to the
+*		given device ID, or NULL if no match is found.
+*
+* @note		None.
+*
+******************************************************************************/
+XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId)
+{
+	extern XDcfg_Config XDcfg_ConfigTable[];
+	XDcfg_Config *CfgPtr = NULL;
+	int Index;
+
+	for (Index = 0; Index < XPAR_XDCFG_NUM_INSTANCES; Index++) {
+		if (XDcfg_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XDcfg_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (CfgPtr);
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/Makefile b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..d1240c586cd64556950a7826e73c46719a2ce887
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/Makefile
@@ -0,0 +1,41 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xdmaps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling dmaps"
+
+xdmaps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xdmaps_includes
+
+xdmaps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
+
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.c
new file mode 100644
index 0000000000000000000000000000000000000000..cb0d62a6feb7e6abb02eba853eaee55eb75f39cc
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.c
@@ -0,0 +1,1982 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal 
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps.c
+* @addtogroup dmaps_v2_1
+* @{
+*
+* This file contains the implementation of the interface functions for XDmaPs
+* driver. Refer to the header file xdmaps.h for more detailed information.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  	Date     Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	hbm    08/19/2010 First Release
+* 1.00  nm     05/25/2011 Updated for minor doxygen corrections
+* 1.02a sg     05/16/2012 Made changes for doxygen and moved some function
+*			  header from the xdmaps.h file to xdmaps.c file
+*			  Other cleanup for coding guidelines and CR 657109
+*			  and CR 657898
+* 1.03a sg     07/16/2012 changed inline to __inline for CR665681
+* 1.04a nm     10/22/2012 Fixed CR# 681671.
+* 1.05a nm     04/15/2013 Fixed CR# 704396. Removed warnings when compiled
+*			  with -Wall and -Wextra option in bsp.
+*	       05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
+*			  function description.
+*			  Fixed CR# 704396. Removed unused variables
+*			  UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
+*			  function.
+* 1.07a asa    11/02/13. Made changes to fix compilation issues for iarcc.
+*			   Removed the PDBG prints. By default they were always
+*			   defined out and never used. The PDBG is non-standard for
+*			   Xilinx drivers and no other driver does something similar.
+*			   Since there is no easy way to fix compilation issues with
+*			   the IARCC compiler around PDBG, it is better to remove it.
+*			   Users can always use xil_printfs if they want to debug.
+* 2.01 kpc    08/23/14   Fixed the IAR compiler reported errors
+* 2.2  mus    12/08/16   Remove definition of INLINE macro to avoid re-definition,
+*                         since it is being defined in xil_io.h
+* 2.3 kpc     14/10/16   Fixed the compiler error when optimization O0 is used.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include <string.h>
+
+#include "xstatus.h"
+#include "xdmaps.h"
+#include "xil_io.h"
+#include "xil_cache.h"
+
+#include "xil_printf.h"
+
+
+/************************** Constant Definitions ****************************/
+
+/* The following constant defines the amount of error that is allowed for
+ * a specified baud rate. This error is the difference between the actual
+ * baud rate that will be generated using the specified clock and the
+ * desired baud rate.
+ */
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+static int XDmaPs_Exec_DMAKILL(u32 BaseAddr,
+				unsigned int Channel,
+				unsigned int Thread);
+
+static void XDmaPs_BufPool_Free(XDmaPs_ProgBuf *Pool, void *Buf);
+
+static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg);
+
+static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel);
+static void *XDmaPs_BufPool_Allocate(XDmaPs_ProgBuf *Pool);
+static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
+				unsigned CacheLength);
+
+static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length);
+
+
+
+/************************** Variable Definitions ****************************/
+
+/****************************************************************************/
+/**
+*
+* Initializes a specific XDmaPs instance such that it is ready to be used.
+* The data format of the device is setup for 8 data bits, 1 stop bit, and no
+* parity by default. The baud rate is set to a default value specified by
+* Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The
+* receive FIFO threshold is set for 8 bytes. The default operating mode of the
+* driver is polled mode.
+*
+* @param	InstPtr is a pointer to the XDmaPs instance.
+* @param	Config is a reference to a structure containing information
+*		about a specific XDmaPs driver.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the
+*		address mapping from EffectiveAddr to the device physical base
+*		address unchanged once this function is invoked. Unexpected
+*		errors may occur if the address mapping changes after this
+*		function is called. If address translation is not used, pass in
+*		the physical address instead.
+*
+* @return
+*
+*		- XST_SUCCESS on initialization completion
+*
+* @note		None.
+*
+*****************************************************************************/
+int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
+			  XDmaPs_Config *Config,
+			  u32 EffectiveAddr)
+{
+	int Status = XST_SUCCESS;
+	unsigned int CacheLength = 0;
+	u32 CfgReg;
+	unsigned Channel;
+	XDmaPs_ChannelData *ChanData;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertNonvoid(InstPtr != NULL);
+	Xil_AssertNonvoid(Config != NULL);
+
+	/*
+	 * Setup the driver instance using passed in parameters
+	 */
+	InstPtr->Config.DeviceId = Config->DeviceId;
+	InstPtr->Config.BaseAddress = EffectiveAddr;
+
+	CfgReg = XDmaPs_ReadReg(EffectiveAddr, XDMAPS_CR1_OFFSET);
+	CacheLength = CfgReg & XDMAPS_CR1_I_CACHE_LEN_MASK;
+	if (CacheLength < 2 || CacheLength > 5)
+		CacheLength = 0;
+	else
+		CacheLength = 1 << CacheLength;
+
+	InstPtr->CacheLength = CacheLength;
+
+	memset(InstPtr->Chans, 0,
+	       sizeof(XDmaPs_ChannelData[XDMAPS_CHANNELS_PER_DEV]));
+
+	for (Channel = 0; Channel < XDMAPS_CHANNELS_PER_DEV; Channel++) {
+		ChanData = InstPtr->Chans + Channel;
+		ChanData->ChanId = Channel;
+		ChanData->DevId = Config->DeviceId;
+	}
+
+	InstPtr->IsReady = 1;
+
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Reset the DMA Manager.
+*
+* @param	InstPtr is the DMA instance.
+*
+* @return	0 on success, -1 on time out
+*
+* @note		None.
+*
+*****************************************************************************/
+int XDmaPs_ResetManager(XDmaPs *InstPtr)
+{
+	int Status;
+	Status = XDmaPs_Exec_DMAKILL(InstPtr->Config.BaseAddress,
+				      0, 0);
+
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Reset the specified DMA Channel.
+*
+* @param	InstPtr is the DMA instance.
+* @param	Channel is the channel to be reset.
+*
+* @return	0 on success, -1 on time out
+*
+* @note		None.
+*
+*****************************************************************************/
+int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel)
+{
+	int Status;
+	Status = XDmaPs_Exec_DMAKILL(InstPtr->Config.BaseAddress,
+				      Channel, 1);
+
+	return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver fault interrupt service routine
+* This is the one that connects the GIC
+*
+* @param	InstPtr is the DMA instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XDmaPs_FaultISR(XDmaPs *InstPtr)
+{
+
+	void *DmaProgBuf;
+	u32 Fsm; /* Fault status DMA manager register value */
+	u32 Fsc; /* Fault status DMA channel register value */
+	u32 FaultType; /* Fault type DMA manager register value */
+
+	u32 BaseAddr = InstPtr->Config.BaseAddress;
+
+	u32 Pc; /* DMA Pc or channel Pc */
+	XDmaPs_ChannelData *ChanData;
+
+	unsigned Chan;
+	unsigned DevId;
+
+	XDmaPs_Cmd *DmaCmd;
+
+	Fsm = XDmaPs_ReadReg(BaseAddr, XDMAPS_FSM_OFFSET) & 0x01;
+	Fsc = XDmaPs_ReadReg(BaseAddr, XDMAPS_FSC_OFFSET) & 0xFF;
+
+
+	DevId = InstPtr->Config.DeviceId;
+
+	if (Fsm) {
+		/*
+		 * if DMA manager is fault
+		 */
+		FaultType = XDmaPs_ReadReg(BaseAddr, XDMAPS_FTM_OFFSET);
+		Pc = XDmaPs_ReadReg(BaseAddr, XDMAPS_DPC_OFFSET);
+
+		xil_printf("PL330 device %d fault with type: %x at Pc %x\n",
+			   DevId,
+			   FaultType, Pc);
+
+		/* kill the DMA manager thread */
+		/* Should we disable interrupt?*/
+		XDmaPs_Exec_DMAKILL(BaseAddr, 0, 0);
+	}
+
+	/*
+	 * check which channel faults and kill the channel thread
+	 */
+	for (Chan = 0;
+	     Chan < XDMAPS_CHANNELS_PER_DEV;
+	     Chan++) {
+		if (Fsc & (0x01 << Chan)) {
+			FaultType =
+				XDmaPs_ReadReg(BaseAddr,
+						XDmaPs_FTCn_OFFSET(Chan));
+			Pc = XDmaPs_ReadReg(BaseAddr,
+					     XDmaPs_CPCn_OFFSET(Chan));
+
+			/* kill the channel thread */
+			/* Should we disable interrupt? */
+			XDmaPs_Exec_DMAKILL(BaseAddr, Chan, 1);
+
+			/*
+			 * get the fault type and fault Pc and invoke the
+			 * fault callback.
+			 */
+			ChanData = InstPtr->Chans + Chan;
+
+			DmaCmd = ChanData->DmaCmdToHw;
+
+			/* Should we check DmaCmd is not null */
+			DmaCmd->DmaStatus = -1;
+			DmaCmd->ChanFaultType = FaultType;
+			DmaCmd->ChanFaultPCAddr = Pc;
+			ChanData->DmaCmdFromHw = DmaCmd;
+			ChanData->DmaCmdToHw = NULL;
+
+			if (!ChanData->HoldDmaProg) {
+				DmaProgBuf = (void *)DmaCmd->GeneratedDmaProg;
+				if (DmaProgBuf)
+					XDmaPs_BufPool_Free(ChanData->ProgBufPool,
+							     DmaProgBuf);
+				DmaCmd->GeneratedDmaProg = NULL;
+			}
+
+			if (InstPtr->FaultHandler)
+				InstPtr->FaultHandler(Chan,
+						      DmaCmd,
+						      InstPtr->FaultRef);
+
+		}
+	}
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Set the done handler for a channel.
+*
+* @param	InstPtr is the DMA instance.
+* @param	Channel is the channel number.
+* @param	DoneHandler is the done interrupt handler.
+* @param	CallbackRef is the callback reference data.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
+			   unsigned Channel,
+			   XDmaPsDoneHandler DoneHandler,
+			   void *CallbackRef)
+{
+	XDmaPs_ChannelData *ChanData;
+
+	Xil_AssertNonvoid(InstPtr != NULL);
+
+	if (Channel >= XDMAPS_CHANNELS_PER_DEV)
+		return XST_FAILURE;
+
+
+	ChanData = InstPtr->Chans + Channel;
+
+	ChanData->DoneHandler = DoneHandler;
+	ChanData->DoneRef = CallbackRef;
+
+	return 0;
+}
+
+/*****************************************************************************/
+/**
+*
+* Set the fault handler for a channel.
+*
+* @param	InstPtr is the DMA instance.
+* @param	FaultHandler is the fault interrupt handler.
+* @param	CallbackRef is the callback reference data.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
+			    XDmaPsFaultHandler FaultHandler,
+			    void *CallbackRef)
+{
+	Xil_AssertNonvoid(InstPtr != NULL);
+
+	InstPtr->FaultHandler = FaultHandler;
+	InstPtr->FaultRef = CallbackRef;
+
+	return XST_SUCCESS;
+}
+
+
+
+/****************************************************************************/
+/**
+* Construction function for DMAEND instruction. This function fills the program
+* buffer with the constructed instruction.
+*
+* @param	DmaProg the DMA program buffer, it's the starting address for
+*		the instruction being constructed
+*
+* @return 	The number of bytes for this instruction which is 1.
+*
+* @note		None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMAEND(char *DmaProg)
+{
+	/*
+	 * DMAEND encoding:
+	 * 7 6 5 4 3 2 1 0
+	 * 0 0 0 0 0 0 0 0
+	 */
+	*DmaProg = 0x0;
+
+	return 1;
+}
+
+static INLINE void XDmaPs_Memcpy4(char *Dst, char *Src)
+{
+	*Dst = *Src;
+	*(Dst + 1) = *(Src + 1);
+	*(Dst + 2) = *(Src + 2);
+	*(Dst + 3) = *(Src + 3);
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMAGO instruction. This function fills the program
+* buffer with the constructed instruction.
+*
+* @param	DmaProg is the DMA program buffer, it's the starting address
+*		for the instruction being constructed
+* @param	Cn is the Channel number, 0 - 7
+* @param	Imm is 32-bit immediate number written to the Channel Program
+*		Counter.
+* @param	Ns is Non-secure flag. If Ns is 1, the DMA channel operates in
+*		the Non-secure state. If Ns is 0, the execution depends on the
+*		security state of the DMA manager:
+*		DMA manager is in the Secure state, DMA channel operates in the
+*		Secure state.
+*		DMA manager is in the Non-secure state, DMAC aborts.
+*
+* @return	The number of bytes for this instruction which is 6.
+*
+* @note		None
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
+			       u32 Imm, unsigned int Ns)
+{
+	/*
+	 * DMAGO encoding:
+	 * 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
+	 *  0  0  0  0  0 |cn[2:0]| 1  0  1  0  0  0 ns  0
+	 *
+	 * 47 ... 16
+	 *  imm[32:0]
+	 */
+	*DmaProg = 0xA0 | ((Ns << 1) & 0x02);
+
+	*(DmaProg + 1) = (u8)(Cn & 0x07);
+
+	// *((u32 *)(DmaProg + 2)) = Imm;
+	XDmaPs_Memcpy4(DmaProg + 2, (char *)&Imm);
+
+	/* success */
+	return 6;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMALD instruction. This function fills the program
+* buffer with the constructed instruction.
+*
+* @param	DmaProg the DMA program buffer, it's the starting address for the
+*		instruction being constructed
+*
+* @return 	The number of bytes for this instruction which is 1.
+*
+* @note		None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMALD(char *DmaProg)
+{
+	/*
+	 * DMALD encoding
+	 * 7 6 5 4 3 2 1  0
+	 * 0 0 0 0 0 1 bs x
+	 *
+	 * Note: this driver doesn't support conditional load or store,
+	 * so the bs bit is 0 and x bit is 0.
+	 */
+	*DmaProg = 0x04;
+	return 1;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMALP instruction. This function fills the program
+* buffer with the constructed instruction.
+*
+* @param	DmaProg is the DMA program buffer, it's the starting address
+*		for the instruction being constructed
+* @param	Lc is the Loop counter register, can either be 0 or 1.
+* @param	LoopIterations: the number of interations, LoopInterations - 1
+*		will be encoded in the DMALP instruction.
+*
+* @return 	The number of bytes for this instruction which is 2.
+*
+* @note		None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
+			       unsigned LoopIterations)
+{
+	/*
+	 * DMALP encoding
+	 * 15   ...   8 7 6 5 4 3 2 1  0
+	 * | iter[7:0] |0 0 1 0 0 0 lc 0
+	 */
+	*DmaProg = (u8)(0x20 | ((Lc & 1) << 1));
+	*(DmaProg + 1) = (u8)(LoopIterations - 1);
+	return 2;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMALPEND instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param	DmaProg is the DMA program buffer, it's the starting address
+*		for the instruction being constructed
+* @param	BodyStart is the starting address of the loop body. It is used
+* 		to calculate the bytes of backward jump.
+* @param	Lc is the Loop counter register, can either be 0 or 1.
+*
+* @return 	The number of bytes for this instruction which is 2.
+*
+* @note	None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc)
+{
+	/*
+	 * DMALPEND encoding
+	 * 15       ...        8 7 6 5 4  3 2  1  0
+	 * | backward_jump[7:0] |0 0 1 nf 1 lc bs x
+	 *
+	 * lc: loop counter
+	 * nf is for loop forever. The driver does not support loop forever,
+	 * so nf is 1.
+	 * The driver does not support conditional LPEND, so bs is 0, x is 0.
+	 */
+	*DmaProg = 0x38 | ((Lc & 1) << 2);
+	*(DmaProg + 1) = (u8)(DmaProg - BodyStart);
+
+	return 2;
+}
+
+/*
+ * Register number for the DMAMOV instruction
+ */
+#define XDMAPS_MOV_SAR 0x0
+#define XDMAPS_MOV_CCR 0x1
+#define XDMAPS_MOV_DAR 0x2
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMAMOV instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param	DmaProg is the DMA program buffer, it's the starting address
+*		for the instruction being constructed
+* @param	Rd is the register id, 0 for SAR, 1 for CCR, and 2 for DAR
+* @param	Imm is the 32-bit immediate number
+*
+* @return 	The number of bytes for this instruction which is 6.
+*
+* @note		None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm)
+{
+	/*
+	 * DMAMOV encoding
+	 * 15 4 3 2 1 10 ... 8 7 6 5 4 3 2 1 0
+	 *  0 0 0 0 0 |rd[2:0]|1 0 1 1 1 1 0 0
+	 *
+	 * 47 ... 16
+	 *  imm[32:0]
+	 *
+	 * rd: b000 for SAR, b001 CCR, b010 DAR
+	 */
+	*DmaProg = 0xBC;
+	*(DmaProg + 1) = Rd & 0x7;
+	// *((u32 *)(DmaProg + 2)) = Imm;
+	XDmaPs_Memcpy4(DmaProg + 2, (char *)&Imm);
+
+	return 6;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMANOP instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param	DmaProg is the DMA program buffer, it's the starting address
+*		for the instruction being constructed
+* @return 	The number of bytes for this instruction which is 1.
+*
+* @note		None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMANOP(char *DmaProg)
+{
+	/*
+	 * DMANOP encoding
+	 * 7 6 5 4 3 2 1 0
+	 * 0 0 0 1 1 0 0 0
+	 */
+	*DmaProg = 0x18;
+	return 1;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMARMB instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param	DmaProg is the DMA program buffer, it's the starting address
+*		for the instruction being constructed
+*
+* @return 	The number of bytes for this instruction which is 1.
+*
+* @note		None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMARMB(char *DmaProg)
+{
+	/*
+	 * DMARMB encoding
+	 * 7 6 5 4 3 2 1 0
+	 * 0 0 0 1 0 0 1 0
+	 */
+	*DmaProg = 0x12;
+	return 1;
+}
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMASEV instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param	DmaProg is the DMA program buffer, it's the starting address
+*		for the instruction being constructed
+* @param	EventNumber is the Event number to signal.
+*
+* @return 	The number of bytes for this instruction which is 2.
+*
+* @note		None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber)
+{
+	/*
+	 * DMASEV encoding
+	 * 15 4 3 2 1  10 9 8 7 6 5 4 3 2 1 0
+	 * |event[4:0]| 0 0 0 0 0 1 1 0 1 0 0
+	 */
+	*DmaProg = 0x34;
+	*(DmaProg + 1) = (u8)(EventNumber << 3);
+
+	return 2;
+}
+
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMAST instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param	DmaProg is the DMA program buffer, it's the starting address
+*		for the instruction being constructed
+*
+* @return 	The number of bytes for this instruction which is 1.
+*
+* @note		None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMAST(char *DmaProg)
+{
+	/*
+	 * DMAST encoding
+	 * 7 6 5 4 3 2 1  0
+	 * 0 0 0 0 1 0 bs x
+	 *
+	 * Note: this driver doesn't support conditional load or store,
+	 * so the bs bit is 0 and x bit is 0.
+	 */
+	*DmaProg = 0x08;
+	return 1;
+}
+
+
+/****************************************************************************/
+/**
+*
+* Construction function for DMAWMB instruction. This function fills the
+* program buffer with the constructed instruction.
+*
+* @param	DmaProg is the DMA program buffer, it's the starting address
+*		for the instruction being constructed
+*
+* @return 	The number of bytes for this instruction which is 1.
+*
+* @note		None.
+*
+*****************************************************************************/
+static INLINE int XDmaPs_Instr_DMAWMB(char *DmaProg)
+{
+	/*
+	 * DMAWMB encoding
+	 * 7 6 5 4 3 2 1 0
+	 * 0 0 0 1 0 0 1 0
+	 */
+	*DmaProg = 0x13;
+	return 1;
+}
+
+/****************************************************************************/
+/**
+*
+* Conversion function from the endian swap size to the bit encoding of the CCR
+*
+* @param	EndianSwapSize is the endian swap size, in terms of bits, it
+*		could be 8, 16, 32, 64, or 128(We are using DMA assembly syntax)
+*
+* @return	The endian swap size bit encoding for the CCR.
+*
+* @note	None.
+*
+*****************************************************************************/
+static INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize)
+{
+	switch (EndianSwapSize) {
+	case 0:
+	case 8:
+		return 0;
+	case 16:
+		return 1;
+	case 32:
+		return 2;
+	case 64:
+		return 3;
+	case 128:
+		return 4;
+	default:
+		return 0;
+	}
+
+}
+
+/****************************************************************************/
+/**
+*
+* Conversion function from the burst size to the bit encoding of the CCR
+*
+* @param	BurstSize is the burst size. It's the data width.
+*		In terms of bytes, it could be 1, 2, 4, 8, 16, 32, 64, or 128.
+*		It must be no larger than the bus width.
+*		(We are using DMA assembly syntax.)
+*
+* @note		None.
+*
+*****************************************************************************/
+static INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize)
+{
+	switch (BurstSize) {
+	case 1:
+		return 0;
+	case 2:
+		return 1;
+	case 4:
+		return 2;
+	case 8:
+		return 3;
+	case 16:
+		return 4;
+	case 32:
+		return 5;
+	case 64:
+		return 6;
+	case 128:
+		return 7;
+	default:
+		return 0;
+	}
+}
+
+
+/****************************************************************************/
+/**
+*
+* Conversion function from PL330 bus transfer descriptors to CCR value. All the
+* values passed to the functions are in terms of assembly languages, not in
+* terms of the register bit encoding.
+*
+* @param	ChanCtrl is the Instance of XDmaPs_ChanCtrl.
+*
+* @return	The 32-bit CCR value.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XDmaPs_ToCCRValue(XDmaPs_ChanCtrl *ChanCtrl)
+{
+	/*
+	 * Channel Control Register encoding
+	 * [31:28] - endian_swap_size
+	 * [27:25] - dst_cache_ctrl
+	 * [24:22] - dst_prot_ctrl
+	 * [21:18] - dst_burst_len
+	 * [17:15] - dst_burst_size
+	 * [14]    - dst_inc
+	 * [13:11] - src_cache_ctrl
+	 * [10:8] - src_prot_ctrl
+	 * [7:4]  - src_burst_len
+	 * [3:1]  - src_burst_size
+	 * [0]     - src_inc
+	 */
+
+	unsigned es =
+		XDmaPs_ToEndianSwapSizeBits(ChanCtrl->EndianSwapSize);
+
+	unsigned dst_burst_size =
+		XDmaPs_ToBurstSizeBits(ChanCtrl->DstBurstSize);
+	unsigned dst_burst_len = (ChanCtrl->DstBurstLen - 1) & 0x0F;
+	unsigned dst_cache_ctrl = (ChanCtrl->DstCacheCtrl & 0x03)
+		| ((ChanCtrl->DstCacheCtrl & 0x08) >> 1);
+	unsigned dst_prot_ctrl = ChanCtrl->DstProtCtrl & 0x07;
+	unsigned dst_inc_bit = ChanCtrl->DstInc & 1;
+
+	unsigned src_burst_size =
+		XDmaPs_ToBurstSizeBits(ChanCtrl->SrcBurstSize);
+	unsigned src_burst_len = (ChanCtrl->SrcBurstLen - 1) & 0x0F;
+	unsigned src_cache_ctrl = (ChanCtrl->SrcCacheCtrl & 0x03)
+		| ((ChanCtrl->SrcCacheCtrl & 0x08) >> 1);
+	unsigned src_prot_ctrl = ChanCtrl->SrcProtCtrl & 0x07;
+	unsigned src_inc_bit = ChanCtrl->SrcInc & 1;
+
+	u32 ccr_value = (es << 28)
+		| (dst_cache_ctrl << 25)
+		| (dst_prot_ctrl << 22)
+		| (dst_burst_len << 18)
+		| (dst_burst_size << 15)
+		| (dst_inc_bit << 14)
+		| (src_cache_ctrl << 11)
+		| (src_prot_ctrl << 8)
+		| (src_burst_len << 4)
+		| (src_burst_size << 1)
+		| (src_inc_bit);
+
+	return ccr_value;
+}
+
+/****************************************************************************/
+/**
+* Construct a loop with only DMALD and DMAST as the body using loop counter 0.
+* The function also makes sure the loop body and the lpend is in the same
+* cache line.
+*
+* @param	DmaProgStart is the very start address of the DMA program.
+*		This is used to calculate whether the loop is in a cache line.
+* @param	CacheLength is the icache line length, in terms of bytes.
+*		If it's zero, the performance enhancement feature will be
+*		turned off.
+* @param	DmaProgLoopStart The starting address of the loop (DMALP).
+* @param	LoopCount The inner loop count. Loop count - 1 will be used to
+* 		initialize the loop counter.
+*
+* @return	The number of bytes the loop has.
+*
+* @note		None.
+*
+*****************************************************************************/
+int XDmaPs_ConstructSingleLoop(char *DmaProgStart,
+				int CacheLength,
+				char *DmaProgLoopStart,
+				int LoopCount)
+{
+	int CacheStartOffset;
+	int CacheEndOffset;
+	int NumNops;
+	char *DmaProgBuf = DmaProgLoopStart;
+
+	DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 0, LoopCount);
+
+	if (CacheLength > 0) {
+		/*
+		 * the CacheLength > 0 switch is ued to turn on/off nop
+		 * insertion
+		 */
+		CacheStartOffset = DmaProgBuf - DmaProgStart;
+		CacheEndOffset = CacheStartOffset + 3;
+
+		/*
+		 * check whether the body and lpend fit in one cache line
+		 */
+		if (CacheStartOffset / CacheLength
+		    != CacheEndOffset / CacheLength) {
+			/* insert the nops */
+			NumNops = CacheLength
+				- CacheStartOffset % CacheLength;
+			while (NumNops--) {
+				DmaProgBuf +=
+					XDmaPs_Instr_DMANOP(DmaProgBuf);
+			}
+		}
+	}
+
+	DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf);
+	DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf);
+	DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf,
+					     DmaProgBuf - 2, 0);
+
+	return DmaProgBuf - DmaProgLoopStart;
+}
+
+/****************************************************************************/
+/**
+* Construct a nested loop with only DMALD and DMAST in the inner loop body.
+* It uses loop counter 1 for the outer loop and loop counter 0 for the
+* inner loop.
+*
+* @param	DmaProgStart is the very start address of the DMA program.
+*		This is used to calculate whether the loop is in a cache line.
+* @param	CacheLength is the icache line length, in terms of bytes.
+*		If it's zero, the performance enhancement feature will be
+*		turned off.
+* @param	DmaProgLoopStart The starting address of the loop (DMALP).
+* @param	LoopCountOuter The outer loop count. Loop count - 1 will be
+*		used to initialize the loop counter.
+* @param	LoopCountInner The inner loop count. Loop count - 1 will be
+*		used to initialize the loop counter.
+*
+* @return	The number byes the nested loop program has.
+*
+* @note		None.
+*
+*****************************************************************************/
+int XDmaPs_ConstructNestedLoop(char *DmaProgStart,
+				int CacheLength,
+				char *DmaProgLoopStart,
+				unsigned int LoopCountOuter,
+				unsigned int LoopCountInner)
+{
+	int CacheStartOffset;
+	int CacheEndOffset;
+	int NumNops;
+	char *InnerLoopStart;
+	char *DmaProgBuf = DmaProgLoopStart;
+
+	DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 1, LoopCountOuter);
+	InnerLoopStart = DmaProgBuf;
+
+	if (CacheLength > 0) {
+		/*
+		 * the CacheLength > 0 switch is ued to turn on/off nop
+		 * insertion
+		 */
+		if (CacheLength < 8) {
+			/*
+			 * if the cache line is too small to fit both loops
+			 * just align the inner loop
+			 */
+			DmaProgBuf +=
+				XDmaPs_ConstructSingleLoop(DmaProgStart,
+							    CacheLength,
+							    DmaProgBuf,
+							    LoopCountInner);
+			/* outer loop end */
+			DmaProgBuf +=
+				XDmaPs_Instr_DMALPEND(DmaProgBuf,
+						       InnerLoopStart,
+						       1);
+
+			/*
+			 * the nested loop is constructed for
+			 * smaller cache line
+			 */
+			return DmaProgBuf - DmaProgLoopStart;
+		}
+
+		/*
+		 * Now let's handle the case where a cache line can
+		 * fit the nested loops.
+		 */
+		CacheStartOffset = DmaProgBuf - DmaProgStart;
+		CacheEndOffset = CacheStartOffset + 7;
+
+		/*
+		 * check whether the body and lpend fit in one cache line
+		 */
+		if (CacheStartOffset / CacheLength
+		    != CacheEndOffset / CacheLength) {
+			/* insert the nops */
+			NumNops = CacheLength
+				- CacheStartOffset % CacheLength;
+			while (NumNops--) {
+				DmaProgBuf +=
+					XDmaPs_Instr_DMANOP(DmaProgBuf);
+			}
+		}
+	}
+
+	/* insert the inner DMALP */
+	DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 0, LoopCountInner);
+
+	/* DMALD and DMAST instructions */
+	DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf);
+	DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf);
+
+	/* inner DMALPEND */
+	DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf,
+					     DmaProgBuf - 2, 0);
+	/* outer DMALPEND */
+	DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf,
+					     InnerLoopStart, 1);
+
+	/* return the number of bytes */
+	return DmaProgBuf - DmaProgLoopStart;
+}
+
+/*
+ * [31:28] endian_swap_size	b0000
+ * [27:25] dst_cache_ctrl	b000
+ * [24:22] dst_prot_ctrl	b000
+ * [21:18] dst_burst_len	b0000
+ * [17:15] dst_burst_size	b000
+ * [14]    dst_inc		b0
+ * [27:25] src_cache_ctrl	b000
+ * [24:22] src_prot_ctrl	b000
+ * [21:18] src_burst_len	b0000
+ * [17:15] src_burst_size	b000
+ * [14]    src_inc		b0
+ */
+#define XDMAPS_CCR_SINGLE_BYTE	(0x0)
+#define XDMAPS_CCR_M2M_SINGLE_BYTE	((0x1 << 14) | 0x1)
+
+
+/****************************************************************************/
+/**
+*
+* Construct the DMA program based on the descriptions of the DMA transfer.
+* The function handles memory to memory DMA transfers.
+* It also handles unalgined head and small amount of residue tail.
+*
+* @param	Channel DMA channel number
+* @param	Cmd is the DMA command.
+* @param	CacheLength is the icache line length, in terms of bytes.
+*		If it's zero, the performance enhancement feature will be
+*		turned off.
+*
+* @returns	The number of bytes for the program.
+*
+* @note		None.
+*
+*****************************************************************************/
+static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
+				unsigned CacheLength)
+{
+	/*
+	 * unpack arguments
+	 */
+	char *DmaProgBuf = (char *)Cmd->GeneratedDmaProg;
+	unsigned DevChan = Channel;
+	unsigned long DmaLength = Cmd->BD.Length;
+	u32 SrcAddr = Cmd->BD.SrcAddr;
+
+	unsigned SrcInc = Cmd->ChanCtrl.SrcInc;
+	u32 DstAddr = Cmd->BD.DstAddr;
+	unsigned DstInc = Cmd->ChanCtrl.DstInc;
+
+	char *DmaProgStart = DmaProgBuf;
+
+	unsigned int BurstBytes;
+	unsigned int LoopCount;
+	unsigned int LoopCount1 = 0;
+	unsigned int LoopResidue = 0;
+	unsigned int TailBytes;
+	unsigned int TailWords;
+	int DmaProgBytes;
+	u32 CCRValue;
+	unsigned int Unaligned;
+	unsigned int UnalignedCount;
+	unsigned int MemBurstSize = 1;
+	u32 MemAddr = 0;
+	unsigned int Index;
+	unsigned int SrcUnaligned = 0;
+	unsigned int DstUnaligned = 0;
+
+	XDmaPs_ChanCtrl *ChanCtrl;
+	XDmaPs_ChanCtrl WordChanCtrl;
+	static XDmaPs_ChanCtrl Mem2MemByteCC;
+
+	Mem2MemByteCC.EndianSwapSize = 0;
+	Mem2MemByteCC.DstCacheCtrl = 0;
+	Mem2MemByteCC.DstProtCtrl = 0;
+	Mem2MemByteCC.DstBurstLen = 1;
+	Mem2MemByteCC.DstBurstSize = 1;
+	Mem2MemByteCC.DstInc = 1;
+	Mem2MemByteCC.SrcCacheCtrl = 0;
+	Mem2MemByteCC.SrcProtCtrl = 0;
+	Mem2MemByteCC.SrcBurstLen = 1;
+	Mem2MemByteCC.SrcBurstSize = 1;
+	Mem2MemByteCC.SrcInc = 1;
+
+	ChanCtrl = &Cmd->ChanCtrl;
+
+	/* insert DMAMOV for SAR and DAR */
+	DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
+					   XDMAPS_MOV_SAR,
+					   SrcAddr);
+	DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
+					 XDMAPS_MOV_DAR,
+					 DstAddr);
+
+
+	if (ChanCtrl->SrcInc)
+		SrcUnaligned = SrcAddr % ChanCtrl->SrcBurstSize;
+
+	if (ChanCtrl->DstInc)
+		DstUnaligned = DstAddr % ChanCtrl->DstBurstSize;
+
+	if ((SrcUnaligned && DstInc) || (DstUnaligned && SrcInc)) {
+		ChanCtrl = &Mem2MemByteCC;
+	}
+
+	if (ChanCtrl->SrcInc) {
+		MemBurstSize = ChanCtrl->SrcBurstSize;
+		MemAddr = SrcAddr;
+
+	} else if (ChanCtrl->DstInc) {
+		MemBurstSize = ChanCtrl->DstBurstSize;
+		MemAddr = DstAddr;
+	}
+
+	/* check whether the head is aligned or not */
+	Unaligned = MemAddr % MemBurstSize;
+
+	if (Unaligned) {
+		/* if head is unaligned, transfer head in bytes */
+		UnalignedCount = MemBurstSize - Unaligned;
+		CCRValue = XDMAPS_CCR_SINGLE_BYTE
+			| (SrcInc & 1)
+			| ((DstInc & 1) << 14);
+
+		DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
+						   XDMAPS_MOV_CCR,
+						   CCRValue);
+
+		for (Index = 0; Index < UnalignedCount; Index++) {
+			DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf);
+			DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf);
+		}
+
+		DmaLength -= UnalignedCount;
+	}
+
+	/* now the burst transfer part */
+	CCRValue = XDmaPs_ToCCRValue(ChanCtrl);
+	DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
+					   XDMAPS_MOV_CCR,
+					   CCRValue);
+
+	BurstBytes = ChanCtrl->SrcBurstSize * ChanCtrl->SrcBurstLen;
+
+	LoopCount = DmaLength / BurstBytes;
+	TailBytes = DmaLength % BurstBytes;
+
+	/*
+	 * the loop count register is 8-bit wide, so if we need
+	 * a larger loop, we need to have nested loops
+	 */
+	if (LoopCount > 256) {
+		LoopCount1 = LoopCount / 256;
+		if (LoopCount1 > 256) {
+			xil_printf("DMA operation cannot fit in a 2-level "
+				   "loop for channel %d, please reduce the "
+				   "DMA length or increase the burst size or "
+				   "length",
+				   Channel);
+			return 0;
+		}
+		LoopResidue = LoopCount % 256;
+
+		if (LoopCount1 > 1)
+			DmaProgBuf +=
+				XDmaPs_ConstructNestedLoop(DmaProgStart,
+							    CacheLength,
+							    DmaProgBuf,
+							    LoopCount1,
+							    256);
+		else
+			DmaProgBuf +=
+				XDmaPs_ConstructSingleLoop(DmaProgStart,
+							    CacheLength,
+							    DmaProgBuf,
+							    256);
+
+		/* there will be some that cannot be covered by
+		 * nested loops
+		 */
+		LoopCount = LoopResidue;
+	}
+
+	if (LoopCount > 0) {
+		DmaProgBuf += XDmaPs_ConstructSingleLoop(DmaProgStart,
+							    CacheLength,
+							    DmaProgBuf,
+							    LoopCount);
+	}
+
+	if (TailBytes) {
+		/* handle the tail */
+		TailWords = TailBytes / MemBurstSize;
+		TailBytes = TailBytes % MemBurstSize;
+
+		if (TailWords) {
+			WordChanCtrl = *ChanCtrl;
+			/*
+			 * if we can transfer the tail in words, we will
+			 * transfer words as much as possible
+			 */
+			WordChanCtrl.SrcBurstSize = MemBurstSize;
+			WordChanCtrl.SrcBurstLen = 1;
+			WordChanCtrl.DstBurstSize = MemBurstSize;
+			WordChanCtrl.DstBurstLen = 1;
+
+
+			/*
+			 * the burst length is 1
+			 */
+			CCRValue = XDmaPs_ToCCRValue(&WordChanCtrl);
+
+			DmaProgBuf +=
+				XDmaPs_Instr_DMAMOV(DmaProgBuf,
+						   XDMAPS_MOV_CCR,
+						   CCRValue);
+			DmaProgBuf +=
+				XDmaPs_ConstructSingleLoop(DmaProgStart,
+							    CacheLength,
+							    DmaProgBuf,
+							    TailWords);
+
+		}
+
+		if (TailBytes) {
+			/*
+			 * for the rest, we'll tranfer in bytes
+			 */
+			/*
+			 * So far just to be safe, the tail bytes
+			 * are transfered in a loop. We can optimize a little
+			 * to perform a burst.
+			 */
+			CCRValue = XDMAPS_CCR_SINGLE_BYTE
+				| (SrcInc & 1)
+				| ((DstInc & 1) << 14);
+
+			DmaProgBuf +=
+				XDmaPs_Instr_DMAMOV(DmaProgBuf,
+						   XDMAPS_MOV_CCR,
+						   CCRValue);
+
+			DmaProgBuf +=
+				XDmaPs_ConstructSingleLoop(DmaProgStart,
+							    CacheLength,
+							    DmaProgBuf,
+							    TailBytes);
+
+		}
+	}
+
+	DmaProgBuf += XDmaPs_Instr_DMASEV(DmaProgBuf, DevChan);
+	DmaProgBuf += XDmaPs_Instr_DMAEND(DmaProgBuf);
+
+	DmaProgBytes = DmaProgBuf - DmaProgStart;
+
+	Xil_DCacheFlushRange((u32)DmaProgStart, DmaProgBytes);
+
+	return DmaProgBytes;
+
+}
+
+
+/****************************************************************************/
+/**
+*
+* Generate a DMA program based for the DMA command, the buffer will be pointed
+* by the GeneratedDmaProg field of the command.
+*
+* @param	InstPtr is then DMA instance.
+* @param	Channel is the DMA channel number.
+* @param	Cmd is the DMA command.
+*
+* @return	- XST_SUCCESS on success.
+* 		- XST_FAILURE if it fails
+*
+* @note		None.
+*
+*****************************************************************************/
+int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd)
+{
+	void *Buf;
+	int ProgLen;
+	XDmaPs_ChannelData *ChanData;
+	XDmaPs_ChanCtrl *ChanCtrl;
+
+	Xil_AssertNonvoid(InstPtr != NULL);
+	Xil_AssertNonvoid(Cmd != NULL);
+
+
+	if (Channel > XDMAPS_CHANNELS_PER_DEV)
+		return XST_FAILURE;
+
+	ChanData = InstPtr->Chans + Channel;
+	ChanCtrl = &Cmd->ChanCtrl;
+
+	if (ChanCtrl->SrcBurstSize * ChanCtrl->SrcBurstLen
+	    != ChanCtrl->DstBurstSize * ChanCtrl->DstBurstLen) {
+		return XST_FAILURE;
+	}
+
+
+	/*
+	 * unaligned fixed address is not supported
+	 */
+	if (!ChanCtrl->SrcInc && Cmd->BD.SrcAddr % ChanCtrl->SrcBurstSize) {
+		return XST_FAILURE;
+	}
+
+	if (!ChanCtrl->DstInc && Cmd->BD.DstAddr % ChanCtrl->DstBurstSize) {
+		return XST_FAILURE;
+	}
+
+	Buf = XDmaPs_BufPool_Allocate(ChanData->ProgBufPool);
+	if (Buf == NULL) {
+		return XST_FAILURE;
+	}
+
+	Cmd->GeneratedDmaProg = Buf;
+	ProgLen = XDmaPs_BuildDmaProg(Channel, Cmd,
+				       InstPtr->CacheLength);
+	Cmd->GeneratedDmaProgLength = ProgLen;
+
+
+#ifdef XDMAPS_DEBUG
+	XDmaPs_Print_DmaProg(Cmd);
+#endif
+
+	if (ProgLen <= 0) {
+		/* something wrong, release the buffer */
+		XDmaPs_BufPool_Free(ChanData->ProgBufPool, Buf);
+		Cmd->GeneratedDmaProgLength = 0;
+		Cmd->GeneratedDmaProg = NULL;
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+
+/****************************************************************************/
+/**
+ * Free the DMA program buffer that is pointed by the GeneratedDmaProg field
+ * of the command.
+ *
+ * @param	InstPtr is then DMA instance.
+ * @param	Channel is the DMA channel number.
+ * @param	Cmd is the DMA command.
+ *
+ * @return	XST_SUCCESS on success.
+ * 		XST_FAILURE if there is any error.
+ *
+ * @note	None.
+ *
+ ****************************************************************************/
+int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd)
+{
+
+	void *Buf;
+	XDmaPs_ChannelData *ChanData;
+
+	Xil_AssertNonvoid(InstPtr != NULL);
+	Xil_AssertNonvoid(Cmd != NULL);
+
+	if (Channel > XDMAPS_CHANNELS_PER_DEV)
+		return XST_FAILURE;
+
+	Buf = (void *)Cmd->GeneratedDmaProg;
+	ChanData = InstPtr->Chans + Channel;
+
+	if (Buf) {
+		XDmaPs_BufPool_Free(ChanData->ProgBufPool, Buf);
+		Cmd->GeneratedDmaProg = 0;
+		Cmd->GeneratedDmaProgLength = 0;
+	}
+
+	return XST_SUCCESS;
+}
+
+
+/****************************************************************************/
+/**
+*
+* Start a DMA command. The command can only be invoked when the channel
+* is idle. The driver takes the command, generates DMA program if needed,
+* then pass the program to DMAC to execute.
+*
+* @param	InstPtr is then DMA instance.
+* @param	Channel is the DMA channel number.
+* @param	Cmd is the DMA command.
+* @param	HoldDmaProg is tag indicating whether the driver can release
+* 		the allocated DMA buffer or not. If a user wants to examine the
+* 		generated DMA program, the flag should be set to 1. After the
+* 		DMA program is finished, a user needs to explicity free the
+*		buffer.
+*
+* @return
+*		- XST_SUCCESS on success
+*		- XST_DEVICE_BUSY if DMA is busy
+*		- XST_FAILURE on other failures
+*
+* @note		None.
+*
+****************************************************************************/
+int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
+		  XDmaPs_Cmd *Cmd,
+		  int HoldDmaProg)
+{
+	int Status;
+	u32 DmaProg = 0;
+	u32 Inten;
+
+	Xil_AssertNonvoid(InstPtr != NULL);
+	Xil_AssertNonvoid(Cmd != NULL);
+
+
+	Cmd->DmaStatus = XST_FAILURE;
+
+	if (XDmaPs_IsActive(InstPtr, Channel))
+		return XST_DEVICE_BUSY;
+
+	if (!Cmd->UserDmaProg && !Cmd->GeneratedDmaProg) {
+		Status = XDmaPs_GenDmaProg(InstPtr, Channel, Cmd);
+		if (Status)
+			return XST_FAILURE;
+	}
+
+	InstPtr->Chans[Channel].HoldDmaProg = HoldDmaProg;
+
+	if (Cmd->UserDmaProg)
+		DmaProg = (u32)Cmd->UserDmaProg;
+	else if (Cmd->GeneratedDmaProg)
+		DmaProg = (u32)Cmd->GeneratedDmaProg;
+
+	if (DmaProg) {
+		/* enable the interrupt */
+		Inten = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
+					XDMAPS_INTEN_OFFSET);
+		Inten |= 0x01 << Channel; /* set the correpsonding bit */
+		XDmaPs_WriteReg(InstPtr->Config.BaseAddress,
+				 XDMAPS_INTEN_OFFSET,
+				 Inten);
+		Inten = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
+				XDMAPS_INTEN_OFFSET);
+
+		InstPtr->Chans[Channel].DmaCmdToHw = Cmd;
+
+		if (Cmd->ChanCtrl.SrcInc) {
+			Xil_DCacheFlushRange(Cmd->BD.SrcAddr, Cmd->BD.Length);
+		}
+		if (Cmd->ChanCtrl.DstInc) {
+			Xil_DCacheInvalidateRange(Cmd->BD.DstAddr,
+					Cmd->BD.Length);
+		}
+
+		Status = XDmaPs_Exec_DMAGO(InstPtr->Config.BaseAddress,
+					    Channel, DmaProg);
+	}
+	else {
+		InstPtr->Chans[Channel].DmaCmdToHw = NULL;
+		Status = XST_FAILURE;
+	}
+
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Checks  whether the DMA channel is active or idle.
+*
+* @param	InstPtr is the DMA instance.
+* @param	Channel is the DMA channel number.
+*
+* @return	0: if the channel is idle
+* 		1: otherwise
+*
+* @note		None.
+*
+*****************************************************************************/
+int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel)
+{
+	Xil_AssertNonvoid(InstPtr != NULL);
+
+	/* Need to assert Channel is in range */
+	if (Channel > XDMAPS_CHANNELS_PER_DEV)
+		return  0;
+
+	return InstPtr->Chans[Channel].DmaCmdToHw != NULL;
+}
+
+
+
+/****************************************************************************/
+/**
+*
+* Allocate a buffer of the DMA program buffer from the pool.
+*
+* @param	Pool the DMA program pool.
+*
+* @return	The allocated buffer, NULL if there is any error.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void *XDmaPs_BufPool_Allocate(XDmaPs_ProgBuf *Pool)
+{
+	int Index;
+
+	Xil_AssertNonvoid(Pool != NULL);
+
+	for (Index = 0; Index < XDMAPS_MAX_CHAN_BUFS; Index++) {
+		if (!Pool[Index].Allocated) {
+			Pool[Index].Allocated = 1;
+			return Pool[Index].Buf;
+		}
+	}
+
+	return NULL;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 0. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param	InstPtr is the DMA instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_0(XDmaPs *InstPtr)
+{
+	XDmaPs_DoneISR_n(InstPtr, 0);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 1. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param	InstPtr is the DMA instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_1(XDmaPs *InstPtr)
+{
+	XDmaPs_DoneISR_n(InstPtr, 1);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 2. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param	InstPtr is the DMA instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_2(XDmaPs *InstPtr)
+{
+	XDmaPs_DoneISR_n(InstPtr, 2);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 3. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param	InstPtr is the DMA instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_3(XDmaPs *InstPtr)
+{
+	XDmaPs_DoneISR_n(InstPtr, 3);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 4. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param	InstPtr is the DMA instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_4(XDmaPs *InstPtr)
+{
+	XDmaPs_DoneISR_n(InstPtr, 4);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 5. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param	InstPtr is the DMA instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_5(XDmaPs *InstPtr)
+{
+	XDmaPs_DoneISR_n(InstPtr, 5);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 6. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param	InstPtr is the DMA instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_6(XDmaPs *InstPtr)
+{
+	XDmaPs_DoneISR_n(InstPtr, 6);
+}
+
+/*****************************************************************************/
+/**
+*
+* Driver done interrupt service routine for channel 7. We need this done ISR
+* mainly because the driver needs to release the DMA program buffer.
+* This is the one that connects the GIC
+*
+* @param	InstPtr is the DMA instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XDmaPs_DoneISR_7(XDmaPs *InstPtr)
+{
+	XDmaPs_DoneISR_n(InstPtr, 7);
+}
+
+#ifndef XDMAPS_MAX_WAIT
+#define XDMAPS_MAX_WAIT 4000
+#endif
+
+/****************************************************************************/
+/**
+* Use the debug registers to kill the DMA thread.
+*
+* @param	BaseAddr is DMA device base address.
+* @param	Channel is the DMA channel number.
+* @param	Thread is Debug thread encoding.
+* 		0: DMA manager thread, 1: DMA channel.
+*
+* @return	0 on success, -1 on time out
+*
+* @note		None.
+*
+*****************************************************************************/
+static int XDmaPs_Exec_DMAKILL(u32 BaseAddr,
+				unsigned int Channel,
+				unsigned int Thread)
+{
+	u32 DbgInst0;
+	int WaitCount;
+
+	DbgInst0 = XDmaPs_DBGINST0(0, 0x01, Channel, Thread);
+
+	/* wait while debug status is busy */
+	WaitCount = 0;
+	while ((XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)
+	       & XDMAPS_DBGSTATUS_BUSY)
+	       && (WaitCount < XDMAPS_MAX_WAIT))
+		WaitCount++;
+
+	if (WaitCount >= XDMAPS_MAX_WAIT) {
+		/* wait time out */
+		xil_printf("PL330 device at %x debug status busy time out\n",
+		       BaseAddr);
+
+		return -1;
+	}
+
+	/* write debug instruction 0 */
+	XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST0_OFFSET, DbgInst0);
+
+	XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST1_OFFSET, 0);
+
+
+	/* run the command in DbgInst0 and DbgInst1 */
+	XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGCMD_OFFSET, 0);
+
+	return 0;
+}
+
+/****************************************************************************/
+/**
+*
+*
+* Free a buffer of the DMA program buffer.
+* @param	Pool the DMA program pool.
+* @param	Buf the DMA program buffer to be release.
+*
+* @return	None
+*
+* @note		None.
+*
+*****************************************************************************/
+static void XDmaPs_BufPool_Free(XDmaPs_ProgBuf *Pool, void *Buf)
+{
+	int Index;
+	Xil_AssertVoid(Pool != NULL);
+
+	for (Index = 0; Index < XDMAPS_MAX_CHAN_BUFS; Index++) {
+		if (Pool[Index].Buf == Buf) {
+			if (Pool[Index].Allocated) {
+				Pool[Index].Allocated = 0;
+			}
+		}
+	}
+}
+
+/*****************************************************************************/
+/**
+* XDmaPs_Exec_DMAGO - Execute the DMAGO to start a channel.
+*
+* @param	BaseAddr PL330 device base address
+* @param	Channel Channel number for the device
+* @param	DmaProg DMA program starting address, this should be DMA address
+*
+* @return	0 on success, -1 on time out
+*
+* @note		None.
+*
+****************************************************************************/
+static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg)
+{
+	char DmaGoProg[8];
+	u32 DbgInst0;
+	u32 DbgInst1;
+
+	int WaitCount;
+
+	XDmaPs_Instr_DMAGO(DmaGoProg, Channel, DmaProg, 0);
+
+	DbgInst0 = XDmaPs_DBGINST0(*(DmaGoProg + 1), *DmaGoProg, 0, 0);
+	DbgInst1 = (u32)DmaProg;
+
+	/* wait while debug status is busy */
+	WaitCount = 0;
+	while ((XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)
+	       & XDMAPS_DBGSTATUS_BUSY)
+	       && (WaitCount < XDMAPS_MAX_WAIT)) {
+
+		WaitCount++;
+	}
+
+	if (WaitCount >= XDMAPS_MAX_WAIT) {
+		xil_printf("PL330 device at %x debug status busy time out\r\n",
+			   BaseAddr);
+		return -1;
+	}
+
+	/* write debug instruction 0 */
+	XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST0_OFFSET, DbgInst0);
+	/* write debug instruction 1 */
+	XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST1_OFFSET, DbgInst1);
+
+
+	/* wait while the DMA Manager is busy */
+	WaitCount = 0;
+	while ((XDmaPs_ReadReg(BaseAddr,
+				XDMAPS_DS_OFFSET) & XDMAPS_DS_DMA_STATUS)
+	       != XDMAPS_DS_DMA_STATUS_STOPPED
+	       && WaitCount <= XDMAPS_MAX_WAIT) {
+		WaitCount++;
+	}
+
+	if (WaitCount >= XDMAPS_MAX_WAIT) {
+		xil_printf("PL330 device at %x debug status busy time out\r\n",
+			   BaseAddr);
+		return -1;
+	}
+
+	/* run the command in DbgInst0 and DbgInst1 */
+	XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGCMD_OFFSET, 0);
+
+	return 0;
+}
+
+
+/****************************************************************************/
+/**
+*
+* It's the generic Done ISR.
+* @param	InstPtr is the DMA instance.
+* @param	Channel is the DMA channel numer.
+*
+* @return	None.*
+*
+* @note		None.
+*
+*****************************************************************************/
+static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel)
+{
+
+	void *DmaProgBuf;
+	XDmaPs_ChannelData *ChanData;
+	XDmaPs_Cmd *DmaCmd;
+	//u32 Value;
+
+	ChanData = InstPtr->Chans + Channel;
+
+	/*Value = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
+			XDMAPS_INTSTATUS_OFFSET);*/
+
+	/* clear the interrupt status */
+	XDmaPs_WriteReg(InstPtr->Config.BaseAddress,
+			XDMAPS_INTCLR_OFFSET,
+			1 << ChanData->ChanId);
+
+	/*Value = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
+			XDMAPS_INTSTATUS_OFFSET);*/
+
+
+	DmaCmd = ChanData->DmaCmdToHw;
+	if (DmaCmd) {
+		if (!ChanData->HoldDmaProg) {
+			DmaProgBuf = (void *)DmaCmd->GeneratedDmaProg;
+			if (DmaProgBuf)
+				XDmaPs_BufPool_Free(ChanData->ProgBufPool,
+						     DmaProgBuf);
+			DmaCmd->GeneratedDmaProg = NULL;
+		}
+
+		DmaCmd->DmaStatus = 0;
+		ChanData->DmaCmdToHw = NULL;
+		ChanData->DmaCmdFromHw = DmaCmd;
+
+		if (ChanData->DoneHandler)
+			ChanData->DoneHandler(Channel, DmaCmd,
+					      ChanData->DoneRef);
+	}
+
+}
+
+
+/****************************************************************************/
+/**
+* Prints the content of the buffer in bytes
+* @param	Buf is the buffer.
+* @param	Length is the length of the DMA program.
+*
+* @return	None.
+*
+* @note		None.
+****************************************************************************/
+static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length)
+{
+	int Index;
+	for (Index = 0; Index < Length; Index++)
+		xil_printf("[%x] %x\r\n", Index, Buf[Index]);
+
+}
+/****************************************************************************/
+/**
+* Print the Dma Prog Contents.
+*
+* @param	Cmd is the command buffer.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+ void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd)
+{
+	if (Cmd->GeneratedDmaProg && Cmd->GeneratedDmaProgLength) {
+		xil_printf("Generated DMA program (%d):\r\n",
+			   Cmd->GeneratedDmaProgLength);
+		XDmaPs_Print_DmaProgBuf((char *)Cmd->GeneratedDmaProg,
+					 Cmd->GeneratedDmaProgLength);
+	}
+
+	if (Cmd->UserDmaProg && Cmd->UserDmaProgLength) {
+		xil_printf("User defined DMA program (%d):\r\n",
+			   Cmd->UserDmaProgLength);
+		XDmaPs_Print_DmaProgBuf((char *)Cmd->UserDmaProg,
+					 Cmd->UserDmaProgLength);
+	}
+}
+
+
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.h
new file mode 100644
index 0000000000000000000000000000000000000000..e0a283600e01f3514af7d1040cb545649f93a1e8
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.h
@@ -0,0 +1,352 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal 
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps.h
+* @addtogroup dmaps_v2_1
+* @{
+* @details
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  	Date     Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	hbm    08/19/10 First Release
+* 1.01a nm     12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+*		        the maximum number of channels.
+*		        Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+*                       with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h.
+*			Added the tcl file to automatically generate the
+*			xparameters.h
+* 1.02a sg     05/16/12 Made changes for doxygen and moved some function
+*			header from the xdmaps.h file to xdmaps.c file
+*			Other cleanup for coding guidelines and CR 657109
+*			and CR 657898
+*			The xdmaps_example_no_intr.c example is removed
+*			as it is using interrupts  and is similar to
+*			the interrupt example - CR 652477
+* 1.03a sg     07/16/2012 changed inline to __inline for CR665681
+* 1.04a nm     10/22/2012 Fixed CR# 681671.
+* 1.05a nm     04/15/2013 Fixed CR# 704396. Removed warnings when compiled
+*			  with -Wall and -Wextra option in bsp.
+*	       05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
+*			  function description.
+*			  Fixed CR# 704396. Removed unused variables
+*			  UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
+*			  function.
+* 1.07a asa    11/02/13. Made changes to fix compilation issues for iarcc.
+*			   Removed the PDBG prints. By default they were always
+*			   defined out and never used. The PDBG is non-standard for
+*			   Xilinx drivers and no other driver does something similar.
+*			   Since there is no easy way to fix compilation issues with
+*			   the IARCC compiler around PDBG, it is better to remove it.
+*			   Users can always use xil_printfs if they want to debug.
+* 2.0   adk    10/12/13  Updated as per the New Tcl API's
+* 2.01  kpc    08/23/14  Fixed the IAR compiler reported errors
+* 2.2   mus    08/12/16  Declared all inline functions in xdmaps.c as extern, to avoid
+*                        linker error for IAR compiler
+* 2.3   ms     01/23/17 Modified xil_printf statement in main function for all
+*                       examples to ensure that "Successfully ran" and "Failed"
+*                       strings are available in all examples. This is a fix
+*                       for CR-965028.
+*       ms     03/17/17 Added readme.txt file in examples folder for doxygen
+*                       generation.
+* </pre>
+*
+*****************************************************************************/
+
+#ifndef XDMAPS_H		/* prevent circular inclusions */
+#define XDMAPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xparameters.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+
+#include "xdmaps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;	 /**< Unique ID  of device */
+	u32 BaseAddress; /**< Base address of device (IPIF) */
+} XDmaPs_Config;
+
+
+/** DMA channle control structure. It's for AXI bus transaction.
+ * This struct will be translated into a 32-bit channel control register value.
+ */
+typedef struct {
+	unsigned int EndianSwapSize;	/**< Endian swap size. */
+	unsigned int DstCacheCtrl;	/**< Destination cache control */
+	unsigned int DstProtCtrl;	/**< Destination protection control */
+	unsigned int DstBurstLen;	/**< Destination burst length */
+	unsigned int DstBurstSize;	/**< Destination burst size */
+	unsigned int DstInc;		/**< Destination incrementing or fixed
+					 *   address */
+	unsigned int SrcCacheCtrl;	/**< Source cache control */
+	unsigned int SrcProtCtrl;	/**< Source protection control */
+	unsigned int SrcBurstLen;	/**< Source burst length */
+	unsigned int SrcBurstSize;	/**< Source burst size */
+	unsigned int SrcInc;		/**< Source incrementing or fixed
+					 *   address */
+} XDmaPs_ChanCtrl;
+
+/** DMA block descriptor stucture.
+ */
+typedef struct {
+	u32 SrcAddr;		/**< Source starting address */
+	u32 DstAddr;		/**< Destination starting address */
+	unsigned int Length;	/**< Number of bytes for the block */
+} XDmaPs_BD;
+
+/**
+ * A DMA command consisits of a channel control struct, a block descriptor,
+ * a user defined program, a pointer pointing to generated DMA program, and
+ * execution result.
+ *
+ */
+typedef struct {
+	XDmaPs_ChanCtrl ChanCtrl; 	/**< Channel Control Struct */
+	XDmaPs_BD BD;			/**< Together with SgLength field,
+					  *  it's a scatter-gather list.
+					  */
+	void *UserDmaProg;		/**< If user wants the driver to
+					  *  execute their own DMA program,
+					  *  this field points to the DMA
+					  *  program.
+					  */
+	int UserDmaProgLength;		/**< The length of user defined
+					  *  DMA program.
+					  */
+
+	void *GeneratedDmaProg;		/**< The DMA program genreated
+					 * by the driver. This field will be
+					 * set if a user invokes the DMA
+					 * program generation function. Or
+					 * the DMA command is finished and
+					 * a user informs the driver not to
+					 * release the program buffer.
+					 * This field has two purposes, one
+					 * is to ask the driver to generate
+					 * a DMA program while the DMAC is
+					 * performaning DMA transactions. The
+					 * other purpose is to debug the
+					 * driver.
+					 */
+	int GeneratedDmaProgLength;	 /**< The length of the DMA program
+					  * generated by the driver
+					  */
+	int DmaStatus;			/**< 0 on success, otherwise error code
+					 */
+	u32 ChanFaultType;	/**< Channel fault type in case of fault
+				 */
+	u32 ChanFaultPCAddr;	/**< Channel fault PC address
+				 */
+} XDmaPs_Cmd;
+
+/**
+ * It's the done handler a user can set for a channel
+ */
+typedef void (*XDmaPsDoneHandler) (unsigned int Channel,
+				    XDmaPs_Cmd *DmaCmd,
+				    void *CallbackRef);
+
+/**
+ * It's the fault handler a user can set for a channel
+ */
+typedef void (*XDmaPsFaultHandler) (unsigned int Channel,
+				     XDmaPs_Cmd *DmaCmd,
+				     void *CallbackRef);
+
+#define XDMAPS_MAX_CHAN_BUFS	2
+#define XDMAPS_CHAN_BUF_LEN	128
+
+/**
+ * The XDmaPs_ProgBuf is the struct for a DMA program buffer.
+ */
+typedef struct {
+	char Buf[XDMAPS_CHAN_BUF_LEN];  /**< The actual buffer the holds the
+					  *  content */
+	unsigned Len;			/**< The actual length of the DMA
+					  *  program in bytes. */
+	int Allocated;			/**< A tag indicating whether the
+					  *  buffer is allocated or not */
+} XDmaPs_ProgBuf;
+
+/**
+ * The XDmaPs_ChannelData is a struct to book keep individual channel of
+ * the DMAC.
+ */
+typedef struct {
+	unsigned DevId;		 	/**< Device id indicating which DMAC */
+	unsigned ChanId; 		/**< Channel number of the DMAC */
+	XDmaPs_ProgBuf ProgBufPool[XDMAPS_MAX_CHAN_BUFS]; /**< A pool of
+							      program buffers*/
+	XDmaPsDoneHandler DoneHandler; 	/**< Done interrupt handler */
+	void *DoneRef;			/**< Done interrupt callback data */
+	XDmaPs_Cmd *DmaCmdToHw; 	/**< DMA command being executed */
+	XDmaPs_Cmd *DmaCmdFromHw; 	/**< DMA  command that is finished.
+				     	  *  This field is for debugging purpose
+				     	  */
+	int HoldDmaProg;		/**< A tag indicating whether to hold the
+					  *  DMA program after the DMA is done.
+					  */
+
+} XDmaPs_ChannelData;
+
+/**
+ * The XDmaPs driver instance data structure. A pointer to an instance data
+ * structure is passed around by functions to refer to a specific driver
+ * instance.
+ */
+typedef struct {
+	XDmaPs_Config Config;	/**< Configuration data structure */
+	int IsReady;		/**< Device is Ready */
+	int CacheLength;	/**< icache length */
+	XDmaPsFaultHandler FaultHandler; /**< fault interrupt handler */
+	void *FaultRef;	/**< fault call back data */
+	XDmaPs_ChannelData Chans[XDMAPS_CHANNELS_PER_DEV];
+	/**<
+	 * channel data
+	 */
+} XDmaPs;
+
+/*
+ * Functions implemented in xdmaps.c
+ */
+int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
+			  XDmaPs_Config *Config,
+			  u32 EffectiveAddr);
+
+int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
+		  XDmaPs_Cmd *Cmd,
+		  int HoldDmaProg);
+
+int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel);
+int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel,
+		       XDmaPs_Cmd *Cmd);
+int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel,
+			XDmaPs_Cmd *Cmd);
+void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
+
+
+int XDmaPs_ResetManager(XDmaPs *InstPtr);
+int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel);
+
+
+int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
+			   unsigned Channel,
+			   XDmaPsDoneHandler DoneHandler,
+			   void *CallbackRef);
+
+int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
+			    XDmaPsFaultHandler FaultHandler,
+			    void *CallbackRef);
+
+void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
+
+/**
+ * To avoid linking error,Declare all inline functions as extern for
+ * IAR compiler
+ */
+#ifdef __ICCARM__
+extern INLINE int XDmaPs_Instr_DMAEND(char *DmaProg);
+extern INLINE void XDmaPs_Memcpy4(char *Dst, char *Src);
+extern INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
+			       u32 Imm, unsigned int Ns);
+extern INLINE int XDmaPs_Instr_DMALD(char *DmaProg);
+extern INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
+	       unsigned LoopIterations);
+extern INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc);
+extern INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm);
+extern INLINE int XDmaPs_Instr_DMANOP(char *DmaProg);
+extern INLINE int XDmaPs_Instr_DMARMB(char *DmaProg);
+extern INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber);
+extern INLINE int XDmaPs_Instr_DMAST(char *DmaProg);
+extern INLINE int XDmaPs_Instr_DMAWMB(char *DmaProg);
+extern INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize);
+extern INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize);
+#endif
+
+/**
+ * Driver done interrupt service routines for the channels.
+ * We need this done ISR mainly because the driver needs to release the
+ * DMA program buffer. This is the one that connects the GIC
+ */
+void XDmaPs_DoneISR_0(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_1(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_2(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_3(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_4(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_5(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_6(XDmaPs *InstPtr);
+void XDmaPs_DoneISR_7(XDmaPs *InstPtr);
+
+/**
+ * Driver fault interrupt service routine
+ */
+void XDmaPs_FaultISR(XDmaPs *InstPtr);
+
+
+/*
+ * Static loopup function implemented in xdmaps_sinit.c
+ */
+XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId);
+
+
+/*
+ * self-test functions in xdmaps_selftest.c
+ */
+int XDmaPs_SelfTest(XDmaPs *InstPtr);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_g.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..00ed746e1f881f6e8ce79d9886aad5f88adbe85e
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_g.c
@@ -0,0 +1,59 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xdmaps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XDmaPs_Config XDmaPs_ConfigTable[XPAR_XDMAPS_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_DMA_NS_DEVICE_ID,
+		XPAR_PS7_DMA_NS_BASEADDR
+	},
+	{
+		XPAR_PS7_DMA_S_DEVICE_ID,
+		XPAR_PS7_DMA_S_BASEADDR
+	}
+};
+
+
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.c
new file mode 100644
index 0000000000000000000000000000000000000000..9fc3dd8986ab57448a0f6c7cde45a263a7e6ad15
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.c
@@ -0,0 +1,116 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal 
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps_hw.c
+* @addtogroup dmaps_v2_1
+* @{
+*
+* This file contains the implementation of the interface reset functionality 
+*	for XDmaPs driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  	Date     Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.06a kpc 10/07/13 First release
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xdmaps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+#ifndef XDMAPS_MAX_WAIT
+#define XDMAPS_MAX_WAIT 4000
+#endif
+/************************** Function Prototypes *****************************/
+
+/************************** Variable Definitions ****************************/
+
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given dmaps interface by 
+* configuring the appropriate control bits in the dmaps specifc registers
+* the dmaps reset squence involves the following steps
+*	Disable all the interuupts 
+*	Clear the pending interrupts
+*	Kill all the active channel threads
+*	Kill the manager thread
+*
+* @param   BaseAddress of the interface
+*
+* @return N/A
+*
+* @note 
+* This function will not modify the slcr registers that are relavant for 
+* dmaps controller
+******************************************************************************/
+void XDmaPs_ResetHw(u32 BaseAddress)
+{
+	u32 DbgInst;
+	u32 WaitCount = 0;
+	u32 ChanIndex;
+
+	/* Disable all the interrupts */
+	XDmaPs_WriteReg(BaseAddress, XDMAPS_INTEN_OFFSET, 0x00);
+	/* Clear the interrupts */
+	XDmaPs_WriteReg(BaseAddress, XDMAPS_INTCLR_OFFSET, XDMAPS_INTCLR_ALL_MASK);
+	/* Kill the dma channel threads */
+	for (ChanIndex=0; ChanIndex < XDMAPS_CHANNELS_PER_DEV; ChanIndex++) {
+		while ((XDmaPs_ReadReg(BaseAddress, XDMAPS_DBGSTATUS_OFFSET)
+				& XDMAPS_DBGSTATUS_BUSY)
+				&& (WaitCount < XDMAPS_MAX_WAIT))
+				WaitCount++;
+
+		DbgInst = XDmaPs_DBGINST0(0, 0x01, ChanIndex, 1);	
+		XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst);
+		XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);	
+		XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0);
+	}	
+	/* Kill the manager thread	*/
+	DbgInst = XDmaPs_DBGINST0(0, 0x01, 0, 0);	
+	XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst);
+	XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);	
+	XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0);	
+}
+
+
+
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..1186107ac0c3adbfbe389b1dae44e15edfa5765d
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.h
@@ -0,0 +1,293 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal 
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xdmaps_hw.h
+* @addtogroup dmaps_v2_1
+* @{
+*
+* This header file contains the hardware interface of an XDmaPs device.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who   Date     Changes
+* ----- ----  -------- ----------------------------------------------
+* 1.00a	hbm   08/18/10 First Release
+* 1.01a nm    12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+*		       the maximum number of channels.
+*		       Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+*                      with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h
+* 1.02a sg    05/16/12 Made changes for doxygen
+* 1.06a kpc   07/10/13 Added function prototype
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XDMAPS_HW_H		/* prevent circular inclusions */
+#define XDMAPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the DMAC.
+ * @{
+ */
+
+#define XDMAPS_DS_OFFSET		0x000 /* DMA Status Register */
+#define XDMAPS_DPC_OFFSET	0x004 /* DMA Program Counter Rregister */
+#define XDMAPS_INTEN_OFFSET	0X020 /* DMA Interrupt Enable Register */
+#define XDMAPS_ES_OFFSET		0x024 /* DMA Event Status Register */
+#define XDMAPS_INTSTATUS_OFFSET	0x028 /* DMA Interrupt Status Register
+					       */
+#define XDMAPS_INTCLR_OFFSET	0x02c /* DMA Interrupt Clear Register */
+#define XDMAPS_FSM_OFFSET 	0x030 /* DMA Fault Status DMA Manager
+				       * Register
+				       */
+#define XDMAPS_FSC_OFFSET	0x034 /* DMA Fault Status DMA Chanel Register
+				       */
+#define XDMAPS_FTM_OFFSET	0x038 /* DMA Fault Type DMA Manager Register */
+
+#define XDMAPS_FTC0_OFFSET	0x040 /* DMA Fault Type for DMA Channel 0 */
+/*
+ * The offset for the rest of the FTC registers is calculated as
+ * FTC0 + dev_chan_num * 4
+ */
+#define XDmaPs_FTCn_OFFSET(ch)	(XDMAPS_FTC0_OFFSET + (ch) * 4)
+
+#define XDMAPS_CS0_OFFSET	0x100 /* Channel Status for DMA Channel 0 */
+/*
+ * The offset for the rest of the CS registers is calculated as
+ * CS0 + * dev_chan_num * 0x08
+ */
+#define XDmaPs_CSn_OFFSET(ch)	(XDMAPS_CS0_OFFSET + (ch) * 8)
+
+#define XDMAPS_CPC0_OFFSET	0x104 /* Channel Program Counter for DMA
+				       * Channel 0
+				       */
+/*
+ * The offset for the rest of the CPC registers is calculated as
+ * CPC0 + dev_chan_num * 0x08
+ */
+#define XDmaPs_CPCn_OFFSET(ch)	(XDMAPS_CPC0_OFFSET + (ch) * 8)
+
+#define XDMAPS_SA_0_OFFSET	0x400 /* Source Address Register for DMA
+				       * Channel 0
+				       */
+/* The offset for the rest of the SA registers is calculated as
+ * SA_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_SA_n_OFFSET(ch)	(XDMAPS_SA_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_DA_0_OFFSET	0x404 /* Destination Address Register for
+				       * DMA Channel 0
+				       */
+/* The offset for the rest of the DA registers is calculated as
+ * DA_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_DA_n_OFFSET(ch)	(XDMAPS_DA_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_CC_0_OFFSET	0x408 /* Channel Control Register for
+				       * DMA Channel 0
+				       */
+/*
+ * The offset for the rest of the CC registers is calculated as
+ * CC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_CC_n_OFFSET(ch)	(XDMAPS_CC_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_LC0_0_OFFSET	0x40C /* Loop Counter 0 for DMA Channel 0 */
+/*
+ * The offset for the rest of the LC0 registers is calculated as
+ * LC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_LC0_n_OFFSET(ch)	(XDMAPS_LC0_0_OFFSET + (ch) * 0x20)
+#define XDMAPS_LC1_0_OFFSET	0x410 /* Loop Counter 1 for DMA Channel 0 */
+/*
+ * The offset for the rest of the LC1 registers is calculated as
+ * LC_0 + dev_chan_num * 0x20
+ */
+#define XDmaPs_LC1_n_OFFSET(ch)	(XDMAPS_LC1_0_OFFSET + (ch) * 0x20)
+
+#define XDMAPS_DBGSTATUS_OFFSET	0xD00 /* Debug Status Register */
+#define XDMAPS_DBGCMD_OFFSET	0xD04 /* Debug Command Register */
+#define XDMAPS_DBGINST0_OFFSET	0xD08 /* Debug Instruction 0 Register */
+#define XDMAPS_DBGINST1_OFFSET	0xD0C /* Debug Instruction 1 Register */
+
+#define XDMAPS_CR0_OFFSET	0xE00 /* Configuration Register 0 */
+#define XDMAPS_CR1_OFFSET	0xE04 /* Configuration Register 1 */
+#define XDMAPS_CR2_OFFSET	0xE08 /* Configuration Register 2 */
+#define XDMAPS_CR3_OFFSET	0xE0C /* Configuration Register 3 */
+#define XDMAPS_CR4_OFFSET	0xE10 /* Configuration Register 4 */
+#define XDMAPS_CRDN_OFFSET	0xE14 /* Configuration Register Dn */
+
+#define XDMAPS_PERIPH_ID_0_OFFSET	0xFE0 /* Peripheral Identification
+					       * Register 0
+					       */
+#define XDMAPS_PERIPH_ID_1_OFFSET	0xFE4 /* Peripheral Identification
+					       * Register 1
+					       */
+#define XDMAPS_PERIPH_ID_2_OFFSET	0xFE8 /* Peripheral Identification
+					       * Register 2
+					       */
+#define XDMAPS_PERIPH_ID_3_OFFSET	0xFEC /* Peripheral Identification
+					       * Register 3
+					       */
+#define XDMAPS_PCELL_ID_0_OFFSET	0xFF0 /* PrimeCell Identification
+				       * Register 0
+				       */
+#define XDMAPS_PCELL_ID_1_OFFSET	0xFF4 /* PrimeCell Identification
+				       * Register 1
+				       */
+#define XDMAPS_PCELL_ID_2_OFFSET	0xFF8 /* PrimeCell Identification
+				       * Register 2
+				       */
+#define XDMAPS_PCELL_ID_3_OFFSET	0xFFC /* PrimeCell Identification
+				       * Register 3
+				       */
+
+/*
+ * Some useful register masks
+ */
+#define XDMAPS_DS_DMA_STATUS		0x0F /* DMA status mask */
+#define XDMAPS_DS_DMA_STATUS_STOPPED	0x00 /* debug status busy mask */
+
+#define XDMAPS_DBGSTATUS_BUSY		0x01 /* debug status busy mask */
+
+#define XDMAPS_CS_ACTIVE_MASK		0x07 /* channel status active mask,
+					      * llast 3 bits of CS register
+					      */
+
+#define XDMAPS_CR1_I_CACHE_LEN_MASK	0x07 /* i_cache_len mask */
+
+
+/*
+ * XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register.
+ * @b1: Instruction byte 1
+ * @b0: Instruction byte 0
+ * @ch: Channel number
+ * @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel
+ */
+#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \
+	(((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1)))
+
+/* @} */
+
+/** @name Control Register
+ *
+ * The Control register (CR) controls the major functions of the device.
+ *
+ * Control Register Bit Definition
+ */
+
+/* @}*/
+
+
+#define XDMAPS_CHANNELS_PER_DEV		8
+
+
+/** @name Mode Register
+ *
+ * The mode register (MR) defines the mode of transfer as well as the data
+ * format. If this register is modified during transmission or reception,
+ * data validity cannot be guaranteed.
+ *
+ * Mode Register Bit Definition
+ * @{
+ */
+
+/* @} */
+
+
+/** @name Interrupt Registers
+ *
+ * Interrupt control logic uses the interrupt enable register (IER) and the
+ * interrupt disable register (IDR) to set the value of the bits in the
+ * interrupt mask register (IMR). The IMR determines whether to pass an
+ * interrupt to the interrupt status register (ISR).
+ * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
+ * interrupt. IMR and ISR are read only, and IER and IDR are write only.
+ * Reading either IER or IDR returns 0x00.
+ *
+ * All four registers have the same bit definitions.
+ *
+ * @{
+ */
+
+/* @} */
+#define XDMAPS_INTCLR_ALL_MASK		0xFF
+
+#define XDmaPs_ReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write a DMAC register.
+*
+* @param    BaseAddress contains the base address of the device.
+* @param    RegOffset contains the offset from the base address of the device.
+* @param    RegisterValue is the value to be written to the register.
+*
+* @return   None.
+*
+* @note
+* C-Style signature:
+*    void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset,
+*                          u32 RegisterValue)
+******************************************************************************/
+#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+    Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes *****************************/
+/*
+ * Perform reset operation to the dmaps interface
+ */
+void XDmaPs_ResetHw(u32 BaseAddr);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_selftest.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_selftest.c
new file mode 100644
index 0000000000000000000000000000000000000000..eae0846b5c8fb272c139627f1da165db639fab25
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_selftest.c
@@ -0,0 +1,110 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal 
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps_selftest.c
+* @addtogroup dmaps_v2_1
+* @{
+*
+* This file contains the self-test functions for the XDmaPs driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00	hbm 	03/29/2010 First Release
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xdmaps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/****************************************************************************/
+/**
+*
+* This function runs a self-test on the driver and hardware device. This self
+* test performs a local loopback and verifies data can be sent and received.
+*
+* The time for this test is proportional to the baud rate that has been set
+* prior to calling this function.
+*
+* The mode and control registers are restored before return.
+*
+* @param	InstPtr is a pointer to the XDmaPs instance
+*
+* @return
+*
+*		- XST_SUCCESS if the test was successful
+*		- XST_FAILURE if the test failed
+*
+* @note
+*
+* This function can hang if the hardware is not functioning properly.
+*
+******************************************************************************/
+int XDmaPs_SelfTest(XDmaPs *InstPtr)
+{
+	u32 BaseAddr = InstPtr->Config.BaseAddress;
+	int i;
+
+	if (XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)
+	    & XDMAPS_DBGSTATUS_BUSY)
+		return XST_FAILURE;
+
+	for (i = 0; i < XDMAPS_CHANNELS_PER_DEV; i++) {
+		if (XDmaPs_ReadReg(BaseAddr,
+				    XDmaPs_CSn_OFFSET(i)))
+			return XST_FAILURE;
+	}
+	return XST_SUCCESS;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_sinit.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..20866cf57133690a8494a5dfdb7e24b39e375c9d
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_sinit.c
@@ -0,0 +1,104 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal 
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xdmaps_sinit.c
+* @addtogroup dmaps_v2_1
+* @{
+*
+* The implementation of the XDmaPs driver's static initialzation
+* functionality.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00  hbm  08/13/10 First Release
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xdmaps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Variable Definitions ****************************/
+extern XDmaPs_Config XDmaPs_ConfigTable[];
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId contains the ID of the device
+*
+* @return
+*
+* A pointer to the configuration structure or NULL if the specified device
+* is not in the system.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId)
+{
+	XDmaPs_Config *CfgPtr = NULL;
+
+	int i;
+
+	for (i = 0; i < XPAR_XDMAPS_NUM_INSTANCES; i++) {
+		if (XDmaPs_ConfigTable[i].DeviceId == DeviceId) {
+			CfgPtr = &XDmaPs_ConfigTable[i];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/Makefile b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..7002e6223103acee2fa1224c2c241cde4bd095ab
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xemacps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling emacps"
+
+xemacps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xemacps_includes
+
+xemacps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps.c
new file mode 100644
index 0000000000000000000000000000000000000000..26df03c3dbb0017990d37f0796687124bbd4eafe
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps.c
@@ -0,0 +1,489 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps.c
+* @addtogroup emacps_v3_1
+* @{
+*
+* The XEmacPs driver. Functions in this file are the minimum required functions
+* for this driver. See xemacps.h for a detailed description of the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 2.1  srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification and
+*		      64-bit changes.
+* 3.00 kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.0  hk   02/20/15 Added support for jumbo frames. Increase AHB burst.
+*                    Disable extended mode. Perform all 64 bit changes under
+*                    check for arch64.
+* 3.1  hk   08/10/15 Update upper 32 bit tx and rx queue ptr registers
+*
+* </pre>
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+void XEmacPs_StubHandler(void);	/* Default handler routine */
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+* Initialize a specific XEmacPs instance/driver. The initialization entails:
+* - Initialize fields of the XEmacPs instance structure
+* - Reset hardware and apply default options
+* - Configure the DMA channels
+*
+* The PHY is setup independently from the device. Use the MII or whatever other
+* interface may be present for setup.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param CfgPtr is the device configuration structure containing required
+*        hardware build data.
+* @param EffectiveAddress is the base address of the device. If address
+*        translation is not utilized, this parameter can be passed in using
+*        CfgPtr->Config.BaseAddress to specify the physical base address.
+*
+* @return
+* - XST_SUCCESS if initialization was successful
+*
+******************************************************************************/
+LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
+			   UINTPTR EffectiveAddress)
+{
+	/* Verify arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(CfgPtr != NULL);
+
+	/* Set device base address and ID */
+	InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddress;
+
+	/* Set callbacks to an initial stub routine */
+	InstancePtr->SendHandler = ((XEmacPs_Handler)((void*)XEmacPs_StubHandler));
+	InstancePtr->RecvHandler = ((XEmacPs_Handler)(void*)XEmacPs_StubHandler);
+	InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void*)XEmacPs_StubHandler);
+
+	/* Reset the hardware and set default options */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+	XEmacPs_Reset(InstancePtr);
+
+	return (LONG)(XST_SUCCESS);
+}
+
+
+/*****************************************************************************/
+/**
+* Start the Ethernet controller as follows:
+*   - Enable transmitter if XTE_TRANSMIT_ENABLE_OPTION is set
+*   - Enable receiver if XTE_RECEIVER_ENABLE_OPTION is set
+*   - Start the SG DMA send and receive channels and enable the device
+*     interrupt
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+*
+* @return N/A
+*
+* @note
+* Hardware is configured with scatter-gather DMA, the driver expects to start
+* the scatter-gather channels and expects that the user has previously set up
+* the buffer descriptor lists.
+*
+* This function makes use of internal resources that are shared between the
+* Start, Stop, and Set/ClearOptions functions. So if one task might be setting
+* device options while another is trying to start the device, the user is
+* required to provide protection of this shared data (typically using a
+* semaphore).
+*
+* This function must not be preempted by an interrupt that may service the
+* device.
+*
+******************************************************************************/
+void XEmacPs_Start(XEmacPs *InstancePtr)
+{
+	u32 Reg;
+
+	/* Assert bad arguments and conditions */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Start DMA */
+	/* When starting the DMA channels, both transmit and receive sides
+	 * need an initialized BD list.
+	 */
+	if (InstancePtr->Version == 2) {
+		Xil_AssertVoid(InstancePtr->RxBdRing.BaseBdAddr != 0);
+		Xil_AssertVoid(InstancePtr->TxBdRing.BaseBdAddr != 0);
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_RXQBASE_OFFSET,
+			   InstancePtr->RxBdRing.BaseBdAddr);
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_TXQBASE_OFFSET,
+			   InstancePtr->TxBdRing.BaseBdAddr);
+	}
+
+	/* clear any existed int status */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
+			   XEMACPS_IXR_ALL_MASK);
+
+	/* Enable transmitter if not already enabled */
+	if ((InstancePtr->Options & (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION)!=0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+		if ((!(Reg & XEMACPS_NWCTRL_TXEN_MASK))==TRUE) {
+			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+					   XEMACPS_NWCTRL_OFFSET,
+				   Reg | (u32)XEMACPS_NWCTRL_TXEN_MASK);
+		}
+	}
+
+	/* Enable receiver if not already enabled */
+	if ((InstancePtr->Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+		if ((!(Reg & XEMACPS_NWCTRL_RXEN_MASK))==TRUE) {
+			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+					   XEMACPS_NWCTRL_OFFSET,
+				   Reg | (u32)XEMACPS_NWCTRL_RXEN_MASK);
+		}
+	}
+
+        /* Enable TX and RX interrupts */
+        XEmacPs_IntEnable(InstancePtr, (XEMACPS_IXR_TX_ERR_MASK |
+	XEMACPS_IXR_RX_ERR_MASK | (u32)XEMACPS_IXR_FRAMERX_MASK |
+	(u32)XEMACPS_IXR_TXCOMPL_MASK));
+
+	/* Enable TX Q1 Interrupts */
+	if (InstancePtr->Version > 2)
+		XEmacPs_IntQ1Enable(InstancePtr, XEMACPS_INTQ1_IXR_ALL_MASK);
+
+	/* Mark as started */
+	InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
+
+	return;
+}
+
+
+/*****************************************************************************/
+/**
+* Gracefully stop the Ethernet MAC as follows:
+*   - Disable all interrupts from this device
+*   - Stop DMA channels
+*   - Disable the tansmitter and receiver
+*
+* Device options currently in effect are not changed.
+*
+* This function will disable all interrupts. Default interrupts settings that
+* had been enabled will be restored when XEmacPs_Start() is called.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+*
+* @note
+* This function makes use of internal resources that are shared between the
+* Start, Stop, SetOptions, and ClearOptions functions. So if one task might be
+* setting device options while another is trying to start the device, the user
+* is required to provide protection of this shared data (typically using a
+* semaphore).
+*
+* Stopping the DMA channels causes this function to block until the DMA
+* operation is complete.
+*
+******************************************************************************/
+void XEmacPs_Stop(XEmacPs *InstancePtr)
+{
+	u32 Reg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Disable all interrupts */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
+			   XEMACPS_IXR_ALL_MASK);
+
+	/* Disable the receiver & transmitter */
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWCTRL_OFFSET);
+	Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
+	Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK);
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_NWCTRL_OFFSET, Reg);
+
+	/* Mark as stopped */
+	InstancePtr->IsStarted = 0U;
+}
+
+
+/*****************************************************************************/
+/**
+* Perform a graceful reset of the Ethernet MAC. Resets the DMA channels, the
+* transmitter, and the receiver.
+*
+* Steps to reset
+* - Stops transmit and receive channels
+* - Stops DMA
+* - Configure transmit and receive buffer size to default
+* - Clear transmit and receive status register and counters
+* - Clear all interrupt sources
+* - Clear phy (if there is any previously detected) address
+* - Clear MAC addresses (1-4) as well as Type IDs and hash value
+*
+* All options are placed in their default state. Any frames in the
+* descriptor lists will remain in the lists. The side effect of doing
+* this is that after a reset and following a restart of the device, frames
+* were in the list before the reset may be transmitted or received.
+*
+* The upper layer software is responsible for re-configuring (if necessary)
+* and restarting the MAC after the reset. Note also that driver statistics
+* are not cleared on reset. It is up to the upper layer software to clear the
+* statistics if needed.
+*
+* When a reset is required, the driver notifies the upper layer software of
+* this need through the ErrorHandler callback and specific status codes.
+* The upper layer software is responsible for calling this Reset function
+* and then re-configuring the device.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+*
+******************************************************************************/
+void XEmacPs_Reset(XEmacPs *InstancePtr)
+{
+	u32 Reg;
+	u8 i;
+	s8 EmacPs_zero_MAC[6] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Stop the device and reset hardware */
+	XEmacPs_Stop(InstancePtr);
+	InstancePtr->Options = XEMACPS_DEFAULT_OPTIONS;
+
+	InstancePtr->Version = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, 0xFC);
+
+	InstancePtr->Version = (InstancePtr->Version >> 16) & 0xFFF;
+
+	InstancePtr->MaxMtuSize = XEMACPS_MTU;
+	InstancePtr->MaxFrameSize = XEMACPS_MTU + XEMACPS_HDR_SIZE +
+					XEMACPS_TRL_SIZE;
+	InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
+					XEMACPS_HDR_VLAN_SIZE;
+	InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_MASK;
+
+	/* Setup hardware with default values */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_NWCTRL_OFFSET,
+			(XEMACPS_NWCTRL_STATCLR_MASK |
+			XEMACPS_NWCTRL_MDEN_MASK) &
+			(u32)(~XEMACPS_NWCTRL_LOOPEN_MASK));
+
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_NWCFG_OFFSET);
+	Reg &= XEMACPS_NWCFG_MDCCLKDIV_MASK;
+
+	Reg = Reg | (u32)XEMACPS_NWCFG_100_MASK |
+			(u32)XEMACPS_NWCFG_FDEN_MASK |
+			(u32)XEMACPS_NWCFG_UCASTHASHEN_MASK;
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCFG_OFFSET, Reg);
+	if (InstancePtr->Version > 2) {
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET,
+			(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET) |
+				XEMACPS_NWCFG_DWIDTH_64_MASK));
+	}
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_DMACR_OFFSET,
+			(((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) +
+				(((((u32)XEMACPS_RX_BUF_SIZE %
+				(u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
+				(u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
+				(u32)(XEMACPS_DMACR_RXBUF_MASK)) |
+				(u32)XEMACPS_DMACR_RXSIZE_MASK |
+				(u32)XEMACPS_DMACR_TXSIZE_MASK);
+
+
+	/* Single bursts */
+	/* FIXME: Why Single bursts? */
+	if (InstancePtr->Version > 2) {
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
+			(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET) |
+#ifdef __aarch64__
+			(u32)XEMACPS_DMACR_ADDR_WIDTH_64 |
+#endif
+			(u32)XEMACPS_DMACR_INCR16_AHB_BURST));
+	}
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_TXSR_OFFSET, 0x0U);
+
+	XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_SEND);
+	if (InstancePtr->Version > 2)
+		XEmacPs_SetQueuePtr(InstancePtr, 0, 0x01U, (u16)XEMACPS_SEND);
+	XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_RECV);
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_RXSR_OFFSET, 0x0U);
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
+			   XEMACPS_IXR_ALL_MASK);
+
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_ISR_OFFSET);
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
+			   Reg);
+
+	XEmacPs_ClearHash(InstancePtr);
+
+	for (i = 1U; i < 5U; i++) {
+		(void)XEmacPs_SetMacAddress(InstancePtr, EmacPs_zero_MAC, i);
+		(void)XEmacPs_SetTypeIdCheck(InstancePtr, 0x00000000U, i);
+	}
+
+	/* clear all counters */
+	for (i = 0U; i < (u8)((XEMACPS_LAST_OFFSET - XEMACPS_OCTTXL_OFFSET) / 4U);
+	     i++) {
+		(void)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+                                   XEMACPS_OCTTXL_OFFSET + (u32)(((u32)i) * ((u32)4)));
+	}
+
+	/* Disable the receiver */
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWCTRL_OFFSET);
+	Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_NWCTRL_OFFSET, Reg);
+
+	/* Sync default options with hardware but leave receiver and
+         * transmitter disabled. They get enabled with XEmacPs_Start() if
+	 * XEMACPS_TRANSMITTER_ENABLE_OPTION and
+         * XEMACPS_RECEIVER_ENABLE_OPTION are set.
+	 */
+	(void)XEmacPs_SetOptions(InstancePtr, InstancePtr->Options &
+			    ~((u32)XEMACPS_TRANSMITTER_ENABLE_OPTION |
+			      (u32)XEMACPS_RECEIVER_ENABLE_OPTION));
+
+	(void)XEmacPs_ClearOptions(InstancePtr, ~InstancePtr->Options);
+}
+
+
+/******************************************************************************/
+/**
+ * This is a stub for the asynchronous callbacks. The stub is here in case the
+ * upper layer forgot to set the handler(s). On initialization, all handlers are
+ * set to this callback. It is considered an error for this handler to be
+ * invoked.
+ *
+ ******************************************************************************/
+void XEmacPs_StubHandler(void)
+{
+	Xil_AssertVoidAlways();
+}
+
+/*****************************************************************************/
+/**
+* This function sets the start address of the transmit/receive buffer queue.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @QPtr		Address of the Queue to be written
+* @QueueNum	Buffer Queue Index
+* @Direction	Transmit/Recive
+*
+* @note
+* The buffer queue addresses has to be set before starting the transfer, so
+* this function has to be called in prior to XEmacPs_Start()
+*
+******************************************************************************/
+void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
+			 u16 Direction)
+{
+	/* Assert bad arguments and conditions */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+        /* If already started, then there is nothing to do */
+        if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+                return;
+        }
+
+	if (QueueNum == 0x00U) {
+		if (Direction == XEMACPS_SEND) {
+			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_TXQBASE_OFFSET,
+				(QPtr & ULONG64_LO_MASK));
+		} else {
+			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_RXQBASE_OFFSET,
+				(QPtr & ULONG64_LO_MASK));
+		}
+	}
+	 else {
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_TXQ1BASE_OFFSET,
+			(QPtr & ULONG64_LO_MASK));
+	}
+#ifdef __aarch64__
+	if (Direction == XEMACPS_SEND) {
+		/* Set the MSB of TX Queue start address */
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_MSBBUF_TXQBASE_OFFSET,
+				(u32)((QPtr & ULONG64_HI_MASK) >> 32U));
+	} else {
+		/* Set the MSB of RX Queue start address */
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_MSBBUF_RXQBASE_OFFSET,
+				(u32)((QPtr & ULONG64_HI_MASK) >> 32U));
+	}
+#endif
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps.h
new file mode 100644
index 0000000000000000000000000000000000000000..1dbdbb20d80a732c8424cf28b6e0d27c4e425ab9
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps.h
@@ -0,0 +1,798 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+ *
+ * @file xemacps.h
+* @addtogroup emacps_v3_1
+* @{
+* @details
+ *
+ * The Xilinx Embedded Processor Block Ethernet driver.
+ *
+ * For a full description of XEMACPS features, please see the hardware spec.
+ * This driver supports the following features:
+ *   - Memory mapped access to host interface registers
+ *   - Statistics counter registers for RMON/MIB
+ *   - API for interrupt driven frame transfers for hardware configured DMA
+ *   - Virtual memory support
+ *   - Unicast, broadcast, and multicast receive address filtering
+ *   - Full and half duplex operation
+ *   - Automatic PAD & FCS insertion and stripping
+ *   - Flow control
+ *   - Support up to four 48bit addresses
+ *   - Address checking for four specific 48bit addresses
+ *   - VLAN frame support
+ *   - Pause frame support
+ *   - Large frame support up to 1536 bytes
+ *   - Checksum offload
+ *
+ * <b>Driver Description</b>
+ *
+ * The device driver enables higher layer software (e.g., an application) to
+ * communicate to the XEmacPs. The driver handles transmission and reception
+ * of Ethernet frames, as well as configuration and control. No pre or post
+ * processing of frame data is performed. The driver does not validate the
+ * contents of an incoming frame in addition to what has already occurred in
+ * hardware.
+ * A single device driver can support multiple devices even when those devices
+ * have significantly different configurations.
+ *
+ * <b>Initialization & Configuration</b>
+ *
+ * The XEmacPs_Config structure is used by the driver to configure itself.
+ * This configuration structure is typically created by the tool-chain based
+ * on hardware build properties.
+ *
+ * The driver instance can be initialized in
+ *
+ *   - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress):  Uses a
+ *     configuration structure provided by the caller. If running in a system
+ *     with address translation, the provided virtual memory base address
+ *     replaces the physical address present in the configuration structure.
+ *
+ * The device supports DMA only as current development plan. No FIFO mode is
+ * supported. The driver expects to start the DMA channels and expects that
+ * the user has set up the buffer descriptor lists.
+ *
+ * <b>Interrupts and Asynchronous Callbacks</b>
+ *
+ * The driver has no dependencies on the interrupt controller. When an
+ * interrupt occurs, the handler will perform a small amount of
+ * housekeeping work, determine the source of the interrupt, and call the
+ * appropriate callback function. All callbacks are registered by the user
+ * level application.
+ *
+ * <b>Virtual Memory</b>
+ *
+ * All virtual to physical memory mappings must occur prior to accessing the
+ * driver API.
+ *
+ * For DMA transactions, user buffers supplied to the driver must be in terms
+ * of their physical address.
+ *
+ * <b>DMA</b>
+ *
+ * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames.
+ * These BDs are typically chained together into a list the hardware follows
+ * when transferring data in and out of the packet buffers. Each BD describes
+ * a memory region containing either a full or partial Ethernet packet.
+ *
+ * Interrupt coalescing is not suppoted from this built-in DMA engine.
+ *
+ * This API requires the user to understand how the DMA operates. The
+ * following paragraphs provide some explanation, but the user is encouraged
+ * to read documentation in xemacps_bdring.h as well as study example code
+ * that accompanies this driver.
+ *
+ * The API is designed to get BDs to and from the DMA engine in the most
+ * efficient means possible. The first step is to establish a  memory region
+ * to contain all BDs for a specific channel. This is done with
+ * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will
+ * follow as BDs are processed. The ring will consist of a user defined number
+ * of BDs which will all be partially initialized. For example on the transmit
+ * channel, the driver will initialize all BDs' so that they are configured
+ * for transmit. The more fields that can be permanently setup at
+ * initialization, then the fewer accesses will be needed to each BD while
+ * the DMA engine is in operation resulting in better throughput and CPU
+ * utilization. The best case initialization would require the user to set
+ * only a frame buffer address and length prior to submitting the BD to the
+ * engine.
+ *
+ * BDs move through the engine with the help of functions
+ * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(),
+ * and XEmacPs_BdRingFree().
+ * All these functions handle BDs that are in place. That is, there are no
+ * copies of BDs kept anywhere and any BD the user interacts with is an actual
+ * BD from the same ring hardware accesses.
+ *
+ * BDs in the ring go through a series of states as follows:
+ *   1. Idle. The driver controls BDs in this state.
+ *   2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to
+ *      reserve BD(s). Once allocated, the user may setup the BD(s) with
+ *      frame buffer address, length, and other attributes. The user controls
+ *      BDs in this state.
+ *   3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs
+ *      in this state are either waiting to be processed by hardware, are in
+ *      process, or have been processed. The DMA engine controls BDs in this
+ *      state.
+ *   4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the
+ *      user. Once retrieved, the user can examine each BD for the outcome of
+ *      the DMA transfer. The user controls BDs in this state. After examining
+ *      the BDs the user calls XEmacPs_BdRingFree() which places the BDs back
+ *      into state 1.
+ *
+ * Each of the four BD accessor functions operate on a set of BDs. A set is
+ * defined as a segment of the BD ring consisting of one or more BDs. The user
+ * views the set as a pointer to the first BD along with the number of BDs for
+ * that set. The set can be navigated by using macros XEmacPs_BdNext(). The
+ * user must exercise extreme caution when changing BDs in a set as there is
+ * nothing to prevent doing a mBdNext past the end of the set and modifying a
+ * BD out of bounds.
+ *
+ * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as
+ * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in
+ * tandem. The same BD set retrieved with BdRingAlloc should be the same one
+ * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and
+ * BdRIngFree.
+ *
+ * <b>Alignment & Data Cache Restrictions</b>
+ *
+ * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte
+ * aligned. Please reference xemacps_bd.h for cache related macros.
+ *
+ * DMA Tx:
+ *
+ *   - If frame buffers exist in cached memory, then they must be flushed
+ *     prior to committing them to hardware.
+ *
+ * DMA Rx:
+ *
+ *   - If frame buffers exist in cached memory, then the cache must be
+ *     invalidated for the memory region containing the frame prior to data
+ *     access
+ *
+ * Both cache invalidate/flush are taken care of in driver code.
+ *
+ * <b>Buffer Copying</b>
+ *
+ * The driver is designed for a zero-copy buffer scheme. That is, the driver
+ * will not copy buffers. This avoids potential throughput bottlenecks within
+ * the driver. If byte copying is required, then the transfer will take longer
+ * to complete.
+ *
+ * <b>Checksum Offloading</b>
+ *
+ * The Embedded Processor Block Ethernet can be configured to perform IP, TCP
+ * and UDP checksum offloading in both receive and transmit directions.
+ *
+ * IP packets contain a 16-bit checksum field, which is the 16-bit 1s
+ * complement of the 1s complement sum of all 16-bit words in the header.
+ * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit
+ * 1s complement of the 1s complement sum of all 16-bit words in the header,
+ * the data and a conceptual pseudo header.
+ *
+ * To calculate these checksums in software requires each byte of the packet
+ * to be read. For TCP and UDP this can use a large amount of processing power.
+ * Offloading the checksum calculation to hardware can result in significant
+ * performance improvements.
+ *
+ * The transmit checksum offload is only available to use DMA in packet buffer
+ * mode. This is because the complete frame to be transmitted must be read
+ * into the packet buffer memory before the checksum can be calculated and
+ * written to the header at the beginning of the frame.
+ *
+ * For IP, TCP or UDP receive checksum offload to be useful, the operating
+ * system containing the protocol stack must be aware that this offload is
+ * available so that it can make use of the fact that the hardware has verified
+ * the checksum.
+ *
+ * When receive checksum offloading is enabled in the hardware, the IP header
+ * checksum is checked, where the packet meets the following criteria:
+ *
+ * 1. If present, the VLAN header must be four octets long and the CFI bit
+ *    must not be set.
+ * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP
+ *    encoding.
+ * 3. IP v4 packet.
+ * 4. IP header is of a valid length.
+ * 5. Good IP header checksum.
+ * 6. No IP fragmentation.
+ * 7. TCP or UDP packet.
+ *
+ * When an IP, TCP or UDP frame is received, the receive buffer descriptor
+ * gives an indication if the hardware was able to verify the checksums.
+ * There is also an indication if the frame had SNAP encapsulation. These
+ * indication bits will replace the type ID match indication bits when the
+ * receive checksum offload is enabled.
+ *
+ * If any of the checksums are verified incorrect by the hardware, the packet
+ * is discarded and the appropriate statistics counter incremented.
+ *
+ * <b>PHY Interfaces</b>
+ *
+ * RGMII 1.3 is the only interface supported.
+ *
+ * <b>Asserts</b>
+ *
+ * Asserts are used within all Xilinx drivers to enforce constraints on
+ * parameters. Asserts can be turned off on a system-wide basis by defining,
+ * at compile time, the NDEBUG identifier. By default, asserts are turned on
+ * and it is recommended that users leave asserts on during development. For
+ * deployment use -DNDEBUG compiler switch to remove assert code.
+ *
+ * @note
+ *
+ * Xilinx drivers are typically composed of two parts, one is the driver
+ * and the other is the adapter.  The driver is independent of OS and processor
+ * and is intended to be highly portable.  The adapter is OS-specific and
+ * facilitates communication between the driver and an OS.
+ * This driver is intended to be RTOS and processor independent. Any needs for
+ * dynamic memory management, threads or thread mutual exclusion, or cache
+ * control must be satisfied bythe layer above this driver.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ * 1.00a asa  11/21/11 The function XEmacPs_BdRingFromHwTx in file
+ *		       xemacps_bdring.c is modified. Earlier it was checking for
+ *		       "BdLimit"(passed argument) number of BDs for finding out
+ *		       which BDs are successfully processed. Now one more check
+ *		       is added. It looks for BDs till the current BD pointer
+ *		       reaches HwTail. By doing this processing time is saved.
+ * 1.00a asa  01/24/12 The function XEmacPs_BdRingFromHwTx in file
+ *		       xemacps_bdring.c is modified. Now start of packet is
+ *		       searched for returning the number of BDs processed.
+ * 1.02a asa  11/05/12 Added a new API for deleting an entry from the HASH
+ *		       registers. Added a new API to set the bust length.
+ *		       Added some new hash-defines.
+ * 1.03a asa  01/23/12 Fix for CR #692702 which updates error handling for
+ *		       Rx errors. Under heavy Rx traffic, there will be a large
+ *		       number of errors related to receive buffer not available.
+ *		       Because of a HW bug (SI #692601), under such heavy errors,
+ *		       the Rx data path can become unresponsive. To reduce the
+ *		       probabilities for hitting this HW bug, the SW writes to
+ *		       bit 18 to flush a packet from Rx DPRAM immediately. The
+ *		       changes for it are done in the function
+ *		       XEmacPs_IntrHandler.
+ * 1.05a asa  09/23/13 Cache operations on BDs are not required and hence
+ *		       removed. It is expected that all BDs are allocated in
+ *		       from uncached area.
+ * 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+ *				to 0x1fff. This fixes the CR#744902.
+ *			  Made changes in example file xemacps_example.h to fix compilation
+ *			  issues with iarcc compiler.
+ * 2.0   adk  10/12/13 Updated as per the New Tcl API's
+ * 2.1   adk  11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
+ * 2.1   bss  09/08/14 Modified driver tcl to fix CR#820349 to export phy
+ *		       address in xparameters.h when GMII to RGMII converter
+ *		       is present in hw.
+ * 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
+ *		       changes.
+ * 2.2   adk  29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
+ *                    1000BASE-X mode export proper values to the xparameters.h
+ *                    file. Changes are made in the driver tcl file.
+ * 3.0   adk  08/1/15  Don't include gem in peripheral test when gem is
+ *                    configured with PCS/PMA Core. Changes are made in the
+ *		       test app tcl(CR:827686).
+ * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0   hk   03/18/15 Added support for jumbo frames. Increase AHB burst.
+ *                     Disable extended mode. Perform all 64 bit changes under
+ *                     check for arch64.
+ *                     Remove "used bit set" from TX error interrupt masks.
+ * 3.1   hk   07/27/15 Do not call error handler with '0' error code when
+ *                     there is no error. CR# 869403
+ *            08/10/15 Update upper 32 bit tx and rx queue ptr registers.
+ * 3.2   hk   02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+ * 3.4   ms   01/23/17 Modified xil_printf statement in main function for all
+ *                     examples to ensure that "Successfully ran" and "Failed"
+ *                     strings are available in all examples. This is a fix
+ *                     for CR-965028.
+ *       ms   03/17/17 Modified text file in examples folder for doxygen
+ *                     generation.
+ * </pre>
+ *
+ ****************************************************************************/
+
+#ifndef XEMACPS_H		/* prevent circular inclusions */
+#define XEMACPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xemacps_hw.h"
+#include "xemacps_bd.h"
+#include "xemacps_bdring.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * Device information
+ */
+#define XEMACPS_DEVICE_NAME     "xemacps"
+#define XEMACPS_DEVICE_DESC     "Xilinx PS 10/100/1000 MAC"
+
+
+/** @name Configuration options
+ *
+ * Device configuration options. See the XEmacPs_SetOptions(),
+ * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to
+ * use options.
+ *
+ * The default state of the options are noted and are what the device and
+ * driver will be set to after calling XEmacPs_Reset() or
+ * XEmacPs_Initialize().
+ *
+ * @{
+ */
+
+#define XEMACPS_PROMISC_OPTION               0x00000001U
+/**< Accept all incoming packets.
+ *   This option defaults to disabled (cleared) */
+
+#define XEMACPS_FRAME1536_OPTION             0x00000002U
+/**< Frame larger than 1516 support for Tx & Rx.
+ *   This option defaults to disabled (cleared) */
+
+#define XEMACPS_VLAN_OPTION                  0x00000004U
+/**< VLAN Rx & Tx frame support.
+ *   This option defaults to disabled (cleared) */
+
+#define XEMACPS_FLOW_CONTROL_OPTION          0x00000010U
+/**< Enable recognition of flow control frames on Rx
+ *   This option defaults to enabled (set) */
+
+#define XEMACPS_FCS_STRIP_OPTION             0x00000020U
+/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
+ *   stripped.
+ *   This option defaults to enabled (set) */
+
+#define XEMACPS_FCS_INSERT_OPTION            0x00000040U
+/**< Generate FCS field and add PAD automatically for outgoing frames.
+ *   This option defaults to disabled (cleared) */
+
+#define XEMACPS_LENTYPE_ERR_OPTION           0x00000080U
+/**< Enable Length/Type error checking for incoming frames. When this option is
+ *   set, the MAC will filter frames that have a mismatched type/length field
+ *   and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these
+ *   types of frames are encountered. When this option is cleared, the MAC will
+ *   allow these types of frames to be received.
+ *
+ *   This option defaults to disabled (cleared) */
+
+#define XEMACPS_TRANSMITTER_ENABLE_OPTION    0x00000100U
+/**< Enable the transmitter.
+ *   This option defaults to enabled (set) */
+
+#define XEMACPS_RECEIVER_ENABLE_OPTION       0x00000200U
+/**< Enable the receiver
+ *   This option defaults to enabled (set) */
+
+#define XEMACPS_BROADCAST_OPTION             0x00000400U
+/**< Allow reception of the broadcast address
+ *   This option defaults to enabled (set) */
+
+#define XEMACPS_MULTICAST_OPTION             0x00000800U
+/**< Allows reception of multicast addresses programmed into hash
+ *   This option defaults to disabled (clear) */
+
+#define XEMACPS_RX_CHKSUM_ENABLE_OPTION      0x00001000U
+/**< Enable the RX checksum offload
+ *   This option defaults to enabled (set) */
+
+#define XEMACPS_TX_CHKSUM_ENABLE_OPTION      0x00002000U
+/**< Enable the TX checksum offload
+ *   This option defaults to enabled (set) */
+
+#define XEMACPS_JUMBO_ENABLE_OPTION	0x00004000U
+#define XEMACPS_SGMII_ENABLE_OPTION	0x00008000U
+
+#define XEMACPS_DEFAULT_OPTIONS                     \
+    ((u32)XEMACPS_FLOW_CONTROL_OPTION |                  \
+     (u32)XEMACPS_FCS_INSERT_OPTION |                    \
+     (u32)XEMACPS_FCS_STRIP_OPTION |                     \
+     (u32)XEMACPS_BROADCAST_OPTION |                     \
+     (u32)XEMACPS_LENTYPE_ERR_OPTION |                   \
+     (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION |            \
+     (u32)XEMACPS_RECEIVER_ENABLE_OPTION |               \
+     (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION |              \
+     (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
+
+/**< Default options set when device is initialized or reset */
+/*@}*/
+
+/** @name Callback identifiers
+ *
+ * These constants are used as parameters to XEmacPs_SetHandler()
+ * @{
+ */
+#define XEMACPS_HANDLER_DMASEND 1U
+#define XEMACPS_HANDLER_DMARECV 2U
+#define XEMACPS_HANDLER_ERROR   3U
+/*@}*/
+
+/* Constants to determine the configuration of the hardware device. They are
+ * used to allow the driver to verify it can operate with the hardware.
+ */
+#define XEMACPS_MDIO_DIV_DFT    MDC_DIV_32 /**< Default MDIO clock divisor */
+
+/* The next few constants help upper layers determine the size of memory
+ * pools used for Ethernet buffers and descriptor lists.
+ */
+#define XEMACPS_MAC_ADDR_SIZE   6U	/* size of Ethernet header */
+
+#define XEMACPS_MTU             1500U	/* max MTU size of Ethernet frame */
+#define XEMACPS_MTU_JUMBO       10240U	/* max MTU size of jumbo frame */
+#define XEMACPS_HDR_SIZE        14U	/* size of Ethernet header */
+#define XEMACPS_HDR_VLAN_SIZE   18U	/* size of Ethernet header with VLAN */
+#define XEMACPS_TRL_SIZE        4U	/* size of Ethernet trailer (FCS) */
+#define XEMACPS_MAX_FRAME_SIZE       (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
+        XEMACPS_TRL_SIZE)
+#define XEMACPS_MAX_VLAN_FRAME_SIZE  (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
+        XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
+#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO  (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \
+        XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
+
+/* DMACR Bust length hash defines */
+
+#define XEMACPS_SINGLE_BURST	0x00000001
+#define XEMACPS_4BYTE_BURST		0x00000004
+#define XEMACPS_8BYTE_BURST		0x00000008
+#define XEMACPS_16BYTE_BURST	0x00000010
+
+
+/**************************** Type Definitions ******************************/
+/** @name Typedefs for callback functions
+ *
+ * These callbacks are invoked in interrupt context.
+ * @{
+ */
+/**
+ * Callback invoked when frame(s) have been sent or received in interrupt
+ * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler().
+ *
+ * @param CallBackRef is user data assigned when the callback was set.
+ *
+ * @note
+ * See xemacps_hw.h for bitmasks definitions and the device hardware spec for
+ * further information on their meaning.
+ *
+ */
+typedef void (*XEmacPs_Handler) (void *CallBackRef);
+
+/**
+ * Callback when an asynchronous error occurs. To set this callback, invoke
+ * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType
+ * paramter.
+ *
+ * @param CallBackRef is user data assigned when the callback was set.
+ * @param Direction defines either receive or transmit error(s) has occurred.
+ * @param ErrorWord definition varies with Direction
+ *
+ */
+typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
+				     u32 ErrorWord);
+
+/*@}*/
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+	u16 DeviceId;	/**< Unique ID  of device */
+	UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
+} XEmacPs_Config;
+
+
+/**
+ * The XEmacPs driver instance data. The user is required to allocate a
+ * structure of this type for every XEmacPs device in the system. A pointer
+ * to a structure of this type is then passed to the driver API functions.
+ */
+typedef struct XEmacPs_Instance {
+	XEmacPs_Config Config;	/* Hardware configuration */
+	u32 IsStarted;		/* Device is currently started */
+	u32 IsReady;		/* Device is initialized and ready */
+	u32 Options;		/* Current options word */
+
+	XEmacPs_BdRing TxBdRing;	/* Transmit BD ring */
+	XEmacPs_BdRing RxBdRing;	/* Receive BD ring */
+
+	XEmacPs_Handler SendHandler;
+	XEmacPs_Handler RecvHandler;
+	void *SendRef;
+	void *RecvRef;
+
+	XEmacPs_ErrHandler ErrorHandler;
+	void *ErrorRef;
+	u32 Version;
+	u32 RxBufMask;
+	u32 MaxMtuSize;
+	u32 MaxFrameSize;
+	u32 MaxVlanFrameSize;
+
+} XEmacPs;
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Retrieve the Tx ring object. This object can be used in the various Ring
+* API functions.
+*
+* @param  InstancePtr is the DMA channel to operate on.
+*
+* @return TxBdRing attribute
+*
+* @note
+* C-style signature:
+*    XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing)
+
+/****************************************************************************/
+/**
+* Retrieve the Rx ring object. This object can be used in the various Ring
+* API functions.
+*
+* @param  InstancePtr is the DMA channel to operate on.
+*
+* @return RxBdRing attribute
+*
+* @note
+* C-style signature:
+*    XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing)
+
+/****************************************************************************/
+/**
+*
+* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
+* each bit set to 1 in <i>Mask</i>, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to enable. The mask can
+*        be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+*     void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntEnable(InstancePtr, Mask)                            \
+	XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
+		XEMACPS_IER_OFFSET,                                     \
+		((Mask) & XEMACPS_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
+* each bit set to 1 in <i>Mask</i>, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to disable. The mask can
+*        be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+*     void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntDisable(InstancePtr, Mask)                           \
+	XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
+		XEMACPS_IDR_OFFSET,                                     \
+		((Mask) & XEMACPS_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
+* each bit set to 1 in <i>Mask</i>, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to enable. The mask can
+*        be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+*     void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntQ1Enable(InstancePtr, Mask)                            \
+	XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
+		XEMACPS_INTQ1_IER_OFFSET,                                \
+		((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
+* each bit set to 1 in <i>Mask</i>, will be enabled.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask contains a bit mask of interrupts to disable. The mask can
+*        be formed using a set of bitwise or'd values.
+*
+* @note
+* The state of the transmitter and receiver are not modified by this function.
+* C-style signature
+*     void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XEmacPs_IntQ1Disable(InstancePtr, Mask)                           \
+	XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,             \
+		XEMACPS_INTQ1_IDR_OFFSET,                               \
+		((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* This macro triggers trasmit circuit to send data currently in TX buffer(s).
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* @note
+*
+* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_Transmit(InstancePtr)                              \
+        XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress,          \
+        XEMACPS_NWCTRL_OFFSET,                                     \
+        (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress,          \
+        XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
+
+/****************************************************************************/
+/**
+*
+* This macro determines if the device is configured with checksum offloading
+* on the receive channel
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* Boolean TRUE if the device is configured with checksum offloading, or
+* FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_IsRxCsum(InstancePtr)                                     \
+        ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress,             \
+          XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U     \
+          ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* This macro determines if the device is configured with checksum offloading
+* on the transmit channel
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+*
+* @return
+*
+* Boolean TRUE if the device is configured with checksum offloading, or
+* FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr)
+*
+*****************************************************************************/
+#define XEmacPs_IsTxCsum(InstancePtr)                                     \
+        ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress,              \
+          XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U       \
+          ? TRUE : FALSE)
+
+/************************** Function Prototypes *****************************/
+
+/*
+ * Initialization functions in xemacps.c
+ */
+LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
+			   UINTPTR EffectiveAddress);
+void XEmacPs_Start(XEmacPs *InstancePtr);
+void XEmacPs_Stop(XEmacPs *InstancePtr);
+void XEmacPs_Reset(XEmacPs *InstancePtr);
+void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
+			 u16 Direction);
+
+/*
+ * Lookup configuration in xemacps_sinit.c
+ */
+XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Interrupt-related functions in xemacps_intr.c
+ * DMA only and FIFO is not supported. This DMA does not support coalescing.
+ */
+LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
+			void *FuncPointer, void *CallBackRef);
+void XEmacPs_IntrHandler(void *XEmacPsPtr);
+
+/*
+ * MAC configuration/control functions in XEmacPs_control.c
+ */
+LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options);
+LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options);
+u32 XEmacPs_GetOptions(XEmacPs *InstancePtr);
+
+LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
+LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr);
+void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
+
+LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr);
+void XEmacPs_ClearHash(XEmacPs *InstancePtr);
+void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
+
+void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
+				XEmacPs_MdcDiv Divisor);
+void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
+u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
+LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
+		     u32 RegisterNum, u16 *PhyDataPtr);
+LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
+		      u32 RegisterNum, u16 PhyData);
+LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
+
+LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr);
+void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_bd.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_bd.h
new file mode 100644
index 0000000000000000000000000000000000000000..52c5f7e7e2b6f845f7010acb26ccdcd127bacc28
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_bd.h
@@ -0,0 +1,804 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xemacps_bd.h
+* @addtogroup emacps_v3_1
+* @{
+ *
+ * This header provides operations to manage buffer descriptors in support
+ * of scatter-gather DMA.
+ *
+ * The API exported by this header defines abstracted macros that allow the
+ * user to read/write specific BD fields.
+ *
+ * <b>Buffer Descriptors</b>
+ *
+ * A buffer descriptor (BD) defines a DMA transaction. The macros defined by
+ * this header file allow access to most fields within a BD to tailor a DMA
+ * transaction according to user and hardware requirements.  See the hardware
+ * IP DMA spec for more information on BD fields and how they affect transfers.
+ *
+ * The XEmacPs_Bd structure defines a BD. The organization of this structure
+ * is driven mainly by the hardware for use in scatter-gather DMA transfers.
+ *
+ * <b>Performance</b>
+ *
+ * Limiting I/O to BDs can improve overall performance of the DMA channel.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ * 2.1   srt  07/15/14 Add support for Zynq Ultrascale MP GEM specification
+ *                     and 64-bit changes.
+ * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0   hk   02/20/15 Added support for jumbo frames.
+ *                     Disable extended mode. Perform all 64 bit changes under
+ *                     check for arch64.
+ * 3.2   hk   11/18/15 Change BD typedef and number of words.
+ *
+ * </pre>
+ *
+ * ***************************************************************************
+ */
+
+#ifndef XEMACPS_BD_H		/* prevent circular inclusions */
+#define XEMACPS_BD_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include <string.h>
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+#ifdef __aarch64__
+/* Minimum BD alignment */
+#define XEMACPS_DMABD_MINIMUM_ALIGNMENT  64U
+#define XEMACPS_BD_NUM_WORDS 4U
+#else
+/* Minimum BD alignment */
+#define XEMACPS_DMABD_MINIMUM_ALIGNMENT  4U
+#define XEMACPS_BD_NUM_WORDS 2U
+#endif
+
+/**
+ * The XEmacPs_Bd is the type for buffer descriptors (BDs).
+ */
+typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ * Zero out BD fields
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @return Nothing
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdClear(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClear(BdPtr)                                  \
+    memset((BdPtr), 0, sizeof(XEmacPs_Bd))
+
+/****************************************************************************/
+/**
+*
+* Read the given Buffer Descriptor word.
+*
+* @param    BaseAddress is the base address of the BD to read
+* @param    Offset is the word offset to be read
+*
+* @return   The 32-bit value of the field
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset)
+*
+*****************************************************************************/
+#define XEmacPs_BdRead(BaseAddress, Offset)             \
+	(*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Buffer Descriptor word.
+*
+* @param    BaseAddress is the base address of the BD to write
+* @param    Offset is the word offset to be written
+* @param    Data is the 32-bit value to write to the field
+*
+* @return   None.
+*
+* @note
+* C-style signature:
+*    void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data)
+*
+*****************************************************************************/
+#define XEmacPs_BdWrite(BaseAddress, Offset, Data)              \
+    (*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data))
+
+/*****************************************************************************/
+/**
+ * Set the BD's Address field (word 0).
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ * @param  Addr  is the value to write to BD's status field.
+ *
+ * @note :
+ *
+ * C-style signature:
+ *    void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
+ *
+ *****************************************************************************/
+#ifdef __aarch64__
+#define XEmacPs_BdSetAddressTx(BdPtr, Addr)                        \
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET,		\
+			(u32)((Addr) & ULONG64_LO_MASK));		\
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET,		\
+	(u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
+#else
+#define XEmacPs_BdSetAddressTx(BdPtr, Addr)                        \
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set the BD's Address field (word 0).
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ * @param  Addr  is the value to write to BD's status field.
+ *
+ * @note : Due to some bits are mixed within recevie BD's address field,
+ *         read-modify-write is performed.
+ *
+ * C-style signature:
+ *    void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
+ *
+ *****************************************************************************/
+#ifdef __aarch64__
+#define XEmacPs_BdSetAddressRx(BdPtr, Addr)                        \
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET,              \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) &           \
+	~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK))));  \
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, 	\
+	(u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
+#else
+#define XEmacPs_BdSetAddressRx(BdPtr, Addr)                        \
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET,              \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) &           \
+    ~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr)))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set the BD's Status field (word 1).
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ * @param  Data  is the value to write to BD's status field.
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetStatus(BdPtr, Data)                           \
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,              \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data))
+
+
+/*****************************************************************************/
+/**
+ * Retrieve the BD's Packet DMA transfer status word (word 1).
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @return Status word
+ *
+ * @note
+ * C-style signature:
+ *    u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr)
+ *
+ * Due to the BD bit layout differences in transmit and receive. User's
+ * caution is required.
+ *****************************************************************************/
+#define XEmacPs_BdGetStatus(BdPtr)                                 \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET)
+
+
+/*****************************************************************************/
+/**
+ * Get the address (bits 0..31) of the BD's buffer address (word 0)
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#ifdef __aarch64__
+#define XEmacPs_BdGetBufAddr(BdPtr)                               \
+    (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) |		  \
+	(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
+#else
+#define XEmacPs_BdGetBufAddr(BdPtr)                               \
+    (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))
+#endif
+
+/*****************************************************************************/
+/**
+ * Set transfer length in bytes for the given BD. The length must be set each
+ * time a BD is submitted to hardware.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ * @param  LenBytes is the number of bytes to transfer.
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetLength(BdPtr, LenBytes)                       \
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,              \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
+
+
+
+/*****************************************************************************/
+/**
+ * Set transfer length in bytes for the given BD. The length must be set each
+ * time a BD is submitted to hardware.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ * @param  LenBytes is the number of bytes to transfer.
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetLength(BdPtr, LenBytes)                       \
+    XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,              \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
+
+
+/*****************************************************************************/
+/**
+ * Retrieve the BD length field.
+ *
+ * For Tx channels, the returned value is the same as that written with
+ * XEmacPs_BdSetLength().
+ *
+ * For Rx channels, the returned value is the size of the received packet.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @return Length field processed by hardware or set by
+ *         XEmacPs_BdSetLength().
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr)
+ *    XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK.
+ *
+ *****************************************************************************/
+#define XEmacPs_BdGetLength(BdPtr)                                 \
+    (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &            \
+    XEMACPS_RXBUF_LEN_MASK)
+
+/*****************************************************************************/
+/**
+ * Retrieve the RX frame size.
+ *
+ * The returned value is the size of the received packet.
+ * This API supports jumbo frame sizes if enabled.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @return Length field processed by hardware or set by
+ *         XEmacPs_BdSetLength().
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr)
+ *    RxBufMask is dependent on whether jumbo is enabled or not.
+ *
+ *****************************************************************************/
+#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr)                   \
+    (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &            \
+    (InstancePtr)->RxBufMask)
+
+/*****************************************************************************/
+/**
+ * Test whether the given BD has been marked as the last BD of a packet.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsLast(BdPtr)                                    \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Tell the DMA engine that the given transmit BD marks the end of the current
+ * packet to be processed.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetLast(BdPtr)                                   \
+    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) |             \
+    XEMACPS_TXBUF_LAST_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Tell the DMA engine that the current packet does not end with the given
+ * BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearLast(BdPtr)                                 \
+    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &             \
+    ~XEMACPS_TXBUF_LAST_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Set this bit to mark the last descriptor in the receive buffer descriptor
+ * list.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+/*#define XEmacPs_BdSetRxWrap(BdPtr)                                 \
+    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET,             \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) |             \
+    XEMACPS_RXBUF_WRAP_MASK))
+*/
+
+/*****************************************************************************/
+/**
+ * Determine the wrap bit of the receive BD which indicates end of the
+ * BD list.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxWrap(BdPtr)                                  \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) &           \
+    XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Sets this bit to mark the last descriptor in the transmit buffer
+ * descriptor list.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+/*#define XEmacPs_BdSetTxWrap(BdPtr)                                 \
+    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) |             \
+    XEMACPS_TXBUF_WRAP_MASK))
+*/
+
+/*****************************************************************************/
+/**
+ * Determine the wrap bit of the transmit BD which indicates end of the
+ * BD list.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxWrap(BdPtr)                                  \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/*
+ * Must clear this bit to enable the MAC to write data to the receive
+ * buffer. Hardware sets this bit once it has successfully written a frame to
+ * memory. Once set, software has to clear the bit before the buffer can be
+ * used again. This macro clear the new bit of the receive BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearRxNew(BdPtr)                                \
+    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET,             \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) &             \
+    ~XEMACPS_RXBUF_NEW_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the new bit of the receive BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxNew(BdPtr)                                   \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) &           \
+    XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Software sets this bit to disable the buffer to be read by the hardware.
+ * Hardware sets this bit for the first buffer of a frame once it has been
+ * successfully transmitted. This macro sets this bit of transmit BD to avoid
+ * confusion.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetTxUsed(BdPtr)                                 \
+    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) |             \
+    XEMACPS_TXBUF_USED_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Software clears this bit to enable the buffer to be read by the hardware.
+ * Hardware sets this bit for the first buffer of a frame once it has been
+ * successfully transmitted. This macro clears this bit of transmit BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearTxUsed(BdPtr)                               \
+    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &             \
+    ~XEMACPS_TXBUF_USED_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the used bit of the transmit BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxUsed(BdPtr)                                  \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to too many retries.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxRetry(BdPtr)                                 \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to data can not be
+ * feteched in time or buffers are exhausted.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxUrun(BdPtr)                                  \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if a frame fails to be transmitted due to buffer is exhausted
+ * mid-frame.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsTxExh(BdPtr)                                   \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Sets this bit, no CRC will be appended to the current frame. This control
+ * bit must be set for the first buffer in a frame and will be ignored for
+ * the subsequent buffers of a frame.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * This bit must be clear when using the transmit checksum generation offload,
+ * otherwise checksum generation and substitution will not occur.
+ *
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdSetTxNoCRC(BdPtr)                                \
+    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) |             \
+    XEMACPS_TXBUF_NOCRC_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Clear this bit, CRC will be appended to the current frame. This control
+ * bit must be set for the first buffer in a frame and will be ignored for
+ * the subsequent buffers of a frame.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * This bit must be clear when using the transmit checksum generation offload,
+ * otherwise checksum generation and substitution will not occur.
+ *
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdClearTxNoCRC(BdPtr)                              \
+    (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET,             \
+    XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &             \
+    ~XEMACPS_TXBUF_NOCRC_MASK))
+
+
+/*****************************************************************************/
+/**
+ * Determine the broadcast bit of the receive BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxBcast(BdPtr)                                 \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the multicast hash bit of the receive BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxMultiHash(BdPtr)                             \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the unicast hash bit of the receive BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxUniHash(BdPtr)                               \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame is a VLAN Tagged frame.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxVlan(BdPtr)                                  \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame has Type ID of 8100h and null VLAN
+ * identifier(Priority tag).
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxPri(BdPtr)                                   \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine if the received frame's Concatenation Format Indicator (CFI) of
+ * the frames VLANTCI field was set.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxCFI(BdPtr)                                   \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the End Of Frame (EOF) bit of the receive BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxEOF(BdPtr)                                   \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ * Determine the Start Of Frame (SOF) bit of the receive BD.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+#define XEmacPs_BdIsRxSOF(BdPtr)                                   \
+    ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) &           \
+    XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE)
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_bdring.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_bdring.c
new file mode 100644
index 0000000000000000000000000000000000000000..7c539f44829e9a62f319e2782b09eadd98fdc480
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_bdring.c
@@ -0,0 +1,1075 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_bdring.c
+* @addtogroup emacps_v3_1
+* @{
+*
+* This file implements buffer descriptor ring related functions.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 1.00a asa  11/21/11 The function XEmacPs_BdRingFromHwTx is modified.
+*		      Earlier it used to search in "BdLimit" number of BDs to
+*		      know which BDs are processed. Now one more check is
+*		      added. It looks for BDs till the current BD pointer
+*		      reaches HwTail. By doing this processing time is saved.
+* 1.00a asa  01/24/12 The function XEmacPs_BdRingFromHwTx in file
+*		      xemacps_bdring.c is modified. Now start of packet is
+*		      searched for returning the number of BDs processed.
+* 1.05a asa  09/23/13 Cache operations on BDs are not required and hence
+*		      removed. It is expected that all BDs are allocated in
+*		      from uncached area. Fix for CR #663885.
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp architecture.
+* 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* </pre>
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xil_cache.h"
+#include "xemacps_hw.h"
+#include "xemacps_bd.h"
+#include "xemacps_bdring.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************
+ * Compute the virtual address of a descriptor from its physical address
+ *
+ * @param BdPtr is the physical address of the BD
+ *
+ * @returns Virtual address of BdPtr
+ *
+ * @note Assume BdPtr is always a valid BD in the ring
+ ****************************************************************************/
+#define XEMACPS_PHYS_TO_VIRT(BdPtr) \
+    ((UINTPTR)(BdPtr) + (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr))
+
+/****************************************************************************
+ * Compute the physical address of a descriptor from its virtual address
+ *
+ * @param BdPtr is the physical address of the BD
+ *
+ * @returns Physical address of BdPtr
+ *
+ * @note Assume BdPtr is always a valid BD in the ring
+ ****************************************************************************/
+#define XEMACPS_VIRT_TO_PHYS(BdPtr) \
+    ((UINTPTR)(BdPtr) - (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr))
+
+/****************************************************************************
+ * Move the BdPtr argument ahead an arbitrary number of BDs wrapping around
+ * to the beginning of the ring if needed.
+ *
+ * We know if a wrapaound should occur if the new BdPtr is greater than
+ * the high address in the ring OR if the new BdPtr crosses over the
+ * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not
+ * allow a BD space to span this boundary.
+ *
+ * @param RingPtr is the ring BdPtr appears in
+ * @param BdPtr on input is the starting BD position and on output is the
+ *        final BD position
+ * @param NumBd is the number of BD spaces to increment
+ *
+ ****************************************************************************/
+#define XEMACPS_RING_SEEKAHEAD(RingPtr, BdPtr, NumBd)                  \
+    {                                                                   \
+        UINTPTR Addr = (UINTPTR)(void *)(BdPtr);                        \
+                                                                        \
+        Addr += ((RingPtr)->Separation * (NumBd));                        \
+        if ((Addr > (RingPtr)->HighBdAddr) || ((UINTPTR)(void *)(BdPtr) > Addr))  \
+        {                                                               \
+            Addr -= (RingPtr)->Length;                                  \
+        }                                                               \
+                                                                        \
+        (BdPtr) = (XEmacPs_Bd*)(void *)Addr;                                     \
+    }
+
+/****************************************************************************
+ * Move the BdPtr argument backwards an arbitrary number of BDs wrapping
+ * around to the end of the ring if needed.
+ *
+ * We know if a wrapaound should occur if the new BdPtr is less than
+ * the base address in the ring OR if the new BdPtr crosses over the
+ * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not
+ * allow a BD space to span this boundary.
+ *
+ * @param RingPtr is the ring BdPtr appears in
+ * @param BdPtr on input is the starting BD position and on output is the
+ *        final BD position
+ * @param NumBd is the number of BD spaces to increment
+ *
+ ****************************************************************************/
+#define XEMACPS_RING_SEEKBACK(RingPtr, BdPtr, NumBd)                   \
+    {                                                                   \
+        UINTPTR Addr = (UINTPTR)(void *)(BdPtr);                                  \
+                                                                        \
+        Addr -= ((RingPtr)->Separation * (NumBd));                        \
+        if ((Addr < (RingPtr)->BaseBdAddr) || ((UINTPTR)(void*)(BdPtr) < Addr))  \
+        {                                                               \
+            Addr += (RingPtr)->Length;                                  \
+        }                                                               \
+                                                                        \
+        (BdPtr) = (XEmacPs_Bd*)(void*)Addr;                                     \
+    }
+
+
+/************************** Function Prototypes ******************************/
+
+static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr);
+static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr);
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+ * Using a memory segment allocated by the caller, create and setup the BD list
+ * for the given DMA channel.
+ *
+ * @param RingPtr is the instance to be worked on.
+ * @param PhysAddr is the physical base address of user memory region.
+ * @param VirtAddr is the virtual base address of the user memory region. If
+ *        address translation is not being utilized, then VirtAddr should be
+ *        equivalent to PhysAddr.
+ * @param Alignment governs the byte alignment of individual BDs. This function
+ *        will enforce a minimum alignment of 4 bytes with no maximum as long
+ *        as it is specified as a power of 2.
+ * @param BdCount is the number of BDs to setup in the user memory region. It
+ *        is assumed the region is large enough to contain the BDs.
+ *
+ * @return
+ *
+ * - XST_SUCCESS if initialization was successful
+ * - XST_NO_FEATURE if the provided instance is a non DMA type
+ *   channel.
+ * - XST_INVALID_PARAM under any of the following conditions:
+ *   1) PhysAddr and/or VirtAddr are not aligned to the given Alignment
+ *      parameter.
+ *   2) Alignment parameter does not meet minimum requirements or is not a
+ *      power of 2 value.
+ *   3) BdCount is 0.
+ * - XST_DMA_SG_LIST_ERROR if the memory segment containing the list spans
+ *   over address 0x00000000 in virtual address space.
+ *
+ * @note
+ * Make sure to pass in the right alignment value.
+ *****************************************************************************/
+LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
+			  UINTPTR VirtAddr, u32 Alignment, u32 BdCount)
+{
+	u32 i;
+	UINTPTR BdVirtAddr;
+	UINTPTR BdPhyAddr;
+	UINTPTR VirtAddrLoc = VirtAddr;
+
+	/* In case there is a failure prior to creating list, make sure the
+	 * following attributes are 0 to prevent calls to other functions
+	 * from doing anything.
+	 */
+	RingPtr->AllCnt = 0U;
+	RingPtr->FreeCnt = 0U;
+	RingPtr->HwCnt = 0U;
+	RingPtr->PreCnt = 0U;
+	RingPtr->PostCnt = 0U;
+
+	/* Make sure Alignment parameter meets minimum requirements */
+	if (Alignment < (u32)XEMACPS_DMABD_MINIMUM_ALIGNMENT) {
+		return (LONG)(XST_INVALID_PARAM);
+	}
+
+	/* Make sure Alignment is a power of 2 */
+	if (((Alignment - 0x00000001U) & Alignment)!=0x00000000U) {
+		return (LONG)(XST_INVALID_PARAM);
+	}
+
+	/* Make sure PhysAddr and VirtAddr are on same Alignment */
+	if (((PhysAddr % Alignment)!=(u32)0) || ((VirtAddrLoc % Alignment)!=(u32)0)) {
+		return (LONG)(XST_INVALID_PARAM);
+	}
+
+	/* Is BdCount reasonable? */
+	if (BdCount == 0x00000000U) {
+		return (LONG)(XST_INVALID_PARAM);
+	}
+
+	/* Figure out how many bytes will be between the start of adjacent BDs */
+	RingPtr->Separation = ((u32)sizeof(XEmacPs_Bd));
+
+	/* Must make sure the ring doesn't span address 0x00000000. If it does,
+	 * then the next/prev BD traversal macros will fail.
+	 */
+	if (VirtAddrLoc > ((VirtAddrLoc + (RingPtr->Separation * BdCount)) - (u32)1)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	/* Initial ring setup:
+	 *  - Clear the entire space
+	 *  - Setup each BD's BDA field with the physical address of the next BD
+	 */
+	(void)memset((void *) VirtAddrLoc, 0, (RingPtr->Separation * BdCount));
+
+	BdVirtAddr = VirtAddrLoc;
+	BdPhyAddr = PhysAddr + RingPtr->Separation;
+	for (i = 1U; i < BdCount; i++) {
+		BdVirtAddr += RingPtr->Separation;
+		BdPhyAddr += RingPtr->Separation;
+	}
+
+	/* Setup and initialize pointers and counters */
+	RingPtr->RunState = (u32)(XST_DMA_SG_IS_STOPPED);
+	RingPtr->BaseBdAddr = VirtAddrLoc;
+	RingPtr->PhysBaseAddr = PhysAddr;
+	RingPtr->HighBdAddr = BdVirtAddr;
+	RingPtr->Length =
+		((RingPtr->HighBdAddr - RingPtr->BaseBdAddr) + RingPtr->Separation);
+	RingPtr->AllCnt = (u32)BdCount;
+	RingPtr->FreeCnt = (u32)BdCount;
+	RingPtr->FreeHead = (XEmacPs_Bd *)(void *)VirtAddrLoc;
+	RingPtr->PreHead = (XEmacPs_Bd *)VirtAddrLoc;
+	RingPtr->HwHead = (XEmacPs_Bd *)VirtAddrLoc;
+	RingPtr->HwTail = (XEmacPs_Bd *)VirtAddrLoc;
+	RingPtr->PostHead = (XEmacPs_Bd *)VirtAddrLoc;
+	RingPtr->BdaRestart = (XEmacPs_Bd *)(void *)PhysAddr;
+
+	return (LONG)(XST_SUCCESS);
+}
+
+
+/*****************************************************************************/
+/**
+ * Clone the given BD into every BD in the list.
+ * every field of the source BD is replicated in every BD of the list.
+ *
+ * This function can be called only when all BDs are in the free group such as
+ * they are immediately after initialization with XEmacPs_BdRingCreate().
+ * This prevents modification of BDs while they are in use by hardware or the
+ * user.
+ *
+ * @param RingPtr is the pointer of BD ring instance to be worked on.
+ * @param SrcBdPtr is the source BD template to be cloned into the list. This
+ *        BD will be modified.
+ * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates
+ *        which direction.
+ *
+ * @return
+ *   - XST_SUCCESS if the list was modified.
+ *   - XST_DMA_SG_NO_LIST if a list has not been created.
+ *   - XST_DMA_SG_LIST_ERROR if some of the BDs in this channel are under
+ *     hardware or user control.
+ *   - XST_DEVICE_IS_STARTED if the DMA channel has not been stopped.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
+			 u8 Direction)
+{
+	u32 i;
+	UINTPTR CurBd;
+
+	/* Can't do this function if there isn't a ring */
+	if (RingPtr->AllCnt == 0x00000000U) {
+		return (LONG)(XST_DMA_SG_NO_LIST);
+	}
+
+	/* Can't do this function with the channel running */
+	if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
+		return (LONG)(XST_DEVICE_IS_STARTED);
+	}
+
+	/* Can't do this function with some of the BDs in use */
+	if (RingPtr->FreeCnt != RingPtr->AllCnt) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
+		return (LONG)(XST_INVALID_PARAM);
+	}
+
+	/* Starting from the top of the ring, save BD.Next, overwrite the entire
+	 * BD with the template, then restore BD.Next
+	 */
+	CurBd = RingPtr->BaseBdAddr;
+	for (i = 0U; i < RingPtr->AllCnt; i++) {
+		memcpy((void *)CurBd, SrcBdPtr, sizeof(XEmacPs_Bd));
+	CurBd += RingPtr->Separation;
+	}
+
+	CurBd -= RingPtr->Separation;
+
+	if (Direction == XEMACPS_RECV) {
+		XEmacPs_BdSetRxWrap(CurBd);
+	}
+	else {
+		XEmacPs_BdSetTxWrap(CurBd);
+	}
+
+	return (LONG)(XST_SUCCESS);
+}
+
+
+/*****************************************************************************/
+/**
+ * Reserve locations in the BD list. The set of returned BDs may be modified
+ * in preparation for future DMA transaction(s). Once the BDs are ready to be
+ * submitted to hardware, the user must call XEmacPs_BdRingToHw() in the same
+ * order which they were allocated here. Example:
+ *
+ * <pre>
+ *        NumBd = 2,
+ *        Status = XEmacPs_BdRingAlloc(MyRingPtr, NumBd, &MyBdSet),
+ *
+ *        if (Status != XST_SUCCESS)
+ *        {
+ *            *Not enough BDs available for the request*
+ *        }
+ *
+ *        CurBd = MyBdSet,
+ *        for (i=0; i<NumBd; i++)
+ *        {
+ *            * Prepare CurBd *.....
+ *
+ *            * Onto next BD *
+ *            CurBd = XEmacPs_BdRingNext(MyRingPtr, CurBd),
+ *        }
+ *
+ *        * Give list to hardware *
+ *        Status = XEmacPs_BdRingToHw(MyRingPtr, NumBd, MyBdSet),
+ * </pre>
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be allocated and given to hardware in the correct sequence:
+ * <pre>
+ *        * Legal *
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
+ *
+ *        * Legal *
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd2, MySet2),
+ *
+ *        * Not legal *
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd2, MySet2),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
+ * </pre>
+ *
+ * Use the API defined in xemacps_bd.h to modify individual BDs. Traversal
+ * of the BD set can be done using XEmacPs_BdRingNext() and
+ * XEmacPs_BdRingPrev().
+ *
+ * @param RingPtr is a pointer to the BD ring instance to be worked on.
+ * @param NumBd is the number of BDs to allocate
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ *        for modification.
+ *
+ * @return
+ *   - XST_SUCCESS if the requested number of BDs was returned in the BdSetPtr
+ *     parameter.
+ *   - XST_FAILURE if there were not enough free BDs to satisfy the request.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ * @note Do not modify more BDs than the number requested with the NumBd
+ *       parameter. Doing so will lead to data corruption and system
+ *       instability.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			 XEmacPs_Bd ** BdSetPtr)
+{
+	LONG Status;
+	/* Enough free BDs available for the request? */
+	if (RingPtr->FreeCnt < NumBd) {
+		Status = (LONG)(XST_FAILURE);
+	} else {
+	/* Set the return argument and move FreeHead forward */
+	*BdSetPtr = RingPtr->FreeHead;
+	XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->FreeHead, NumBd);
+	RingPtr->FreeCnt -= NumBd;
+	RingPtr->PreCnt += NumBd;
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * Fully or partially undo an XEmacPs_BdRingAlloc() operation. Use this
+ * function if all the BDs allocated by XEmacPs_BdRingAlloc() could not be
+ * transferred to hardware with XEmacPs_BdRingToHw().
+ *
+ * This function helps out in situations when an unrelated error occurs after
+ * BDs have been allocated but before they have been given to hardware.
+ * An example of this type of error would be an OS running out of resources.
+ *
+ * This function is not the same as XEmacPs_BdRingFree(). The Free function
+ * returns BDs to the free list after they have been processed by hardware,
+ * while UnAlloc returns them before being processed by hardware.
+ *
+ * There are two scenarios where this function can be used. Full UnAlloc or
+ * Partial UnAlloc. A Full UnAlloc means all the BDs Alloc'd will be returned:
+ *
+ * <pre>
+ *    Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr),
+ *        ...
+ *    if (Error)
+ *    {
+ *        Status = XEmacPs_BdRingUnAlloc(MyRingPtr, 10, &BdPtr),
+ *    }
+ * </pre>
+ *
+ * A partial UnAlloc means some of the BDs Alloc'd will be returned:
+ *
+ * <pre>
+ *    Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr),
+ *    BdsLeft = 10,
+ *    CurBdPtr = BdPtr,
+ *
+ *    while (BdsLeft)
+ *    {
+ *       if (Error)
+ *       {
+ *          Status = XEmacPs_BdRingUnAlloc(MyRingPtr, BdsLeft, CurBdPtr),
+ *       }
+ *
+ *       CurBdPtr = XEmacPs_BdRingNext(MyRingPtr, CurBdPtr),
+ *       BdsLeft--,
+ *    }
+ * </pre>
+ *
+ * A partial UnAlloc must include the last BD in the list that was Alloc'd.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs to allocate
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ *        for modification.
+ *
+ * @return
+ *   - XST_SUCCESS if the BDs were unallocated.
+ *   - XST_FAILURE if NumBd parameter was greater that the number of BDs in
+ *     the preprocessing state.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			   XEmacPs_Bd * BdSetPtr)
+{
+	LONG Status;
+	(void) BdSetPtr;
+	Xil_AssertNonvoid(RingPtr != NULL);
+	Xil_AssertNonvoid(BdSetPtr != NULL);
+
+	/* Enough BDs in the free state for the request? */
+	if (RingPtr->PreCnt < NumBd) {
+		Status = (LONG)(XST_FAILURE);
+	} else {
+	/* Set the return argument and move FreeHead backward */
+		XEMACPS_RING_SEEKBACK(RingPtr, (RingPtr->FreeHead), NumBd);
+	RingPtr->FreeCnt += NumBd;
+	RingPtr->PreCnt -= NumBd;
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Enqueue a set of BDs to hardware that were previously allocated by
+ * XEmacPs_BdRingAlloc(). Once this function returns, the argument BD set goes
+ * under hardware control. Any changes made to these BDs after this point will
+ * corrupt the BD list leading to data corruption and system instability.
+ *
+ * The set will be rejected if the last BD of the set does not mark the end of
+ * a packet (see XEmacPs_BdSetLast()).
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs in the set.
+ * @param BdSetPtr is the first BD of the set to commit to hardware.
+ *
+ * @return
+ *   - XST_SUCCESS if the set of BDs was accepted and enqueued to hardware.
+ *   - XST_FAILURE if the set of BDs was rejected because the last BD of the set
+ *     did not have its "last" bit set.
+ *   - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
+ *     XEmacPs_BdRingAlloc().
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			XEmacPs_Bd * BdSetPtr)
+{
+	XEmacPs_Bd *CurBdPtr;
+	u32 i;
+	LONG Status;
+	/* if no bds to process, simply return. */
+	if (0U == NumBd){
+		Status = (LONG)(XST_SUCCESS);
+	} else {
+	/* Make sure we are in sync with XEmacPs_BdRingAlloc() */
+	if ((RingPtr->PreCnt < NumBd) || (RingPtr->PreHead != BdSetPtr)) {
+			Status = (LONG)(XST_DMA_SG_LIST_ERROR);
+		} else {
+	CurBdPtr = BdSetPtr;
+			for (i = 0U; i < NumBd; i++) {
+				CurBdPtr = (XEmacPs_Bd *)((void *)XEmacPs_BdRingNext(RingPtr, CurBdPtr));
+	}
+	/* Adjust ring pointers & counters */
+	XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PreHead, NumBd);
+	RingPtr->PreCnt -= NumBd;
+	RingPtr->HwTail = CurBdPtr;
+	RingPtr->HwCnt += NumBd;
+
+			Status = (LONG)(XST_SUCCESS);
+		}
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Returns a set of BD(s) that have been processed by hardware. The returned
+ * BDs may be examined to determine the outcome of the DMA transaction(s).
+ * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
+ * in the same order which they were retrieved here. Example:
+ *
+ * <pre>
+ *        NumBd = XEmacPs_BdRingFromHwTx(MyRingPtr, MaxBd, &MyBdSet),
+ *        if (NumBd == 0)
+ *        {
+ *           * hardware has nothing ready for us yet*
+ *        }
+ *
+ *        CurBd = MyBdSet,
+ *        for (i=0; i<NumBd; i++)
+ *        {
+ *           * Examine CurBd for post processing *.....
+ *
+ *           * Onto next BD *
+ *           CurBd = XEmacPs_BdRingNext(MyRingPtr, CurBd),
+ *           }
+ *
+ *           XEmacPs_BdRingFree(MyRingPtr, NumBd, MyBdSet),  *Return list*
+ *        }
+ * </pre>
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be retrieved from hardware and freed in the correct sequence:
+ * <pre>
+ *        * Legal *
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ *
+ *        * Legal *
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
+ *
+ *        * Not legal *
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ * </pre>
+ *
+ * If hardware has only partially completed a packet spanning multiple BDs,
+ * then none of the BDs for that packet will be included in the results.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param BdLimit is the maximum number of BDs to return in the set.
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ *        for examination.
+ *
+ * @return
+ *   The number of BDs processed by hardware. A value of 0 indicates that no
+ *   data is available. No more than BdLimit BDs will be returned.
+ *
+ * @note Treat BDs returned by this function as read-only.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+				 XEmacPs_Bd ** BdSetPtr)
+{
+	XEmacPs_Bd *CurBdPtr;
+	u32 BdStr = 0U;
+	u32 BdCount;
+	u32 BdPartialCount;
+	u32 Sop = 0U;
+	u32 Status;
+	u32 BdLimitLoc = BdLimit;
+	CurBdPtr = RingPtr->HwHead;
+	BdCount = 0U;
+	BdPartialCount = 0U;
+
+	/* If no BDs in work group, then there's nothing to search */
+	if (RingPtr->HwCnt == 0x00000000U) {
+		*BdSetPtr = NULL;
+		Status = 0U;
+	} else {
+
+		if (BdLimitLoc > RingPtr->HwCnt){
+			BdLimitLoc = RingPtr->HwCnt;
+	}
+	/* Starting at HwHead, keep moving forward in the list until:
+	 *  - A BD is encountered with its new/used bit set which means
+	 *    hardware has not completed processing of that BD.
+	 *  - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
+	 *  - The number of requested BDs has been processed
+	 */
+		while (BdCount < BdLimitLoc) {
+		/* Read the status */
+			if(CurBdPtr != NULL){
+		BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
+			}
+
+			if ((Sop == 0x00000000U) && ((BdStr & XEMACPS_TXBUF_USED_MASK)!=0x00000000U)){
+				Sop = 1U;
+			}
+			if (Sop == 0x00000001U) {
+			BdCount++;
+			BdPartialCount++;
+		}
+
+		/* hardware has processed this BD so check the "last" bit.
+		 * If it is clear, then there are more BDs for the current
+		 * packet. Keep a count of these partial packet BDs.
+		 */
+			if ((Sop == 0x00000001U) && ((BdStr & XEMACPS_TXBUF_LAST_MASK)!=0x00000000U)) {
+				Sop = 0U;
+				BdPartialCount = 0U;
+		}
+
+		/* Move on to next BD in work group */
+		CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
+	}
+
+	/* Subtract off any partial packet BDs found */
+        BdCount -= BdPartialCount;
+
+	/* If BdCount is non-zero then BDs were found to return. Set return
+	 * parameters, update pointers and counters, return success
+	 */
+		if (BdCount > 0x00000000U) {
+		*BdSetPtr = RingPtr->HwHead;
+		RingPtr->HwCnt -= BdCount;
+		RingPtr->PostCnt += BdCount;
+		XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
+			Status = (BdCount);
+		} else {
+			*BdSetPtr = NULL;
+			Status = 0U;
+	}
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Returns a set of BD(s) that have been processed by hardware. The returned
+ * BDs may be examined to determine the outcome of the DMA transaction(s).
+ * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
+ * in the same order which they were retrieved here. Example:
+ *
+ * <pre>
+ *        NumBd = XEmacPs_BdRingFromHwRx(MyRingPtr, MaxBd, &MyBdSet),
+ *
+ *        if (NumBd == 0)
+ *        {
+ *           *hardware has nothing ready for us yet*
+ *        }
+ *
+ *        CurBd = MyBdSet,
+ *        for (i=0; i<NumBd; i++)
+ *        {
+ *           * Examine CurBd for post processing *.....
+ *
+ *           * Onto next BD *
+ *           CurBd = XEmacPs_BdRingNext(MyRingPtr, CurBd),
+ *           }
+ *
+ *           XEmacPs_BdRingFree(MyRingPtr, NumBd, MyBdSet),  * Return list *
+ *        }
+ * </pre>
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be retrieved from hardware and freed in the correct sequence:
+ * <pre>
+ *        * Legal *
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ *
+ *        * Legal *
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
+ *
+ *        * Not legal *
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ * </pre>
+ *
+ * If hardware has only partially completed a packet spanning multiple BDs,
+ * then none of the BDs for that packet will be included in the results.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param BdLimit is the maximum number of BDs to return in the set.
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ *        for examination.
+ *
+ * @return
+ *   The number of BDs processed by hardware. A value of 0 indicates that no
+ *   data is available. No more than BdLimit BDs will be returned.
+ *
+ * @note Treat BDs returned by this function as read-only.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+				 XEmacPs_Bd ** BdSetPtr)
+{
+	XEmacPs_Bd *CurBdPtr;
+	u32 BdStr = 0U;
+	u32 BdCount;
+	u32 BdPartialCount;
+	u32 Status;
+
+	CurBdPtr = RingPtr->HwHead;
+	BdCount = 0U;
+	BdPartialCount = 0U;
+
+	/* If no BDs in work group, then there's nothing to search */
+	if (RingPtr->HwCnt == 0x00000000U) {
+		*BdSetPtr = NULL;
+		Status = 0U;
+	} else {
+
+	/* Starting at HwHead, keep moving forward in the list until:
+	 *  - A BD is encountered with its new/used bit set which means
+	 *    hardware has completed processing of that BD.
+	 *  - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
+	 *  - The number of requested BDs has been processed
+	 */
+	while (BdCount < BdLimit) {
+
+		/* Read the status */
+			if(CurBdPtr!=NULL){
+		BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
+			}
+			if ((!(XEmacPs_BdIsRxNew(CurBdPtr)))==TRUE) {
+			break;
+		}
+
+		BdCount++;
+
+		/* hardware has processed this BD so check the "last" bit. If
+                 * it is clear, then there are more BDs for the current packet.
+                 * Keep a count of these partial packet BDs.
+		 */
+			if ((BdStr & XEMACPS_RXBUF_EOF_MASK)!=0x00000000U) {
+				BdPartialCount = 0U;
+			} else {
+			BdPartialCount++;
+		}
+
+		/* Move on to next BD in work group */
+		CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
+	}
+
+	/* Subtract off any partial packet BDs found */
+	BdCount -= BdPartialCount;
+
+	/* If BdCount is non-zero then BDs were found to return. Set return
+	 * parameters, update pointers and counters, return success
+	 */
+		if (BdCount > 0x00000000U) {
+		*BdSetPtr = RingPtr->HwHead;
+		RingPtr->HwCnt -= BdCount;
+		RingPtr->PostCnt += BdCount;
+		XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
+			Status = (BdCount);
+	}
+	else {
+		*BdSetPtr = NULL;
+			Status = 0U;
+	}
+}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Frees a set of BDs that had been previously retrieved with
+ * XEmacPs_BdRingFromHw().
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs to free.
+ * @param BdSetPtr is the head of a list of BDs returned by
+ * XEmacPs_BdRingFromHw().
+ *
+ * @return
+ *   - XST_SUCCESS if the set of BDs was freed.
+ *   - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
+ *     XEmacPs_BdRingFromHw().
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			XEmacPs_Bd * BdSetPtr)
+{
+	LONG Status;
+	/* if no bds to process, simply return. */
+	if (0x00000000U == NumBd){
+		Status = (LONG)(XST_SUCCESS);
+	} else {
+	/* Make sure we are in sync with XEmacPs_BdRingFromHw() */
+	if ((RingPtr->PostCnt < NumBd) || (RingPtr->PostHead != BdSetPtr)) {
+			Status = (LONG)(XST_DMA_SG_LIST_ERROR);
+		} else {
+	/* Update pointers and counters */
+	RingPtr->FreeCnt += NumBd;
+	RingPtr->PostCnt -= NumBd;
+	XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PostHead, NumBd);
+			Status = (LONG)(XST_SUCCESS);
+		}
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Check the internal data structures of the BD ring for the provided channel.
+ * The following checks are made:
+ *
+ *   - Is the BD ring linked correctly in physical address space.
+ *   - Do the internal pointers point to BDs in the ring.
+ *   - Do the internal counters add up.
+ *
+ * The channel should be stopped prior to calling this function.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates
+ *        which direction.
+ *
+ * @return
+ *   - XST_SUCCESS if the set of BDs was freed.
+ *   - XST_DMA_SG_NO_LIST if the list has not been created.
+ *   - XST_IS_STARTED if the channel is not stopped.
+ *   - XST_DMA_SG_LIST_ERROR if a problem is found with the internal data
+ *     structures. If this value is returned, the channel should be reset to
+ *     avoid data corruption or system instability.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction)
+{
+	UINTPTR AddrV, AddrP;
+	u32 i;
+
+	if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
+		return (LONG)(XST_INVALID_PARAM);
+	}
+
+	/* Is the list created */
+	if (RingPtr->AllCnt == 0x00000000U) {
+		return (LONG)(XST_DMA_SG_NO_LIST);
+	}
+
+	/* Can't check if channel is running */
+	if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
+		return (LONG)(XST_IS_STARTED);
+	}
+
+	/* RunState doesn't make sense */
+	if (RingPtr->RunState != (u32)XST_DMA_SG_IS_STOPPED) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	/* Verify internal pointers point to correct memory space */
+	AddrV = (UINTPTR) RingPtr->FreeHead;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	AddrV = (UINTPTR) RingPtr->PreHead;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	AddrV = (UINTPTR) RingPtr->HwHead;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	AddrV = (UINTPTR) RingPtr->HwTail;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	AddrV = (UINTPTR) RingPtr->PostHead;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	/* Verify internal counters add up */
+	if ((RingPtr->HwCnt + RingPtr->PreCnt + RingPtr->FreeCnt +
+	     RingPtr->PostCnt) != RingPtr->AllCnt) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	/* Verify BDs are linked correctly */
+	AddrV = RingPtr->BaseBdAddr;
+	AddrP = RingPtr->PhysBaseAddr + RingPtr->Separation;
+
+	for (i = 1U; i < RingPtr->AllCnt; i++) {
+		/* Check BDA for this BD. It should point to next physical addr */
+		if (XEmacPs_BdRead(AddrV, XEMACPS_BD_ADDR_OFFSET) != AddrP) {
+			return (LONG)(XST_DMA_SG_LIST_ERROR);
+		}
+
+		/* Move on to next BD */
+		AddrV += RingPtr->Separation;
+		AddrP += RingPtr->Separation;
+	}
+
+	/* Last BD should have wrap bit set */
+	if (XEMACPS_SEND == Direction) {
+		if ((!XEmacPs_BdIsTxWrap(AddrV))==TRUE) {
+			return (LONG)(XST_DMA_SG_LIST_ERROR);
+		}
+	}
+	else {			/* XEMACPS_RECV */
+		if ((!XEmacPs_BdIsRxWrap(AddrV))==TRUE) {
+			return (LONG)(XST_DMA_SG_LIST_ERROR);
+		}
+	}
+
+	/* No problems found */
+	return (LONG)(XST_SUCCESS);
+}
+
+/*****************************************************************************/
+/**
+ * Set this bit to mark the last descriptor in the receive buffer descriptor
+ * list.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr)
+{
+    u32 DataValueRx;
+	u32 *TempPtr;
+
+	BdPtr += (u32)(XEMACPS_BD_ADDR_OFFSET);
+	TempPtr = (u32 *)BdPtr;
+	if(TempPtr != NULL) {
+		DataValueRx = *TempPtr;
+		DataValueRx |= XEMACPS_RXBUF_WRAP_MASK;
+		*TempPtr = DataValueRx;
+	}
+}
+
+/*****************************************************************************/
+/**
+ * Sets this bit to mark the last descriptor in the transmit buffer
+ * descriptor list.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr)
+{
+    u32 DataValueTx;
+	u32 *TempPtr;
+
+	BdPtr += (u32)(XEMACPS_BD_STAT_OFFSET);
+	TempPtr = (u32 *)BdPtr;
+	if(TempPtr != NULL) {
+		DataValueTx = *TempPtr;
+		DataValueTx |= XEMACPS_TXBUF_WRAP_MASK;
+		*TempPtr = DataValueTx;
+	}
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_bdring.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_bdring.h
new file mode 100644
index 0000000000000000000000000000000000000000..de78cf28f7e14d645d9a7d065bacd1b5de373ad7
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_bdring.h
@@ -0,0 +1,238 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_bdring.h
+* @addtogroup emacps_v3_1
+* @{
+*
+* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
+* DMA functionalities.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp architecture.
+* 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XEMACPS_BDRING_H	/* prevent curcular inclusions */
+#define XEMACPS_BDRING_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**************************** Type Definitions *******************************/
+
+/** This is an internal structure used to maintain the DMA list */
+typedef struct {
+	UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
+	UINTPTR BaseBdAddr;	 /**< Virtual address of 1st BD in list */
+	UINTPTR HighBdAddr;	 /**< Virtual address of last BD in the list */
+	u32 Length;	 /**< Total size of ring in bytes */
+	u32 RunState;	 /**< Flag to indicate DMA is started */
+	u32 Separation;	 /**< Number of bytes between the starting address
+                                  of adjacent BDs */
+	XEmacPs_Bd *FreeHead;
+			     /**< First BD in the free group */
+	XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
+	XEmacPs_Bd *HwHead; /**< First BD in the work group */
+	XEmacPs_Bd *HwTail; /**< Last BD in the work group */
+	XEmacPs_Bd *PostHead;
+			     /**< First BD in the post-work group */
+	XEmacPs_Bd *BdaRestart;
+			     /**< BDA to load when channel is started */
+
+	u32 HwCnt;	     /**< Number of BDs in work group */
+	u32 PreCnt;     /**< Number of BDs in pre-work group */
+	u32 FreeCnt;    /**< Number of allocatable BDs in the free group */
+	u32 PostCnt;    /**< Number of BDs in post-work group */
+	u32 AllCnt;     /**< Total Number of BDs for channel */
+} XEmacPs_BdRing;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many BDs will fit
+* in a BD list within the given memory constraints.
+*
+* The results of this macro can be provided to XEmacPs_BdRingCreate().
+*
+* @param Alignment specifies what byte alignment the BDs must fall on and
+*        must be a power of 2 to get an accurate calculation (32, 64, 128,...)
+* @param Bytes is the number of bytes to be used to store BDs.
+*
+* @return Number of BDs that can fit in the given memory area
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)
+*
+******************************************************************************/
+#define XEmacPs_BdRingCntCalc(Alignment, Bytes)                    \
+    (u32)((Bytes) / (sizeof(XEmacPs_Bd)))
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many bytes of memory
+* is required to contain a given number of BDs at a given alignment.
+*
+* @param Alignment specifies what byte alignment the BDs must fall on. This
+*        parameter must be a power of 2 to get an accurate calculation (32, 64,
+*        128,...)
+* @param NumBd is the number of BDs to calculate memory size requirements for
+*
+* @return The number of bytes of memory required to create a BD list with the
+*         given memory constraints.
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)
+*
+******************************************************************************/
+#define XEmacPs_BdRingMemCalc(Alignment, NumBd)                    \
+    (u32)(sizeof(XEmacPs_Bd) * (NumBd))
+
+/****************************************************************************/
+/**
+* Return the total number of BDs allocated by this channel with
+* XEmacPs_BdRingCreate().
+*
+* @param  RingPtr is the DMA channel to operate on.
+*
+* @return The total number of BDs allocated for this channel.
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
+
+/****************************************************************************/
+/**
+* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre-
+* processing.
+*
+* @param  RingPtr is the DMA channel to operate on.
+*
+* @return The number of BDs currently allocatable.
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetFreeCnt(RingPtr)   ((RingPtr)->FreeCnt)
+
+/****************************************************************************/
+/**
+* Return the next BD from BdPtr in a list.
+*
+* @param  RingPtr is the DMA channel to operate on.
+* @param  BdPtr is the BD to operate on.
+*
+* @return The next BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+*    XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr,
+*                                      XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingNext(RingPtr, BdPtr)                           \
+    (((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ?                     \
+    (XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) :                              \
+    (XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation))
+
+/****************************************************************************/
+/**
+* Return the previous BD from BdPtr in the list.
+*
+* @param  RingPtr is the DMA channel to operate on.
+* @param  BdPtr is the BD to operate on
+*
+* @return The previous BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+*    XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr,
+*                                      XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingPrev(RingPtr, BdPtr)                           \
+    (((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ?                     \
+    (XEmacPs_Bd*)(RingPtr)->HighBdAddr :                              \
+    (XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Scatter gather DMA related functions in xemacps_bdring.c
+ */
+LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
+			  UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
+LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
+			 u8 Direction);
+LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			 XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			   XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			XEmacPs_Bd * BdSetPtr);
+u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+				 XEmacPs_Bd ** BdSetPtr);
+u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+				 XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* end of protection macros */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_control.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_control.c
new file mode 100644
index 0000000000000000000000000000000000000000..f52451a8c555cfcd33cf07dc70da387324ea6652
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_control.c
@@ -0,0 +1,1174 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xemacps_control.c
+* @addtogroup emacps_v3_1
+* @{
+ *
+ * Functions in this file implement general purpose command and control related
+ * functionality. See xemacps.h for a detailed description of the driver.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ * 1.02a asa  11/05/12 Added a new API for deleting an entry from the HASH
+ *					   register. Added a new API for setting the BURST length
+ *					   in DMACR register.
+ * 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp architecture.
+ * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0   hk   02/20/15 Added support for jumbo frames.
+ * 3.2   hk   02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+ * </pre>
+ *****************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+ * Set the MAC address for this driver/device.  The address is a 48-bit value.
+ * The device must be stopped before calling this function.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is a pointer to a 6-byte MAC address.
+ * @param Index is a index to which MAC (1-4) address.
+ *
+ * @return
+ * - XST_SUCCESS if the MAC address was set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
+{
+	u32 MacAddr;
+	u8 *Aptr = (u8 *)(void *)AddressPtr;
+	u8 IndexLoc = Index;
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Aptr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	}
+	else{
+	/* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+		IndexLoc--;
+
+	/* Set the MAC bits [31:0] in BOT */
+		MacAddr = *(Aptr);
+		MacAddr |= ((u32)(*(Aptr+1)) << 8U);
+		MacAddr |= ((u32)(*(Aptr+2)) << 16U);
+		MacAddr |= ((u32)(*(Aptr+3)) << 24U);
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
+
+	/* There are reserved bits in TOP so don't affect them */
+	MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
+
+		MacAddr &= (u32)(~XEMACPS_LADDR_MACH_MASK);
+
+	/* Set MAC bits [47:32] in TOP */
+		MacAddr |= (u32)(*(Aptr+4));
+		MacAddr |= (u32)(*(Aptr+5)) << 8U;
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Get the MAC address for this driver/device.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is an output parameter, and is a pointer to a buffer into
+ *        which the current MAC address will be copied.
+ * @param Index is a index to which MAC (1-4) address.
+ *
+ *****************************************************************************/
+void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
+{
+	u32 MacAddr;
+	u8 *Aptr = (u8 *)(void *)AddressPtr;
+	u8 IndexLoc = Index;
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Aptr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
+
+	/* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+	IndexLoc--;
+
+	MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    ((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)));
+	*Aptr = (u8) MacAddr;
+	*(Aptr+1) = (u8) (MacAddr >> 8U);
+	*(Aptr+2) = (u8) (MacAddr >> 16U);
+	*(Aptr+3) = (u8) (MacAddr >> 24U);
+
+	/* Read MAC bits [47:32] in TOP */
+	MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    ((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
+	*(Aptr+4) = (u8) MacAddr;
+	*(Aptr+5) = (u8) (MacAddr >> 8U);
+}
+
+
+/*****************************************************************************/
+/**
+ * Set 48-bit MAC addresses in hash table.
+ * The device must be stopped before calling this function.
+ *
+ * The hash address register is 64 bits long and takes up two locations in
+ * the memory map. The least significant bits are stored in hash register
+ * bottom and the most significant bits in hash register top.
+ *
+ * The unicast hash enable and the multicast hash enable bits in the network
+ * configuration register enable the reception of hash matched frames. The
+ * destination address is reduced to a 6 bit index into the 64 bit hash
+ * register using the following hash function. The hash function is an XOR
+ * of every sixth bit of the destination address.
+ *
+ * <pre>
+ * hash_index[05] = da[05]^da[11]^da[17]^da[23]^da[29]^da[35]^da[41]^da[47]
+ * hash_index[04] = da[04]^da[10]^da[16]^da[22]^da[28]^da[34]^da[40]^da[46]
+ * hash_index[03] = da[03]^da[09]^da[15]^da[21]^da[27]^da[33]^da[39]^da[45]
+ * hash_index[02] = da[02]^da[08]^da[14]^da[20]^da[26]^da[32]^da[38]^da[44]
+ * hash_index[01] = da[01]^da[07]^da[13]^da[19]^da[25]^da[31]^da[37]^da[43]
+ * hash_index[00] = da[00]^da[06]^da[12]^da[18]^da[24]^da[30]^da[36]^da[42]
+ * </pre>
+ *
+ * da[0] represents the least significant bit of the first byte received,
+ * that is, the multicast/unicast indicator, and da[47] represents the most
+ * significant bit of the last byte received.
+ *
+ * If the hash index points to a bit that is set in the hash register then
+ * the frame will be matched according to whether the frame is multicast
+ * or unicast.
+ *
+ * A multicast match will be signaled if the multicast hash enable bit is
+ * set, da[0] is logic 1 and the hash index points to a bit set in the hash
+ * register.
+ *
+ * A unicast match will be signaled if the unicast hash enable bit is set,
+ * da[0] is logic 0 and the hash index points to a bit set in the hash
+ * register.
+ *
+ * To receive all multicast frames, the hash register should be set with
+ * all ones and the multicast hash enable bit should be set in the network
+ * configuration register.
+ *
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is a pointer to a 6-byte MAC address.
+ *
+ * @return
+ * - XST_SUCCESS if the HASH MAC address was set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ * - XST_INVALID_PARAM if the HASH MAC address passed in does not meet
+ *   requirement after calculation
+ *
+ * @note
+ * Having Aptr be unsigned type prevents the following operations from sign
+ * extending.
+ *****************************************************************************/
+LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr)
+{
+	u32 HashAddr;
+	u8 *Aptr = (u8 *)(void *)AddressPtr;
+	u8 Temp1, Temp2, Temp3, Temp4, Temp5, Temp6, Temp7, Temp8;
+	u32 Result;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(AddressPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+		Temp1 = (*(Aptr+0)) & 0x3FU;
+		Temp2 = ((*(Aptr+0) >> 6U) & 0x03U) | ((*(Aptr+1) & 0x0FU) << 2U);
+
+		Temp3 = ((*(Aptr+1) >> 4U) & 0x0FU) | ((*(Aptr+2) & 0x3U) << 4U);
+		Temp4 = ((*(Aptr+2) >> 2U) & 0x3FU);
+		Temp5 =   (*(Aptr+3)) & 0x3FU;
+		Temp6 = ((*(Aptr+3) >> 6U) & 0x03U) | ((*(Aptr+4) & 0x0FU) << 2U);
+		Temp7 = ((*(Aptr+4) >> 4U) & 0x0FU) | ((*(Aptr+5) & 0x03U) << 4U);
+		Temp8 = ((*(Aptr+5) >> 2U) & 0x3FU);
+
+		Result = (u32)((u32)Temp1 ^ (u32)Temp2 ^ (u32)Temp3 ^ (u32)Temp4 ^
+				(u32)Temp5 ^ (u32)Temp6 ^ (u32)Temp7 ^ (u32)Temp8);
+
+		if (Result >= (u32)XEMACPS_MAX_HASH_BITS) {
+			Status = (LONG)(XST_INVALID_PARAM);
+		} else {
+
+			if (Result < (u32)32) {
+		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHL_OFFSET);
+				HashAddr |= (u32)(0x00000001U << Result);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_HASHL_OFFSET, HashAddr);
+	} else {
+		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHH_OFFSET);
+				HashAddr |= (u32)(0x00000001U << (u32)(Result - (u32)32));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_HASHH_OFFSET, HashAddr);
+	}
+			Status = (LONG)(XST_SUCCESS);
+		}
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * Delete 48-bit MAC addresses in hash table.
+ * The device must be stopped before calling this function.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is a pointer to a 6-byte MAC address.
+ *
+ * @return
+ * - XST_SUCCESS if the HASH MAC address was deleted successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ * - XST_INVALID_PARAM if the HASH MAC address passed in does not meet
+ *   requirement after calculation
+ *
+ * @note
+ * Having Aptr be unsigned type prevents the following operations from sign
+ * extending.
+ *****************************************************************************/
+LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr)
+{
+	u32 HashAddr;
+	u8 *Aptr = (u8 *)(void *)AddressPtr;
+	u8 Temp1, Temp2, Temp3, Temp4, Temp5, Temp6, Temp7, Temp8;
+	u32 Result;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Aptr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+		Temp1 = (*(Aptr+0)) & 0x3FU;
+		Temp2 = ((*(Aptr+0) >> 6U) & 0x03U) | ((*(Aptr+1) & 0x0FU) << 2U);
+		Temp3 = ((*(Aptr+1) >> 4U) & 0x0FU) | ((*(Aptr+2) & 0x03U) << 4U);
+		Temp4 = ((*(Aptr+2) >> 2U) & 0x3FU);
+		Temp5 =   (*(Aptr+3)) & 0x3FU;
+		Temp6 = ((*(Aptr+3) >> 6U) & 0x03U) | ((*(Aptr+4) & 0x0FU) << 2U);
+		Temp7 = ((*(Aptr+4) >> 4U) & 0x0FU) | ((*(Aptr+5) & 0x03U) << 4U);
+		Temp8 = ((*(Aptr+5) >> 2U) & 0x3FU);
+
+		Result = (u32)((u32)Temp1 ^ (u32)Temp2 ^ (u32)Temp3 ^ (u32)Temp4 ^
+					(u32)Temp5 ^ (u32)Temp6 ^ (u32)Temp7 ^ (u32)Temp8);
+
+		if (Result >= (u32)(XEMACPS_MAX_HASH_BITS)) {
+			Status =  (LONG)(XST_INVALID_PARAM);
+		} else {
+			if (Result < (u32)32) {
+		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHL_OFFSET);
+				HashAddr &= (u32)(~(0x00000001U << Result));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHL_OFFSET, HashAddr);
+	} else {
+		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHH_OFFSET);
+				HashAddr &= (u32)(~(0x00000001U << (u32)(Result - (u32)32)));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_HASHH_OFFSET, HashAddr);
+	}
+			Status = (LONG)(XST_SUCCESS);
+		}
+	}
+	return Status;
+}
+/*****************************************************************************/
+/**
+ * Clear the Hash registers for the mac address pointed by AddressPtr.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ *
+ *****************************************************************************/
+void XEmacPs_ClearHash(XEmacPs *InstancePtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_HASHL_OFFSET, 0x0U);
+
+	/* write bits [63:32] in TOP */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_HASHH_OFFSET, 0x0U);
+}
+
+
+/*****************************************************************************/
+/**
+ * Get the Hash address for this driver/device.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is an output parameter, and is a pointer to a buffer into
+ *        which the current HASH MAC address will be copied.
+ *
+ *****************************************************************************/
+void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr)
+{
+	u32 *Aptr = (u32 *)(void *)AddressPtr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(AddressPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	*(Aptr+0) = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_HASHL_OFFSET);
+
+	/* Read Hash bits [63:32] in TOP */
+	*(Aptr+1) = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_HASHH_OFFSET);
+}
+
+
+/*****************************************************************************/
+/**
+ * Set the Type ID match for this driver/device.  The register is a 32-bit
+ * value. The device must be stopped before calling this function.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Id_Check is type ID to be configured.
+ * @param Index is a index to which Type ID (1-4).
+ *
+ * @return
+ * - XST_SUCCESS if the MAC address was set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index)
+{
+	u8 IndexLoc = Index;
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((IndexLoc <= (u8)XEMACPS_MAX_TYPE_ID) && (IndexLoc > 0x00U));
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+
+	/* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+		IndexLoc--;
+
+	/* Set the ID bits in MATCHx register */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   ((u32)XEMACPS_MATCH1_OFFSET + ((u32)IndexLoc * (u32)4)), Id_Check);
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * Set options for the driver/device. The driver should be stopped with
+ * XEmacPs_Stop() before changing options.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Options are the options to set. Multiple options can be set by OR'ing
+ *        XTE_*_OPTIONS constants together. Options not specified are not
+ *        affected.
+ *
+ * @return
+ * - XST_SUCCESS if the options were set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ * @note
+ * See xemacps.h for a description of the available options.
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options)
+{
+	u32 Reg;		/* Generic register contents */
+	u32 RegNetCfg;		/* Reflects original contents of NET_CONFIG */
+	u32 RegNewNetCfg;	/* Reflects new contents of NET_CONFIG */
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+
+	/* Many of these options will change the NET_CONFIG registers.
+	 * To reduce the amount of IO to the device, group these options here
+	 * and change them all at once.
+	 */
+
+	/* Grab current register contents */
+	RegNetCfg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XEMACPS_NWCFG_OFFSET);
+	RegNewNetCfg = RegNetCfg;
+
+	/*
+	 * It is configured to max 1536.
+	 */
+		if ((Options & XEMACPS_FRAME1536_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= (XEMACPS_NWCFG_1536RXEN_MASK);
+	}
+
+	/* Turn on VLAN packet only, only VLAN tagged will be accepted */
+		if ((Options & XEMACPS_VLAN_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_NVLANDISC_MASK;
+	}
+
+	/* Turn on FCS stripping on receive packets */
+		if ((Options & XEMACPS_FCS_STRIP_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_FCSREM_MASK;
+	}
+
+	/* Turn on length/type field checking on receive packets */
+		if ((Options & XEMACPS_LENTYPE_ERR_OPTION) != 0x00000000U) {
+			RegNewNetCfg |= XEMACPS_NWCFG_LENERRDSCRD_MASK;
+	}
+
+	/* Turn on flow control */
+		if ((Options & XEMACPS_FLOW_CONTROL_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_PAUSEEN_MASK;
+	}
+
+	/* Turn on promiscuous frame filtering (all frames are received) */
+		if ((Options & XEMACPS_PROMISC_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_COPYALLEN_MASK;
+	}
+
+	/* Allow broadcast address reception */
+		if ((Options & XEMACPS_BROADCAST_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_BCASTDI_MASK);
+	}
+
+	/* Allow multicast address filtering */
+		if ((Options & XEMACPS_MULTICAST_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_MCASTHASHEN_MASK;
+	}
+
+	/* enable RX checksum offload */
+		if ((Options & XEMACPS_RX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_RXCHKSUMEN_MASK;
+	}
+
+	/* Enable jumbo frames */
+	if (((Options & XEMACPS_JUMBO_ENABLE_OPTION) != 0x00000000U) &&
+		(InstancePtr->Version > 2)) {
+		RegNewNetCfg |= XEMACPS_NWCFG_JUMBO_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_JUMBOMAXLEN_OFFSET, XEMACPS_RX_BUF_SIZE_JUMBO);
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XEMACPS_DMACR_OFFSET);
+		Reg &= ~XEMACPS_DMACR_RXBUF_MASK;
+		Reg |= (((((u32)XEMACPS_RX_BUF_SIZE_JUMBO / (u32)XEMACPS_RX_BUF_UNIT) +
+			(((((u32)XEMACPS_RX_BUF_SIZE_JUMBO %
+			(u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
+			(u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
+			(u32)(XEMACPS_DMACR_RXBUF_MASK));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_DMACR_OFFSET, Reg);
+		InstancePtr->MaxMtuSize = XEMACPS_MTU_JUMBO;
+		InstancePtr->MaxFrameSize = XEMACPS_MTU_JUMBO +
+					XEMACPS_HDR_SIZE + XEMACPS_TRL_SIZE;
+		InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
+					XEMACPS_HDR_VLAN_SIZE;
+		InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_JUMBO_MASK;
+	}
+
+	if (((Options & XEMACPS_SGMII_ENABLE_OPTION) != 0x00000000U) &&
+		(InstancePtr->Version > 2)) {
+		RegNewNetCfg |= (XEMACPS_NWCFG_SGMIIEN_MASK |
+						XEMACPS_NWCFG_PCSSEL_MASK);
+	}
+
+	/* Officially change the NET_CONFIG registers if it needs to be
+	 * modified.
+	 */
+	if (RegNetCfg != RegNewNetCfg) {
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCFG_OFFSET, RegNewNetCfg);
+	}
+
+	/* Enable TX checksum offload */
+		if ((Options & XEMACPS_TX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_DMACR_OFFSET);
+		Reg |= XEMACPS_DMACR_TCPCKSUM_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XEMACPS_DMACR_OFFSET, Reg);
+	}
+
+	/* Enable transmitter */
+		if ((Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+		Reg |= XEMACPS_NWCTRL_TXEN_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCTRL_OFFSET, Reg);
+	}
+
+	/* Enable receiver */
+		if ((Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+		Reg |= XEMACPS_NWCTRL_RXEN_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCTRL_OFFSET, Reg);
+	}
+
+	/* The remaining options not handled here are managed elsewhere in the
+	 * driver. No register modifications are needed at this time. Reflecting
+	 * the option in InstancePtr->Options is good enough for now.
+	 */
+
+	/* Set options word to its new value */
+	InstancePtr->Options |= Options;
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Clear options for the driver/device
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Options are the options to clear. Multiple options can be cleared by
+ *        OR'ing XEMACPS_*_OPTIONS constants together. Options not specified
+ *        are not affected.
+ *
+ * @return
+ * - XST_SUCCESS if the options were set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ * @note
+ * See xemacps.h for a description of the available options.
+ *
+ *****************************************************************************/
+LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options)
+{
+	u32 Reg;		/* Generic */
+	u32 RegNetCfg;		/* Reflects original contents of NET_CONFIG */
+	u32 RegNewNetCfg;	/* Reflects new contents of NET_CONFIG */
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+
+	/* Many of these options will change the NET_CONFIG registers.
+	 * To reduce the amount of IO to the device, group these options here
+	 * and change them all at once.
+	 */
+
+	/* Grab current register contents */
+	RegNetCfg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XEMACPS_NWCFG_OFFSET);
+	RegNewNetCfg = RegNetCfg;
+
+	/* There is only RX configuration!?
+	 * It is configured in two different length, upto 1536 and 10240 bytes
+	 */
+		if ((Options & XEMACPS_FRAME1536_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_1536RXEN_MASK);
+	}
+
+	/* Turn off VLAN packet only */
+		if ((Options & XEMACPS_VLAN_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_NVLANDISC_MASK);
+	}
+
+	/* Turn off FCS stripping on receive packets */
+		if ((Options & XEMACPS_FCS_STRIP_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_FCSREM_MASK);
+	}
+
+	/* Turn off length/type field checking on receive packets */
+		if ((Options & XEMACPS_LENTYPE_ERR_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_LENERRDSCRD_MASK);
+	}
+
+	/* Turn off flow control */
+		if ((Options & XEMACPS_FLOW_CONTROL_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_PAUSEEN_MASK);
+	}
+
+	/* Turn off promiscuous frame filtering (all frames are received) */
+		if ((Options & XEMACPS_PROMISC_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_COPYALLEN_MASK);
+	}
+
+	/* Disallow broadcast address filtering => broadcast reception */
+		if ((Options & XEMACPS_BROADCAST_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_BCASTDI_MASK;
+	}
+
+	/* Disallow multicast address filtering */
+		if ((Options & XEMACPS_MULTICAST_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_MCASTHASHEN_MASK);
+	}
+
+	/* Disable RX checksum offload */
+		if ((Options & XEMACPS_RX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_RXCHKSUMEN_MASK);
+	}
+
+	/* Disable jumbo frames */
+	if (((Options & XEMACPS_JUMBO_ENABLE_OPTION) != 0x00000000U) &&
+		(InstancePtr->Version > 2)) {
+		RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_JUMBO_MASK);
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XEMACPS_DMACR_OFFSET);
+		Reg &= ~XEMACPS_DMACR_RXBUF_MASK;
+		Reg |= (((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) +
+			(((((u32)XEMACPS_RX_BUF_SIZE %
+			(u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
+			(u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
+			(u32)(XEMACPS_DMACR_RXBUF_MASK));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_DMACR_OFFSET, Reg);
+		InstancePtr->MaxMtuSize = XEMACPS_MTU;
+		InstancePtr->MaxFrameSize = XEMACPS_MTU +
+					XEMACPS_HDR_SIZE + XEMACPS_TRL_SIZE;
+		InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
+					XEMACPS_HDR_VLAN_SIZE;
+		InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_MASK;
+	}
+
+	if (((Options & XEMACPS_SGMII_ENABLE_OPTION) != 0x00000000U) &&
+		(InstancePtr->Version > 2)) {
+		RegNewNetCfg &= (u32)(~(XEMACPS_NWCFG_SGMIIEN_MASK |
+						XEMACPS_NWCFG_PCSSEL_MASK));
+	}
+
+	/* Officially change the NET_CONFIG registers if it needs to be
+	 * modified.
+	 */
+	if (RegNetCfg != RegNewNetCfg) {
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCFG_OFFSET, RegNewNetCfg);
+	}
+
+	/* Disable TX checksum offload */
+		if ((Options & XEMACPS_TX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_DMACR_OFFSET);
+			Reg &= (u32)(~XEMACPS_DMACR_TCPCKSUM_MASK);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XEMACPS_DMACR_OFFSET, Reg);
+	}
+
+	/* Disable transmitter */
+		if ((Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+			Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCTRL_OFFSET, Reg);
+	}
+
+	/* Disable receiver */
+		if ((Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+			Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCTRL_OFFSET, Reg);
+	}
+
+	/* The remaining options not handled here are managed elsewhere in the
+	 * driver. No register modifications are needed at this time. Reflecting
+	 * option in InstancePtr->Options is good enough for now.
+	 */
+
+	/* Set options word to its new value */
+	InstancePtr->Options &= ~Options;
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Get current option settings
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ *
+ * @return
+ * A bitmask of XTE_*_OPTION constants. Any bit set to 1 is to be interpreted
+ * as a set opion.
+ *
+ * @note
+ * See xemacps.h for a description of the available options.
+ *
+ *****************************************************************************/
+u32 XEmacPs_GetOptions(XEmacPs *InstancePtr)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	return (InstancePtr->Options);
+}
+
+
+/*****************************************************************************/
+/**
+ * Send a pause packet
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ *
+ * @return
+ * - XST_SUCCESS if pause frame transmission was initiated
+ * - XST_DEVICE_IS_STOPPED if the device has not been started.
+ *
+ *****************************************************************************/
+LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr)
+{
+	u32 Reg;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Make sure device is ready for this operation */
+	if (InstancePtr->IsStarted != (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STOPPED);
+	} else {
+	/* Send flow control frame */
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWCTRL_OFFSET);
+	Reg |= XEMACPS_NWCTRL_PAUSETX_MASK;
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_NWCTRL_OFFSET, Reg);
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * XEmacPs_GetOperatingSpeed gets the current operating link speed. This may
+ * be the value set by XEmacPs_SetOperatingSpeed() or a hardware default.
+ *
+ * @param InstancePtr references the TEMAC channel on which to operate.
+ *
+ * @return XEmacPs_GetOperatingSpeed returns the link speed in units of
+ *         megabits per second.
+ *
+ * @note
+ *
+ *****************************************************************************/
+u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr)
+{
+	u32 Reg;
+	u16 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_NWCFG_OFFSET);
+
+	if ((Reg & XEMACPS_NWCFG_1000_MASK) != 0x00000000U) {
+		Status = (u16)(1000);
+	} else {
+		if ((Reg & XEMACPS_NWCFG_100_MASK) != 0x00000000U) {
+			Status = (u16)(100);
+		} else {
+			Status = (u16)(10);
+		}
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * XEmacPs_SetOperatingSpeed sets the current operating link speed. For any
+ * traffic to be passed, this speed must match the current MII/GMII/SGMII/RGMII
+ * link speed.
+ *
+ * @param InstancePtr references the TEMAC channel on which to operate.
+ * @param Speed is the speed to set in units of Mbps. Valid values are 10, 100,
+ *        or 1000. XEmacPs_SetOperatingSpeed ignores invalid values.
+ *
+ * @note
+ *
+ *****************************************************************************/
+void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed)
+{
+        u32 Reg;
+	u16 Status;
+        Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+    Xil_AssertVoid((Speed == (u16)10) || (Speed == (u16)100) || (Speed == (u16)1000));
+
+        Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_NWCFG_OFFSET);
+	Reg &= (u32)(~(XEMACPS_NWCFG_1000_MASK | XEMACPS_NWCFG_100_MASK));
+
+	switch (Speed) {
+		case (u16)10:
+				Status = 0U;
+                break;
+
+        case (u16)100:
+			Status = 0U;
+                Reg |= XEMACPS_NWCFG_100_MASK;
+                break;
+
+        case (u16)1000:
+			Status = 0U;
+                Reg |= XEMACPS_NWCFG_1000_MASK;
+                break;
+
+        default:
+			Status = 1U;
+                break;
+    }
+	if(Status == (u16)1){
+                return;
+        }
+
+        /* Set register and return */
+        XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+                XEMACPS_NWCFG_OFFSET, Reg);
+}
+
+
+/*****************************************************************************/
+/**
+ * Set the MDIO clock divisor.
+ *
+ * Calculating the divisor:
+ *
+ * <pre>
+ *              f[HOSTCLK]
+ *   f[MDC] = -----------------
+ *            (1 + Divisor) * 2
+ * </pre>
+ *
+ * where f[HOSTCLK] is the bus clock frequency in MHz, and f[MDC] is the
+ * MDIO clock frequency in MHz to the PHY. Typically, f[MDC] should not
+ * exceed 2.5 MHz. Some PHYs can tolerate faster speeds which means faster
+ * access. Here is the table to show values to generate MDC,
+ *
+ * <pre>
+ * 000 : divide pclk by   8 (pclk up to  20 MHz)
+ * 001 : divide pclk by  16 (pclk up to  40 MHz)
+ * 010 : divide pclk by  32 (pclk up to  80 MHz)
+ * 011 : divide pclk by  48 (pclk up to 120 MHz)
+ * 100 : divide pclk by  64 (pclk up to 160 MHz)
+ * 101 : divide pclk by  96 (pclk up to 240 MHz)
+ * 110 : divide pclk by 128 (pclk up to 320 MHz)
+ * 111 : divide pclk by 224 (pclk up to 540 MHz)
+ * </pre>
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Divisor is the divisor to set. Range is 0b000 to 0b111.
+ *
+ *****************************************************************************/
+void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, XEmacPs_MdcDiv Divisor)
+{
+	u32 Reg;
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Divisor <= (XEmacPs_MdcDiv)0x7); /* only last three bits are valid */
+
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWCFG_OFFSET);
+	/* clear these three bits, could be done with mask */
+	Reg &= (u32)(~XEMACPS_NWCFG_MDCCLKDIV_MASK);
+
+	Reg |= ((u32)Divisor << XEMACPS_NWCFG_MDC_SHIFT_MASK);
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_NWCFG_OFFSET, Reg);
+}
+
+
+/*****************************************************************************/
+/**
+* Read the current value of the PHY register indicated by the PhyAddress and
+* the RegisterNum parameters. The MAC provides the driver with the ability to
+* talk to a PHY that adheres to the Media Independent Interface (MII) as
+* defined in the IEEE 802.3 standard.
+*
+* Prior to PHY access with this function, the user should have setup the MDIO
+* clock with XEmacPs_SetMdioDivisor().
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param PhyAddress is the address of the PHY to be read (supports multiple
+*        PHYs)
+* @param RegisterNum is the register number, 0-31, of the specific PHY register
+*        to read
+* @param PhyDataPtr is an output parameter, and points to a 16-bit buffer into
+*        which the current value of the register will be copied.
+*
+* @return
+*
+* - XST_SUCCESS if the PHY was read from successfully
+* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
+*
+* @note
+*
+* This function is not thread-safe. The user must provide mutually exclusive
+* access to this function if there are to be multiple threads that can call it.
+*
+* There is the possibility that this function will not return if the hardware
+* is broken (i.e., it never sets the status bit indicating that the read is
+* done). If this is of concern to the user, the user should provide a mechanism
+* suitable to their needs for recovery.
+*
+* For the duration of this function, all host interface reads and writes are
+* blocked to the current XEmacPs instance.
+*
+******************************************************************************/
+LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
+		     u32 RegisterNum, u16 *PhyDataPtr)
+{
+	u32 Mgtcr;
+	volatile u32 Ipisr;
+	u32 IpReadTemp;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/* Make sure no other PHY operation is currently in progress */
+	if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWSR_OFFSET) &
+	      XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
+		Status = (LONG)(XST_EMAC_MII_BUSY);
+	} else {
+
+	/* Construct Mgtcr mask for the operation */
+	Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_R_MASK |
+			(PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
+			(RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK);
+
+	/* Write Mgtcr and wait for completion */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
+
+	do {
+		Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XEMACPS_NWSR_OFFSET);
+			IpReadTemp = Ipisr;
+		} while ((IpReadTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
+
+	/* Read data */
+		*PhyDataPtr = (u16)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_PHYMNTNC_OFFSET);
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+* Write data to the specified PHY register. The Ethernet driver does not
+* require the device to be stopped before writing to the PHY.  Although it is
+* probably a good idea to stop the device, it is the responsibility of the
+* application to deem this necessary. The MAC provides the driver with the
+* ability to talk to a PHY that adheres to the Media Independent Interface
+* (MII) as defined in the IEEE 802.3 standard.
+*
+* Prior to PHY access with this function, the user should have setup the MDIO
+* clock with XEmacPs_SetMdioDivisor().
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param PhyAddress is the address of the PHY to be written (supports multiple
+*        PHYs)
+* @param RegisterNum is the register number, 0-31, of the specific PHY register
+*        to write
+* @param PhyData is the 16-bit value that will be written to the register
+*
+* @return
+*
+* - XST_SUCCESS if the PHY was written to successfully. Since there is no error
+*   status from the MAC on a write, the user should read the PHY to verify the
+*   write was successful.
+* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
+*
+* @note
+*
+* This function is not thread-safe. The user must provide mutually exclusive
+* access to this function if there are to be multiple threads that can call it.
+*
+* There is the possibility that this function will not return if the hardware
+* is broken (i.e., it never sets the status bit indicating that the write is
+* done). If this is of concern to the user, the user should provide a mechanism
+* suitable to their needs for recovery.
+*
+* For the duration of this function, all host interface reads and writes are
+* blocked to the current XEmacPs instance.
+*
+******************************************************************************/
+LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
+		      u32 RegisterNum, u16 PhyData)
+{
+	u32 Mgtcr;
+	volatile u32 Ipisr;
+	u32 IpWriteTemp;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/* Make sure no other PHY operation is currently in progress */
+	if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWSR_OFFSET) &
+	      XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
+		Status = (LONG)(XST_EMAC_MII_BUSY);
+	} else {
+	/* Construct Mgtcr mask for the operation */
+	Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_W_MASK |
+			(PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
+			(RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK) | (u32)PhyData;
+
+	/* Write Mgtcr and wait for completion */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
+
+	do {
+		Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XEMACPS_NWSR_OFFSET);
+				IpWriteTemp = Ipisr;
+		} while ((IpWriteTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+* API to update the Burst length in the DMACR register.
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param BLength is the length in bytes for the dma burst.
+*
+* @return None
+*
+******************************************************************************/
+void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength)
+{
+	u32 Reg;
+	u32 RegUpdateVal;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid((BLength == XEMACPS_SINGLE_BURST) ||
+					(BLength == XEMACPS_4BYTE_BURST) ||
+					(BLength == XEMACPS_8BYTE_BURST) ||
+					(BLength == XEMACPS_16BYTE_BURST));
+
+	switch (BLength) {
+		case XEMACPS_SINGLE_BURST:
+			RegUpdateVal = XEMACPS_DMACR_SINGLE_AHB_BURST;
+			break;
+
+		case XEMACPS_4BYTE_BURST:
+			RegUpdateVal = XEMACPS_DMACR_INCR4_AHB_BURST;
+			break;
+
+		case XEMACPS_8BYTE_BURST:
+			RegUpdateVal = XEMACPS_DMACR_INCR8_AHB_BURST;
+			break;
+
+		case XEMACPS_16BYTE_BURST:
+			RegUpdateVal = XEMACPS_DMACR_INCR16_AHB_BURST;
+			break;
+
+		default:
+			RegUpdateVal = 0x00000000U;
+			break;
+	}
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XEMACPS_DMACR_OFFSET);
+
+	Reg &= (u32)(~XEMACPS_DMACR_BLENGTH_MASK);
+	Reg |= RegUpdateVal;
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
+																	Reg);
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_g.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..081f9ed53da64ed304969493a18dcdb256468bad
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xemacps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_ETHERNET_0_DEVICE_ID,
+		XPAR_PS7_ETHERNET_0_BASEADDR
+	}
+};
+
+
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_hw.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_hw.c
new file mode 100644
index 0000000000000000000000000000000000000000..daba38397018c1235343256f1765568f3263ef2e
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_hw.c
@@ -0,0 +1,123 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_hw.c
+* @addtogroup emacps_v3_1
+* @{
+*
+* This file contains the implementation of the ethernet interface reset sequence
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.05a kpc  28/06/13 First release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps_hw.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given emacps interface by
+* configuring the appropriate control bits in the emacps specifc registers.
+* the emacps reset squence involves the following steps
+*	Disable all the interuupts
+*	Clear the status registers
+*	Disable Rx and Tx engines
+*	Update the Tx and Rx descriptor queue registers with reset values
+*	Update the other relevant control registers with reset value
+*
+* @param   BaseAddress of the interface
+*
+* @return N/A
+*
+* @note
+* This function will not modify the slcr registers that are relavant for
+* emacps controller
+******************************************************************************/
+void XEmacPs_ResetHw(u32 BaseAddr)
+{
+	u32 RegVal;
+
+	/* Disable the interrupts  */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_IDR_OFFSET,0x0U);
+
+	/* Stop transmission,disable loopback and Stop tx and Rx engines */
+	RegVal = XEmacPs_ReadReg(BaseAddr,XEMACPS_NWCTRL_OFFSET);
+	RegVal &= ~((u32)XEMACPS_NWCTRL_TXEN_MASK|
+				(u32)XEMACPS_NWCTRL_RXEN_MASK|
+				(u32)XEMACPS_NWCTRL_HALTTX_MASK|
+				(u32)XEMACPS_NWCTRL_LOOPEN_MASK);
+	/* Clear the statistic registers, flush the packets in DPRAM*/
+	RegVal |= (XEMACPS_NWCTRL_STATCLR_MASK|
+				XEMACPS_NWCTRL_FLUSH_DPRAM_MASK);
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCTRL_OFFSET,RegVal);
+	/* Clear the interrupt status */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_ISR_OFFSET,XEMACPS_IXR_ALL_MASK);
+	/* Clear the tx status */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_TXSR_OFFSET,(XEMACPS_TXSR_ERROR_MASK|
+									(u32)XEMACPS_TXSR_TXCOMPL_MASK|
+									(u32)XEMACPS_TXSR_TXGO_MASK));
+	/* Clear the rx status */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_RXSR_OFFSET,
+								XEMACPS_RXSR_FRAMERX_MASK);
+	/* Clear the tx base address */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_TXQBASE_OFFSET,0x0U);
+	/* Clear the rx base address */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_RXQBASE_OFFSET,0x0U);
+	/* Update the network config register with reset value */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCFG_OFFSET,XEMACPS_NWCFG_RESET_MASK);
+	/* Update the hash address registers with reset value */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHL_OFFSET,0x0U);
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHH_OFFSET,0x0U);
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..953cc6265bfbc92359b6639d5d5d833663a287af
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_hw.h
@@ -0,0 +1,656 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_hw.h
+* @addtogroup emacps_v3_1
+* @{
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
+* High-level driver functions are defined in xemacps.h.
+*
+* @note
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release.
+* 1.02a asa  11/05/12 Added hash defines for DMACR burst length configuration.
+* 1.05a kpc  28/06/13 Added XEmacPs_ResetHw function prototype
+* 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+*					  to 0x1fff. This fixes the CR#744902.
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
+* 3.0   kvn  12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
+*					  XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
+* 3.0  kpc   1/23/15  Corrected the extended descriptor macro values.
+* 3.0  kvn   02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.0  hk   03/18/15 Added support for jumbo frames.
+*                    Remove "used bit set" from TX error interrupt masks.
+* 3.1  hk   08/10/15 Update upper 32 bit tx and rx queue ptr register offsets.
+* 3.2   hk   02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XEMACPS_HW_H		/* prevent circular inclusions */
+#define XEMACPS_HW_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+#define XEMACPS_MAX_MAC_ADDR     4U   /**< Maxmum number of mac address
+                                           supported */
+#define XEMACPS_MAX_TYPE_ID      4U   /**< Maxmum number of type id supported */
+
+#ifdef __aarch64__
+#define XEMACPS_BD_ALIGNMENT     64U   /**< Minimum buffer descriptor alignment
+                                           on the local bus */
+#else
+
+#define XEMACPS_BD_ALIGNMENT     4U   /**< Minimum buffer descriptor alignment
+                                           on the local bus */
+#endif
+#define XEMACPS_RX_BUF_ALIGNMENT 4U   /**< Minimum buffer alignment when using
+                                           options that impose alignment
+                                           restrictions on the buffer data on
+                                           the local bus */
+
+/** @name Direction identifiers
+ *
+ *  These are used by several functions and callbacks that need
+ *  to specify whether an operation specifies a send or receive channel.
+ * @{
+ */
+#define XEMACPS_SEND        1U	      /**< send direction */
+#define XEMACPS_RECV        2U	      /**< receive direction */
+/*@}*/
+
+/**  @name MDC clock division
+ *  currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
+ * @{
+ */
+typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
+	MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
+} XEmacPs_MdcDiv;
+
+/*@}*/
+
+#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
+                                       bytes, 64, 128, ... 10240 */
+#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U
+
+#define XEMACPS_RX_BUF_UNIT   64U /**< Number of receive buffer bytes as a
+                                       unit, this is HW setup */
+
+#define XEMACPS_MAX_RXBD     128U /**< Size of RX buffer descriptor queues */
+#define XEMACPS_MAX_TXBD     128U /**< Size of TX buffer descriptor queues */
+
+#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */
+
+/* Register offset definitions. Unless otherwise noted, register access is
+ * 32 bit. Names are self explained here.
+ */
+
+#define XEMACPS_NWCTRL_OFFSET        0x00000000U /**< Network Control reg */
+#define XEMACPS_NWCFG_OFFSET         0x00000004U /**< Network Config reg */
+#define XEMACPS_NWSR_OFFSET          0x00000008U /**< Network Status reg */
+
+#define XEMACPS_DMACR_OFFSET         0x00000010U /**< DMA Control reg */
+#define XEMACPS_TXSR_OFFSET          0x00000014U /**< TX Status reg */
+#define XEMACPS_RXQBASE_OFFSET       0x00000018U /**< RX Q Base address reg */
+#define XEMACPS_TXQBASE_OFFSET       0x0000001CU /**< TX Q Base address reg */
+#define XEMACPS_RXSR_OFFSET          0x00000020U /**< RX Status reg */
+
+#define XEMACPS_ISR_OFFSET           0x00000024U /**< Interrupt Status reg */
+#define XEMACPS_IER_OFFSET           0x00000028U /**< Interrupt Enable reg */
+#define XEMACPS_IDR_OFFSET           0x0000002CU /**< Interrupt Disable reg */
+#define XEMACPS_IMR_OFFSET           0x00000030U /**< Interrupt Mask reg */
+
+#define XEMACPS_PHYMNTNC_OFFSET      0x00000034U /**< Phy Maintaince reg */
+#define XEMACPS_RXPAUSE_OFFSET       0x00000038U /**< RX Pause Time reg */
+#define XEMACPS_TXPAUSE_OFFSET       0x0000003CU /**< TX Pause Time reg */
+
+#define XEMACPS_JUMBOMAXLEN_OFFSET   0x00000048U /**< Jumbo max length reg */
+
+#define XEMACPS_HASHL_OFFSET         0x00000080U /**< Hash Low address reg */
+#define XEMACPS_HASHH_OFFSET         0x00000084U /**< Hash High address reg */
+
+#define XEMACPS_LADDR1L_OFFSET       0x00000088U /**< Specific1 addr low reg */
+#define XEMACPS_LADDR1H_OFFSET       0x0000008CU /**< Specific1 addr high reg */
+#define XEMACPS_LADDR2L_OFFSET       0x00000090U /**< Specific2 addr low reg */
+#define XEMACPS_LADDR2H_OFFSET       0x00000094U /**< Specific2 addr high reg */
+#define XEMACPS_LADDR3L_OFFSET       0x00000098U /**< Specific3 addr low reg */
+#define XEMACPS_LADDR3H_OFFSET       0x0000009CU /**< Specific3 addr high reg */
+#define XEMACPS_LADDR4L_OFFSET       0x000000A0U /**< Specific4 addr low reg */
+#define XEMACPS_LADDR4H_OFFSET       0x000000A4U /**< Specific4 addr high reg */
+
+#define XEMACPS_MATCH1_OFFSET        0x000000A8U /**< Type ID1 Match reg */
+#define XEMACPS_MATCH2_OFFSET        0x000000ACU /**< Type ID2 Match reg */
+#define XEMACPS_MATCH3_OFFSET        0x000000B0U /**< Type ID3 Match reg */
+#define XEMACPS_MATCH4_OFFSET        0x000000B4U /**< Type ID4 Match reg */
+
+#define XEMACPS_STRETCH_OFFSET       0x000000BCU /**< IPG Stretch reg */
+
+#define XEMACPS_OCTTXL_OFFSET        0x00000100U /**< Octects transmitted Low
+                                                      reg */
+#define XEMACPS_OCTTXH_OFFSET        0x00000104U /**< Octects transmitted High
+                                                      reg */
+
+#define XEMACPS_TXCNT_OFFSET         0x00000108U /**< Error-free Frmaes
+                                                      transmitted counter */
+#define XEMACPS_TXBCCNT_OFFSET       0x0000010CU /**< Error-free Broadcast
+                                                      Frames counter*/
+#define XEMACPS_TXMCCNT_OFFSET       0x00000110U /**< Error-free Multicast
+                                                      Frame counter */
+#define XEMACPS_TXPAUSECNT_OFFSET    0x00000114U /**< Pause Frames Transmitted
+                                                      Counter */
+#define XEMACPS_TX64CNT_OFFSET       0x00000118U /**< Error-free 64 byte Frames
+                                                      Transmitted counter */
+#define XEMACPS_TX65CNT_OFFSET       0x0000011CU /**< Error-free 65-127 byte
+                                                      Frames Transmitted
+                                                      counter */
+#define XEMACPS_TX128CNT_OFFSET      0x00000120U /**< Error-free 128-255 byte
+                                                      Frames Transmitted
+                                                      counter*/
+#define XEMACPS_TX256CNT_OFFSET      0x00000124U /**< Error-free 256-511 byte
+                                                      Frames transmitted
+                                                      counter */
+#define XEMACPS_TX512CNT_OFFSET      0x00000128U /**< Error-free 512-1023 byte
+                                                      Frames transmitted
+                                                      counter */
+#define XEMACPS_TX1024CNT_OFFSET     0x0000012CU /**< Error-free 1024-1518 byte
+                                                      Frames transmitted
+                                                      counter */
+#define XEMACPS_TX1519CNT_OFFSET     0x00000130U /**< Error-free larger than
+                                                      1519 byte Frames
+                                                      transmitted counter */
+#define XEMACPS_TXURUNCNT_OFFSET     0x00000134U /**< TX under run error
+                                                      counter */
+
+#define XEMACPS_SNGLCOLLCNT_OFFSET   0x00000138U /**< Single Collision Frame
+                                                      Counter */
+#define XEMACPS_MULTICOLLCNT_OFFSET  0x0000013CU /**< Multiple Collision Frame
+                                                      Counter */
+#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame
+                                                      Counter */
+#define XEMACPS_LATECOLLCNT_OFFSET   0x00000144U /**< Late Collision Frame
+                                                      Counter */
+#define XEMACPS_TXDEFERCNT_OFFSET    0x00000148U /**< Deferred Transmission
+                                                      Frame Counter */
+#define XEMACPS_TXCSENSECNT_OFFSET   0x0000014CU /**< Transmit Carrier Sense
+                                                      Error Counter */
+
+#define XEMACPS_OCTRXL_OFFSET        0x00000150U /**< Octects Received register
+                                                      Low */
+#define XEMACPS_OCTRXH_OFFSET        0x00000154U /**< Octects Received register
+                                                      High */
+
+#define XEMACPS_RXCNT_OFFSET         0x00000158U /**< Error-free Frames
+                                                      Received Counter */
+#define XEMACPS_RXBROADCNT_OFFSET    0x0000015CU /**< Error-free Broadcast
+                                                      Frames Received Counter */
+#define XEMACPS_RXMULTICNT_OFFSET    0x00000160U /**< Error-free Multicast
+                                                      Frames Received Counter */
+#define XEMACPS_RXPAUSECNT_OFFSET    0x00000164U /**< Pause Frames
+                                                      Received Counter */
+#define XEMACPS_RX64CNT_OFFSET       0x00000168U /**< Error-free 64 byte Frames
+                                                      Received Counter */
+#define XEMACPS_RX65CNT_OFFSET       0x0000016CU /**< Error-free 65-127 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX128CNT_OFFSET      0x00000170U /**< Error-free 128-255 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX256CNT_OFFSET      0x00000174U /**< Error-free 256-512 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX512CNT_OFFSET      0x00000178U /**< Error-free 512-1023 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX1024CNT_OFFSET     0x0000017CU /**< Error-free 1024-1518 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX1519CNT_OFFSET     0x00000180U /**< Error-free 1519-max byte
+                                                      Frames Received Counter */
+#define XEMACPS_RXUNDRCNT_OFFSET     0x00000184U /**< Undersize Frames Received
+                                                      Counter */
+#define XEMACPS_RXOVRCNT_OFFSET      0x00000188U /**< Oversize Frames Received
+                                                      Counter */
+#define XEMACPS_RXJABCNT_OFFSET      0x0000018CU /**< Jabbers Received
+                                                      Counter */
+#define XEMACPS_RXFCSCNT_OFFSET      0x00000190U /**< Frame Check Sequence
+                                                      Error Counter */
+#define XEMACPS_RXLENGTHCNT_OFFSET   0x00000194U /**< Length Field Error
+                                                      Counter */
+#define XEMACPS_RXSYMBCNT_OFFSET     0x00000198U /**< Symbol Error Counter */
+#define XEMACPS_RXALIGNCNT_OFFSET    0x0000019CU /**< Alignment Error Counter */
+#define XEMACPS_RXRESERRCNT_OFFSET   0x000001A0U /**< Receive Resource Error
+                                                      Counter */
+#define XEMACPS_RXORCNT_OFFSET       0x000001A4U /**< Receive Overrun Counter */
+#define XEMACPS_RXIPCCNT_OFFSET      0x000001A8U /**< IP header Checksum Error
+                                                      Counter */
+#define XEMACPS_RXTCPCCNT_OFFSET     0x000001ACU /**< TCP Checksum Error
+                                                      Counter */
+#define XEMACPS_RXUDPCCNT_OFFSET     0x000001B0U /**< UDP Checksum Error
+                                                      Counter */
+#define XEMACPS_LAST_OFFSET          0x000001B4U /**< Last statistic counter
+						      offset, for clearing */
+
+#define XEMACPS_1588_SEC_OFFSET      0x000001D0U /**< 1588 second counter */
+#define XEMACPS_1588_NANOSEC_OFFSET  0x000001D4U /**< 1588 nanosecond counter */
+#define XEMACPS_1588_ADJ_OFFSET      0x000001D8U /**< 1588 nanosecond
+						      adjustment counter */
+#define XEMACPS_1588_INC_OFFSET      0x000001DCU /**< 1588 nanosecond
+						      increment counter */
+#define XEMACPS_PTP_TXSEC_OFFSET     0x000001E0U /**< 1588 PTP transmit second
+						      counter */
+#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
+						      nanosecond counter */
+#define XEMACPS_PTP_RXSEC_OFFSET     0x000001E8U /**< 1588 PTP receive second
+						      counter */
+#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
+						      nanosecond counter */
+#define XEMACPS_PTPP_TXSEC_OFFSET    0x000001F0U /**< 1588 PTP peer transmit
+						      second counter */
+#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
+						      nanosecond counter */
+#define XEMACPS_PTPP_RXSEC_OFFSET    0x000001F8U /**< 1588 PTP peer receive
+						      second counter */
+#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
+						      nanosecond counter */
+
+#define XEMACPS_INTQ1_STS_OFFSET     0x00000400U /**< Interrupt Q1 Status
+							reg */
+#define XEMACPS_TXQ1BASE_OFFSET	     0x00000440U /**< TX Q1 Base address
+							reg */
+#define XEMACPS_RXQ1BASE_OFFSET	     0x00000480U /**< RX Q1 Base address
+							reg */
+#define XEMACPS_MSBBUF_TXQBASE_OFFSET  0x000004C8U /**< MSB Buffer TX Q Base
+							reg */
+#define XEMACPS_MSBBUF_RXQBASE_OFFSET  0x000004D4U /**< MSB Buffer RX Q Base
+							reg */
+#define XEMACPS_INTQ1_IER_OFFSET     0x00000600U /**< Interrupt Q1 Enable
+							reg */
+#define XEMACPS_INTQ1_IDR_OFFSET     0x00000620U /**< Interrupt Q1 Disable
+							reg */
+#define XEMACPS_INTQ1_IMR_OFFSET     0x00000640U /**< Interrupt Q1 Mask
+							reg */
+
+/* Define some bit positions for registers. */
+
+/** @name network control register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK	0x00040000U /**< Flush a packet from
+							Rx SRAM */
+#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
+                                                         pause frame */
+#define XEMACPS_NWCTRL_PAUSETX_MASK     0x00000800U /**< Transmit pause frame */
+#define XEMACPS_NWCTRL_HALTTX_MASK      0x00000400U /**< Halt transmission
+                                                         after current frame */
+#define XEMACPS_NWCTRL_STARTTX_MASK     0x00000200U /**< Start tx (tx_go) */
+
+#define XEMACPS_NWCTRL_STATWEN_MASK     0x00000080U /**< Enable writing to
+                                                         stat counters */
+#define XEMACPS_NWCTRL_STATINC_MASK     0x00000040U /**< Increment statistic
+                                                         registers */
+#define XEMACPS_NWCTRL_STATCLR_MASK     0x00000020U /**< Clear statistic
+                                                         registers */
+#define XEMACPS_NWCTRL_MDEN_MASK        0x00000010U /**< Enable MDIO port */
+#define XEMACPS_NWCTRL_TXEN_MASK        0x00000008U /**< Enable transmit */
+#define XEMACPS_NWCTRL_RXEN_MASK        0x00000004U /**< Enable receive */
+#define XEMACPS_NWCTRL_LOOPEN_MASK      0x00000002U /**< local loopback */
+/*@}*/
+
+/** @name network configuration register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of
+                                                        non-standard preamble */
+#define XEMACPS_NWCFG_IPDSTRETCH_MASK  0x10000000U /**< enable transmit IPG */
+#define XEMACPS_NWCFG_SGMIIEN_MASK     0x08000000U /**< SGMII Enable */
+#define XEMACPS_NWCFG_FCSIGNORE_MASK   0x04000000U /**< disable rejection of
+                                                        FCS error */
+#define XEMACPS_NWCFG_HDRXEN_MASK      0x02000000U /**< RX half duplex */
+#define XEMACPS_NWCFG_RXCHKSUMEN_MASK  0x01000000U /**< enable RX checksum
+                                                        offload */
+#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
+                                                        Frames to memory */
+#define XEMACPS_NWCFG_DWIDTH_64_MASK   0x00200000U /**< 64 bit Data bus width */
+#define XEMACPS_NWCFG_MDC_SHIFT_MASK   18U	   /**< shift bits for MDC */
+#define XEMACPS_NWCFG_MDCCLKDIV_MASK   0x001C0000U /**< MDC Mask PCLK divisor */
+#define XEMACPS_NWCFG_FCSREM_MASK      0x00020000U /**< Discard FCS from
+                                                        received frames */
+#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
+/**< RX length error discard */
+#define XEMACPS_NWCFG_RXOFFS_MASK      0x0000C000U /**< RX buffer offset */
+#define XEMACPS_NWCFG_PAUSEEN_MASK     0x00002000U /**< Enable pause RX */
+#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
+#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
+/**< External address match enable */
+#define XEMACPS_NWCFG_PCSSEL_MASK      0x00000800U /**< PCS Select */
+#define XEMACPS_NWCFG_1000_MASK        0x00000400U /**< 1000 Mbps */
+#define XEMACPS_NWCFG_1536RXEN_MASK    0x00000100U /**< Enable 1536 byte
+                                                        frames reception */
+#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash
+                                                        frames */
+#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash
+                                                        frames */
+#define XEMACPS_NWCFG_BCASTDI_MASK     0x00000020U /**< Do not receive
+                                                        broadcast frames */
+#define XEMACPS_NWCFG_COPYALLEN_MASK   0x00000010U /**< Copy all frames */
+#define XEMACPS_NWCFG_JUMBO_MASK       0x00000008U /**< Jumbo frames */
+#define XEMACPS_NWCFG_NVLANDISC_MASK   0x00000004U /**< Receive only VLAN
+                                                        frames */
+#define XEMACPS_NWCFG_FDEN_MASK        0x00000002U/**< full duplex */
+#define XEMACPS_NWCFG_100_MASK         0x00000001U /**< 100 Mbps */
+#define XEMACPS_NWCFG_RESET_MASK       0x00080000U/**< reset value */
+/*@}*/
+
+/** @name network status register bit definitaions
+ * @{
+ */
+#define XEMACPS_NWSR_MDIOIDLE_MASK     0x00000004U /**< PHY management idle */
+#define XEMACPS_NWSR_MDIO_MASK         0x00000002U /**< Status of mdio_in */
+/*@}*/
+
+
+/** @name MAC address register word 1 mask
+ * @{
+ */
+#define XEMACPS_LADDR_MACH_MASK        0x0000FFFFU /**< Address bits[47:32]
+                                                      bit[31:0] are in BOTTOM */
+/*@}*/
+
+
+/** @name DMA control register bit definitions
+ * @{
+ */
+#define XEMACPS_DMACR_ADDR_WIDTH_64		0x40000000U /**< 64 bit address bus */
+#define XEMACPS_DMACR_TXEXTEND_MASK		0x20000000U /**< Tx Extended desc mode */
+#define XEMACPS_DMACR_RXEXTEND_MASK		0x10000000U /**< Rx Extended desc mode */
+#define XEMACPS_DMACR_RXBUF_MASK		0x00FF0000U /**< Mask bit for RX buffer
+													size */
+#define XEMACPS_DMACR_RXBUF_SHIFT 		16U	/**< Shift bit for RX buffer
+												size */
+#define XEMACPS_DMACR_TCPCKSUM_MASK		0x00000800U /**< enable/disable TX
+													    checksum offload */
+#define XEMACPS_DMACR_TXSIZE_MASK		0x00000400U /**< TX buffer memory size */
+#define XEMACPS_DMACR_RXSIZE_MASK		0x00000300U /**< RX buffer memory size */
+#define XEMACPS_DMACR_ENDIAN_MASK		0x00000080U /**< endian configuration */
+#define XEMACPS_DMACR_BLENGTH_MASK		0x0000001FU /**< buffer burst length */
+#define XEMACPS_DMACR_SINGLE_AHB_BURST	0x00000001U /**< single AHB bursts */
+#define XEMACPS_DMACR_INCR4_AHB_BURST	0x00000004U /**< 4 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR8_AHB_BURST	0x00000008U /**< 8 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR16_AHB_BURST	0x00000010U /**< 16 bytes AHB bursts */
+/*@}*/
+
+/** @name transmit status register bit definitions
+ * @{
+ */
+#define XEMACPS_TXSR_HRESPNOK_MASK    0x00000100U /**< Transmit hresp not OK */
+#define XEMACPS_TXSR_URUN_MASK        0x00000040U /**< Transmit underrun */
+#define XEMACPS_TXSR_TXCOMPL_MASK     0x00000020U /**< Transmit completed OK */
+#define XEMACPS_TXSR_BUFEXH_MASK      0x00000010U /**< Transmit buffs exhausted
+                                                       mid frame */
+#define XEMACPS_TXSR_TXGO_MASK        0x00000008U /**< Status of go flag */
+#define XEMACPS_TXSR_RXOVR_MASK       0x00000004U /**< Retry limit exceeded */
+#define XEMACPS_TXSR_FRAMERX_MASK     0x00000002U /**< Collision tx frame */
+#define XEMACPS_TXSR_USEDREAD_MASK    0x00000001U /**< TX buffer used bit set */
+
+#define XEMACPS_TXSR_ERROR_MASK      ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \
+                                       (u32)XEMACPS_TXSR_URUN_MASK | \
+                                       (u32)XEMACPS_TXSR_BUFEXH_MASK | \
+                                       (u32)XEMACPS_TXSR_RXOVR_MASK | \
+                                       (u32)XEMACPS_TXSR_FRAMERX_MASK | \
+                                       (u32)XEMACPS_TXSR_USEDREAD_MASK)
+/*@}*/
+
+/**
+ * @name receive status register bit definitions
+ * @{
+ */
+#define XEMACPS_RXSR_HRESPNOK_MASK    0x00000008U /**< Receive hresp not OK */
+#define XEMACPS_RXSR_RXOVR_MASK       0x00000004U /**< Receive overrun */
+#define XEMACPS_RXSR_FRAMERX_MASK     0x00000002U /**< Frame received OK */
+#define XEMACPS_RXSR_BUFFNA_MASK      0x00000001U /**< RX buffer used bit set */
+
+#define XEMACPS_RXSR_ERROR_MASK      ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \
+                                       (u32)XEMACPS_RXSR_RXOVR_MASK | \
+                                       (u32)XEMACPS_RXSR_BUFFNA_MASK)
+/*@}*/
+
+/**
+ * @name Interrupt Q1 status register bit definitions
+ * @{
+ */
+#define XEMACPS_INTQ1SR_TXCOMPL_MASK	0x00000080U /**< Transmit completed OK */
+#define XEMACPS_INTQ1SR_TXERR_MASK	0x00000040U /**< Transmit AMBA Error */
+
+#define XEMACPS_INTQ1_IXR_ALL_MASK	((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
+					 (u32)XEMACPS_INTQ1SR_TXERR_MASK)
+
+/*@}*/
+
+/**
+ * @name interrupts bit definitions
+ * Bits definitions are same in XEMACPS_ISR_OFFSET,
+ * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
+ * @{
+ */
+#define XEMACPS_IXR_PTPPSTX_MASK    0x02000000U /**< PTP Psync transmitted */
+#define XEMACPS_IXR_PTPPDRTX_MASK   0x01000000U /**< PTP Pdelay_req
+						     transmitted */
+#define XEMACPS_IXR_PTPSTX_MASK     0x00800000U /**< PTP Sync transmitted */
+#define XEMACPS_IXR_PTPDRTX_MASK    0x00400000U /**< PTP Delay_req transmitted
+						*/
+#define XEMACPS_IXR_PTPPSRX_MASK    0x00200000U /**< PTP Psync received */
+#define XEMACPS_IXR_PTPPDRRX_MASK   0x00100000U /**< PTP Pdelay_req received */
+#define XEMACPS_IXR_PTPSRX_MASK     0x00080000U /**< PTP Sync received */
+#define XEMACPS_IXR_PTPDRRX_MASK    0x00040000U /**< PTP Delay_req received */
+#define XEMACPS_IXR_PAUSETX_MASK    0x00004000U	/**< Pause frame transmitted */
+#define XEMACPS_IXR_PAUSEZERO_MASK  0x00002000U	/**< Pause time has reached
+                                                     zero */
+#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U	/**< Pause frame received */
+#define XEMACPS_IXR_HRESPNOK_MASK   0x00000800U	/**< hresp not ok */
+#define XEMACPS_IXR_RXOVR_MASK      0x00000400U	/**< Receive overrun occurred */
+#define XEMACPS_IXR_TXCOMPL_MASK    0x00000080U	/**< Frame transmitted ok */
+#define XEMACPS_IXR_TXEXH_MASK      0x00000040U	/**< Transmit err occurred or
+                                                     no buffers*/
+#define XEMACPS_IXR_RETRY_MASK      0x00000020U	/**< Retry limit exceeded */
+#define XEMACPS_IXR_URUN_MASK       0x00000010U	/**< Transmit underrun */
+#define XEMACPS_IXR_TXUSED_MASK     0x00000008U	/**< Tx buffer used bit read */
+#define XEMACPS_IXR_RXUSED_MASK     0x00000004U	/**< Rx buffer used bit read */
+#define XEMACPS_IXR_FRAMERX_MASK    0x00000002U	/**< Frame received ok */
+#define XEMACPS_IXR_MGMNT_MASK      0x00000001U	/**< PHY management complete */
+#define XEMACPS_IXR_ALL_MASK        0x00007FFFU	/**< Everything! */
+
+#define XEMACPS_IXR_TX_ERR_MASK    ((u32)XEMACPS_IXR_TXEXH_MASK |         \
+                                     (u32)XEMACPS_IXR_RETRY_MASK |         \
+                                     (u32)XEMACPS_IXR_URUN_MASK)
+
+
+#define XEMACPS_IXR_RX_ERR_MASK    ((u32)XEMACPS_IXR_HRESPNOK_MASK |      \
+                                     (u32)XEMACPS_IXR_RXUSED_MASK |        \
+                                     (u32)XEMACPS_IXR_RXOVR_MASK)
+
+/*@}*/
+
+/** @name PHY Maintenance bit definitions
+ * @{
+ */
+#define XEMACPS_PHYMNTNC_OP_MASK    0x40020000U	/**< operation mask bits */
+#define XEMACPS_PHYMNTNC_OP_R_MASK  0x20000000U	/**< read operation */
+#define XEMACPS_PHYMNTNC_OP_W_MASK  0x10000000U	/**< write operation */
+#define XEMACPS_PHYMNTNC_ADDR_MASK  0x0F800000U	/**< Address bits */
+#define XEMACPS_PHYMNTNC_REG_MASK   0x007C0000U	/**< register bits */
+#define XEMACPS_PHYMNTNC_DATA_MASK  0x00000FFFU	/**< data bits */
+#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK   23U	/**< Shift bits for PHYAD */
+#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK   18U	/**< Shift bits for PHREG */
+/*@}*/
+
+/* Transmit buffer descriptor status words offset
+ * @{
+ */
+#define XEMACPS_BD_ADDR_OFFSET  0x00000000U /**< word 0/addr of BDs */
+#define XEMACPS_BD_STAT_OFFSET  0x00000004U /**< word 1/status of BDs */
+#define XEMACPS_BD_ADDR_HI_OFFSET  0x00000008U /**< word 2/addr of BDs */
+
+/*
+ * @}
+ */
+
+/* Transmit buffer descriptor status words bit positions.
+ * Transmit buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit address pointing to the location of
+ * the transmit data.
+ * The following register - word1, consists of various information to control
+ * the XEmacPs transmit process.  After transmit, this is updated with status
+ * information, whether the frame was transmitted OK or why it had failed.
+ * @{
+ */
+#define XEMACPS_TXBUF_USED_MASK  0x80000000U /**< Used bit. */
+#define XEMACPS_TXBUF_WRAP_MASK  0x40000000U /**< Wrap bit, last descriptor */
+#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
+#define XEMACPS_TXBUF_URUN_MASK  0x10000000U /**< Transmit underrun occurred */
+#define XEMACPS_TXBUF_EXH_MASK   0x08000000U /**< Buffers exhausted */
+#define XEMACPS_TXBUF_TCP_MASK   0x04000000U /**< Late collision. */
+#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
+#define XEMACPS_TXBUF_LAST_MASK  0x00008000U /**< Last buffer */
+#define XEMACPS_TXBUF_LEN_MASK   0x00003FFFU /**< Mask for length field */
+/*
+ * @}
+ */
+
+/* Receive buffer descriptor status words bit positions.
+ * Receive buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit word aligned address pointing to the
+ * address of the buffer. The lower two bits make up the wrap bit indicating
+ * the last descriptor and the ownership bit to indicate it has been used by
+ * the XEmacPs.
+ * The following register - word1, contains status information regarding why
+ * the frame was received (the filter match condition) as well as other
+ * useful info.
+ * @{
+ */
+#define XEMACPS_RXBUF_BCAST_MASK     0x80000000U /**< Broadcast frame */
+#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
+#define XEMACPS_RXBUF_UNIHASH_MASK   0x20000000U /**< Unicast hashed frame */
+#define XEMACPS_RXBUF_EXH_MASK       0x08000000U /**< buffer exhausted */
+#define XEMACPS_RXBUF_AMATCH_MASK    0x06000000U /**< Specific address
+                                                      matched */
+#define XEMACPS_RXBUF_IDFOUND_MASK   0x01000000U /**< Type ID matched */
+#define XEMACPS_RXBUF_IDMATCH_MASK   0x00C00000U /**< ID matched mask */
+#define XEMACPS_RXBUF_VLAN_MASK      0x00200000U /**< VLAN tagged */
+#define XEMACPS_RXBUF_PRI_MASK       0x00100000U /**< Priority tagged */
+#define XEMACPS_RXBUF_VPRI_MASK      0x000E0000U /**< Vlan priority */
+#define XEMACPS_RXBUF_CFI_MASK       0x00010000U /**< CFI frame */
+#define XEMACPS_RXBUF_EOF_MASK       0x00008000U /**< End of frame. */
+#define XEMACPS_RXBUF_SOF_MASK       0x00004000U /**< Start of frame. */
+#define XEMACPS_RXBUF_LEN_MASK       0x00001FFFU /**< Mask for length field */
+#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */
+
+#define XEMACPS_RXBUF_WRAP_MASK      0x00000002U /**< Wrap bit, last BD */
+#define XEMACPS_RXBUF_NEW_MASK       0x00000001U /**< Used bit.. */
+#define XEMACPS_RXBUF_ADD_MASK       0xFFFFFFFCU /**< Mask for address */
+/*
+ * @}
+ */
+
+/*
+ * Define appropriate I/O access method to memory mapped I/O or other
+ * interface if necessary.
+ */
+
+#define XEmacPs_In32  Xil_In32
+#define XEmacPs_Out32 Xil_Out32
+
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param    BaseAddress is the base address of the device
+* @param    RegOffset is the register offset to be read
+*
+* @return   The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
+    XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param    BaseAddress is the base address of the device
+* @param    RegOffset is the register offset to be written
+* @param    Data is the 32-bit value to write to the register
+*
+* @return   None.
+*
+* @note
+* C-style signature:
+*    void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
+*         u32 Data)
+*
+*****************************************************************************/
+#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
+    XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes *****************************/
+/*
+ * Perform reset operation to the emacps interface
+ */
+void XEmacPs_ResetHw(u32 BaseAddr);
+
+#ifdef __cplusplus
+  }
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_intr.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_intr.c
new file mode 100644
index 0000000000000000000000000000000000000000..59636c4efdd027fe4b4a3fdc492234c8fe680282
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_intr.c
@@ -0,0 +1,268 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_intr.c
+* @addtogroup emacps_v3_1
+* @{
+*
+* Functions in this file implement general purpose interrupt processing related
+* functionality. See xemacps.h for a detailed description of the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 1.03a asa  01/24/13 Fix for CR #692702 which updates error handling for
+*		      Rx errors. Under heavy Rx traffic, there will be a large
+*		      number of errors related to receive buffer not available.
+*		      Because of a HW bug (SI #692601), under such heavy errors,
+*		      the Rx data path can become unresponsive. To reduce the
+*		      probabilities for hitting this HW bug, the SW writes to
+*		      bit 18 to flush a packet from Rx DPRAM immediately. The
+*		      changes for it are done in the function
+*		      XEmacPs_IntrHandler.
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification
+*		       and 64-bit changes.
+* 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1   hk   07/27/15 Do not call error handler with '0' error code when
+*                     there is no error. CR# 869403
+* </pre>
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+ * Install an asynchronious handler function for the given HandlerType:
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param HandlerType indicates what interrupt handler type is.
+ *        XEMACPS_HANDLER_DMASEND, XEMACPS_HANDLER_DMARECV and
+ *        XEMACPS_HANDLER_ERROR.
+ * @param FuncPointer is the pointer to the callback function
+ * @param CallBackRef is the upper layer callback reference passed back when
+ *        when the callback function is invoked.
+ *
+ * @return
+ *
+ * None.
+ *
+ * @note
+ * There is no assert on the CallBackRef since the driver doesn't know what
+ * it is.
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
+			void *FuncPointer, void *CallBackRef)
+{
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(FuncPointer != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	switch (HandlerType) {
+	case XEMACPS_HANDLER_DMASEND:
+		Status = (LONG)(XST_SUCCESS);
+		InstancePtr->SendHandler = ((XEmacPs_Handler)(void *)FuncPointer);
+		InstancePtr->SendRef = CallBackRef;
+		break;
+	case XEMACPS_HANDLER_DMARECV:
+		Status = (LONG)(XST_SUCCESS);
+		InstancePtr->RecvHandler = ((XEmacPs_Handler)(void *)FuncPointer);
+		InstancePtr->RecvRef = CallBackRef;
+		break;
+	case XEMACPS_HANDLER_ERROR:
+		Status = (LONG)(XST_SUCCESS);
+		InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void *)FuncPointer);
+		InstancePtr->ErrorRef = CallBackRef;
+		break;
+	default:
+		Status = (LONG)(XST_INVALID_PARAM);
+		break;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+* Master interrupt handler for EMAC driver. This routine will query the
+* status of the device, bump statistics, and invoke user callbacks.
+*
+* This routine must be connected to an interrupt controller using OS/BSP
+* specific methods.
+*
+* @param XEmacPsPtr is a pointer to the XEMACPS instance that has caused the
+*        interrupt.
+*
+******************************************************************************/
+void XEmacPs_IntrHandler(void *XEmacPsPtr)
+{
+	u32 RegISR;
+	u32 RegSR;
+	u32 RegCtrl;
+	u32 RegQ1ISR = 0U;
+	XEmacPs *InstancePtr = (XEmacPs *) XEmacPsPtr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* This ISR will try to handle as many interrupts as it can in a single
+	 * call. However, in most of the places where the user's error handler
+         * is called, this ISR exits because it is expected that the user will
+         * reset the device in nearly all instances.
+	 */
+	RegISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_ISR_OFFSET);
+
+	/* Read Transmit Q1 ISR */
+
+	if (InstancePtr->Version > 2)
+		RegQ1ISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_INTQ1_STS_OFFSET);
+
+	/* Clear the interrupt status register */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
+			   RegISR);
+
+	/* Receive complete interrupt */
+	if ((RegISR & XEMACPS_IXR_FRAMERX_MASK) != 0x00000000U) {
+		/* Clear RX status register RX complete indication but preserve
+		 * error bits if there is any */
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_RXSR_OFFSET,
+				   ((u32)XEMACPS_RXSR_FRAMERX_MASK |
+				   (u32)XEMACPS_RXSR_BUFFNA_MASK));
+		InstancePtr->RecvHandler(InstancePtr->RecvRef);
+	}
+
+	/* Transmit Q1 complete interrupt */
+	if ((InstancePtr->Version > 2) &&
+			((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
+		/* Clear TX status register TX complete indication but preserve
+		 * error bits if there is any */
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_INTQ1_STS_OFFSET,
+				   XEMACPS_INTQ1SR_TXCOMPL_MASK);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_TXSR_OFFSET,
+				   ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
+				   (u32)XEMACPS_TXSR_USEDREAD_MASK));
+		InstancePtr->SendHandler(InstancePtr->SendRef);
+	}
+
+	/* Transmit complete interrupt */
+	if ((RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U) {
+		/* Clear TX status register TX complete indication but preserve
+		 * error bits if there is any */
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_TXSR_OFFSET,
+				   ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
+				   (u32)XEMACPS_TXSR_USEDREAD_MASK));
+		InstancePtr->SendHandler(InstancePtr->SendRef);
+	}
+
+	/* Receive error conditions interrupt */
+	if ((RegISR & XEMACPS_IXR_RX_ERR_MASK) != 0x00000000U) {
+		/* Clear RX status register */
+		RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XEMACPS_RXSR_OFFSET);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_RXSR_OFFSET, RegSR);
+
+		/* Fix for CR # 692702. Write to bit 18 of net_ctrl
+		 * register to flush a packet out of Rx SRAM upon
+		 * an error for receive buffer not available. */
+		if ((RegISR & XEMACPS_IXR_RXUSED_MASK) != 0x00000000U) {
+			RegCtrl =
+			XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XEMACPS_NWCTRL_OFFSET);
+			RegCtrl |= (u32)XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
+			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET, RegCtrl);
+		}
+
+		if(RegSR != 0) {
+			InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
+						XEMACPS_RECV, RegSR);
+		}
+	}
+
+        /* When XEMACPS_IXR_TXCOMPL_MASK is flaged, XEMACPS_IXR_TXUSED_MASK
+         * will be asserted the same time.
+         * Have to distinguish this bit to handle the real error condition.
+         */
+	/* Transmit Q1 error conditions interrupt */
+        if ((InstancePtr->Version > 2) &&
+			((RegQ1ISR & XEMACPS_INTQ1SR_TXERR_MASK) != 0x00000000U) &&
+            ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
+			/* Clear Interrupt Q1 status register */
+			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_INTQ1_STS_OFFSET, RegQ1ISR);
+			InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
+					  RegQ1ISR);
+	   }
+
+	/* Transmit error conditions interrupt */
+        if (((RegISR & XEMACPS_IXR_TX_ERR_MASK) != 0x00000000U) &&
+            (!(RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U)) {
+		/* Clear TX status register */
+		RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XEMACPS_TXSR_OFFSET);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_TXSR_OFFSET, RegSR);
+		InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
+					  RegSR);
+	}
+
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_sinit.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..1bc5b3b196d47bd72ae94b9002e9c97bd902d3b1
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/emacps_v3_4/src/xemacps_sinit.c
@@ -0,0 +1,97 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_sinit.c
+* @addtogroup emacps_v3_1
+* @{
+*
+* This file contains lookup method by device ID when success, it returns
+* pointer to config table to be used to initialize the device.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 New
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/*************************** Variable Definitions *****************************/
+extern XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES];
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID.  The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return
+* A pointer to the configuration table entry corresponding to the given
+* device ID, or NULL if no match is found.
+*
+******************************************************************************/
+XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId)
+{
+	XEmacPs_Config *CfgPtr = NULL;
+	u32 i;
+
+	for (i = 0U; i < (u32)XPAR_XEMACPS_NUM_INSTANCES; i++) {
+		if (XEmacPs_ConfigTable[i].DeviceId == DeviceId) {
+			CfgPtr = &XEmacPs_ConfigTable[i];
+			break;
+		}
+	}
+
+	return (XEmacPs_Config *)(CfgPtr);
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/Makefile b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..a88927f81af19f95afa2ff292bb3675aed0f3da0
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/Makefile
@@ -0,0 +1,28 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=xgpio_l.h xgpio.h
+
+LIBSOURCES=*.c
+OUTS = *.o 
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs:
+	echo "Compiling gpio"
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS)
+	make clean
+
+include: 
+	 ${CP} ${INCLUDEFILES} ${INCLUDEDIR} 
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio.c
new file mode 100644
index 0000000000000000000000000000000000000000..fe968c86855a0be853cddec8ce6e69ff1f62767a
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio.c
@@ -0,0 +1,255 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xgpio.c
+* @addtogroup gpio_v4_2
+* @{
+*
+* The implementation of the XGpio driver's basic functionality. See xgpio.h
+* for more information about the driver.
+*
+* @note
+*
+* None
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a rmm  02/04/02 First release
+* 2.00a jhl  12/16/02 Update for dual channel and interrupt support
+* 2.01a jvb  12/13/05 Changed Initialize() into CfgInitialize(), and made
+*                     CfgInitialize() take a pointer to a config structure
+*                     instead of a device id. Moved Initialize() into
+*                     xgpio_sinit.c, and had Initialize() call CfgInitialize()
+*                     after it retrieved the config structure using the device
+*                     id. Removed include of xparameters.h along with any
+*                     dependencies on xparameters.h and the _g.c config table.
+* 2.11a mta  03/21/07 Updated to new coding style, added GetDataDirection
+* 2.12a sv   11/21/07 Updated driver to support access through DCR bus
+* 3.00a sv   11/21/09 Updated to use HAL Processor APIs. Renamed the
+*		      macros to remove _m from the name.
+* 4.1   lks  11/18/15 Clean up of the comments in the code and
+*		      removed support for DCR bridge
+* 4.2   sk   08/16/16 Used UINTPTR instead of u32 for Baseaddress as part of
+*                     adding 64 bit support. CR# 867425.
+*                     Changed the prototype of XGpio_CfgInitialize API.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xgpio.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+
+/************************** Function Prototypes *****************************/
+
+
+/****************************************************************************/
+/**
+* Initialize the XGpio instance provided by the caller based on the
+* given configuration data.
+*
+* Nothing is done except to initialize the InstancePtr.
+*
+* @param	InstancePtr is a pointer to an XGpio instance. The memory the
+*		pointer references must be pre-allocated by the caller. Further
+*		calls to manipulate the driver through the XGpio API must be
+*		made with this pointer.
+* @param	Config is a reference to a structure containing information
+*		about a specific GPIO device. This function initializes an
+*		InstancePtr object for a specific device specified by the
+*		contents of Config. This function can initialize multiple
+*		instance objects with the use of multiple calls giving different
+*		Config information on each call.
+* @param 	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, use
+*		Config->BaseAddress for this parameters, passing the physical
+*		address instead.
+*
+* @return
+* 		- XST_SUCCESS if the initialization is successfull.
+*
+* @note		None.
+*
+*****************************************************************************/
+int XGpio_CfgInitialize(XGpio * InstancePtr, XGpio_Config * Config,
+			UINTPTR EffectiveAddr)
+{
+	/* Assert arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/* Set some default values. */
+	InstancePtr->BaseAddress = EffectiveAddr;
+
+	InstancePtr->InterruptPresent = Config->InterruptPresent;
+	InstancePtr->IsDual = Config->IsDual;
+
+	/*
+	 * Indicate the instance is now ready to use, initialized without error
+	 */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+	return (XST_SUCCESS);
+}
+
+
+/****************************************************************************/
+/**
+* Set the input/output direction of all discrete signals for the specified
+* GPIO channel.
+*
+* @param	InstancePtr is a pointer to an XGpio instance to be worked on.
+* @param	Channel contains the channel of the GPIO (1 or 2) to operate on.
+* @param	DirectionMask is a bitmask specifying which discretes are input
+*		and which are output. Bits set to 0 are output and bits set to 1
+*		are input.
+*
+* @return	None.
+*
+* @note		The hardware must be built for dual channels if this function
+*		is used with any channel other than 1.  If it is not, this
+*		function will assert.
+*
+*****************************************************************************/
+void XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel,
+			    u32 DirectionMask)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((Channel == 1) ||
+		     ((Channel == 2) && (InstancePtr->IsDual == TRUE)));
+
+	XGpio_WriteReg(InstancePtr->BaseAddress,
+			((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_TRI_OFFSET,
+			DirectionMask);
+}
+
+/****************************************************************************/
+/**
+* Get the input/output direction of all discrete signals for the specified
+* GPIO channel.
+*
+* @param	InstancePtr is a pointer to an XGpio instance to be worked on.
+* @param	Channel contains the channel of the GPIO (1 or 2) to operate on.
+*
+* @return	Bitmask specifying which discretes are input and
+*		which are output. Bits set to 0 are output and bits set to 1 are
+*		input.
+*
+* @note
+*
+* The hardware must be built for dual channels if this function is used
+* with any channel other than 1.  If it is not, this function will assert.
+*
+*****************************************************************************/
+u32 XGpio_GetDataDirection(XGpio *InstancePtr, unsigned Channel)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((Channel == 1)  ||
+		((Channel == 2) &&
+		(InstancePtr->IsDual == TRUE)));
+
+	return XGpio_ReadReg(InstancePtr->BaseAddress,
+		((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_TRI_OFFSET);
+}
+
+/****************************************************************************/
+/**
+* Read state of discretes for the specified GPIO channnel.
+*
+* @param	InstancePtr is a pointer to an XGpio instance to be worked on.
+* @param	Channel contains the channel of the GPIO (1 or 2) to operate on.
+*
+* @return	Current copy of the discretes register.
+*
+* @note		The hardware must be built for dual channels if this function
+*		is used with any channel other than 1.  If it is not, this
+*		function will assert.
+*
+*****************************************************************************/
+u32 XGpio_DiscreteRead(XGpio * InstancePtr, unsigned Channel)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((Channel == 1) ||
+			((Channel == 2) && (InstancePtr->IsDual == TRUE)));
+
+	return XGpio_ReadReg(InstancePtr->BaseAddress,
+			      ((Channel - 1) * XGPIO_CHAN_OFFSET) +
+			      XGPIO_DATA_OFFSET);
+}
+
+/****************************************************************************/
+/**
+* Write to discretes register for the specified GPIO channel.
+*
+* @param	InstancePtr is a pointer to an XGpio instance to be worked on.
+* @param	Channel contains the channel of the GPIO (1 or 2) to operate on.
+* @param	Data is the value to be written to the discretes register.
+*
+* @return	None.
+*
+* @note		The hardware must be built for dual channels if this function
+*		is  used with any channel other than 1.  If it is not, this
+*		function will assert. See also XGpio_DiscreteSet() and
+*		XGpio_DiscreteClear().
+*
+*****************************************************************************/
+void XGpio_DiscreteWrite(XGpio * InstancePtr, unsigned Channel, u32 Data)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((Channel == 1) ||
+		     ((Channel == 2) && (InstancePtr->IsDual == TRUE)));
+
+	XGpio_WriteReg(InstancePtr->BaseAddress,
+			((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET,
+			Data);
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio.h
new file mode 100644
index 0000000000000000000000000000000000000000..fc3f0bd338a05a0c1a5f72e2026125187cddfc3c
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio.h
@@ -0,0 +1,214 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xgpio.h
+* @addtogroup gpio_v4_2
+* @{
+* @details
+*
+* This file contains the software API definition of the Xilinx General Purpose
+* I/O (XGpio) device driver.
+*
+* The Xilinx GPIO controller is a soft IP core designed for Xilinx FPGAs and
+* contains the following general features:
+*   - Support for up to 32 I/O discretes for each channel (64 bits total).
+*   - Each of the discretes can be configured for input or output.
+*   - Configurable support for dual channels and interrupt generation.
+*
+* The driver provides interrupt management functions. Implementation of
+* interrupt handlers is left to the user. Refer to the provided interrupt
+* example in the examples directory for details.
+*
+* This driver is intended to be RTOS and processor independent. Any needs for
+* dynamic memory management, threads or thread mutual exclusion, virtual
+* memory, or cache control must be satisfied by the layer above this driver.
+*
+* <b>Initialization & Configuration</b>
+*
+* The XGpio_Config structure is used by the driver to configure itself. This
+* configuration structure is typically created by the tool-chain based on HW
+* build properties.
+*
+* To support multiple runtime loading and initialization strategies employed
+* by various operating systems, the driver instance can be initialized in one
+* of the following ways:
+*
+*   - XGpio_Initialize(InstancePtr, DeviceId) - The driver looks up its own
+*     configuration structure created by the tool-chain based on an ID provided
+*     by the tool-chain.
+*
+*   - XGpio_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+*     configuration structure provided by the caller. If running in a system
+*     with address translation, the provided virtual memory base address
+*     replaces the physical address present in the configuration structure.
+*
+* @note
+*
+* This API utilizes 32 bit I/O to the GPIO registers. With less than 32 bits,
+* the unused bits from registers are read as zero and written as don't cares.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a rmm  03/13/02 First release
+* 2.00a jhl  11/26/03 Added support for dual channels and interrupts
+* 2.01a jvb  12/14/05 I separated dependency on the static config table and
+*                     xparameters.h from the driver initialization by moving
+*                     _Initialize and _LookupConfig to _sinit.c. I also added
+*                     the new _CfgInitialize routine.
+* 2.11a mta  03/21/07 Updated to new coding style, added GetDataDirection
+* 2.12a sv   11/21/07 Updated driver to support access through DCR bus
+* 2.12a sv   06/05/08 Updated driver to fix the XGpio_InterruptDisable function
+*		      to properly update the Interrupt Enable register
+* 2.13a sdm  08/22/08 Removed support for static interrupt handlers from the MDD
+*		      file
+* 3.00a sv   11/21/09 Updated to use HAL Processor APIs.
+*		      Renamed the macros XGpio_mWriteReg to XGpio_WriteReg and
+*		      XGpio_mReadReg to XGpio_ReadReg. Removed the macros
+*		      XGpio_mSetDataDirection, XGpio_mGetDataReg and
+*		      XGpio_mSetDataReg. Users should use XGpio_WriteReg and
+*		      XGpio_ReadReg to achieve the same functionality.
+* 3.01a bss  04/18/13 Updated driver tcl to generate Canonical params in
+*		      xparameters.h. CR#698589
+* 4.0   adk  19/12/13 Updated as per the New Tcl API's
+* 4.1   lks  11/18/15 Updated to use cannonical xparameters in examples and
+*		      clean up of the comments, removed support for DCR bridge
+*		      and removed xgpio_intr_example for CR 900381
+* 4.2   sk   08/16/16 Used UINTPTR instead of u32 for Baseaddress as part of
+*                     adding 64 bit support. CR# 867425.
+*                     Changed the prototype of XGpio_CfgInitialize API.
+* 4.3   sk   09/29/16 Modified the example to make it work when LED_bits are
+*                     configured as an output. CR# 958644
+*       ms   01/23/17 Added xil_printf statement in main function for all
+*                     examples to ensure that "Successfully ran" and "Failed"
+*                     strings are available in all examples. This is a fix
+*                     for CR-965028.
+*       ms   03/17/17 Added readme.txt file in examples folder for doxygen
+*                     generation.
+*
+* </pre>
+*****************************************************************************/
+
+#ifndef XGPIO_H			/* prevent circular inclusions */
+#define XGPIO_H			/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xgpio_l.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;		/* Unique ID  of device */
+	UINTPTR BaseAddress;	/* Device base address */
+	int InterruptPresent;	/* Are interrupts supported in h/w */
+	int IsDual;		/* Are 2 channels supported in h/w */
+} XGpio_Config;
+
+/**
+ * The XGpio driver instance data. The user is required to allocate a
+ * variable of this type for every GPIO device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	UINTPTR BaseAddress;	/* Device base address */
+	u32 IsReady;		/* Device is initialized and ready */
+	int InterruptPresent;	/* Are interrupts supported in h/w */
+	int IsDual;		/* Are 2 channels supported in h/w */
+} XGpio;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+/*
+ * Initialization functions in xgpio_sinit.c
+ */
+int XGpio_Initialize(XGpio *InstancePtr, u16 DeviceId);
+XGpio_Config *XGpio_LookupConfig(u16 DeviceId);
+
+/*
+ * API Basic functions implemented in xgpio.c
+ */
+int XGpio_CfgInitialize(XGpio *InstancePtr, XGpio_Config * Config,
+			UINTPTR EffectiveAddr);
+void XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel,
+			    u32 DirectionMask);
+u32 XGpio_GetDataDirection(XGpio *InstancePtr, unsigned Channel);
+u32 XGpio_DiscreteRead(XGpio *InstancePtr, unsigned Channel);
+void XGpio_DiscreteWrite(XGpio *InstancePtr, unsigned Channel, u32 Mask);
+
+
+/*
+ * API Functions implemented in xgpio_extra.c
+ */
+void XGpio_DiscreteSet(XGpio *InstancePtr, unsigned Channel, u32 Mask);
+void XGpio_DiscreteClear(XGpio *InstancePtr, unsigned Channel, u32 Mask);
+
+/*
+ * API Functions implemented in xgpio_selftest.c
+ */
+int XGpio_SelfTest(XGpio *InstancePtr);
+
+/*
+ * API Functions implemented in xgpio_intr.c
+ */
+void XGpio_InterruptGlobalEnable(XGpio *InstancePtr);
+void XGpio_InterruptGlobalDisable(XGpio *InstancePtr);
+void XGpio_InterruptEnable(XGpio *InstancePtr, u32 Mask);
+void XGpio_InterruptDisable(XGpio *InstancePtr, u32 Mask);
+void XGpio_InterruptClear(XGpio *InstancePtr, u32 Mask);
+u32 XGpio_InterruptGetEnabled(XGpio *InstancePtr);
+u32 XGpio_InterruptGetStatus(XGpio *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_extra.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_extra.c
new file mode 100644
index 0000000000000000000000000000000000000000..219952678c8324f2c8a9457519f5b361b88bc75e
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_extra.c
@@ -0,0 +1,164 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xgpio_extra.c
+* @addtogroup gpio_v4_2
+* @{
+*
+* The implementation of the XGpio driver's advanced discrete functions.
+* See xgpio.h for more information about the driver.
+*
+* @note
+*
+* These APIs can only be used if the GPIO_IO ports in the IP are used for
+* connecting to the external output ports.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a rmm  02/04/02 First release
+* 2.00a jhl  12/16/02 Update for dual channel and interrupt support
+* 2.11a mta  03/21/07 Updated to new coding style
+* 3.00a sv   11/21/09 Updated to use HAL Processor APIs. Renamed the macros
+*		      XGpio_mWriteReg to XGpio_WriteReg, and XGpio_mReadReg
+*		      to XGpio_ReadReg.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xgpio.h"
+#include "xgpio_i.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+
+/****************************************************************************/
+/**
+* Set output discrete(s) to logic 1 for the specified GPIO channel.
+*
+* @param	InstancePtr is a pointer to an XGpio instance to be worked on.
+* @param	Channel contains the channel of the GPIO (1 or 2) to operate on.
+* @param	Mask is the set of bits that will be set to 1 in the discrete
+*		data register. All other bits in the data register are
+*		unaffected.
+*
+* @return	None.
+*
+* @note
+*
+* The hardware must be built for dual channels if this function is used
+* with any channel other than 1.  If it is not, this function will assert.
+*
+* This API can only be used if the GPIO_IO ports in the IP are used for
+* connecting to the external output ports.
+*
+*****************************************************************************/
+void XGpio_DiscreteSet(XGpio * InstancePtr, unsigned Channel, u32 Mask)
+{
+	u32 Current;
+	unsigned DataOffset;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((Channel == 1) ||
+		     ((Channel == 2) && (InstancePtr->IsDual == TRUE)));
+
+	/* Calculate the offset to the data register of the GPIO  */
+	DataOffset = ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET;
+
+	/*
+	 * Read the contents of the data register, merge in Mask and write
+	 * back results
+	 */
+	Current = XGpio_ReadReg(InstancePtr->BaseAddress, DataOffset);
+	Current |= Mask;
+	XGpio_WriteReg(InstancePtr->BaseAddress, DataOffset, Current);
+}
+
+
+/****************************************************************************/
+/**
+* Set output discrete(s) to logic 0 for the specified GPIO channel.
+*
+* @param	InstancePtr is a pointer to an XGpio instance to be worked on.
+* @param	Channel contains the channel of the GPIO (1 or 2) to operate on.
+* @param	Mask is the set of bits that will be set to 0 in the discrete
+*		data register. All other bits in the data register are
+*		unaffected.
+*
+* @return	None.
+*
+* @note
+*
+* The hardware must be built for dual channels if this function is used
+* with any channel other than 1.  If it is not, this function will assert.
+*
+* This API can only be used if the GPIO_IO ports in the IP are used for
+* connecting to the external output ports.
+*
+*****************************************************************************/
+void XGpio_DiscreteClear(XGpio * InstancePtr, unsigned Channel, u32 Mask)
+{
+	u32 Current;
+	unsigned DataOffset;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((Channel == 1) ||
+		     ((Channel == 2) && (InstancePtr->IsDual == TRUE)));
+
+	/* Calculate the offset to the data register of the GPIO  */
+	DataOffset = ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET;
+
+	/*
+	 * Read the contents of the data register, merge in Mask and write
+	 * back results
+	 */
+	Current = XGpio_ReadReg(InstancePtr->BaseAddress, DataOffset);
+	Current &= ~Mask;
+	XGpio_WriteReg(InstancePtr->BaseAddress, DataOffset, Current);
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_g.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..547585f78bd3f6e94278ca93a17dc528ffc3ce61
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_g.c
@@ -0,0 +1,63 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xgpio.h"
+
+/*
+* The configuration table for devices
+*/
+
+XGpio_Config XGpio_ConfigTable[XPAR_XGPIO_NUM_INSTANCES] =
+{
+	{
+		XPAR_AXI_GPIO_0_DEVICE_ID,
+		XPAR_AXI_GPIO_0_BASEADDR,
+		XPAR_AXI_GPIO_0_INTERRUPT_PRESENT,
+		XPAR_AXI_GPIO_0_IS_DUAL
+	},
+	{
+		XPAR_AXI_GPIO_1_DEVICE_ID,
+		XPAR_AXI_GPIO_1_BASEADDR,
+		XPAR_AXI_GPIO_1_INTERRUPT_PRESENT,
+		XPAR_AXI_GPIO_1_IS_DUAL
+	}
+};
+
+
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_i.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_i.h
new file mode 100644
index 0000000000000000000000000000000000000000..50f59baa7bbaad0ee08f8912c1af281754c828de
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_i.h
@@ -0,0 +1,87 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************/
+/**
+* @file xgpio_i.h
+* @addtogroup gpio_v4_2
+* @{
+*
+* This header file contains internal identifiers, which are those shared
+* between the files of the driver. It is intended for internal use only.
+*
+* NOTES:
+*
+* None.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a rmm  03/13/02 First release
+* 2.11a mta  03/21/07 Updated to new coding style
+* </pre>
+******************************************************************************/
+
+#ifndef XGPIO_I_H		/* prevent circular inclusions */
+#define XGPIO_I_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xgpio.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions ****************************/
+
+extern XGpio_Config XGpio_ConfigTable[];
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_intr.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_intr.c
new file mode 100644
index 0000000000000000000000000000000000000000..271bb765af6c4acd9d3d6f8ca40f86bb0d3c5df9
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_intr.c
@@ -0,0 +1,294 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xgpio_intr.c
+* @addtogroup gpio_v4_2
+* @{
+*
+* Implements GPIO interrupt processing functions for the XGpio driver.
+* See xgpio.h for more information about the driver.
+*
+* The functions in this file require the hardware device to be built with
+* interrupt capabilities. The functions will assert if called using hardware
+* that does not have interrupt capabilities.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 2.00a jhl  11/26/03 Initial release
+* 2.11a mta  03/21/07 Updated to new coding style
+* 2.12a sv   06/05/08 Updated driver to fix the XGpio_InterruptDisable function
+*		      to properly update the Interrupt Enable register
+* 3.00a sv   11/21/09 Updated to use HAL Processor APIs. Renamed the macros
+*		      XGpio_mWriteReg to XGpio_WriteReg, and XGpio_mReadReg
+*		      to XGpio_ReadReg.
+
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xgpio.h"
+
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+
+/****************************************************************************/
+/**
+* Enable the interrupt output signal. Interrupts enabled through
+* XGpio_InterruptEnable() will not be passed through until the global enable
+* bit is set by this function. This function is designed to allow all
+* interrupts (both channels) to be enabled easily for exiting a critical
+* section. This function will assert if the hardware device has not been
+* built with interrupt capabilities.
+*
+* @param	InstancePtr is the GPIO instance to operate on.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpio_InterruptGlobalEnable(XGpio *InstancePtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
+
+	XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_GIE_OFFSET,
+			XGPIO_GIE_GINTR_ENABLE_MASK);
+}
+
+
+/****************************************************************************/
+/**
+* Disable the interrupt output signal. Interrupts enabled through
+* XGpio_InterruptEnable() will no longer be passed through until the global
+* enable bit is set by XGpio_InterruptGlobalEnable(). This function is
+* designed to allow all interrupts (both channels) to be disabled easily for
+* entering a critical section. This function will assert if the hardware
+* device has not been built with interrupt capabilities.
+*
+* @param	InstancePtr is the GPIO instance to operate on.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpio_InterruptGlobalDisable(XGpio *InstancePtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
+
+
+	XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_GIE_OFFSET, 0x0);
+
+}
+
+
+/****************************************************************************/
+/**
+* Enable interrupts. The global interrupt must also be enabled by calling
+* XGpio_InterruptGlobalEnable() for interrupts to occur. This function will
+* assert if the hardware device has not been built with interrupt capabilities.
+*
+* @param	InstancePtr is the GPIO instance to operate on.
+* @param	Mask is the mask to enable. Bit positions of 1 are enabled.
+*		This mask is formed by OR'ing bits from XGPIO_IR* bits which
+*		are contained in xgpio_l.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpio_InterruptEnable(XGpio *InstancePtr, u32 Mask)
+{
+	u32 Register;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
+
+	/*
+	 * Read the interrupt enable register and only enable the specified
+	 * interrupts without disabling or enabling any others.
+	 */
+
+	Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET);
+	XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET,
+			Register | Mask);
+
+}
+
+
+/****************************************************************************/
+/**
+* Disable interrupts. This function allows specific interrupts for each
+* channel to be disabled. This function will assert if the hardware device
+* has not been built with interrupt capabilities.
+*
+* @param	InstancePtr is the GPIO instance to operate on.
+* @param 	Mask is the mask to disable. Bits set to 1 are disabled. This
+*		mask is formed by OR'ing bits from XGPIO_IR* bits which are
+*		contained in xgpio_l.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpio_InterruptDisable(XGpio *InstancePtr, u32 Mask)
+{
+	u32 Register;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
+
+	/*
+	 * Read the interrupt enable register and only disable the specified
+	 * interrupts without enabling or disabling any others.
+	 */
+	Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET);
+	XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET,
+			Register & (~Mask));
+
+}
+
+/****************************************************************************/
+/**
+* Clear pending interrupts with the provided mask. This function should be
+* called after the software has serviced the interrupts that are pending.
+* This function will assert if the hardware device has not been built with
+* interrupt capabilities.
+*
+* @param 	InstancePtr is the GPIO instance to operate on.
+* @param 	Mask is the mask to clear pending interrupts for. Bit positions
+*		of 1 are cleared. This mask is formed by OR'ing bits from
+*		XGPIO_IR* bits which are contained in xgpio_l.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpio_InterruptClear(XGpio * InstancePtr, u32 Mask)
+{
+	u32 Register;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
+
+	/*
+	 * Read the interrupt status register and only clear the interrupts
+	 * that are specified without affecting any others.  Since the register
+	 * is a toggle on write, make sure any bits to be written are already
+	 * set.
+	 */
+	Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET);
+	XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET,
+			Register & Mask);
+
+
+}
+
+
+/****************************************************************************/
+/**
+* Returns the interrupt enable mask. This function will assert if the
+* hardware device has not been built with interrupt capabilities.
+*
+* @param	InstancePtr is the GPIO instance to operate on.
+*
+* @return	A mask of bits made from XGPIO_IR* bits which are contained in
+*		xgpio_l.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpio_InterruptGetEnabled(XGpio * InstancePtr)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(InstancePtr->InterruptPresent == TRUE);
+
+	return XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET);
+}
+
+
+/****************************************************************************/
+/**
+* Returns the status of interrupt signals. Any bit in the mask set to 1
+* indicates that the channel associated with the bit has asserted an interrupt
+* condition. This function will assert if the hardware device has not been
+* built with interrupt capabilities.
+*
+* @param	InstancePtr is the GPIO instance to operate on.
+*
+* @return	A pointer to a mask of bits made from XGPIO_IR* bits which are
+*		 contained in xgpio_l.h.
+*
+* @note
+*
+* The interrupt status indicates the status of the device irregardless if
+* the interrupts from the devices have been enabled or not through
+* XGpio_InterruptEnable().
+*
+*****************************************************************************/
+u32 XGpio_InterruptGetStatus(XGpio * InstancePtr)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(InstancePtr->InterruptPresent == TRUE);
+
+
+	return XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET);
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_l.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_l.h
new file mode 100644
index 0000000000000000000000000000000000000000..9c88aba2e7d6198a9d175eea234b472cca1a6ae6
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_l.h
@@ -0,0 +1,193 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpio_l.h
+* @addtogroup gpio_v4_2
+* @{
+*
+* This header file contains identifiers and driver functions (or
+* macros) that can be used to access the device.  The user should refer to the
+* hardware device specification for more details of the device operation.
+*
+* The macros that are available in this file use a multiply to calculate the
+* addresses of registers. The user can control whether that multiply is done
+* at run time or at compile time. A constant passed as the channel parameter
+* will cause the multiply to be done at compile time. A variable passed as the
+* channel parameter will cause it to occur at run time.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a jhl  04/24/02 First release of low level driver
+* 2.00a jhl  11/26/03 Added support for dual channels and interrupts. This
+*                     change required the functions to be changed such that
+*                     the interface is not compatible with previous versions.
+*                     See the examples in the example directory for macros
+*                     to help compile an application that was designed for
+*                     previous versions of the driver. The interrupt registers
+*                     are accessible using the ReadReg and WriteReg macros and
+*                     a channel parameter was added to the other macros.
+* 2.11a mta  03/21/07 Updated to new coding style
+* 2.12a sv   11/21/07 Updated driver to support access through DCR bus.
+* 3.00a sv   11/21/09 Renamed the macros XGpio_mWriteReg to XGpio_WriteReg
+*		      XGpio_mReadReg to XGpio_ReadReg.
+*		      Removed the macros XGpio_mSetDataDirection,
+*		      XGpio_mGetDataReg and XGpio_mSetDataReg. Users
+*		      should use XGpio_WriteReg/XGpio_ReadReg to achieve the
+*		      same functionality.
+* 4.1  lks   11/18/15 Removed support for DCR bridge
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XGPIO_L_H		/* prevent circular inclusions */
+#define XGPIO_L_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+
+/************************** Constant Definitions *****************************/
+
+/** @name Registers
+ *
+ * Register offsets for this device.
+ * @{
+ */
+#define XGPIO_DATA_OFFSET	0x0   /**< Data register for 1st channel */
+#define XGPIO_TRI_OFFSET	0x4   /**< I/O direction reg for 1st channel */
+#define XGPIO_DATA2_OFFSET	0x8   /**< Data register for 2nd channel */
+#define XGPIO_TRI2_OFFSET	0xC   /**< I/O direction reg for 2nd channel */
+
+#define XGPIO_GIE_OFFSET	0x11C /**< Glogal interrupt enable register */
+#define XGPIO_ISR_OFFSET	0x120 /**< Interrupt status register */
+#define XGPIO_IER_OFFSET	0x128 /**< Interrupt enable register */
+
+/* @} */
+
+/* The following constant describes the offset of each channels data and
+ * tristate register from the base address.
+ */
+#define XGPIO_CHAN_OFFSET  8
+
+/** @name Interrupt Status and Enable Register bitmaps and masks
+ *
+ * Bit definitions for the interrupt status register and interrupt enable
+ * registers.
+ * @{
+ */
+#define XGPIO_IR_MASK		0x3 /**< Mask of all bits */
+#define XGPIO_IR_CH1_MASK	0x1 /**< Mask for the 1st channel */
+#define XGPIO_IR_CH2_MASK	0x2 /**< Mask for the 2nd channel */
+/*@}*/
+
+
+/** @name Global Interrupt Enable Register bitmaps and masks
+ *
+ * Bit definitions for the Global Interrupt  Enable register
+ * @{
+ */
+#define XGPIO_GIE_GINTR_ENABLE_MASK	0x80000000
+/*@}*/
+
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XGpio_In32  Xil_In32
+#define XGpio_Out32 Xil_Out32
+
+
+/****************************************************************************/
+/**
+*
+* Write a value to a GPIO register. A 32 bit write is performed. If the
+* GPIO core is implemented in a smaller width, only the least significant data
+* is written.
+*
+* @param	BaseAddress is the base address of the GPIO device.
+* @param	RegOffset is the register offset from the base to write to.
+* @param	Data is the data written to the register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XGpio_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+****************************************************************************/
+#define XGpio_WriteReg(BaseAddress, RegOffset, Data) \
+	XGpio_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/****************************************************************************/
+/**
+*
+* Read a value from a GPIO register. A 32 bit read is performed. If the
+* GPIO core is implemented in a smaller width, only the least
+* significant data is read from the register. The most significant data
+* will be read as 0.
+*
+* @param	BaseAddress is the base address of the GPIO device.
+* @param	RegOffset is the register offset from the base to read from.
+*
+* @return	Data read from the register.
+*
+* @note		C-style signature:
+*		u32 XGpio_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+****************************************************************************/
+#define XGpio_ReadReg(BaseAddress, RegOffset) \
+	XGpio_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_selftest.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_selftest.c
new file mode 100644
index 0000000000000000000000000000000000000000..77982e35d70849a46ebedc4ac91ba03d56d253f6
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_selftest.c
@@ -0,0 +1,110 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xgpio_selftest.c
+* @addtogroup gpio_v4_2
+* @{
+*
+* The implementation of the XGpio driver's self test function.
+* See xgpio.h for more information about the driver.
+*
+* @note
+*
+* None
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a rmm  02/04/02 First release
+* 2.00a jhl  01/13/04 Addition of dual channels and interrupts.
+* 2.11a mta  03/21/07 Updated to new coding style
+* 3.00a sv   11/21/09 Updated to use HAL Processor APIs.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xgpio.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+
+/******************************************************************************/
+/**
+* Run a self-test on the driver/device. This function does a minimal test
+* in which the data register is read. It only does a read without any kind
+* of test because the hardware has been parameterized such that it may be only
+* an input such that the state of the inputs won't be known.
+*
+* All other hardware features of the device are not guaranteed to be in the
+* hardware since they are parameterizable.
+*
+*
+* @param	InstancePtr is a pointer to the XGpio instance to be worked on.
+*		This parameter must have been previously initialized with
+*		XGpio_Initialize().
+*
+* @return 	XST_SUCCESS always. If the GPIO device was not present in the
+*		hardware a bus error could be generated. Other indicators of a
+*		bus error, such as registers in bridges or buses, may be
+*		necessary to determine if this function caused a bus error.
+*
+* @note		None.
+*
+******************************************************************************/
+int XGpio_SelfTest(XGpio * InstancePtr)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read from the data register of channel 1 which is always guaranteed
+	 * to be in the hardware device. Since the data may be configured as
+	 * all inputs, there is not way to guarantee the value read so don't
+	 * test it.
+	 */
+	(void) XGpio_DiscreteRead(InstancePtr, 1);
+
+	return (XST_SUCCESS);
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_sinit.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..e61de8412d9dda37b2a26ff735f8cbc00117781b
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpio_v4_3/src/xgpio_sinit.c
@@ -0,0 +1,159 @@
+/******************************************************************************
+*
+* Copyright (C) 2003 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xgpio_sinit.c
+* @addtogroup gpio_v4_2
+* @{
+*
+* The implementation of the XGpio driver's static initialzation
+* functionality.
+*
+* @note
+*
+* None
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 2.01a jvb  10/13/05 First release
+* 2.11a mta  03/21/07 Updated to new coding style
+* 4.0   sha  07/15/15 Defined macro XPAR_XGPIO_NUM_INSTANCES if not
+*		      defined in xparameters.h
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xgpio_i.h"
+
+/************************** Constant Definitions ****************************/
+
+#ifndef XPAR_XGPIO_NUM_INSTANCES
+#define XPAR_XGPIO_NUM_INSTANCES		0
+#endif
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+
+/************************** Function Prototypes *****************************/
+
+
+/******************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID.  The table
+* ConfigTable contains the configuration info for each device in the system.
+*
+* @param	DeviceId is the device identifier to lookup.
+*
+* @return
+*		 - A pointer of data type XGpio_Config which points to the
+*		device configuration if DeviceID is found.
+* 		- NULL if DeviceID is not found.
+*
+* @note		None.
+*
+******************************************************************************/
+XGpio_Config *XGpio_LookupConfig(u16 DeviceId)
+{
+	XGpio_Config *CfgPtr = NULL;
+
+	int Index;
+
+	for (Index = 0; Index < XPAR_XGPIO_NUM_INSTANCES; Index++) {
+		if (XGpio_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XGpio_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}
+
+
+/****************************************************************************/
+/**
+* Initialize the XGpio instance provided by the caller based on the
+* given DeviceID.
+*
+* Nothing is done except to initialize the InstancePtr.
+*
+* @param	InstancePtr is a pointer to an XGpio instance. The memory the
+*		pointer references must be pre-allocated by the caller. Further
+*		calls to manipulate the instance/driver through the XGpio API
+*		must be made with this pointer.
+* @param	DeviceId is the unique id of the device controlled by this XGpio
+*		instance. Passing in a device id associates the generic XGpio
+*		instance to a specific device, as chosen by the caller or
+*		application developer.
+*
+* @return
+*		- XST_SUCCESS if the initialization was successfull.
+* 		- XST_DEVICE_NOT_FOUND  if the device configuration data was not
+*		found for a device with the supplied device ID.
+*
+* @note		None.
+*
+*****************************************************************************/
+int XGpio_Initialize(XGpio * InstancePtr, u16 DeviceId)
+{
+	XGpio_Config *ConfigPtr;
+
+	/*
+	 * Assert arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/*
+	 * Lookup configuration data in the device configuration table.
+	 * Use this configuration info down below when initializing this
+	 * driver.
+	 */
+	ConfigPtr = XGpio_LookupConfig(DeviceId);
+	if (ConfigPtr == (XGpio_Config *) NULL) {
+		InstancePtr->IsReady = 0;
+		return (XST_DEVICE_NOT_FOUND);
+	}
+
+	return XGpio_CfgInitialize(InstancePtr, ConfigPtr,
+				   ConfigPtr->BaseAddress);
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/Makefile b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..8601ce4c7ccc85be4806137993703475251fb65e
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xgpiops_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling gpiops"
+
+xgpiops_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xgpiops_includes
+
+xgpiops_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops.c
new file mode 100644
index 0000000000000000000000000000000000000000..90eedb87dca3d4d524d86c3a58c189e34edc469f
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops.c
@@ -0,0 +1,628 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops.c
+* @addtogroup gpiops_v3_1
+* @{
+*
+* The XGpioPs driver. Functions in this file are the minimum required functions
+* for this driver. See xgpiops.h for a detailed description of the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.01a sv   04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+*                     XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+*		      relevant to Zynq device. The interrupts are disabled
+*		      for output pins on all banks during initialization.
+* 2.1   hk   04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+extern void StubHandler(void *CallBackRef, u32 Bank, u32 Status);
+
+/*****************************************************************************/
+/*
+*
+* This function initializes a XGpioPs instance/driver.
+* All members of the XGpioPs instance structure are initialized and
+* StubHandlers are assigned to the Bank Status Handlers.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	ConfigPtr points to the XGpioPs device configuration structure.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. If the address translation is not used then the
+*		physical address should be passed.
+*		Unexpected errors may occur if the address mapping is changed
+*		after this function is invoked.
+*
+* @return	XST_SUCCESS always.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	s32 Status = XST_SUCCESS;
+	u8 i;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+	Xil_AssertNonvoid(EffectiveAddr != (u32)0);
+	/*
+	 * Set some default values for instance data, don't indicate the device
+	 * is ready to use until everything has been initialized successfully.
+	 */
+	InstancePtr->IsReady = 0U;
+	InstancePtr->GpioConfig.BaseAddr = EffectiveAddr;
+	InstancePtr->GpioConfig.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Handler = StubHandler;
+	InstancePtr->Platform = XGetPlatform_Info();
+
+	/* Initialize the Bank data based on platform */
+	if (InstancePtr->Platform == XPLAT_ZYNQ_ULTRA_MP) {
+		/*
+		 *	Max pins in the ZynqMP GPIO device
+		 *	0 - 25,  Bank 0
+		 *	26 - 51, Bank 1
+		 *	52 - 77, Bank 2
+		 *	78 - 109, Bank 3
+		 *	110 - 141, Bank 4
+		 *	142 - 173, Bank 5
+		 */
+		InstancePtr->MaxPinNum = (u32)174;
+		InstancePtr->MaxBanks = (u8)6;
+	} else {
+		/*
+		 *	Max pins in the GPIO device
+		 *	0 - 31,  Bank 0
+		 *	32 - 53, Bank 1
+		 *	54 - 85, Bank 2
+		 *	86 - 117, Bank 3
+		 */
+		InstancePtr->MaxPinNum = (u32)118;
+		InstancePtr->MaxBanks = (u8)4;
+	}
+
+	/*
+	 * By default, interrupts are not masked in GPIO. Disable
+	 * interrupts for all pins in all the 4 banks.
+	 */
+	for (i=0;i<InstancePtr->MaxBanks;i++) {
+		XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+					  ((u32)(i) * XGPIOPS_REG_MASK_OFFSET) +
+					  XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
+	}
+
+	/* Indicate the component is now ready to use. */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Read the Data register of the specified GPIO bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return	Current value of the Data register.
+*
+* @note		This function is used for reading the state of all the GPIO pins
+*		of specified bank.
+*
+*****************************************************************************/
+u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+	return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				 ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+				 XGPIOPS_DATA_RO_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Read Data from the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the data has to be read.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*		See xgpiops.h for the mapping of the pin numbers in the banks.
+*
+* @return	Current value of the Pin (0 or 1).
+*
+* @note		This function is used for reading the state of the specified
+*		GPIO pin.
+*
+*****************************************************************************/
+u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				 ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+				 XGPIOPS_DATA_RO_OFFSET) >> (u32)PinNumber) & (u32)1;
+
+}
+
+/****************************************************************************/
+/**
+*
+* Write to the Data register of the specified GPIO bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	Data is the value to be written to the Data register.
+*
+* @return	None.
+*
+* @note		This function is used for writing to all the GPIO pins of
+*		the bank. The previous state of the pins is not maintained.
+*
+*****************************************************************************/
+void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+			  XGPIOPS_DATA_OFFSET, Data);
+}
+
+/****************************************************************************/
+/**
+*
+* Write data to the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number to which the Data is to be written.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param	Data is the data to be written to the specified pin (0 or 1).
+*
+* @return	None.
+*
+* @note		This function does a masked write to the specified pin of
+*		the specified GPIO bank. The previous state of other pins
+*		is maintained.
+*
+*****************************************************************************/
+void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data)
+{
+	u32 RegOffset;
+	u32 Value;
+	u8 Bank;
+	u8 PinNumber;
+	u32 DataVar = Data;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	if (PinNumber > 15U) {
+		/* There are only 16 data bits in bit maskable register. */
+		PinNumber -= (u8)16;
+		RegOffset = XGPIOPS_DATA_MSW_OFFSET;
+	} else {
+		RegOffset = XGPIOPS_DATA_LSW_OFFSET;
+	}
+
+	/*
+	 * Get the 32 bit value to be written to the Mask/Data register where
+	 * the upper 16 bits is the mask and lower 16 bits is the data.
+	 */
+	DataVar &= (u32)0x01;
+	Value = ~((u32)1 << (PinNumber + 16U)) & ((DataVar << PinNumber) | 0xFFFF0000U);
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_DATA_MASK_OFFSET) +
+			  RegOffset, Value);
+}
+
+
+
+/****************************************************************************/
+/**
+*
+* Set the Direction of the pins of the specified GPIO Bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	Direction is the 32 bit mask of the Pin direction to be set for
+*		all the pins in the Bank. Bits with 0 are set to Input mode,
+*		bits with 1 are	set to Output Mode.
+*
+* @return	None.
+*
+* @note		This function is used for setting the direction of all the pins
+*		in the specified bank. The previous state of the pins is
+*		not maintained.
+*
+*****************************************************************************/
+void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_DIRM_OFFSET, Direction);
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Direction of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number to which the Data is to be written.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param	Direction is the direction to be set for the specified pin.
+*		Valid values are 0 for Input Direction, 1 for Output Direction.
+*
+* @return	None.
+*
+*****************************************************************************/
+void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 DirModeReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+	Xil_AssertVoid(Direction <= (u32)1);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	DirModeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				      ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				      XGPIOPS_DIRM_OFFSET);
+
+	if (Direction!=(u32)0) { /*  Output Direction */
+		DirModeReg |= ((u32)1 << (u32)PinNumber);
+	} else { /* Input Direction */
+		DirModeReg &= ~ ((u32)1 << (u32)PinNumber);
+	}
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			 XGPIOPS_DIRM_OFFSET, DirModeReg);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Direction of the pins of the specified GPIO Bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* return	Returns a 32 bit mask of the Direction register. Bits with 0 are
+*		in Input mode, bits with 1 are in Output Mode.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+	return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				XGPIOPS_DIRM_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Direction of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the Direction is to be
+*		retrieved.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return	Direction of the specified pin.
+*		- 0 for Input Direction
+*		- 1 for Output Direction
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_DIRM_OFFSET) >> (u32)PinNumber) & (u32)1;
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Output Enable of the pins of the specified GPIO Bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	OpEnable is the 32 bit mask of the Output Enables to be set for
+*		all the pins in the Bank. The Output Enable of bits with 0 are
+*		disabled, the Output Enable of bits with 1 are enabled.
+*
+* @return	None.
+*
+* @note		This function is used for setting the Output Enables of all the
+*		pins in the specified bank. The previous state of the Output
+*		Enables is not maintained.
+*
+*****************************************************************************/
+void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_OUTEN_OFFSET, OpEnable);
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Output Enable of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number to which the Data is to be written.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param	OpEnable specifies whether the Output Enable for the specified
+*		pin should be enabled.
+*		Valid values are 0 for Disabling Output Enable,
+*		1 for Enabling Output Enable.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 OpEnableReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+	Xil_AssertVoid(OpEnable <= (u32)1);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	OpEnableReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				       ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				       XGPIOPS_OUTEN_OFFSET);
+
+	if (OpEnable != (u32)0) { /*  Enable Output Enable */
+		OpEnableReg |= ((u32)1 << (u32)PinNumber);
+	} else { /* Disable Output Enable */
+		OpEnableReg &= ~ ((u32)1 << (u32)PinNumber);
+	}
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_OUTEN_OFFSET, OpEnableReg);
+}
+/****************************************************************************/
+/**
+*
+* Get the Output Enable status of the pins of the specified GPIO Bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* return	Returns a a 32 bit mask of the Output Enable register.
+*		Bits with 0 are in Disabled state, bits with 1 are in
+*		Enabled State.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+	return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				XGPIOPS_OUTEN_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Output Enable status of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the Output Enable status is to
+*		be retrieved.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return	Output Enable of the specified pin.
+*		- 0 if Output Enable is disabled for this pin
+*		- 1 if Output Enable is enabled for this pin
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_OUTEN_OFFSET) >> (u32)PinNumber) & (u32)1;
+}
+
+/****************************************************************************/
+/*
+*
+* Get the Bank number and the Pin number in the Bank, for the given PinNumber
+* in the GPIO device.
+*
+* @param	PinNumber is the Pin number in the GPIO device.
+* @param	BankNumber returns the Bank in which this GPIO pin is present.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+* @param	PinNumberInBank returns the Pin Number within the Bank.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank)
+{
+	u32 XGpioPsPinTable[6] = {0};
+	u32 Platform = XGetPlatform_Info();
+
+	if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
+		/*
+		 * This structure defines the mapping of the pin numbers to the banks when
+		 * the driver APIs are used for working on the individual pins.
+		 */
+
+		XGpioPsPinTable[0] = (u32)25; /* 0 - 25, Bank 0 */
+		XGpioPsPinTable[1] = (u32)51; /* 26 - 51, Bank 1 */
+		XGpioPsPinTable[2] = (u32)77; /* 52 - 77, Bank 2 */
+		XGpioPsPinTable[3] = (u32)109; /* 78 - 109, Bank 3 */
+		XGpioPsPinTable[4] = (u32)141; /* 110 - 141, Bank 4 */
+		XGpioPsPinTable[5] = (u32)173; /* 142 - 173 Bank 5 */
+
+		*BankNumber = 0U;
+		while (*BankNumber < 6U) {
+			if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
+				break;
+			}
+			(*BankNumber)++;
+		}
+	} else {
+		XGpioPsPinTable[0] = (u32)31; /* 0 - 31, Bank 0 */
+		XGpioPsPinTable[1] = (u32)53; /* 32 - 53, Bank 1 */
+		XGpioPsPinTable[2] = (u32)85; /* 54 - 85, Bank 2 */
+		XGpioPsPinTable[3] = (u32)117; /* 86 - 117 Bank 3 */
+
+		*BankNumber = 0U;
+		while (*BankNumber < 4U) {
+			if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
+				break;
+			}
+			(*BankNumber)++;
+		}
+	}
+	if (*BankNumber == (u8)0) {
+		*PinNumberInBank = PinNumber;
+	} else {
+		*PinNumberInBank = (u8)((u32)PinNumber %
+					(XGpioPsPinTable[*BankNumber - (u8)1] + (u32)1));
+	}
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops.h
new file mode 100644
index 0000000000000000000000000000000000000000..367380656282ba41858dcb558f819eb39f23fbdd
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops.h
@@ -0,0 +1,270 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops.h
+* @addtogroup gpiops_v3_1
+* @{
+* @details
+*
+* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
+* Controller.
+*
+* The GPIO Controller supports the following features:
+*	- 4 banks
+*	- Masked writes (There are no masked reads)
+*	- Bypass mode
+*	- Configurable Interrupts (Level/Edge)
+*
+* This driver is intended to be RTOS and processor independent. Any needs for
+* dynamic memory management, threads or thread mutual exclusion, virtual
+* memory, or cache control must be satisfied by the layer above this driver.
+
+* This driver supports all the features listed above, if applicable.
+*
+* <b>Driver Description</b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the GPIO.
+*
+* <b>Interrupts</b>
+*
+* The driver provides interrupt management functions and an interrupt handler.
+* Users of this driver need to provide callback functions. An interrupt handler
+* example is available with the driver.
+*
+* <b>Threads</b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* <b>Asserts</b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* <b>Building the driver</b>
+*
+* The XGpioPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+* <br><br>
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.01a sv   04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+*                     XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+*		      relevant to Zynq device.The interrupts are disabled
+*		      for output pins on all banks during initialization.
+* 1.02a hk   08/22/13 Added low level reset API
+* 2.1   hk   04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+* 2.2	sk	 10/13/14 Used Pin number in Bank instead of pin number
+* 					  passed to APIs. CR# 822636
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+*       ms   03/17/17 Added readme.txt file in examples folder for doxygen
+*                     generation.
+*
+* </pre>
+*
+******************************************************************************/
+#ifndef XGPIOPS_H		/* prevent circular inclusions */
+#define XGPIOPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xgpiops_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Interrupt types
+ *  @{
+ * The following constants define the interrupt types that can be set for each
+ * GPIO pin.
+ */
+#define XGPIOPS_IRQ_TYPE_EDGE_RISING	0x00U  /**< Interrupt on Rising edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_FALLING	0x01U  /**< Interrupt Falling edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_BOTH	0x02U  /**< Interrupt on both edges */
+#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH	0x03U  /**< Interrupt on high level */
+#define XGPIOPS_IRQ_TYPE_LEVEL_LOW	0x04U  /**< Interrupt on low level */
+/*@}*/
+
+#define XGPIOPS_BANK_MAX_PINS		(u32)32 /**< Max pins in a GPIO bank */
+#define XGPIOPS_BANK0			0x00U  /**< GPIO Bank 0 */
+#define XGPIOPS_BANK1			0x01U  /**< GPIO Bank 1 */
+#define XGPIOPS_BANK2			0x02U  /**< GPIO Bank 2 */
+#define XGPIOPS_BANK3			0x03U  /**< GPIO Bank 3 */
+
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+#define XGPIOPS_BANK4			0x04U  /**< GPIO Bank 4 */
+#define XGPIOPS_BANK5			0x05U  /**< GPIO Bank 5 */
+#endif
+
+#define XGPIOPS_MAX_BANKS_ZYNQMP		0x06U  /**< Max banks in a
+										*	Zynq Ultrascale+ MP GPIO device
+										*/
+#define XGPIOPS_MAX_BANKS		0x04U  /**< Max banks in a Zynq GPIO device */
+
+#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP	(u32)174 /**< Max pins in the
+						  *	Zynq Ultrascale+ MP GPIO device
+					      * 0 - 25,  Bank 0
+					      * 26 - 51, Bank 1
+					      *	52 - 77, Bank 2
+					      *	78 - 109, Bank 3
+					      *	110 - 141, Bank 4
+					      *	142 - 173, Bank 5
+					      */
+#define XGPIOPS_DEVICE_MAX_PIN_NUM	(u32)118 /**< Max pins in the Zynq GPIO device
+					      * 0 - 31,  Bank 0
+					      * 32 - 53, Bank 1
+					      *	54 - 85, Bank 2
+					      *	86 - 117, Bank 3
+					      */
+
+/**************************** Type Definitions *******************************/
+
+/****************************************************************************/
+/**
+ * This handler data type allows the user to define a callback function to
+ * handle the interrupts for the GPIO device. The application using this
+ * driver is expected to define a handler of this type, to support interrupt
+ * driven mode. The handler executes in an interrupt context such that minimal
+ * processing should be performed.
+ *
+ * @param	CallBackRef is a callback reference passed in by the upper layer
+ *		when setting the callback functions for a GPIO bank. It is
+ *		passed back to the upper layer when the callback is invoked. Its
+ *		type is not important to the driver component, so it is a void
+ *		pointer.
+ * @param	Bank is the bank for which the interrupt status has changed.
+ * @param	Status is the Interrupt status of the GPIO bank.
+ *
+ *****************************************************************************/
+typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID of device */
+	u32 BaseAddr;		/**< Register base address */
+} XGpioPs_Config;
+
+/**
+ * The XGpioPs driver instance data. The user is required to allocate a
+ * variable of this type for the GPIO device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XGpioPs_Config GpioConfig;	/**< Device configuration */
+	u32 IsReady;			/**< Device is initialized and ready */
+	XGpioPs_Handler Handler;	/**< Status handlers for all banks */
+	void *CallBackRef; 		/**< Callback ref for bank handlers */
+	u32 Platform;			/**< Platform data */
+	u32 MaxPinNum;			/**< Max pins in the GPIO device */
+	u8 MaxBanks;			/**< Max banks in a GPIO device */
+} XGpioPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/* Functions in xgpiops.c */
+s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
+			   u32 EffectiveAddr);
+
+/* Bank APIs in xgpiops.c */
+u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data);
+void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction);
+u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
+u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_GetBankPin(u8 PinNumber,	u8 *BankNumber, u8 *PinNumberInBank);
+
+/* Pin APIs in xgpiops.c */
+u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data);
+void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction);
+u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
+u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin);
+
+/* Diagnostic functions in xgpiops_selftest.c */
+s32 XGpioPs_SelfTest(XGpioPs *InstancePtr);
+
+/* Functions in xgpiops_intr.c */
+/* Bank APIs in xgpiops_intr.c */
+void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank);
+u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
+			  u32 IntrPolarity, u32 IntrOnAny);
+void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
+			  u32 *IntrPolarity, u32 *IntrOnAny);
+void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
+			     XGpioPs_Handler FuncPointer);
+void XGpioPs_IntrHandler(XGpioPs *InstancePtr);
+
+/* Pin APIs in xgpiops_intr.c */
+void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
+u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin);
+
+void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin);
+u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin);
+u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin);
+
+/* Functions in xgpiops_sinit.c */
+XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_g.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..44ac94fc5052471785ec4016b5ca7514b01e7206
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xgpiops.h"
+
+/*
+* The configuration table for devices
+*/
+
+XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_GPIO_0_DEVICE_ID,
+		XPAR_PS7_GPIO_0_BASEADDR
+	}
+};
+
+
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_hw.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_hw.c
new file mode 100644
index 0000000000000000000000000000000000000000..d7a5e00f06e681f427345af88d54fedeef239e73
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_hw.c
@@ -0,0 +1,169 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_hw.c
+* @addtogroup gpiops_v3_1
+* @{
+*
+* This file contains low level GPIO functions.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.02a hk   08/22/13 First Release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops_hw.h"
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/*
+*
+* This function resets the GPIO module by writing reset values to
+* all registers
+*
+* @param	Base address of GPIO module
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XGpioPs_ResetHw(u32 BaseAddress)
+{
+	u32 BankCount;
+	u32 Platform,MaxBanks;
+
+	Platform = XGetPlatform_Info();
+	if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
+		MaxBanks = (u32)6;
+	} else {
+		MaxBanks = (u32)4;
+	}
+	/* Write reset values to all mask data registers */
+	for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) {
+
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
+				 XGPIOPS_DATA_LSW_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
+				 XGPIOPS_DATA_MSW_OFFSET), 0x0U);
+	}
+	/* Write reset values to all output data registers */
+	for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) {
+
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_DATA_BANK_OFFSET) +
+				 XGPIOPS_DATA_OFFSET), 0x0U);
+	}
+
+	/* Reset all registers of all GPIO banks */
+	for(BankCount = 0U; BankCount < (u32)MaxBanks; BankCount++) {
+
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_DIRM_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_OUTEN_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTMASK_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTEN_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTDIS_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTSTS_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTPOL_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTANY_OFFSET), 0x0U);
+	}
+
+	/* Bank 0 Int type */
+	XGpioPs_WriteReg(BaseAddress, XGPIOPS_INTTYPE_OFFSET,
+			XGPIOPS_INTTYPE_BANK0_RESET);
+	/* Bank 1 Int type */
+	XGpioPs_WriteReg(BaseAddress,
+			((u32)XGPIOPS_REG_MASK_OFFSET + (u32)XGPIOPS_INTTYPE_OFFSET),
+			XGPIOPS_INTTYPE_BANK1_RESET);
+	/* Bank 2 Int type */
+	XGpioPs_WriteReg(BaseAddress,
+			(((u32)2 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+			XGPIOPS_INTTYPE_BANK2_RESET);
+	/* Bank 3 Int type */
+	XGpioPs_WriteReg(BaseAddress,
+			(((u32)3 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+			XGPIOPS_INTTYPE_BANK3_RESET);
+
+	if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
+		/* Bank 4 Int type */
+		XGpioPs_WriteReg(BaseAddress,
+				(((u32)4 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+				XGPIOPS_INTTYPE_BANK4_RESET);
+		/* Bank 5 Int type */
+		XGpioPs_WriteReg(BaseAddress,
+				(((u32)5 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+				XGPIOPS_INTTYPE_BANK5_RESET);
+	}
+
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..81e8d6a9ffd1b8ca42f717278bf5dcd4447d973b
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_hw.h
@@ -0,0 +1,164 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_hw.h
+* @addtogroup gpiops_v3_1
+* @{
+*
+* This header file contains the identifiers and basic driver functions (or
+* macros) that can be used to access the device. Other driver functions
+* are defined in xgpiops.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.02a hk   08/22/13 Added low level reset API function prototype and
+*                     related constant definitions
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Corrected reset values of banks.
+* </pre>
+*
+******************************************************************************/
+#ifndef XGPIOPS_HW_H		/* prevent circular inclusions */
+#define XGPIOPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register offsets for the GPIO. Each register is 32 bits.
+ *  @{
+ */
+#define XGPIOPS_DATA_LSW_OFFSET  0x00000000U  /* Mask and Data Register LSW, WO */
+#define XGPIOPS_DATA_MSW_OFFSET  0x00000004U  /* Mask and Data Register MSW, WO */
+#define XGPIOPS_DATA_OFFSET	 0x00000040U  /* Data Register, RW */
+#define XGPIOPS_DATA_RO_OFFSET	 0x00000060U  /* Data Register - Input, RO */
+#define XGPIOPS_DIRM_OFFSET	 0x00000204U  /* Direction Mode Register, RW */
+#define XGPIOPS_OUTEN_OFFSET	 0x00000208U  /* Output Enable Register, RW */
+#define XGPIOPS_INTMASK_OFFSET	 0x0000020CU  /* Interrupt Mask Register, RO */
+#define XGPIOPS_INTEN_OFFSET	 0x00000210U  /* Interrupt Enable Register, WO */
+#define XGPIOPS_INTDIS_OFFSET	 0x00000214U  /* Interrupt Disable Register, WO*/
+#define XGPIOPS_INTSTS_OFFSET	 0x00000218U  /* Interrupt Status Register, RO */
+#define XGPIOPS_INTTYPE_OFFSET	 0x0000021CU  /* Interrupt Type Register, RW */
+#define XGPIOPS_INTPOL_OFFSET	 0x00000220U  /* Interrupt Polarity Register, RW */
+#define XGPIOPS_INTANY_OFFSET	 0x00000224U  /* Interrupt On Any Register, RW */
+/* @} */
+
+/** @name Register offsets for each Bank.
+ *  @{
+ */
+#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U  /* Data/Mask Registers offset */
+#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U  /* Data Registers offset */
+#define XGPIOPS_REG_MASK_OFFSET  0x00000040U  /* Registers offset */
+/* @} */
+
+/* For backwards compatibility */
+#define XGPIOPS_BYPM_MASK_OFFSET	(u32)0x40
+
+/** @name Interrupt type reset values for each bank
+ *  @{
+ */
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+#define XGPIOPS_INTTYPE_BANK0_RESET  0x03FFFFFFU  /* Resets specific to Zynq Ultrascale+ MP */
+#define XGPIOPS_INTTYPE_BANK1_RESET  0x03FFFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET  0x03FFFFFFU
+#else
+#define XGPIOPS_INTTYPE_BANK0_RESET  0xFFFFFFFFU  /* Resets specific to Zynq */
+#define XGPIOPS_INTTYPE_BANK1_RESET  0x003FFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET  0xFFFFFFFFU
+#endif
+
+#define XGPIOPS_INTTYPE_BANK3_RESET  0xFFFFFFFFU  /* Reset common to both platforms */
+#define XGPIOPS_INTTYPE_BANK4_RESET  0xFFFFFFFFU  /* Resets specific to Zynq Ultrascale+ MP */
+#define XGPIOPS_INTTYPE_BANK5_RESET  0xFFFFFFFFU
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param	BaseAddr is the base address of the device.
+* @param	RegOffset is the register offset to be read.
+*
+* @return	The 32-bit value of the register
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XGpioPs_ReadReg(BaseAddr, RegOffset)		\
+		Xil_In32((BaseAddr) + (u32)(RegOffset))
+
+/****************************************************************************/
+/**
+*
+* This macro writes to the given register.
+*
+* @param	BaseAddr is the base address of the device.
+* @param	RegOffset is the offset of the register to be written.
+* @param	Data is the 32-bit value to write to the register.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data)	\
+		Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes ******************************/
+
+void XGpioPs_ResetHw(u32 BaseAddress);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XGPIOPS_HW_H */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_intr.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_intr.c
new file mode 100644
index 0000000000000000000000000000000000000000..f69a71828b0608d92803b3079c5c168af9b59447
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_intr.c
@@ -0,0 +1,731 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_intr.c
+* @addtogroup gpiops_v3_1
+* @{
+*
+* This file contains functions related to GPIO interrupt handling.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/18/10 First Release
+* 2.2	sk	 10/13/14 Used Pin number in Bank instead of pin number
+* 					  passed to API's. CR# 822636
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void StubHandler(void *CallBackRef, u32 Bank, u32 Status);
+
+/****************************************************************************/
+/**
+*
+* This function enables the interrupts for the specified pins in the specified
+* bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	Mask is the bit mask of the pins for which interrupts are to
+*		be enabled. Bit positions of 1 will be enabled. Bit positions
+*		of 0 will keep the previous setting.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTEN_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the interrupt for the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt is to be enabled.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg = 0U;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrReg = ((u32)1 << (u32)PinNumber);
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTEN_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables the interrupts for the specified pins in the specified
+* bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	Mask is the bit mask of the pins for which interrupts are
+*		to be disabled. Bit positions of 1 will be disabled. Bit
+*		positions of 0 will keep the previous setting.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTDIS_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables the interrupts for the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt is to be disabled.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg = 0U;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrReg =  ((u32)1 << (u32)PinNumber);
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTDIS_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the interrupt enable status for a bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return	Enabled interrupt(s) in a 32-bit format. Bit positions with 1
+*		indicate that the interrupt for that pin is enabled, bit
+*		positions with 0 indicate that the interrupt for that pin is
+*		disabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank)
+{
+	u32 IntrMask;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+	IntrMask = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				    ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				    XGPIOPS_INTMASK_OFFSET);
+	return (~IntrMask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns whether interrupts are enabled for the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt enable status
+*		is to be known.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return
+*		- TRUE if the interrupt is enabled.
+*		- FALSE if the interrupt is disabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrReg  = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				    ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				    XGPIOPS_INTMASK_OFFSET);
+
+	return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? FALSE : TRUE);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns interrupt status read from Interrupt Status Register.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return	The value read from Interrupt Status Register.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+	return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				XGPIOPS_INTSTS_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns interrupt enable status of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt enable status
+*		is to be known.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return
+*		- TRUE if the interrupt has occurred.
+*		- FALSE if the interrupt has not occurred.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				   XGPIOPS_INTSTS_OFFSET);
+
+	return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? TRUE : FALSE);
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears pending interrupt(s) with the provided mask. This
+* function should be called after the software has serviced the interrupts
+* that are pending.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	Mask is the mask of the interrupts to be cleared. Bit positions
+*		of 1 will be cleared. Bit positions of 0 will not change the
+*		previous interrupt status.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	/* Clear the currently pending interrupts. */
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTSTS_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears the specified pending interrupt. This function should be
+* called after the software has serviced the interrupts that are pending.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt status is to be
+*		cleared. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	/* Clear the specified pending interrupts. */
+	IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				   XGPIOPS_INTSTS_OFFSET);
+
+	IntrReg &= ((u32)1 << PinNumber);
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTSTS_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for setting the Interrupt Type, Interrupt Polarity and
+* Interrupt On Any for the specified GPIO Bank pins.
+*
+* @param	InstancePtr is a pointer to an XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	IntrType is the 32 bit mask of the interrupt type.
+*		0 means Level Sensitive and 1 means Edge Sensitive.
+* @param	IntrPolarity is the 32 bit mask of the interrupt polarity.
+*		0 means Active Low or Falling Edge and 1 means Active High or
+*		Rising Edge.
+* @param	IntrOnAny is the 32 bit mask of the interrupt trigger for
+*		edge triggered interrupts. 0 means trigger on single edge using
+*		the configured interrupt polarity and 1 means  trigger on both
+*		edges.
+*
+* @return	None.
+*
+* @note		This function is used for setting the interrupt related
+*		properties of all the pins in the specified bank. The previous
+*		state of the pins is not maintained.
+*		To change the Interrupt properties of a single GPIO pin, use the
+*		function XGpioPs_SetPinIntrType().
+*
+*****************************************************************************/
+void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
+			  u32 IntrPolarity, u32 IntrOnAny)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTTYPE_OFFSET, IntrType);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTPOL_OFFSET, IntrPolarity);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTANY_OFFSET, IntrOnAny);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for getting the Interrupt Type, Interrupt Polarity and
+* Interrupt On Any for the specified GPIO Bank pins.
+*
+* @param	InstancePtr is a pointer to an XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	IntrType returns the 32 bit mask of the interrupt type.
+*		0 means Level Sensitive and 1 means Edge Sensitive.
+* @param	IntrPolarity returns the 32 bit mask of the interrupt
+*		polarity. 0 means Active Low or Falling Edge and 1 means
+*		Active High or Rising Edge.
+* @param	IntrOnAny returns the 32 bit mask of the interrupt trigger for
+*		edge triggered interrupts. 0 means trigger on single edge using
+*		the configured interrupt polarity and 1 means trigger on both
+*		edges.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
+			  u32 *IntrPolarity, u32 *IntrOnAny)
+
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	*IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				     ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				     XGPIOPS_INTTYPE_OFFSET);
+
+	*IntrPolarity = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+					 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+					 XGPIOPS_INTPOL_OFFSET);
+
+	*IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				      ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				      XGPIOPS_INTANY_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for setting the IRQ Type of a single GPIO pin.
+*
+* @param	InstancePtr is a pointer to an XGpioPs instance.
+* @param	Pin is the pin number whose IRQ type is to be set.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param	IrqType is the IRQ type for GPIO Pin. Use XGPIOPS_IRQ_TYPE_*
+*		defined in xgpiops.h to specify the IRQ type.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType)
+{
+	u32 IntrTypeReg;
+	u32 IntrPolReg;
+	u32 IntrOnAnyReg;
+	u8 Bank;
+	u8 PinNumber;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+	Xil_AssertVoid(IrqType <= XGPIOPS_IRQ_TYPE_LEVEL_LOW);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrTypeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				       ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				       XGPIOPS_INTTYPE_OFFSET);
+
+	IntrPolReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				      ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				      XGPIOPS_INTPOL_OFFSET);
+
+	IntrOnAnyReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+					((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+					XGPIOPS_INTANY_OFFSET);
+
+	switch (IrqType) {
+		case XGPIOPS_IRQ_TYPE_EDGE_RISING:
+			IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+			IntrPolReg |= ((u32)1 << (u32)PinNumber);
+			IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
+			break;
+		case XGPIOPS_IRQ_TYPE_EDGE_FALLING:
+			IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+			IntrPolReg &= ~((u32)1 << (u32)PinNumber);
+			IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
+			break;
+		case XGPIOPS_IRQ_TYPE_EDGE_BOTH:
+			IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+			IntrOnAnyReg |= ((u32)1 << (u32)PinNumber);
+			break;
+		case XGPIOPS_IRQ_TYPE_LEVEL_HIGH:
+			IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
+			IntrPolReg |= ((u32)1 << (u32)PinNumber);
+			break;
+		case XGPIOPS_IRQ_TYPE_LEVEL_LOW:
+			IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
+			IntrPolReg &= ~((u32)1 << (u32)PinNumber);
+			break;
+		default:
+			/**< Default statement is added for MISRA C compliance. */
+			break;
+	}
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTTYPE_OFFSET, IntrTypeReg);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTPOL_OFFSET, IntrPolReg);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTANY_OFFSET, IntrOnAnyReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the IRQ Type of a given GPIO pin.
+*
+* @param	InstancePtr is a pointer to an XGpioPs instance.
+* @param	Pin is the pin number whose IRQ type is to be obtained.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return	None.
+*
+* @note		Use XGPIOPS_IRQ_TYPE_* defined in xgpiops.h for the IRQ type
+*		returned by this function.
+*
+*****************************************************************************/
+u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u32 IntrType;
+	u32 IntrPol;
+	u32 IntrOnAny;
+	u8 Bank;
+	u8 PinNumber;
+	u8 IrqType;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				    ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				    XGPIOPS_INTTYPE_OFFSET) & ((u32)1 << PinNumber);
+
+	if (IntrType == ((u32)1 << PinNumber)) {
+
+		IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				     ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				     XGPIOPS_INTANY_OFFSET) & ((u32)1 << PinNumber);
+
+		IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				   XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
+
+
+		if (IntrOnAny == ((u32)1 << PinNumber)) {
+			IrqType = XGPIOPS_IRQ_TYPE_EDGE_BOTH;
+		} else if (IntrPol == ((u32)1 << PinNumber)) {
+			IrqType = XGPIOPS_IRQ_TYPE_EDGE_RISING;
+		} else {
+			IrqType = XGPIOPS_IRQ_TYPE_EDGE_FALLING;
+		}
+	} else {
+
+		IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				   XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
+
+		if (IntrPol == ((u32)1 << PinNumber)) {
+			IrqType = XGPIOPS_IRQ_TYPE_LEVEL_HIGH;
+		} else {
+			IrqType = XGPIOPS_IRQ_TYPE_LEVEL_LOW;
+		}
+	}
+
+	return IrqType;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the status callback function. The callback function is
+* called by the  XGpioPs_IntrHandler when an interrupt occurs.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+* @param	FuncPtr is the pointer to the callback function.
+*
+*
+* @return	None.
+*
+* @note		The handler is called within interrupt context, so it should do
+*		its work quickly and queue potentially time-consuming work to a
+*		task-level thread.
+*
+******************************************************************************/
+void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
+				 XGpioPs_Handler FuncPointer)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FuncPointer != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->Handler = FuncPointer;
+	InstancePtr->CallBackRef = CallBackRef;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is the interrupt handler for GPIO interrupts.It checks the
+* interrupt status registers of all the banks to determine the actual bank in
+* which an interrupt has been triggered. It then calls the upper layer callback
+* handler set by the function XGpioPs_SetBankHandler(). The callback is called
+* when an interrupt
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+*
+* @return	None.
+*
+* @note		This function does not save and restore the processor context
+*		such that the user must provide this processing.
+*
+******************************************************************************/
+void XGpioPs_IntrHandler(XGpioPs *InstancePtr)
+{
+	u8 Bank;
+	u32 IntrStatus;
+	u32 IntrEnabled;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	for (Bank = 0U; Bank < InstancePtr->MaxBanks; Bank++) {
+		IntrStatus = XGpioPs_IntrGetStatus(InstancePtr, Bank);
+		if (IntrStatus != (u32)0) {
+			IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr,
+							      Bank);
+			XGpioPs_IntrClear((XGpioPs *)InstancePtr, Bank,
+							(IntrStatus & IntrEnabled));
+			InstancePtr->Handler(InstancePtr->
+					     CallBackRef, Bank,
+					     (IntrStatus & IntrEnabled));
+		}
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This is a stub for the status callback. The stub is here in case the upper
+* layers do not set the handler.
+*
+* @param	CallBackRef is a pointer to the upper layer callback reference
+* @param	Bank is the GPIO Bank in which an interrupt occurred.
+* @param	Status is the Interrupt status of the GPIO bank.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void StubHandler(void *CallBackRef, u32 Bank, u32 Status)
+{
+	(void) CallBackRef;
+	(void) Bank;
+	(void) Status;
+
+	Xil_AssertVoidAlways();
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_selftest.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_selftest.c
new file mode 100644
index 0000000000000000000000000000000000000000..da1973a2d9d52928171a9d4e447807421fe22da9
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_selftest.c
@@ -0,0 +1,133 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_selftest.c
+* @addtogroup gpiops_v3_1
+* @{
+*
+* This file contains a diagnostic self-test function for the XGpioPs driver.
+*
+* Read xgpiops.h file for more information.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/18/10 First Release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xgpiops.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function runs a self-test on the GPIO driver/device. This function
+* does a register read/write test on some of the Interrupt Registers.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+*
+* @return
+*		- XST_SUCCESS if the self-test passed.
+* 		- XST_FAILURE otherwise.
+*
+*
+******************************************************************************/
+s32 XGpioPs_SelfTest(XGpioPs *InstancePtr)
+{
+	s32 Status = XST_SUCCESS;
+	u32 IntrEnabled;
+	u32 CurrentIntrType = 0U;
+	u32 CurrentIntrPolarity = 0U;
+	u32 CurrentIntrOnAny = 0U;
+	u32 IntrType = 0U;
+	u32 IntrPolarity = 0U;
+	u32 IntrOnAny = 0U;
+	u32 IntrTestValue = 0x22U;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Disable the Interrupts for Bank 0 . */
+	IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr, XGPIOPS_BANK0);
+	XGpioPs_IntrDisable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
+
+	/*
+	 * Get the Current Interrupt properties for Bank 0.
+	 * Set them to a known value, read it back and compare.
+	 */
+	XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &CurrentIntrType,
+			     &CurrentIntrPolarity, &CurrentIntrOnAny);
+
+	XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, IntrTestValue,
+			     IntrTestValue, IntrTestValue);
+
+	XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &IntrType,
+			     &IntrPolarity, &IntrOnAny);
+
+	if ((IntrType != IntrTestValue) && (IntrPolarity != IntrTestValue) &&
+	    (IntrOnAny != IntrTestValue)) {
+
+		Status = XST_FAILURE;
+	}
+
+	/*
+	 * Restore the contents of all the interrupt registers modified in this
+	 * test.
+	 */
+	XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, CurrentIntrType,
+			     CurrentIntrPolarity, CurrentIntrOnAny);
+
+	XGpioPs_IntrEnable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
+
+	return Status;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_sinit.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..2ca008373d51da15a266af01bf72e11b5be9b222
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/gpiops_v3_2/src/xgpiops_sinit.c
@@ -0,0 +1,101 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_sinit.c
+* @addtogroup gpiops_v3_1
+* @{
+*
+* This file contains the implementation of the XGpioPs driver's static
+* initialization functionality.
+*
+* @note		None.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* This function looks for the device configuration based on the unique device
+* ID. The table XGpioPs_ConfigTable[] contains the configuration information
+* for each device in the system.
+*
+* @param	DeviceId is the unique device ID of the device being looked up.
+*
+* @return	A pointer to the configuration table entry corresponding to the
+*		given device ID, or NULL if no match is found.
+*
+* @note		None.
+*
+******************************************************************************/
+XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId)
+{
+	XGpioPs_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XGPIOPS_NUM_INSTANCES; Index++) {
+		if (XGpioPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XGpioPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XGpioPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/Makefile b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..8c16c35aef36d4f0fda42e7679b98a8941e04a80
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xiicps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling iicps"
+
+xiicps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xiicps_includes
+
+xiicps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps.c
new file mode 100644
index 0000000000000000000000000000000000000000..1c681915269ccb4c5310d8eb6bb9ae88d4a3d84a
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps.c
@@ -0,0 +1,333 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps.c
+* @addtogroup iicps_v3_0
+* @{
+*
+* Contains implementation of required functions for the XIicPs driver.
+* See xiicps.h for detailed description of the device and driver.
+*
+* <pre> MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- --------------------------------------------
+* 1.00a drg/jz  01/30/10 First release
+* 1.00a sdm     09/21/11 Updated the InstancePtr->Options in the
+*			 XIicPs_CfgInitialize by calling XIicPs_GetOptions.
+* 2.1   hk      04/25/14 Explicitly reset CR and clear FIFO in Abort function
+*                        and state the same in the comments. CR# 784254.
+*                        Fix for CR# 761060 - provision for repeated start.
+* 2.3	sk		10/07/14 Repeated start feature removed.
+* 3.0	sk		11/03/14 Modified TimeOut Register value to 0xFF
+* 						 in XIicPs_Reset.
+*				12/06/14 Implemented Repeated start feature.
+*				01/31/15 Modified the code according to MISRAC 2012 Compliant.
+* 3.3   kvn		05/05/16 Modified latest code for MISRA-C:2012 Compliance.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+static void StubHandler(void *CallBackRef, u32 StatusEvent);
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XIicPs instance such that the driver is ready to use.
+*
+* The state of the device after initialization is:
+*   - Device is disabled
+*   - Slave mode
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	ConfigPtr is a reference to a structure containing information
+*		about a specific IIC device. This function initializes an
+*		InstancePtr object for a specific device specified by the
+*		contents of Config.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, use
+*		ConfigPtr->BaseAddress for this parameter, passing the physical
+*		address instead.
+*
+* @return	The return value is XST_SUCCESS if successful.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config *ConfigPtr,
+				  u32 EffectiveAddr)
+{
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * Set some default values.
+	 */
+	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
+	InstancePtr->StatusHandler = StubHandler;
+	InstancePtr->CallBackRef = NULL;
+
+	InstancePtr->IsReady = (u32)XIL_COMPONENT_IS_READY;
+
+	/*
+	 * Reset the IIC device to get it into its initial state. It is expected
+	 * that device configuration will take place after this initialization
+	 * is done, but before the device is started.
+	 */
+	XIicPs_Reset(InstancePtr);
+
+	/*
+	 * Keep a copy of what options this instance has.
+	 */
+	InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
+
+	/* Initialize repeated start flag to 0 */
+	InstancePtr->IsRepeatedStart = 0;
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Check whether the I2C bus is busy
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return
+* 		- TRUE if the bus is busy.
+*		- FALSE if the bus is not busy.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XIicPs_BusIsBusy(XIicPs *InstancePtr)
+{
+	u32 StatusReg;
+	s32	Status;
+
+	StatusReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					   XIICPS_SR_OFFSET);
+	if ((StatusReg & XIICPS_SR_BA_MASK) != 0x0U) {
+		Status = (s32)TRUE;
+	}else {
+		Status = (s32)FALSE;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This is a stub for the status callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param	CallBackRef is a pointer to the upper layer callback reference.
+* @param	StatusEvent is the event that just occurred.
+* @param	ByteCount is the number of bytes transferred up until the event
+*		occurred.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void StubHandler(void *CallBackRef, u32 StatusEvent)
+{
+	(void) ((void *)CallBackRef);
+	(void) StatusEvent;
+	Xil_AssertVoidAlways();
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Aborts a transfer in progress by resetting the FIFOs. The byte counts are
+* cleared.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XIicPs_Abort(XIicPs *InstancePtr)
+{
+	u32 IntrMaskReg;
+	u32 IntrStatusReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Enter a critical section, so disable the interrupts while we clear
+	 * the FIFO and the status register.
+	 */
+	IntrMaskReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					   XIICPS_IMR_OFFSET);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_IDR_OFFSET, XIICPS_IXR_ALL_INTR_MASK);
+
+	/*
+	 * Reset the settings in config register and clear the FIFOs.
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
+			  (u32)XIICPS_CR_RESET_VALUE | (u32)XIICPS_CR_CLR_FIFO_MASK);
+
+	/*
+	 * Read, then write the interrupt status to make sure there are no
+	 * pending interrupts.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					 XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Restore the interrupt state.
+	 */
+	IntrMaskReg = (u32)XIICPS_IXR_ALL_INTR_MASK & (~IntrMaskReg);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_IER_OFFSET, IntrMaskReg);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Resets the IIC device. Reset must only be called after the driver has been
+* initialized. The configuration of the device after reset is the same as its
+* configuration after initialization.  Any data transfer that is in progress is
+* aborted.
+*
+* The upper layer software is responsible for re-configuring (if necessary)
+* and reenabling interrupts for the IIC device after the reset.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XIicPs_Reset(XIicPs *InstancePtr)
+{
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Abort any transfer that is in progress.
+	 */
+	XIicPs_Abort(InstancePtr);
+
+	/*
+	 * Reset any values so the software state matches the hardware device.
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
+			  XIICPS_CR_RESET_VALUE);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_TIME_OUT_OFFSET, XIICPS_TO_RESET_VALUE);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_IDR_OFFSET,
+			  XIICPS_IXR_ALL_INTR_MASK);
+
+}
+/*****************************************************************************/
+/**
+* Put more data into the transmit FIFO, number of bytes is ether expected
+* number of bytes for this transfer or available space in FIFO, which ever
+* is less.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	Number of bytes left for this instance.
+*
+* @note		This is function is shared by master and slave.
+*
+******************************************************************************/
+s32 TransmitFifoFill(XIicPs *InstancePtr)
+{
+	u8 AvailBytes;
+	s32 LoopCnt;
+	s32 NumBytesToSend;
+
+	/*
+	 * Determine number of bytes to write to FIFO.
+	 */
+	AvailBytes = (u8)XIICPS_FIFO_DEPTH -
+		(u8)XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					   XIICPS_TRANS_SIZE_OFFSET);
+
+	if (InstancePtr->SendByteCount > (s32)AvailBytes) {
+		NumBytesToSend = (s32)AvailBytes;
+	} else {
+		NumBytesToSend = InstancePtr->SendByteCount;
+	}
+
+	/*
+	 * Fill FIFO with amount determined above.
+	 */
+	for (LoopCnt = 0; LoopCnt < NumBytesToSend; LoopCnt++) {
+		XIicPs_SendByte(InstancePtr);
+	}
+
+	return InstancePtr->SendByteCount;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps.h
new file mode 100644
index 0000000000000000000000000000000000000000..a7b956f64a11a963435455c09b6a3b77047626b1
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps.h
@@ -0,0 +1,423 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps.h
+* @addtogroup iicps_v3_0
+* @{
+* @details
+*
+* This is an implementation of IIC driver in the PS block. The device can
+* be either a master or a slave on the IIC bus. This implementation supports
+* both interrupt mode transfer and polled mode transfer. Only 7-bit address
+* is used in the driver, although the hardware also supports 10-bit address.
+*
+* IIC is a 2-wire serial interface.  The master controls the clock, so it can
+* regulate when it wants to send or receive data. The slave is under control of
+* the master, it must respond quickly since it has no control of the clock and
+* must send/receive data as fast or as slow as the master does.
+*
+* The higher level software must implement a higher layer protocol to inform
+* the slave what to send to the master.
+*
+* <b>Initialization & Configuration</b>
+*
+* The XIicPs_Config structure is used by the driver to configure itself. This
+* configuration structure is typically created by the tool-chain based on HW
+* build properties.
+*
+* To support multiple runtime loading and initialization strategies employed by
+* various operating systems, the driver instance can be initialized in the
+* following way:
+*
+*    - XIicPs_LookupConfig(DeviceId) - Use the device identifier to find
+*      the static configuration structure defined in xiicps_g.c. This is
+*      setup by the tools. For some operating systems the config structure
+*      will be initialized by the software and this call is not needed.
+*
+*   - XIicPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+*     configuration structure provided by the caller. If running in a
+*     system with address translation, the provided virtual memory base
+*     address replaces the physical address in the configuration
+*     structure.
+*
+* <b>Multiple Masters</b>
+*
+* More than one master can exist, bus arbitration is defined in the IIC
+* standard. Lost of arbitration causes arbitration loss interrupt on the device.
+*
+* <b>Multiple Slaves</b>
+*
+* Multiple slaves are supported by selecting them with unique addresses. It is
+* up to the system designer to be sure all devices on the IIC bus have
+* unique addresses.
+*
+* <b>Addressing</b>
+*
+* The IIC hardware can use 7 or 10 bit addresses.  The driver provides the
+* ability to control which address size is sent in messages as a master to a
+* slave device.
+*
+* <b>FIFO Size </b>
+* The hardware FIFO is 32 bytes deep. The user must know the limitations of
+* other IIC devices on the bus. Some are only able to receive a limited number
+* of bytes in a single transfer.
+*
+* <b>Data Rates</b>
+*
+* The data rate is set by values in the control register. The formula for
+* determining the correct register values is:
+* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
+*
+* When the device is configured as a slave, the slck setting controls the
+* sample rate and so must be set to be at least as fast as the fastest scl
+* expected to be seen in the system.
+*
+* <b>Polled Mode Operation</b>
+*
+* This driver supports polled mode transfers.
+*
+* <b>Interrupts</b>
+*
+* The user must connect the interrupt handler of the driver,
+* XIicPs_InterruptHandler to an interrupt system such that it will be called
+* when an interrupt occurs. This function does not save and restore the
+* processor context such that the user must provide this processing.
+*
+* The driver handles the following interrupts:
+* - Transfer complete
+* - More Data
+* - Transfer not Acknowledged
+* - Transfer Time out
+* - Monitored slave ready - master mode only
+* - Receive Overflow
+* - Transmit FIFO overflow
+* - Receive FIFO underflow
+* - Arbitration lost
+*
+* <b>Bus Busy</b>
+*
+* Bus busy is checked before the setup of a master mode device, to avoid
+* unnecessary arbitration loss interrupt.
+*
+* <b>RTOS Independence</b>
+*
+* This driver is intended to be RTOS and processor independent.  It works with
+* physical addresses only.  Any needs for dynamic memory management, threads or
+* thread mutual exclusion, virtual memory, or cache control must be satisfied by
+* the layer above this driver.
+*
+*<b>Repeated Start</b>
+*
+* The I2C controller does not indicate completion of a receive transfer if HOLD
+* bit is set. Due to this errata, repeated start cannot be used if a receive
+* transfer is followed by any other transfer.
+*
+* <pre> MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/08 First release
+* 1.00a sdm     09/21/11 Fixed an issue in the XIicPs_SetOptions and
+*			 XIicPs_ClearOptions where the InstancePtr->Options
+*			 was not updated correctly.
+* 			 Updated the InstancePtr->Options in the
+*			 XIicPs_CfgInitialize by calling XIicPs_GetOptions.
+*			 Updated the XIicPs_SetupMaster to not check for
+*			 Bus Busy condition when the Hold Bit is set.
+*			 Removed some unused variables.
+* 1.01a sg      03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
+*			 check for transfer completion is added, which indicates
+*			 the completion of current transfer.
+* 1.02a sg	08/29/12 Updated the logic to arrive at the best divisors
+*			 to achieve I2C clock with minimum error for
+*			 CR #674195
+* 1.03a hk  05/04/13 Initialized BestDivA and BestDivB to 0.
+*			 This is fix for CR#704398 to remove warning.
+* 2.0   hk  03/07/14 Added check for error status in the while loop that
+*                    checks for completion.
+*                    (XIicPs_MasterSendPolled function). CR# 762244, 764875.
+*                    Limited frequency set when 100KHz or 400KHz is
+*                    selected. This is a hardware limitation. CR#779290.
+* 2.1   hk  04/24/14 Fix for CR# 789821 to handle >14 byte transfers.
+*                    Explicitly reset CR and clear FIFO in Abort function
+*                    and state the same in the comments. CR# 784254.
+*                    Fix for CR# 761060 - provision for repeated start.
+* 2.2   hk  08/23/14 Slave monitor mode changes - clear FIFO, enable
+*                    read mode and clear transfer size register.
+*                    Disable NACK to avoid interrupts on each retry.
+* 2.3	sk	10/07/14 Repeated start feature deleted.
+* 3.0	sk	11/03/14 Modified TimeOut Register value to 0xFF
+* 					 in XIicPs_Reset.
+* 			12/06/14 Implemented Repeated start feature.
+*			01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*			02/18/15 Implemented larger data transfer using repeated start
+*					  in Zynq UltraScale MP.
+* 3.3   kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
+*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+*                    generation.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIICPS_H       /* prevent circular inclusions */
+#define XIICPS_H       /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xiicps_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Configuration options
+ *
+ * The following options may be specified or retrieved for the device and
+ * enable/disable additional features of the IIC.  Each of the options
+ * are bit fields, so more than one may be specified.
+ *
+ * @{
+ */
+#define XIICPS_7_BIT_ADDR_OPTION	0x01U  /**< 7-bit address mode */
+#define XIICPS_10_BIT_ADDR_OPTION	0x02U  /**< 10-bit address mode */
+#define XIICPS_SLAVE_MON_OPTION		0x04U  /**< Slave monitor mode */
+#define XIICPS_REP_START_OPTION		0x08U  /**< Repeated Start */
+/*@}*/
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that are passed to an application
+ * event handler from the driver.  These constants are bit masks such that
+ * more than one event can be passed to the handler.
+ *
+ * @{
+ */
+#define XIICPS_EVENT_COMPLETE_SEND	0x0001U  /**< Transmit Complete Event*/
+#define XIICPS_EVENT_COMPLETE_RECV	0x0002U  /**< Receive Complete Event*/
+#define XIICPS_EVENT_TIME_OUT		0x0004U  /**< Transfer timed out */
+#define XIICPS_EVENT_ERROR			0x0008U  /**< Receive error */
+#define XIICPS_EVENT_ARB_LOST		0x0010U  /**< Arbitration lost */
+#define XIICPS_EVENT_NACK			0x0020U  /**< NACK Received */
+#define XIICPS_EVENT_SLAVE_RDY		0x0040U  /**< Slave ready */
+#define XIICPS_EVENT_RX_OVR			0x0080U  /**< RX overflow */
+#define XIICPS_EVENT_TX_OVR			0x0100U  /**< TX overflow */
+#define XIICPS_EVENT_RX_UNF			0x0200U  /**< RX underflow */
+/*@}*/
+
+/** @name Role constants
+ *
+ * These constants are used to pass into the device setup routines to
+ * set up the device according to transfer direction.
+ */
+#define SENDING_ROLE		1  /**< Transfer direction is sending */
+#define RECVING_ROLE		0  /**< Transfer direction is receiving */
+
+/* Maximum transfer size */
+#define XIICPS_MAX_TRANSFER_SIZE	(u32)(255U - 3U)
+
+/**************************** Type Definitions *******************************/
+
+/**
+* The handler data type allows the user to define a callback function to
+* respond to interrupt events in the system. This function is executed
+* in interrupt context, so amount of processing should be minimized.
+*
+* @param	CallBackRef is the callback reference passed in by the upper
+*		layer when setting the callback functions, and passed back to
+*		the upper layer when the callback is invoked. Its type is
+*		not important to the driver, so it is a void pointer.
+* @param	StatusEvent indicates one or more status events that occurred.
+*/
+typedef void (*XIicPs_IntrHandler) (void *CallBackRef, u32 StatusEvent);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;     /**< Unique ID  of device */
+	u32 BaseAddress;  /**< Base address of the device */
+	u32 InputClockHz; /**< Input clock frequency */
+} XIicPs_Config;
+
+/**
+ * The XIicPs driver instance data. The user is required to allocate a
+ * variable of this type for each IIC device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XIicPs_Config Config;	/* Configuration structure */
+	u32 IsReady;		/* Device is initialized and ready */
+	u32 Options;		/* Options set in the device */
+
+	u8 *SendBufferPtr;	/* Pointer to send buffer */
+	u8 *RecvBufferPtr;	/* Pointer to recv buffer */
+	s32 SendByteCount;	/* Number of bytes still expected to send */
+	s32 RecvByteCount;	/* Number of bytes still expected to receive */
+	s32 CurrByteCount;	/* No. of bytes expected in current transfer */
+
+	s32 UpdateTxSize;	/* If tx size register has to be updated */
+	s32 IsSend;		/* Whether master is sending or receiving */
+	s32 IsRepeatedStart;	/* Indicates if user set repeated start */
+
+	XIicPs_IntrHandler StatusHandler;  /* Event handler function */
+	void *CallBackRef;	/* Callback reference for event handler */
+} XIicPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/****************************************************************************/
+/*
+*
+* Place one byte into the transmit FIFO.
+*
+* @param	InstancePtr is the instance of IIC
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XIicPs_SendByte(XIicPs *InstancePtr)
+*
+*****************************************************************************/
+#define XIicPs_SendByte(InstancePtr)					\
+{									\
+	u8 Data;							\
+	Data = *((InstancePtr)->SendBufferPtr);				\
+	 XIicPs_Out32((InstancePtr)->Config.BaseAddress			\
+			 + (u32)(XIICPS_DATA_OFFSET), 			\
+					(u32)(Data));			\
+	(InstancePtr)->SendBufferPtr += 1;				\
+	(InstancePtr)->SendByteCount -= 1;\
+}
+
+/****************************************************************************/
+/*
+*
+* Receive one byte from FIFO.
+*
+* @param	InstancePtr is the instance of IIC
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		u8 XIicPs_RecvByte(XIicPs *InstancePtr)
+*
+*****************************************************************************/
+#define XIicPs_RecvByte(InstancePtr)					\
+{									\
+	u8 *Data, Value;						\
+	Value = (u8)(XIicPs_In32((InstancePtr)->Config.BaseAddress	\
+		  + (u32)XIICPS_DATA_OFFSET));  			\
+	Data = &Value;							\
+	*(InstancePtr)->RecvBufferPtr = *Data;				\
+	(InstancePtr)->RecvBufferPtr += 1;				\
+	 (InstancePtr)->RecvByteCount --; 				\
+}
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Function for configuration lookup, in xiicps_sinit.c
+ */
+XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Functions for general setup, in xiicps.c
+ */
+s32 XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config * ConfigPtr,
+				  u32 EffectiveAddr);
+
+void XIicPs_Abort(XIicPs *InstancePtr);
+void XIicPs_Reset(XIicPs *InstancePtr);
+
+s32 XIicPs_BusIsBusy(XIicPs *InstancePtr);
+s32 TransmitFifoFill(XIicPs *InstancePtr);
+
+/*
+ * Functions for interrupts, in xiicps_intr.c
+ */
+void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef,
+				  XIicPs_IntrHandler FunctionPtr);
+
+/*
+ * Functions for device as master, in xiicps_master.c
+ */
+void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		u16 SlaveAddr);
+void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		u16 SlaveAddr);
+s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		u16 SlaveAddr);
+s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		u16 SlaveAddr);
+void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr);
+void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr);
+void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr);
+
+/*
+ * Functions for device as slave, in xiicps_slave.c
+ */
+void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr);
+void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+s32 XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr);
+
+/*
+ * Functions for selftest, in xiicps_selftest.c
+ */
+s32 XIicPs_SelfTest(XIicPs *InstancePtr);
+
+/*
+ * Functions for setting and getting data rate, in xiicps_options.c
+ */
+s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options);
+s32 XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options);
+u32 XIicPs_GetOptions(XIicPs *InstancePtr);
+
+s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz);
+u32 XIicPs_GetSClk(XIicPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_g.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..f1fff951ba928240b01332c5d5e704f443611567
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_g.c
@@ -0,0 +1,61 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xiicps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XIicPs_Config XIicPs_ConfigTable[XPAR_XIICPS_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_I2C_0_DEVICE_ID,
+		XPAR_PS7_I2C_0_BASEADDR,
+		XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PS7_I2C_1_DEVICE_ID,
+		XPAR_PS7_I2C_1_BASEADDR,
+		XPAR_PS7_I2C_1_I2C_CLK_FREQ_HZ
+	}
+};
+
+
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_hw.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_hw.c
new file mode 100644
index 0000000000000000000000000000000000000000..a1dba8e624a200984470f3cc045e06e004a94ff1
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_hw.c
@@ -0,0 +1,111 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_hw.c
+* @addtogroup iicps_v3_0
+* @{
+*
+* Contains implementation of required functions for providing the reset sequence
+* to the i2c interface
+*
+* <pre> MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- --------------------------------------------
+* 1.04a kpc     11/07/13 First release
+* 3.0	sk		11/03/14 Modified TimeOut Register value to 0xFF
+*				01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps_hw.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given I2c interface by
+* configuring the appropriate control bits in the I2c specifc registers
+* the i2cps reset squence involves the following steps
+*	Disable all the interuupts
+*	Clear the status
+*	Clear FIFO's and disable hold bit
+*	Clear the line status
+*	Update relevant config registers with reset values
+*
+* @param   BaseAddress of the interface
+*
+* @return N/A
+*
+* @note
+* This function will not modify the slcr registers that are relavant for
+* I2c controller
+******************************************************************************/
+void XIicPs_ResetHw(u32 BaseAddress)
+{
+	u32 RegVal;
+
+	/* Disable all the interrupts */
+	XIicPs_WriteReg(BaseAddress, XIICPS_IDR_OFFSET, XIICPS_IXR_ALL_INTR_MASK);
+	/* Clear the interrupt status */
+	RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(BaseAddress, XIICPS_ISR_OFFSET, RegVal);
+	/* Clear the hold bit,master enable bit and ack bit */
+	RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_CR_OFFSET);
+	RegVal &= ~(XIICPS_CR_HOLD_MASK|XIICPS_CR_MS_MASK|XIICPS_CR_ACKEN_MASK);
+	/* Clear the fifos */
+	RegVal |= XIICPS_CR_CLR_FIFO_MASK;
+	XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, RegVal);
+	/* Clear the timeout register */
+	XIicPs_WriteReg(BaseAddress, XIICPS_TIME_OUT_OFFSET, XIICPS_TO_RESET_VALUE);
+	/* Clear the transfer size register */
+	XIicPs_WriteReg(BaseAddress, XIICPS_TRANS_SIZE_OFFSET, 0x0U);
+	/* Clear the status register */
+	RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_SR_OFFSET);
+	XIicPs_WriteReg(BaseAddress, XIICPS_SR_OFFSET, RegVal);
+	/* Update the configuraqtion register with reset value */
+	XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, 0x0U);
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..3b00cf8b17c45a75162e3d7fdcb4cc0f554a96f2
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_hw.h
@@ -0,0 +1,383 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_hw.h
+* @addtogroup iicps_v3_0
+* @{
+*
+* This header file contains the hardware definition for an IIC device.
+* It includes register definitions and interface functions to read/write
+* the registers.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who 	Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/10 First release
+* 1.04a kpc		11/07/13 Added function prototype.
+* 3.0	sk		11/03/14 Modified the TimeOut Register value to 0xFF
+*				01/31/15 Modified the code according to MISRAC 2012 Compliant.
+* </pre>
+*
+******************************************************************************/
+#ifndef XIICPS_HW_H		/* prevent circular inclusions */
+#define XIICPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the IIC.
+ * @{
+ */
+#define XIICPS_CR_OFFSET			0x00U  /**< 32-bit Control */
+#define XIICPS_SR_OFFSET			0x04U  /**< Status */
+#define XIICPS_ADDR_OFFSET			0x08U  /**< IIC Address */
+#define XIICPS_DATA_OFFSET			0x0CU  /**< IIC FIFO Data */
+#define XIICPS_ISR_OFFSET			0x10U  /**< Interrupt Status */
+#define XIICPS_TRANS_SIZE_OFFSET	0x14U  /**< Transfer Size */
+#define XIICPS_SLV_PAUSE_OFFSET		0x18U  /**< Slave monitor pause */
+#define XIICPS_TIME_OUT_OFFSET		0x1CU  /**< Time Out */
+#define XIICPS_IMR_OFFSET			0x20U  /**< Interrupt Enabled Mask */
+#define XIICPS_IER_OFFSET			0x24U  /**< Interrupt Enable */
+#define XIICPS_IDR_OFFSET			0x28U  /**< Interrupt Disable */
+/* @} */
+
+/** @name Control Register
+ *
+ * This register contains various control bits that
+ * affects the operation of the IIC controller. Read/Write.
+ * @{
+ */
+
+#define XIICPS_CR_DIV_A_MASK	0x0000C000U /**< Clock Divisor A */
+#define XIICPS_CR_DIV_A_SHIFT			14U /**< Clock Divisor A shift */
+#define XIICPS_DIV_A_MAX				 4U /**< Maximum value of Divisor A */
+#define XIICPS_CR_DIV_B_MASK	0x00003F00U /**< Clock Divisor B */
+#define XIICPS_CR_DIV_B_SHIFT			 8U /**< Clock Divisor B shift */
+#define XIICPS_CR_CLR_FIFO_MASK	0x00000040U /**< Clear FIFO, auto clears*/
+#define XIICPS_CR_SLVMON_MASK	0x00000020U /**< Slave monitor mode */
+#define XIICPS_CR_HOLD_MASK		0x00000010U /**<  Hold bus 1=Hold scl,
+												0=terminate transfer */
+#define XIICPS_CR_ACKEN_MASK	0x00000008U /**< Enable TX of ACK when
+												Master receiver*/
+#define XIICPS_CR_NEA_MASK		0x00000004U /**< Addressing Mode 1=7 bit,
+												0=10 bit */
+#define XIICPS_CR_MS_MASK		0x00000002U /**< Master mode bit 1=Master,
+												0=Slave */
+#define XIICPS_CR_RD_WR_MASK	0x00000001U /**< Read or Write Master
+												transfer  0=Transmitter,
+												1=Receiver*/
+#define XIICPS_CR_RESET_VALUE			 0U /**< Reset value of the Control
+												register */
+/* @} */
+
+/** @name IIC Status Register
+ *
+ * This register is used to indicate status of the IIC controller. Read only
+ * @{
+ */
+#define XIICPS_SR_BA_MASK		0x00000100U  /**< Bus Active Mask */
+#define XIICPS_SR_RXOVF_MASK	0x00000080U  /**< Receiver Overflow Mask */
+#define XIICPS_SR_TXDV_MASK		0x00000040U  /**< Transmit Data Valid Mask */
+#define XIICPS_SR_RXDV_MASK		0x00000020U  /**< Receiver Data Valid Mask */
+#define XIICPS_SR_RXRW_MASK		0x00000008U  /**< Receive read/write Mask */
+/* @} */
+
+/** @name IIC Address Register
+ *
+ * Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0].
+ * A write access to this register always initiates a transfer if the IIC is in
+ * master mode. Read/Write
+ * @{
+ */
+#define XIICPS_ADDR_MASK	0x000003FF  /**< IIC Address Mask */
+/* @} */
+
+/** @name IIC Data Register
+ *
+ * When written to, the data register sets data to transmit. When read from, the
+ * data register reads the last received byte of data. Read/Write
+ * @{
+ */
+#define XIICPS_DATA_MASK	0x000000FF  /**< IIC Data Mask */
+/* @} */
+
+/** @name IIC Interrupt Registers
+ *
+ * <b>IIC Interrupt Status Register</b>
+ *
+ * This register holds the interrupt status flags for the IIC controller. Some
+ * of the flags are level triggered
+ * - i.e. are set as long as the interrupt condition exists.  Other flags are
+ *   edge triggered, which means they are set one the interrupt condition occurs
+ *   then remain set until they are cleared by software.
+ *   The interrupts are cleared by writing a one to the interrupt bit position
+ *   in the Interrupt Status Register. Read/Write.
+ *
+ * <b>IIC Interrupt Enable Register</b>
+ *
+ * This register is used to enable interrupt sources for the IIC controller.
+ * Writing a '1' to a bit in this register clears the corresponding bit in the
+ * IIC Interrupt Mask register.  Write only.
+ *
+ * <b>IIC Interrupt Disable Register </b>
+ *
+ * This register is used to disable interrupt sources for the IIC controller.
+ * Writing a '1' to a bit in this register sets the corresponding bit in the
+ * IIC Interrupt Mask register. Write only.
+ *
+ * <b>IIC Interrupt Mask Register</b>
+ *
+ * This register shows the enabled/disabled status of each IIC controller
+ * interrupt source. A bit set to 1 will ignore the corresponding interrupt in
+ * the status register. A bit set to 0 means the interrupt is enabled.
+ * All mask bits are set and all interrupts are disabled after reset. Read only.
+ *
+ * All four registers have the same bit definitions. They are only defined once
+ * for each of the Interrupt Enable Register, Interrupt Disable Register,
+ * Interrupt Mask Register, and Interrupt Status Register
+ * @{
+ */
+
+#define XIICPS_IXR_ARB_LOST_MASK  0x00000200U	 /**< Arbitration Lost Interrupt
+													mask */
+#define XIICPS_IXR_RX_UNF_MASK    0x00000080U	 /**< FIFO Recieve Underflow
+													Interrupt mask */
+#define XIICPS_IXR_TX_OVR_MASK    0x00000040U	 /**< Transmit Overflow
+													Interrupt mask */
+#define XIICPS_IXR_RX_OVR_MASK    0x00000020U	 /**< Receive Overflow Interrupt
+													mask */
+#define XIICPS_IXR_SLV_RDY_MASK   0x00000010U	 /**< Monitored Slave Ready
+													Interrupt mask */
+#define XIICPS_IXR_TO_MASK        0x00000008U	 /**< Transfer Time Out
+													Interrupt mask */
+#define XIICPS_IXR_NACK_MASK      0x00000004U	 /**< NACK Interrupt mask */
+#define XIICPS_IXR_DATA_MASK      0x00000002U	 /**< Data Interrupt mask */
+#define XIICPS_IXR_COMP_MASK      0x00000001U	 /**< Transfer Complete
+													Interrupt mask */
+#define XIICPS_IXR_DEFAULT_MASK   0x000002FFU	 /**< Default ISR Mask */
+#define XIICPS_IXR_ALL_INTR_MASK  0x000002FFU	 /**< All ISR Mask */
+/* @} */
+
+
+/** @name IIC Transfer Size Register
+*
+* The register's meaning varies according to the operating mode as follows:
+*   - Master transmitter mode: number of data bytes still not transmitted minus
+*     one
+*   - Master receiver mode: number of data bytes that are still expected to be
+*     received
+*   - Slave transmitter mode: number of bytes remaining in the FIFO after the
+*     master terminates the transfer
+*   - Slave receiver mode: number of valid data bytes in the FIFO
+*
+* This register is cleared if CLR_FIFO bit in the control register is set.
+* Read/Write
+* @{
+*/
+#define XIICPS_TRANS_SIZE_MASK  0x0000003F /**< IIC Transfer Size Mask */
+#define XIICPS_FIFO_DEPTH          16	  /**< Number of bytes in the FIFO */
+#define XIICPS_DATA_INTR_DEPTH     14    /**< Number of bytes at DATA intr */
+/* @} */
+
+
+/** @name IIC Slave Monitor Pause Register
+*
+* This register is associated with the slave monitor mode of the I2C interface.
+* It is meaningful only when the module is in master mode and bit SLVMON in the
+* control register is set.
+*
+* This register defines the pause interval between consecutive attempts to
+* address the slave once a write to an I2C address register is done by the
+* host. It represents the number of sclk cycles minus one between two attempts.
+*
+* The reset value of the register is 0, which results in the master repeatedly
+* trying to access the slave immediately after unsuccessful attempt.
+* Read/Write
+* @{
+*/
+#define XIICPS_SLV_PAUSE_MASK    0x0000000F  /**< Slave monitor pause mask */
+/* @} */
+
+
+/** @name IIC Time Out Register
+*
+* The value of time out register represents the time out interval in number of
+* sclk cycles minus one.
+*
+* When the accessed slave holds the sclk line low for longer than the time out
+* period, thus prohibiting the I2C interface in master mode to complete the
+* current transfer, an interrupt is generated and TO interrupt flag is set.
+*
+* The reset value of the register is 0x1f.
+* Read/Write
+* @{
+ */
+#define XIICPS_TIME_OUT_MASK    0x000000FFU    /**< IIC Time Out mask */
+#define XIICPS_TO_RESET_VALUE   0x000000FFU    /**< IIC Time Out reset value */
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XIicPs_In32 Xil_In32
+#define XIicPs_Out32 Xil_Out32
+
+/****************************************************************************/
+/**
+* Read an IIC register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to select the specific register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XIicPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XIicPs_ReadReg(BaseAddress, RegOffset) \
+	XIicPs_In32((BaseAddress) + (u32)(RegOffset))
+
+/***************************************************************************/
+/**
+* Write an IIC register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to select the specific register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note	C-Style signature:
+*	void XIicPs_WriteReg(u32 BaseAddress, int RegOffset, u32 RegisterValue)
+*
+******************************************************************************/
+#define XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+	XIicPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
+
+/***************************************************************************/
+/**
+* Read the interrupt enable register.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	Current bit mask that represents currently enabled interrupts.
+*
+* @note		C-Style signature:
+*		u32 XIicPs_ReadIER(u32 BaseAddress)
+*
+******************************************************************************/
+#define XIicPs_ReadIER(BaseAddress) \
+	XIicPs_ReadReg((BaseAddress),  XIICPS_IER_OFFSET)
+
+/***************************************************************************/
+/**
+* Write to the interrupt enable register.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @param	IntrMask is the interrupts to be enabled.
+*
+* @return	None.
+*
+* @note	C-Style signature:
+*	void XIicPs_EnabledInterrupts(u32 BaseAddress, u32 IntrMask)
+*
+******************************************************************************/
+#define XIicPs_EnableInterrupts(BaseAddress, IntrMask) \
+	XIicPs_WriteReg((BaseAddress), XIICPS_IER_OFFSET, (IntrMask))
+
+/***************************************************************************/
+/**
+* Disable all interrupts.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XIicPs_DisableAllInterrupts(u32 BaseAddress)
+*
+******************************************************************************/
+#define XIicPs_DisableAllInterrupts(BaseAddress) \
+	XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
+		XIICPS_IXR_ALL_INTR_MASK)
+
+/***************************************************************************/
+/**
+* Disable selected interrupts.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @param	IntrMask is the interrupts to be disabled.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XIicPs_DisableInterrupts(u32 BaseAddress, u32 IntrMask)
+*
+******************************************************************************/
+#define XIicPs_DisableInterrupts(BaseAddress, IntrMask) \
+	XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
+		(IntrMask))
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the I2c interface
+ */
+void XIicPs_ResetHw(u32 BaseAddress);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_intr.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_intr.c
new file mode 100644
index 0000000000000000000000000000000000000000..5231049c714f2410caa59078c331fa951fdff1c6
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_intr.c
@@ -0,0 +1,101 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_intr.c
+* @addtogroup iicps_v3_0
+* @{
+*
+* Contains functions of the XIicPs driver for interrupt-driven transfers.
+* See xiicps.h for a detailed description of the device and driver.
+*
+* <pre> MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/10 First release
+* 3.00	sk		01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************* Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function sets the status callback function, the status handler, which the
+* driver calls when it encounters conditions that should be reported to the
+* higher layer software. The handler executes in an interrupt context, so
+* the amount of processing should be minimized
+*
+* Refer to the xiicps.h file for a list of the Callback events. The events are
+* defined to start with XIICPS_EVENT_*.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+* @param	FunctionPtr is the pointer to the callback function.
+*
+* @return	None.
+*
+* @note
+*
+* The handler is called within interrupt context, so it should finish its
+* work quickly.
+*
+******************************************************************************/
+void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef,
+				  XIicPs_IntrHandler FunctionPtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FunctionPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	InstancePtr->StatusHandler = FunctionPtr;
+	InstancePtr->CallBackRef = CallBackRef;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_master.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_master.c
new file mode 100644
index 0000000000000000000000000000000000000000..99890afaadf58ecbe54b83c12ec16d66c1786e2b
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_master.c
@@ -0,0 +1,996 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_master.c
+* @addtogroup iicps_v3_0
+* @{
+*
+* Handles master mode transfers.
+*
+* <pre> MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---  -------- ---------------------------------------------
+* 1.00a jz   01/30/10 First release
+* 1.00a sdm  09/21/11 Updated the XIicPs_SetupMaster to not check for
+*		      Bus Busy condition when the Hold Bit is set.
+* 1.01a sg   03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
+*		      check for transfer completion is added, which indicates
+*			 the completion of current transfer.
+* 2.0   hk   03/07/14 Added check for error status in the while loop that
+*                     checks for completion. CR# 762244, 764875.
+* 2.1   hk   04/24/14 Fix for CR# 789821 to handle >14 byte transfers.
+*                     Fix for CR# 761060 - provision for repeated start.
+* 2.2   hk   08/23/14 Slave monitor mode changes - clear FIFO, enable
+*                     read mode and clear transfer size register.
+*                     Disable NACK to avoid interrupts on each retry.
+* 2.3	sk	 10/06/14 Fill transmit fifo before address register when sending.
+* 					  Replaced XIICPS_DATA_INTR_DEPTH with XIICPS_FIFO_DEPTH.
+* 					  Repeated start feature removed.
+* 3.0	sk	 12/06/14 Implemented Repeated start feature.
+*			 01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*			 02/18/15 Implemented larger data transfer using repeated start
+*					  in Zynq UltraScale MP.
+* 3.3   kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+s32 TransmitFifoFill(XIicPs *InstancePtr);
+
+static s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role);
+static void MasterSendData(XIicPs *InstancePtr);
+
+/************************* Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function initiates an interrupt-driven send in master mode.
+*
+* It tries to send the first FIFO-full of data, then lets the interrupt
+* handler to handle the rest of the data if there is any.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the send buffer.
+* @param	ByteCount is the number of bytes to be sent.
+* @param	SlaveAddr is the address of the slave we are sending to.
+*
+* @return	None.
+*
+* @note		This send routine is for interrupt-driven transfer only.
+*
+ ****************************************************************************/
+void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		 u16 SlaveAddr)
+{
+	u32 BaseAddr;
+	u32 Platform = XGetPlatform_Info();
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(MsgPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->SendBufferPtr = MsgPtr;
+	InstancePtr->SendByteCount = ByteCount;
+	InstancePtr->RecvBufferPtr = NULL;
+	InstancePtr->IsSend = 1;
+
+	/*
+	 * Set repeated start if sending more than FIFO of data.
+	 */
+	if (((InstancePtr->IsRepeatedStart) != 0)||
+		((ByteCount > XIICPS_FIFO_DEPTH) != 0U)) {
+		XIicPs_WriteReg(BaseAddr, (u32)XIICPS_CR_OFFSET,
+			XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
+				(u32)XIICPS_CR_HOLD_MASK);
+	}
+
+	/*
+	 * Setup as a master sending role.
+	 */
+	(void)XIicPs_SetupMaster(InstancePtr, SENDING_ROLE);
+
+	(void)TransmitFifoFill(InstancePtr);
+
+	XIicPs_EnableInterrupts(BaseAddr,
+		(u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_COMP_MASK |
+		(u32)XIICPS_IXR_ARB_LOST_MASK);
+	/*
+	 * Do the address transfer to notify the slave.
+	 */
+	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+	/* Clear the Hold bit in ZYNQ if receive byte count is less than
+	 * the FIFO depth to get the completion interrupt properly.
+	 */
+	if ((ByteCount < XIICPS_FIFO_DEPTH) && (Platform == (u32)XPLAT_ZYNQ))
+	{
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) &
+				(u32)(~XIICPS_CR_HOLD_MASK));
+	}
+
+}
+
+/*****************************************************************************/
+/**
+* This function initiates an interrupt-driven receive in master mode.
+*
+* It sets the transfer size register so the slave can send data to us.
+* The rest of the work is managed by interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the receive buffer.
+* @param	ByteCount is the number of bytes to be received.
+* @param	SlaveAddr is the address of the slave we are receiving from.
+*
+* @return	None.
+*
+* @note		This receive routine is for interrupt-driven transfer only.
+*
+****************************************************************************/
+void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		 u16 SlaveAddr)
+{
+	u32 BaseAddr;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(MsgPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->RecvBufferPtr = MsgPtr;
+	InstancePtr->RecvByteCount = ByteCount;
+	InstancePtr->SendBufferPtr = NULL;
+	InstancePtr->IsSend = 0;
+
+	if ((ByteCount > XIICPS_FIFO_DEPTH) ||
+		((InstancePtr->IsRepeatedStart) !=0))
+	{
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
+						(u32)XIICPS_CR_HOLD_MASK);
+	}
+
+	/*
+	 * Initialize for a master receiving role.
+	 */
+	(void)XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
+	/*
+	 * Setup the transfer size register so the slave knows how much
+	 * to send to us.
+	 */
+	if (ByteCount > (s32)XIICPS_MAX_TRANSFER_SIZE) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
+				XIICPS_MAX_TRANSFER_SIZE);
+		InstancePtr->CurrByteCount = (s32)XIICPS_MAX_TRANSFER_SIZE;
+		InstancePtr->UpdateTxSize = 1;
+	}else {
+		InstancePtr->CurrByteCount = ByteCount;
+		XIicPs_WriteReg(BaseAddr, (u32)(XIICPS_TRANS_SIZE_OFFSET),
+			 (u32)ByteCount);
+		InstancePtr->UpdateTxSize = 0;
+	}
+
+	XIicPs_EnableInterrupts(BaseAddr,
+		(u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_DATA_MASK |
+		(u32)XIICPS_IXR_RX_OVR_MASK | (u32)XIICPS_IXR_COMP_MASK |
+		(u32)XIICPS_IXR_ARB_LOST_MASK);
+	/*
+	 * Do the address transfer to signal the slave.
+	 */
+	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+}
+
+/*****************************************************************************/
+/**
+* This function initiates a polled mode send in master mode.
+*
+* It sends data to the FIFO and waits for the slave to pick them up.
+* If slave fails to remove data from FIFO, the send fails with
+* time out.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the send buffer.
+* @param	ByteCount is the number of bytes to be sent.
+* @param	SlaveAddr is the address of the slave we are sending to.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if timed out.
+*
+* @note		This send routine is for polled mode transfer only.
+*
+****************************************************************************/
+s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr,
+		 s32 ByteCount, u16 SlaveAddr)
+{
+	u32 IntrStatusReg;
+	u32 StatusReg;
+	u32 BaseAddr;
+	u32 Intrs;
+	_Bool Value;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((u16)XIICPS_ADDR_MASK >= SlaveAddr);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->SendBufferPtr = MsgPtr;
+	InstancePtr->SendByteCount = ByteCount;
+
+	if (((InstancePtr->IsRepeatedStart) != 0) ||
+		((ByteCount > XIICPS_FIFO_DEPTH) != 0U)) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
+						(u32)XIICPS_CR_HOLD_MASK);
+	}
+
+	(void)XIicPs_SetupMaster(InstancePtr, SENDING_ROLE);
+
+	/*
+	 * Intrs keeps all the error-related interrupts.
+	 */
+	Intrs = (u32)XIICPS_IXR_ARB_LOST_MASK | (u32)XIICPS_IXR_TX_OVR_MASK |
+		(u32)XIICPS_IXR_NACK_MASK;
+
+	/*
+	 * Clear the interrupt status register before use it to monitor.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Transmit first FIFO full of data.
+	 */
+	(void)TransmitFifoFill(InstancePtr);
+
+	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+
+	/*
+	 * Continue sending as long as there is more data and
+	 * there are no errors.
+	 */
+	Value = ((InstancePtr->SendByteCount > (s32)0) &&
+		((IntrStatusReg & Intrs) == (u32)0U));
+	while (Value != FALSE) {
+		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+		/*
+		 * Wait until transmit FIFO is empty.
+		 */
+		if ((StatusReg & XIICPS_SR_TXDV_MASK) != 0U) {
+			IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+					XIICPS_ISR_OFFSET);
+			Value = ((InstancePtr->SendByteCount > (s32)0) &&
+				((IntrStatusReg & Intrs) == (u32)0U));
+			continue;
+		}
+
+		/*
+		 * Send more data out through transmit FIFO.
+		 */
+		(void)TransmitFifoFill(InstancePtr);
+		Value = ((InstancePtr->SendByteCount > (s32)0) &&
+			((IntrStatusReg & Intrs) == (u32)0U));
+	}
+
+	/*
+	 * Check for completion of transfer.
+	 */
+	while ((IntrStatusReg & XIICPS_IXR_COMP_MASK) != XIICPS_IXR_COMP_MASK){
+
+		IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+		/*
+		 * If there is an error, tell the caller.
+		 */
+		if ((IntrStatusReg & Intrs) != 0U) {
+			return (s32)XST_FAILURE;
+		}
+	}
+
+	if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr,XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+	}
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* This function initiates a polled mode receive in master mode.
+*
+* It repeatedly sets the transfer size register so the slave can
+* send data to us. It polls the data register for data to come in.
+* If slave fails to send us data, it fails with time out.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the receive buffer.
+* @param	ByteCount is the number of bytes to be received.
+* @param	SlaveAddr is the address of the slave we are receiving from.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if timed out.
+*
+* @note		This receive routine is for polled mode transfer only.
+*
+****************************************************************************/
+s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
+				s32 ByteCount, u16 SlaveAddr)
+{
+	u32 IntrStatusReg;
+	u32 Intrs;
+	u32 StatusReg;
+	u32 BaseAddr;
+	s32 Result;
+	s32 IsHold;
+	s32 UpdateTxSize = 0;
+	s32 ByteCountVar = ByteCount;
+	u32 Platform;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->RecvBufferPtr = MsgPtr;
+	InstancePtr->RecvByteCount = ByteCountVar;
+
+	Platform = XGetPlatform_Info();
+
+	if((ByteCountVar > XIICPS_FIFO_DEPTH) ||
+		((InstancePtr->IsRepeatedStart) !=0))
+	{
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
+						(u32)XIICPS_CR_HOLD_MASK);
+		IsHold = 1;
+	} else {
+		IsHold = 0;
+	}
+
+	(void)XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
+
+	/*
+	 * Clear the interrupt status register before use it to monitor.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
+
+	/*
+	 * Set up the transfer size register so the slave knows how much
+	 * to send to us.
+	 */
+	if (ByteCountVar > (s32)XIICPS_MAX_TRANSFER_SIZE) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
+				XIICPS_MAX_TRANSFER_SIZE);
+		ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE;
+		UpdateTxSize = 1;
+	}else {
+		XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
+			 ByteCountVar);
+	}
+
+	/*
+	 * Intrs keeps all the error-related interrupts.
+	 */
+	Intrs = (u32)XIICPS_IXR_ARB_LOST_MASK | (u32)XIICPS_IXR_RX_OVR_MASK |
+			(u32)XIICPS_IXR_RX_UNF_MASK | (u32)XIICPS_IXR_NACK_MASK;
+	/*
+	 * Poll the interrupt status register to find the errors.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	while ((InstancePtr->RecvByteCount > 0) &&
+			((IntrStatusReg & Intrs) == 0U)) {
+		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+	    while ((StatusReg & XIICPS_SR_RXDV_MASK) != 0U) {
+		    if (((InstancePtr->RecvByteCount <
+			    XIICPS_DATA_INTR_DEPTH) != 0U) && (IsHold != 0) &&
+			    ((!InstancePtr->IsRepeatedStart) != 0) &&
+			    (UpdateTxSize == 0)) {
+				IsHold = 0;
+				XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+						XIicPs_ReadReg(BaseAddr,
+						XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+			}
+			XIicPs_RecvByte(InstancePtr);
+		    ByteCountVar --;
+
+			if (Platform == (u32)XPLAT_ZYNQ) {
+			    if ((UpdateTxSize != 0) &&
+				    (ByteCountVar == (XIICPS_FIFO_DEPTH + 1))) {
+				    break;
+				}
+			}
+
+			StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+		}
+		if (Platform == (u32)XPLAT_ZYNQ) {
+			if ((UpdateTxSize != 0) &&
+				(ByteCountVar == (XIICPS_FIFO_DEPTH + 1))) {
+			    /*  wait while fifo is full */
+			    while (XIicPs_ReadReg(BaseAddr,
+				    XIICPS_TRANS_SIZE_OFFSET) !=
+				    (u32)(ByteCountVar - XIICPS_FIFO_DEPTH)) { ;
+				}
+
+				if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) >
+					(s32)XIICPS_MAX_TRANSFER_SIZE) {
+
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						XIICPS_MAX_TRANSFER_SIZE);
+				    ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE +
+							XIICPS_FIFO_DEPTH;
+				} else {
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						InstancePtr->RecvByteCount -
+						XIICPS_FIFO_DEPTH);
+					UpdateTxSize = 0;
+				    ByteCountVar = InstancePtr->RecvByteCount;
+				}
+			}
+		} else {
+		    if ((InstancePtr->RecvByteCount > 0) && (ByteCountVar == 0)) {
+				/*
+				 * Clear the interrupt status register before use it to
+				 * monitor.
+				 */
+				IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+				XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+				XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
+
+				if ((InstancePtr->RecvByteCount) >
+					(s32)XIICPS_MAX_TRANSFER_SIZE) {
+
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						XIICPS_MAX_TRANSFER_SIZE);
+				    ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE;
+				} else {
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						InstancePtr->RecvByteCount);
+					UpdateTxSize = 0;
+				    ByteCountVar = InstancePtr->RecvByteCount;
+				}
+			}
+		}
+
+		IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	}
+
+	if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr,XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+	}
+	if ((IntrStatusReg & Intrs) != 0x0U) {
+		Result = (s32)XST_FAILURE;
+	}
+	else {
+		Result =  (s32)XST_SUCCESS;
+	}
+
+	return Result;
+}
+
+/*****************************************************************************/
+/**
+* This function enables the slave monitor mode.
+*
+* It enables slave monitor in the control register and enables
+* slave ready interrupt. It then does an address transfer to slave.
+* Interrupt handler will signal the caller if slave responds to
+* the address transfer.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	SlaveAddr is the address of the slave we want to contact.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr)
+{
+	u32 BaseAddr;
+	u32 ConfigReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	/* Clear transfer size register */
+	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_TRANS_SIZE_OFFSET, 0x0U);
+
+	/*
+	 * Enable slave monitor mode in control register.
+	 */
+	ConfigReg = XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET);
+	ConfigReg |= (u32)XIICPS_CR_MS_MASK | (u32)XIICPS_CR_NEA_MASK |
+			(u32)XIICPS_CR_CLR_FIFO_MASK | (u32)XIICPS_CR_SLVMON_MASK;
+	ConfigReg &= (u32)(~XIICPS_CR_RD_WR_MASK);
+
+	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_CR_OFFSET, ConfigReg);
+
+	/*
+	 * Set up interrupt flag for slave monitor interrupt.
+	 * Dont enable NACK.
+	 */
+	XIicPs_EnableInterrupts(BaseAddr, (u32)XIICPS_IXR_SLV_RDY_MASK);
+
+	/*
+	 * Initialize the slave monitor register.
+	 */
+	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_SLV_PAUSE_OFFSET, 0xFU);
+
+	/*
+	 * Set the slave address to start the slave address transmission.
+	 */
+	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+	return;
+}
+
+/*****************************************************************************/
+/**
+* This function disables slave monitor mode.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr)
+{
+	u32 BaseAddr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	/*
+	 * Clear slave monitor control bit.
+	 */
+	XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+		XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET)
+			& (~XIICPS_CR_SLVMON_MASK));
+
+	/*
+	 * wait for slv monitor control bit to be clear
+	 */
+	while (XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET)
+				& XIICPS_CR_SLVMON_MASK);
+	/*
+	 * Clear interrupt flag for slave monitor interrupt.
+	 */
+	XIicPs_DisableInterrupts(BaseAddr, XIICPS_IXR_SLV_RDY_MASK);
+
+	return;
+}
+
+/*****************************************************************************/
+/**
+* The interrupt handler for the master mode. It does the protocol handling for
+* the interrupt-driven transfers.
+*
+* Completion events and errors are signaled to upper layer for proper handling.
+*
+* <pre>
+* The interrupts that are handled are:
+* - DATA
+*	This case is handled only for master receive data.
+*	The master has to request for more data (if there is more data to
+*	receive) and read the data from the FIFO .
+*
+* - COMP
+*	If the Master is transmitting data and there is more data to be
+*	sent then the data is written to the FIFO. If there is no more data to
+*	be transmitted then a completion event is signalled to the upper layer
+*	by calling the callback handler.
+*
+*	If the Master is receiving data then the data is read from the FIFO and
+*	the Master has to request for more data (if there is more data to
+*	receive). If all the data has been received then a completion event
+*	is signalled to the upper layer by calling the callback handler.
+*	It is an error if the amount of received data is more than expected.
+*
+* - NAK and SLAVE_RDY
+*	This is signalled to the upper layer by calling the callback handler.
+*
+* - All Other interrupts
+*	These interrupts are marked as error. This is signalled to the upper
+*	layer by calling the callback handler.
+*
+* </pre>
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note 	None.
+*
+****************************************************************************/
+void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
+{
+	u32 IntrStatusReg;
+	u32 StatusEvent = 0U;
+	u32 BaseAddr;
+	u16 SlaveAddr;
+	s32 ByteCnt;
+	s32 IsHold;
+	u32 Platform;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	Platform = XGetPlatform_Info();
+
+	/*
+	 * Read the Interrupt status register.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+					 (u32)XIICPS_ISR_OFFSET);
+
+	/*
+	 * Write the status back to clear the interrupts so no events are
+	 * missed while processing this interrupt.
+	 */
+	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Use the Mask register AND with the Interrupt Status register so
+	 * disabled interrupts are not processed.
+	 */
+	IntrStatusReg &= ~(XIicPs_ReadReg(BaseAddr, (u32)XIICPS_IMR_OFFSET));
+
+	ByteCnt = InstancePtr->CurrByteCount;
+
+	IsHold = 0;
+	if ((XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) & (u32)XIICPS_CR_HOLD_MASK) != 0U) {
+		IsHold = 1;
+	}
+
+	/*
+	 * Send
+	 */
+	if (((InstancePtr->IsSend) != 0) &&
+		((u32)0U != (IntrStatusReg & (u32)XIICPS_IXR_COMP_MASK))) {
+		if (InstancePtr->SendByteCount > 0) {
+			MasterSendData(InstancePtr);
+		} else {
+			StatusEvent |= XIICPS_EVENT_COMPLETE_SEND;
+		}
+	}
+
+
+	/*
+	 * Receive
+	 */
+	if (((!(InstancePtr->IsSend))!= 0) &&
+		((0 != (IntrStatusReg & (u32)XIICPS_IXR_DATA_MASK)) ||
+		(0 != (IntrStatusReg & (u32)XIICPS_IXR_COMP_MASK)))){
+
+		while ((XIicPs_ReadReg(BaseAddr, (u32)XIICPS_SR_OFFSET) &
+				XIICPS_SR_RXDV_MASK) != 0U) {
+			if (((InstancePtr->RecvByteCount <
+				XIICPS_DATA_INTR_DEPTH)!= 0U)  && (IsHold != 0)  &&
+				((!InstancePtr->IsRepeatedStart)!= 0) &&
+				(InstancePtr->UpdateTxSize == 0)) {
+				IsHold = 0;
+				XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+						XIicPs_ReadReg(BaseAddr,
+						XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+			}
+			XIicPs_RecvByte(InstancePtr);
+			ByteCnt--;
+
+			if (Platform == (u32)XPLAT_ZYNQ) {
+			    if ((InstancePtr->UpdateTxSize != 0) &&
+				    (ByteCnt == (XIICPS_FIFO_DEPTH + 1))) {
+				    break;
+				}
+			}
+		}
+
+		if (Platform == (u32)XPLAT_ZYNQ) {
+			if ((InstancePtr->UpdateTxSize != 0) &&
+				(ByteCnt == (XIICPS_FIFO_DEPTH + 1))) {
+				/* wait while fifo is full */
+				while (XIicPs_ReadReg(BaseAddr,
+					XIICPS_TRANS_SIZE_OFFSET) !=
+					(u32)(ByteCnt - XIICPS_FIFO_DEPTH)) {
+				}
+
+				if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) >
+					(s32)XIICPS_MAX_TRANSFER_SIZE) {
+
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						XIICPS_MAX_TRANSFER_SIZE);
+					ByteCnt = (s32)XIICPS_MAX_TRANSFER_SIZE +
+							XIICPS_FIFO_DEPTH;
+				} else {
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						InstancePtr->RecvByteCount -
+						XIICPS_FIFO_DEPTH);
+					InstancePtr->UpdateTxSize = 0;
+					ByteCnt = InstancePtr->RecvByteCount;
+				}
+			}
+		} else {
+			if ((InstancePtr->RecvByteCount > 0) && (ByteCnt == 0)) {
+				/*
+				 * Clear the interrupt status register before use it to
+				 * monitor.
+				 */
+				IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+				XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+				SlaveAddr = (u16)XIicPs_ReadReg(BaseAddr, (u32)XIICPS_ADDR_OFFSET);
+				XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
+
+				if ((InstancePtr->RecvByteCount) >
+					(s32)XIICPS_MAX_TRANSFER_SIZE) {
+
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						XIICPS_MAX_TRANSFER_SIZE);
+					ByteCnt = (s32)XIICPS_MAX_TRANSFER_SIZE;
+				} else {
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						InstancePtr->RecvByteCount);
+					InstancePtr->UpdateTxSize = 0;
+					ByteCnt = InstancePtr->RecvByteCount;
+				}
+				XIicPs_EnableInterrupts(BaseAddr,
+					(u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_DATA_MASK |
+					(u32)XIICPS_IXR_RX_OVR_MASK | (u32)XIICPS_IXR_COMP_MASK |
+					(u32)XIICPS_IXR_ARB_LOST_MASK);
+			}
+		}
+		InstancePtr->CurrByteCount = ByteCnt;
+	}
+
+	if (((!(InstancePtr->IsSend)) != 0) &&
+		(0U != (IntrStatusReg & XIICPS_IXR_COMP_MASK))) {
+		/*
+		 * If all done, tell the application.
+		 */
+		if (InstancePtr->RecvByteCount == 0){
+			if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+				XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+						XIicPs_ReadReg(BaseAddr,
+						XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+			}
+			StatusEvent |= XIICPS_EVENT_COMPLETE_RECV;
+		}
+	}
+
+
+	/*
+	 * Slave ready interrupt, it is only meaningful for master mode.
+	 */
+	if (0U != (IntrStatusReg & XIICPS_IXR_SLV_RDY_MASK)) {
+		StatusEvent |= XIICPS_EVENT_SLAVE_RDY;
+	}
+
+	if (0U != (IntrStatusReg & XIICPS_IXR_NACK_MASK)) {
+		if ((!(InstancePtr->IsRepeatedStart)) != 0 ) {
+			XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+					XIicPs_ReadReg(BaseAddr,
+					XIICPS_CR_OFFSET) &
+					(~XIICPS_CR_HOLD_MASK));
+		}
+		StatusEvent |= XIICPS_EVENT_NACK;
+	}
+
+	/*
+	 * Arbitration lost interrupt
+	 */
+	if (0U != (IntrStatusReg & XIICPS_IXR_ARB_LOST_MASK)) {
+		StatusEvent |= XIICPS_EVENT_ARB_LOST;
+	}
+
+	/*
+	 * All other interrupts are treated as error.
+	 */
+	if (0U != (IntrStatusReg & (XIICPS_IXR_NACK_MASK |
+			XIICPS_IXR_RX_UNF_MASK | XIICPS_IXR_TX_OVR_MASK |
+			XIICPS_IXR_RX_OVR_MASK))) {
+		if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+			XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+					XIicPs_ReadReg(BaseAddr,
+					XIICPS_CR_OFFSET) &
+					(~XIICPS_CR_HOLD_MASK));
+		}
+		StatusEvent |= XIICPS_EVENT_ERROR;
+	}
+
+	/*
+	 * Signal application if there are any events.
+	 */
+	if (StatusEvent != 0U) {
+		InstancePtr->StatusHandler(InstancePtr->CallBackRef,
+					   StatusEvent);
+	}
+
+}
+
+/*****************************************************************************/
+/*
+* This function prepares a device to transfers as a master.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @param	Role specifies whether the device is sending or receiving.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if bus is busy.
+*
+* @note		Interrupts are always disabled, device which needs to use
+*		interrupts needs to setup interrupts after this call.
+*
+****************************************************************************/
+static s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role)
+{
+	u32 ControlReg;
+	u32 BaseAddr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	ControlReg = XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET);
+
+
+	/*
+	 * Only check if bus is busy when repeated start option is not set.
+	 */
+	if ((ControlReg & XIICPS_CR_HOLD_MASK) == 0U) {
+		if (XIicPs_BusIsBusy(InstancePtr) == (s32)1) {
+			return (s32)XST_FAILURE;
+		}
+	}
+
+	/*
+	 * Set up master, AckEn, nea and also clear fifo.
+	 */
+	ControlReg |= (u32)XIICPS_CR_ACKEN_MASK | (u32)XIICPS_CR_CLR_FIFO_MASK |
+			(u32)XIICPS_CR_NEA_MASK | (u32)XIICPS_CR_MS_MASK;
+
+	if (Role == RECVING_ROLE) {
+		ControlReg |= (u32)XIICPS_CR_RD_WR_MASK;
+	}else {
+		ControlReg &= (u32)(~XIICPS_CR_RD_WR_MASK);
+	}
+
+	XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, ControlReg);
+
+	XIicPs_DisableAllInterrupts(BaseAddr);
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/*
+* This function handles continuation of sending data. It is invoked
+* from interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+static void MasterSendData(XIicPs *InstancePtr)
+{
+	(void)TransmitFifoFill(InstancePtr);
+
+	/*
+	 * Clear hold bit if done, so stop can be sent out.
+	 */
+	if (InstancePtr->SendByteCount == 0) {
+
+		/*
+		 * If user has enabled repeated start as an option,
+		 * do not disable it.
+		 */
+		if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+
+			XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			(u32)XIICPS_CR_OFFSET,
+			XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+			(u32)XIICPS_CR_OFFSET) & (u32)(~ XIICPS_CR_HOLD_MASK));
+		}
+	}
+
+	return;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_options.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_options.c
new file mode 100644
index 0000000000000000000000000000000000000000..1ebd786730d4d97f9799f98af7c2f962c86419fa
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_options.c
@@ -0,0 +1,497 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_options.c
+* @addtogroup iicps_v3_0
+* @{
+*
+* Contains functions for the configuration of the XIccPs driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/10 First release
+* 1.02a sg	08/29/12 Updated the logic to arrive at the best divisors
+*			 to achieve I2C clock with minimum error.
+*			 This is a fix for CR #674195
+* 1.03a hk  05/04/13 Initialized BestDivA and BestDivB to 0.
+*			 This is fix for CR#704398 to remove warning.
+* 2.0   hk  03/07/14 Limited frequency set when 100KHz or 400KHz is
+*                    selected. This is a hardware limitation. CR#779290.
+* 2.1   hk  04/24/14 Fix for CR# 761060 - provision for repeated start.
+* 2.3	sk	10/07/14 Repeated start feature removed.
+* 3.0	sk	12/06/14 Implemented Repeated start feature.
+*			01/31/15 Modified the code according to MISRAC 2012 Compliant.
+* 3.3   kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+/*
+ * Create the table of options which are processed to get/set the device
+ * options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+typedef struct {
+		u32 Option;
+		u32 Mask;
+} OptionsMap;
+
+static OptionsMap OptionsTable[] = {
+		{XIICPS_7_BIT_ADDR_OPTION, XIICPS_CR_NEA_MASK},
+		{XIICPS_10_BIT_ADDR_OPTION, XIICPS_CR_NEA_MASK},
+		{XIICPS_SLAVE_MON_OPTION, XIICPS_CR_SLVMON_MASK},
+		{XIICPS_REP_START_OPTION, XIICPS_CR_HOLD_MASK},
+};
+
+#define XIICPS_NUM_OPTIONS      (sizeof(OptionsTable) / sizeof(OptionsMap))
+
+/*****************************************************************************/
+/**
+*
+* This function sets the options for the IIC device driver. The options control
+* how the device behaves relative to the IIC bus. The device must be idle
+* rather than busy transferring data before setting these device options.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	Options contains the specified options to be set. This is a bit
+*		mask where a 1 means to turn the option on. One or more bit
+*		values may be contained in the mask. See the bit definitions
+*		named XIICPS_*_OPTION in xiicps.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_IS_STARTED if the device is currently transferring
+*		data. The transfer must complete or be aborted before setting
+*		options.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options)
+{
+	u32 ControlReg;
+	u32 Index;
+	u32 OptionsVar = Options;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XIICPS_CR_OFFSET);
+
+	/*
+	 * If repeated start option is requested, set the flag.
+	 * The hold bit in CR will be written by driver when the next transfer
+	 * is initiated.
+	 */
+	if ((OptionsVar & (u32)XIICPS_REP_START_OPTION) != (u32)0 ) {
+		InstancePtr->IsRepeatedStart = 1;
+		OptionsVar = OptionsVar & (~XIICPS_REP_START_OPTION);
+	}
+
+	/*
+	 * Loop through the options table, turning the option on.
+	 */
+	for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
+		if ((OptionsVar & OptionsTable[Index].Option) != (u32)0x0U) {
+			/*
+			 * 10-bit option is specially treated, because it is
+			 * using the 7-bit option, so turning it on means
+			 * turning 7-bit option off.
+			 */
+			if ((OptionsTable[Index].Option &
+				XIICPS_10_BIT_ADDR_OPTION) != (u32)0x0U) {
+				/* Turn 7-bit off */
+				ControlReg &= ~OptionsTable[Index].Mask;
+			} else {
+				/* Turn 7-bit on */
+				ControlReg |= OptionsTable[Index].Mask;
+			}
+		}
+	}
+
+	/*
+	 * Now write to the control register. Leave it to the upper layers
+	 * to restart the device.
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
+			  ControlReg);
+
+	/*
+	 * Keep a copy of what options this instance has.
+	 */
+	InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function clears the options for the IIC device driver. The options
+* control how the device behaves relative to the IIC bus. The device must be
+* idle rather than busy transferring data before setting these device options.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	Options contains the specified options to be cleared. This is a
+*		bit mask where a 1 means to turn the option off. One or more bit
+*		values may be contained in the mask. See the bit definitions
+*		named XIICPS_*_OPTION in xiicps.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_IS_STARTED if the device is currently transferring
+*		data. The transfer must complete or be aborted before setting
+*		options.
+*
+* @note		None
+*
+******************************************************************************/
+s32 XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options)
+{
+	u32 ControlReg;
+	u32 Index;
+	u32 OptionsVar = Options;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XIICPS_CR_OFFSET);
+
+	/*
+	 * If repeated start option is cleared, set the flag.
+	 * The hold bit in CR will be cleared by driver when the
+	 * following transfer ends.
+	 */
+	if ((OptionsVar & XIICPS_REP_START_OPTION) != (u32)0x0U ) {
+		InstancePtr->IsRepeatedStart = 0;
+		OptionsVar = OptionsVar & (~XIICPS_REP_START_OPTION);
+	}
+
+	/*
+	 * Loop through the options table and clear the specified options.
+	 */
+	for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
+		if ((OptionsVar & OptionsTable[Index].Option) != (u32)0x0U) {
+
+			/*
+			 * 10-bit option is specially treated, because it is
+			 * using the 7-bit option, so clearing it means turning
+			 * 7-bit option on.
+			 */
+			if ((OptionsTable[Index].Option &
+				XIICPS_10_BIT_ADDR_OPTION) != (u32)0x0U) {
+
+				/* Turn 7-bit on */
+				ControlReg |= OptionsTable[Index].Mask;
+			} else {
+
+				/* Turn 7-bit off */
+				ControlReg &= ~OptionsTable[Index].Mask;
+			}
+		}
+	}
+
+
+	/*
+	 * Now write the control register. Leave it to the upper layers
+	 * to restart the device.
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
+			  ControlReg);
+
+	/*
+	 * Keep a copy of what options this instance has.
+	 */
+	InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the options for the IIC device. The options control how
+* the device behaves relative to the IIC bus.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	32 bit mask of the options, where a 1 means the option is on,
+*		and a 0 means to the option is off. One or more bit values may
+*		be contained in the mask. See the bit definitions named
+* 		XIICPS_*_OPTION in the file xiicps.h.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XIicPs_GetOptions(XIicPs *InstancePtr)
+{
+	u32 OptionsFlag = 0U;
+	u32 ControlReg;
+	u32 Index;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read control register to find which options are currently set.
+	 */
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XIICPS_CR_OFFSET);
+
+	/*
+	 * Loop through the options table to determine which options are set.
+	 */
+	for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
+		if ((ControlReg & OptionsTable[Index].Mask) != (u32)0x0U) {
+			OptionsFlag |= OptionsTable[Index].Option;
+		}
+		if ((ControlReg & XIICPS_CR_NEA_MASK) == (u32)0x0U) {
+			OptionsFlag |= XIICPS_10_BIT_ADDR_OPTION;
+		}
+	}
+
+	if (InstancePtr->IsRepeatedStart != 0 ) {
+		OptionsFlag |= XIICPS_REP_START_OPTION;
+	}
+	return OptionsFlag;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the serial clock rate for the IIC device. The device
+* must be idle rather than busy transferring data before setting these device
+* options.
+*
+* The data rate is set by values in the control register. The formula for
+* determining the correct register values is:
+* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
+* See the hardware data sheet for a full explanation of setting the serial
+* clock rate.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	FsclHz is the clock frequency in Hz. The two most common clock
+*		rates are 100KHz and 400KHz.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_IS_STARTED if the device is currently transferring
+*		data. The transfer must complete or be aborted before setting
+*		options.
+*		- XST_FAILURE if the Fscl frequency can not be set.
+*
+* @note		The clock can not be faster than the input clock divide by 22.
+*
+******************************************************************************/
+s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz)
+{
+	u32 Div_a;
+	u32 Div_b;
+	u32 ActualFscl;
+	u32 Temp;
+	u32 TempLimit;
+	u32 LastError;
+	u32 BestError;
+	u32 CurrentError;
+	u32 ControlReg;
+	u32 CalcDivA;
+	u32 CalcDivB;
+	u32 BestDivA;
+	u32 BestDivB;
+	u32 FsclHzVar = FsclHz;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(FsclHzVar > 0U);
+
+	if (0U != XIicPs_In32((InstancePtr->Config.BaseAddress) +
+					XIICPS_TRANS_SIZE_OFFSET)) {
+		return (s32)XST_DEVICE_IS_STARTED;
+	}
+
+	/*
+	 * Assume Div_a is 0 and calculate (divisor_a+1) x (divisor_b+1).
+	 */
+	Temp = (InstancePtr->Config.InputClockHz) / ((u32)22U * FsclHzVar);
+
+	/*
+	 * If the answer is negative or 0, the Fscl input is out of range.
+	 */
+	if ((u32)(0U) == Temp) {
+		return (s32)XST_FAILURE;
+	}
+
+	/*
+	 * If frequency 400KHz is selected, 384.6KHz should be set.
+	 * If frequency 100KHz is selected, 90KHz should be set.
+	 * This is due to a hardware limitation.
+	 */
+	if(FsclHzVar > (u32)384600U) {
+		FsclHzVar = (u32)384600U;
+	}
+
+	if((FsclHzVar <= (u32)100000U) && (FsclHzVar > (u32)90000U)) {
+		FsclHzVar = (u32)90000U;
+	}
+
+	/*
+	 * TempLimit helps in iterating over the consecutive value of Temp to
+	 * find the closest clock rate achievable with divisors.
+	 * Iterate over the next value only if fractional part is involved.
+	 */
+	TempLimit = (((InstancePtr->Config.InputClockHz) %
+			((u32)22 * FsclHzVar)) != 	(u32)0x0U) ?
+						Temp + (u32)1U : Temp;
+	BestError = FsclHzVar;
+
+	BestDivA = 0U;
+	BestDivB = 0U;
+	for ( ; Temp <= TempLimit ; Temp++)
+	{
+		LastError = FsclHzVar;
+		CalcDivA = 0U;
+		CalcDivB = 0U;
+
+		for (Div_b = 0U; Div_b < 64U; Div_b++) {
+
+			Div_a = Temp / (Div_b + 1U);
+
+			if (Div_a != 0U){
+				Div_a = Div_a - (u32)1U;
+			}
+			if (Div_a > 3U){
+				continue;
+			}
+			ActualFscl = (InstancePtr->Config.InputClockHz) /
+						(22U * (Div_a + 1U) * (Div_b + 1U));
+
+			if (ActualFscl > FsclHzVar){
+				CurrentError = (ActualFscl - FsclHzVar);}
+			else{
+				CurrentError = (FsclHzVar - ActualFscl);}
+
+			if (LastError > CurrentError) {
+				CalcDivA = Div_a;
+				CalcDivB = Div_b;
+				LastError = CurrentError;
+			}
+		}
+
+		/*
+		 * Used to capture the best divisors.
+		 */
+		if (LastError < BestError) {
+			BestError = LastError;
+			BestDivA = CalcDivA;
+			BestDivB = CalcDivB;
+		}
+	}
+
+
+	/*
+	 * Read the control register and mask the Divisors.
+	 */
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  (u32)XIICPS_CR_OFFSET);
+	ControlReg &= ~((u32)XIICPS_CR_DIV_A_MASK | (u32)XIICPS_CR_DIV_B_MASK);
+	ControlReg |= (BestDivA << XIICPS_CR_DIV_A_SHIFT) |
+		(BestDivB << XIICPS_CR_DIV_B_SHIFT);
+
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, (u32)XIICPS_CR_OFFSET,
+			  ControlReg);
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the serial clock rate for the IIC device. The device
+* must be idle rather than busy transferring data before setting these device
+* options.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	The value of the IIC clock to the nearest Hz based on the
+*		control register settings. The actual value may not be exact to
+*		to integer math rounding errors.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XIicPs_GetSClk(XIicPs *InstancePtr)
+{
+	u32 ControlReg;
+	u32 ActualFscl;
+	u32 Div_a;
+	u32 Div_b;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XIICPS_CR_OFFSET);
+
+	Div_a = (ControlReg & XIICPS_CR_DIV_A_MASK) >> XIICPS_CR_DIV_A_SHIFT;
+	Div_b = (ControlReg & XIICPS_CR_DIV_B_MASK) >> XIICPS_CR_DIV_B_SHIFT;
+
+	ActualFscl = (InstancePtr->Config.InputClockHz) /
+		(22U * (Div_a + 1U) * (Div_b + 1U));
+
+	return ActualFscl;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_selftest.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_selftest.c
new file mode 100644
index 0000000000000000000000000000000000000000..dd57a1a511dcf8af3a24aaec1c8682996258ece6
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_selftest.c
@@ -0,0 +1,132 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_selftest.c
+* @addtogroup iicps_v3_0
+* @{
+*
+* This component contains the implementation of selftest functions for the
+* XIicPs driver component.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/30/10 First release
+* 1.00a sdm    09/22/11 Removed unused code
+* 3.0	sk	   11/03/14 Removed TimeOut Register value check
+*			   01/31/15	Modified the code according to MISRAC 2012 Compliant.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+#define REG_TEST_VALUE    0x00000005U
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Runs a self-test on the driver/device. The self-test is destructive in that
+* a reset of the device is performed in order to check the reset values of
+* the registers and to get the device into a known state.
+*
+* Upon successful return from the self-test, the device is reset.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_REGISTER_ERROR indicates a register did not read or write
+*		correctly
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XIicPs_SelfTest(XIicPs *InstancePtr)
+{
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/*
+	 * All the IIC registers should be in their default state right now.
+	 */
+	if ((XIICPS_CR_RESET_VALUE !=
+		 XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XIICPS_CR_OFFSET)) ||
+		(XIICPS_IXR_ALL_INTR_MASK !=
+		 XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XIICPS_IMR_OFFSET))) {
+		return (s32)XST_FAILURE;
+	}
+
+	XIicPs_Reset(InstancePtr);
+
+	/*
+	 * Write, Read then write a register
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_SLV_PAUSE_OFFSET, REG_TEST_VALUE);
+
+	if (REG_TEST_VALUE != XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+						   XIICPS_SLV_PAUSE_OFFSET)) {
+		return (s32)XST_FAILURE;
+	}
+
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_SLV_PAUSE_OFFSET, 0U);
+
+	XIicPs_Reset(InstancePtr);
+
+	return (s32)XST_SUCCESS;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_sinit.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..7d7dadaa81953273dbc349d05c02a1c4491c29e2
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_sinit.c
@@ -0,0 +1,102 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_sinit.c
+* @addtogroup iicps_v3_0
+* @{
+*
+* The implementation of the XIicPs component's static initialization
+* functionality.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- --------------------------------------------
+* 1.00a drg/jz 01/30/10 First release
+* 3.00	sk	   01/31/15	Modified the code according to MISRAC 2012 Compliant.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XIicPs_Config XIicPs_ConfigTable[XPAR_XIICPS_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device to look up the
+*		configuration for.
+*
+* @return	A pointer to the configuration found or NULL if the specified
+*		device ID was not found. See xiicps.h for the definition of
+*		XIicPs_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId)
+{
+	XIicPs_Config *CfgPtr = NULL;
+	s32 Index;
+
+	for (Index = 0; Index < XPAR_XIICPS_NUM_INSTANCES; Index++) {
+		if (XIicPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XIicPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XIicPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_slave.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_slave.c
new file mode 100644
index 0000000000000000000000000000000000000000..fef640b77c1ad8b19de384df6d92b86ee07b6e98
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/iicps_v3_5/src/xiicps_slave.c
@@ -0,0 +1,595 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xiicps_slave.c
+* @addtogroup iicps_v3_0
+* @{
+*
+* Handles slave transfers
+*
+* <pre> MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --  -------- ---------------------------------------------
+* 1.00a jz  01/30/10 First release
+* 1.04a kpc 08/30/13 Avoid buffer overwrite in SlaveRecvData function
+* 3.00	sk	01/31/15 Modified the code according to MISRAC 2012 Compliant.
+* 3.3   kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+extern s32 TransmitFifoFill(XIicPs *InstancePtr);
+
+static s32 SlaveRecvData(XIicPs *InstancePtr);
+
+/************************* Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function sets up the device to be a slave.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	SlaveAddr is the address of the slave we are receiving from.
+*
+* @return	None.
+*
+* @note
+*	Interrupt is always enabled no matter the tranfer is interrupt-
+*	driven or polled mode. Whether device will be interrupted or not
+*	depends on whether the device is connected to an interrupt
+*	controller and interrupt for the device is enabled.
+*
+****************************************************************************/
+void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr)
+{
+	u32 ControlReg;
+	u32 BaseAddr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	ControlReg = XIicPs_In32(BaseAddr + XIICPS_CR_OFFSET);
+
+	/*
+	 * Set up master, AckEn, nea and also clear fifo.
+	 */
+	ControlReg |= (u32)XIICPS_CR_ACKEN_MASK | (u32)XIICPS_CR_CLR_FIFO_MASK;
+	ControlReg |= (u32)XIICPS_CR_NEA_MASK;
+	ControlReg &= (u32)(~XIICPS_CR_MS_MASK);
+
+	XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+			  ControlReg);
+
+	XIicPs_DisableAllInterrupts(BaseAddr);
+
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+	return;
+}
+
+/*****************************************************************************/
+/**
+* This function setup a slave interrupt-driven send. It set the repeated
+* start for the device is the tranfer size is larger than FIFO depth.
+* Data processing for the send is initiated by the interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the send buffer.
+* @param	ByteCount is the number of bytes to be sent.
+*
+* @return	None.
+*
+* @note		This send routine is for interrupt-driven transfer only.
+*
+****************************************************************************/
+void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
+{
+	u32 BaseAddr;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(MsgPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->SendBufferPtr = MsgPtr;
+	InstancePtr->SendByteCount = ByteCount;
+	InstancePtr->RecvBufferPtr = NULL;
+
+	XIicPs_EnableInterrupts(BaseAddr,
+			(u32)XIICPS_IXR_DATA_MASK | (u32)XIICPS_IXR_COMP_MASK |
+			(u32)XIICPS_IXR_TO_MASK | (u32)XIICPS_IXR_NACK_MASK |
+			(u32)XIICPS_IXR_TX_OVR_MASK);
+}
+
+/*****************************************************************************/
+/**
+* This function setup a slave interrupt-driven receive.
+* Data processing for the receive is handled by the interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the receive buffer.
+* @param	ByteCount is the number of bytes to be received.
+*
+* @return	None.
+*
+* @note		This routine is for interrupt-driven transfer only.
+*
+****************************************************************************/
+void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
+{
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(MsgPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+
+	InstancePtr->RecvBufferPtr = MsgPtr;
+	InstancePtr->RecvByteCount = ByteCount;
+	InstancePtr->SendBufferPtr = NULL;
+
+	XIicPs_EnableInterrupts(InstancePtr->Config.BaseAddress,
+		(u32)XIICPS_IXR_DATA_MASK | (u32)XIICPS_IXR_COMP_MASK |
+		(u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_TO_MASK |
+		(u32)XIICPS_IXR_RX_OVR_MASK | (u32)XIICPS_IXR_RX_UNF_MASK);
+
+}
+
+/*****************************************************************************/
+/**
+* This function sends  a buffer in polled mode as a slave.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the send buffer.
+* @param	ByteCount is the number of bytes to be sent.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if master sends us data or master terminates the
+*		transfer before all data has sent out.
+*
+* @note		This send routine is for polled mode transfer only.
+*
+****************************************************************************/
+s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
+{
+	u32 IntrStatusReg;
+	u32 StatusReg;
+	u32 BaseAddr;
+	s32 Tmp;
+	s32 BytesToSend;
+	s32 Error = 0;
+	s32 Status = (s32)XST_SUCCESS;
+	_Bool Value;
+	_Bool Result;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->SendBufferPtr = MsgPtr;
+	InstancePtr->SendByteCount = ByteCount;
+
+	/*
+	 * Use RXRW bit in status register to wait master to start a read.
+	 */
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+	Result = (((u32)(StatusReg & XIICPS_SR_RXRW_MASK) == (u32)0x0U) &&
+			(Error == 0));
+	while (Result != FALSE) {
+
+		/*
+		 * If master tries to send us data, it is an error.
+		 */
+		if ((StatusReg & XIICPS_SR_RXDV_MASK) != 0x0U) {
+			Error = 1;
+		}
+
+		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+		Result = (((u32)(StatusReg & XIICPS_SR_RXRW_MASK) == (u32)0x0U) &&
+				(Error == 0));
+	}
+
+	if (Error != 0) {
+		Status = (s32)XST_FAILURE;
+	} else {
+
+		/*
+		 * Clear the interrupt status register.
+		 */
+		IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+		XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+		/*
+		 * Send data as long as there is more data to send and
+		 * there are no errors.
+		 */
+		Value = (InstancePtr->SendByteCount > (s32)0) &&
+						((Error == 0));
+		while (Value != FALSE) {
+
+			/*
+			 * Find out how many can be sent.
+			 */
+			BytesToSend = InstancePtr->SendByteCount;
+			if (BytesToSend > (s32)(XIICPS_FIFO_DEPTH)) {
+				BytesToSend = (s32)(XIICPS_FIFO_DEPTH);
+			}
+
+			for(Tmp = 0; Tmp < BytesToSend; Tmp ++) {
+				XIicPs_SendByte(InstancePtr);
+			}
+
+			StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+			/*
+			 * Wait for master to read the data out of fifo.
+			 */
+			while (((StatusReg & XIICPS_SR_TXDV_MASK) != (u32)0x00U) &&
+							(Error == 0)) {
+
+				/*
+				 * If master terminates the transfer before all data is
+				 * sent, it is an error.
+				 */
+				IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+				XIICPS_ISR_OFFSET);
+				if ((IntrStatusReg & XIICPS_IXR_NACK_MASK) != 0x0U) {
+					Error = 1;
+				}
+
+				/* Clear ISR.
+				 */
+				XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET,
+							IntrStatusReg);
+
+				StatusReg = XIicPs_ReadReg(BaseAddr,
+						XIICPS_SR_OFFSET);
+			}
+			Value = ((InstancePtr->SendByteCount > (s32)0) &&
+							(Error == 0));
+		}
+	}
+	if (Error != 0) {
+		Status = (s32)XST_FAILURE;
+	}
+
+	return Status;
+}
+/*****************************************************************************/
+/**
+* This function receives a buffer in polled mode as a slave.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the receive buffer.
+* @param	ByteCount is the number of bytes to be received.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if timed out.
+*
+* @note		This receive routine is for polled mode transfer only.
+*
+****************************************************************************/
+s32 XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
+{
+	u32 IntrStatusReg;
+	u32 StatusReg;
+	u32 BaseAddr;
+	s32 Count;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->RecvBufferPtr = MsgPtr;
+	InstancePtr->RecvByteCount = ByteCount;
+
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+	/*
+	 * Clear the interrupt status register.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Clear the status register.
+	 */
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+	XIicPs_WriteReg(BaseAddr, XIICPS_SR_OFFSET, StatusReg);
+
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+	Count = InstancePtr->RecvByteCount;
+	while (Count > (s32)0) {
+
+		/* Wait for master to put data */
+		while ((StatusReg & XIICPS_SR_RXDV_MASK) == 0U) {
+		    StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+			/*
+			 * If master terminates the transfer before we get all
+			 * the data or the master tries to read from us,
+			 * it is an error.
+			 */
+			IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+						XIICPS_ISR_OFFSET);
+			if (((IntrStatusReg & (XIICPS_IXR_DATA_MASK |
+					XIICPS_IXR_COMP_MASK))!=0x0U) &&
+				((StatusReg & XIICPS_SR_RXDV_MASK) == 0U) &&
+				((InstancePtr->RecvByteCount > 0) != 0x0U)) {
+
+				return (s32)XST_FAILURE;
+			}
+
+			/*
+			 * Clear the interrupt status register.
+			 */
+			XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET,
+			IntrStatusReg);
+		}
+
+		/*
+		 * Read all data from FIFO.
+		 */
+		while (((StatusReg & XIICPS_SR_RXDV_MASK)!=0x0U) &&
+			 ((InstancePtr->RecvByteCount > 0) != 0x0U)){
+
+			XIicPs_RecvByte(InstancePtr);
+
+			StatusReg = XIicPs_ReadReg(BaseAddr,
+				XIICPS_SR_OFFSET);
+		}
+		Count = InstancePtr->RecvByteCount;
+	}
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* The interrupt handler for slave mode. It does the protocol handling for
+* the interrupt-driven transfers.
+*
+* Completion events and errors are signaled to upper layer for proper
+* handling.
+*
+* <pre>
+*
+* The interrupts that are handled are:
+* - DATA
+*	If the instance is sending, it means that the master wants to read more
+*	data from us. Send more data, and check whether we are done with this
+*	send.
+*
+*	If the instance is receiving, it means that the master has writen
+* 	more data to us. Receive more data, and check whether we are done with
+*	with this receive.
+*
+* - COMP
+*	This marks that stop sequence has been sent from the master, transfer
+*	is about to terminate. However, for receiving, the master may have
+*	written us some data, so receive that first.
+*
+*	It is an error if the amount of transfered data is less than expected.
+*
+* - NAK
+*	This marks that master does not want our data. It is for send only.
+*
+* - Other interrupts
+*	These interrupts are marked as error.
+*
+* </pre>
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note 	None.
+*
+****************************************************************************/
+void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr)
+{
+	u32 IntrStatusReg;
+	u32 IsSend = 0U;
+	u32 StatusEvent = 0U;
+	s32 LeftOver;
+	u32 BaseAddr;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	/*
+	 * Read the Interrupt status register.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+
+	/*
+	 * Write the status back to clear the interrupts so no events are missed
+	 * while processing this interrupt.
+	 */
+	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Use the Mask register AND with the Interrupt Status register so
+	 * disabled interrupts are not processed.
+	 */
+	IntrStatusReg &= ~(XIicPs_ReadReg(BaseAddr, XIICPS_IMR_OFFSET));
+
+	/*
+	 * Determine whether the device is sending.
+	 */
+	if (InstancePtr->RecvBufferPtr == NULL) {
+		IsSend = 1U;
+	}
+
+	/* Data interrupt
+	 *
+	 * This means master wants to do more data transfers.
+	 * Also check for completion of transfer, signal upper layer if done.
+	 */
+	if ((u32)0U != (IntrStatusReg & XIICPS_IXR_DATA_MASK)) {
+		if (IsSend != 0x0U) {
+			LeftOver = TransmitFifoFill(InstancePtr);
+				/*
+				 * We may finish send here
+				 */
+				if (LeftOver == 0) {
+					StatusEvent |=
+						XIICPS_EVENT_COMPLETE_SEND;
+				}
+		} else {
+			LeftOver = SlaveRecvData(InstancePtr);
+
+			/* We may finish the receive here */
+			if (LeftOver == 0) {
+				StatusEvent |= XIICPS_EVENT_COMPLETE_RECV;
+			}
+		}
+	}
+
+	/*
+	 * Complete interrupt.
+	 *
+	 * In slave mode, it means the master has done with this transfer, so
+	 * we signal the application using completion event.
+	 */
+	if (0U != (IntrStatusReg & XIICPS_IXR_COMP_MASK)) {
+		if (IsSend != 0x0U) {
+			if (InstancePtr->SendByteCount > 0) {
+				StatusEvent |= XIICPS_EVENT_ERROR;
+			}else {
+				StatusEvent |= XIICPS_EVENT_COMPLETE_SEND;
+			}
+		} else {
+			LeftOver = SlaveRecvData(InstancePtr);
+			if (LeftOver > 0) {
+				StatusEvent |= XIICPS_EVENT_ERROR;
+			} else {
+				StatusEvent |= XIICPS_EVENT_COMPLETE_RECV;
+			}
+		}
+	}
+
+	/*
+	 * Nack interrupt, pass this information to application.
+	 */
+	if (0U != (IntrStatusReg & XIICPS_IXR_NACK_MASK)) {
+		StatusEvent |= XIICPS_EVENT_NACK;
+	}
+
+	/*
+	 * All other interrupts are treated as error.
+	 */
+	if (0U != (IntrStatusReg & (XIICPS_IXR_TO_MASK |
+				XIICPS_IXR_RX_UNF_MASK |
+				XIICPS_IXR_TX_OVR_MASK |
+				XIICPS_IXR_RX_OVR_MASK))){
+
+		StatusEvent |= XIICPS_EVENT_ERROR;
+	}
+
+	/*
+	 * Signal application if there are any events.
+	 */
+	if ((u32)0U != StatusEvent) {
+		InstancePtr->StatusHandler(InstancePtr->CallBackRef,
+					   StatusEvent);
+	}
+}
+
+/*****************************************************************************/
+/*
+*
+* This function handles continuation of receiving data. It is invoked
+* from interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	Number of bytes still expected by the instance.
+*
+* @note		None.
+*
+****************************************************************************/
+static s32 SlaveRecvData(XIicPs *InstancePtr)
+{
+	u32 StatusReg;
+	u32 BaseAddr;
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+	while (((StatusReg & XIICPS_SR_RXDV_MASK)!=0x0U) &&
+			((InstancePtr->RecvByteCount > 0) != 0x0U)) {
+		XIicPs_RecvByte(InstancePtr);
+		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+	}
+
+	return InstancePtr->RecvByteCount;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/Makefile b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..68ad57aba48f5be085f29b876d35509897b0c099
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/Makefile
@@ -0,0 +1,26 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o
+
+libs:
+	echo "Compiling pwm_recorder..."
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+	make clean
+
+include:
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder.c
new file mode 100644
index 0000000000000000000000000000000000000000..bed446fbf14cf53017258dd4c93e86a366fd3691
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder.c
@@ -0,0 +1,6 @@
+
+
+/***************************** Include Files *******************************/
+#include "pwm_recorder.h"
+
+/************************** Function Definitions ***************************/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder.h
new file mode 100644
index 0000000000000000000000000000000000000000..cedcc1e5074066ee8d882c8034363d639255f7dd
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder.h
@@ -0,0 +1,79 @@
+
+#ifndef PWM_RECORDER_H
+#define PWM_RECORDER_H
+
+
+/****************** Include Files ********************/
+#include "xil_types.h"
+#include "xstatus.h"
+
+#define PWM_RECORDER_S_AXI_SLV_REG0_OFFSET 0
+#define PWM_RECORDER_S_AXI_SLV_REG1_OFFSET 4
+#define PWM_RECORDER_S_AXI_SLV_REG2_OFFSET 8
+#define PWM_RECORDER_S_AXI_SLV_REG3_OFFSET 12
+
+
+/**************************** Type Definitions *****************************/
+/**
+ *
+ * Write a value to a PWM_RECORDER register. A 32 bit write is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is written.
+ *
+ * @param   BaseAddress is the base address of the PWM_RECORDERdevice.
+ * @param   RegOffset is the register offset from the base to write to.
+ * @param   Data is the data written to the register.
+ *
+ * @return  None.
+ *
+ * @note
+ * C-style signature:
+ * 	void PWM_RECORDER_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
+ *
+ */
+#define PWM_RECORDER_mWriteReg(BaseAddress, RegOffset, Data) \
+  	Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/**
+ *
+ * Read a value from a PWM_RECORDER register. A 32 bit read is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is read from the register. The most significant data
+ * will be read as 0.
+ *
+ * @param   BaseAddress is the base address of the PWM_RECORDER device.
+ * @param   RegOffset is the register offset from the base to write to.
+ *
+ * @return  Data is the data from the register.
+ *
+ * @note
+ * C-style signature:
+ * 	u32 PWM_RECORDER_mReadReg(u32 BaseAddress, unsigned RegOffset)
+ *
+ */
+#define PWM_RECORDER_mReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ****************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the PWM_RECORDER instance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus PWM_RECORDER_Reg_SelfTest(void * baseaddr_p);
+
+#endif // PWM_RECORDER_H
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder_selftest.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder_selftest.c
new file mode 100644
index 0000000000000000000000000000000000000000..8f6d89fbac0b22cb357695f4f78aea3d8e5186ae
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_recorder_v1_0/src/pwm_recorder_selftest.c
@@ -0,0 +1,60 @@
+
+/***************************** Include Files *******************************/
+#include "pwm_recorder.h"
+#include "xparameters.h"
+#include "stdio.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ***************************/
+#define READ_WRITE_MUL_FACTOR 0x10
+
+/************************** Function Definitions ***************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the PWM_RECORDERinstance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus PWM_RECORDER_Reg_SelfTest(void * baseaddr_p)
+{
+	u32 baseaddr;
+	int write_loop_index;
+	int read_loop_index;
+	int Index;
+
+	baseaddr = (u32) baseaddr_p;
+
+	xil_printf("******************************\n\r");
+	xil_printf("* User Peripheral Self Test\n\r");
+	xil_printf("******************************\n\n\r");
+
+	/*
+	 * Write to user logic slave module register(s) and read back
+	 */
+	xil_printf("User logic slave module test...\n\r");
+
+	for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
+	  PWM_RECORDER_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
+	for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
+	  if ( PWM_RECORDER_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
+	    xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
+	    return XST_FAILURE;
+	  }
+
+	xil_printf("   - slave register write/read passed\n\n\r");
+
+	return XST_SUCCESS;
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/Makefile b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..30682bc09c2ab69e329baaf842a4f94b21546516
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/Makefile
@@ -0,0 +1,26 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o
+
+libs:
+	echo "Compiling pwm_signal_out..."
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+	make clean
+
+include:
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out.c
new file mode 100644
index 0000000000000000000000000000000000000000..5c5383eca518fa6202375f790a8e1818a3c60597
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out.c
@@ -0,0 +1,6 @@
+
+
+/***************************** Include Files *******************************/
+#include "pwm_signal_out.h"
+
+/************************** Function Definitions ***************************/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out.h
new file mode 100644
index 0000000000000000000000000000000000000000..4a80786f653d5f83b9b3dd6e992e4f6e5afab37a
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out.h
@@ -0,0 +1,79 @@
+
+#ifndef PWM_SIGNAL_OUT_H
+#define PWM_SIGNAL_OUT_H
+
+
+/****************** Include Files ********************/
+#include "xil_types.h"
+#include "xstatus.h"
+
+#define PWM_SIGNAL_OUT_S_AXI_SLV_REG0_OFFSET 0
+#define PWM_SIGNAL_OUT_S_AXI_SLV_REG1_OFFSET 4
+#define PWM_SIGNAL_OUT_S_AXI_SLV_REG2_OFFSET 8
+#define PWM_SIGNAL_OUT_S_AXI_SLV_REG3_OFFSET 12
+
+
+/**************************** Type Definitions *****************************/
+/**
+ *
+ * Write a value to a PWM_SIGNAL_OUT register. A 32 bit write is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is written.
+ *
+ * @param   BaseAddress is the base address of the PWM_SIGNAL_OUTdevice.
+ * @param   RegOffset is the register offset from the base to write to.
+ * @param   Data is the data written to the register.
+ *
+ * @return  None.
+ *
+ * @note
+ * C-style signature:
+ * 	void PWM_SIGNAL_OUT_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
+ *
+ */
+#define PWM_SIGNAL_OUT_mWriteReg(BaseAddress, RegOffset, Data) \
+  	Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/**
+ *
+ * Read a value from a PWM_SIGNAL_OUT register. A 32 bit read is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is read from the register. The most significant data
+ * will be read as 0.
+ *
+ * @param   BaseAddress is the base address of the PWM_SIGNAL_OUT device.
+ * @param   RegOffset is the register offset from the base to write to.
+ *
+ * @return  Data is the data from the register.
+ *
+ * @note
+ * C-style signature:
+ * 	u32 PWM_SIGNAL_OUT_mReadReg(u32 BaseAddress, unsigned RegOffset)
+ *
+ */
+#define PWM_SIGNAL_OUT_mReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ****************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the PWM_SIGNAL_OUT instance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus PWM_SIGNAL_OUT_Reg_SelfTest(void * baseaddr_p);
+
+#endif // PWM_SIGNAL_OUT_H
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out_selftest.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out_selftest.c
new file mode 100644
index 0000000000000000000000000000000000000000..f21e3dd81e221dbe6a089366bcddde2c8c7bc66d
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/pwm_signal_out_v1_0/src/pwm_signal_out_selftest.c
@@ -0,0 +1,60 @@
+
+/***************************** Include Files *******************************/
+#include "pwm_signal_out.h"
+#include "xparameters.h"
+#include "stdio.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ***************************/
+#define READ_WRITE_MUL_FACTOR 0x10
+
+/************************** Function Definitions ***************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the PWM_SIGNAL_OUTinstance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus PWM_SIGNAL_OUT_Reg_SelfTest(void * baseaddr_p)
+{
+	u32 baseaddr;
+	int write_loop_index;
+	int read_loop_index;
+	int Index;
+
+	baseaddr = (u32) baseaddr_p;
+
+	xil_printf("******************************\n\r");
+	xil_printf("* User Peripheral Self Test\n\r");
+	xil_printf("******************************\n\n\r");
+
+	/*
+	 * Write to user logic slave module register(s) and read back
+	 */
+	xil_printf("User logic slave module test...\n\r");
+
+	for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
+	  PWM_SIGNAL_OUT_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
+	for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
+	  if ( PWM_SIGNAL_OUT_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
+	    xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
+	    return XST_FAILURE;
+	  }
+
+	xil_printf("   - slave register write/read passed\n\n\r");
+
+	return XST_SUCCESS;
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/Makefile b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..360092897d0444300c671d62d1838fa8be36008e
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xqspips_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling qspips"
+
+xqspips_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xqspips_includes
+
+xqspips_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips.c
new file mode 100644
index 0000000000000000000000000000000000000000..086b9887e88f69d9be9e75b9ed4fde4e1639d8ce
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips.c
@@ -0,0 +1,1571 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips.c
+* @addtogroup qspips_v3_2
+* @{
+*
+* Contains implements the interface functions of the XQspiPs driver.
+* See xqspips.h for a detailed description of the device and driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00  sdm 11/25/10 First release
+* 2.00a kka 07/25/12 Removed XQspiPs_GetWriteData API.
+*		     The XQspiPs_SetSlaveSelect has been modified to remove
+*		     the argument of the slave select as the QSPI controller
+*		     only supports one slave.
+* 		     XQspiPs_GetSlaveSelect API has been removed
+* 		     Added logic to XQspiPs_GetReadData to handle data
+*		     shift for normal data reads and instruction/status
+*		     reads differently based on the ShiftReadData flag.
+* 		     Removed the selection for the following options:
+*		     Master mode (XQSPIPS_MASTER_OPTION) and
+*		     Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
+*		     as the QSPI driver supports the Master mode
+*		     and Flash Interface mode and doesnot support
+*		     Slave mode or the legacy mode.
+*		     Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
+*		     APIs so that the last argument (IsInst) specifying whether
+*		     it is instruction or data has been removed. The first byte
+*		     in the SendBufPtr argument of these APIs specify the
+*		     instruction to be sent to the Flash Device.
+*		     The XQspiPs_PolledTransfer function has been updated
+*		     to fill the data to fifo depth.
+*		     This version of the driver fixes CRs 670197/663787.
+* 2.01a sg  02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
+*		     Created macros XQspiPs_IsManualStart and
+*		     XQspiPs_IsManualChipSelect.
+*		     Changed QSPI transfer logic for polled and interrupt
+*		     modes to be based on filled tx fifo count and receive
+*		     based on it. RXNEMPTY interrupt is not used.
+*		     Added assertions to XQspiPs_LqspiRead function.
+*
+* 2.02a hk  05/14/13 Added enable and disable to the XQspiPs_LqspiRead()
+*			 function
+*            Added instructions for bank selection, die erase and
+*            flag status register to the flash instruction table
+*            Handling for instructions not in flash instruction
+*			 table added. Checking for Tx FIFO empty when switching from
+*			 TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
+*            byte count 3 (spansion), instruction size and TXD register
+*			 changed accordingly. CR# 712502 and 703869.
+*            Added (#ifdef linear base address) in the Linear read function.
+*            Changed  XPAR_XQSPIPS_0_LINEAR_BASEADDR to
+*            XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
+*            XQspiPs_LqspiRead function. Fix for CR#718141
+*
+* 2.03a hk  09/05/13 Modified polled and interrupt transfers to make use of
+*                    thresholds. This is to improve performance.
+*                    Added RX and TX threshold reset to one in XQspiPs_Abort.
+*                    Added RX threshold reset(1) after transfer in polled and
+*                    interrupt transfers. Made changes to make sure threshold
+*                    change is done only when no transfer is in progress.
+* 3.1   hk  08/13/14 When writing to the configuration register, set/reset
+*                    required bits leaving reserved bits untouched. CR# 796813.
+* 3.2	sk	02/05/15 Add SLCR reset in abort function as a workaround because
+* 					 controller does not update FIFO status flags as expected
+* 					 when thresholds are used.
+* 3.3   sk  11/07/15 Modified the API prototypes according to MISRAC standards
+*                    to remove compilation warnings. CR# 868893.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef defines qspi flash instruction format
+ */
+typedef struct {
+	u8 OpCode;	/**< Operational code of the instruction */
+	u8 InstSize;	/**< Size of the instruction including address bytes */
+	u8 TxOffset;	/**< Register address where instruction has to be
+			     written */
+} XQspiPsInstFormat;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define ARRAY_SIZE(Array)		(sizeof(Array) / sizeof((Array)[0]))
+
+/************************** Function Prototypes ******************************/
+static void XQspiPs_GetReadData(XQspiPs *InstancePtr, u32 Data, u8 Size);
+static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
+				unsigned ByteCount);
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * List of all the QSPI instructions and its format
+ */
+static XQspiPsInstFormat FlashInst[] = {
+	{ XQSPIPS_FLASH_OPCODE_WREN, 1, XQSPIPS_TXD_01_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_WRDS, 1, XQSPIPS_TXD_01_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_RDSR1, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_RDSR2, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_WRSR, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_PP, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_SE, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_BE_32K, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_BE_4K, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_BE, 1, XQSPIPS_TXD_01_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_ERASE_SUS, 1, XQSPIPS_TXD_01_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_ERASE_RES, 1, XQSPIPS_TXD_01_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_RDID, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_NORM_READ, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_FAST_READ, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_DUAL_READ, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_QUAD_READ, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_DUAL_IO_READ, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_QUAD_IO_READ, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_BRWR, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_BRRD, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_EARWR, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_EARRD, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_DIE_ERASE, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_READ_FLAG_SR, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR, 1, XQSPIPS_TXD_01_OFFSET },
+	/* Add all the instructions supported by the flash device */
+};
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XQspiPs instance such that the driver is ready to use.
+*
+* The state of the device after initialization is:
+*   - Master mode
+*   - Active high clock polarity
+*   - Clock phase 0
+*   - Baud rate divisor 2
+*   - Transfer width 32
+*   - Master reference clock = pclk
+*   - No chip select active
+*   - Manual CS and Manual Start disabled
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	ConfigPtr is a reference to a structure containing information
+*		about a specific QSPI device. This function initializes an
+*		InstancePtr object for a specific device specified by the
+*		contents of Config.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, use
+*		ConfigPtr->Config.BaseAddress for this device.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_DEVICE_IS_STARTED if the device is already started.
+*		It must be stopped to re-initialize.
+*
+* @note		None.
+*
+******************************************************************************/
+int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * If the device is busy, disallow the initialize and return a status
+	 * indicating it is already started. This allows the user to stop the
+	 * device and re-initialize, but prevents a user from inadvertently
+	 * initializing. This assumes the busy flag is cleared at startup.
+	 */
+	if (InstancePtr->IsBusy == TRUE) {
+		return XST_DEVICE_IS_STARTED;
+	}
+
+	/*
+	 * Set some default values.
+	 */
+	InstancePtr->IsBusy = FALSE;
+
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->StatusHandler = StubStatusHandler;
+
+	InstancePtr->SendBufferPtr = NULL;
+	InstancePtr->RecvBufferPtr = NULL;
+	InstancePtr->RequestedBytes = 0;
+	InstancePtr->RemainingBytes = 0;
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	InstancePtr->Config.ConnectionMode = ConfigPtr->ConnectionMode;
+
+	/*
+	 * Reset the QSPI device to get it into its initial state. It is
+	 * expected that device configuration will take place after this
+	 * initialization is done, but before the device is started.
+	 */
+	XQspiPs_Reset(InstancePtr);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Resets the QSPI device. Reset must only be called after the driver has been
+* initialized. Any data transfer that is in progress is aborted.
+*
+* The upper layer software is responsible for re-configuring (if necessary)
+* and restarting the QSPI device after the reset.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XQspiPs_Reset(XQspiPs *InstancePtr)
+{
+	u32 ConfigReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Abort any transfer that is in progress
+	 */
+	XQspiPs_Abort(InstancePtr);
+
+	/*
+	 * Write default value to configuration register.
+	 * Do not modify reserved bits.
+	 */
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+			 XQSPIPS_CR_OFFSET);
+	ConfigReg |= XQSPIPS_CR_RESET_MASK_SET;
+	ConfigReg &= ~XQSPIPS_CR_RESET_MASK_CLR;
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET,
+			  ConfigReg);
+}
+
+/*****************************************************************************/
+/**
+*
+* Aborts a transfer in progress by disabling the device and flush the RxFIFO.
+* The byte counts are cleared, the busy flag is cleared.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	None.
+*
+* @note
+*
+* This function does a read/modify/write of the config register. The user of
+* this function needs to take care of critical sections.
+*
+******************************************************************************/
+void XQspiPs_Abort(XQspiPs *InstancePtr)
+{
+	u32 ConfigReg;
+	u32 IsLock;
+
+	XQspiPs_Disable(InstancePtr);
+
+	/*
+	 * De-assert slave select lines.
+	 */
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+			 XQSPIPS_CR_OFFSET);
+	ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK);
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			 XQSPIPS_CR_OFFSET, ConfigReg);
+
+	/*
+	 * QSPI Software Reset
+	 */
+	IsLock = XQspiPs_ReadReg(XPAR_XSLCR_0_BASEADDR, SLCR_LOCKSTA);
+	if (IsLock) {
+		XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, SLCR_UNLOCK,
+				SLCR_UNLOCK_MASK);
+	}
+	XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, LQSPI_RST_CTRL,
+			LQSPI_RST_CTRL_MASK);
+	XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, LQSPI_RST_CTRL, 0x0);
+	if (IsLock) {
+		XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, SLCR_LOCK,
+				SLCR_LOCK_MASK);
+	}
+
+	/*
+	 * Set the RX and TX FIFO threshold to reset value (one)
+	 */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPS_TXWR_OFFSET, XQSPIPS_TXWR_RESET_VALUE);
+
+	InstancePtr->RemainingBytes = 0;
+	InstancePtr->RequestedBytes = 0;
+	InstancePtr->IsBusy = FALSE;
+}
+
+/*****************************************************************************/
+/**
+*
+* Transfers specified data on the QSPI bus. Initiates bus communication and
+* sends/receives data to/from the selected QSPI slave. For every byte sent,
+* a byte is received.
+*
+* The caller has the option of providing two different buffers for send and
+* receive, or one buffer for both send and receive, or no buffer for receive.
+* The receive buffer must be at least as big as the send buffer to prevent
+* unwanted memory writes. This implies that the byte count passed in as an
+* argument must be the smaller of the two buffers if they differ in size.
+* Here are some sample usages:
+* <pre>
+*   XQspiPs_Transfer(InstancePtr, SendBuf, RecvBuf, ByteCount)
+*	The caller wishes to send and receive, and provides two different
+*	buffers for send and receive.
+*
+*   XQspiPs_Transfer(InstancePtr, SendBuf, NULL, ByteCount)
+*	The caller wishes only to send and does not care about the received
+*	data. The driver ignores the received data in this case.
+*
+*   XQspiPs_Transfer(InstancePtr, SendBuf, SendBuf, ByteCount)
+*	The caller wishes to send and receive, but provides the same buffer
+*	for doing both. The driver sends the data and overwrites the send
+*	buffer with received data as it transfers the data.
+*
+*   XQspiPs_Transfer(InstancePtr, RecvBuf, RecvBuf, ByteCount)
+*	The caller wishes to only receive and does not care about sending
+*	data.  In this case, the caller must still provide a send buffer, but
+*	it can be the same as the receive buffer if the caller does not care
+*	what it sends.  The device must send N bytes of data if it wishes to
+*	receive N bytes of data.
+* </pre>
+* Although this function takes entire buffers as arguments, the driver can only
+* transfer a limited number of bytes at a time, limited by the size of the
+* FIFO. A call to this function only starts the transfer, then subsequent
+* transfers of the data is performed by the interrupt service routine until
+* the entire buffer has been transferred. The status callback function is
+* called when the entire buffer has been sent/received.
+*
+* This function is non-blocking. The SetSlaveSelect function must be called
+* prior to this function.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	SendBufPtr is a pointer to a data buffer that needs to be
+*		transmitted. This buffer must not be NULL.
+* @param	RecvBufPtr is a pointer to a buffer for received data.
+*		This argument can be NULL if do not care about receiving.
+* @param	ByteCount contains the number of bytes to send/receive.
+*		The number of bytes received always equals the number of bytes
+*		sent.
+*
+* @return
+*		- XST_SUCCESS if the buffers are successfully handed off to the
+*		  device for transfer.
+*		- XST_DEVICE_BUSY indicates that a data transfer is already in
+*		  progress. This is determined by the driver.
+*
+* @note
+*
+* This function is not thread-safe.  The higher layer software must ensure that
+* no two threads are transferring data on the QSPI bus at the same time.
+*
+******************************************************************************/
+s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
+			u32 ByteCount)
+{
+	u32 StatusReg;
+	u32 ConfigReg;
+	u8 Instruction;
+	u32 Data;
+	unsigned int Index;
+	u8 TransCount = 0;
+	XQspiPsInstFormat *CurrInst;
+	XQspiPsInstFormat NewInst[2];
+	u8 SwitchFlag  = 0;
+
+	CurrInst = &NewInst[0];
+
+	/*
+	 * The RecvBufPtr argument can be null
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(SendBufPtr != NULL);
+	Xil_AssertNonvoid(ByteCount > 0);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Check whether there is another transfer in progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	/*
+	 * Set the busy flag, which will be cleared in the ISR when the
+	 * transfer is entirely done.
+	 */
+	InstancePtr->IsBusy = TRUE;
+
+	/*
+	 * Set up buffer pointers.
+	 */
+	InstancePtr->SendBufferPtr = SendBufPtr;
+	InstancePtr->RecvBufferPtr = RecvBufPtr;
+
+	InstancePtr->RequestedBytes = ByteCount;
+	InstancePtr->RemainingBytes = ByteCount;
+
+	/*
+	 * The first byte with every chip-select assertion is always
+	 * expected to be an instruction for flash interface mode
+	 */
+	Instruction = *InstancePtr->SendBufferPtr;
+
+	for (Index = 0 ; Index < ARRAY_SIZE(FlashInst); Index++) {
+		if (Instruction == FlashInst[Index].OpCode) {
+			break;
+		}
+	}
+
+	/*
+	 * Set the RX FIFO threshold
+	 */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT);
+
+	/*
+	 * If the slave select is "Forced" or under manual control,
+	 * set the slave select now, before beginning the transfer.
+	 */
+	if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+		ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XQSPIPS_CR_OFFSET);
+		ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPS_CR_OFFSET,
+				  ConfigReg);
+	}
+
+	/*
+	 * Enable the device.
+	 */
+	XQspiPs_Enable(InstancePtr);
+
+	/*
+	 * Clear all the interrrupts.
+	 */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_SR_OFFSET,
+			XQSPIPS_IXR_WR_TO_CLR_MASK);
+
+	if (Index < ARRAY_SIZE(FlashInst)) {
+		CurrInst = &FlashInst[Index];
+		/*
+		 * Check for WRSR instruction which has different size for
+		 * Spansion (3 bytes) and Micron (2 bytes)
+		 */
+		if( (CurrInst->OpCode == XQSPIPS_FLASH_OPCODE_WRSR) &&
+			(ByteCount == 3) ) {
+			CurrInst->InstSize = 3;
+			CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
+		}
+	}
+
+	/*
+	 * If instruction not present in table
+	 */
+	if (Index == ARRAY_SIZE(FlashInst)) {
+		/*
+		 * Assign current instruction, size and TXD register to be used
+		 * The InstSize mentioned in case of instructions greater than
+		 * 4 bytes is not the actual size, but is indicative of
+		 * the TXD register used.
+		 * The remaining bytes of the instruction will be transmitted
+		 * through TXD0 below.
+		 */
+		switch(ByteCount%4)
+		{
+			case XQSPIPS_SIZE_ONE:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_ONE;
+				CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET;
+				if(ByteCount > 4) {
+					SwitchFlag = 1;
+				}
+				break;
+			case XQSPIPS_SIZE_TWO:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_TWO;
+				CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET;
+				if(ByteCount > 4) {
+					SwitchFlag = 1;
+				}
+				break;
+			case XQSPIPS_SIZE_THREE:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_THREE;
+				CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
+				if(ByteCount > 4) {
+					SwitchFlag = 1;
+				}
+				break;
+			default:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_FOUR;
+				CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET;
+				break;
+		}
+	}
+
+	/*
+	 * If the instruction size in not 4 bytes then the data received needs
+	 * to be shifted
+	 */
+	if( CurrInst->InstSize != 4 ) {
+		InstancePtr->ShiftReadData = 1;
+	} else {
+		InstancePtr->ShiftReadData = 0;
+	}
+
+	/* Get the complete command (flash inst + address/data) */
+	Data = *((u32 *)InstancePtr->SendBufferPtr);
+	InstancePtr->SendBufferPtr += CurrInst->InstSize;
+	InstancePtr->RemainingBytes -= CurrInst->InstSize;
+	if (InstancePtr->RemainingBytes < 0) {
+		InstancePtr->RemainingBytes = 0;
+	}
+
+	/* Write the command to the FIFO */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			 CurrInst->TxOffset, Data);
+	TransCount++;
+
+	/*
+	 * If switching from TXD1/2/3 to TXD0, then start transfer and
+	 * check for FIFO empty
+	 */
+	if(SwitchFlag == 1) {
+		SwitchFlag = 0;
+		/*
+		 * If, in Manual Start mode, start the transfer.
+		 */
+		if (XQspiPs_IsManualStart(InstancePtr)) {
+			ConfigReg = XQspiPs_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET);
+			ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+			XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET, ConfigReg);
+		}
+		/*
+		 * Wait for the transfer to finish by polling Tx fifo status.
+		 */
+		do {
+			StatusReg = XQspiPs_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					XQSPIPS_SR_OFFSET);
+		} while ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0);
+
+	}
+
+	/*
+	 * Fill the Tx FIFO with as many bytes as it takes (or as many as
+	 * we have to send).
+	 */
+	while ((InstancePtr->RemainingBytes > 0) &&
+		(TransCount < XQSPIPS_FIFO_DEPTH)) {
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPS_TXD_00_OFFSET,
+				  *((u32 *)InstancePtr->SendBufferPtr));
+		InstancePtr->SendBufferPtr += 4;
+		InstancePtr->RemainingBytes -= 4;
+		if (InstancePtr->RemainingBytes < 0) {
+			InstancePtr->RemainingBytes = 0;
+		}
+		TransCount++;
+	}
+
+	/*
+	 * Enable QSPI interrupts (connecting to the interrupt controller and
+	 * enabling interrupts should have been done by the caller).
+	 */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XQSPIPS_IER_OFFSET, XQSPIPS_IXR_RXNEMPTY_MASK |
+			  XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXOVR_MASK |
+			  XQSPIPS_IXR_TXUF_MASK);
+
+	/*
+	 * If, in Manual Start mode, Start the transfer.
+	 */
+	if (XQspiPs_IsManualStart(InstancePtr)) {
+		ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XQSPIPS_CR_OFFSET);
+		ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPS_CR_OFFSET, ConfigReg);
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Transfers specified data on the QSPI bus in polled mode.
+*
+* The caller has the option of providing two different buffers for send and
+* receive, or one buffer for both send and receive, or no buffer for receive.
+* The receive buffer must be at least as big as the send buffer to prevent
+* unwanted memory writes. This implies that the byte count passed in as an
+* argument must be the smaller of the two buffers if they differ in size.
+* Here are some sample usages:
+* <pre>
+*   XQspiPs_PolledTransfer(InstancePtr, SendBuf, RecvBuf, ByteCount)
+*	The caller wishes to send and receive, and provides two different
+*	buffers for send and receive.
+*
+*   XQspiPs_PolledTransfer(InstancePtr, SendBuf, NULL, ByteCount)
+*	The caller wishes only to send and does not care about the received
+*	data. The driver ignores the received data in this case.
+*
+*   XQspiPs_PolledTransfer(InstancePtr, SendBuf, SendBuf, ByteCount)
+*	The caller wishes to send and receive, but provides the same buffer
+*	for doing both. The driver sends the data and overwrites the send
+*	buffer with received data as it transfers the data.
+*
+*   XQspiPs_PolledTransfer(InstancePtr, RecvBuf, RecvBuf, ByteCount)
+*	The caller wishes to only receive and does not care about sending
+*	data.  In this case, the caller must still provide a send buffer, but
+*	it can be the same as the receive buffer if the caller does not care
+*	what it sends.  The device must send N bytes of data if it wishes to
+*	receive N bytes of data.
+*
+* </pre>
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	SendBufPtr is a pointer to a data buffer that needs to be
+*		transmitted. This buffer must not be NULL.
+* @param	RecvBufPtr is a pointer to a buffer for received data.
+*		This argument can be NULL if do not care about receiving.
+* @param	ByteCount contains the number of bytes to send/receive.
+*		The number of bytes received always equals the number of bytes
+*		sent.
+* @return
+*		- XST_SUCCESS if the buffers are successfully handed off to the
+*		  device for transfer.
+*		- XST_DEVICE_BUSY indicates that a data transfer is already in
+*		  progress. This is determined by the driver.
+*
+* @note
+*
+* This function is not thread-safe.  The higher layer software must ensure that
+* no two threads are transferring data on the QSPI bus at the same time.
+*
+******************************************************************************/
+s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
+			    u8 *RecvBufPtr, u32 ByteCount)
+{
+	u32 StatusReg;
+	u32 ConfigReg;
+	u8 Instruction;
+	u32 Data;
+	u8 TransCount;
+	unsigned int Index;
+	XQspiPsInstFormat *CurrInst;
+	XQspiPsInstFormat NewInst[2];
+	u8 SwitchFlag  = 0;
+	u8 IsManualStart = FALSE;
+	u32 RxCount = 0;
+
+	CurrInst = &NewInst[0];
+	/*
+	 * The RecvBufPtr argument can be NULL.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(SendBufPtr != NULL);
+	Xil_AssertNonvoid(ByteCount > 0);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Check whether there is another transfer in progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	/*
+	 * Set the busy flag, which will be cleared when the transfer is
+	 * entirely done.
+	 */
+	InstancePtr->IsBusy = TRUE;
+
+	/*
+	 * Set up buffer pointers.
+	 */
+	InstancePtr->SendBufferPtr = SendBufPtr;
+	InstancePtr->RecvBufferPtr = RecvBufPtr;
+
+	InstancePtr->RequestedBytes = ByteCount;
+	InstancePtr->RemainingBytes = ByteCount;
+
+	/*
+	 * The first byte with every chip-select assertion is always
+	 * expected to be an instruction for flash interface mode
+	 */
+	Instruction = *InstancePtr->SendBufferPtr;
+
+	for (Index = 0 ; Index < ARRAY_SIZE(FlashInst); Index++) {
+		if (Instruction == FlashInst[Index].OpCode) {
+			break;
+		}
+	}
+
+	/*
+	 * Set the RX FIFO threshold
+	 */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT);
+
+	/*
+	 * If the slave select is "Forced" or under manual control,
+	 * set the slave select now, before beginning the transfer.
+	 */
+	if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+		ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XQSPIPS_CR_OFFSET);
+		ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPS_CR_OFFSET,
+				  ConfigReg);
+	}
+
+	/*
+	 * Enable the device.
+	 */
+	XQspiPs_Enable(InstancePtr);
+
+	if (Index < ARRAY_SIZE(FlashInst)) {
+
+		CurrInst = &FlashInst[Index];
+		/*
+		 * Check for WRSR instruction which has different size for
+		 * Spansion (3 bytes) and Micron (2 bytes)
+		 */
+		if( (CurrInst->OpCode == XQSPIPS_FLASH_OPCODE_WRSR) &&
+			(ByteCount == 3) ) {
+			CurrInst->InstSize = 3;
+			CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
+		}
+	}
+
+	/*
+	 * If instruction not present in table
+	 */
+	if (Index == ARRAY_SIZE(FlashInst)) {
+		/*
+		 * Assign current instruction, size and TXD register to be used.
+		 * The InstSize mentioned in case of instructions greater than 4 bytes
+		 * is not the actual size, but is indicative of the TXD register used.
+		 * The remaining bytes of the instruction will be transmitted
+		 * through TXD0 below.
+		 */
+		switch(ByteCount%4)
+		{
+			case XQSPIPS_SIZE_ONE:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_ONE;
+				CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET;
+				if(ByteCount > 4) {
+					SwitchFlag = 1;
+				}
+				break;
+			case XQSPIPS_SIZE_TWO:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_TWO;
+				CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET;
+				if(ByteCount > 4) {
+					SwitchFlag = 1;
+				}
+				break;
+			case XQSPIPS_SIZE_THREE:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_THREE;
+				CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
+				if(ByteCount > 4) {
+					SwitchFlag = 1;
+				}
+				break;
+			default:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_FOUR;
+				CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET;
+				break;
+		}
+	}
+
+	/*
+	 * If the instruction size in not 4 bytes then the data received needs
+	 * to be shifted
+	 */
+	if( CurrInst->InstSize != 4 ) {
+		InstancePtr->ShiftReadData = 1;
+	} else {
+		InstancePtr->ShiftReadData = 0;
+	}
+	TransCount = 0;
+	/* Get the complete command (flash inst + address/data) */
+	Data = *((u32 *)InstancePtr->SendBufferPtr);
+	InstancePtr->SendBufferPtr += CurrInst->InstSize;
+	InstancePtr->RemainingBytes -= CurrInst->InstSize;
+	if (InstancePtr->RemainingBytes < 0) {
+		InstancePtr->RemainingBytes = 0;
+	}
+
+	/* Write the command to the FIFO */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+					CurrInst->TxOffset, Data);
+	++TransCount;
+
+	/*
+	 * If switching from TXD1/2/3 to TXD0, then start transfer and
+	 * check for FIFO empty
+	 */
+	if(SwitchFlag == 1) {
+		SwitchFlag = 0;
+		/*
+		 * If, in Manual Start mode, start the transfer.
+		 */
+		if (XQspiPs_IsManualStart(InstancePtr)) {
+			ConfigReg = XQspiPs_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET);
+			ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+			XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET, ConfigReg);
+		}
+		/*
+		 * Wait for the transfer to finish by polling Tx fifo status.
+		 */
+		do {
+			StatusReg = XQspiPs_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					XQSPIPS_SR_OFFSET);
+		} while ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0);
+
+	}
+
+	/*
+	 * Check if manual start is selected and store it in a
+	 * local varibale for reference. This is to avoid reading
+	 * the config register everytime.
+	 */
+	IsManualStart = XQspiPs_IsManualStart(InstancePtr);
+
+	/*
+	 * Fill the DTR/FIFO with as many bytes as it will take (or as
+	 * many as we have to send).
+	 */
+	while ((InstancePtr->RemainingBytes > 0) &&
+		(TransCount < XQSPIPS_FIFO_DEPTH)) {
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				 XQSPIPS_TXD_00_OFFSET,
+				 *((u32 *)InstancePtr->SendBufferPtr));
+		InstancePtr->SendBufferPtr += 4;
+		InstancePtr->RemainingBytes -= 4;
+		if (InstancePtr->RemainingBytes < 0) {
+			InstancePtr->RemainingBytes = 0;
+		}
+		++TransCount;
+	}
+
+	while((InstancePtr->RemainingBytes > 0) ||
+	      (InstancePtr->RequestedBytes > 0)) {
+
+		/*
+		 * Fill the TX FIFO with RX threshold no. of entries (or as
+		 * many as we have to send, in case that's less).
+		 */
+		while ((InstancePtr->RemainingBytes > 0) &&
+			(TransCount < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
+			XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XQSPIPS_TXD_00_OFFSET,
+					 *((u32 *)InstancePtr->SendBufferPtr));
+			InstancePtr->SendBufferPtr += 4;
+			InstancePtr->RemainingBytes -= 4;
+			if (InstancePtr->RemainingBytes < 0) {
+				InstancePtr->RemainingBytes = 0;
+			}
+			++TransCount;
+		}
+
+		/*
+		 * If, in Manual Start mode, start the transfer.
+		 */
+		if (IsManualStart == TRUE) {
+			ConfigReg = XQspiPs_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET);
+			ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+			XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET, ConfigReg);
+		}
+
+		/*
+		 * Reset TransCount - this is only used to fill TX FIFO
+		 * in the above loop;
+		 * RxCount is used to keep track of data received
+		 */
+		TransCount = 0;
+
+		/*
+		 * Wait for RX FIFO to reach threshold (or)
+		 * TX FIFO to become empty.
+		 * The latter check is required for
+		 * small transfers (<32 words) and
+		 * when the last chunk in a large data transfer is < 32 words.
+		 */
+
+		do {
+			StatusReg = XQspiPs_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					XQSPIPS_SR_OFFSET);
+		} while ( ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0) &&
+			((StatusReg & XQSPIPS_IXR_RXNEMPTY_MASK) == 0) );
+
+		/*
+		 * A transmit has just completed. Process received data
+		 * and check for more data to transmit.
+		 * First get the data received as a result of the
+		 * transmit that just completed. Receive data based on the
+		 * count obtained while filling tx fifo. Always get
+		 * the received data, but only fill the receive
+		 * buffer if it points to something (the upper layer
+		 * software may not care to receive data).
+		 */
+		while ((InstancePtr->RequestedBytes > 0) &&
+			(RxCount < XQSPIPS_RXFIFO_THRESHOLD_OPT )) {
+			u32 Data;
+
+			RxCount++;
+
+			if (InstancePtr->RecvBufferPtr != NULL) {
+				if (InstancePtr->RequestedBytes < 4) {
+					Data = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XQSPIPS_RXD_OFFSET);
+					XQspiPs_GetReadData(InstancePtr, Data,
+						InstancePtr->RequestedBytes);
+				} else {
+					(*(u32 *)InstancePtr->RecvBufferPtr) =
+						XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XQSPIPS_RXD_OFFSET);
+					InstancePtr->RecvBufferPtr += 4;
+					InstancePtr->RequestedBytes -= 4;
+					if (InstancePtr->RequestedBytes < 0) {
+						InstancePtr->RequestedBytes = 0;
+					}
+				}
+			} else {
+				Data = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XQSPIPS_RXD_OFFSET);
+				InstancePtr->RequestedBytes -= 4;
+			}
+		}
+		RxCount = 0;
+	}
+
+	/*
+	 * If the Slave select lines are being manually controlled, disable
+	 * them because the transfer is complete.
+	 */
+	if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+		ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XQSPIPS_CR_OFFSET);
+		ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPS_CR_OFFSET, ConfigReg);
+	}
+
+	/*
+	 * Clear the busy flag.
+	 */
+	InstancePtr->IsBusy = FALSE;
+
+	/*
+	 * Disable the device.
+	 */
+	XQspiPs_Disable(InstancePtr);
+
+	/*
+	 * Reset the RX FIFO threshold to one
+	 */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Read the flash in Linear QSPI mode.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	RecvBufPtr is a pointer to a buffer for received data.
+* @param	Address is the starting address within the flash from
+*		from where data needs to be read.
+* @param	ByteCount contains the number of bytes to receive.
+*
+* @return
+*		- XST_SUCCESS if read is performed
+*		- XST_FAILURE if Linear mode is not set
+*
+* @note		None.
+*
+*
+******************************************************************************/
+int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
+			u32 Address, unsigned ByteCount)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(RecvBufPtr != NULL);
+	Xil_AssertNonvoid(ByteCount > 0);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+#ifndef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
+#define	XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
+#endif
+	/*
+	 * Enable the controller
+	 */
+	XQspiPs_Enable(InstancePtr);
+
+	if (XQspiPs_GetLqspiConfigReg(InstancePtr) &
+		XQSPIPS_LQSPI_CR_LINEAR_MASK) {
+		memcpy((void*)RecvBufPtr,
+		      (const void*)(XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR +
+		       Address),
+		      (size_t)ByteCount);
+		return XST_SUCCESS;
+	} else {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Disable the controller
+	 */
+	XQspiPs_Disable(InstancePtr);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Selects the slave with which the master communicates.
+*
+* The user is not allowed to select the slave while a transfer is in progress.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+*		- XST_SUCCESS if the slave is selected or deselected
+*		  successfully.
+*		- XST_DEVICE_BUSY if a transfer is in progress, slave cannot be
+*		  changed.
+*
+* @note
+*
+* This function only sets the slave which will be selected when a transfer
+* occurs. The slave is not selected when the QSPI is idle.
+*
+******************************************************************************/
+int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr)
+{
+	u32 ConfigReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Do not allow the slave select to change while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	/*
+	 * Select the slave
+	 */
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPS_CR_OFFSET);
+	ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XQSPIPS_CR_OFFSET, ConfigReg);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Sets the status callback function, the status handler, which the driver
+* calls when it encounters conditions that should be reported to upper
+* layer software. The handler executes in an interrupt context, so it must
+* minimize the amount of processing performed. One of the following status
+* events is passed to the status handler.
+*
+* <pre>
+*
+* XST_SPI_TRANSFER_DONE		The requested data transfer is done
+*
+* XST_SPI_TRANSMIT_UNDERRUN	As a slave device, the master clocked data
+*				but there were none available in the transmit
+*				register/FIFO. This typically means the slave
+*				application did not issue a transfer request
+*				fast enough, or the processor/driver could not
+*				fill the transmit register/FIFO fast enough.
+*
+* XST_SPI_RECEIVE_OVERRUN	The QSPI device lost data. Data was received
+*				but the receive data register/FIFO was full.
+*
+* </pre>
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+* @param	FuncPtr is the pointer to the callback function.
+*
+* @return	None.
+*
+* @note
+*
+* The handler is called within interrupt context, so it should do its work
+* quickly and queue potentially time-consuming work to a task-level thread.
+*
+******************************************************************************/
+void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
+				XQspiPs_StatusHandler FuncPtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FuncPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->StatusHandler = FuncPtr;
+	InstancePtr->StatusRef = CallBackRef;
+}
+
+/*****************************************************************************/
+/**
+*
+* This is a stub for the status callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param	CallBackRef is a pointer to the upper layer callback reference
+* @param	StatusEvent is the event that just occurred.
+* @param	ByteCount is the number of bytes transferred up until the event
+*		occurred.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
+				unsigned ByteCount)
+{
+	(void) CallBackRef;
+	(void) StatusEvent;
+	(void) ByteCount;
+
+	Xil_AssertVoidAlways();
+}
+
+/*****************************************************************************/
+/**
+*
+* The interrupt handler for QSPI interrupts. This function must be connected
+* by the user to an interrupt controller.
+*
+* The interrupts that are handled are:
+*
+*
+* - Data Transmit Register (FIFO) Empty. This interrupt is generated when the
+*   transmit register or FIFO is empty. The driver uses this interrupt during a
+*   transmission to continually send/receive data until the transfer is done.
+*
+* - Data Transmit Register (FIFO) Underflow. This interrupt is generated when
+*   the QSPI device, when configured as a slave, attempts to read an empty
+*   DTR/FIFO.  An empty DTR/FIFO usually means that software is not giving the
+*   device data in a timely manner. No action is taken by the driver other than
+*   to inform the upper layer software of the error.
+*
+* - Data Receive Register (FIFO) Overflow. This interrupt is generated when the
+*   QSPI device attempts to write a received byte to an already full DRR/FIFO.
+*   A full DRR/FIFO usually means software is not emptying the data in a timely
+*   manner.  No action is taken by the driver other than to inform the upper
+*   layer software of the error.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	None.
+*
+* @note
+*
+* The slave select register is being set to deselect the slave when a transfer
+* is complete.
+*
+******************************************************************************/
+void XQspiPs_InterruptHandler(void *InstancePtr)
+{
+	XQspiPs *QspiPtr = (XQspiPs *)InstancePtr;
+	u32 IntrStatus;
+	u32 ConfigReg;
+	u32 Data;
+	u32 TransCount;
+	u32 Count = 0;
+	unsigned BytesDone; /* Number of bytes done so far. */
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(QspiPtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Immediately clear the interrupts in case the ISR causes another
+	 * interrupt to be generated. If we clear at the end of the ISR,
+	 * we may miss newly generated interrupts. This occurs because we
+	 * transmit from within the ISR, which could potentially cause another
+	 * TX_EMPTY interrupt.
+	 */
+	IntrStatus = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
+				      XQSPIPS_SR_OFFSET);
+	XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_SR_OFFSET,
+			  (IntrStatus & XQSPIPS_IXR_WR_TO_CLR_MASK));
+	XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_IDR_OFFSET,
+			XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXNEMPTY_MASK |
+			XQSPIPS_IXR_RXOVR_MASK | XQSPIPS_IXR_TXUF_MASK);
+
+	if ((IntrStatus & XQSPIPS_IXR_TXOW_MASK) ||
+		(IntrStatus & XQSPIPS_IXR_RXNEMPTY_MASK)) {
+
+		/*
+		 * Rx FIFO has just reached threshold no. of entries.
+		 * Read threshold no. of entries from RX FIFO
+		 * Another possiblity of entering this loop is when
+		 * the last byte has been transmitted and TX FIFO is empty,
+		 * in which case, read all the data from RX FIFO.
+		 * Always get the received data, but only fill the
+		 * receive buffer if it is not null (it can be null when
+		 * the device does not care to receive data).
+		 */
+		TransCount = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
+		if (TransCount % 4) {
+			TransCount = TransCount/4 + 1;
+		} else {
+			TransCount = TransCount/4;
+		}
+
+		while ((Count < TransCount) &&
+			(Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
+
+			if (QspiPtr->RecvBufferPtr != NULL) {
+				if (QspiPtr->RequestedBytes < 4) {
+					Data = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
+						XQSPIPS_RXD_OFFSET);
+					XQspiPs_GetReadData(QspiPtr, Data,
+						QspiPtr->RequestedBytes);
+				} else {
+					(*(u32 *)QspiPtr->RecvBufferPtr) =
+						XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
+						XQSPIPS_RXD_OFFSET);
+					QspiPtr->RecvBufferPtr += 4;
+					QspiPtr->RequestedBytes -= 4;
+					if (QspiPtr->RequestedBytes < 0) {
+						QspiPtr->RequestedBytes = 0;
+					}
+				}
+			} else {
+				XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
+						XQSPIPS_RXD_OFFSET);
+				QspiPtr->RequestedBytes -= 4;
+				if (QspiPtr->RequestedBytes < 0) {
+					QspiPtr->RequestedBytes = 0;
+				}
+
+			}
+			Count++;
+		}
+		Count = 0;
+		/*
+		 * Interrupt asserted as TX_OW got asserted
+		 * See if there is more data to send.
+		 * Fill TX FIFO with RX threshold no. of entries or
+		 * remaining entries (in case that is less than threshold)
+		 */
+		while ((QspiPtr->RemainingBytes > 0) &&
+			(Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
+			/*
+			 * Send more data.
+			 */
+			XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+				XQSPIPS_TXD_00_OFFSET,
+				*((u32 *)QspiPtr->SendBufferPtr));
+			QspiPtr->SendBufferPtr += 4;
+			QspiPtr->RemainingBytes -= 4;
+			if (QspiPtr->RemainingBytes < 0) {
+				QspiPtr->RemainingBytes = 0;
+			}
+
+			Count++;
+		}
+
+		if ((QspiPtr->RemainingBytes == 0) &&
+			(QspiPtr->RequestedBytes == 0)) {
+			/*
+			 * No more data to send.  Disable the interrupt
+			 * and inform the upper layer software that the
+			 * transfer is done. The interrupt will be re-enabled
+			 * when another transfer is initiated.
+			 */
+			XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+					  XQSPIPS_IDR_OFFSET,
+					  XQSPIPS_IXR_RXNEMPTY_MASK |
+					  XQSPIPS_IXR_TXOW_MASK |
+					  XQSPIPS_IXR_RXOVR_MASK |
+					  XQSPIPS_IXR_TXUF_MASK);
+
+			/*
+			 * If the Slave select is being manually controlled,
+			 * disable it because the transfer is complete.
+			 */
+			if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+				ConfigReg = XQspiPs_ReadReg(
+						QspiPtr->Config.BaseAddress,
+						XQSPIPS_CR_OFFSET);
+				ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
+				XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+						  XQSPIPS_CR_OFFSET,
+						   ConfigReg);
+			}
+
+			/*
+			 * Clear the busy flag.
+			 */
+			QspiPtr->IsBusy = FALSE;
+
+			/*
+			 * Disable the device.
+			 */
+			XQspiPs_Disable(QspiPtr);
+
+			/*
+			 * Reset the RX FIFO threshold to one
+			 */
+			XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+				XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+			QspiPtr->StatusHandler(QspiPtr->StatusRef,
+						XST_SPI_TRANSFER_DONE,
+						QspiPtr->RequestedBytes);
+		} else {
+			/*
+			 * Enable the TXOW interrupt.
+			 */
+			XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+					 XQSPIPS_IER_OFFSET,
+					 XQSPIPS_IXR_RXNEMPTY_MASK |
+					 XQSPIPS_IXR_TXOW_MASK |
+					 XQSPIPS_IXR_RXOVR_MASK |
+					 XQSPIPS_IXR_TXUF_MASK);
+			/*
+			 * If, in Manual Start mode, start the transfer.
+			 */
+			if (XQspiPs_IsManualStart(QspiPtr)) {
+				ConfigReg = XQspiPs_ReadReg(
+					QspiPtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET);
+				ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+				XQspiPs_WriteReg(
+					QspiPtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET, ConfigReg);
+			}
+		}
+	}
+
+	/*
+	 * Check for overflow and underflow errors.
+	 */
+	if (IntrStatus & XQSPIPS_IXR_RXOVR_MASK) {
+		BytesDone = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
+		QspiPtr->IsBusy = FALSE;
+
+		/*
+		 * If the Slave select lines is being manually controlled,
+		 * disable it because the transfer is complete.
+		 */
+		if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+			ConfigReg = XQspiPs_ReadReg(
+					QspiPtr->Config.BaseAddress,
+					XQSPIPS_CR_OFFSET);
+			ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
+			XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+				XQSPIPS_CR_OFFSET, ConfigReg);
+		}
+
+		/*
+		 * Disable the device.
+		 */
+		XQspiPs_Disable(QspiPtr);
+
+		/*
+		 * Reset the RX FIFO threshold to one
+		 */
+		XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+			XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+		QspiPtr->StatusHandler(QspiPtr->StatusRef,
+			XST_SPI_RECEIVE_OVERRUN, BytesDone);
+	}
+
+	if (IntrStatus & XQSPIPS_IXR_TXUF_MASK) {
+		BytesDone = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
+
+		QspiPtr->IsBusy = FALSE;
+		/*
+		 * If the Slave select lines is being manually controlled,
+		 * disable it because the transfer is complete.
+		 */
+		if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+			ConfigReg = XQspiPs_ReadReg(
+					QspiPtr->Config.BaseAddress,
+					XQSPIPS_CR_OFFSET);
+			ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
+			XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+					  XQSPIPS_CR_OFFSET, ConfigReg);
+		}
+
+		/*
+		 * Disable the device.
+		 */
+		XQspiPs_Disable(QspiPtr);
+
+		/*
+		 * Reset the RX FIFO threshold to one
+		 */
+		XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+			XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+		QspiPtr->StatusHandler(QspiPtr->StatusRef,
+				      XST_SPI_TRANSMIT_UNDERRUN, BytesDone);
+	}
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Copies data from Data to the Receive buffer.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	Data is the data which needs to be copied to the Rx buffer.
+* @param	Size is the number of bytes to be copied to the Receive buffer.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void XQspiPs_GetReadData(XQspiPs *InstancePtr, u32 Data, u8 Size)
+{
+	u8 DataByte3;
+
+	if (InstancePtr->RecvBufferPtr) {
+		switch (Size) {
+		case 1:
+			if (InstancePtr->ShiftReadData == 1) {
+				*((u8 *)InstancePtr->RecvBufferPtr) =
+					((Data & 0xFF000000) >> 24);
+			} else {
+				*((u8 *)InstancePtr->RecvBufferPtr) =
+					(Data & 0xFF);
+			}
+			InstancePtr->RecvBufferPtr += 1;
+			break;
+		case 2:
+			if (InstancePtr->ShiftReadData == 1) {
+				*((u16 *)InstancePtr->RecvBufferPtr) =
+					((Data & 0xFFFF0000) >> 16);
+			} else 	{
+				*((u16 *)InstancePtr->RecvBufferPtr) =
+					(Data & 0xFFFF);
+			}
+			InstancePtr->RecvBufferPtr += 2;
+			break;
+		case 3:
+			if (InstancePtr->ShiftReadData == 1) {
+				*((u16 *)InstancePtr->RecvBufferPtr) =
+					((Data & 0x00FFFF00) >> 8);
+				InstancePtr->RecvBufferPtr += 2;
+				DataByte3 = ((Data & 0xFF000000) >> 24);
+				*((u8 *)InstancePtr->RecvBufferPtr) = DataByte3;
+			} else {
+				*((u16 *)InstancePtr->RecvBufferPtr) =
+					(Data & 0xFFFF);
+				InstancePtr->RecvBufferPtr += 2;
+				DataByte3 = ((Data & 0x00FF0000) >> 16);
+				*((u8 *)InstancePtr->RecvBufferPtr) = DataByte3;
+			}
+			InstancePtr->RecvBufferPtr += 1;
+			break;
+		default:
+			/* This will never execute */
+			break;
+		}
+	}
+	InstancePtr->ShiftReadData  = 0;
+	InstancePtr->RequestedBytes -= Size;
+	if (InstancePtr->RequestedBytes < 0) {
+		InstancePtr->RequestedBytes = 0;
+	}
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips.h
new file mode 100644
index 0000000000000000000000000000000000000000..671f3f636e7a1031268756757e9bfa538d547e85
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips.h
@@ -0,0 +1,793 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips.h
+* @addtogroup qspips_v3_2
+* @{
+* @details
+*
+* This file contains the implementation of the XQspiPs driver. It supports only
+* master mode. User documentation for the driver functions is contained in this
+* file in the form of comment blocks at the front of each function.
+*
+* A QSPI device connects to an QSPI bus through a 4-wire serial interface.
+* The QSPI bus is a full-duplex, synchronous bus that facilitates communication
+* between one master and one slave. The device is always full-duplex,
+* which means that for every byte sent, one is received, and vice-versa.
+* The master controls the clock, so it can regulate when it wants to
+* send or receive data. The slave is under control of the master, it must
+* respond quickly since it has no control of the clock and must send/receive
+* data as fast or as slow as the master does.
+*
+* <b> Linear Mode </b>
+* The Linear Quad-SPI Controller extends the existing Quad-SPI Controller�s
+* functionality by adding a linear addressing scheme that allows the SPI flash
+* memory subsystem to behave like a typical ROM device.  The new feature hides
+* the normal SPI protocol from a master reading from the SPI flash memory. The
+* feature improves both the user friendliness and the overall read memory
+* throughput over that of the current Quad-SPI Controller by lessening the
+* amount of software overheads required and by the use of the faster AXI
+* interface.
+*
+* <b>Initialization & Configuration</b>
+*
+* The XQspiPs_Config structure is used by the driver to configure itself. This
+* configuration structure is typically created by the tool-chain based on HW
+* build properties.
+*
+* To support multiple runtime loading and initialization strategies employed by
+* various operating systems, the driver instance can be initialized in the
+* following way:
+*	- XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find
+*	  static configuration structure defined in xqspips_g.c. This is setup
+*	  by the tools. For some operating systems the config structure will be
+*	  initialized by the software and this call is not needed.
+*	- XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+*	  configuration structure provided by the caller. If running in a system
+*	  with address translation, the provided virtual memory base address
+*	  replaces the physical address present in the configuration structure.
+*
+* <b>Multiple Masters</b>
+*
+* More than one master can exist, but arbitration is the responsibility of
+* the higher layer software. The device driver does not perform any type of
+* arbitration.
+*
+* <b>Modes of Operation</b>
+*
+* There are four modes to perform a data transfer and the selection of a mode
+* is based on Chip Select(CS) and Start. These two options individually, can
+* be controlled either by software(Manual) or hardware(Auto).
+* - Auto CS: Chip select is automatically asserted as soon as the first word
+*	     is written into the TXFIFO and de asserted when the TXFIFO becomes
+*	     empty
+* - Manual CS: Software must assert and de assert CS.
+* - Auto Start: Data transmission starts as soon as there is data in the
+*		TXFIFO and stalls when the TXFIFO is empty
+* - Manual Start: Software must start data transmission at the beginning of
+*		  the transaction or whenever the TXFIFO has become empty
+*
+* The preferred combination is Manual CS and Auto Start.
+* In this combination, the software asserts CS before loading any data into
+* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it
+* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the
+* data is available. If no further data, software disables CS.
+*
+* Risks/challenges of other combinations:
+* - Manual CS and Manual Start: Manual Start bit should be set after each
+*   TXFIFO write otherwise there could be a race condition where the TXFIFO
+*   becomes empty before the new word is written. In that case the
+*   transmission stops.
+* - Auto CS with Manual or Auto Start: It is very difficult for software to
+*   keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted.
+*   This results in a single transaction to be split into multiple pieces each
+*   with its own chip select. This will result in garbage data to be sent.
+*
+* <b>Interrupts</b>
+*
+* The user must connect the interrupt handler of the driver,
+* XQspiPs_InterruptHandler, to an interrupt system such that it will be
+* called when an interrupt occurs. This function does not save and restore
+* the processor context such that the user must provide this processing.
+*
+* The driver handles the following interrupts:
+* - Data Transmit Register/FIFO Underflow
+* - Data Receive Register/FIFO Not Empty
+* - Data Transmit Register/FIFO Overwater
+* - Data Receive Register/FIFO Overrun
+*
+* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the
+* QSPI device has transmitted the data available to transmit, and now its data
+* register and FIFO is ready to accept more data. The driver uses this
+* interrupt to indicate progress while sending data.  The driver may have
+* more data to send, in which case the data transmit register and FIFO is
+* filled for subsequent transmission. When this interrupt arrives and all
+* the data has been sent, the driver invokes the status callback with a
+* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that
+* all data has been sent.
+*
+* The Data Transmit Register/FIFO Underflow interrupt -- indicates that,
+* as slave, the QSPI device was required to transmit but there was no data
+* available to transmit in the transmit register (or FIFO). This may not
+* be an error if the master is not expecting data. But in the case where
+* the master is expecting data, this serves as a notification of such a
+* condition. The driver reports this condition to the upper layer
+* software through the status handler.
+*
+* The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI
+* device received data and subsequently dropped the data because the data
+* receive register and FIFO was full. The driver reports this condition to the
+* upper layer software through the status handler. This likely indicates a
+* problem with the higher layer protocol, or a problem with the slave
+* performance.
+*
+*
+* <b>Polled Operation</b>
+*
+* Transfer in polled mode is supported through a separate interface function
+* XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode,
+* this function blocks until all data has been sent/received.
+*
+* <b>Device Busy</b>
+*
+* Some operations are disallowed when the device is busy. The driver tracks
+* whether a device is busy. The device is considered busy when a data transfer
+* request is outstanding, and is considered not busy only when that transfer
+* completes (or is aborted with a mode fault error).
+*
+* <b>Device Configuration</b>
+*
+* The device can be configured in various ways during the FPGA implementation
+* process. Configuration parameters are stored in the xqspips_g.c file or
+* passed in via XQspiPs_CfgInitialize(). A table is defined where each entry
+* contains configuration information for an QSPI device, including the base
+* address for the device.
+*
+* <b>RTOS Independence</b>
+*
+* This driver is intended to be RTOS and processor independent.  It works with
+* physical addresses only.  Any needs for dynamic memory management, threads or
+* thread mutual exclusion, virtual memory, or cache control must be satisfied
+* by the layer above this driver.
+*
+* NOTE: This driver was always tested with endianess set to little-endian.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a sdm 11/25/10 First release, based on the PS SPI driver...
+* 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters
+*		     in xparameters.h
+* 2.00a kka 07/25/12 Added a few register defines for CR 670297
+* 		     Removed code related to mode fault for CR 671468
+*		     The XQspiPs_SetSlaveSelect has been modified to remove
+*		     the argument of the slave select as the QSPI controller
+*		     only supports one slave.
+* 		     XQspiPs_GetSlaveSelect API has been removed
+* 		     Added a flag ShiftReadData to the instance structure
+*.		     and is used in the XQspiPs_GetReadData API.
+*		     The ShiftReadData Flag indicates whether the data
+*		     read from the Rx FIFO needs to be shifted
+*		     in cases where the data is less than 4  bytes
+* 		     Removed the selection for the following options:
+*		     Master mode (XQSPIPS_MASTER_OPTION) and
+*		     Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
+*		     as the QSPI driver supports the Master mode
+*		     and Flash Interface mode and doesnot support
+*		     Slave mode or the legacy mode.
+*		     Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
+*		     APIs so that the last argument (IsInst) specifying whether
+*		     it is instruction or data has been removed. The first byte
+*		     in the SendBufPtr argument of these APIs specify the
+*		     instruction to be sent to the Flash Device.
+*		     This version of the driver fixes CRs 670197/663787/
+*		     670297/671468.
+* 		     Added the option for setting the Holdb_dr bit in the
+*		     configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
+*		     is the option to be used for setting this bit in the
+*		     configuration register.
+*		     The XQspiPs_PolledTransfer function has been updated
+*		     to fill the data to fifo depth.
+* 2.01a sg  02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
+*		     Added macros for Set/Get Rx Watermark. Changed QSPI
+*		     Enable/Disable macro argument from BaseAddress to
+*		     Instance Pointer. Added DelayNss argument to SetDelays
+*		     and GetDelays API's.
+*		     Created macros XQspiPs_IsManualStart and
+*		     XQspiPs_IsManualChipSelect.
+*		     Changed QSPI transfer logic for polled and interrupt
+*		     modes to be based on filled tx fifo count and receive
+*		     based on it. RXNEMPTY interrupt is not used.
+*		     Added assertions to XQspiPs_LqspiRead function.
+*		     SetDelays and GetDelays API's include DelayNss parameter.
+*		     Added defines for DelayNss,Rx Watermark,Interrupts
+*		     which need write to clear. Removed Read zeros mask from
+*		     LQSPI Config register. Renamed Fixed burst error to
+*		     data FSM error in  LQSPI Status register.
+*
+* 2.02a hk  05/07/13 Added ConnectionMode to config structure.
+*			 Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel
+*			 Added enable and disable to the XQspiPs_LqspiRead() function
+*			 Removed XQspi_Reset() in Set_Options() function when
+*			 LQSPI_MODE_OPTION is set.
+*            Added instructions for bank selection, die erase and
+*            flag status register to the flash instruction table
+*            Handling for instructions not in flash instruction
+*			 table added. Checking for Tx FIFO empty when switching from
+*			 TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
+*            byte count 3 (spansion), instruction size and TXD register
+*			 changed accordingly. CR# 712502 and 703869.
+*            Added prefix to constant definitions for ConnectionMode
+*            Added (#ifdef linear base address) in the Linear read function.
+*            Changed  XPAR_XQSPIPS_0_LINEAR_BASEADDR to
+*            XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
+*            XQspiPs_LqspiRead function. Fix for CR#718141.
+*
+* 2.03a hk  09/17/13 Modified polled and interrupt transfers to make use of
+*                    thresholds. This is to improve performance.
+*                    Added API's for QSPI reset and
+*                    linear mode initialization for boot.
+*                    Added RX and TX threshold reset to one in XQspiPs_Abort.
+*                    Added RX threshold reset(1) after transfer in polled and
+*                    interrupt transfers. Made changes to make sure threshold
+*                    change is done only when no transfer is in progress.
+*                    Updated linear init API for parallel and stacked modes.
+*                    CR#737760.
+* 3.1   hk  08/13/14 When writing to the configuration register, set/reset
+*                    required bits leaving reserved bits untouched. CR# 796813.
+* 3.2	sk	02/05/15 Add SLCR reset in abort function as a workaround because
+* 					 controller does not update FIFO status flags as expected
+* 					 when thresholds are used.
+* 3.3   sk  11/07/15 Modified the API prototypes according to MISRAC standards
+*                    to remove compilation warnings. CR# 868893.
+*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+*                    generation.
+*
+* </pre>
+*
+******************************************************************************/
+#ifndef XQSPIPS_H		/* prevent circular inclusions */
+#define XQSPIPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xqspips_hw.h"
+#include <string.h>
+
+/************************** Constant Definitions *****************************/
+
+/** @name Configuration options
+ *
+ * The following options are supported to enable/disable certain features of
+ * an QSPI device.  Each of the options is a bit mask, so more than one may be
+ * specified.
+ *
+ *
+ * The <b>Active Low Clock option</b> configures the device's clock polarity.
+ * Setting this option means the clock is active low and the SCK signal idles
+ * high. By default, the clock is active high and SCK idles low.
+ *
+ * The <b>Clock Phase option</b> configures the QSPI device for one of two
+ * transfer formats.  A clock phase of 0, the default, means data is valid on
+ * the first SCK edge (rising or falling) after the slave select (SS) signal
+ * has been asserted. A clock phase of 1 means data is valid on the second SCK
+ * edge (rising or falling) after SS has been asserted.
+ *
+ *
+ * The <b>QSPI Force Slave Select option</b> is used to enable manual control of
+ * the slave select signal.
+ * 0: The SPI_SS signal is controlled by the QSPI controller during
+ * transfers. (Default)
+ * 1: The SPI_SS signal is forced active (driven low) regardless of any
+ * transfers in progress.
+ *
+ * NOTE: The driver will handle setting and clearing the Slave Select when
+ * the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the
+ * QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the
+ * processor cannot empty and refill the FIFOs before the TX FIFO is empty
+ * When the QSPI hardware is controlling the Slave Select signals, this
+ * will cause slave to be de-selected and terminate the transfer.
+ *
+ * The <b>Manual Start option</b> is used to enable manual control of
+ * the Start command to perform data transfer.
+ * 0: The Start command is controlled by the QSPI controller during
+ * transfers(Default). Data transmission starts as soon as there is data in
+ * the TXFIFO and stalls when the TXFIFO is empty
+ * 1: The Start command must be issued by software to perform data transfer.
+ * Bit 15 of Configuration register is used to issue Start command. This bit
+ * must be set whenever TXFIFO is filled with new data.
+ *
+ * NOTE: The driver will set the Manual Start Enable bit in Configuration
+ * Register, if Manual Start option is selected. Software will issue
+ * Manual Start command whenever TXFIFO is filled with data. When there is
+ * no further data, driver will clear the Manual Start Enable bit.
+ *
+ * @{
+ */
+#define XQSPIPS_CLK_ACTIVE_LOW_OPTION	0x2  /**< Active Low Clock option */
+#define XQSPIPS_CLK_PHASE_1_OPTION	0x4  /**< Clock Phase one option */
+#define XQSPIPS_FORCE_SSELECT_OPTION	0x10 /**< Force Slave Select */
+#define XQSPIPS_MANUAL_START_OPTION	0x20 /**< Manual Start enable */
+#define XQSPIPS_LQSPI_MODE_OPTION	0x80 /**< Linear QPSI mode */
+#define XQSPIPS_HOLD_B_DRIVE_OPTION	0x100 /**< Drive HOLD_B Pin */
+/*@}*/
+
+
+/** @name QSPI Clock Prescaler options
+ * The QSPI Clock Prescaler Configuration bits are used to program master mode
+ * bit rate. The bit rate can be programmed in divide-by-two decrements from
+ * pclk/2 to pclk/256.
+ *
+ * @{
+ */
+#define XQSPIPS_CLK_PRESCALE_2		0x00 /**< PCLK/2 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_4		0x01 /**< PCLK/4 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_8		0x02 /**< PCLK/8 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_16		0x03 /**< PCLK/16 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_32		0x04 /**< PCLK/32 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_64		0x05 /**< PCLK/64 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_128	0x06 /**< PCLK/128 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_256	0x07 /**< PCLK/256 Prescaler */
+
+/*@}*/
+
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that are passed to
+ * a handler from the driver.  These constants are not bit masks such that
+ * only one will be passed at a time to the handler.
+ *
+ * @{
+ */
+#define XQSPIPS_EVENT_TRANSFER_DONE	2 /**< Transfer done */
+#define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */
+#define XQSPIPS_EVENT_RECEIVE_OVERRUN	4 /**< Receive data loss because
+						RX FIFO full */
+/*@}*/
+
+/** @name Flash commands
+ *
+ * The following constants define most of the commands supported by flash
+ * devices. Users can add more commands supported by the flash devices
+ *
+ * @{
+ */
+#define	XQSPIPS_FLASH_OPCODE_WRSR	0x01 /* Write status register */
+#define	XQSPIPS_FLASH_OPCODE_PP		0x02 /* Page program */
+#define	XQSPIPS_FLASH_OPCODE_NORM_READ	0x03 /* Normal read data bytes */
+#define	XQSPIPS_FLASH_OPCODE_WRDS	0x04 /* Write disable */
+#define	XQSPIPS_FLASH_OPCODE_RDSR1	0x05 /* Read status register 1 */
+#define	XQSPIPS_FLASH_OPCODE_WREN	0x06 /* Write enable */
+#define	XQSPIPS_FLASH_OPCODE_FAST_READ	0x0B /* Fast read data bytes */
+#define	XQSPIPS_FLASH_OPCODE_BE_4K	0x20 /* Erase 4KiB block */
+#define	XQSPIPS_FLASH_OPCODE_RDSR2	0x35 /* Read status register 2 */
+#define	XQSPIPS_FLASH_OPCODE_DUAL_READ	0x3B /* Dual read data bytes */
+#define	XQSPIPS_FLASH_OPCODE_BE_32K	0x52 /* Erase 32KiB block */
+#define	XQSPIPS_FLASH_OPCODE_QUAD_READ	0x6B /* Quad read data bytes */
+#define	XQSPIPS_FLASH_OPCODE_ERASE_SUS	0x75 /* Erase suspend */
+#define	XQSPIPS_FLASH_OPCODE_ERASE_RES	0x7A /* Erase resume */
+#define	XQSPIPS_FLASH_OPCODE_RDID	0x9F /* Read JEDEC ID */
+#define	XQSPIPS_FLASH_OPCODE_BE		0xC7 /* Erase whole flash block */
+#define	XQSPIPS_FLASH_OPCODE_SE		0xD8 /* Sector erase (usually 64KB)*/
+#define XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */
+#define XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */
+#define XQSPIPS_FLASH_OPCODE_BRWR	0x17 /* Bank Register Write */
+#define XQSPIPS_FLASH_OPCODE_BRRD	0x16 /* Bank Register Read */
+/* Extende Address Register Write - Micron's equivalent of Bank Register */
+#define XQSPIPS_FLASH_OPCODE_EARWR	0xC5
+/* Extende Address Register Read - Micron's equivalent of Bank Register */
+#define XQSPIPS_FLASH_OPCODE_EARRD	0xC8
+#define XQSPIPS_FLASH_OPCODE_DIE_ERASE	0xC4
+#define XQSPIPS_FLASH_OPCODE_READ_FLAG_SR	0x70
+#define XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR	0x50
+#define XQSPIPS_FLASH_OPCODE_READ_LOCK_REG	0xE8	/* Lock register Read */
+#define XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG	0xE5	/* Lock Register Write */
+
+/*@}*/
+
+/** @name Instruction size
+ *
+ * The following constants define numbers 1 to 4.
+ * Used to identify whether TXD0,1,2 or 3 is to be used.
+ *
+ * @{
+ */
+#define XQSPIPS_SIZE_ONE 	1
+#define XQSPIPS_SIZE_TWO 	2
+#define XQSPIPS_SIZE_THREE 	3
+#define XQSPIPS_SIZE_FOUR 	4
+
+/*@}*/
+
+/** @name ConnectionMode
+ *
+ * The following constants are the possible values of ConnectionMode in
+ * Config structure.
+ *
+ * @{
+ */
+#define XQSPIPS_CONNECTION_MODE_SINGLE		0
+#define XQSPIPS_CONNECTION_MODE_STACKED		1
+#define XQSPIPS_CONNECTION_MODE_PARALLEL	2
+
+/*@}*/
+
+/** @name FIFO threshold value
+ *
+ * This is the Rx FIFO threshold (in words) that was found to be most
+ * optimal in terms of performance
+ *
+ * @{
+ */
+#define XQSPIPS_RXFIFO_THRESHOLD_OPT		32
+
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+/**
+ * The handler data type allows the user to define a callback function to
+ * handle the asynchronous processing for the QSPI device.  The application
+ * using this driver is expected to define a handler of this type to support
+ * interrupt driven mode.  The handler executes in an interrupt context, so
+ * only minimal processing should be performed.
+ *
+ * @param	CallBackRef is the callback reference passed in by the upper
+ *		layer when setting the callback functions, and passed back to
+ *		the upper layer when the callback is invoked. Its type is
+ *		not important to the driver, so it is a void pointer.
+ * @param 	StatusEvent holds one or more status events that have occurred.
+ *		See the XQspiPs_SetStatusHandler() for details on the status
+ *		events that can be passed in the callback.
+ * @param	ByteCount indicates how many bytes of data were successfully
+ *		transferred.  This may be less than the number of bytes
+ *		requested if the status event indicates an error.
+ */
+typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
+					unsigned ByteCount);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID  of device */
+	u32 BaseAddress;	/**< Base address of the device */
+	u32 InputClockHz;	/**< Input clock frequency */
+	u8  ConnectionMode; /**< Single, Stacked and Parallel mode */
+} XQspiPs_Config;
+
+/**
+ * The XQspiPs driver instance data. The user is required to allocate a
+ * variable of this type for every QSPI device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XQspiPs_Config Config;	 /**< Configuration structure */
+	u32 IsReady;		 /**< Device is initialized and ready */
+
+	u8 *SendBufferPtr;	 /**< Buffer to send (state) */
+	u8 *RecvBufferPtr;	 /**< Buffer to receive (state) */
+	int RequestedBytes;	 /**< Number of bytes to transfer (state) */
+	int RemainingBytes;	 /**< Number of bytes left to transfer(state) */
+	u32 IsBusy;		 /**< A transfer is in progress (state) */
+	XQspiPs_StatusHandler StatusHandler;
+	void *StatusRef;  	 /**< Callback reference for status handler */
+	u32 ShiftReadData;	 /**<  Flag to indicate whether the data
+				   *   read from the Rx FIFO needs to be shifted
+				   *   in cases where the data is less than 4
+				   *   bytes
+				   */
+} XQspiPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/*
+*
+* Check in OptionsTable if Manual Start Option is enabled or disabled.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+*		- TRUE if option is set
+*		- FALSE if option is not set
+*
+* @note		C-Style signature:
+*		u8 XQspiPs_IsManualStart(XQspiPs *InstancePtr);
+*
+*****************************************************************************/
+#define XQspiPs_IsManualStart(InstancePtr) \
+	((XQspiPs_GetOptions(InstancePtr) & \
+	  XQSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE)
+
+/****************************************************************************/
+/*
+*
+* Check in OptionsTable if Manual Chip Select Option is enabled or disabled.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+*
+* @return
+*		- TRUE if option is set
+*		- FALSE if option is not set
+*
+* @note		C-Style signature:
+*		u8 XQspiPs_IsManualChipSelect(XQspiPs *InstancePtr);
+*
+*****************************************************************************/
+#define XQspiPs_IsManualChipSelect(InstancePtr) \
+	((XQspiPs_GetOptions(InstancePtr) & \
+	  XQSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the slave idle count register.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	RegisterValue is the value to be written, valid values are
+*		0-255.
+*
+* @return	None
+*
+* @note
+* C-Style signature:
+*	void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr, u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue)	\
+	XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + 	\
+			XQSPIPS_SICR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the slave idle count register. Use the XQSPIPS_SICR_*
+* constants defined in xqspips_hw.h to interpret the bit-mask returned.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	An 8-bit value representing Slave Idle Count.
+*
+* @note		C-Style signature:
+*		u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetSlaveIdle(InstancePtr)				\
+	XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + 		\
+	XQSPIPS_SICR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the transmit FIFO watermark register.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	RegisterValue is the value to be written, valid values are 1-63.
+*
+* @return	None.
+*
+* @note
+* C-Style signature:
+*	void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr, u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue)		\
+	XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + 		\
+			XQSPIPS_TXWR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the transmit FIFO watermark register.
+* Valid values are in the range 1-63.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	A 6-bit value representing Tx Watermark level.
+*
+* @note		C-Style signature:
+*		u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetTXWatermark(InstancePtr)				\
+	XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the receive FIFO watermark register.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	RegisterValue is the value to be written, valid values are 1-63.
+*
+* @return	None.
+*
+* @note
+* C-Style signature:
+*	void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr, u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue)		\
+	XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + 		\
+			XQSPIPS_RXWR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the receive FIFO watermark register.
+* Valid values are in the range 1-63.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	A 6-bit value representing Rx Watermark level.
+*
+* @note		C-Style signature:
+*		u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetRXWatermark(InstancePtr)				\
+	XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Enable the device and uninhibit master transactions.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XQspiPs_Enable(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_Enable(InstancePtr)					\
+	XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \
+			XQSPIPS_ER_ENABLE_MASK)
+
+/****************************************************************************/
+/**
+*
+* Disable the device.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XQspiPs_Disable(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_Disable(InstancePtr)					\
+	XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the Linear QSPI Configuration register.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	RegisterValue is the value to be written to the Linear QSPI
+*		configuration register.
+*
+* @return	None.
+*
+* @note
+* C-Style signature:
+*	void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr,
+*					u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue)		\
+	XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) +		\
+			XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the Linear QSPI Configuration register.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	A 32-bit value representing the contents of the LQSPI Config
+*		register.
+*
+* @note		C-Style signature:
+*		u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetLqspiConfigReg(InstancePtr)				\
+	XQspiPs_In32((InstancePtr->Config.BaseAddress) +		\
+			XQSPIPS_LQSPI_CR_OFFSET)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization function, implemented in xqspips_sinit.c
+ */
+XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Functions implemented in xqspips.c
+ */
+int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config * Config,
+			   u32 EffectiveAddr);
+void XQspiPs_Reset(XQspiPs *InstancePtr);
+void XQspiPs_Abort(XQspiPs *InstancePtr);
+
+s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
+		      u32 ByteCount);
+s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
+			    u8 *RecvBufPtr, u32 ByteCount);
+int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
+			u32 Address, unsigned ByteCount);
+
+int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr);
+
+void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
+				XQspiPs_StatusHandler FuncPtr);
+void XQspiPs_InterruptHandler(void *InstancePtr);
+
+/*
+ * Functions for selftest, in xqspips_selftest.c
+ */
+int XQspiPs_SelfTest(XQspiPs *InstancePtr);
+
+/*
+ * Functions for options, in xqspips_options.c
+ */
+s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options);
+u32 XQspiPs_GetOptions(XQspiPs *InstancePtr);
+
+s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler);
+u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr);
+
+int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
+			 u8 DelayAfter, u8 DelayInit);
+void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
+			 u8 *DelayAfter, u8 *DelayInit);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_g.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..6723db11fe96b752f578f4ff6c23ef3cfb2645c3
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_g.c
@@ -0,0 +1,57 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xqspips.h"
+
+/*
+* The configuration table for devices
+*/
+
+XQspiPs_Config XQspiPs_ConfigTable[XPAR_XQSPIPS_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_QSPI_0_DEVICE_ID,
+		XPAR_PS7_QSPI_0_BASEADDR,
+		XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ,
+		XPAR_PS7_QSPI_0_QSPI_MODE
+	}
+};
+
+
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_hw.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_hw.c
new file mode 100644
index 0000000000000000000000000000000000000000..47cf6d4c9b370e689e0a00e2bdf3dc1a359b1c91
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_hw.c
@@ -0,0 +1,224 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_hw.c
+* @addtogroup qspips_v3_2
+* @{
+*
+* Contains low level functions, primarily reset related.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 2.03a hk  09/17/13 First release
+* 3.1   hk  06/19/14 When writing to the configuration register, set/reset
+*                    required bits leaving reserved bits untouched. CR# 796813.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspips_hw.h"
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Pre-scaler value for divided by 4
+ *
+ * Pre-scaler value for divided by 4
+ *
+ * @{
+ */
+#define XQSPIPS_CR_PRESC_DIV_BY_4	0x01
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Resets QSPI by disabling the device and bringing it to reset state through
+* register writes.
+*
+* @param	None
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XQspiPs_ResetHw(u32 BaseAddress)
+{
+	u32 ConfigReg;
+
+	/*
+	 * Disable interrupts
+	 */
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_IDR_OFFSET,
+				XQSPIPS_IXR_DISABLE_ALL);
+
+	/*
+	 * Disable device
+	 */
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
+				0);
+
+	/*
+	 * De-assert slave select lines.
+	 */
+	ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
+	ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK);
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
+
+	/*
+	 * Write default value to RX and TX threshold registers
+	 * RX threshold should be set to 1 here because the corresponding
+	 * status bit is used next to clear the RXFIFO
+	 */
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_TXWR_OFFSET,
+			(XQSPIPS_TXWR_RESET_VALUE & XQSPIPS_TXWR_MASK));
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_RXWR_OFFSET,
+			(XQSPIPS_RXWR_RESET_VALUE & XQSPIPS_RXWR_MASK));
+
+	/*
+	 * Clear RXFIFO
+	 */
+	while ((XQspiPs_ReadReg(BaseAddress,XQSPIPS_SR_OFFSET) &
+		XQSPIPS_IXR_RXNEMPTY_MASK) != 0) {
+		XQspiPs_ReadReg(BaseAddress, XQSPIPS_RXD_OFFSET);
+	}
+
+	/*
+	 * Clear status register by reading register and
+	 * writing 1 to clear the write to clear bits
+	 */
+	XQspiPs_ReadReg(BaseAddress, XQSPIPS_SR_OFFSET);
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_SR_OFFSET,
+				XQSPIPS_IXR_WR_TO_CLR_MASK);
+
+	/*
+	 * Write default value to configuration register
+	 */
+	ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
+	ConfigReg |= XQSPIPS_CR_RESET_MASK_SET;
+	ConfigReg &= ~XQSPIPS_CR_RESET_MASK_CLR;
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
+
+	/*
+	 * De-select linear mode
+	 */
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
+				0x0);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Initializes QSPI to Linear mode with default QSPI boot settings.
+*
+* @param	None
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XQspiPs_LinearInit(u32 BaseAddress)
+{
+	u32 BaudRateDiv;
+	u32 LinearCfg;
+	u32 ConfigReg;
+
+	/*
+	 * Baud rate divisor for dividing by 4. Value of CR bits [5:3]
+	 * should be set to 0x001; hence shift the value and use the mask.
+	 */
+	BaudRateDiv = ( (XQSPIPS_CR_PRESC_DIV_BY_4) <<
+			XQSPIPS_CR_PRESC_SHIFT) & XQSPIPS_CR_PRESC_MASK;
+	/*
+	 * Write configuration register with default values, slave selected &
+	 * pre-scaler value for divide by 4
+	 */
+	ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
+	ConfigReg |= (XQSPIPS_CR_RESET_MASK_SET | BaudRateDiv);
+	ConfigReg &= ~(XQSPIPS_CR_RESET_MASK_CLR | XQSPIPS_CR_SSCTRL_MASK);
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
+
+	/*
+	 * Write linear configuration register with default value -
+	 * enable linear mode and use fast read.
+	 */
+
+	if(XPAR_XQSPIPS_0_QSPI_MODE == XQSPIPS_CONNECTION_MODE_SINGLE){
+
+		LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE;
+
+	}else if(XPAR_XQSPIPS_0_QSPI_MODE ==
+			XQSPIPS_CONNECTION_MODE_STACKED){
+
+		LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
+				XQSPIPS_LQSPI_CR_TWO_MEM_MASK;
+
+	}else if(XPAR_XQSPIPS_0_QSPI_MODE ==
+			XQSPIPS_CONNECTION_MODE_PARALLEL){
+
+		LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
+				XQSPIPS_LQSPI_CR_TWO_MEM_MASK |
+				XQSPIPS_LQSPI_CR_SEP_BUS_MASK;
+
+	}
+
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
+				LinearCfg);
+
+	/*
+	 * Enable device
+	 */
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
+				XQSPIPS_ER_ENABLE_MASK);
+
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..404afed94f5afd468b74b5ea3e1ffa994357edab
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_hw.h
@@ -0,0 +1,423 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_hw.h
+* @addtogroup qspips_v3_2
+* @{
+*
+* This header file contains the identifiers and basic HW access driver
+* functions (or  macros) that can be used to access the device. Other driver
+* functions are defined in xqspips.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00  sdm 11/25/10 First release
+* 2.00a ka  07/25/12 Added a few register defines for CR 670297
+*		     and removed some defines of reserved fields for
+*		     CR 671468
+*		     Added define XQSPIPS_CR_HOLD_B_MASK for Holdb_dr
+*		     bit in Configuration register.
+* 2.01a sg  02/03/13 Added defines for DelayNss,Rx Watermark,Interrupts
+*		     which need write to clear. Removed Read zeros mask from
+*		     LQSPI Config register.
+* 2.03a hk  08/22/13 Added prototypes of API's for QSPI reset and
+*                    linear mode initialization for boot. Added related
+*                    constant definitions.
+* 3.1   hk  08/13/14 Changed definition of CR reset value masks to set/reset
+*                    required bits leaving reserved bits untouched. CR# 796813.
+* 3.2	sk	02/05/15 Add SLCR reset in abort function as a workaround because
+* 					 controller does not update FIFO status flags as expected
+* 					 when thresholds are used.
+*
+* </pre>
+*
+******************************************************************************/
+#ifndef XQSPIPS_HW_H		/* prevent circular inclusions */
+#define XQSPIPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of an QSPI device.
+ * @{
+ */
+#define XQSPIPS_CR_OFFSET	 	0x00 /**< Configuration Register */
+#define XQSPIPS_SR_OFFSET	 	0x04 /**< Interrupt Status */
+#define XQSPIPS_IER_OFFSET	 	0x08 /**< Interrupt Enable */
+#define XQSPIPS_IDR_OFFSET	 	0x0c /**< Interrupt Disable */
+#define XQSPIPS_IMR_OFFSET	 	0x10 /**< Interrupt Enabled Mask */
+#define XQSPIPS_ER_OFFSET	 	0x14 /**< Enable/Disable Register */
+#define XQSPIPS_DR_OFFSET	 	0x18 /**< Delay Register */
+#define XQSPIPS_TXD_00_OFFSET	 	0x1C /**< Transmit 4-byte inst/data */
+#define XQSPIPS_RXD_OFFSET	 	0x20 /**< Data Receive Register */
+#define XQSPIPS_SICR_OFFSET	 	0x24 /**< Slave Idle Count */
+#define XQSPIPS_TXWR_OFFSET	 	0x28 /**< Transmit FIFO Watermark */
+#define XQSPIPS_RXWR_OFFSET	 	0x2C /**< Receive FIFO Watermark */
+#define XQSPIPS_GPIO_OFFSET	 	0x30 /**< GPIO Register */
+#define XQSPIPS_LPBK_DLY_ADJ_OFFSET	0x38 /**< Loopback Delay Adjust Reg */
+#define XQSPIPS_TXD_01_OFFSET	 	0x80 /**< Transmit 1-byte inst */
+#define XQSPIPS_TXD_10_OFFSET	 	0x84 /**< Transmit 2-byte inst */
+#define XQSPIPS_TXD_11_OFFSET	 	0x88 /**< Transmit 3-byte inst */
+#define XQSPIPS_LQSPI_CR_OFFSET  	0xA0 /**< Linear QSPI config register */
+#define XQSPIPS_LQSPI_SR_OFFSET  	0xA4 /**< Linear QSPI status register */
+#define XQSPIPS_MOD_ID_OFFSET  		0xFC /**< Module ID register */
+
+/* @} */
+
+/** @name Configuration Register
+ *
+ * This register contains various control bits that
+ * affect the operation of the QSPI device. Read/Write.
+ * @{
+ */
+
+#define XQSPIPS_CR_IFMODE_MASK    0x80000000 /**< Flash mem interface mode */
+#define XQSPIPS_CR_ENDIAN_MASK    0x04000000 /**< Tx/Rx FIFO endianness */
+#define XQSPIPS_CR_MANSTRT_MASK   0x00010000 /**< Manual Transmission Start */
+#define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start
+						   Enable */
+#define XQSPIPS_CR_SSFORCE_MASK   0x00004000 /**< Force Slave Select */
+#define XQSPIPS_CR_SSCTRL_MASK    0x00000400 /**< Slave Select Decode */
+#define XQSPIPS_CR_SSCTRL_SHIFT   10	      /**< Slave Select Decode shift */
+#define XQSPIPS_CR_DATA_SZ_MASK   0x000000C0 /**< Size of word to be
+						   transferred */
+#define XQSPIPS_CR_PRESC_MASK     0x00000038 /**< Prescaler Setting */
+#define XQSPIPS_CR_PRESC_SHIFT    3	      /**< Prescaler shift */
+#define XQSPIPS_CR_PRESC_MAXIMUM  0x07	      /**< Prescaler maximum value */
+
+#define XQSPIPS_CR_CPHA_MASK      0x00000004 /**< Phase Configuration */
+#define XQSPIPS_CR_CPOL_MASK      0x00000002 /**< Polarity Configuration */
+
+#define XQSPIPS_CR_MSTREN_MASK    0x00000001 /**< Master Mode Enable */
+
+#define XQSPIPS_CR_HOLD_B_MASK    0x00080000 /**< HOLD_B Pin Drive Enable */
+
+#define XQSPIPS_CR_REF_CLK_MASK   0x00000100 /**< Ref clk bit - should be 0 */
+
+/* Deselect the Slave select line and set the transfer size to 32 at reset */
+#define XQSPIPS_CR_RESET_MASK_SET  XQSPIPS_CR_IFMODE_MASK | \
+				   XQSPIPS_CR_SSCTRL_MASK | \
+				   XQSPIPS_CR_DATA_SZ_MASK | \
+				   XQSPIPS_CR_MSTREN_MASK | \
+				   XQSPIPS_CR_SSFORCE_MASK | \
+				   XQSPIPS_CR_HOLD_B_MASK
+#define XQSPIPS_CR_RESET_MASK_CLR  XQSPIPS_CR_CPOL_MASK | \
+				   XQSPIPS_CR_CPHA_MASK | \
+				   XQSPIPS_CR_PRESC_MASK | \
+				   XQSPIPS_CR_MANSTRTEN_MASK | \
+				   XQSPIPS_CR_MANSTRT_MASK | \
+				   XQSPIPS_CR_ENDIAN_MASK | \
+				   XQSPIPS_CR_REF_CLK_MASK
+/* @} */
+
+
+/** @name QSPI Interrupt Registers
+ *
+ * <b>QSPI Status Register</b>
+ *
+ * This register holds the interrupt status flags for an QSPI device. Some
+ * of the flags are level triggered, which means that they are set as long
+ * as the interrupt condition exists. Other flags are edge triggered,
+ * which means they are set once the interrupt condition occurs and remain
+ * set until they are cleared by software. The interrupts are cleared by
+ * writing a '1' to the interrupt bit position in the Status Register.
+ * Read/Write.
+ *
+ * <b>QSPI Interrupt Enable Register</b>
+ *
+ * This register is used to enable chosen interrupts for an QSPI device.
+ * Writing a '1' to a bit in this register sets the corresponding bit in the
+ * QSPI Interrupt Mask register.  Write only.
+ *
+ * <b>QSPI Interrupt Disable Register </b>
+ *
+ * This register is used to disable chosen interrupts for an QSPI device.
+ * Writing a '1' to a bit in this register clears the corresponding bit in the
+ * QSPI Interrupt Mask register. Write only.
+ *
+ * <b>QSPI Interrupt Mask Register</b>
+ *
+ * This register shows the enabled/disabled interrupts of an QSPI device.
+ * Read only.
+ *
+ * All four registers have the same bit definitions. They are only defined once
+ * for each of the Interrupt Enable Register, Interrupt Disable Register,
+ * Interrupt Mask Register, and Channel Interrupt Status Register
+ * @{
+ */
+
+#define XQSPIPS_IXR_TXUF_MASK	   0x00000040  /**< QSPI Tx FIFO Underflow */
+#define XQSPIPS_IXR_RXFULL_MASK    0x00000020  /**< QSPI Rx FIFO Full */
+#define XQSPIPS_IXR_RXNEMPTY_MASK  0x00000010  /**< QSPI Rx FIFO Not Empty */
+#define XQSPIPS_IXR_TXFULL_MASK    0x00000008  /**< QSPI Tx FIFO Full */
+#define XQSPIPS_IXR_TXOW_MASK	   0x00000004  /**< QSPI Tx FIFO Overwater */
+#define XQSPIPS_IXR_RXOVR_MASK	   0x00000001  /**< QSPI Rx FIFO Overrun */
+#define XQSPIPS_IXR_DFLT_MASK	   0x00000025  /**< QSPI default interrupts
+						    mask */
+#define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041  /**< Interrupts which
+						    need write to clear */
+#define XQSPIPS_ISR_RESET_STATE    0x00000004  /**< Default to tx/rx empty */
+#define XQSPIPS_IXR_DISABLE_ALL    0x0000007D  /**< Disable all interrupts */
+/* @} */
+
+
+/** @name Enable Register
+ *
+ * This register is used to enable or disable an QSPI device.
+ * Read/Write
+ * @{
+ */
+#define XQSPIPS_ER_ENABLE_MASK    0x00000001 /**< QSPI Enable Bit Mask */
+/* @} */
+
+
+/** @name Delay Register
+ *
+ * This register is used to program timing delays in
+ * slave mode. Read/Write
+ * @{
+ */
+#define XQSPIPS_DR_NSS_MASK	0xFF000000 /**< Delay to de-assert slave select
+						between two words mask */
+#define XQSPIPS_DR_NSS_SHIFT	24	   /**< Delay to de-assert slave select
+						between two words shift */
+#define XQSPIPS_DR_BTWN_MASK	0x00FF0000 /**< Delay Between Transfers
+						mask */
+#define XQSPIPS_DR_BTWN_SHIFT	16	   /**< Delay Between Transfers shift */
+#define XQSPIPS_DR_AFTER_MASK	0x0000FF00 /**< Delay After Transfers mask */
+#define XQSPIPS_DR_AFTER_SHIFT	8 	   /**< Delay After Transfers shift */
+#define XQSPIPS_DR_INIT_MASK	0x000000FF /**< Delay Initially mask */
+/* @} */
+
+/** @name Slave Idle Count Registers
+ *
+ * This register defines the number of pclk cycles the slave waits for a the
+ * QSPI clock to become stable in quiescent state before it can detect the start
+ * of the next transfer in CPHA = 1 mode.
+ * Read/Write
+ *
+ * @{
+ */
+#define XQSPIPS_SICR_MASK	0x000000FF /**< Slave Idle Count Mask */
+/* @} */
+
+
+/** @name Transmit FIFO Watermark Register
+ *
+ * This register defines the watermark setting for the Transmit FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_TXWR_MASK           0x0000003F /**< Transmit Watermark Mask */
+#define XQSPIPS_TXWR_RESET_VALUE    0x00000001 /**< Transmit Watermark
+						  * register reset value */
+
+/* @} */
+
+/** @name Receive FIFO Watermark Register
+ *
+ * This register defines the watermark setting for the Receive FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_RXWR_MASK	    0x0000003F /**< Receive Watermark Mask */
+#define XQSPIPS_RXWR_RESET_VALUE    0x00000001 /**< Receive Watermark
+						  * register reset value */
+
+/* @} */
+
+/** @name FIFO Depth
+ *
+ * This macro provides the depth of transmit FIFO and receive FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_FIFO_DEPTH	63	/**< FIFO depth (words) */
+/* @} */
+
+
+/** @name Linear QSPI Configuration Register
+ *
+ * This register contains various control bits that
+ * affect the operation of the Linear QSPI controller. Read/Write.
+ *
+ * @{
+ */
+#define XQSPIPS_LQSPI_CR_LINEAR_MASK	 0x80000000 /**< LQSPI mode enable */
+#define XQSPIPS_LQSPI_CR_TWO_MEM_MASK	 0x40000000 /**< Both memories or one */
+#define XQSPIPS_LQSPI_CR_SEP_BUS_MASK	 0x20000000 /**< Seperate memory bus */
+#define XQSPIPS_LQSPI_CR_U_PAGE_MASK	 0x10000000 /**< Upper memory page */
+#define XQSPIPS_LQSPI_CR_MODE_EN_MASK	 0x02000000 /**< Enable mode bits */
+#define XQSPIPS_LQSPI_CR_MODE_ON_MASK	 0x01000000 /**< Mode on */
+#define XQSPIPS_LQSPI_CR_MODE_BITS_MASK  0x00FF0000 /**< Mode value for dual I/O
+							 or quad I/O */
+#define XQSPIPS_LQSPI_CR_DUMMY_MASK	 0x00000700 /**< Number of dummy bytes
+							 between addr and return
+							 read data */
+#define XQSPIPS_LQSPI_CR_INST_MASK	 0x000000FF /**< Read instr code */
+#define XQSPIPS_LQSPI_CR_RST_STATE	 0x8000016B /**< Default CR value */
+/* @} */
+
+/** @name Linear QSPI Status Register
+ *
+ * This register contains various status bits of the Linear QSPI controller.
+ * Read/Write.
+ *
+ * @{
+ */
+#define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK	  0x00000004 /**< AXI Data FSM Error
+							  received */
+#define XQSPIPS_LQSPI_SR_WR_RECVD_MASK	  0x00000002 /**< AXI write command
+							  received */
+/* @} */
+
+
+/** @name Loopback Delay Adjust Register
+ *
+ * This register contains various bit masks of Loopback Delay Adjust Register.
+ *
+ * @{
+ */
+
+#define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 /**< Loopback Bit */
+
+/* @} */
+
+
+/** @name SLCR Register
+ *
+ * Register offsets from SLCR base address.
+ *
+ * @{
+ */
+
+#define SLCR_LOCK 0x00000004 /**< SLCR Write Protection Lock */
+#define SLCR_UNLOCK 0x00000008 /**< SLCR Write Protection Unlock */
+#define LQSPI_RST_CTRL 0x00000230 /**< Quad SPI Software Reset Control */
+#define SLCR_LOCKSTA 0x0000000C /**< SLCR Write Protection status */
+
+/* @} */
+
+
+/** @name SLCR Register
+ *
+ * Bit Masks of above SLCR Registers .
+ *
+ * @{
+ */
+
+#ifndef XPAR_XSLCR_0_BASEADDR
+#define XPAR_XSLCR_0_BASEADDR 0xF8000000
+#endif
+#define SLCR_LOCK_MASK 0x767B /**< Write Protection Lock mask*/
+#define SLCR_UNLOCK_MASK 0xDF0D /**< SLCR Write Protection Unlock */
+#define LQSPI_RST_CTRL_MASK 0x3 /**< Quad SPI Software Reset Control */
+
+/* @} */
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XQspiPs_In32 Xil_In32
+#define XQspiPs_Out32 Xil_Out32
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XQspiPs_ReadReg(BaseAddress, RegOffset) \
+	XQspiPs_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u32 RegisterValue)
+*
+******************************************************************************/
+#define XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+	XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Functions implemented in xqspips_hw.c
+ */
+void XQspiPs_ResetHw(u32 BaseAddress);
+void XQspiPs_LinearInit(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_options.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_options.c
new file mode 100644
index 0000000000000000000000000000000000000000..911391ccd55a9602c3749c3d6e8e2a6d489b3b3a
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_options.c
@@ -0,0 +1,430 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_options.c
+* @addtogroup qspips_v3_2
+* @{
+*
+* Contains functions for the configuration of the XQspiPs driver component.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00  sdm 11/25/10 First release
+* 2.00a kka 07/25/12 Removed the selection for the following options:
+*		     Master mode (XQSPIPS_MASTER_OPTION) and
+*		     Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
+*		     as the QSPI driver supports the Master mode
+*		     and Flash Interface mode. The driver doesnot support
+*		     Slave mode or the legacy mode.
+* 		     Added the option for setting the Holdb_dr bit in the
+*		     configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
+*		     is the option to be used for setting this bit in the
+*		     configuration register.
+* 2.01a sg  02/03/13 SetDelays and GetDelays API's include DelayNss parameter.
+*
+* 2.02a hk  26/03/13 Removed XQspi_Reset() in Set_Options() function when
+*			 LQSPI_MODE_OPTION is set. Moved Enable() to XQpsiPs_LqspiRead().
+* 3.3   sk  11/07/15 Modified the API prototypes according to MISRAC standards
+*                    to remove compilation warnings. CR# 868893.
+*</pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * Create the table of options which are processed to get/set the device
+ * options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+typedef struct {
+	u32 Option;
+	u32 Mask;
+} OptionsMap;
+
+static OptionsMap OptionsTable[] = {
+	{XQSPIPS_CLK_ACTIVE_LOW_OPTION, XQSPIPS_CR_CPOL_MASK},
+	{XQSPIPS_CLK_PHASE_1_OPTION, XQSPIPS_CR_CPHA_MASK},
+	{XQSPIPS_FORCE_SSELECT_OPTION, XQSPIPS_CR_SSFORCE_MASK},
+	{XQSPIPS_MANUAL_START_OPTION, XQSPIPS_CR_MANSTRTEN_MASK},
+	{XQSPIPS_HOLD_B_DRIVE_OPTION, XQSPIPS_CR_HOLD_B_MASK},
+};
+
+#define XQSPIPS_NUM_OPTIONS	(sizeof(OptionsTable) / sizeof(OptionsMap))
+
+/*****************************************************************************/
+/**
+*
+* This function sets the options for the QSPI device driver. The options control
+* how the device behaves relative to the QSPI bus. The device must be idle
+* rather than busy transferring data before setting these device options.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	Options contains the specified options to be set. This is a bit
+*		mask where a 1 means to turn the option on, and a 0 means to
+*		turn the option off. One or more bit values may be contained in
+*		the mask. See the bit definitions named XQSPIPS_*_OPTIONS in
+*		the file xqspips.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting options.
+*
+* @note
+* This function is not thread-safe.
+*
+******************************************************************************/
+s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options)
+{
+	u32 ConfigReg;
+	unsigned int Index;
+	u32 QspiOptions;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Do not allow to modify the Control Register while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	QspiOptions = Options & XQSPIPS_LQSPI_MODE_OPTION;
+	Options &= ~XQSPIPS_LQSPI_MODE_OPTION;
+
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPS_CR_OFFSET);
+
+	/*
+	 * Loop through the options table, turning the option on or off
+	 * depending on whether the bit is set in the incoming options flag.
+	 */
+	for (Index = 0; Index < XQSPIPS_NUM_OPTIONS; Index++) {
+		if (Options & OptionsTable[Index].Option) {
+			/* Turn it on */
+			ConfigReg |= OptionsTable[Index].Mask;
+		} else {
+			/* Turn it off */
+			ConfigReg &= ~(OptionsTable[Index].Mask);
+		}
+	}
+
+	/*
+	 * Now write the control register. Leave it to the upper layers
+	 * to restart the device.
+	 */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET,
+			 ConfigReg);
+
+	/*
+	 * Check for the LQSPI configuration options.
+	 */
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPS_LQSPI_CR_OFFSET);
+
+
+	if (QspiOptions & XQSPIPS_LQSPI_MODE_OPTION) {
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPS_LQSPI_CR_OFFSET,
+				  XQSPIPS_LQSPI_CR_RST_STATE);
+		XQspiPs_SetSlaveSelect(InstancePtr);
+	} else {
+		ConfigReg &= ~XQSPIPS_LQSPI_CR_LINEAR_MASK;
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPS_LQSPI_CR_OFFSET, ConfigReg);
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the options for the QSPI device. The options control how
+* the device behaves relative to the QSPI bus.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+*
+* Options contains the specified options currently set. This is a bit value
+* where a 1 means the option is on, and a 0 means the option is off.
+* See the bit definitions named XQSPIPS_*_OPTIONS in file xqspips.h.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XQspiPs_GetOptions(XQspiPs *InstancePtr)
+{
+	u32 OptionsFlag = 0;
+	u32 ConfigReg;
+	unsigned int Index;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Get the current options from QSPI configuration register.
+	 */
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPS_CR_OFFSET);
+
+	/*
+	 * Loop through the options table to grab options
+	 */
+	for (Index = 0; Index < XQSPIPS_NUM_OPTIONS; Index++) {
+		if (ConfigReg & OptionsTable[Index].Mask) {
+			OptionsFlag |= OptionsTable[Index].Option;
+		}
+	}
+
+	/*
+	 * Check for the LQSPI configuration options.
+	 */
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPS_LQSPI_CR_OFFSET);
+
+	if ((ConfigReg & XQSPIPS_LQSPI_CR_LINEAR_MASK) != 0) {
+		OptionsFlag |= XQSPIPS_LQSPI_MODE_OPTION;
+	}
+
+	return OptionsFlag;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the clock prescaler for an QSPI device. The device
+* must be idle rather than busy transferring data before setting these device
+* options.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	Prescaler is the value that determine how much the clock should
+*		be divided by. Use the XQSPIPS_CLK_PRESCALE_* constants defined
+*		in xqspips.h for this setting.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting options.
+*
+* @note
+* This function is not thread-safe.
+*
+******************************************************************************/
+s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler)
+{
+	u32 ConfigReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Prescaler <= XQSPIPS_CR_PRESC_MAXIMUM);
+
+	/*
+	 * Do not allow the slave select to change while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	/*
+	 * Read the configuration register, mask out the interesting bits, and set
+	 * them with the shifted value passed into the function. Write the
+	 * results back to the configuration register.
+	 */
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPS_CR_OFFSET);
+
+	ConfigReg &= ~XQSPIPS_CR_PRESC_MASK;
+	ConfigReg |= (u32) (Prescaler & XQSPIPS_CR_PRESC_MAXIMUM) <<
+			    XQSPIPS_CR_PRESC_SHIFT;
+
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XQSPIPS_CR_OFFSET,
+			  ConfigReg);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the clock prescaler of an QSPI device.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	The prescaler value.
+*
+* @note		None.
+*
+*
+******************************************************************************/
+u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr)
+{
+	u32 ConfigReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPS_CR_OFFSET);
+
+	ConfigReg &= XQSPIPS_CR_PRESC_MASK;
+
+	return (u8)(ConfigReg >> XQSPIPS_CR_PRESC_SHIFT);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the delay register for the QSPI device driver.
+* The delay register controls the Delay Between Transfers, Delay After
+* Transfers, and the Delay Initially. The default value is 0x0. The range of
+* each delay value is 0-255.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	DelayNss is the delay to de-assert slave select between
+*		two word transfers.
+* @param	DelayBtwn is the delay between one Slave Select being
+*		de-activated and the activation of another slave. The delay is
+*		the number of master clock periods given by DelayBtwn + 2.
+* @param	DelayAfter define the delay between the last bit of the current
+*		byte transfer and the first bit of the next byte transfer.
+*		The delay in number of master clock periods is given as:
+*		CHPA=0:DelayInit+DelayAfter+3
+*		CHPA=1:DelayAfter+1
+* @param	DelayInit is the delay between asserting the slave select signal
+*		and the first bit transfer. The delay int number of master clock
+*		periods is DelayInit+1.
+*
+* @return
+*		- XST_SUCCESS if delays are successfully set.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting options.
+*
+* @note		None.
+*
+******************************************************************************/
+int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
+			 u8 DelayAfter, u8 DelayInit)
+{
+	u32 DelayRegister;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Do not allow the delays to change while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	/* Shift, Mask and OR the values to build the register settings */
+	DelayRegister = (u32) DelayNss << XQSPIPS_DR_NSS_SHIFT;
+	DelayRegister |= (u32) DelayBtwn << XQSPIPS_DR_BTWN_SHIFT;
+	DelayRegister |= (u32) DelayAfter << XQSPIPS_DR_AFTER_SHIFT;
+	DelayRegister |= (u32) DelayInit;
+
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XQSPIPS_DR_OFFSET, DelayRegister);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the delay settings for an QSPI device.
+* The delay register controls the Delay Between Transfers, Delay After
+* Transfers, and the Delay Initially. The default value is 0x0.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	DelayNss is a pointer to the Delay to de-assert slave select
+*		between two word transfers.
+* @param	DelayBtwn is a pointer to the Delay Between transfers value.
+*		This is a return parameter.
+* @param	DelayAfter is a pointer to the Delay After transfer value.
+*		This is a return parameter.
+* @param	DelayInit is a pointer to the Delay Initially value. This is
+*		a return parameter.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
+			 u8 *DelayAfter, u8 *DelayInit)
+{
+	u32 DelayRegister;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	DelayRegister = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+					 XQSPIPS_DR_OFFSET);
+
+	*DelayInit = (u8)(DelayRegister & XQSPIPS_DR_INIT_MASK);
+
+	*DelayAfter = (u8)((DelayRegister & XQSPIPS_DR_AFTER_MASK) >>
+			   XQSPIPS_DR_AFTER_SHIFT);
+
+	*DelayBtwn = (u8)((DelayRegister & XQSPIPS_DR_BTWN_MASK) >>
+			  XQSPIPS_DR_BTWN_SHIFT);
+
+	*DelayNss = (u8)((DelayRegister & XQSPIPS_DR_NSS_MASK) >>
+			  XQSPIPS_DR_NSS_SHIFT);
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_selftest.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_selftest.c
new file mode 100644
index 0000000000000000000000000000000000000000..309b36e2b8ff8f1be384f4d7c2037ff0c9274466
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_selftest.c
@@ -0,0 +1,139 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_selftest.c
+* @addtogroup qspips_v3_2
+* @{
+*
+* This file contains the implementation of selftest function for the QSPI
+* device.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00  sdm 11/25/10 First release
+* 2.01a sg  02/03/13 Delay Register test is added with DelayNss parameter.
+* 3.1   hk  06/19/14 Remove checks for CR and ISR register values as they are
+*                    reset in the previous step.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Runs a self-test on the driver/device. The self-test is destructive in that
+* a reset of the device is performed in order to check the reset values of
+* the registers and to get the device into a known state.
+*
+* Upon successful return from the self-test, the device is reset.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+* 		- XST_SUCCESS if successful
+*		- XST_REGISTER_ERROR indicates a register did not read or write
+*		correctly.
+*
+* @note		None.
+*
+******************************************************************************/
+int XQspiPs_SelfTest(XQspiPs *InstancePtr)
+{
+	int Status;
+	u8 DelayTestNss;
+	u8 DelayTestBtwn;
+	u8 DelayTestAfter;
+	u8 DelayTestInit;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Reset the QSPI device to leave it in a known good state
+	 */
+	XQspiPs_Reset(InstancePtr);
+
+	DelayTestNss = 0x5A;
+	DelayTestBtwn = 0xA5;
+	DelayTestAfter = 0xAA;
+	DelayTestInit = 0x55;
+
+	/*
+	 * Write and read the delay register, just to be sure there is some
+	 * hardware out there.
+	 */
+	Status = XQspiPs_SetDelays(InstancePtr, DelayTestNss, DelayTestBtwn,
+				DelayTestAfter, DelayTestInit);
+	if (Status != XST_SUCCESS) {
+		return Status;
+	}
+
+	XQspiPs_GetDelays(InstancePtr, &DelayTestNss, &DelayTestBtwn,
+				&DelayTestAfter, &DelayTestInit);
+	if ((0x5A != DelayTestNss) || (0xA5 != DelayTestBtwn) ||
+		(0xAA != DelayTestAfter) || (0x55 != DelayTestInit)) {
+		return XST_REGISTER_ERROR;
+	}
+
+	Status = XQspiPs_SetDelays(InstancePtr, 0, 0, 0, 0);
+	if (Status != XST_SUCCESS) {
+		return Status;
+	}
+
+	/*
+	 * Reset the QSPI device to leave it in a known good state
+	 */
+	XQspiPs_Reset(InstancePtr);
+
+	return XST_SUCCESS;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_sinit.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..be154be992ac7bb7a2b96050de90b1967531a91c
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_sinit.c
@@ -0,0 +1,100 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_sinit.c
+* @addtogroup qspips_v3_2
+* @{
+*
+* The implementation of the XQspiPs component's static initialization
+* functionality.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00  sdm 11/25/10 First release
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xqspips.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+extern XQspiPs_Config XQspiPs_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device to look up the
+*		configuration for.
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xqspips.h for the definition of XQspiPs_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId)
+{
+	XQspiPs_Config *CfgPtr = NULL;
+	int Index;
+
+	for (Index = 0; Index < XPAR_XQSPIPS_NUM_INSTANCES; Index++) {
+		if (XQspiPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XQspiPs_ConfigTable[Index];
+			break;
+		}
+	}
+	return CfgPtr;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/Makefile b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..04867a48426ff72c6b489901e8c934d39ec68038
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner scugic_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling scugic"
+
+scugic_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: scugic_includes
+
+scugic_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic.c
new file mode 100644
index 0000000000000000000000000000000000000000..8c83a8ad36ea51db766e847bd50d134a73c7ed22
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic.c
@@ -0,0 +1,946 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic.c
+* @addtogroup scugic_v3_1
+* @{
+*
+* Contains required functions for the XScuGic driver for the Interrupt
+* Controller. See xscugic.h for a detailed description of the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- --------------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 1.01a sdm  11/09/11 Changes are made in function XScuGic_CfgInitialize. Since
+*		      		  "Config" entry is now made as pointer in the XScuGic
+*		      		  structure, necessary changes are made.
+*		      		  The HandlerTable can now be populated through the low
+*		      		  level routine XScuGic_RegisterHandler added in this
+*		      		  release. Hence necessary checks are added not to
+*		      		  overwrite the HandlerTable entriesin function
+*		      		  XScuGic_CfgInitialize.
+* 1.03a srt  02/27/13 Added APIs
+*					  - XScuGic_SetPriTrigTypeByDistAddr()
+*					  - XScuGic_GetPriTrigTypeByDistAddr()
+* 		    		  Removed Offset calculation macros, defined in _hw.h
+*		      		  (CR 702687)
+*			  		  Added support to direct interrupts to the appropriate CPU. Earlier
+*			  		  interrupts were directed to CPU1 (hard coded). Now depending
+*			  		  upon the CPU selected by the user (xparameters.h), interrupts
+*			  		  will be directed to the relevant CPU. This fixes CR 699688.
+*
+* 1.04a hk   05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+*			  		  XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+*			  		  Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+*             		  XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+*			  		  This is fix for CR#705621.
+* 1.06a asa  16/11/13 Fix for CR#749178. Assignment for EffectiveAddr
+*			  		  in function XScuGic_CfgInitialize is removed as it was
+*		      		  a bug.
+* 3.00  kvn  02/13/14 Modified code for MISRA-C:2012 compliance.
+* 3.01	pkp	 06/19/15 Added XScuGic_InterruptMaptoCpu API for an interrupt
+*			  		  target CPU mapping
+* 3.02	pkp	 11/09/15 Modified DistributorInit function for AMP case to add
+*					  the current cpu to interrupt processor targets registers
+* 3.2   asa  02/29/16 Modified DistributorInit function for Zynq AMP case. The
+*			  		  distributor is left uninitialized for Zynq AMP. It is assumed
+*             		  that the distributor will be initialized by Linux master. However
+*             		  for CortexR5 case, the earlier code is left unchanged where the
+*             		  the interrupt processor target registers in the distributor is
+*             		  initialized with the corresponding CPU ID on which the application
+*             		  built over the scugic driver runs.
+*             		  These changes fix CR#937243.
+* 3.3	pkp  05/12/16 Modified XScuGic_InterruptMaptoCpu to write proper value
+*					  to interrupt target register to fix CR#951848
+*
+* 3.4   asa  04/07/16 Created a new static function DoDistributorInit to simplify
+*                     the flow and avoid code duplication. Changes are made for
+*                     USE_AMP use case for R5. In a scenario (in R5 split mode) when
+*                     one R5 is operating with A53 in open amp config and other
+*                     R5 running baremetal app, the existing code
+*                     had the potential to stop the whole AMP solution to work (if
+*                     for some reason the R5 running the baremetal app tasked to
+*                     initialize the Distributor hangs or crashes before initializing).
+*                     Changes are made so that the R5 under AMP first checks if
+*                     the distributor is enabled or not and if not, it does the
+*                     standard Distributor initialization.
+*                     This fixes the CR#952962.
+* 3.4   mus  09/08/16 Added assert to avoid invalid access of GIC from CPUID 1
+*                     for single core zynq-7000s
+* 3.5   mus  10/05/16 Modified DistributorInit function to avoid re-initialization of
+*                     distributor,If it is already initialized by other CPU.
+* 3.5	pkp	 10/17/16 Modified XScuGic_InterruptMaptoCpu to correct the CPU Id value
+*					  and properly mask interrupt target processor value to modify
+*					  interrupt target processor register for a given interrupt ID
+*					  and cpu ID
+* 3.6	pkp	 20/01/17 Added new API XScuGic_Stop to Disable distributor and
+*					  interrupts in case they are being used only by current cpu.
+*					  It also removes current cpu from interrupt target registers
+*					  for all interrupts.
+*       kvn  02/17/17 Add support for changing GIC CPU master at run time.
+*       kvn  02/28/17 Make the CpuId as static variable and Added new
+*                     XScugiC_GetCpuId to access CpuId.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+static u32 CpuId = XPAR_CPU_ID; /**< CPU Core identifier */
+
+/************************** Function Prototypes ******************************/
+
+static void StubHandler(void *CallBackRef);
+
+/*****************************************************************************/
+/**
+*
+* DoDistributorInit initializes the distributor of the GIC. The
+* initialization entails:
+*
+* - Write the trigger mode, priority and target CPU
+* - All interrupt sources are disabled
+* - Enable the distributor
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	CpuID is the Cpu ID to be initialized.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void DoDistributorInit(XScuGic *InstancePtr, u32 CpuID)
+{
+	u32 Int_Id;
+	u32 LocalCpuID = CpuID;
+
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0U);
+
+	/*
+	 * Set the security domains in the int_security registers for
+	 * non-secure interrupts
+	 * All are secure, so leave at the default. Set to 1 for non-secure
+	 * interrupts.
+	 */
+
+	/*
+	 * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
+	 */
+
+	/*
+	 * 1. The trigger mode in the int_config register
+	 * Only write to the SPI interrupts, so start at 32
+	 */
+	for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id=Int_Id+16U) {
+		/*
+		 * Each INT_ID uses two bits, or 16 INT_ID per register
+		 * Set them all to be level sensitive, active HIGH.
+		 */
+		XScuGic_DistWriteReg(InstancePtr,
+					XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+					0U);
+	}
+
+
+#define DEFAULT_PRIORITY    0xa0a0a0a0U
+	for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id=Int_Id+4U) {
+		/*
+		 * 2. The priority using int the priority_level register
+		 * The priority_level and spi_target registers use one byte per
+		 * INT_ID.
+		 * Write a default value that can be changed elsewhere.
+		 */
+		XScuGic_DistWriteReg(InstancePtr,
+					XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+					DEFAULT_PRIORITY);
+	}
+
+	for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U) {
+		/*
+		 * 3. The CPU interface in the spi_target register
+		 * Only write to the SPI interrupts, so start at 32
+		 */
+		LocalCpuID |= LocalCpuID << 8U;
+		LocalCpuID |= LocalCpuID << 16U;
+
+		XScuGic_DistWriteReg(InstancePtr,
+					 XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
+					 LocalCpuID);
+	}
+
+	for (Int_Id = 0U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+32U) {
+		/*
+		 * 4. Enable the SPI using the enable_set register. Leave all
+		 * disabled for now.
+		 */
+		XScuGic_DistWriteReg(InstancePtr,
+		XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET, Int_Id),
+			0xFFFFFFFFU);
+
+	}
+
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET,
+					XSCUGIC_EN_INT_MASK);
+}
+
+/*****************************************************************************/
+/**
+*
+* DistributorInit initializes the distributor of the GIC. It calls
+* DoDistributorInit to finish the initialization.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	CpuID is the Cpu ID to be initialized.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void DistributorInit(XScuGic *InstancePtr, u32 CpuID)
+{
+	u32 Int_Id;
+	u32 LocalCpuID = CpuID;
+	u32 RegValue;
+
+#if USE_AMP==1 && (defined (ARMA9) || defined(__aarch64__))
+#warning "Building GIC for AMP"
+	/*
+	 * GIC initialization is taken care by master CPU in
+	 * openamp configuration, so do nothing and return.
+	 */
+	return;
+#endif
+
+	RegValue = XScuGic_DistReadReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET);
+	if ((RegValue & XSCUGIC_EN_INT_MASK) == 0U) {
+		Xil_AssertVoid(InstancePtr != NULL);
+		DoDistributorInit(InstancePtr, CpuID);
+		return;
+	}
+
+	/*
+	 * The overall distributor should not be initialized in AMP case where
+	 * another CPU is taking care of it.
+	 */
+	LocalCpuID |= LocalCpuID << 8U;
+	LocalCpuID |= LocalCpuID << 16U;
+	for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U) {
+		RegValue = XScuGic_DistReadReg(InstancePtr,
+						XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+		RegValue |= LocalCpuID;
+		XScuGic_DistWriteReg(InstancePtr,
+				     XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
+				     RegValue);
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* CPUInitialize initializes the CPU Interface of the GIC. The initialization entails:
+*
+*	- Set the priority of the CPU
+*	- Enable the CPU interface
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void CPUInitialize(XScuGic *InstancePtr)
+{
+	/*
+	 * Program the priority mask of the CPU using the Priority mask register
+	 */
+	XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_CPU_PRIOR_OFFSET, 0xF0U);
+
+
+	/*
+	 * If the CPU operates in both security domains, set parameters in the
+	 * control_s register.
+	 * 1. Set FIQen=1 to use FIQ for secure interrupts,
+	 * 2. Program the AckCtl bit
+	 * 3. Program the SBPR bit to select the binary pointer behavior
+	 * 4. Set EnableS = 1 to enable secure interrupts
+	 * 5. Set EnbleNS = 1 to enable non secure interrupts
+	 */
+
+	/*
+	 * If the CPU operates only in the secure domain, setup the
+	 * control_s register.
+	 * 1. Set FIQen=1,
+	 * 2. Set EnableS=1, to enable the CPU interface to signal secure interrupts.
+	 * Only enable the IRQ output unless secure interrupts are needed.
+	 */
+	XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_CONTROL_OFFSET, 0x07U);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* CfgInitialize a specific interrupt controller instance/driver. The
+* initialization entails:
+*
+* - Initialize fields of the XScuGic structure
+* - Initial vector table with stub function calls
+* - All interrupt sources are disabled
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	ConfigPtr is a pointer to a config table for the particular
+*		device this driver is associated with.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, use
+*		Config->BaseAddress for this parameters, passing the physical
+*		address instead.
+*
+* @return
+*		- XST_SUCCESS if initialization was successful
+*
+* @note		None.
+*
+******************************************************************************/
+s32  XScuGic_CfgInitialize(XScuGic *InstancePtr,
+				XScuGic_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	u32 Int_Id;
+	u32 Cpu_Id = CpuId + (u32)1;
+	(void) EffectiveAddr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+	/*
+     * Detect Zynq-7000 base silicon configuration,Dual or Single CPU.
+     * If it is single CPU cnfiguration then invoke assert for CPU ID=1
+	 */
+#ifdef ARMA9
+	if ( XPAR_CPU_ID == 0x01 )
+	{
+		Xil_AssertNonvoid((Xil_In32(XPS_EFUSE_BASEADDR + EFUSE_STATUS_OFFSET)
+		 & EFUSE_STATUS_CPU_MASK ) == 0);
+	}
+#endif
+
+	if(InstancePtr->IsReady != XIL_COMPONENT_IS_READY) {
+
+		InstancePtr->IsReady = 0U;
+		InstancePtr->Config = ConfigPtr;
+
+
+		for (Int_Id = 0U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id++) {
+			/*
+			* Initalize the handler to point to a stub to handle an
+			* interrupt which has not been connected to a handler. Only
+			* initialize it if the handler is 0 which means it was not
+			* initialized statically by the tools/user. Set the callback
+			* reference to this instance so that unhandled interrupts
+			* can be tracked.
+			*/
+			if 	((InstancePtr->Config->HandlerTable[Int_Id].Handler == NULL)) {
+				InstancePtr->Config->HandlerTable[Int_Id].Handler =
+									StubHandler;
+			}
+			InstancePtr->Config->HandlerTable[Int_Id].CallBackRef =
+								InstancePtr;
+		}
+		XScuGic_Stop(InstancePtr);
+		DistributorInit(InstancePtr, Cpu_Id);
+		CPUInitialize(InstancePtr);
+
+		InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Makes the connection between the Int_Id of the interrupt source and the
+* associated handler that is to run when the interrupt is recognized. The
+* argument provided in this call as the Callbackref is used as the argument
+* for the handler when it is called.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	Int_Id contains the ID of the interrupt source and should be
+*		in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+* @param	Handler to the handler for that interrupt.
+* @param	CallBackRef is the callback reference, usually the instance
+*		pointer of the connecting driver.
+*
+* @return
+*
+*		- XST_SUCCESS if the handler was connected correctly.
+*
+* @note
+*
+* WARNING: The handler provided as an argument will overwrite any handler
+* that was previously connected.
+*
+****************************************************************************/
+s32  XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
+                      Xil_InterruptHandler Handler, void *CallBackRef)
+{
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertNonvoid(Handler != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The Int_Id is used as an index into the table to select the proper
+	 * handler
+	 */
+	InstancePtr->Config->HandlerTable[Int_Id].Handler = Handler;
+	InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = CallBackRef;
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Updates the interrupt table with the Null Handler and NULL arguments at the
+* location pointed at by the Int_Id. This effectively disconnects that interrupt
+* source from any handler. The interrupt is disabled also.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance to be worked on.
+* @param	Int_Id contains the ID of the interrupt source and should
+*		be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id)
+{
+	u32 Mask;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The Int_Id is used to create the appropriate mask for the
+	 * desired bit position. Int_Id currently limited to 0 - 31
+	 */
+	Mask = 0x00000001U << (Int_Id % 32U);
+
+	/*
+	 * Disable the interrupt such that it won't occur while disconnecting
+	 * the handler, only disable the specified interrupt id without modifying
+	 * the other interrupt ids
+	 */
+	XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET +
+						((Int_Id / 32U) * 4U), Mask);
+
+	/*
+	 * Disconnect the handler and connect a stub, the callback reference
+	 * must be set to this instance to allow unhandled interrupts to be
+	 * tracked
+	 */
+	InstancePtr->Config->HandlerTable[Int_Id].Handler = StubHandler;
+	InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = InstancePtr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Enables the interrupt source provided as the argument Int_Id. Any pending
+* interrupt condition for the specified Int_Id will occur after this function is
+* called.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	Int_Id contains the ID of the interrupt source and should be
+*		in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id)
+{
+	u32 Mask;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The Int_Id is used to create the appropriate mask for the
+	 * desired bit position. Int_Id currently limited to 0 - 31
+	 */
+	Mask = 0x00000001U << (Int_Id % 32U);
+
+	/*
+	 * Enable the selected interrupt source by setting the
+	 * corresponding bit in the Enable Set register.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_ENABLE_SET_OFFSET +
+						((Int_Id / 32U) * 4U), Mask);
+}
+
+/*****************************************************************************/
+/**
+*
+* Disables the interrupt source provided as the argument Int_Id such that the
+* interrupt controller will not cause interrupts for the specified Int_Id. The
+* interrupt controller will continue to hold an interrupt condition for the
+* Int_Id, but will not cause an interrupt.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	Int_Id contains the ID of the interrupt source and should be
+*		in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id)
+{
+	u32 Mask;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The Int_Id is used to create the appropriate mask for the
+	 * desired bit position. Int_Id currently limited to 0 - 31
+	 */
+	Mask = 0x00000001U << (Int_Id % 32U);
+
+	/*
+	 * Disable the selected interrupt source by setting the
+	 * corresponding bit in the IDR.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET +
+						((Int_Id / 32U) * 4U), Mask);
+}
+
+/*****************************************************************************/
+/**
+*
+* Allows software to simulate an interrupt in the interrupt controller.  This
+* function will only be successful when the interrupt controller has been
+* started in simulation mode.  A simulated interrupt allows the interrupt
+* controller to be tested without any device to drive an interrupt input
+* signal into it.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	Int_Id is the software interrupt ID to simulate an interrupt.
+* @param	Cpu_Id is the list of CPUs to send the interrupt.
+*
+* @return
+*
+* XST_SUCCESS if successful, or XST_FAILURE if the interrupt could not be
+* simulated
+*
+* @note		None.
+*
+******************************************************************************/
+s32  XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id)
+{
+	u32 Mask;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Int_Id <= 15U) ;
+	Xil_AssertNonvoid(Cpu_Id <= 255U) ;
+
+
+	/*
+	 * The Int_Id is used to create the appropriate mask for the
+	 * desired interrupt. Int_Id currently limited to 0 - 15
+	 * Use the target list for the Cpu ID.
+	 */
+	Mask = ((Cpu_Id << 16U) | Int_Id) &
+		(XSCUGIC_SFI_TRIG_CPU_MASK | XSCUGIC_SFI_TRIG_INTID_MASK);
+
+	/*
+	 * Write to the Software interrupt trigger register. Use the appropriate
+	 * CPU Int_Id.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_SFI_TRIG_OFFSET, Mask);
+
+	/* Indicate the interrupt was successfully simulated */
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* A stub for the asynchronous callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param	CallBackRef is a pointer to the upper layer callback reference
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void StubHandler(void *CallBackRef) {
+	/*
+	 * verify that the inputs are valid
+	 */
+	Xil_AssertVoid(CallBackRef != NULL);
+
+	/*
+	 * Indicate another unhandled interrupt for stats
+	 */
+	((XScuGic *)((void *)CallBackRef))->UnhandledInterrupts++;
+}
+
+/****************************************************************************/
+/**
+* Sets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Int_Id is the IRQ source number to modify
+* @param	Priority is the new priority for the IRQ source. 0 is highest
+* 			priority, 0xF8 (248) is lowest. There are 32 priority levels
+*			supported with a step of 8. Hence the supported priorities are
+*			0, 8, 16, 32, 40 ..., 248.
+* @param	Trigger is the new trigger type for the IRQ source.
+* Each bit pair describes the configuration for an INT_ID.
+* SFI    Read Only    b10 always
+* PPI    Read Only    depending on how the PPIs are configured.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive
+* SPI                LSB is read only.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive/
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 Priority, u8 Trigger)
+{
+	u32 RegValue;
+	u8 LocalPriority;
+	LocalPriority = Priority;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(Trigger <= (u8)XSCUGIC_INT_CFG_MASK);
+	Xil_AssertVoid(LocalPriority <= (u8)XSCUGIC_MAX_INTR_PRIO_VAL);
+
+	/*
+	 * Determine the register to write to using the Int_Id.
+	 */
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+			XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+	/*
+	 * The priority bits are Bits 7 to 3 in GIC Priority Register. This
+	 * means the number of priority levels supported are 32 and they are
+	 * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
+	 * The lower order 3 bits are masked before putting it in the register.
+	 */
+	LocalPriority = LocalPriority & (u8)XSCUGIC_INTR_PRIO_MASK;
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U));
+	RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U);
+
+	/*
+	 * Write the value back to the register.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+				RegValue);
+
+	/*
+	 * Determine the register to write to using the Int_Id.
+	 */
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+			XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U));
+	RegValue |= (u32)Trigger << ((Int_Id%16U)*2U);
+
+	/*
+	 * Write the value back to the register.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+				RegValue);
+
+}
+
+/****************************************************************************/
+/**
+* Gets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Int_Id is the IRQ source number to modify
+* @param	Priority is a pointer to the value of the priority of the IRQ
+*		source. This is a return value.
+* @param	Trigger is pointer to the value of the trigger of the IRQ
+*		source. This is a return value.
+*
+* @return	None.
+*
+* @note		None
+*
+*****************************************************************************/
+void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 *Priority, u8 *Trigger)
+{
+	u32 RegValue;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(Priority != NULL);
+	Xil_AssertVoid(Trigger != NULL);
+
+	/*
+	 * Determine the register to read to using the Int_Id.
+	 */
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+	    XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue = RegValue >> ((Int_Id%4U)*8U);
+	*Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
+
+	/*
+	 * Determine the register to read to using the Int_Id.
+	 */
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+	XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue = RegValue >> ((Int_Id%16U)*2U);
+
+	*Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
+}
+/****************************************************************************/
+/**
+* Sets the target CPU for the interrupt of a peripheral
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Cpu_Id is a CPU number for which the interrupt has to be targeted
+* @param	Int_Id is the IRQ source number to modify
+*
+* @return	None.
+*
+* @note		None
+*
+*****************************************************************************/
+void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id)
+{
+	u32 RegValue, Offset;
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+			XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+
+	Offset = (Int_Id & 0x3U);
+	Cpu_Id = (0x1U << Cpu_Id);
+
+	RegValue = (RegValue & (~(0xFFU << (Offset*8U))) );
+	RegValue |= ((Cpu_Id) << (Offset*8U));
+
+	XScuGic_DistWriteReg(InstancePtr,
+						 XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
+						 RegValue);
+}
+/****************************************************************************/
+/**
+* It checks if the interrupt target register contains all interrupts to be
+* targeted for current CPU. If they are programmed to be forwarded to current
+* cpu, this API disable all interrupts and disable GIC distributor.
+* This API also removes current CPU from interrupt target registers for all
+* interrupt.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+*
+* @return	None.
+*
+* @note		None
+*
+*****************************************************************************/
+void XScuGic_Stop(XScuGic *InstancePtr)
+{
+	u32 Int_Id;
+	u32 RegValue;
+	u32 Target_Cpu;
+	u32 DistDisable = 1; /* To track if distributor need to be disabled or not */
+	u32 LocalCpuID = ((u32)0x1 << CpuId);
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	/* If distributor is already disabled, no need to do anything */
+	RegValue = XScuGic_DistReadReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET);
+	if ((RegValue & XSCUGIC_EN_INT_MASK) == 0U) {
+		return;
+	}
+
+	LocalCpuID |= LocalCpuID << 8U;
+	LocalCpuID |= LocalCpuID << 16U;
+
+	/*
+	 * Check if the interrupt are targeted to current cpu only or not.
+	 * Also remove current cpu from interrupt target register for all
+	 * interrupts.
+	 */
+	for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U) {
+
+		Target_Cpu = XScuGic_DistReadReg(InstancePtr,
+									XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+		if ((Target_Cpu != LocalCpuID) && (Target_Cpu!= 0)) {
+			/*
+			 * If any other CPU is also programmed to target register, GIC
+			 * distributor can not be disabled.
+			 */
+			DistDisable = 0;
+		}
+
+		/* Remove current CPU from interrupt target register */
+		Target_Cpu &= (~LocalCpuID);
+		XScuGic_DistWriteReg(InstancePtr,
+						XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu);
+
+	}
+
+	/*
+	 * If GIC distributor is safe to be disabled, disable all the interrupt
+	 * and then disable distributor.
+	 */
+	if ( DistDisable == 1) {
+		for (Int_Id = 0U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+32U) {
+			/*
+			 * Disable all the interrupts
+			 */
+			XScuGic_DistWriteReg(InstancePtr,
+							XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET,
+							Int_Id),
+			0xFFFFFFFFU);
+		}
+		XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0U);
+	}
+}
+
+/****************************************************************************/
+/**
+* This updates the CpuId global variable.
+*
+* @param	CpuCoreId is the CPU core number.
+*
+* @return	None.
+*
+* @note		None
+*
+*****************************************************************************/
+void XScuGic_SetCpuID(u32 CpuCoreId)
+{
+	Xil_AssertVoid(CpuCoreId <= 1U);
+
+	CpuId = CpuCoreId;
+}
+
+/****************************************************************************/
+/**
+* This function returns the CpuId variable.
+*
+* @param	None.
+*
+* @return	The CPU core number.
+*
+* @note        None.
+*
+*****************************************************************************/
+u32 XScuGic_GetCpuID(void)
+{
+	return CpuId;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic.h
new file mode 100644
index 0000000000000000000000000000000000000000..fb6624239ffdb197717fda8864cbcf9d6385ca52
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic.h
@@ -0,0 +1,357 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic.h
+* @addtogroup scugic_v3_1
+* @{
+* @details
+*
+* The generic interrupt controller driver component.
+*
+* The interrupt controller driver uses the idea of priority for the various
+* handlers. Priority is an integer within the range of 1 and 31 inclusive with
+* default of 1 being the highest priority interrupt source. The priorities
+* of the various sources can be dynamically altered as needed through
+* hardware configuration.
+*
+* The generic interrupt controller supports the following
+* features:
+*
+*   - specific individual interrupt enabling/disabling
+*   - specific individual interrupt acknowledging
+*   - attaching specific callback function to handle interrupt source
+*   - assigning desired priority to interrupt source if default is not
+*     acceptable.
+*
+* Details about connecting the interrupt handler of the driver are contained
+* in the source file specific to interrupt processing, xscugic_intr.c.
+*
+* This driver is intended to be RTOS and processor independent.  It works with
+* physical addresses only.  Any needs for dynamic memory management, threads
+* or thread mutual exclusion, virtual memory, or cache control must be
+* satisfied by the layer above this driver.
+*
+* <b>Interrupt Vector Tables</b>
+*
+* The device ID of the interrupt controller device is used by the driver as a
+* direct index into the configuration data table. The user should populate the
+* vector table with handlers and callbacks at run-time using the
+* XScuGic_Connect() and XScuGic_Disconnect() functions.
+*
+* Each vector table entry corresponds to a device that can generate an
+* interrupt. Each entry contains an interrupt handler function and an
+* argument to be passed to the handler when an interrupt occurs.  The
+* user must use XScuGic_Connect() when the interrupt handler takes an
+* argument other than the base address.
+*
+* <b>Nested Interrupts Processing</b>
+*
+* Nested interrupts are not supported by this driver.
+*
+* NOTE:
+* The generic interrupt controller is not a part of the snoop control unit
+* as indicated by the prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a drg  01/19/00 First release
+* 1.01a sdm  11/09/11 The XScuGic and XScuGic_Config structures have changed.
+*		      The HandlerTable (of type XScuGic_VectorTableEntry) is
+*		      moved to XScuGic_Config structure from XScuGic structure.
+*
+*		      The "Config" entry in XScuGic structure is made as
+*		      pointer for better efficiency.
+*
+*		      A new file named as xscugic_hw.c is now added. It is
+*		      to implement low level driver routines without using
+*		      any xscugic instance pointer. They are useful when the
+*		      user wants to use xscugic through device id or
+*		      base address. The driver routines provided are explained
+*		      below.
+*		      XScuGic_DeviceInitialize that takes device id as
+*		      argument and initializes the device (without calling
+*		      XScuGic_CfgInitialize).
+*		      XScuGic_DeviceInterruptHandler that takes device id
+*		      as argument and calls appropriate handlers from the
+*		      HandlerTable.
+*		      XScuGic_RegisterHandler that registers a new handler
+*		      by taking xscugic hardware base address as argument.
+*		      LookupConfigByBaseAddress is used to return the
+*		      corresponding config structure from XScuGic_ConfigTable
+*		      based on the scugic base address passed.
+* 1.02a sdm  12/20/11 Removed AckBeforeService from the XScuGic_Config
+*		      structure.
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
+*		      *_hw.h
+*		      Added APIs
+*			- XScuGic_SetPriTrigTypeByDistAddr()
+*			- XScuGic_GetPriTrigTypeByDistAddr()
+*		      (CR 702687)
+*			Added support to direct interrupts to the appropriate CPU. Earlier
+*			  interrupts were directed to CPU1 (hard coded). Now depending
+*			  upon the CPU selected by the user (xparameters.h), interrupts
+*			  will be directed to the relevant CPU. This fixes CR 699688.
+* 1.04a hk   05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+*			  XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+*			  Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+*             XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+*			  This is fix for CR#705621.
+* 1.05a hk   06/26/13 Modified tcl to export external interrupts correctly to
+*                     xparameters.h. Fix for CR's 690505, 708928 & 719359.
+* 2.0   adk  12/10/13 Updated as per the New Tcl API's
+* 2.1   adk  25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.2   asa  02/29/16 Modified DistributorInit function for Zynq AMP case. The
+*			  distributor is left uninitialized for Zynq AMP. It is assumed
+*             that the distributor will be initialized by Linux master. However
+*             for CortexR5 case, the earlier code is left unchanged where the
+*             the interrupt processor target registers in the distributor is
+*             initialized with the corresponding CPU ID on which the application
+*             built over the scugic driver runs.
+*             These changes fix CR#937243.
+*
+* 3.4   asa  04/07/16 Created a new static function DoDistributorInit to simplify
+*            the flow and avoid code duplication. Changes are made for
+*            USE_AMP use case for R5. In a scenario (in R5 split mode) when
+*            one R5 is operating with A53 in open amp config and other
+*            R5 running baremetal app, the existing code
+*            had the potential to stop the whole AMP solution to work (if
+*            for some reason the R5 running the baremetal app tasked to
+*            initialize the Distributor hangs or crashes before initializing).
+*            Changes are made so that the R5 under AMP first checks if
+*            the distributor is enabled or not and if not, it does the
+*            standard Distributor initialization.
+*            This fixes the CR#952962.
+* 3.6   ms   01/23/17 Modified xil_printf statement in main function for all
+*                     examples to ensure that "Successfully ran" and "Failed"
+*                     strings are available in all examples. This is a fix
+*                     for CR-965028.
+*       kvn  02/17/17 Add support for changing GIC CPU master at run time.
+*       kvn  02/28/17 Make the CpuId as static variable and Added new
+*                     XScugiC_GetCpuId to access CpuId.
+*       ms   03/17/17 Added readme.txt file in examples folder for doxygen
+*                     generation.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XSCUGIC_H /* prevent circular inclusions */
+#define XSCUGIC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xil_io.h"
+#include "xscugic_hw.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+#define EFUSE_STATUS_OFFSET   0x10
+#define EFUSE_STATUS_CPU_MASK 0x80
+
+#if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
+#define ARMA9
+#endif
+/**************************** Type Definitions *******************************/
+
+/* The following data type defines each entry in an interrupt vector table.
+ * The callback reference is the base address of the interrupting device
+ * for the low level driver and an instance pointer for the high level driver.
+ */
+typedef struct
+{
+	Xil_InterruptHandler Handler;
+	void *CallBackRef;
+} XScuGic_VectorTableEntry;
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct
+{
+	u16 DeviceId;		/**< Unique ID  of device */
+	u32 CpuBaseAddress;	/**< CPU Interface Register base address */
+	u32 DistBaseAddress;	/**< Distributor Register base address */
+	XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**<
+				 Vector table of interrupt handlers */
+} XScuGic_Config;
+
+/**
+ * The XScuGic driver instance data. The user is required to allocate a
+ * variable of this type for every intc device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct
+{
+	XScuGic_Config *Config;  /**< Configuration table entry */
+	u32 IsReady;		 /**< Device is initialized and ready */
+	u32 UnhandledInterrupts; /**< Intc Statistics */
+} XScuGic;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Write the given CPU Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be written
+* @param    Data is the 32-bit value to write to the register
+*
+* @return   None.
+*
+* @note
+* C-style signature:
+*    void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \
+					((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given CPU Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be read
+*
+* @return   The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \
+	(XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Distributor Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be written
+* @param    Data is the 32-bit value to write to the register
+*
+* @return   None.
+*
+* @note
+* C-style signature:
+*    void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \
+					((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given Distributor Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be read
+*
+* @return   The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_DistReadReg(InstancePtr, RegOffset) \
+(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset)))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Required functions in xscugic.c
+ */
+
+s32  XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
+			Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id);
+
+void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id);
+void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id);
+
+s32  XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr,
+							u32 EffectiveAddr);
+
+s32  XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id);
+
+void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 *Priority, u8 *Trigger);
+void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 Priority, u8 Trigger);
+void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
+void XScuGic_Stop(XScuGic *InstancePtr);
+void XScuGic_SetCpuID(u32 CpuCoreId);
+u32 XScuGic_GetCpuID(void);
+/*
+ * Initialization functions in xscugic_sinit.c
+ */
+XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId);
+
+/*
+ * Interrupt functions in xscugic_intr.c
+ */
+void XScuGic_InterruptHandler(XScuGic *InstancePtr);
+
+/*
+ * Self-test functions in xscugic_selftest.c
+ */
+s32  XScuGic_SelfTest(XScuGic *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_g.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..e062f1d1f2ed382421b3aff49e115d3e2e87c9a0
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_g.c
@@ -0,0 +1,56 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xscugic.h"
+
+/*
+* The configuration table for devices
+*/
+
+XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_SCUGIC_0_DEVICE_ID,
+		XPAR_PS7_SCUGIC_0_BASEADDR,
+		XPAR_PS7_SCUGIC_0_DIST_BASEADDR
+	}
+};
+
+
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_hw.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_hw.c
new file mode 100644
index 0000000000000000000000000000000000000000..80feb4d113e3c3af16eef16fc33c1b3a18c05cc6
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_hw.c
@@ -0,0 +1,574 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_hw.c
+* @addtogroup scugic_v3_1
+* @{
+*
+* This file contains low-level driver functions that can be used to access the
+* device.  The user should refer to the hardware device specification for more
+* details of the device operation.
+* These routines are used when the user does not want to create an instance of
+* XScuGic structure but still wants to use the ScuGic device. Hence the
+* routines provided here take device id or scugic base address as arguments.
+* Separate static versions of DistInit and CPUInit are provided to implement
+* the low level driver routines.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.01a sdm  07/18/11 First release
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *_hw.c (CR
+*		      702687).
+*					  Added support to direct interrupts to the appropriate CPU.
+*			  Earlier interrupts were directed to CPU1 (hard coded). Now
+*			  depending upon the CPU selected by the user (xparameters.h),
+*			  interrupts will be directed to the relevant CPU.
+*			  This fixes CR 699688.
+* 1.04a hk   05/04/13 Fix for CR#705621. Moved functions
+*			  XScuGic_SetPriTrigTypeByDistAddr and
+*             XScuGic_GetPriTrigTypeByDistAddr here from xscugic.c
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.6   kvn  02/17/17 Add support for changing GIC CPU master at run time.
+*       kvn  02/28/17 Make the CpuId as static variable and Added new
+*                     XScugiC_GetCpuId to access CpuId.
+*
+* </pre>
+*
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+static void DistInit(XScuGic_Config *Config, u32 CpuID);
+static void CPUInit(XScuGic_Config *Config);
+static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+extern XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES];
+extern u32 CpuId;
+
+/*****************************************************************************/
+/**
+*
+* DistInit initializes the distributor of the GIC. The
+* initialization entails:
+*
+* - Write the trigger mode, priority and target CPU
+* - All interrupt sources are disabled
+* - Enable the distributor
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	CpuID is the Cpu ID to be initialized.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void DistInit(XScuGic_Config *Config, u32 CpuID)
+{
+	u32 Int_Id;
+	u32 LocalCpuID = CpuID;
+
+#if USE_AMP==1
+	#warning "Building GIC for AMP"
+
+	/*
+	 * The distrubutor should not be initialized by FreeRTOS in the case of
+	 * AMP -- it is assumed that Linux is the master of this device in that
+	 * case.
+	 */
+	return;
+#endif
+
+	XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, 0U);
+
+	/*
+	 * Set the security domains in the int_security registers for non-secure
+	 * interrupts. All are secure, so leave at the default. Set to 1 for
+	 * non-secure interrupts.
+	 */
+
+
+	/*
+	 * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
+	 */
+
+	/*
+	 * 1. The trigger mode in the int_config register
+	 * Only write to the SPI interrupts, so start at 32
+	 */
+	for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+16U) {
+	/*
+	 * Each INT_ID uses two bits, or 16 INT_ID per register
+	 * Set them all to be level sensitive, active HIGH.
+	 */
+		XScuGic_WriteReg(Config->DistBaseAddress,
+			XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id), 0U);
+	}
+
+
+#define DEFAULT_PRIORITY	0xa0a0a0a0U
+	for (Int_Id = 0U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U) {
+		/*
+		 * 2. The priority using int the priority_level register
+		 * The priority_level and spi_target registers use one byte per
+		 * INT_ID.
+		 * Write a default value that can be changed elsewhere.
+		 */
+		XScuGic_WriteReg(Config->DistBaseAddress,
+				XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+				DEFAULT_PRIORITY);
+	}
+
+	for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U) {
+		/*
+		 * 3. The CPU interface in the spi_target register
+		 * Only write to the SPI interrupts, so start at 32
+		 */
+		LocalCpuID |= LocalCpuID << 8U;
+		LocalCpuID |= LocalCpuID << 16U;
+
+		XScuGic_WriteReg(Config->DistBaseAddress,
+				XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), LocalCpuID);
+	}
+
+	for (Int_Id = 0U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+32U) {
+	/*
+	 * 4. Enable the SPI using the enable_set register. Leave all disabled
+	 * for now.
+	 */
+		XScuGic_WriteReg(Config->DistBaseAddress,
+		XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET,
+		Int_Id),
+		0xFFFFFFFFU);
+
+	}
+
+	XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET,
+						XSCUGIC_EN_INT_MASK);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* CPUInit initializes the CPU Interface of the GIC. The initialization entails:
+*
+* - Set the priority of the CPU.
+* - Enable the CPU interface
+*
+* @param	ConfigPtr is a pointer to a config table for the particular
+*		device this driver is associated with.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void CPUInit(XScuGic_Config *Config)
+{
+	/*
+	 * Program the priority mask of the CPU using the Priority mask
+	 * register
+	 */
+	XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CPU_PRIOR_OFFSET,
+									0xF0U);
+
+	/*
+	 * If the CPU operates in both security domains, set parameters in the
+	 * control_s register.
+	 * 1. Set FIQen=1 to use FIQ for secure interrupts,
+	 * 2. Program the AckCtl bit
+	 * 3. Program the SBPR bit to select the binary pointer behavior
+	 * 4. Set EnableS = 1 to enable secure interrupts
+	 * 5. Set EnbleNS = 1 to enable non secure interrupts
+	 */
+
+	/*
+	 * If the CPU operates only in the secure domain, setup the
+	 * control_s register.
+	 * 1. Set FIQen=1,
+	 * 2. Set EnableS=1, to enable the CPU interface to signal secure .
+	 * interrupts Only enable the IRQ output unless secure interrupts
+	 * are needed.
+	 */
+	XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CONTROL_OFFSET, 0x07U);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* CfgInitialize a specific interrupt controller instance/driver. The
+* initialization entails:
+*
+* - Initialize fields of the XScuGic structure
+* - Initial vector table with stub function calls
+* - All interrupt sources are disabled
+*
+* @param InstancePtr is a pointer to the XScuGic instance to be worked on.
+* @param ConfigPtr is a pointer to a config table for the particular device
+*        this driver is associated with.
+* @param EffectiveAddr is the device base address in the virtual memory address
+*        space. The caller is responsible for keeping the address mapping
+*        from EffectiveAddr to the device physical base address unchanged
+*        once this function is invoked. Unexpected errors may occur if the
+*        address mapping changes after this function is called. If address
+*        translation is not used, use Config->BaseAddress for this parameters,
+*        passing the physical address instead.
+*
+* @return
+*
+* - XST_SUCCESS if initialization was successful
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+s32 XScuGic_DeviceInitialize(u32 DeviceId)
+{
+	XScuGic_Config *Config;
+	u32 Cpu_Id = XScuGic_GetCpuID() + (u32)1;
+
+	Config = &XScuGic_ConfigTable[(u32 )DeviceId];
+
+	DistInit(Config, Cpu_Id);
+
+	CPUInit(Config);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* This function is the primary interrupt handler for the driver.  It must be
+* connected to the interrupt source such that it is called when an interrupt of
+* the interrupt controller is active. It will resolve which interrupts are
+* active and enabled and call the appropriate interrupt handler. It uses
+* the Interrupt Type information to determine when to acknowledge the
+* interrupt.Highest priority interrupts are serviced first.
+*
+* This function assumes that an interrupt vector table has been previously
+* initialized.  It does not verify that entries in the table are valid before
+* calling an interrupt handler.
+*
+* @param	DeviceId is the unique identifier for the ScuGic device.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XScuGic_DeviceInterruptHandler(void *DeviceId)
+{
+
+	u32 InterruptID;
+	u32 IntIDFull;
+	XScuGic_VectorTableEntry *TablePtr;
+	XScuGic_Config *CfgPtr;
+
+	CfgPtr = &XScuGic_ConfigTable[(INTPTR )DeviceId];
+
+	/*
+	 * Read the int_ack register to identify the highest priority
+	 * interrupt ID and make sure it is valid. Reading Int_Ack will
+	 * clear the interrupt in the GIC.
+	 */
+	IntIDFull = XScuGic_ReadReg(CfgPtr->CpuBaseAddress, XSCUGIC_INT_ACK_OFFSET);
+	InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
+	if(XSCUGIC_MAX_NUM_INTR_INPUTS < InterruptID){
+		goto IntrExit;
+	}
+
+	/*
+	 * If the interrupt is shared, do some locking here if there are
+	 * multiple processors.
+	 */
+	/*
+	 * If pre-eption is required:
+	 * Re-enable pre-emption by setting the CPSR I bit for non-secure ,
+	 * interrupts or the F bit for secure interrupts
+	 */
+
+	/*
+	 * If we need to change security domains, issue a SMC instruction here.
+	 */
+
+	/*
+	 * Execute the ISR. Jump into the Interrupt service routine based on
+	 * the IRQSource. A software trigger is cleared by the ACK.
+	 */
+	TablePtr = &(CfgPtr->HandlerTable[InterruptID]);
+	if(TablePtr != NULL) {
+		TablePtr->Handler(TablePtr->CallBackRef);
+	}
+
+IntrExit:
+	/*
+	 * Write to the EOI register, we are all done here.
+	 * Let this function return, the boot code will restore the stack.
+	 */
+	XScuGic_WriteReg(CfgPtr->CpuBaseAddress, XSCUGIC_EOI_OFFSET, IntIDFull);
+
+	/*
+	 * Return from the interrupt. Change security domains could happen
+	 * here.
+	 */
+}
+
+/*****************************************************************************/
+/**
+*
+* Register a handler function for a specific interrupt ID.  The vector table
+* of the interrupt controller is updated, overwriting any previous handler.
+* The handler function will be called when an interrupt occurs for the given
+* interrupt ID.
+*
+* @param	BaseAddress is the CPU Interface Register base address of the
+*		interrupt controller whose vector table will be modified.
+* @param	InterruptId is the interrupt ID to be associated with the input
+*		handler.
+* @param	Handler is the function pointer that will be added to
+*		the vector table for the given interrupt ID.
+* @param	CallBackRef is the argument that will be passed to the new
+*		handler function when it is called. This is user-specific.
+*
+* @return	None.
+*
+* @note
+*
+* Note that this function has no effect if the input base address is invalid.
+*
+******************************************************************************/
+void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
+			     Xil_InterruptHandler IntrHandler, void *CallBackRef)
+{
+	XScuGic_Config *CfgPtr;
+	CfgPtr = LookupConfigByBaseAddress(BaseAddress);
+
+	if(CfgPtr != NULL) {
+		if( IntrHandler != NULL) {
+			CfgPtr->HandlerTable[InterruptID].Handler = IntrHandler;
+		}
+		if( CallBackRef != NULL) {
+			CfgPtr->HandlerTable[InterruptID].CallBackRef = CallBackRef;
+		}
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the CPU interface base address of
+* the device. A table contains the configuration info for each device in the
+* system.
+*
+* @param	CpuBaseAddress is the CPU Interface Register base address.
+*
+* @return 	A pointer to the configuration structure for the specified
+*		device, or NULL if the device was not found.
+*
+* @note		None.
+*
+******************************************************************************/
+static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress)
+{
+	XScuGic_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < XPAR_SCUGIC_NUM_INSTANCES; Index++) {
+		if (XScuGic_ConfigTable[Index].CpuBaseAddress ==
+				CpuBaseAddress) {
+			CfgPtr = &XScuGic_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XScuGic_Config *)CfgPtr;
+}
+
+/****************************************************************************/
+/**
+* Sets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param	BaseAddr is the device base address
+* @param	Int_Id is the IRQ source number to modify
+* @param	Priority is the new priority for the IRQ source. 0 is highest
+* 			priority, 0xF8 (248) is lowest. There are 32 priority levels
+*			supported with a step of 8. Hence the supported priorities are
+*			0, 8, 16, 32, 40 ..., 248.
+* @param	Trigger is the new trigger type for the IRQ source.
+* Each bit pair describes the configuration for an INT_ID.
+* SFI    Read Only    b10 always
+* PPI    Read Only    depending on how the PPIs are configured.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive
+* SPI                LSB is read only.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive/
+*
+* @return	None.
+*
+* @note		This API has the similar functionality of XScuGic_SetPriority
+*	        TriggerType() and should be used when there is no InstancePtr.
+*
+*****************************************************************************/
+void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+					u8 Priority, u8 Trigger)
+{
+	u32 RegValue;
+	u8 LocalPriority = Priority;
+
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(Trigger <= XSCUGIC_INT_CFG_MASK);
+	Xil_AssertVoid(LocalPriority <= XSCUGIC_MAX_INTR_PRIO_VAL);
+
+	/*
+	 * Determine the register to write to using the Int_Id.
+	 */
+	RegValue = XScuGic_ReadReg(DistBaseAddress,
+			XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+	/*
+	 * The priority bits are Bits 7 to 3 in GIC Priority Register. This
+	 * means the number of priority levels supported are 32 and they are
+	 * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
+	 * The lower order 3 bits are masked before putting it in the register.
+	 */
+	LocalPriority = LocalPriority & XSCUGIC_INTR_PRIO_MASK;
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U));
+	RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U);
+
+	/*
+	 * Write the value back to the register.
+	 */
+	XScuGic_WriteReg(DistBaseAddress, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+					RegValue);
+	/*
+	 * Determine the register to write to using the Int_Id.
+	 */
+	RegValue = XScuGic_ReadReg(DistBaseAddress,
+			XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U));
+	RegValue |= (u32)Trigger << ((Int_Id%16U)*2U);
+
+	/*
+	 * Write the value back to the register.
+	 */
+	XScuGic_WriteReg(DistBaseAddress, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+				RegValue);
+}
+
+/****************************************************************************/
+/**
+* Gets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param	BaseAddr is the device base address
+* @param	Int_Id is the IRQ source number to modify
+* @param	Priority is a pointer to the value of the priority of the IRQ
+*		source. This is a return value.
+* @param	Trigger is pointer to the value of the trigger of the IRQ
+*		source. This is a return value.
+*
+* @return	None.
+*
+* @note		This API has the similar functionality of XScuGic_GetPriority
+*	        TriggerType() and should be used when there is no InstancePtr.
+*
+*****************************************************************************/
+void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+					u8 *Priority, u8 *Trigger)
+{
+	u32 RegValue;
+
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(Priority != NULL);
+	Xil_AssertVoid(Trigger != NULL);
+
+	/*
+	 * Determine the register to read to using the Int_Id.
+	 */
+	RegValue = XScuGic_ReadReg(DistBaseAddress,
+	    XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue = RegValue >> ((Int_Id%4U)*8U);
+	*Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
+
+	/*
+	 * Determine the register to read to using the Int_Id.
+	 */
+	RegValue = XScuGic_ReadReg(DistBaseAddress,
+	    XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue = RegValue >> ((Int_Id%16U)*2U);
+
+	*Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..5eaa633e342e275350e1e3faba7d964fffca01d3
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_hw.h
@@ -0,0 +1,642 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_hw.h
+* @addtogroup scugic_v3_1
+* @{
+*
+* This header file contains identifiers and HW access functions (or
+* macros) that can be used to access the device.  The user should refer to the
+* hardware device specification for more details of the device operation.
+* The driver functions/APIs are defined in xscugic.h.
+*
+* This GIC device has two parts, a distributor and CPU interface(s). Each part
+* has separate register definition sections.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 1.01a sdm  11/09/11 "xil_exception.h" added as include.
+*		      Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
+*		      added to enable or disable interrupts based on
+*		      Distributor Register base address. Normally users use
+*		      XScuGic instance and call XScuGic_Enable or
+*		      XScuGic_Disable to enable/disable interrupts. These
+*		      new macros are provided when user does not want to
+*		      use an instance pointer but still wants to enable or
+*		      disable interrupts.
+*		      Function prototypes for functions (present in newly
+*		      added file xscugic_hw.c) are added.
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *_hw.c (CR
+*		      702687).
+* 1.04a hk   05/04/13 Fix for CR#705621. Moved function prototypes
+*		      XScuGic_SetPriTrigTypeByDistAddr and
+*         	      XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
+* 3.0	pkp  12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
+*		      Zynq Ultrascale Mp
+* 3.0   kvn  02/13/14 Modified code for MISRA-C:2012 compliance.
+* 3.2	pkp  11/09/15 Corrected the interrupt processsor target mask value
+*					  for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XSCUGIC_HW_H /* prevent circular inclusions */
+#define XSCUGIC_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The maximum number of interrupts supported by the hardware.
+ */
+#ifdef __ARM_NEON__
+#define XSCUGIC_MAX_NUM_INTR_INPUTS    	95U /* Maximum number of interrupt defined by Zynq */
+#else
+#define XSCUGIC_MAX_NUM_INTR_INPUTS    	195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */
+#endif
+
+/*
+ * The maximum priority value that can be used in the GIC.
+ */
+#define XSCUGIC_MAX_INTR_PRIO_VAL    	248U
+#define XSCUGIC_INTR_PRIO_MASK			0x000000F8U
+
+/** @name Distributor Interface Register Map
+ *
+ * Define the offsets from the base address for all Distributor registers of
+ * the interrupt controller, some registers may be reserved in the hardware
+ * device.
+ * @{
+ */
+#define XSCUGIC_DIST_EN_OFFSET		0x00000000U /**< Distributor Enable
+							Register */
+#define XSCUGIC_IC_TYPE_OFFSET		0x00000004U /**< Interrupt Controller
+							Type Register */
+#define XSCUGIC_DIST_IDENT_OFFSET	0x00000008U /**< Implementor ID
+							Register */
+#define XSCUGIC_SECURITY_OFFSET		0x00000080U /**< Interrupt Security
+							Register */
+#define XSCUGIC_ENABLE_SET_OFFSET	0x00000100U /**< Enable Set
+							Register */
+#define XSCUGIC_DISABLE_OFFSET		0x00000180U /**< Enable Clear Register */
+#define XSCUGIC_PENDING_SET_OFFSET	0x00000200U /**< Pending Set
+							Register */
+#define XSCUGIC_PENDING_CLR_OFFSET	0x00000280U /**< Pending Clear
+							Register */
+#define XSCUGIC_ACTIVE_OFFSET		0x00000300U /**< Active Status Register */
+#define XSCUGIC_PRIORITY_OFFSET		0x00000400U /**< Priority Level Register */
+#define XSCUGIC_SPI_TARGET_OFFSET	0x00000800U /**< SPI Target
+							Register 0x800-0x8FB */
+#define XSCUGIC_INT_CFG_OFFSET		0x00000C00U /**< Interrupt Configuration
+							Register 0xC00-0xCFC */
+#define XSCUGIC_PPI_STAT_OFFSET		0x00000D00U /**< PPI Status Register */
+#define XSCUGIC_SPI_STAT_OFFSET		0x00000D04U /**< SPI Status Register
+							0xd04-0xd7C */
+#define XSCUGIC_AHB_CONFIG_OFFSET	0x00000D80U /**< AHB Configuration
+							Register */
+#define XSCUGIC_SFI_TRIG_OFFSET		0x00000F00U /**< Software Triggered
+							Interrupt Register */
+#define XSCUGIC_PERPHID_OFFSET		0x00000FD0U /**< Peripheral ID Reg */
+#define XSCUGIC_PCELLID_OFFSET		0x00000FF0U /**< Pcell ID Register */
+/* @} */
+
+/** @name  Distributor Enable Register
+ * Controls if the distributor response to external interrupt inputs.
+ * @{
+ */
+#define XSCUGIC_EN_INT_MASK		0x00000001U /**< Interrupt In Enable */
+/* @} */
+
+/** @name  Interrupt Controller Type Register
+ * @{
+ */
+#define XSCUGIC_LSPI_MASK	0x0000F800U /**< Number of Lockable
+						Shared Peripheral
+						Interrupts*/
+#define XSCUGIC_DOMAIN_MASK	0x00000400U /**< Number os Security domains*/
+#define XSCUGIC_CPU_NUM_MASK	0x000000E0U /**< Number of CPU Interfaces */
+#define XSCUGIC_NUM_INT_MASK	0x0000001FU /**< Number of Interrupt IDs */
+/* @} */
+
+/** @name  Implementor ID Register
+ * Implementor and revision information.
+ * @{
+ */
+#define XSCUGIC_REV_MASK	0x00FFF000U /**< Revision Number */
+#define XSCUGIC_IMPL_MASK	0x00000FFFU /**< Implementor */
+/* @} */
+
+/** @name  Interrupt Security Registers
+ * Each bit controls the security level of an interrupt, either secure or non
+ * secure. These registers can only be accessed using secure read and write.
+ * There are registers for each of the CPU interfaces at offset 0x080.  A
+ * register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x084.
+ * @{
+ */
+#define XSCUGIC_INT_NS_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Enable Set Register
+ * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
+ * bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x100. With up
+ * to 8 registers aliased to the same address. A register set for the SPI
+ * interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x104.
+ * @{
+ */
+#define XSCUGIC_INT_EN_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Enable Clear Register
+ * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
+ * sets the corresponding bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x180. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x184.
+ * @{
+ */
+#define XSCUGIC_INT_CLR_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Pending Set Register
+ * Each bit controls the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
+ * an interrupt to the pending state.
+ * There are registers for each of the CPU interfaces at offset 0x200. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x204.
+ * @{
+ */
+#define XSCUGIC_PEND_SET_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Pending Clear Register
+ * Each bit can clear the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
+ * clears the pending state of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x280. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x284.
+ * @{
+ */
+#define XSCUGIC_PEND_CLR_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Active Status Register
+ * Each bit provides the Active status of an interrupt, a
+ * 0 is not Active, a 1 is Active. This is a read only register.
+ * There are registers for each of the CPU interfaces at offset 0x300. With up
+ * to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x380.
+ * @{
+ */
+#define XSCUGIC_ACTIVE_MASK	0x00000001U /**< Each bit corresponds to an
+					      INT_ID */
+/* @} */
+
+/** @name  Priority Level Register
+ * Each byte in a Priority Level Register sets the priority level of an
+ * interrupt. Reading the register provides the priority level of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x400 through
+ * 0x41C. With up to 8 registers aliased to each address.
+ * 0 is highest priority, 0xFF is lowest.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x420.
+ * @{
+ */
+#define XSCUGIC_PRIORITY_MASK	0x000000FFU /**< Each Byte corresponds to an
+						INT_ID */
+#define XSCUGIC_PRIORITY_MAX	0x000000FFU /**< Highest value of a priority
+						actually the lowest priority*/
+/* @} */
+
+/** @name  SPI Target Register 0x800-0x8FB
+ * Each byte references a separate SPI and programs which of the up to 8 CPU
+ * interfaces are sent a Pending interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x800 through
+ * 0x81C. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x820.
+ *
+ * This driver does not support multiple CPU interfaces. These are included
+ * for complete documentation.
+ * @{
+ */
+#define XSCUGIC_SPI_CPU7_MASK	0x00000080U /**< CPU 7 Mask*/
+#define XSCUGIC_SPI_CPU6_MASK	0x00000040U /**< CPU 6 Mask*/
+#define XSCUGIC_SPI_CPU5_MASK	0x00000020U /**< CPU 5 Mask*/
+#define XSCUGIC_SPI_CPU4_MASK	0x00000010U /**< CPU 4 Mask*/
+#define XSCUGIC_SPI_CPU3_MASK	0x00000008U /**< CPU 3 Mask*/
+#define XSCUGIC_SPI_CPU2_MASK	0x00000004U /**< CPU 2 Mask*/
+#define XSCUGIC_SPI_CPU1_MASK	0x00000002U /**< CPU 1 Mask*/
+#define XSCUGIC_SPI_CPU0_MASK	0x00000001U /**< CPU 0 Mask*/
+/* @} */
+
+/** @name  Interrupt Configuration Register 0xC00-0xCFC
+ * The interrupt configuration registers program an SFI to be active HIGH level
+ * sensitive or rising edge sensitive.
+ * Each bit pair describes the configuration for an INT_ID.
+ * SFI    Read Only    b10 always
+ * PPI    Read Only    depending on how the PPIs are configured.
+ *                    b01    Active HIGH level sensitive
+ *                    b11 Rising edge sensitive
+ * SPI                LSB is read only.
+ *                    b01    Active HIGH level sensitive
+ *                    b11 Rising edge sensitive/
+ * There are registers for each of the CPU interfaces at offset 0xC00 through
+ * 0xC04. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0xC08.
+ * @{
+ */
+#define XSCUGIC_INT_CFG_MASK    0x00000003U    /**< */
+/* @} */
+
+/** @name  PPI Status Register
+ * Enables an external AMBA master to access the status of the PPI inputs.
+ * A CPU can only read the status of its local PPI signals and cannot read the
+ * status for other CPUs.
+ * This register is aliased for each CPU interface.
+ * @{
+ */
+#define XSCUGIC_PPI_C15_MASK	0x00008000U    /**< PPI Status */
+#define XSCUGIC_PPI_C14_MASK	0x00004000U    /**< PPI Status */
+#define XSCUGIC_PPI_C13_MASK	0x00002000U    /**< PPI Status */
+#define XSCUGIC_PPI_C12_MASK	0x00001000U    /**< PPI Status */
+#define XSCUGIC_PPI_C11_MASK	0x00000800U    /**< PPI Status */
+#define XSCUGIC_PPI_C10_MASK	0x00000400U    /**< PPI Status */
+#define XSCUGIC_PPI_C09_MASK	0x00000200U    /**< PPI Status */
+#define XSCUGIC_PPI_C08_MASK	0x00000100U    /**< PPI Status */
+#define XSCUGIC_PPI_C07_MASK	0x00000080U    /**< PPI Status */
+#define XSCUGIC_PPI_C06_MASK	0x00000040U    /**< PPI Status */
+#define XSCUGIC_PPI_C05_MASK	0x00000020U    /**< PPI Status */
+#define XSCUGIC_PPI_C04_MASK	0x00000010U    /**< PPI Status */
+#define XSCUGIC_PPI_C03_MASK	0x00000008U    /**< PPI Status */
+#define XSCUGIC_PPI_C02_MASK	0x00000004U    /**< PPI Status */
+#define XSCUGIC_PPI_C01_MASK	0x00000002U    /**< PPI Status */
+#define XSCUGIC_PPI_C00_MASK	0x00000001U    /**< PPI Status */
+/* @} */
+
+/** @name  SPI Status Register 0xd04-0xd7C
+ * Enables an external AMBA master to access the status of the SPI inputs.
+ * There are up to 63 registers if the maximum number of SPI inputs are
+ * configured.
+ * @{
+ */
+#define XSCUGIC_SPI_N_MASK    0x00000001U    /**< Each bit corresponds to an SPI
+					     input */
+/* @} */
+
+/** @name  AHB Configuration Register
+ * Provides the status of the CFGBIGEND input signal and allows the endianess
+ * of the GIC to be set.
+ * @{
+ */
+#define XSCUGIC_AHB_END_MASK       0x00000004U    /**< 0-GIC uses little Endian,
+                                                  1-GIC uses Big Endian */
+#define XSCUGIC_AHB_ENDOVR_MASK    0x00000002U    /**< 0-Uses CFGBIGEND control,
+                                                  1-use the AHB_END bit */
+#define XSCUGIC_AHB_TIE_OFF_MASK   0x00000001U    /**< State of CFGBIGEND */
+
+/* @} */
+
+/** @name  Software Triggered Interrupt Register
+ * Controls issueing of software interrupts.
+ * @{
+ */
+#define XSCUGIC_SFI_SELFTRIG_MASK	0x02010000U
+#define XSCUGIC_SFI_TRIG_TRGFILT_MASK    0x03000000U    /**< Target List filter
+                                                            b00-Use the target List
+                                                            b01-All CPUs except requester
+                                                            b10-To Requester
+                                                            b11-reserved */
+#define XSCUGIC_SFI_TRIG_CPU_MASK	0x00FF0000U    /**< CPU Target list */
+#define XSCUGIC_SFI_TRIG_SATT_MASK	0x00008000U    /**< 0= Use a secure interrupt */
+#define XSCUGIC_SFI_TRIG_INTID_MASK	0x0000000FU    /**< Set to the INTID
+                                                        signaled to the CPU*/
+/* @} */
+
+/** @name CPU Interface Register Map
+ *
+ * Define the offsets from the base address for all CPU registers of the
+ * interrupt controller, some registers may be reserved in the hardware device.
+ * @{
+ */
+#define XSCUGIC_CONTROL_OFFSET		0x00000000U /**< CPU Interface Control
+							Register */
+#define XSCUGIC_CPU_PRIOR_OFFSET	0x00000004U /**< Priority Mask Reg */
+#define XSCUGIC_BIN_PT_OFFSET		0x00000008U /**< Binary Point Register */
+#define XSCUGIC_INT_ACK_OFFSET		0x0000000CU /**< Interrupt ACK Reg */
+#define XSCUGIC_EOI_OFFSET		0x00000010U /**< End of Interrupt Reg */
+#define XSCUGIC_RUN_PRIOR_OFFSET	0x00000014U /**< Running Priority Reg */
+#define XSCUGIC_HI_PEND_OFFSET		0x00000018U /**< Highest Pending Interrupt
+							Register */
+#define XSCUGIC_ALIAS_BIN_PT_OFFSET	0x0000001CU /**< Aliased non-Secure
+						        Binary Point Register */
+
+/**<  0x00000020 to 0x00000FBC are reserved and should not be read or written
+ * to. */
+/* @} */
+
+
+/** @name Control Register
+ * CPU Interface Control register definitions
+ * All bits are defined here although some are not available in the non-secure
+ * mode.
+ * @{
+ */
+#define XSCUGIC_CNTR_SBPR_MASK	0x00000010U    /**< Secure Binary Pointer,
+                                                 0=separate registers,
+                                                 1=both use bin_pt_s */
+#define XSCUGIC_CNTR_FIQEN_MASK	0x00000008U    /**< Use nFIQ_C for secure
+                                                  interrupts,
+                                                  0= use IRQ for both,
+                                                  1=Use FIQ for secure, IRQ for non*/
+#define XSCUGIC_CNTR_ACKCTL_MASK	0x00000004U    /**< Ack control for secure or non secure */
+#define XSCUGIC_CNTR_EN_NS_MASK		0x00000002U    /**< Non Secure enable */
+#define XSCUGIC_CNTR_EN_S_MASK		0x00000001U    /**< Secure enable, 0=Disabled, 1=Enabled */
+/* @} */
+
+/** @name Priority Mask Register
+ * Priority Mask register definitions
+ * The CPU interface does not send interrupt if the level of the interrupt is
+ * lower than the level of the register.
+ * @{
+ */
+/*#define XSCUGIC_PRIORITY_MASK		0x000000FFU*/   /**< All interrupts */
+/* @} */
+
+/** @name Binary Point Register
+ * Binary Point register definitions
+ * @{
+ */
+
+#define XSCUGIC_BIN_PT_MASK	0x00000007U  /**< Binary point mask value
+						Value  Secure  Non-secure
+						b000    0xFE    0xFF
+						b001    0xFC    0xFE
+						b010    0xF8    0xFC
+						b011    0xF0    0xF8
+						b100    0xE0    0xF0
+						b101    0xC0    0xE0
+						b110    0x80    0xC0
+						b111    0x00    0x80
+						*/
+/*@}*/
+
+/** @name Interrupt Acknowledge Register
+ * Interrupt Acknowledge register definitions
+ * Identifies the current Pending interrupt, and the CPU ID for software
+ * interrupts.
+ */
+#define XSCUGIC_ACK_INTID_MASK		0x000003FFU /**< Interrupt ID */
+#define XSCUGIC_CPUID_MASK		0x00000C00U /**< CPU ID */
+/* @} */
+
+/** @name End of Interrupt Register
+ * End of Interrupt register definitions
+ * Allows the CPU to signal the GIC when it completes an interrupt service
+ * routine.
+ */
+#define XSCUGIC_EOI_INTID_MASK		0x000003FFU /**< Interrupt ID */
+
+/* @} */
+
+/** @name Running Priority Register
+ * Running Priority register definitions
+ * Identifies the interrupt priority level of the highest priority active
+ * interrupt.
+ */
+#define XSCUGIC_RUN_PRIORITY_MASK	0x000000FFU    /**< Interrupt Priority */
+/* @} */
+
+/*
+ * Highest Pending Interrupt register definitions
+ * Identifies the interrupt priority of the highest priority pending interupt
+ */
+#define XSCUGIC_PEND_INTID_MASK		0x000003FFU /**< Pending Interrupt ID */
+/*#define XSCUGIC_CPUID_MASK		0x00000C00U */	 /**< CPU ID */
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Configuration Register offset for an interrupt id.
+*
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
+	((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Priority Register offset for an interrupt id.
+*
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
+	((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the SPI Target Register offset for an interrupt id.
+*
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
+	((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Clear-Enable Register offset for an interrupt ID
+*
+* @param	Register is the register offset for the clear/enable bank.
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \
+		((Register) + (((InterruptID)/32U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the given Intc register.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_ReadReg(BaseAddress, RegOffset) \
+	(Xil_In32((BaseAddress) + (RegOffset)))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given Intc register.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note
+* C-style signature:
+*    void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
+	(Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data))))
+
+
+/****************************************************************************/
+/**
+*
+* Enable specific interrupt(s) in the interrupt controller.
+*
+* @param	DistBaseAddress is the Distributor Register base address of the
+*		device
+* @param	Int_Id is the ID of the interrupt source and should be in the
+*		range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id)
+*
+*****************************************************************************/
+#define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \
+	XScuGic_WriteReg((DistBaseAddress), \
+			 XSCUGIC_ENABLE_SET_OFFSET + (((Int_Id) / 32U) * 4U), \
+			 (0x00000001U << ((Int_Id) % 32U)))
+
+/****************************************************************************/
+/**
+*
+* Disable specific interrupt(s) in the interrupt controller.
+*
+* @param	DistBaseAddress is the Distributor Register base address of the
+*		device
+* @param	Int_Id is the ID of the interrupt source and should be in the
+*		range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id)
+*
+*****************************************************************************/
+#define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \
+	XScuGic_WriteReg((DistBaseAddress), \
+			 XSCUGIC_DISABLE_OFFSET + (((Int_Id) / 32U) * 4U), \
+			 (0x00000001U << ((Int_Id) % 32U)))
+
+
+/************************** Function Prototypes ******************************/
+
+void XScuGic_DeviceInterruptHandler(void *DeviceId);
+s32  XScuGic_DeviceInitialize(u32 DeviceId);
+void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
+			     Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+                                        u8 Priority, u8 Trigger);
+void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+					u8 *Priority, u8 *Trigger);
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_intr.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_intr.c
new file mode 100644
index 0000000000000000000000000000000000000000..d05a51c5ec88855ddb9e79e187dee76fea235f99
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_intr.c
@@ -0,0 +1,173 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_intr.c
+* @addtogroup scugic_v3_1
+* @{
+*
+* This file contains the interrupt processing for the driver for the Xilinx
+* Interrupt Controller.  The interrupt processing is partitioned separately such
+* that users are not required to use the provided interrupt processing.  This
+* file requires other files of the driver to be linked in also.
+*
+* The interrupt handler, XScuGic_InterruptHandler, uses an input argument which
+* is an instance pointer to an interrupt controller driver such that multiple
+* interrupt controllers can be supported.  This handler requires the calling
+* function to pass it the appropriate argument, so another level of indirection
+* may be required.
+*
+* The interrupt processing may be used by connecting the interrupt handler to
+* the interrupt system.  The handler does not save and restore the processor
+* context but only handles the processing of the Interrupt Controller. The user
+* is encouraged to supply their own interrupt handler when performance tuning is
+* deemed necessary.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 1.01a sdm  11/09/11 XScuGic_InterruptHandler has changed correspondingly
+*		      since the HandlerTable has now moved to XScuGic_Config.
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* </pre>
+*
+* @internal
+*
+* This driver assumes that the context of the processor has been saved prior to
+* the calling of the Interrupt Controller interrupt handler and then restored
+* after the handler returns. This requires either the running RTOS to save the
+* state of the machine or that a wrapper be used as the destination of the
+* interrupt vector to save the state of the processor and restore the state
+* after the interrupt handler returns.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function is the primary interrupt handler for the driver.  It must be
+* connected to the interrupt source such that it is called when an interrupt of
+* the interrupt controller is active. It will resolve which interrupts are
+* active and enabled and call the appropriate interrupt handler. It uses
+* the Interrupt Type information to determine when to acknowledge the interrupt.
+* Highest priority interrupts are serviced first.
+*
+* This function assumes that an interrupt vector table has been previously
+* initialized.  It does not verify that entries in the table are valid before
+* calling an interrupt handler.
+*
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XScuGic_InterruptHandler(XScuGic *InstancePtr)
+{
+
+	u32 InterruptID;
+	    u32 IntIDFull;
+	    XScuGic_VectorTableEntry *TablePtr;
+
+	    /* Assert that the pointer to the instance is valid
+	     */
+	    Xil_AssertVoid(InstancePtr != NULL);
+
+	    /*
+	     * Read the int_ack register to identify the highest priority interrupt ID
+	     * and make sure it is valid. Reading Int_Ack will clear the interrupt
+	     * in the GIC.
+	     */
+	    IntIDFull = XScuGic_CPUReadReg(InstancePtr, XSCUGIC_INT_ACK_OFFSET);
+	    InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
+
+	    if(XSCUGIC_MAX_NUM_INTR_INPUTS < InterruptID){
+		goto IntrExit;
+	    }
+
+	    /*
+	     * If the interrupt is shared, do some locking here if there are multiple
+	     * processors.
+	     */
+	    /*
+	     * If pre-eption is required:
+	     * Re-enable pre-emption by setting the CPSR I bit for non-secure ,
+	     * interrupts or the F bit for secure interrupts
+	     */
+
+	    /*
+	     * If we need to change security domains, issue a SMC instruction here.
+	     */
+
+	    /*
+	     * Execute the ISR. Jump into the Interrupt service routine based on the
+	     * IRQSource. A software trigger is cleared by the ACK.
+	     */
+	    TablePtr = &(InstancePtr->Config->HandlerTable[InterruptID]);
+		if(TablePtr != NULL) {
+	        TablePtr->Handler(TablePtr->CallBackRef);
+		}
+
+	IntrExit:
+	    /*
+	     * Write to the EOI register, we are all done here.
+	     * Let this function return, the boot code will restore the stack.
+	     */
+	    XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_EOI_OFFSET, IntIDFull);
+
+	    /*
+	     * Return from the interrupt. Change security domains could happen here.
+     */
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_selftest.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_selftest.c
new file mode 100644
index 0000000000000000000000000000000000000000..47620d6445c2c543807433f3be9d85d7b4252af3
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_selftest.c
@@ -0,0 +1,115 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_selftest.c
+* @addtogroup scugic_v3_1
+* @{
+*
+* Contains diagnostic self-test functions for the XScuGic driver.
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+#define	XSCUGIC_PCELL_ID	0xB105F00DU
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Run a self-test on the driver/device. This test reads the ID registers and
+* compares them.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+*
+* @return
+*
+* 		- XST_SUCCESS if self-test is successful.
+* 		- XST_FAILURE if the self-test is not successful.
+*
+* @note		None.
+*
+******************************************************************************/
+s32  XScuGic_SelfTest(XScuGic *InstancePtr)
+{
+	u32 RegValue1 = 0U;
+	u32 Index;
+	s32 Status;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the ID registers.
+	 */
+	for(Index=0U; Index<=3U; Index++) {
+		RegValue1 |= XScuGic_DistReadReg(InstancePtr,
+			((u32)XSCUGIC_PCELLID_OFFSET + (Index * 4U))) << (Index * 8U);
+	}
+
+	if(XSCUGIC_PCELL_ID != RegValue1){
+		Status = XST_FAILURE;
+	} else {
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_sinit.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..d30390ab826c6afa58db94ceb515ec6386033857
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scugic_v3_6/src/xscugic_sinit.c
@@ -0,0 +1,103 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_sinit.c
+* @addtogroup scugic_v3_1
+* @{
+*
+* Contains static init functions for the XScuGic driver for the Interrupt
+* Controller. See xscugic.h for a detailed description of the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- --------------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xparameters.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+extern XScuGic_Config XScuGic_ConfigTable[XPAR_SCUGIC_NUM_INSTANCES];
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId is the unique identifier for a device.
+*
+* @return	A pointer to the XScuGic configuration structure for the
+*		specified device, or NULL if the device was not found.
+*
+* @note		None.
+*
+******************************************************************************/
+XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId)
+{
+	XScuGic_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index=0U; Index < (u32)XPAR_SCUGIC_NUM_INSTANCES; Index++) {
+		if (XScuGic_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XScuGic_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XScuGic_Config *)CfgPtr;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/Makefile b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..7c673d4b6e3ac3a30f3e0f580e2f15a54d3dc33e
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner scutimer_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling scutimer"
+
+scutimer_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: scutimer_includes
+
+scutimer_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.c
new file mode 100644
index 0000000000000000000000000000000000000000..9d477d971eac89fe821b93f90e85ca9565a44965
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.c
@@ -0,0 +1,286 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer.c
+* @addtogroup scutimer_v2_1
+* @{
+*
+* Contains the implementation of interface functions of the SCU Timer driver.
+* See xscutimer.h for a description of the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm  03/10/10 First release
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscutimer.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Initialize a specific timer instance/driver. This function  must be called
+* before other functions of the driver are called.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+* @param	ConfigPtr points to the XScuTimer configuration structure.
+* @param	EffectiveAddress is the base address for the device. It could be
+*		a virtual address if address translation is supported in the
+*		system, otherwise it is the physical address.
+*
+* @return
+*		- XST_SUCCESS if initialization was successful.
+*		- XST_DEVICE_IS_STARTED if the device has already been started.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
+			 XScuTimer_Config *ConfigPtr, u32 EffectiveAddress)
+{
+	s32 Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * If the device is started, disallow the initialize and return a
+	 * status indicating it is started. This allows the user to stop the
+	 * device and reinitialize, but prevents a user from inadvertently
+	 * initializing.
+	 */
+	if (InstancePtr->IsStarted != XIL_COMPONENT_IS_STARTED) {
+		/*
+		 * Copy configuration into the instance structure.
+		 */
+		InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+
+		/*
+		 * Save the base address pointer such that the registers of the block
+		 * can be accessed and indicate it has not been started yet.
+		 */
+		InstancePtr->Config.BaseAddr = EffectiveAddress;
+
+		InstancePtr->IsStarted = (u32)0;
+
+		/*
+		 * Indicate the instance is ready to use, successfully initialized.
+		 */
+		InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+		Status =(s32)XST_SUCCESS;
+	}
+	else {
+		Status = (s32)XST_DEVICE_IS_STARTED;
+	}
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Start the timer.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XScuTimer_Start(XScuTimer *InstancePtr)
+{
+	u32 Register;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the contents of the Control register.
+	 */
+	Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+				  XSCUTIMER_CONTROL_OFFSET);
+
+	/*
+	 * Set the 'timer enable' bit in the register.
+	 */
+	Register |= XSCUTIMER_CONTROL_ENABLE_MASK;
+
+	/*
+	 * Update the Control register with the new value.
+	 */
+	XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+			XSCUTIMER_CONTROL_OFFSET, Register);
+
+	/*
+	 * Indicate that the device is started.
+	 */
+	InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
+}
+
+/****************************************************************************/
+/**
+*
+* Stop the timer.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XScuTimer_Stop(XScuTimer *InstancePtr)
+{
+	u32 Register;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the contents of the Control register.
+	 */
+	Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+				  XSCUTIMER_CONTROL_OFFSET);
+
+	/*
+	 * Clear the 'timer enable' bit in the register.
+	 */
+	Register &= (u32)(~XSCUTIMER_CONTROL_ENABLE_MASK);
+
+	/*
+	 * Update the Control register with the new value.
+	 */
+	XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+			XSCUTIMER_CONTROL_OFFSET, Register);
+
+	/*
+	 * Indicate that the device is stopped.
+	 */
+	InstancePtr->IsStarted = (u32)0;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the prescaler bits in the timer control register.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+* @param	PrescalerValue is a 8 bit value that sets the prescaler to use.
+*
+* @return	None
+*
+* @note		None
+*
+****************************************************************************/
+void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue)
+{
+	u32 ControlReg;
+
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	/*
+	 * Read the Timer control register.
+	 */
+	ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+					XSCUTIMER_CONTROL_OFFSET);
+
+	/*
+	 * Clear all of the prescaler control bits in the register.
+	 */
+	ControlReg &= (u32)(~XSCUTIMER_CONTROL_PRESCALER_MASK);
+
+	/*
+	 * Set the prescaler value.
+	 */
+	ControlReg |= (((u32)PrescalerValue) << XSCUTIMER_CONTROL_PRESCALER_SHIFT);
+
+	/*
+	 * Write the register with the new values.
+	 */
+	XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+			  XSCUTIMER_CONTROL_OFFSET, ControlReg);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function returns the current prescaler value.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	The prescaler value.
+*
+* @note		None.
+*
+****************************************************************************/
+u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr)
+{
+	u32 ControlReg;
+
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Timer control register.
+	 */
+	ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+				    XSCUTIMER_CONTROL_OFFSET);
+	ControlReg &= XSCUTIMER_CONTROL_PRESCALER_MASK;
+
+	return (u8)(ControlReg >> XSCUTIMER_CONTROL_PRESCALER_SHIFT);
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h
new file mode 100644
index 0000000000000000000000000000000000000000..ea4ba79de086a74eb57b0ab5c22fe3441ee3ce1e
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h
@@ -0,0 +1,368 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer.h
+* @addtogroup scutimer_v2_1
+* @{
+* @details
+*
+* The timer driver supports the Cortex A9 private timer.
+*
+* The timer driver supports the following features:
+* - Normal mode and Auto reload mode
+* - Interrupts (Interrupt handler is not provided in this driver. Application
+* 		has to register it's own handler)
+*
+* <b> Initialization and Configuration </b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Timer.
+*
+* XScuTimer_CfgInitialize() API is used to initialize the Timer. The
+* user needs to first call the XScuTimer_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to
+* the XScuTimer_CfgInitialize() API.
+*
+* <b> Interrupts </b>
+*
+* The Timer hardware supports interrupts.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* Timer in interrupt mode.
+*
+* <b> Virtual Memory </b>
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+* <b> Threads </b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* <b> Asserts </b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* <b> Building the driver </b>
+*
+* The XScuTimer driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* <br><br>
+*
+* NOTE:
+* The timer is not a part of the snoop control unit as indicated by the
+* prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm  03/10/10 First release
+* 1.02a sg  07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+*                    generation.
+* </pre>
+*
+******************************************************************************/
+#ifndef XSCUTIMER_H		/* prevent circular inclusions */
+#define XSCUTIMER_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xscutimer_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;	/**< Unique ID of device */
+	u32 BaseAddr;	/**< Base address of the device */
+} XScuTimer_Config;
+
+/**
+ * The XScuTimer driver instance data. The user is required to allocate a
+ * variable of this type for every timer device in the system.
+ * A pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+	XScuTimer_Config Config; /**< Hardware Configuration */
+	u32 IsReady;		/**< Device is initialized and ready */
+	u32 IsStarted;		/**< Device timer is running */
+} XScuTimer;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Check if the timer has expired.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return
+*		- TRUE if the timer has expired.
+*		- FALSE if the timer has not expired.
+*
+* @note		C-style signature:
+*		int XScuTimer_IsExpired(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_IsExpired(InstancePtr) \
+	((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+				XSCUTIMER_ISR_OFFSET) & \
+				XSCUTIMER_ISR_EVENT_FLAG_MASK) == \
+				XSCUTIMER_ISR_EVENT_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* Re-start the timer. This macro will read the timer load register
+* and writes the same value to load register to update the counter register.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_RestartTimer(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_RestartTimer(InstancePtr)				\
+	XScuTimer_LoadTimer((InstancePtr),				\
+		XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+					XSCUTIMER_LOAD_OFFSET))
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+* @param	Value is the count to be loaded in to the load register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_LoadTimer(XScuTimer *InstancePtr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_LoadTimer(InstancePtr, Value)				\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value. It can be called at any
+* time.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	Contents of the timer counter register.
+*
+* @note		C-style signature:
+		u32 XScuTimer_GetCounterValue(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_GetCounterValue(InstancePtr)				\
+	XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,		\
+				XSCUTIMER_COUNTER_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Enable auto-reload mode.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_EnableAutoReload(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_EnableAutoReload(InstancePtr)				\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_CONTROL_OFFSET,			\
+			(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+				XSCUTIMER_CONTROL_OFFSET) |		 \
+				XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable auto-reload mode.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_DisableAutoReload(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_DisableAutoReload(InstancePtr)			\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_CONTROL_OFFSET,			\
+			(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+				XSCUTIMER_CONTROL_OFFSET) &		\
+				~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Enable the Timer interrupt.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_EnableInterrupt(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_EnableInterrupt(InstancePtr)				\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_CONTROL_OFFSET,			\
+			(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+					XSCUTIMER_CONTROL_OFFSET) |	\
+					XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable the Timer interrupt.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_DisableInterrupt(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_DisableInterrupt(InstancePtr)				\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_CONTROL_OFFSET,			\
+			(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+				XSCUTIMER_CONTROL_OFFSET) &		\
+				~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)))
+
+/*****************************************************************************/
+/**
+*
+* This function reads the interrupt status.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_GetInterruptStatus(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_GetInterruptStatus(InstancePtr)			\
+	XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_ISR_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears the interrupt status.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_ClearInterruptStatus(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_ClearInterruptStatus(InstancePtr)			\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+		XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xscutimer_sinit.c
+ */
+XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xscutimer_selftest.c
+ */
+s32 XScuTimer_SelfTest(XScuTimer *InstancePtr);
+
+/*
+ * Interface functions in xscutimer.c
+ */
+s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
+			    XScuTimer_Config *ConfigPtr, u32 EffectiveAddress);
+void XScuTimer_Start(XScuTimer *InstancePtr);
+void XScuTimer_Stop(XScuTimer *InstancePtr);
+void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue);
+u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..9d81780fcba4ee16ff6aadc5601871acd3743a9b
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xscutimer.h"
+
+/*
+* The configuration table for devices
+*/
+
+XScuTimer_Config XScuTimer_ConfigTable[XPAR_XSCUTIMER_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_SCUTIMER_0_DEVICE_ID,
+		XPAR_PS7_SCUTIMER_0_BASEADDR
+	}
+};
+
+
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..ac7b42934796aa41e49adfc510057e951e0b2e0d
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_hw.h
@@ -0,0 +1,287 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer_hw.h
+* @addtogroup scutimer_v2_1
+* @{
+*
+* This file contains the hardware interface to the Timer.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm  03/10/10 First release
+* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control
+*		     and interrupt registers
+* 1.02a  sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+#ifndef XSCUTIMER_HW_H		/* prevent circular inclusions */
+#define XSCUTIMER_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device
+ * @{
+ */
+
+#define XSCUTIMER_LOAD_OFFSET		0x00U /**< Timer Load Register */
+#define XSCUTIMER_COUNTER_OFFSET	0x04U /**< Timer Counter Register */
+#define XSCUTIMER_CONTROL_OFFSET	0x08U /**< Timer Control Register */
+#define XSCUTIMER_ISR_OFFSET		0x0CU /**< Timer Interrupt
+						  Status Register */
+/* @} */
+
+/** @name Timer Control register
+ * This register bits control the prescaler, Intr enable,
+ * auto-reload and timer enable.
+ * @{
+ */
+
+#define XSCUTIMER_CONTROL_PRESCALER_MASK	0x0000FF00U /**< Prescaler */
+#define XSCUTIMER_CONTROL_PRESCALER_SHIFT	8U
+#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK	0x00000004U /**< Intr enable */
+#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK	0x00000002U /**< Auto-reload */
+#define XSCUTIMER_CONTROL_ENABLE_MASK		0x00000001U /**< Timer enable */
+/* @} */
+
+/** @name Interrupt Status register
+ * This register indicates the Timer counter register has reached zero.
+ * @{
+ */
+
+#define XSCUTIMER_ISR_EVENT_FLAG_MASK		0x00000001U /**< Event flag */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+* @param	Value is the count to be loaded in to the load register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetLoadReg(BaseAddr, Value)				\
+	XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer load register value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+*
+* @return	Contents of the timer load register.
+*
+* @note		C-style signature:
+*		u32 XScuTimer_GetLoadReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetLoadReg(BaseAddr)					\
+	XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer counter register.
+*
+* @param	BaseAddr is the base address of the scu timer.
+* @param	Value is the count to be loaded in to the counter register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetCounterReg(BaseAddr, Value)			\
+	XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+*
+* @return	Contents of the timer counter register.
+*
+* @note		C-style signature:
+		u32 XScuTimer_GetCounterReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetCounterReg(BaseAddr)				\
+	XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+* @param	Value is the count to be loaded in to the load register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetControlReg(BaseAddr, Value)			\
+	XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer load register value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+*
+* @return	Contents of the timer load register.
+*
+* @note		C-style signature:
+		u32 XScuTimer_GetControlReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetControlReg(BaseAddr)				\
+	XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer counter register.
+*
+* @param	BaseAddr is the base address of the scu timer.
+* @param	Value is the count to be loaded in to the counter register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetIntrReg(BaseAddr, Value)				\
+	XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+*
+* @return	Contents of the timer counter register.
+*
+* @note		C-style signature:
+		u32 XScuTimer_GetIntrReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetIntrReg(BaseAddr)					\
+	XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Read from the given Timer register.
+*
+* @param	BaseAddr is the base address of the device
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note		C-style signature:
+*		u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuTimer_ReadReg(BaseAddr, RegOffset)		\
+	Xil_In32((BaseAddr) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write to the given Timer register.
+*
+* @param	BaseAddr is the base address of the device
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data)	\
+	Xil_Out32((BaseAddr) + (RegOffset), (Data))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_selftest.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_selftest.c
new file mode 100644
index 0000000000000000000000000000000000000000..6e37fef3bb77005e3111e97a5b15830ce42d30e0
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_selftest.c
@@ -0,0 +1,139 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer_selftest.c
+* @addtogroup scutimer_v2_1
+* @{
+*
+* Contains diagnostic self-test functions for the XScuTimer driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm  03/10/10 First release
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscutimer.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XSCUTIMER_SELFTEST_VALUE	0xA55AF00FU
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Run a self-test on the timer. This test clears the timer enable bit in
+* the control register, writes to the timer load register and verifies the
+* value read back matches the value written and restores the control register
+* and the timer load register.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return
+*		- XST_SUCCESS if self-test was successful.
+*		- XST_FAILURE if self test was not successful.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XScuTimer_SelfTest(XScuTimer *InstancePtr)
+{
+	u32 Register;
+	u32 CtrlOrig;
+	u32 LoadOrig;
+	s32 Status;
+
+	/*
+	 * Assert to ensure the inputs are valid and the instance has been
+	 * initialized.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Save the contents of the Control Register and stop the timer.
+	 */
+	CtrlOrig = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+				  XSCUTIMER_CONTROL_OFFSET);
+	Register = CtrlOrig & (u32)(~XSCUTIMER_CONTROL_ENABLE_MASK);
+	XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+			XSCUTIMER_CONTROL_OFFSET, Register);
+
+	/*
+	 * Save the contents of the Load Register.
+	 * Load a new test value in the Load Register, read it back and
+	 * compare it with the written value.
+	 */
+	LoadOrig = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,
+				  XSCUTIMER_LOAD_OFFSET);
+	XScuTimer_LoadTimer(InstancePtr, XSCUTIMER_SELFTEST_VALUE);
+	Register = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,
+				  XSCUTIMER_LOAD_OFFSET);
+
+	/*
+	 * Restore the contents of the Load Register and Control Register.
+	 */
+	XScuTimer_LoadTimer(InstancePtr, LoadOrig);
+	XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+			XSCUTIMER_CONTROL_OFFSET, CtrlOrig);
+
+	/*
+	 * Return a Failure if the contents of the Load Register do not
+	 * match with the value written to it.
+	 */
+	if (Register != XSCUTIMER_SELFTEST_VALUE) {
+		Status = (s32)XST_FAILURE;
+	}
+	else {
+		Status = (s32)XST_SUCCESS;
+	}
+
+	return Status;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_sinit.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..3bcc57ebde32600b754f7a01d71ece0fb0eecbdb
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_sinit.c
@@ -0,0 +1,96 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscutimer_sinit.c
+* @addtogroup scutimer_v2_1
+* @{
+*
+* This file contains method for static initialization (compile-time) of the
+* driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm  03/10/10 First release
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscutimer.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions ****************************/
+extern XScuTimer_Config XScuTimer_ConfigTable[XPAR_XSCUTIMER_NUM_INSTANCES];
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId is the unique device ID of the device being looked up.
+*
+* @return	A pointer to the configuration table entry corresponding to the
+*		given device ID, or NULL if no match is found.
+*
+* @note		None.
+*
+******************************************************************************/
+XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId)
+{
+	XScuTimer_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < XPAR_XSCUTIMER_NUM_INSTANCES; Index++) {
+		if (XScuTimer_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XScuTimer_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XScuTimer_Config *)CfgPtr;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/Makefile b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..493ad9a4e8e87a236832a0e1875ad594931b2647
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner scuwdt_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling scuwdt"
+
+scuwdt_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: scuwdt_includes
+
+scuwdt_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c
new file mode 100644
index 0000000000000000000000000000000000000000..8e9788551e9b97e1999909edf1192887ac4aba55
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c
@@ -0,0 +1,218 @@
+/* $Id: xscuwdt.c,v 1.1.2.1 2011/01/20 04:04:40 sadanan Exp $ */
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt.c
+* @addtogroup scuwdt_v2_1
+* @{
+*
+* Contains the implementation of interface functions of the XScuWdt driver.
+* See xscuwdt.h for a description of the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscuwdt.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Initialize a specific watchdog timer instance/driver. This function
+* must be called before other functions of the driver are called.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+* @param	ConfigPtr is the config structure.
+* @param	EffectiveAddress is the base address for the device. It could be
+*		a virtual address if address translation is supported in the
+*		system, otherwise it is the physical address.
+*
+* @return
+*		- XST_SUCCESS if initialization was successful.
+*		- XST_DEVICE_IS_STARTED if the device has already been started.
+*
+* @note		This function enables the watchdog mode.
+*
+******************************************************************************/
+s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
+			 XScuWdt_Config *ConfigPtr, u32 EffectiveAddress)
+{
+	s32 CfgStatus;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+	Xil_AssertNonvoid(EffectiveAddress != 0x00U);
+
+	/*
+	 * If the device is started, disallow the initialize and return a
+	 * status indicating it is started. This allows the user to stop the
+	 * device and reinitialize, but prevents a user from inadvertently
+	 * initializing.
+	 */
+	if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
+		CfgStatus = (s32)XST_DEVICE_IS_STARTED;
+	}
+	else {
+		/*
+		 * Copy configuration into instance.
+		 */
+		InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+
+		/*
+		 * Save the base address pointer such that the registers of the block
+		 * can be accessed and indicate it has not been started yet.
+		 */
+		InstancePtr->Config.BaseAddr = EffectiveAddress;
+		InstancePtr->IsStarted = 0U;
+
+		/*
+		 * Put the watchdog timer in Watchdog mode.
+		 */
+		XScuWdt_SetWdMode(InstancePtr);
+
+		/*
+		 * Indicate the instance is ready to use, successfully initialized.
+		 */
+		InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+		CfgStatus =(s32)XST_SUCCESS;
+	}
+	return CfgStatus;
+}
+
+/****************************************************************************/
+/**
+*
+* Start the watchdog counter of the device.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	None.
+*
+* @note		User needs to select the appropriate mode (watchdog/timer)
+*		before using this API.
+*		See XScuWdt_SetWdMode/XScuWdt_SetTimerMode macros in
+*		xscuwdt.h.
+*
+******************************************************************************/
+void XScuWdt_Start(XScuWdt *InstancePtr)
+{
+	u32 Register;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the contents of the Control register.
+	 */
+	Register = XScuWdt_ReadReg(InstancePtr->Config.BaseAddr,
+				  XSCUWDT_CONTROL_OFFSET);
+
+	/*
+	 * Set the 'watchdog enable' bit in the register.
+	 */
+	Register |= XSCUWDT_CONTROL_WD_ENABLE_MASK;
+
+	/*
+	 * Update the Control register with the new value.
+	 */
+	XScuWdt_WriteReg(InstancePtr->Config.BaseAddr,
+			XSCUWDT_CONTROL_OFFSET, Register);
+
+	/*
+	 * Indicate that the device is started.
+	 */
+	InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
+}
+
+/****************************************************************************/
+/**
+*
+* Stop the watchdog timer.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XScuWdt_Stop(XScuWdt *InstancePtr)
+{
+	u32 Register;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the contents of the Control register.
+	 */
+	Register = XScuWdt_ReadReg(InstancePtr->Config.BaseAddr,
+				  XSCUWDT_CONTROL_OFFSET);
+
+	/*
+	 * Clear the 'watchdog enable' bit in the register.
+	 */
+	Register &= (u32)(~XSCUWDT_CONTROL_WD_ENABLE_MASK);
+
+	/*
+	 * Update the Control register with the new value.
+	 */
+	XScuWdt_WriteReg(InstancePtr->Config.BaseAddr,
+			XSCUWDT_CONTROL_OFFSET, Register);
+
+	/*
+	 * Indicate that the device is stopped.
+	 */
+	InstancePtr->IsStarted = 0U;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h
new file mode 100644
index 0000000000000000000000000000000000000000..372bbc3439aadbb94cf3fe04b97535757d4d1107
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h
@@ -0,0 +1,383 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt.h
+* @addtogroup scuwdt_v2_1
+* @{
+* @details
+*
+* The Xilinx SCU watchdog timer driver (XScuWdt) supports the Xilinx SCU private
+* watchdog timer hardware.
+*
+* The XScuWdt driver supports the following features:
+* - Watchdog mode
+* - Timer mode
+* - Auto reload (timer mode only)
+*
+* The watchdog counter register is a down counter and starts decrementing when
+* the watchdog is started.
+* In watchdog mode, when the counter reaches 0, the Reset flag is set in the
+* Reset status register and the WDRESETREQ pin is asserted, causing a system
+* reset. The Reset flag is not reset by normal processor reset and is cleared
+* when written with a value of 1. This enables the user to differentiate a
+* normal reset and a reset caused by watchdog time-out. The user needs to call
+* XScuWdt_RestartWdt() periodically, to avoid the watchdog from being timed-out.
+*
+* The IsWdtExpired function can be used to check if the watchdog was the cause
+* of the last reset. In this situation, call Initialize then call IsWdtExpired.
+* If the result is true, watchdog timeout caused the last system reset. The
+* application then needs to clear the Reset flag.
+*
+* In timer mode, when the counter reaches 0, the Event flag is set in the
+* Interrupt status register and if interrupts are enabled, interrupt ID 30 is
+* set as pending in the interrupt distributor. The IsTimerExpired function
+* is used to check if the watchdog counter has decremented to 0 in timer mode.
+* If auto-reload mode is enabled, the Counter register is automatically reloaded
+* from the Load register.
+*
+* <b> Initialization and Configuration </b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Watchdog Timer.
+*
+* XScuWdt_CfgInitialize() API is used to initialize the Watchdog Timer. The
+* user needs to first call the XScuWdt_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to
+* the XScuWdt_CfgInitialize() API.
+*
+* <b>Interrupts</b>
+*
+* The SCU Watchdog Timer supports interrupts in Timer mode.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* Timer in interrupt mode.
+*
+* <b> Virtual Memory </b>
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+* <b> Threads </b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* <b> Asserts </b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* <b> Building the driver </b>
+*
+* The XScuWdt driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* <br><br>
+*
+* NOTE:
+* The watchdog timer is not a part of the snoop control unit as indicated
+* by the prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.02a  sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+*                    generation.
+* </pre>
+*
+******************************************************************************/
+#ifndef XSCUWDT_H		/* prevent circular inclusions */
+#define XSCUWDT_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xscuwdt_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID of device */
+	u32 BaseAddr;		/**< Base address of the device */
+} XScuWdt_Config;
+
+/**
+ * The XScuWdt driver instance data. The user is required to allocate a
+ * variable of this type for every watchdog/timer device in the system.
+ * A pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+	XScuWdt_Config Config;/**< Hardware Configuration */
+	u32 IsReady;		/**< Device is initialized and ready */
+	u32 IsStarted;		/**< Device watchdog timer is running */
+} XScuWdt;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/****************************************************************************/
+/**
+*
+* This function is used to check if the watchdog has timed-out and the last
+* reset was caused by the watchdog reset.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+*		- TRUE if the watchdog has expired.
+*		- FALSE if the watchdog has not expired.
+*
+* @note		C-style signature:
+*		int XScuWdt_IsWdtExpired(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_IsWdtExpired(InstancePtr)				\
+	((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,		\
+			  XSCUWDT_RST_STS_OFFSET) &			\
+	 XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* This function is used to check if the watchdog counter has reached 0 in timer
+* mode.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+*		- TRUE if the watchdog has expired.
+*		- FALSE if the watchdog has not expired.
+*
+* @note		C-style signature:
+*		int XScuWdt_IsTimerExpired(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_IsTimerExpired(InstancePtr)				\
+	((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,		\
+			  XSCUWDT_ISR_OFFSET) &				\
+	 XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* Re-start the watchdog timer. This macro will read the watchdog load register
+* and write the same value to load register to update the counter register.
+* An application needs to call this function periodically to keep the watchdog
+* from asserting the WDRESETREQ reset request output pin.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_RestartWdt(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_RestartWdt(InstancePtr)					 \
+	XScuWdt_LoadWdt((InstancePtr),					 \
+			(XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+					 XSCUWDT_LOAD_OFFSET)))
+
+/****************************************************************************/
+/**
+*
+* Write to the watchdog timer load register. This will also update the
+* watchdog counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+* @param	Value is the value to be written to the Watchdog Load register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_LoadWdt(XScuWdt *InstancePtr, u32 Value)
+*
+******************************************************************************/
+#define XScuWdt_LoadWdt(InstancePtr, Value)				\
+	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUWDT_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Put the watchdog timer in Watchdog mode by setting the WD mode bit of the
+* Watchdog control register.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_SetWdMode(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_SetWdMode(InstancePtr)					  \
+	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		  \
+			 XSCUWDT_CONTROL_OFFSET,			  \
+			 (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+			  XSCUWDT_CONTROL_OFFSET) |			  \
+			  (XSCUWDT_CONTROL_WD_MODE_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Put the watchdog timer in Timer mode by writing 0x12345678 and 0x87654321
+* successively to the Watchdog Disable Register.
+* The software must write 0x12345678 and 0x87654321 successively to the
+* Watchdog Disable Register so that the watchdog mode bit in the Watchdog
+* Control Register is set to zero.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_SetTimerMode(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_SetTimerMode(InstancePtr)				\
+{									\
+	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUWDT_DISABLE_OFFSET,				\
+			XSCUWDT_DISABLE_VALUE1);			\
+	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUWDT_DISABLE_OFFSET,				\
+			XSCUWDT_DISABLE_VALUE2);			\
+}
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the watchdog control register.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	Contents of the watchdog control register.
+*
+* @note		C-style signature:
+		u32 XScuWdt_GetControlReg(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_GetControlReg(InstancePtr)				\
+	XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,			\
+			XSCUWDT_CONTROL_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the watchdog control register.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+* @param	ControlReg is the value to be written to the watchdog control
+*		register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+		void XScuWdt_SetControlReg(XScuWdt *InstancePtr, u32 ControlReg)
+*
+******************************************************************************/
+#define XScuWdt_SetControlReg(InstancePtr, ControlReg)			\
+	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			 XSCUWDT_CONTROL_OFFSET, (ControlReg))
+
+/****************************************************************************/
+/**
+*
+* Enable auto-reload mode.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_EnableAutoReload(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_EnableAutoReload(InstancePtr)				\
+	XScuWdt_SetControlReg((InstancePtr),				\
+			      (XScuWdt_GetControlReg(InstancePtr) |	\
+			      XSCUWDT_CONTROL_AUTO_RELOAD_MASK))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xscuwdt_sinit.c.
+ */
+XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xscuwdt_selftest.c
+ */
+s32 XScuWdt_SelfTest(XScuWdt *InstancePtr);
+
+/*
+ * Interface functions in xscuwdt.c
+ */
+s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
+			  XScuWdt_Config *ConfigPtr, u32 EffectiveAddress);
+
+void XScuWdt_Start(XScuWdt *InstancePtr);
+
+void XScuWdt_Stop(XScuWdt *InstancePtr);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..ba21a50bfac022b18a7da20765e8a1391e067e91
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xscuwdt.h"
+
+/*
+* The configuration table for devices
+*/
+
+XScuWdt_Config XScuWdt_ConfigTable[XPAR_XSCUWDT_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_SCUWDT_0_DEVICE_ID,
+		XPAR_PS7_SCUWDT_0_BASEADDR
+	}
+};
+
+
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..2067d3a531870de0fe1851b65a2f653f58aa73f8
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_hw.h
@@ -0,0 +1,182 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt_hw.h
+* @addtogroup scuwdt_v2_1
+* @{
+*
+* This file contains the hardware interface to the Xilinx SCU private Watch Dog
+* Timer (XSCUWDT).
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.01a bss 02/27/12 Updated the register offsets to start at 0x0 instead
+*                    of 0x20 as the base address obtained from the tools
+*		     starts at 0x20.
+* 1.02a  sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+#ifndef XSCUWDT_HW_H		/* prevent circular inclusions */
+#define XSCUWDT_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device. The WDT registers start at
+ * an offset 0x20
+ * @{
+ */
+
+#define XSCUWDT_LOAD_OFFSET	0x00U /**< Watchdog Load Register */
+#define XSCUWDT_COUNTER_OFFSET	0x04U /**< Watchdog Counter Register */
+#define XSCUWDT_CONTROL_OFFSET	0x08U /**< Watchdog Control Register */
+#define XSCUWDT_ISR_OFFSET	0x0CU /**< Watchdog Interrupt Status Register */
+#define XSCUWDT_RST_STS_OFFSET	0x10U /**< Watchdog Reset Status Register */
+#define XSCUWDT_DISABLE_OFFSET	0x14U /**< Watchdog Disable Register */
+/* @} */
+
+/** @name Watchdog Control register
+ * This register bits control the prescaler, WD/Timer mode, Intr enable,
+ * auto-reload, watchdog enable.
+ * @{
+ */
+
+#define XSCUWDT_CONTROL_PRESCALER_MASK	 0x0000FF00U /**< Prescaler */
+#define XSCUWDT_CONTROL_PRESCALER_SHIFT	 8U
+#define XSCUWDT_CONTROL_WD_MODE_MASK	 0x00000008U /**< Watchdog/Timer mode */
+#define XSCUWDT_CONTROL_IT_ENABLE_MASK	 0x00000004U /**< Intr enable (in
+							 timer mode) */
+#define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload (in
+							 timer mode) */
+#define XSCUWDT_CONTROL_WD_ENABLE_MASK	 0x00000001U /**< Watchdog enable */
+/* @} */
+
+/** @name Interrupt Status register
+ * This register indicates the Counter register has reached zero in Counter
+ * mode.
+ * @{
+ */
+
+#define XSCUWDT_ISR_EVENT_FLAG_MASK	0x00000001U /**< Event flag */
+/*@}*/
+
+/** @name Reset Status register
+ * This register indicates the Counter register has reached zero in Watchdog
+ * mode and a reset request is sent.
+ * @{
+ */
+
+#define XSCUWDT_RST_STS_RESET_FLAG_MASK	0x00000001U /**< Time out occured */
+/*@}*/
+
+/** @name Disable register
+ * This register is used to switch from watchdog mode to timer mode.
+ * The software must write 0x12345678 and 0x87654321 successively to the
+ * Watchdog Disable Register so that the watchdog mode bit in the Watchdog
+ * Control Register is set to zero.
+ * @{
+ */
+#define XSCUWDT_DISABLE_VALUE1		0x12345678U /**< Watchdog mode disable
+							value 1 */
+#define XSCUWDT_DISABLE_VALUE2		0x87654321U /**< Watchdog mode disable
+							value 2 */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param	BaseAddr is the base address of the device
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note		C-style signature:
+*		u32 XScuWdt_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuWdt_ReadReg(BaseAddr, RegOffset)		\
+	Xil_In32((BaseAddr) + ((u32)RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param	BaseAddr is the base address of the device
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuWdt_WriteReg(BaseAddr, RegOffset, Data)	\
+	Xil_Out32((BaseAddr) + ((u32)RegOffset), ((u32)Data))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_selftest.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_selftest.c
new file mode 100644
index 0000000000000000000000000000000000000000..95d50651030e1886a6bc176623c74ae986aeff68
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_selftest.c
@@ -0,0 +1,131 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt_selftest.c
+* @addtogroup scuwdt_v2_1
+* @{
+*
+* Contains diagnostic self-test functions for the XScuWdt driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscuwdt.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Run a self-test on the WDT. This test stops the watchdog, writes a value to
+* the watchdog load register, starts the watchdog and verifies that the value
+* read from the counter register is less that the value written to the load
+* register. It then restores the control register and the watchdog load
+* register.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+*		- XST_SUCCESS if self-test was successful.
+*		- XST_FAILURE if the WDT is not decrementing.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XScuWdt_SelfTest(XScuWdt *InstancePtr)
+{
+	s32 SelfTestStatus;
+	u32 Register;
+	u32 CtrlOrig;
+	u32 LoadOrig;
+
+	/*
+	 * Assert to ensure the inputs are valid and the instance has been
+	 * initialized.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Stop the watchdog timer.
+	 */
+	CtrlOrig = XScuWdt_GetControlReg(InstancePtr);
+	XScuWdt_SetControlReg(InstancePtr,
+			      CtrlOrig & (u32)(~XSCUWDT_CONTROL_WD_ENABLE_MASK));
+
+	LoadOrig = XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,
+				   XSCUWDT_LOAD_OFFSET);
+	XScuWdt_LoadWdt(InstancePtr, 0xFFFFFFFFU);
+
+	/*
+	 * Start the watchdog timer and check if the watchdog counter is
+	 * decrementing.
+	 */
+	XScuWdt_SetControlReg(InstancePtr,
+			      CtrlOrig | (u32)XSCUWDT_CONTROL_WD_ENABLE_MASK);
+
+	Register = XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,
+				   XSCUWDT_COUNTER_OFFSET);
+
+	XScuWdt_LoadWdt(InstancePtr, LoadOrig);
+	XScuWdt_SetControlReg(InstancePtr, CtrlOrig);
+
+	if (Register == 0xFFFFFFFFU) {
+		SelfTestStatus = (s32)XST_FAILURE;
+	}
+	else {
+		SelfTestStatus = (s32)XST_SUCCESS;
+	}
+
+	return SelfTestStatus;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_sinit.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..c63eb9af03395e6ab4294af62a380205bba1c58f
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_sinit.c
@@ -0,0 +1,96 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscuwdt_sinit.c
+* @addtogroup scuwdt_v2_1
+* @{
+*
+* This file contains method for static initialization (compile-time) of the
+* driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscuwdt.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XScuWdt_Config XScuWdt_ConfigTable[XPAR_XSCUWDT_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId is the unique device ID of the device being looked up.
+*
+* @return	A pointer to the configuration table entry corresponding to the
+*		given device ID, or NULL if no match is found.
+*
+* @note		None.
+*
+******************************************************************************/
+XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId)
+{
+	XScuWdt_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < XPAR_XSCUWDT_NUM_INSTANCES; Index++) {
+		if (XScuWdt_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XScuWdt_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XScuWdt_Config *)CfgPtr;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/Makefile b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..f57081af62aab0d058d075fd27383824b280d42e
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xsdps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling sdps"
+
+xsdps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xsdps_includes
+
+xsdps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps.c
new file mode 100644
index 0000000000000000000000000000000000000000..38b11168a40222738132aae821e3033d6bc09d82
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps.c
@@ -0,0 +1,1639 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps.c
+* @addtogroup sdps_v2_5
+* @{
+*
+* Contains the interface functions of the XSdPs driver.
+* See xsdps.h for a detailed description of the device and driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.0   hk     12/13/13 Added check for arm to use sleep.h and its API's
+* 2.1   hk     04/18/14 Add sleep for microblaze designs. CR# 781117.
+* 2.2   hk     07/28/14 Make changes to enable use of data cache.
+* 2.3   sk     09/23/14 Send command for relative card address
+*                       when re-initialization is done.CR# 819614.
+*						Use XSdPs_Change_ClkFreq API whenever changing
+*						clock.CR# 816586.
+* 2.4	sk	   12/04/14 Added support for micro SD without
+* 						WP/CD. CR# 810655.
+*						Checked for DAT Inhibit mask instead of CMD
+* 						Inhibit mask in Cmd Transfer API.
+*						Added Support for SD Card v1.0
+* 2.5 	sg	   07/09/15 Added SD 3.0 features
+*       kvn    07/15/15 Modified the code according to MISRAC-2012.
+* 2.6   sk     10/12/15 Added support for SD card v1.0 CR# 840601.
+* 2.7   sk     11/24/15 Considered the slot type befoe checking CD/WP pins.
+*       sk     12/10/15 Added support for MMC cards.
+*       sk     02/16/16 Corrected the Tuning logic.
+*       sk     03/01/16 Removed Bus Width check for eMMC. CR# 938311.
+* 2.8   sk     05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
+* 3.0   sk     06/09/16 Added support for mkfs to calculate sector count.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/07/16 Used usleep API for both arm and microblaze.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+* 3.1   mi     09/07/16 Removed compilation warnings with extra compiler flags.
+*       sk     10/13/16 Reduced the delay during power cycle to 1ms as per spec
+*       sk     10/19/16 Used emmc_hwreset pin to reset eMMC.
+*       sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* 3.2   sk     11/30/16 Modified the voltage switching sequence as per spec.
+*       sk     02/01/17 Added HSD and DDR mode support for eMMC.
+*       vns    02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
+*       sk     03/20/17 Add support for EL1 non-secure mode.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xsdps.h"
+#include "sleep.h"
+
+/************************** Constant Definitions *****************************/
+#define XSDPS_CMD8_VOL_PATTERN	0x1AAU
+#define XSDPS_RESPOCR_READY	0x80000000U
+#define XSDPS_ACMD41_HCS	0x40000000U
+#define XSDPS_ACMD41_3V3	0x00300000U
+#define XSDPS_CMD1_HIGH_VOL	0x00FF8000U
+#define XSDPS_CMD1_DUAL_VOL	0x00FF8010U
+#define HIGH_SPEED_SUPPORT	0x2U
+#define WIDTH_4_BIT_SUPPORT	0x4U
+#define SD_CLK_25_MHZ		25000000U
+#define SD_CLK_19_MHZ		19000000U
+#define SD_CLK_26_MHZ		26000000U
+#define EXT_CSD_DEVICE_TYPE_BYTE	196U
+#define EXT_CSD_SEC_COUNT_BYTE1		212U
+#define EXT_CSD_SEC_COUNT_BYTE2		213U
+#define EXT_CSD_SEC_COUNT_BYTE3		214U
+#define EXT_CSD_SEC_COUNT_BYTE4		215U
+#define EXT_CSD_DEVICE_TYPE_HIGH_SPEED			0x2U
+#define EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED	0x4U
+#define EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED	0x8U
+#define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200		0x10U
+#define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200		0x20U
+#define CSD_SPEC_VER_3		0x3U
+
+/* Note: Remove this once fixed */
+#define UHS_BROKEN
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd);
+s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
+extern s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
+static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr);
+#ifndef UHS_BROKEN
+static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr);
+#endif
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XSdPs instance such that the driver is ready to use.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	ConfigPtr is a reference to a structure containing information
+*		about a specific SD device. This function initializes an
+*		InstancePtr object for a specific device specified by the
+*		contents of Config.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, use
+*		ConfigPtr->Config.BaseAddress for this device.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_DEVICE_IS_STARTED if the device is already started.
+*		It must be stopped to re-initialize.
+*
+* @note		This function initializes the host controller.
+*		Initial clock of 400KHz is set.
+*		Voltage of 3.3V is selected as that is supported by host.
+*		Interrupts status is enabled and signal disabled by default.
+*		Default data direction is card to host and
+*		32 bit ADMA2 is selected. Defualt Block size is 512 bytes.
+*
+******************************************************************************/
+s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	s32 Status;
+	u8 PowerLevel;
+	u8 ReadReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/* Set some default values. */
+	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+	InstancePtr->Config.CardDetect =  ConfigPtr->CardDetect;
+	InstancePtr->Config.WriteProtect =  ConfigPtr->WriteProtect;
+	InstancePtr->Config.BusWidth = ConfigPtr->BusWidth;
+	InstancePtr->Config.BankNumber = ConfigPtr->BankNumber;
+	InstancePtr->Config.HasEMIO = ConfigPtr->HasEMIO;
+	InstancePtr->SectorCount = 0;
+	InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
+	InstancePtr->Config_TapDelay = NULL;
+
+	/* Disable bus power and issue emmc hw reset */
+	if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK) ==
+			XSDPS_HC_SPEC_V3)
+		XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_POWER_CTRL_OFFSET, XSDPS_PC_EMMC_HW_RST_MASK);
+	else
+		XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_POWER_CTRL_OFFSET, 0x0);
+
+	/* Delay to poweroff card */
+    (void)usleep(1000U);
+
+	/* "Software reset for all" is initiated */
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
+			XSDPS_SWRST_ALL_MASK);
+
+	/* Proceed with initialization only after reset is complete */
+	ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_SW_RST_OFFSET);
+	while ((ReadReg & XSDPS_SWRST_ALL_MASK) != 0U) {
+		ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_SW_RST_OFFSET);
+	}
+	/* Host Controller version is read. */
+	 InstancePtr->HC_Version =
+			(u8)(XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK);
+
+	/*
+	 * Read capabilities register and update it in Instance pointer.
+	 * It is sufficient to read this once on power on.
+	 */
+	InstancePtr->Host_Caps = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XSDPS_CAPS_OFFSET);
+
+	/* Select voltage and enable bus power. */
+	if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
+		XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_POWER_CTRL_OFFSET,
+				(XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK) &
+				~XSDPS_PC_EMMC_HW_RST_MASK);
+	else
+		XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_POWER_CTRL_OFFSET,
+				XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK);
+
+	/* Delay before issuing the command after emmc reset */
+	if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
+		if ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) ==
+				XSDPS_CAPS_EMB_SLOT)
+			usleep(200);
+
+	/* Change the clock frequency to 400 KHz */
+	Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_400_KHZ);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH ;
+	}
+
+    if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V3_MASK) != 0U) {
+		PowerLevel = XSDPS_PC_BUS_VSEL_3V3_MASK;
+	} else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V0_MASK) != 0U) {
+		PowerLevel = XSDPS_PC_BUS_VSEL_3V0_MASK;
+	} else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_1V8_MASK) != 0U) {
+		PowerLevel = XSDPS_PC_BUS_VSEL_1V8_MASK;
+	} else {
+		PowerLevel = 0U;
+	}
+
+	/* Select voltage based on capability and enable bus power. */
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_POWER_CTRL_OFFSET,
+			PowerLevel | XSDPS_PC_BUS_PWR_MASK);
+	/* Enable ADMA2 in 64bit mode. */
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL1_OFFSET,
+			XSDPS_HC_DMA_ADMA2_32_MASK);
+
+	/* Enable all interrupt status except card interrupt initially */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_EN_OFFSET,
+			XSDPS_NORM_INTR_ALL_MASK & (~XSDPS_INTR_CARD_MASK));
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_ERR_INTR_STS_EN_OFFSET,
+			XSDPS_ERROR_INTR_ALL_MASK);
+
+	/* Disable all interrupt signals by default. */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_SIG_EN_OFFSET, 0x0U);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_ERR_INTR_SIG_EN_OFFSET, 0x0U);
+
+	/*
+	 * Transfer mode register - default value
+	 * DMA enabled, block count enabled, data direction card to host(read)
+	 */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK |
+			XSDPS_TM_DAT_DIR_SEL_MASK);
+
+	/* Set block size to 512 by default */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, XSDPS_BLK_SIZE_512_MASK);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+
+}
+
+/*****************************************************************************/
+/**
+* SD initialization is done in this function
+*
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because
+* 			a) SD is already initialized
+* 			b) There is no card inserted
+* 			c) One of the steps (commands) in the
+			   initialization cycle failed
+*
+* @note		This function initializes the SD card by following its
+*		initialization and identification state diagram.
+*		CMD0 is sent to reset card.
+*		CMD8 and ACDM41 are sent to identify voltage and
+*		high capacity support
+*		CMD2 and CMD3 are sent to obtain Card ID and
+*		Relative card address respectively.
+*		CMD9 is sent to read the card specific data.
+*
+******************************************************************************/
+s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr)
+{
+	u32 PresentStateReg;
+	s32 Status;
+	u32 RespOCR;
+	u32 CSD[4];
+	u32 Arg;
+	u8 ReadReg;
+	u32 BlkLen, DeviceSize, Mult;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+				((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+				!= XSDPS_CAPS_EMB_SLOT)) {
+		if(InstancePtr->Config.CardDetect != 0U) {
+			/*
+			 * Check the present state register to make sure
+			 * card is inserted and detected by host controller
+			 */
+			PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+			if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U)	{
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	}
+
+	/* CMD0 no response expected */
+	Status = XSdPs_CmdTransfer(InstancePtr, (u32)CMD0, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * CMD8; response expected
+	 * 0x1AA - Supply Voltage 2.7 - 3.6V and AA is pattern
+	 */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD8,
+			XSDPS_CMD8_VOL_PATTERN, 0U);
+	if ((Status != XST_SUCCESS) && (Status != XSDPS_CT_ERROR)) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	if (Status == XSDPS_CT_ERROR) {
+		 /* "Software reset for all" is initiated */
+		XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
+				XSDPS_SWRST_CMD_LINE_MASK);
+
+		/* Proceed with initialization only after reset is complete */
+		ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+						XSDPS_SW_RST_OFFSET);
+		while ((ReadReg & XSDPS_SWRST_CMD_LINE_MASK) != 0U) {
+			ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+						XSDPS_SW_RST_OFFSET);
+		}
+	}
+
+	RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XSDPS_RESP0_OFFSET);
+	if (RespOCR != XSDPS_CMD8_VOL_PATTERN) {
+		InstancePtr->Card_Version = XSDPS_SD_VER_1_0;
+	}
+	else {
+		InstancePtr->Card_Version = XSDPS_SD_VER_2_0;
+	}
+
+	RespOCR = 0U;
+	/* Send ACMD41 while card is still busy with power up */
+	while ((RespOCR & XSDPS_RESPOCR_READY) == 0U) {
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD55, 0U, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+        Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FFU << 15U);
+		if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
+		    Arg |= XSDPS_OCR_S18;
+		}
+
+		/* 0x40300000 - Host High Capacity support & 3.3V window */
+		Status = XSdPs_CmdTransfer(InstancePtr, ACMD41,
+				Arg, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/* Response with card capacity */
+		RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_RESP0_OFFSET);
+
+	}
+
+	/* Update HCS support flag based on card capacity response */
+	if ((RespOCR & XSDPS_ACMD41_HCS) != 0U) {
+		InstancePtr->HCS = 1U;
+	}
+
+	/* There is no support to switch to 1.8V and use UHS mode on 1.0 silicon */
+#ifndef UHS_BROKEN
+    if (((RespOCR & XSDPS_OCR_S18) != 0U) &&
+		(InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) {
+		InstancePtr->Switch1v8 = 1U;
+		Status = XSdPs_Switch_Voltage(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+	}
+#endif
+
+	/* CMD2 for Card ID */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	InstancePtr->CardID[0] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+	InstancePtr->CardID[1] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP1_OFFSET);
+	InstancePtr->CardID[2] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP2_OFFSET);
+	InstancePtr->CardID[3] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP3_OFFSET);
+	do {
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD3, 0U, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/*
+		 * Relative card address is stored as the upper 16 bits
+		 * This is to avoid shifting when sending commands
+		 */
+		InstancePtr->RelCardAddr =
+				XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_RESP0_OFFSET) & 0xFFFF0000U;
+	} while (InstancePtr->RelCardAddr == 0U);
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Card specific data is read.
+	 * Currently not used for any operation.
+	 */
+	CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+	CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP1_OFFSET);
+	CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP2_OFFSET);
+	CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP3_OFFSET);
+
+	if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 0U) {
+		BlkLen = 1 << ((CSD[2] & READ_BLK_LEN_MASK) >> 8U);
+		Mult = 1 << (((CSD[1] & C_SIZE_MULT_MASK) >> 7U) + 2U);
+		DeviceSize = (CSD[1] & C_SIZE_LOWER_MASK) >> 22U;
+		DeviceSize |= (CSD[2] & C_SIZE_UPPER_MASK) << 10U;
+		DeviceSize = (DeviceSize + 1U) * Mult;
+		DeviceSize =  DeviceSize * BlkLen;
+		InstancePtr->SectorCount = (DeviceSize/XSDPS_BLK_SIZE_512_MASK);
+	} else if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 1U) {
+		InstancePtr->SectorCount = (((CSD[1] & CSD_V2_C_SIZE_MASK) >> 8U) +
+										1U) * 1024U;
+	}
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Initialize Card with Identification mode sequence
+*
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because
+* 			a) SD is already initialized
+* 			b) There is no card inserted
+* 			c) One of the steps (commands) in the
+*			   initialization cycle failed
+*
+*
+******************************************************************************/
+s32 XSdPs_CardInitialize(XSdPs *InstancePtr)
+{
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+static u8 ExtCsd[512];
+#pragma data_alignment = 4
+#else
+static u8 ExtCsd[512] __attribute__ ((aligned(32)));
+#endif
+	u8 SCR[8] = { 0U };
+	u8 ReadBuff[64] = { 0U };
+	s32 Status;
+	u32 Arg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Default settings */
+	InstancePtr->BusWidth = XSDPS_1_BIT_WIDTH;
+	InstancePtr->CardType = XSDPS_CARD_SD;
+	InstancePtr->Switch1v8 = 0U;
+	InstancePtr->BusSpeed = XSDPS_CLK_400_KHZ;
+
+	if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
+			((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+			== XSDPS_CAPS_EMB_SLOT)) {
+		InstancePtr->CardType = XSDPS_CHIP_EMMC;
+	} else {
+		Status = XSdPs_IdentifyCard(InstancePtr);
+		if (Status == XST_FAILURE) {
+			goto RETURN_PATH;
+		}
+	}
+
+	if ((InstancePtr->CardType != XSDPS_CARD_SD) &&
+		(InstancePtr->CardType != XSDPS_CARD_MMC) &&
+		(InstancePtr->CardType != XSDPS_CHIP_EMMC)) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	if (InstancePtr->CardType == XSDPS_CARD_SD) {
+		Status = XSdPs_SdCardInitialize(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/* Change clock to default clock 25MHz */
+		/*
+		 * SD default speed mode timing should be closed at 19 MHz.
+		 * The reason for this is SD requires a voltage level shifter.
+		 * This limitation applies to ZynqMPSoC.
+		 */
+		if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
+			InstancePtr->BusSpeed = SD_CLK_19_MHZ;
+		else
+			InstancePtr->BusSpeed = SD_CLK_25_MHZ;
+		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+	} else if ((InstancePtr->CardType == XSDPS_CARD_MMC)
+			|| (InstancePtr->CardType == XSDPS_CHIP_EMMC)) {
+		Status = XSdPs_MmcCardInitialize(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+		/* Change clock to default clock 26MHz */
+		InstancePtr->BusSpeed = SD_CLK_26_MHZ;
+		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} else {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XSdPs_Select_Card(InstancePtr);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	if (InstancePtr->CardType == XSDPS_CARD_SD) {
+		/* Pull-up disconnected during data transfer */
+		Status = XSdPs_Pullup(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		Status = XSdPs_Get_BusWidth(InstancePtr, SCR);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		if ((SCR[1] & WIDTH_4_BIT_SUPPORT) != 0U) {
+			Status = XSdPs_Change_BusWidth(InstancePtr);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+
+		/* Get speed supported by device */
+		Status = XSdPs_Get_BusSpeed(InstancePtr, ReadBuff);
+		if (Status != XST_SUCCESS) {
+			goto RETURN_PATH;
+		}
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+		if (InstancePtr->Switch1v8 != 0U) {
+
+			/* Identify the UHS mode supported by card */
+			XSdPs_Identify_UhsMode(InstancePtr, ReadBuff);
+
+			/* Set UHS-I SDR104 mode */
+			Status = XSdPs_Uhs_ModeInit(InstancePtr, InstancePtr->Mode);
+			if (Status != XST_SUCCESS) {
+				goto RETURN_PATH;
+			}
+
+		} else {
+#endif
+			/*
+			 * card supports CMD6 when SD_SPEC field in SCR register
+			 * indicates that the Physical Layer Specification Version
+			 * is 1.10 or later. So for SD v1.0 cmd6 is not supported.
+			 */
+			if (SCR[0] != 0U) {
+				/* Check for high speed support */
+				if (((ReadBuff[13] & HIGH_SPEED_SUPPORT) != 0U) &&
+						(InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+					InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+					InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay;
+#endif
+					Status = XSdPs_Change_BusSpeed(InstancePtr);
+					if (Status != XST_SUCCESS) {
+						Status = XST_FAILURE;
+						goto RETURN_PATH;
+					}
+				}
+			}
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+		}
+#endif
+
+	} else if (((InstancePtr->CardType == XSDPS_CARD_MMC) &&
+				(InstancePtr->Card_Version > CSD_SPEC_VER_3)) &&
+				(InstancePtr->HC_Version == XSDPS_HC_SPEC_V2)) {
+
+		Status = XSdPs_Change_BusWidth(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24;
+		InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16;
+		InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8;
+		InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1];
+
+		if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
+				EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) &&
+				(InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+			InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
+			Status = XSdPs_Change_BusSpeed(InstancePtr);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+
+			Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+
+			if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	} else if (InstancePtr->CardType == XSDPS_CHIP_EMMC){
+		/* Change bus width to 8-bit */
+		Status = XSdPs_Change_BusWidth(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/* Get Extended CSD */
+		Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24;
+		InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16;
+		InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8;
+		InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1];
+
+		/* Check for card supported speed */
+		if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
+				(EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 |
+				EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200)) != 0U) &&
+				(InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+			InstancePtr->Mode = XSDPS_HS200_MODE;
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+			InstancePtr->Config_TapDelay = XSdPs_sdr104_hs200_tapdelay;
+#endif
+		} else if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
+				(EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED |
+				EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED)) != 0U) &&
+				(InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+			InstancePtr->Mode = XSDPS_DDR52_MODE;
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+			InstancePtr->Config_TapDelay = XSdPs_ddr50_tapdelay;
+#endif
+		} else if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
+				EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) &&
+				(InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+			InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+			InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay;
+#endif
+		} else
+			InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
+
+		if (InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) {
+			Status = XSdPs_Change_BusSpeed(InstancePtr);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+
+			Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+
+			if (InstancePtr->Mode == XSDPS_HS200_MODE) {
+				if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HS200) {
+					Status = XST_FAILURE;
+					goto RETURN_PATH;
+				}
+			}
+
+			if ((InstancePtr->Mode == XSDPS_HIGH_SPEED_MODE) ||
+					InstancePtr->Mode == XSDPS_DDR52_MODE) {
+				if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) {
+					Status = XST_FAILURE;
+					goto RETURN_PATH;
+				}
+
+				if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
+					Status = XSdPs_Change_BusWidth(InstancePtr);
+					if (Status != XST_SUCCESS) {
+						Status = XST_FAILURE;
+						goto RETURN_PATH;
+					}
+				}
+			}
+		}
+
+		/* Enable Rst_n_Fun bit if it is disabled */
+		if(ExtCsd[EXT_CSD_RST_N_FUN_BYTE] == EXT_CSD_RST_N_FUN_TEMP_DIS) {
+			Arg = XSDPS_MMC_RST_FUN_EN_ARG;
+			Status = XSdPs_Set_Mmc_ExtCsd(InstancePtr, Arg);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	}
+	if ((InstancePtr->Mode != XSDPS_DDR52_MODE) ||
+			(InstancePtr->CardType == XSDPS_CARD_SD)) {
+		Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	}
+
+RETURN_PATH:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Identify type of card using CMD0 + CMD1 sequence
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+******************************************************************************/
+static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr)
+{
+	s32 Status;
+	u8 ReadReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* 74 CLK delay after card is powered up, before the first command. */
+	usleep(XSDPS_INIT_DELAY);
+
+	/* CMD0 no response expected */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/* Host High Capacity support & High voltage window */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD1,
+			XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U);
+	if (Status != XST_SUCCESS) {
+		InstancePtr->CardType = XSDPS_CARD_SD;
+	} else {
+		InstancePtr->CardType = XSDPS_CARD_MMC;
+	}
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
+
+	/* "Software reset for all" is initiated */
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
+			XSDPS_SWRST_CMD_LINE_MASK);
+
+	/* Proceed with initialization only after reset is complete */
+	ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+					XSDPS_SW_RST_OFFSET);
+	while ((ReadReg & XSDPS_SWRST_CMD_LINE_MASK) != 0U) {
+		ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+					XSDPS_SW_RST_OFFSET);
+	}
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+}
+
+#ifndef UHS_BROKEN
+/*****************************************************************************/
+/**
+*
+* Switches the SD card voltage from 3v3 to 1v8
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+******************************************************************************/
+static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr)
+{
+	s32 Status;
+	u16 CtrlReg;
+	u32 ReadReg, ClockReg;
+
+	/* Send switch voltage command */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD11, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+	}
+
+	/* Wait for CMD and DATA line to go low */
+	ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_PRES_STATE_OFFSET);
+	while ((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK |
+					XSDPS_PSR_DAT30_SG_LVL_MASK)) != 0U) {
+		ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+	}
+
+	/* Stop the clock */
+	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	CtrlReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+			CtrlReg);
+
+	/* Enabling 1.8V in controller */
+	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL2_OFFSET);
+	CtrlReg |= XSDPS_HC2_1V8_EN_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET,
+			CtrlReg);
+
+	/* Wait minimum 5mSec */
+	(void)usleep(5000U);
+
+	/* Check for 1.8V signal enable bit is cleared by Host */
+	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_HOST_CTRL2_OFFSET);
+	if ((CtrlReg & XSDPS_HC2_1V8_EN_MASK) == 0U) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/* Wait for internal clock to stabilize */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_CLK_CTRL_OFFSET);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_CLK_CTRL_OFFSET,
+				ClockReg | XSDPS_CC_INT_CLK_EN_MASK);
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_CLK_CTRL_OFFSET);
+	while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
+		ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_CLK_CTRL_OFFSET);
+	}
+
+	/* Enable SD clock */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET,
+			ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+
+	/* Wait for 1mSec */
+	(void)usleep(1000U);
+
+	/* Wait for CMD and DATA line to go high */
+	ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_PRES_STATE_OFFSET);
+	while ((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK))
+			!= (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK)) {
+		ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+	}
+
+RETURN_PATH:
+	return Status;
+}
+#endif
+
+/*****************************************************************************/
+/**
+
+* This function does SD command generation.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Cmd is the command to be sent.
+* @param	Arg is the argument to be sent along with the command.
+* 		This could be address or any other information
+* @param	BlkCnt - Block count passed by the user.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because another transfer
+* 			is in progress or command or data inhibit is set
+*
+******************************************************************************/
+s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt)
+{
+	u32 PresentStateReg;
+	u32 CommandReg;
+	u32 StatusReg;
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Check the command inhibit to make sure no other
+	 * command transfer is in progress
+	 */
+	PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_PRES_STATE_OFFSET);
+	if ((PresentStateReg & XSDPS_PSR_INHIBIT_CMD_MASK) != 0U) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/* Write block count register */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_CNT_OFFSET, (u16)BlkCnt);
+
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_TIMEOUT_CTRL_OFFSET, 0xEU);
+
+	/* Write argument register */
+	XSdPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XSDPS_ARGMT_OFFSET, Arg);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
+	/* Command register is set to trigger transfer of command */
+	CommandReg = XSdPs_FrameCmd(InstancePtr, Cmd);
+
+	/*
+	 * Mask to avoid writing to reserved bits 31-30
+	 * This is necessary because 0x80000000 is used  by this software to
+	 * distinguish between ACMD and CMD of same number
+	 */
+	CommandReg = CommandReg & 0x3FFFU;
+
+	/*
+	 * Check for data inhibit in case of command using DAT lines.
+	 * For Tuning Commands DAT lines check can be ignored.
+	 */
+	if ((Cmd != CMD21) && (Cmd != CMD19)) {
+		PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_PRES_STATE_OFFSET);
+		if (((PresentStateReg & (XSDPS_PSR_INHIBIT_DAT_MASK |
+									XSDPS_PSR_INHIBIT_DAT_MASK)) != 0U) &&
+				((CommandReg & XSDPS_DAT_PRESENT_SEL_MASK) != 0U)) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	}
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CMD_OFFSET,
+			(u16)CommandReg);
+
+	/* Polling for response for now */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((Cmd == CMD21) || (Cmd == CMD19)) {
+			if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET) & XSDPS_INTR_BRR_MASK) != 0U){
+				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_BRR_MASK);
+				break;
+			}
+		}
+
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			Status = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+									XSDPS_ERR_INTR_STS_OFFSET);
+			if ((Status & ~XSDPS_INTR_ERR_CT_MASK) == 0) {
+				Status = XSDPS_CT_ERROR;
+			}
+			 /* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			goto RETURN_PATH;
+		}
+	} while((StatusReg & XSDPS_INTR_CC_MASK) == 0U);
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET,
+			XSDPS_INTR_CC_MASK);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+* This function frames the Command register for a particular command.
+* Note that this generates only the command register value i.e.
+* the upper 16 bits of the transfer mode and command register.
+* This value is already shifted to be upper 16 bits and can be directly
+* OR'ed with transfer mode register value.
+*
+* @param	Command to be sent.
+*
+* @return	Command register value complete with response type and
+* 		data, CRC and index related flags.
+*
+******************************************************************************/
+u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd)
+{
+		u32 RetVal;
+
+		RetVal = Cmd;
+
+		switch(Cmd) {
+		case CMD0:
+			RetVal |= RESP_NONE;
+		break;
+		case CMD1:
+			RetVal |= RESP_R3;
+		break;
+		case CMD2:
+			RetVal |= RESP_R2;
+		break;
+		case CMD3:
+			RetVal |= RESP_R6;
+		break;
+		case CMD4:
+			RetVal |= RESP_NONE;
+			break;
+		case CMD5:
+			RetVal |= RESP_R1B;
+		break;
+		case CMD6:
+			if (InstancePtr->CardType == XSDPS_CARD_SD) {
+				RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+			} else {
+				RetVal |= RESP_R1B;
+			}
+			break;
+		case ACMD6:
+			RetVal |= RESP_R1;
+		break;
+		case CMD7:
+			RetVal |= RESP_R1;
+		break;
+		case CMD8:
+			if (InstancePtr->CardType == XSDPS_CARD_SD) {
+				RetVal |= RESP_R1;
+			} else {
+				RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+			}
+			break;
+		case CMD9:
+			RetVal |= RESP_R2;
+		break;
+		case CMD11:
+		case CMD10:
+		case CMD12:
+		case ACMD13:
+		case CMD16:
+			RetVal |= RESP_R1;
+		break;
+		case CMD17:
+		case CMD18:
+		case CMD19:
+		case CMD21:
+			RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+		break;
+		case CMD23:
+		case ACMD23:
+		case CMD24:
+		case CMD25:
+			RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+		case ACMD41:
+			RetVal |= RESP_R3;
+		break;
+		case ACMD42:
+			RetVal |= RESP_R1;
+		break;
+		case ACMD51:
+			RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+		break;
+		case CMD52:
+		case CMD55:
+			RetVal |= RESP_R1;
+		break;
+		case CMD58:
+		break;
+		default :
+			RetVal |= Cmd;
+		break;
+		}
+
+		return RetVal;
+}
+
+/*****************************************************************************/
+/**
+* This function performs SD read in polled mode.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Arg is the address passed by the user that is to be sent as
+* 		argument along with the command.
+* @param	BlkCnt - Block count passed by the user.
+* @param	Buff - Pointer to the data buffer for a DMA transfer.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because another transfer
+* 		is in progress or command or data inhibit is set
+*
+******************************************************************************/
+s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
+{
+	s32 Status;
+	u32 PresentStateReg;
+	u32 StatusReg;
+
+	if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+				((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+				!= XSDPS_CAPS_EMB_SLOT)) {
+		if(InstancePtr->Config.CardDetect != 0U) {
+			/* Check status to ensure card is initialized */
+			PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+			if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	}
+
+	/* Set block size to 512 if not already set */
+	if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) {
+		Status = XSdPs_SetBlkSize(InstancePtr,
+			XSDPS_BLK_SIZE_512_MASK);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	}
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_AUTO_CMD12_EN_MASK |
+			XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DAT_DIR_SEL_MASK |
+			XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK);
+
+	Xil_DCacheInvalidateRange((INTPTR)Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK);
+
+	/* Send block read command */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/* Check for transfer complete */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+* This function performs SD write in polled mode.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Arg is the address passed by the user that is to be sent as
+* 		argument along with the command.
+* @param	BlkCnt - Block count passed by the user.
+* @param	Buff - Pointer to the data buffer for a DMA transfer.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because another transfer
+* 		is in progress or command or data inhibit is set
+*
+******************************************************************************/
+s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff)
+{
+	s32 Status;
+	u32 PresentStateReg;
+	u32 StatusReg;
+
+	if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+				((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+				!= XSDPS_CAPS_EMB_SLOT)) {
+		if(InstancePtr->Config.CardDetect != 0U) {
+			/* Check status to ensure card is initialized */
+			PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+			if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	}
+
+	/* Set block size to 512 if not already set */
+	if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) {
+		Status = XSdPs_SetBlkSize(InstancePtr,
+			XSDPS_BLK_SIZE_512_MASK);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+	}
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
+	Xil_DCacheFlushRange((INTPTR)Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_AUTO_CMD12_EN_MASK |
+			XSDPS_TM_BLK_CNT_EN_MASK |
+			XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+
+	/* Send block write command */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Selects card and sets default block size
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Select_Card (XSdPs *InstancePtr)
+{
+	s32 Status = 0;
+
+	/* Send CMD7 - Select card */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD7,
+			InstancePtr->RelCardAddr, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to setup ADMA2 descriptor table
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	BlkCnt - block count.
+* @param	Buff pointer to data buffer.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff)
+{
+	u32 TotalDescLines = 0U;
+	u32 DescNum = 0U;
+	u32 BlkSize = 0U;
+
+	/* Setup ADMA2 - Write descriptor table and point ADMA SAR to it */
+	BlkSize = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_BLK_SIZE_OFFSET);
+	BlkSize = BlkSize & XSDPS_BLK_SIZE_MASK;
+
+	if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) {
+
+		TotalDescLines = 1U;
+
+	}else {
+
+		TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH);
+		if (((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH) != 0U) {
+			TotalDescLines += 1U;
+		}
+
+	}
+
+	for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) {
+		InstancePtr->Adma2_DescrTbl[DescNum].Address =
+				(u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+		InstancePtr->Adma2_DescrTbl[DescNum].Attribute =
+				XSDPS_DESC_TRAN | XSDPS_DESC_VALID;
+		/* This will write '0' to length field which indicates 65536 */
+		InstancePtr->Adma2_DescrTbl[DescNum].Length =
+				(u16)XSDPS_DESC_MAX_LENGTH;
+	}
+
+	InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address =
+			(u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+
+	InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Attribute =
+			XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID;
+
+	InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Length =
+			(u16)((BlkCnt*BlkSize) - (DescNum*XSDPS_DESC_MAX_LENGTH));
+
+
+	XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
+			(u32)(UINTPTR)&(InstancePtr->Adma2_DescrTbl[0]));
+
+	Xil_DCacheFlushRange((INTPTR)&(InstancePtr->Adma2_DescrTbl[0]),
+			sizeof(XSdPs_Adma2Descriptor) * 32U);
+
+}
+
+/*****************************************************************************/
+/**
+* Mmc initialization is done in this function
+*
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because
+* 			a) MMC is already initialized
+* 			b) There is no card inserted
+* 			c) One of the steps (commands) in the initialization
+*			   cycle failed
+* @note 	This function initializes the SD card by following its
+*		initialization and identification state diagram.
+*		CMD0 is sent to reset card.
+*		CMD1 sent to identify voltage and high capacity support
+*		CMD2 and CMD3 are sent to obtain Card ID and
+*		Relative card address respectively.
+*		CMD9 is sent to read the card specific data.
+*
+******************************************************************************/
+s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr)
+{
+	u32 PresentStateReg;
+	s32 Status;
+	u32 RespOCR;
+	u32 CSD[4];
+	u32 BlkLen, DeviceSize, Mult;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+				((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+				!= XSDPS_CAPS_EMB_SLOT)) {
+		if(InstancePtr->Config.CardDetect != 0U) {
+			/*
+			 * Check the present state register to make sure
+			 * card is inserted and detected by host controller
+			 */
+			PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+			if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U)	{
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	}
+
+	/* CMD0 no response expected */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	RespOCR = 0U;
+	/* Send CMD1 while card is still busy with power up */
+	while ((RespOCR & XSDPS_RESPOCR_READY) == 0U) {
+
+		/* Host High Capacity support & High volage window */
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD1,
+				XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/* Response with card capacity */
+		RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_RESP0_OFFSET);
+
+	}
+
+	/* Update HCS support flag based on card capacity response */
+	if ((RespOCR & XSDPS_ACMD41_HCS) != 0U) {
+		InstancePtr->HCS = 1U;
+	}
+
+	/* CMD2 for Card ID */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	InstancePtr->CardID[0] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+	InstancePtr->CardID[1] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP1_OFFSET);
+	InstancePtr->CardID[2] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP2_OFFSET);
+	InstancePtr->CardID[3] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP3_OFFSET);
+
+	/* Set relative card address */
+	InstancePtr->RelCardAddr = 0x12340000U;
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD3, (InstancePtr->RelCardAddr), 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Card specific data is read.
+	 * Currently not used for any operation.
+	 */
+	CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+	CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP1_OFFSET);
+	CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP2_OFFSET);
+	CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP3_OFFSET);
+
+	InstancePtr->Card_Version =  (CSD[3] & CSD_SPEC_VER_MASK) >>18U;
+
+	/* Calculating the memory capacity */
+	BlkLen = 1 << ((CSD[2] & READ_BLK_LEN_MASK) >> 8U);
+	Mult = 1 << (((CSD[1] & C_SIZE_MULT_MASK) >> 7U) + 2U);
+	DeviceSize = (CSD[1] & C_SIZE_LOWER_MASK) >> 22U;
+	DeviceSize |= (CSD[2] & C_SIZE_UPPER_MASK) << 10U;
+	DeviceSize = (DeviceSize + 1U) * Mult;
+	DeviceSize =  DeviceSize * BlkLen;
+
+	InstancePtr->SectorCount = (DeviceSize/XSDPS_BLK_SIZE_512_MASK);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps.h
new file mode 100644
index 0000000000000000000000000000000000000000..9e475207daa03784e2c9d030ca0bf7cc45f50c36
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps.h
@@ -0,0 +1,263 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps.h
+* @addtogroup sdps_v2_5
+* @{
+* @details
+*
+* This file contains the implementation of XSdPs driver.
+* This driver is used initialize read from and write to the SD card.
+* Features such as switching bus width to 4-bit and switching to high speed,
+* changing clock frequency, block size etc. are supported.
+* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however
+* is done using 1-bit bus width and 400KHz clock frequency.
+* SD commands are classified as broadcast and addressed. Commands can be
+* those with response only (using only command line) or
+* response + data (using command and data lines).
+* Only one command can be sent at a time. During a data transfer however,
+* when dsta lines are in use, certain commands (which use only the command
+* line) can be sent, most often to obtain status.
+* This driver does not support multi card slots at present.
+*
+* Intialization:
+* This includes initialization on the host controller side to select
+* clock frequency, bus power and default transfer related parameters.
+* The default voltage is 3.3V.
+* On the SD card side, the initialization and identification state diagram is
+* implemented. This resets the card, gives it a unique address/ID and
+* identifies key card related specifications.
+*
+* Data transfer:
+* The SD card is put in tranfer state to read from or write to it.
+* The default block size is 512 bytes and if supported,
+* default bus width is 4-bit and bus speed is High speed.
+* The read and write functions are implemented in polled mode using ADMA2.
+*
+* At any point, when key parameters such as block size or
+* clock/speed or bus width are modified, this driver takes care of
+* maintaining the same selection on host and card.
+* All error bits in host controller are monitored by the driver and in the
+* event one of them is set, driver will clear the interrupt status and
+* communicate failure to the upper layer.
+*
+* File system use:
+* This driver can be used with xilffs library to read and write files to SD.
+* (Please refer to procedure in diskio.c). The file system read/write example
+* in polled mode can used for reference.
+*
+* There is no example for using SD driver without file system at present.
+* However, the driver can be used without the file system. The glue layer
+* in filesytem can be used as reference for the same. The block count
+* passed to the read/write function in one call is limited by the ADMA2
+* descriptor table and hence care will have to be taken to call read/write
+* API's in a loop for large file sizes.
+*
+* Interrupt mode is not supported because it offers no improvement when used
+* with file system.
+*
+* eMMC support:
+* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK.
+* The features of eMMC supported by the driver will depend on those supported
+* by the host controller. The current driver supports read/write on eMMC card
+* using 4-bit and high speed mode currently.
+*
+* Features not supported include - card write protect, password setting,
+* lock/unlock, interrupts, SDMA mode, programmed I/O mode and
+* 64-bit addressed ADMA2, erase/pre-erase commands.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.0   hk      03/07/14 Version number revised.
+* 2.1   hk     04/18/14 Increase sleep for eMMC switch command.
+*                       Add sleep for microblaze designs. CR# 781117.
+* 2.2   hk     07/28/14 Make changes to enable use of data cache.
+* 2.3   sk     09/23/14 Send command for relative card address
+*                       when re-initialization is done.CR# 819614.
+*						Use XSdPs_Change_ClkFreq API whenever changing
+*						clock.CR# 816586.
+* 2.4	sk	   12/04/14 Added support for micro SD without
+* 						WP/CD. CR# 810655.
+*						Checked for DAT Inhibit mask instead of CMD
+* 						Inhibit mask in Cmd Transfer API.
+*						Added Support for SD Card v1.0
+* 2.5 	sg		07/09/15 Added SD 3.0 features
+*       kvn     07/15/15 Modified the code according to MISRAC-2012.
+* 2.6   sk     10/12/15 Added support for SD card v1.0 CR# 840601.
+* 2.7   sk     11/24/15 Considered the slot type befoe checking CD/WP pins.
+*       sk     12/10/15 Added support for MMC cards.
+*              01/08/16 Added workaround for issue in auto tuning mode
+*                       of SDR50, SDR104 and HS200.
+*       sk     02/16/16 Corrected the Tuning logic.
+*       sk     03/01/16 Removed Bus Width check for eMMC. CR# 938311.
+* 2.8   sk     04/20/16 Added new workaround for auto tuning.
+*              05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
+* 3.0   sk     06/09/16 Added support for mkfs to calculate sector count.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/07/16 Used usleep API for both arm and microblaze.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+*       sk     08/13/16 Removed sleep.h from xsdps.h as a temporary fix for
+*                       CR#956899.
+* 3.1   mi     09/07/16 Removed compilation warnings with extra compiler flags.
+*       sk     10/13/16 Reduced the delay during power cycle to 1ms as per spec
+*       sk     10/19/16 Used emmc_hwreset pin to reset eMMC.
+*       sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+*       sk     11/16/16 Issue DLL reset at 31 iteration to load new zero value.
+* 3.2   sk     11/30/16 Modified the voltage switching sequence as per spec.
+*       sk     02/01/17 Added HSD and DDR mode support for eMMC.
+*       sk     02/01/17 Consider bus width parameter from design for switching
+*       vns    02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
+*       sk     03/20/17 Add support for EL1 non-secure mode.
+*
+* </pre>
+*
+******************************************************************************/
+
+
+#ifndef SDPS_H_
+#define SDPS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_printf.h"
+#include "xil_cache.h"
+#include "xstatus.h"
+#include "xsdps_hw.h"
+#include <string.h>
+
+/************************** Constant Definitions *****************************/
+
+#define XSDPS_CT_ERROR	0x2U	/**< Command timeout flag */
+#define MAX_TUNING_COUNT	40U		/**< Maximum Tuning count */
+
+/**************************** Type Definitions *******************************/
+
+typedef void (*XSdPs_ConfigTap) (u32 Bank, u32 DeviceId, u32 CardType);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;			/**< Unique ID  of device */
+	u32 BaseAddress;		/**< Base address of the device */
+	u32 InputClockHz;		/**< Input clock frequency */
+	u32 CardDetect;			/**< Card Detect */
+	u32 WriteProtect;			/**< Write Protect */
+	u32 BusWidth;			/**< Bus Width */
+	u32 BankNumber;			/**< MIO Bank selection for SD */
+	u32 HasEMIO;			/**< If SD is connected to EMIO */
+} XSdPs_Config;
+
+/* ADMA2 descriptor table */
+typedef struct {
+	u16 Attribute;		/**< Attributes of descriptor */
+	u16 Length;		/**< Length of current dma transfer */
+	u32 Address;		/**< Address of current dma transfer */
+} XSdPs_Adma2Descriptor;
+
+/**
+ * The XSdPs driver instance data. The user is required to allocate a
+ * variable of this type for every SD device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XSdPs_Config Config;	/**< Configuration structure */
+	u32 IsReady;		/**< Device is initialized and ready */
+	u32 Host_Caps;		/**< Capabilities of host controller */
+	u32 Host_CapsExt;	/**< Extended Capabilities */
+	u32 HCS;		/**< High capacity support in card */
+	u8  CardType;		/**< Type of card - SD/MMC/eMMC */
+	u8  Card_Version;	/**< Card version */
+	u8  HC_Version;		/**< Host controller version */
+	u8  BusWidth;		/**< Current operating bus width */
+	u32 BusSpeed;		/**< Current operating bus speed */
+	u8  Switch1v8;		/**< 1.8V Switch support */
+	u32 CardID[4];		/**< Card ID Register */
+	u32 RelCardAddr;	/**< Relative Card Address */
+	u32 CardSpecData[4];	/**< Card Specific Data Register */
+	u32 SectorCount;		/**< Sector Count */
+	u32 SdCardConfig;	/**< Sd Card Configuration Register */
+	u32 Mode;			/**< Bus Speed Mode */
+	XSdPs_ConfigTap Config_TapDelay;	/**< Configuring the tap delays */
+	/**< ADMA Descriptors */
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+	XSdPs_Adma2Descriptor Adma2_DescrTbl[32];
+#pragma data_alignment = 4
+#else
+	XSdPs_Adma2Descriptor Adma2_DescrTbl[32] __attribute__ ((aligned(32)));
+#endif
+} XSdPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId);
+s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
+				u32 EffectiveAddr);
+s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
+s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);
+s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize);
+s32 XSdPs_Select_Card (XSdPs *InstancePtr);
+s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq);
+s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr);
+s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr);
+s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR);
+s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff);
+s32 XSdPs_Pullup(XSdPs *InstancePtr);
+s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_CardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff);
+s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg);
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff);
+void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_H_ */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps_g.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..b8eca64baecad8a8eae455c78e41ecb31886eedd
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps_g.c
@@ -0,0 +1,61 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xsdps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_SD_0_DEVICE_ID,
+		XPAR_PS7_SD_0_BASEADDR,
+		XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ,
+		XPAR_PS7_SD_0_HAS_CD,
+		XPAR_PS7_SD_0_HAS_WP,
+		XPAR_PS7_SD_0_BUS_WIDTH,
+		XPAR_PS7_SD_0_MIO_BANK,
+		XPAR_PS7_SD_0_HAS_EMIO
+	}
+};
+
+
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..6bb6c2a616ca3bcc38a0270f58b558870f172b5b
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps_hw.h
@@ -0,0 +1,1249 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_hw.h
+* @addtogroup sdps_v2_5
+* @{
+*
+* This header file contains the identifiers and basic HW access driver
+* functions (or  macros) that can be used to access the device. Other driver
+* functions are defined in xsdps.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.5 	sg	   07/09/15 Added SD 3.0 features
+*       kvn    07/15/15 Modified the code according to MISRAC-2012.
+* 2.7   sk     12/10/15 Added support for MMC cards.
+*       sk     03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
+* 2.8   sk     04/20/16 Added new workaround for auto tuning.
+* 3.0   sk     06/09/16 Added support for mkfs to calculate sector count.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+* 3.1   sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* 3.2   sk     03/20/17 Add support for EL1 non-secure mode.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef SD_HW_H_
+#define SD_HW_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of an SD device.
+ * @{
+ */
+
+#define XSDPS_SDMA_SYS_ADDR_OFFSET	0x00U	/**< SDMA System Address
+							Register */
+#define XSDPS_SDMA_SYS_ADDR_LO_OFFSET	XSDPS_SDMA_SYS_ADDR_OFFSET
+						/**< SDMA System Address
+							Low Register */
+#define XSDPS_ARGMT2_LO_OFFSET		0x00U	/**< Argument2 Low Register */
+#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET	0x02U	/**< SDMA System Address
+							High Register */
+#define XSDPS_ARGMT2_HI_OFFSET		0x02U	/**< Argument2 High Register */
+
+#define XSDPS_BLK_SIZE_OFFSET		0x04U	/**< Block Size Register */
+#define XSDPS_BLK_CNT_OFFSET		0x06U	/**< Block Count Register */
+#define XSDPS_ARGMT_OFFSET		0x08U	/**< Argument Register */
+#define XSDPS_ARGMT1_LO_OFFSET		XSDPS_ARGMT_OFFSET
+						/**< Argument1 Register */
+#define XSDPS_ARGMT1_HI_OFFSET		0x0AU	/**< Argument1 Register */
+
+#define XSDPS_XFER_MODE_OFFSET		0x0CU	/**< Transfer Mode Register */
+#define XSDPS_CMD_OFFSET		0x0EU	/**< Command Register */
+#define XSDPS_RESP0_OFFSET		0x10U	/**< Response0 Register */
+#define XSDPS_RESP1_OFFSET		0x14U	/**< Response1 Register */
+#define XSDPS_RESP2_OFFSET		0x18U	/**< Response2 Register */
+#define XSDPS_RESP3_OFFSET		0x1CU	/**< Response3 Register */
+#define XSDPS_BUF_DAT_PORT_OFFSET	0x20U	/**< Buffer Data Port */
+#define XSDPS_PRES_STATE_OFFSET		0x24U	/**< Present State */
+#define XSDPS_HOST_CTRL1_OFFSET		0x28U	/**< Host Control 1 */
+#define XSDPS_POWER_CTRL_OFFSET		0x29U	/**< Power Control */
+#define XSDPS_BLK_GAP_CTRL_OFFSET	0x2AU	/**< Block Gap Control */
+#define XSDPS_WAKE_UP_CTRL_OFFSET	0x2BU	/**< Wake Up Control */
+#define XSDPS_CLK_CTRL_OFFSET		0x2CU	/**< Clock Control */
+#define XSDPS_TIMEOUT_CTRL_OFFSET	0x2EU	/**< Timeout Control */
+#define XSDPS_SW_RST_OFFSET		0x2FU	/**< Software Reset */
+#define XSDPS_NORM_INTR_STS_OFFSET 	0x30U	/**< Normal Interrupt
+							Status Register */
+#define XSDPS_ERR_INTR_STS_OFFSET 	0x32U	/**< Error Interrupt
+							Status Register */
+#define XSDPS_NORM_INTR_STS_EN_OFFSET	0x34U	/**< Normal Interrupt
+						Status Enable Register */
+#define XSDPS_ERR_INTR_STS_EN_OFFSET	0x36U	/**< Error Interrupt
+						Status Enable Register */
+#define XSDPS_NORM_INTR_SIG_EN_OFFSET	0x38U	/**< Normal Interrupt
+						Signal Enable Register */
+#define XSDPS_ERR_INTR_SIG_EN_OFFSET	0x3AU	/**< Error Interrupt
+						Signal Enable Register */
+
+#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET	0x3CU	/**< Auto CMD12 Error Status
+							Register */
+#define XSDPS_HOST_CTRL2_OFFSET		0x3EU	/**< Host Control2 Register */
+#define XSDPS_CAPS_OFFSET 		0x40U	/**< Capabilities Register */
+#define XSDPS_CAPS_EXT_OFFSET 		0x44U	/**< Capabilities Extended */
+#define XSDPS_MAX_CURR_CAPS_OFFSET	0x48U	/**< Maximum Current
+						Capabilities Register */
+#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET	0x4CU	/**< Maximum Current
+						Capabilities Ext Register */
+#define XSDPS_FE_ERR_INT_STS_OFFSET	0x52U	/**< Force Event for
+						Error Interrupt Status */
+#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET	0x50U	/**< Auto CM12 Error Interrupt
+							Status Register */
+#define XSDPS_ADMA_ERR_STS_OFFSET	0x54U	/**< ADMA Error Status
+							Register */
+#define XSDPS_ADMA_SAR_OFFSET		0x58U	/**< ADMA System Address
+							Register */
+#define XSDPS_ADMA_SAR_EXT_OFFSET	0x5CU	/**< ADMA System Address
+							Extended Register */
+#define XSDPS_PRE_VAL_1_OFFSET		0x60U	/**< Preset Value Register */
+#define XSDPS_PRE_VAL_2_OFFSET		0x64U	/**< Preset Value Register */
+#define XSDPS_PRE_VAL_3_OFFSET		0x68U	/**< Preset Value Register */
+#define XSDPS_PRE_VAL_4_OFFSET		0x6CU	/**< Preset Value Register */
+#define XSDPS_BOOT_TOUT_CTRL_OFFSET	0x70U	/**< Boot timeout control
+							register */
+
+#define XSDPS_SHARED_BUS_CTRL_OFFSET	0xE0U	/**< Shared Bus Control
+							Register */
+#define XSDPS_SLOT_INTR_STS_OFFSET	0xFCU	/**< Slot Interrupt Status
+							Register */
+#define XSDPS_HOST_CTRL_VER_OFFSET	0xFEU	/**< Host Controller Version
+							Register */
+
+/* @} */
+
+/** @name Control Register - Host control, Power control,
+ * 			Block Gap control and Wakeup control
+ *
+ * This register contains bits for various configuration options of
+ * the SD host controller. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XSDPS_HC_LED_MASK		0x00000001U /**< LED Control */
+#define XSDPS_HC_WIDTH_MASK		0x00000002U /**< Bus width */
+#define XSDPS_HC_BUS_WIDTH_4		0x00000002U
+#define XSDPS_HC_SPEED_MASK		0x00000004U /**< High Speed */
+#define XSDPS_HC_DMA_MASK		0x00000018U /**< DMA Mode Select */
+#define XSDPS_HC_DMA_SDMA_MASK		0x00000000U /**< SDMA Mode */
+#define XSDPS_HC_DMA_ADMA1_MASK		0x00000008U /**< ADMA1 Mode */
+#define XSDPS_HC_DMA_ADMA2_32_MASK	0x00000010U /**< ADMA2 Mode - 32 bit */
+#define XSDPS_HC_DMA_ADMA2_64_MASK	0x00000018U /**< ADMA2 Mode - 64 bit */
+#define XSDPS_HC_EXT_BUS_WIDTH		0x00000020U /**< Bus width - 8 bit */
+#define XSDPS_HC_CARD_DET_TL_MASK	0x00000040U /**< Card Detect Tst Lvl */
+#define XSDPS_HC_CARD_DET_SD_MASK	0x00000080U /**< Card Detect Sig Det */
+
+#define XSDPS_PC_BUS_PWR_MASK		0x00000001U /**< Bus Power Control */
+#define XSDPS_PC_BUS_VSEL_MASK		0x0000000EU /**< Bus Voltage Select */
+#define XSDPS_PC_BUS_VSEL_3V3_MASK	0x0000000EU /**< Bus Voltage 3.3V */
+#define XSDPS_PC_BUS_VSEL_3V0_MASK	0x0000000CU /**< Bus Voltage 3.0V */
+#define XSDPS_PC_BUS_VSEL_1V8_MASK	0x0000000AU /**< Bus Voltage 1.8V */
+#define XSDPS_PC_EMMC_HW_RST_MASK	0x00000010U /**< HW reset for eMMC */
+
+#define XSDPS_BGC_STP_REQ_MASK		0x00000001U /**< Block Gap Stop Req */
+#define XSDPS_BGC_CNT_REQ_MASK		0x00000002U /**< Block Gap Cont Req */
+#define XSDPS_BGC_RWC_MASK		0x00000004U /**< Block Gap Rd Wait */
+#define XSDPS_BGC_INTR_MASK		0x00000008U /**< Block Gap Intr */
+#define XSDPS_BGC_SPI_MODE_MASK		0x00000010U /**< Block Gap SPI Mode */
+#define XSDPS_BGC_BOOT_EN_MASK		0x00000020U /**< Block Gap Boot Enb */
+#define XSDPS_BGC_ALT_BOOT_EN_MASK	0x00000040U /**< Block Gap Alt BootEn */
+#define XSDPS_BGC_BOOT_ACK_MASK		0x00000080U /**< Block Gap Boot Ack */
+
+#define XSDPS_WC_WUP_ON_INTR_MASK	0x00000001U /**< Wakeup Card Intr */
+#define XSDPS_WC_WUP_ON_INSRT_MASK	0x00000002U /**< Wakeup Card Insert */
+#define XSDPS_WC_WUP_ON_REM_MASK	0x00000004U /**< Wakeup Card Removal */
+
+/* @} */
+
+/** @name Control Register - Clock control, Timeout control & Software reset
+ *
+ * This register contains bits for configuration options of clock, timeout and
+ * software reset.
+ * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits.
+ * @{
+ */
+
+#define XSDPS_CC_INT_CLK_EN_MASK		0x00000001U
+#define XSDPS_CC_INT_CLK_STABLE_MASK	0x00000002U
+#define XSDPS_CC_SD_CLK_EN_MASK			0x00000004U
+#define XSDPS_CC_SD_CLK_GEN_SEL_MASK		0x00000020U
+#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK	0x000000C0U
+#define XSDPS_CC_SDCLK_FREQ_SEL_MASK		0x0000FF00U
+#define XSDPS_CC_SDCLK_FREQ_D256_MASK		0x00008000U
+#define XSDPS_CC_SDCLK_FREQ_D128_MASK		0x00004000U
+#define XSDPS_CC_SDCLK_FREQ_D64_MASK		0x00002000U
+#define XSDPS_CC_SDCLK_FREQ_D32_MASK		0x00001000U
+#define XSDPS_CC_SDCLK_FREQ_D16_MASK		0x00000800U
+#define XSDPS_CC_SDCLK_FREQ_D8_MASK		0x00000400U
+#define XSDPS_CC_SDCLK_FREQ_D4_MASK		0x00000200U
+#define XSDPS_CC_SDCLK_FREQ_D2_MASK		0x00000100U
+#define XSDPS_CC_SDCLK_FREQ_BASE_MASK	0x00000000U
+#define XSDPS_CC_MAX_DIV_CNT			256U
+#define XSDPS_CC_EXT_MAX_DIV_CNT		2046U
+#define XSDPS_CC_EXT_DIV_SHIFT			6U
+
+#define XSDPS_TC_CNTR_VAL_MASK			0x0000000FU
+
+#define XSDPS_SWRST_ALL_MASK			0x00000001U
+#define XSDPS_SWRST_CMD_LINE_MASK		0x00000002U
+#define XSDPS_SWRST_DAT_LINE_MASK		0x00000004U
+
+#define XSDPS_CC_MAX_NUM_OF_DIV		9U
+#define XSDPS_CC_DIV_SHIFT		8U
+
+/* @} */
+
+/** @name SD Interrupt Registers
+ *
+ * <b> Normal and Error Interrupt Status Register </b>
+ * This register shows the normal and error interrupt status.
+ * Status enable register affects reads of this register.
+ * If Signal enable register is set and the corresponding status bit is set,
+ * interrupt is generated.
+ * Write to clear except
+ * Error_interrupt and Card_Interrupt bits - Read only
+ *
+ * <b> Normal and Error Interrupt Status Enable Register </b>
+ * Setting this register bits enables Interrupt status.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ * <b> Normal and Error Interrupt Signal Enable Register </b>
+ * This register is used to select which interrupt status is
+ * indicated to the Host System as the interrupt.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ * All three registers have same bit definitions
+ * @{
+ */
+
+#define XSDPS_INTR_CC_MASK		0x00000001U /**< Command Complete */
+#define XSDPS_INTR_TC_MASK		0x00000002U /**< Transfer Complete */
+#define XSDPS_INTR_BGE_MASK		0x00000004U /**< Block Gap Event */
+#define XSDPS_INTR_DMA_MASK		0x00000008U /**< DMA Interrupt */
+#define XSDPS_INTR_BWR_MASK		0x00000010U /**< Buffer Write Ready */
+#define XSDPS_INTR_BRR_MASK		0x00000020U /**< Buffer Read Ready */
+#define XSDPS_INTR_CARD_INSRT_MASK	0x00000040U /**< Card Insert */
+#define XSDPS_INTR_CARD_REM_MASK	0x00000080U /**< Card Remove */
+#define XSDPS_INTR_CARD_MASK		0x00000100U /**< Card Interrupt */
+#define XSDPS_INTR_INT_A_MASK		0x00000200U /**< INT A Interrupt */
+#define XSDPS_INTR_INT_B_MASK		0x00000400U /**< INT B Interrupt */
+#define XSDPS_INTR_INT_C_MASK		0x00000800U /**< INT C Interrupt */
+#define XSDPS_INTR_RE_TUNING_MASK	0x00001000U /**< Re-Tuning Interrupt */
+#define XSDPS_INTR_BOOT_ACK_RECV_MASK	0x00002000U /**< Boot Ack Recv
+							Interrupt */
+#define XSDPS_INTR_BOOT_TERM_MASK	0x00004000U /**< Boot Terminate
+							Interrupt */
+#define XSDPS_INTR_ERR_MASK		0x00008000U /**< Error Interrupt */
+#define XSDPS_NORM_INTR_ALL_MASK	0x0000FFFFU
+
+#define XSDPS_INTR_ERR_CT_MASK		0x00000001U /**< Command Timeout
+							Error */
+#define XSDPS_INTR_ERR_CCRC_MASK	0x00000002U /**< Command CRC Error */
+#define XSDPS_INTR_ERR_CEB_MASK		0x00000004U /**< Command End Bit
+							Error */
+#define XSDPS_INTR_ERR_CI_MASK		0x00000008U /**< Command Index Error */
+#define XSDPS_INTR_ERR_DT_MASK		0x00000010U /**< Data Timeout Error */
+#define XSDPS_INTR_ERR_DCRC_MASK	0x00000020U /**< Data CRC Error */
+#define XSDPS_INTR_ERR_DEB_MASK		0x00000040U /**< Data End Bit Error */
+#define XSDPS_INTR_ERR_CUR_LMT_MASK	0x00000080U /**< Current Limit Error */
+#define XSDPS_INTR_ERR_AUTO_CMD12_MASK	0x00000100U /**< Auto CMD12 Error */
+#define XSDPS_INTR_ERR_ADMA_MASK	0x00000200U /**< ADMA Error */
+#define XSDPS_INTR_ERR_TR_MASK		0x00001000U /**< Tuning Error */
+#define XSDPS_INTR_VEND_SPF_ERR_MASK	0x0000E000U /**< Vendor Specific
+							Error */
+#define XSDPS_ERROR_INTR_ALL_MASK	0x0000F3FFU /**< Mask for error bits */
+/* @} */
+
+/** @name Block Size and Block Count Register
+ *
+ * This register contains the block count for current transfer,
+ * block size and SDMA buffer size.
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_MASK		0x00000FFFU /**< Transfer Block Size */
+#define XSDPS_SDMA_BUFF_SIZE_MASK	0x00007000U /**< Host SDMA Buffer Size */
+#define XSDPS_BLK_SIZE_1024		0x400U
+#define XSDPS_BLK_SIZE_2048		0x800U
+#define XSDPS_BLK_CNT_MASK		0x0000FFFFU /**< Block Count for
+								Current Transfer */
+
+/* @} */
+
+/** @name Transfer Mode and Command Register
+ *
+ * The Transfer Mode register is used to control the data transfers and
+ * Command register is used for command generation
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_TM_DMA_EN_MASK		0x00000001U /**< DMA Enable */
+#define XSDPS_TM_BLK_CNT_EN_MASK	0x00000002U /**< Block Count Enable */
+#define XSDPS_TM_AUTO_CMD12_EN_MASK	0x00000004U /**< Auto CMD12 Enable */
+#define XSDPS_TM_DAT_DIR_SEL_MASK	0x00000010U /**< Data Transfer
+							Direction Select */
+#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK	0x00000020U /**< Multi/Single
+							Block Select */
+
+#define XSDPS_CMD_RESP_SEL_MASK		0x00000003U /**< Response Type
+							Select */
+#define XSDPS_CMD_RESP_NONE_MASK	0x00000000U /**< No Response */
+#define XSDPS_CMD_RESP_L136_MASK	0x00000001U /**< Response length 138 */
+#define XSDPS_CMD_RESP_L48_MASK		0x00000002U /**< Response length 48 */
+#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK	0x00000003U /**< Response length 48 &
+							check busy after
+							response */
+#define XSDPS_CMD_CRC_CHK_EN_MASK	0x00000008U /**< Command CRC Check
+							Enable */
+#define XSDPS_CMD_INX_CHK_EN_MASK	0x00000010U /**< Command Index Check
+							Enable */
+#define XSDPS_DAT_PRESENT_SEL_MASK	0x00000020U /**< Data Present Select */
+#define XSDPS_CMD_TYPE_MASK		0x000000C0U /**< Command Type */
+#define XSDPS_CMD_TYPE_NORM_MASK	0x00000000U /**< CMD Type - Normal */
+#define XSDPS_CMD_TYPE_SUSPEND_MASK	0x00000040U /**< CMD Type - Suspend */
+#define XSDPS_CMD_TYPE_RESUME_MASK	0x00000080U /**< CMD Type - Resume */
+#define XSDPS_CMD_TYPE_ABORT_MASK	0x000000C0U /**< CMD Type - Abort */
+#define XSDPS_CMD_MASK			0x00003F00U /**< Command Index Mask -
+							Set to CMD0-63,
+							AMCD0-63 */
+
+/* @} */
+
+/** @name Auto CMD Error Status Register
+ *
+ * This register is read only register which contains
+ * information about the error status of Auto CMD 12 and 23.
+ * Read Only
+ * @{
+ */
+#define XSDPS_AUTO_CMD12_NT_EX_MASK	0x0001U /**< Auto CMD12 Not
+							executed */
+#define XSDPS_AUTO_CMD_TOUT_MASK	0x0002U /**< Auto CMD Timeout
+							Error */
+#define XSDPS_AUTO_CMD_CRC_MASK		0x0004U /**< Auto CMD CRC Error */
+#define XSDPS_AUTO_CMD_EB_MASK		0x0008U /**< Auto CMD End Bit
+							Error */
+#define XSDPS_AUTO_CMD_IND_MASK		0x0010U /**< Auto CMD Index Error */
+#define XSDPS_AUTO_CMD_CNI_ERR_MASK	0x0080U /**< Command not issued by
+							Auto CMD12 Error */
+/* @} */
+
+/** @name Host Control2 Register
+ *
+ * This register contains extended configuration bits.
+ * Read Write
+ * @{
+ */
+#define XSDPS_HC2_UHS_MODE_MASK		0x0007U /**< UHS Mode select bits */
+#define XSDPS_HC2_UHS_MODE_SDR12_MASK	0x0000U /**< SDR12 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR25_MASK	0x0001U /**< SDR25 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR50_MASK	0x0002U /**< SDR50 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR104_MASK	0x0003U /**< SDR104 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_DDR50_MASK	0x0004U /**< DDR50 UHS Mode */
+#define XSDPS_HC2_1V8_EN_MASK		0x0008U /**< 1.8V Signal Enable */
+#define XSDPS_HC2_DRV_STR_SEL_MASK	0x0030U /**< Driver Strength
+							Selection */
+#define XSDPS_HC2_DRV_STR_B_MASK	0x0000U /**< Driver Strength B */
+#define XSDPS_HC2_DRV_STR_A_MASK	0x0010U /**< Driver Strength A */
+#define XSDPS_HC2_DRV_STR_C_MASK	0x0020U /**< Driver Strength C */
+#define XSDPS_HC2_DRV_STR_D_MASK	0x0030U /**< Driver Strength D */
+#define XSDPS_HC2_EXEC_TNG_MASK		0x0040U /**< Execute Tuning */
+#define XSDPS_HC2_SAMP_CLK_SEL_MASK	0x0080U /**< Sampling Clock
+							Selection */
+#define XSDPS_HC2_ASYNC_INTR_EN_MASK	0x4000U /**< Asynchronous Interrupt
+							Enable */
+#define XSDPS_HC2_PRE_VAL_EN_MASK	0x8000U /**< Preset Value Enable */
+
+/* @} */
+
+/** @name Capabilities Register
+ *
+ * Capabilities register is a read only register which contains
+ * information about the host controller.
+ * Sufficient if read once after power on.
+ * Read Only
+ * @{
+ */
+#define XSDPS_CAP_TOUT_CLK_FREQ_MASK	0x0000003FU /**< Timeout clock freq
+							select */
+#define XSDPS_CAP_TOUT_CLK_UNIT_MASK	0x00000080U /**< Timeout clock unit -
+							MHz/KHz */
+#define XSDPS_CAP_MAX_BLK_LEN_MASK	0x00030000U /**< Max block length */
+#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK	0x00000000U /**< Max block 512 bytes */
+#define XSDPS_CAP_MAX_BL_LN_1024_MASK	0x00010000U /**< Max block 1024 bytes */
+#define XSDPS_CAP_MAX_BL_LN_2048_MASK	0x00020000U /**< Max block 2048 bytes */
+#define XSDPS_CAP_MAX_BL_LN_4096_MASK	0x00030000U /**< Max block 4096 bytes */
+
+#define XSDPS_CAP_EXT_MEDIA_BUS_MASK	0x00040000U /**< Extended media bus */
+#define XSDPS_CAP_ADMA2_MASK		0x00080000U /**< ADMA2 support */
+#define XSDPS_CAP_HIGH_SPEED_MASK	0x00200000U /**< High speed support */
+#define XSDPS_CAP_SDMA_MASK		0x00400000U /**< SDMA support */
+#define XSDPS_CAP_SUSP_RESUME_MASK	0x00800000U /**< Suspend/Resume
+							support */
+#define XSDPS_CAP_VOLT_3V3_MASK		0x01000000U /**< 3.3V support */
+#define XSDPS_CAP_VOLT_3V0_MASK		0x02000000U /**< 3.0V support */
+#define XSDPS_CAP_VOLT_1V8_MASK		0x04000000U /**< 1.8V support */
+
+#define XSDPS_CAP_SYS_BUS_64_MASK	0x10000000U /**< 64 bit system bus
+							support */
+/* Spec 2.0 */
+#define XSDPS_CAP_INTR_MODE_MASK	0x08000000U /**< Interrupt mode
+							support */
+#define XSDPS_CAP_SPI_MODE_MASK		0x20000000U /**< SPI mode */
+#define XSDPS_CAP_SPI_BLOCK_MODE_MASK	0x40000000U /**< SPI block mode */
+
+
+/* Spec 3.0 */
+#define XSDPS_CAPS_ASYNC_INTR_MASK	0x20000000U /**< Async Interrupt
+							support */
+#define XSDPS_CAPS_SLOT_TYPE_MASK	0xC0000000U /**< Slot Type */
+#define XSDPS_CAPS_REM_CARD			0x00000000U /**< Removable Slot */
+#define XSDPS_CAPS_EMB_SLOT			0x40000000U /**< Embedded Slot */
+#define XSDPS_CAPS_SHR_BUS			0x80000000U /**< Shared Bus Slot */
+
+#define XSDPS_ECAPS_SDR50_MASK		0x00000001U /**< SDR50 Mode support */
+#define XSDPS_ECAPS_SDR104_MASK		0x00000002U /**< SDR104 Mode support */
+#define XSDPS_ECAPS_DDR50_MASK		0x00000004U /**< DDR50 Mode support */
+#define XSDPS_ECAPS_DRV_TYPE_A_MASK	0x00000010U /**< DriverType A support */
+#define XSDPS_ECAPS_DRV_TYPE_C_MASK	0x00000020U /**< DriverType C support */
+#define XSDPS_ECAPS_DRV_TYPE_D_MASK	0x00000040U /**< DriverType D support */
+#define XSDPS_ECAPS_TMR_CNT_MASK	0x00000F00U /**< Timer Count for
+							Re-tuning */
+#define XSDPS_ECAPS_USE_TNG_SDR50_MASK	0x00002000U /**< SDR50 Mode needs
+							tuning */
+#define XSDPS_ECAPS_RE_TNG_MODES_MASK	0x0000C000U /**< Re-tuning modes
+							support */
+#define XSDPS_ECAPS_RE_TNG_MODE1_MASK	0x00000000U /**< Re-tuning mode 1 */
+#define XSDPS_ECAPS_RE_TNG_MODE2_MASK	0x00004000U /**< Re-tuning mode 2 */
+#define XSDPS_ECAPS_RE_TNG_MODE3_MASK	0x00008000U /**< Re-tuning mode 3 */
+#define XSDPS_ECAPS_CLK_MULT_MASK	0x00FF0000U /**< Clock Multiplier value
+							for Programmable clock
+							mode */
+#define XSDPS_ECAPS_SPI_MODE_MASK	0x01000000U /**< SPI mode */
+#define XSDPS_ECAPS_SPI_BLK_MODE_MASK	0x02000000U /**< SPI block mode */
+
+/* @} */
+
+/** @name Present State Register
+ *
+ * Gives the current status of the host controller
+ * Read Only
+ * @{
+ */
+
+#define XSDPS_PSR_INHIBIT_CMD_MASK	0x00000001U /**< Command inhibit - CMD */
+#define XSDPS_PSR_INHIBIT_DAT_MASK	0x00000002U /**< Command Inhibit - DAT */
+#define XSDPS_PSR_DAT_ACTIVE_MASK	0x00000004U /**< DAT line active */
+#define XSDPS_PSR_RE_TUNING_REQ_MASK	0x00000008U /**< Re-tuning request */
+#define XSDPS_PSR_WR_ACTIVE_MASK	0x00000100U /**< Write transfer active */
+#define XSDPS_PSR_RD_ACTIVE_MASK	0x00000200U /**< Read transfer active */
+#define XSDPS_PSR_BUFF_WR_EN_MASK	0x00000400U /**< Buffer write enable */
+#define XSDPS_PSR_BUFF_RD_EN_MASK	0x00000800U /**< Buffer read enable */
+#define XSDPS_PSR_CARD_INSRT_MASK	0x00010000U /**< Card inserted */
+#define XSDPS_PSR_CARD_STABLE_MASK	0x00020000U /**< Card state stable */
+#define XSDPS_PSR_CARD_DPL_MASK		0x00040000U /**< Card detect pin level */
+#define XSDPS_PSR_WPS_PL_MASK		0x00080000U /**< Write protect switch
+								pin level */
+#define XSDPS_PSR_DAT30_SG_LVL_MASK	0x00F00000U /**< Data 3:0 signal lvl */
+#define XSDPS_PSR_CMD_SG_LVL_MASK	0x01000000U /**< Cmd Line signal lvl */
+#define XSDPS_PSR_DAT74_SG_LVL_MASK	0x1E000000U /**< Data 7:4 signal lvl */
+
+/* @} */
+
+/** @name Maximum Current Capablities Register
+ *
+ * This register is read only register which contains
+ * information about current capabilities at each voltage levels.
+ * Read Only
+ * @{
+ */
+#define XSDPS_MAX_CUR_CAPS_1V8_MASK	0x00000F00U /**< Maximum Current
+							Capability at 1.8V */
+#define XSDPS_MAX_CUR_CAPS_3V0_MASK	0x000000F0U /**< Maximum Current
+							Capability at 3.0V */
+#define XSDPS_MAX_CUR_CAPS_3V3_MASK	0x0000000FU /**< Maximum Current
+							Capability at 3.3V */
+/* @} */
+
+
+/** @name Force Event for Auto CMD Error Status Register
+ *
+ * This register is write only register which contains
+ * control bits to generate events for Auto CMD error status.
+ * Write Only
+ * @{
+ */
+#define XSDPS_FE_AUTO_CMD12_NT_EX_MASK	0x0001U /**< Auto CMD12 Not
+							executed */
+#define XSDPS_FE_AUTO_CMD_TOUT_MASK	0x0002U /**< Auto CMD Timeout
+							Error */
+#define XSDPS_FE_AUTO_CMD_CRC_MASK	0x0004U /**< Auto CMD CRC Error */
+#define XSDPS_FE_AUTO_CMD_EB_MASK	0x0008U /**< Auto CMD End Bit
+							Error */
+#define XSDPS_FE_AUTO_CMD_IND_MASK	0x0010U /**< Auto CMD Index Error */
+#define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK	0x0080U /**< Command not issued by
+							Auto CMD12 Error */
+/* @} */
+
+
+
+/** @name Force Event for Error Interrupt Status Register
+ *
+ * This register is write only register which contains
+ * control bits to generate events of error interrupt status register.
+ * Write Only
+ * @{
+ */
+#define XSDPS_FE_INTR_ERR_CT_MASK	0x0001U /**< Command Timeout
+							Error */
+#define XSDPS_FE_INTR_ERR_CCRC_MASK	0x0002U /**< Command CRC Error */
+#define XSDPS_FE_INTR_ERR_CEB_MASK	0x0004U /**< Command End Bit
+							Error */
+#define XSDPS_FE_INTR_ERR_CI_MASK	0x0008U /**< Command Index Error */
+#define XSDPS_FE_INTR_ERR_DT_MASK	0x0010U /**< Data Timeout Error */
+#define XSDPS_FE_INTR_ERR_DCRC_MASK	0x0020U /**< Data CRC Error */
+#define XSDPS_FE_INTR_ERR_DEB_MASK	0x0040U /**< Data End Bit Error */
+#define XSDPS_FE_INTR_ERR_CUR_LMT_MASK	0x0080U /**< Current Limit Error */
+#define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK	0x0100U /**< Auto CMD Error */
+#define XSDPS_FE_INTR_ERR_ADMA_MASK	0x0200U /**< ADMA Error */
+#define XSDPS_FE_INTR_ERR_TR_MASK	0x1000U /**< Target Reponse */
+#define XSDPS_FE_INTR_VEND_SPF_ERR_MASK	0xE000U /**< Vendor Specific
+							Error */
+
+/* @} */
+
+/** @name ADMA Error Status Register
+ *
+ * This register is read only register which contains
+ * status information about ADMA errors.
+ * Read Only
+ * @{
+ */
+#define XSDPS_ADMA_ERR_MM_LEN_MASK	0x04U /**< ADMA Length Mismatch
+							Error */
+#define XSDPS_ADMA_ERR_STATE_MASK	0x03U /**< ADMA Error State */
+#define XSDPS_ADMA_ERR_STATE_STOP_MASK	0x00U /**< ADMA Error State
+							STOP */
+#define XSDPS_ADMA_ERR_STATE_FDS_MASK	0x01U /**< ADMA Error State
+							FDS */
+#define XSDPS_ADMA_ERR_STATE_TFR_MASK	0x03U /**< ADMA Error State
+							TFR */
+/* @} */
+
+/** @name Preset Values Register
+ *
+ * This register is read only register which contains
+ * preset values for each of speed modes.
+ * Read Only
+ * @{
+ */
+#define XSDPS_PRE_VAL_SDCLK_FSEL_MASK	0x03FFU /**< SDCLK Frequency
+							Select Value */
+#define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK	0x0400U /**< Clock Generator
+							Mode Select */
+#define XSDPS_PRE_VAL_DRV_STR_SEL_MASK	0xC000U /**< Driver Strength
+							Select Value */
+
+/* @} */
+
+/** @name Slot Interrupt Status Register
+ *
+ * This register is read only register which contains
+ * interrupt slot signal for each slot.
+ * Read Only
+ * @{
+ */
+#define XSDPS_SLOT_INTR_STS_INT_MASK	0x0007U /**< Interrupt Signal
+							mask */
+
+/* @} */
+
+/** @name Host Controller Version Register
+ *
+ * This register is read only register which contains
+ * Host Controller and Vendor Specific version.
+ * Read Only
+ * @{
+ */
+#define XSDPS_HC_VENDOR_VER		0xFF00U /**< Vendor
+							Specification
+							version mask */
+#define XSDPS_HC_SPEC_VER_MASK		0x00FFU /**< Host
+							Specification
+							version mask */
+#define XSDPS_HC_SPEC_V3		0x0002U
+#define XSDPS_HC_SPEC_V2		0x0001U
+#define XSDPS_HC_SPEC_V1		0x0000U
+
+/** @name Block size mask for 512 bytes
+ *
+ * Block size mask for 512 bytes - This is the default block size.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_512_MASK	0x200U
+
+/* @} */
+
+/** @name Commands
+ *
+ * Constant definitions for commands and response related to SD
+ * @{
+ */
+
+#define XSDPS_APP_CMD_PREFIX	 0x8000U
+#define CMD0	 0x0000U
+#define CMD1	 0x0100U
+#define CMD2	 0x0200U
+#define CMD3	 0x0300U
+#define CMD4	 0x0400U
+#define CMD5	 0x0500U
+#define CMD6	 0x0600U
+#define ACMD6	(XSDPS_APP_CMD_PREFIX + 0x0600U)
+#define CMD7	 0x0700U
+#define CMD8	 0x0800U
+#define CMD9	 0x0900U
+#define CMD10	 0x0A00U
+#define CMD11	 0x0B00U
+#define CMD12	 0x0C00U
+#define ACMD13	 (XSDPS_APP_CMD_PREFIX + 0x0D00U)
+#define CMD16	 0x1000U
+#define CMD17	 0x1100U
+#define CMD18	 0x1200U
+#define CMD19	 0x1300U
+#define CMD21	 0x1500U
+#define CMD23	 0x1700U
+#define ACMD23	 (XSDPS_APP_CMD_PREFIX + 0x1700U)
+#define CMD24	 0x1800U
+#define CMD25	 0x1900U
+#define CMD41	 0x2900U
+#define ACMD41	 (XSDPS_APP_CMD_PREFIX + 0x2900U)
+#define ACMD42	 (XSDPS_APP_CMD_PREFIX + 0x2A00U)
+#define ACMD51	 (XSDPS_APP_CMD_PREFIX + 0x3300U)
+#define CMD52	 0x3400U
+#define CMD55	 0x3700U
+#define CMD58	 0x3A00U
+
+#define RESP_NONE	(u32)XSDPS_CMD_RESP_NONE_MASK
+#define RESP_R1		(u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \
+			(u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R1B	(u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+			(u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R2		(u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK
+#define RESP_R3		(u32)XSDPS_CMD_RESP_L48_MASK
+
+#define RESP_R6		(u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+			(u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+/* @} */
+
+/* Card Interface Conditions Definitions */
+#define XSDPS_CIC_CHK_PATTERN	0xAAU
+#define XSDPS_CIC_VOLT_MASK	(0xFU<<8)
+#define XSDPS_CIC_VOLT_2V7_3V6	(1U<<8)
+#define XSDPS_CIC_VOLT_LOW	(1U<<9)
+
+/* Operation Conditions Register Definitions */
+#define XSDPS_OCR_PWRUP_STS	(1U<<31)
+#define XSDPS_OCR_CC_STS	(1U<<30)
+#define XSDPS_OCR_S18		(1U<<24)
+#define XSDPS_OCR_3V5_3V6	(1U<<23)
+#define XSDPS_OCR_3V4_3V5	(1U<<22)
+#define XSDPS_OCR_3V3_3V4	(1U<<21)
+#define XSDPS_OCR_3V2_3V3	(1U<<20)
+#define XSDPS_OCR_3V1_3V2	(1U<<19)
+#define XSDPS_OCR_3V0_3V1	(1U<<18)
+#define XSDPS_OCR_2V9_3V0	(1U<<17)
+#define XSDPS_OCR_2V8_2V9	(1U<<16)
+#define XSDPS_OCR_2V7_2V8	(1U<<15)
+#define XSDPS_OCR_1V7_1V95	(1U<<7)
+#define XSDPS_OCR_HIGH_VOL	0x00FF8000U
+#define XSDPS_OCR_LOW_VOL	0x00000080U
+
+/* SD Card Configuration Register Definitions */
+#define XSDPS_SCR_REG_LEN		8U
+#define XSDPS_SCR_STRUCT_MASK		(0xFU<<28)
+#define XSDPS_SCR_SPEC_MASK		(0xFU<<24)
+#define XSDPS_SCR_SPEC_1V0		0U
+#define XSDPS_SCR_SPEC_1V1		(1U<<24)
+#define XSDPS_SCR_SPEC_2V0_3V0		(2U<<24)
+#define XSDPS_SCR_MEM_VAL_AF_ERASE	(1U<<23)
+#define XSDPS_SCR_SEC_SUPP_MASK		(7U<<20)
+#define XSDPS_SCR_SEC_SUPP_NONE		0U
+#define XSDPS_SCR_SEC_SUPP_1V1		(2U<<20)
+#define XSDPS_SCR_SEC_SUPP_2V0		(3U<<20)
+#define XSDPS_SCR_SEC_SUPP_3V0		(4U<<20)
+#define XSDPS_SCR_BUS_WIDTH_MASK	(0xFU<<16)
+#define XSDPS_SCR_BUS_WIDTH_1		(1U<<16)
+#define XSDPS_SCR_BUS_WIDTH_4		(4U<<16)
+#define XSDPS_SCR_SPEC3_MASK		(1U<<12)
+#define XSDPS_SCR_SPEC3_2V0		0U
+#define XSDPS_SCR_SPEC3_3V0		(1U<<12)
+#define XSDPS_SCR_CMD_SUPP_MASK		0x3U
+#define XSDPS_SCR_CMD23_SUPP		(1U<<1)
+#define XSDPS_SCR_CMD20_SUPP		(1U<<0)
+
+/* Card Status Register Definitions */
+#define XSDPS_CD_STS_OUT_OF_RANGE	(1U<<31)
+#define XSDPS_CD_STS_ADDR_ERR		(1U<<30)
+#define XSDPS_CD_STS_BLK_LEN_ERR	(1U<<29)
+#define XSDPS_CD_STS_ER_SEQ_ERR		(1U<<28)
+#define XSDPS_CD_STS_ER_PRM_ERR		(1U<<27)
+#define XSDPS_CD_STS_WP_VIO		(1U<<26)
+#define XSDPS_CD_STS_IS_LOCKED		(1U<<25)
+#define XSDPS_CD_STS_LOCK_UNLOCK_FAIL	(1U<<24)
+#define XSDPS_CD_STS_CMD_CRC_ERR	(1U<<23)
+#define XSDPS_CD_STS_ILGL_CMD		(1U<<22)
+#define XSDPS_CD_STS_CARD_ECC_FAIL	(1U<<21)
+#define XSDPS_CD_STS_CC_ERR		(1U<<20)
+#define XSDPS_CD_STS_ERR		(1U<<19)
+#define XSDPS_CD_STS_CSD_OVRWR		(1U<<16)
+#define XSDPS_CD_STS_WP_ER_SKIP		(1U<<15)
+#define XSDPS_CD_STS_CARD_ECC_DIS	(1U<<14)
+#define XSDPS_CD_STS_ER_RST		(1U<<13)
+#define XSDPS_CD_STS_CUR_STATE		(0xFU<<9)
+#define XSDPS_CD_STS_RDY_FOR_DATA	(1U<<8)
+#define XSDPS_CD_STS_APP_CMD		(1U<<5)
+#define XSDPS_CD_STS_AKE_SEQ_ERR	(1U<<2)
+
+/* Switch Function Definitions CMD6 */
+#define XSDPS_SWITCH_SD_RESP_LEN	64U
+
+#define XSDPS_SWITCH_FUNC_SWITCH	(1U<<31)
+#define XSDPS_SWITCH_FUNC_CHECK		0U
+
+#define XSDPS_MODE_FUNC_GRP1		1U
+#define XSDPS_MODE_FUNC_GRP2		2U
+#define XSDPS_MODE_FUNC_GRP3		3U
+#define XSDPS_MODE_FUNC_GRP4		4U
+#define XSDPS_MODE_FUNC_GRP5		5U
+#define XSDPS_MODE_FUNC_GRP6		6U
+
+#define XSDPS_FUNC_GRP_DEF_VAL		0xFU
+#define XSDPS_FUNC_ALL_GRP_DEF_VAL	0xFFFFFFU
+
+#define XSDPS_ACC_MODE_DEF_SDR12	0U
+#define XSDPS_ACC_MODE_HS_SDR25		1U
+#define XSDPS_ACC_MODE_SDR50		2U
+#define XSDPS_ACC_MODE_SDR104		3U
+#define XSDPS_ACC_MODE_DDR50		4U
+
+#define XSDPS_CMD_SYS_ARG_SHIFT		4U
+#define XSDPS_CMD_SYS_DEF		0U
+#define XSDPS_CMD_SYS_eC		1U
+#define XSDPS_CMD_SYS_OTP		3U
+#define XSDPS_CMD_SYS_ASSD		4U
+#define XSDPS_CMD_SYS_VEND		5U
+
+#define XSDPS_DRV_TYPE_ARG_SHIFT	8U
+#define XSDPS_DRV_TYPE_B		0U
+#define XSDPS_DRV_TYPE_A		1U
+#define XSDPS_DRV_TYPE_C		2U
+#define XSDPS_DRV_TYPE_D		3U
+
+#define XSDPS_CUR_LIM_ARG_SHIFT		12U
+#define XSDPS_CUR_LIM_200		0U
+#define XSDPS_CUR_LIM_400		1U
+#define XSDPS_CUR_LIM_600		2U
+#define XSDPS_CUR_LIM_800		3U
+
+#define CSD_SPEC_VER_MASK		0x3C0000U
+#define READ_BLK_LEN_MASK		0x00000F00U
+#define C_SIZE_MULT_MASK		0x00000380U
+#define C_SIZE_LOWER_MASK		0xFFC00000U
+#define C_SIZE_UPPER_MASK		0x00000003U
+#define CSD_STRUCT_MASK			0x00C00000U
+#define CSD_V2_C_SIZE_MASK		0x3FFFFF00U
+
+/* EXT_CSD field definitions */
+#define XSDPS_EXT_CSD_SIZE		512U
+
+#define EXT_CSD_WR_REL_PARAM_EN		(1U<<2)
+
+#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS    (0x40U)
+#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS   (0x10U)
+#define EXT_CSD_BOOT_WP_B_PERM_WP_EN    (0x04U)
+#define EXT_CSD_BOOT_WP_B_PWR_WP_EN     (0x01U)
+
+#define EXT_CSD_PART_CONFIG_ACC_MASK    (0x7U)
+#define EXT_CSD_PART_CONFIG_ACC_BOOT0   (0x1U)
+#define EXT_CSD_PART_CONFIG_ACC_RPMB    (0x3U)
+#define EXT_CSD_PART_CONFIG_ACC_GP0     (0x4U)
+
+#define EXT_CSD_PART_SUPPORT_PART_EN    (0x1U)
+
+#define EXT_CSD_CMD_SET_NORMAL          (1U<<0)
+#define EXT_CSD_CMD_SET_SECURE          (1U<<1)
+#define EXT_CSD_CMD_SET_CPSECURE        (1U<<2)
+
+#define EXT_CSD_CARD_TYPE_26    	(1U<<0)  /* Card can run at 26MHz */
+#define EXT_CSD_CARD_TYPE_52    	(1U<<1)  /* Card can run at 52MHz */
+#define EXT_CSD_CARD_TYPE_MASK  	0x3FU    /* Mask out reserved bits */
+#define EXT_CSD_CARD_TYPE_DDR_1_8V	(1U<<2)   /* Card can run at 52MHz */
+                                             /* DDR mode @1.8V or 3V I/O */
+#define EXT_CSD_CARD_TYPE_DDR_1_2V	(1U<<3)   /* Card can run at 52MHz */
+                                             /* DDR mode @1.2V I/O */
+#define EXT_CSD_CARD_TYPE_DDR_52	(EXT_CSD_CARD_TYPE_DDR_1_8V  \
+                                        | EXT_CSD_CARD_TYPE_DDR_1_2V)
+#define EXT_CSD_CARD_TYPE_SDR_1_8V      (1U<<4)  /* Card can run at 200MHz */
+#define EXT_CSD_CARD_TYPE_SDR_1_2V      (1U<<5)  /* Card can run at 200MHz */
+                                                /* SDR mode @1.2V I/O */
+#define EXT_CSD_BUS_WIDTH_BYTE			183U
+#define EXT_CSD_BUS_WIDTH_1_BIT			0U	/* Card is in 1 bit mode */
+#define EXT_CSD_BUS_WIDTH_4_BIT			1U	/* Card is in 4 bit mode */
+#define EXT_CSD_BUS_WIDTH_8_BIT			2U	/* Card is in 8 bit mode */
+#define EXT_CSD_BUS_WIDTH_DDR_4_BIT		5U	/* Card is in 4 bit DDR mode */
+#define EXT_CSD_BUS_WIDTH_DDR_8_BIT		6U	/* Card is in 8 bit DDR mode */
+
+#define EXT_CSD_HS_TIMING_BYTE		185U
+#define EXT_CSD_HS_TIMING_DEF		0U
+#define EXT_CSD_HS_TIMING_HIGH		1U	/* Card is in high speed mode */
+#define EXT_CSD_HS_TIMING_HS200		2U	/* Card is in HS200 mode */
+
+#define EXT_CSD_RST_N_FUN_BYTE		162U
+#define EXT_CSD_RST_N_FUN_TEMP_DIS	0U	/* RST_n signal is temporarily disabled */
+#define EXT_CSD_RST_N_FUN_PERM_EN	1U	/* RST_n signal is permanently enabled */
+#define EXT_CSD_RST_N_FUN_PERM_DIS	2U	/* RST_n signal is permanently disabled */
+
+#define XSDPS_EXT_CSD_CMD_SET		0U
+#define XSDPS_EXT_CSD_SET_BITS		1U
+#define XSDPS_EXT_CSD_CLR_BITS		2U
+#define XSDPS_EXT_CSD_WRITE_BYTE	3U
+
+#define XSDPS_MMC_DEF_SPEED_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					| ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+					| ((u32)EXT_CSD_HS_TIMING_DEF << 8))
+
+#define XSDPS_MMC_HIGH_SPEED_ARG	(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+					 | ((u32)EXT_CSD_HS_TIMING_HIGH << 8))
+
+#define XSDPS_MMC_HS200_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+					 | ((u32)EXT_CSD_HS_TIMING_HS200 << 8))
+
+#define XSDPS_MMC_1_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WITH_1_BIT << 8))
+
+#define XSDPS_MMC_4_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8))
+
+#define XSDPS_MMC_8_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8))
+
+#define XSDPS_MMC_DDR_4_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8))
+
+#define XSDPS_MMC_DDR_8_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8))
+
+#define XSDPS_MMC_RST_FUN_EN_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \
+					 | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8))
+
+#define XSDPS_MMC_DELAY_FOR_SWITCH	1000U
+
+/* @} */
+
+/* @400KHz, in usec */
+#define XSDPS_74CLK_DELAY	2960U
+#define XSDPS_100CLK_DELAY	4000U
+#define XSDPS_INIT_DELAY	10000U
+
+#define XSDPS_DEF_VOLT_LVL	XSDPS_PC_BUS_VSEL_3V0_MASK
+#define XSDPS_CARD_DEF_ADDR	0x1234U
+
+#define XSDPS_CARD_SD		1U
+#define XSDPS_CARD_MMC		2U
+#define XSDPS_CARD_SDIO		3U
+#define XSDPS_CARD_SDCOMBO	4U
+#define XSDPS_CHIP_EMMC		5U
+
+
+/** @name ADMA2 Descriptor related definitions
+ *
+ * ADMA2 Descriptor related definitions
+ * @{
+ */
+
+#define XSDPS_DESC_MAX_LENGTH 65536U
+
+#define XSDPS_DESC_VALID     	(0x1U << 0)
+#define XSDPS_DESC_END       	(0x1U << 1)
+#define XSDPS_DESC_INT       	(0x1U << 2)
+#define XSDPS_DESC_TRAN  	(0x2U << 4)
+
+/* @} */
+
+/* For changing clock frequencies */
+#define XSDPS_CLK_400_KHZ		400000U		/**< 400 KHZ */
+#define XSDPS_CLK_50_MHZ		50000000U	/**< 50 MHZ */
+#define XSDPS_CLK_52_MHZ		52000000U	/**< 52 MHZ */
+#define XSDPS_SD_VER_1_0		0x1U		/**< SD ver 1 */
+#define XSDPS_SD_VER_2_0		0x2U		/**< SD ver 2 */
+#define XSDPS_SCR_BLKCNT	1U
+#define XSDPS_SCR_BLKSIZE	8U
+#define XSDPS_1_BIT_WIDTH	0x1U
+#define XSDPS_4_BIT_WIDTH	0x2U
+#define XSDPS_8_BIT_WIDTH	0x3U
+#define XSDPS_UHS_SPEED_MODE_SDR12	0x0U
+#define XSDPS_UHS_SPEED_MODE_SDR25	0x1U
+#define XSDPS_UHS_SPEED_MODE_SDR50	0x2U
+#define XSDPS_UHS_SPEED_MODE_SDR104	0x3U
+#define XSDPS_UHS_SPEED_MODE_DDR50	0x4U
+#define XSDPS_HIGH_SPEED_MODE		0x5U
+#define XSDPS_DEFAULT_SPEED_MODE	0x6U
+#define XSDPS_HS200_MODE			0x7U
+#define XSDPS_DDR52_MODE			0x4U
+#define XSDPS_SWITCH_CMD_BLKCNT		1U
+#define XSDPS_SWITCH_CMD_BLKSIZE	64U
+#define XSDPS_SWITCH_CMD_HS_GET		0x00FFFFF0U
+#define XSDPS_SWITCH_CMD_HS_SET		0x80FFFFF1U
+#define XSDPS_SWITCH_CMD_SDR12_SET		0x80FFFFF0U
+#define XSDPS_SWITCH_CMD_SDR25_SET		0x80FFFFF1U
+#define XSDPS_SWITCH_CMD_SDR50_SET		0x80FFFFF2U
+#define XSDPS_SWITCH_CMD_SDR104_SET		0x80FFFFF3U
+#define XSDPS_SWITCH_CMD_DDR50_SET		0x80FFFFF4U
+#define XSDPS_EXT_CSD_CMD_BLKCNT	1U
+#define XSDPS_EXT_CSD_CMD_BLKSIZE	512U
+#define XSDPS_TUNING_CMD_BLKCNT		1U
+#define XSDPS_TUNING_CMD_BLKSIZE	64U
+
+#define XSDPS_HIGH_SPEED_MAX_CLK	50000000U
+#define XSDPS_UHS_SDR104_MAX_CLK	208000000U
+#define XSDPS_UHS_SDR50_MAX_CLK		100000000U
+#define XSDPS_UHS_DDR50_MAX_CLK		50000000U
+#define XSDPS_UHS_SDR25_MAX_CLK		50000000U
+#define XSDPS_UHS_SDR12_MAX_CLK		25000000U
+
+#define SD_DRIVER_TYPE_B	0x01U
+#define SD_DRIVER_TYPE_A	0x02U
+#define SD_DRIVER_TYPE_C	0x04U
+#define SD_DRIVER_TYPE_D	0x08U
+#define SD_SET_CURRENT_LIMIT_200	0U
+#define SD_SET_CURRENT_LIMIT_400	1U
+#define SD_SET_CURRENT_LIMIT_600	2U
+#define SD_SET_CURRENT_LIMIT_800	3U
+
+#define SD_MAX_CURRENT_200	(1U << SD_SET_CURRENT_LIMIT_200)
+#define SD_MAX_CURRENT_400	(1U << SD_SET_CURRENT_LIMIT_400)
+#define SD_MAX_CURRENT_600	(1U << SD_SET_CURRENT_LIMIT_600)
+#define SD_MAX_CURRENT_800	(1U << SD_SET_CURRENT_LIMIT_800)
+
+#define XSDPS_SD_SDR12_MAX_CLK	25000000U
+#define XSDPS_SD_SDR25_MAX_CLK	50000000U
+#define XSDPS_SD_SDR50_MAX_CLK	100000000U
+#define XSDPS_SD_DDR50_MAX_CLK	50000000U
+#define XSDPS_SD_SDR104_MAX_CLK	208000000U
+#define XSDPS_MMC_HS200_MAX_CLK	200000000U
+#define XSDPS_MMC_HSD_MAX_CLK	52000000U
+#define XSDPS_MMC_DDR_MAX_CLK	52000000U
+
+#define XSDPS_CARD_STATE_IDLE		0U
+#define XSDPS_CARD_STATE_RDY		1U
+#define XSDPS_CARD_STATE_IDEN		2U
+#define XSDPS_CARD_STATE_STBY		3U
+#define XSDPS_CARD_STATE_TRAN		4U
+#define XSDPS_CARD_STATE_DATA		5U
+#define XSDPS_CARD_STATE_RCV		6U
+#define XSDPS_CARD_STATE_PROG		7U
+#define XSDPS_CARD_STATE_DIS		8U
+#define XSDPS_CARD_STATE_BTST		9U
+#define XSDPS_CARD_STATE_SLP		10U
+
+#define XSDPS_SLOT_REM			0U
+#define XSDPS_SLOT_EMB			1U
+
+#define XSDPS_WIDTH_8		8U
+#define XSDPS_WIDTH_4		4U
+
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+#define SD0_ITAPDLY_SEL_MASK		0x000000FFU
+#define SD0_OTAPDLY_SEL_MASK		0x0000003FU
+#define SD1_ITAPDLY_SEL_MASK		0x00FF0000U
+#define SD1_OTAPDLY_SEL_MASK		0x003F0000U
+#define SD_DLL_CTRL 				0x00000358U
+#define SD_ITAPDLY					0x00000314U
+#define SD_OTAPDLY					0x00000318U
+#define SD0_DLL_RST					0x00000004U
+#define SD1_DLL_RST					0x00040000U
+#define SD0_ITAPCHGWIN				0x00000200U
+#define SD0_ITAPDLYENA				0x00000100U
+#define SD0_OTAPDLYENA				0x00000040U
+#define SD1_ITAPCHGWIN				0x02000000U
+#define SD1_ITAPDLYENA				0x01000000U
+#define SD1_OTAPDLYENA				0x00400000U
+
+#define SD0_OTAPDLYSEL_HS200_B0		0x00000003U
+#define SD0_OTAPDLYSEL_HS200_B2		0x00000002U
+#define SD0_ITAPDLYSEL_SD50			0x00000014U
+#define SD0_OTAPDLYSEL_SD50			0x00000003U
+#define SD0_ITAPDLYSEL_SD_DDR50		0x0000003DU
+#define SD0_ITAPDLYSEL_EMMC_DDR50	0x00000012U
+#define SD0_OTAPDLYSEL_SD_DDR50		0x00000004U
+#define SD0_OTAPDLYSEL_EMMC_DDR50	0x00000006U
+#define SD0_ITAPDLYSEL_HSD			0x00000015U
+#define SD0_OTAPDLYSEL_SD_HSD		0x00000005U
+#define SD0_OTAPDLYSEL_EMMC_HSD		0x00000006U
+
+#define SD1_OTAPDLYSEL_HS200_B0		0x00030000U
+#define SD1_OTAPDLYSEL_HS200_B2		0x00020000U
+#define SD1_ITAPDLYSEL_SD50			0x00140000U
+#define SD1_OTAPDLYSEL_SD50			0x00030000U
+#define SD1_ITAPDLYSEL_SD_DDR50		0x003D0000U
+#define SD1_ITAPDLYSEL_EMMC_DDR50	0x00120000U
+#define SD1_OTAPDLYSEL_SD_DDR50		0x00040000U
+#define SD1_OTAPDLYSEL_EMMC_DDR50	0x00060000U
+#define SD1_ITAPDLYSEL_HSD			0x00150000U
+#define SD1_OTAPDLYSEL_SD_HSD		0x00050000U
+#define SD1_OTAPDLYSEL_EMMC_HSD		0x00060000U
+
+#endif
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define XSdPs_In64 Xil_In64
+#define XSdPs_Out64 Xil_Out64
+
+#define XSdPs_In32 Xil_In32
+#define XSdPs_Out32 Xil_Out32
+
+#define XSdPs_In16 Xil_In16
+#define XSdPs_Out16 Xil_Out16
+
+#define XSdPs_In8 Xil_In8
+#define XSdPs_Out8 Xil_Out8
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg64(InstancePtr, RegOffset) \
+	XSdPs_In64((InstancePtr->Config.BaseAddress) + RegOffset)
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset,
+*		u64 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \
+	XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \
+		(RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg(BaseAddress, RegOffset) \
+	XSdPs_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u32 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+	XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg16(BaseAddress, RegOffset) \
+	XSdPs_In16((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u16 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg16(BaseAddress, RegOffset, RegisterValue) \
+	XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg8(BaseAddress, RegOffset) \
+	XSdPs_In8((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u8 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg8(BaseAddress, RegOffset, RegisterValue) \
+	XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue))
+
+/***************************************************************************/
+/**
+* Macro to get present status register
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u8 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_GetPresentStatusReg(BaseAddress) \
+		XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_HW_H_ */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps_options.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps_options.c
new file mode 100644
index 0000000000000000000000000000000000000000..6743f1b34cf0dd8fa9f9bdb45a1400ce9aef84cd
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps_options.c
@@ -0,0 +1,1785 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_options.c
+* @addtogroup sdps_v2_5
+* @{
+*
+* Contains API's for changing the various options in host and card.
+* See xsdps.h for a detailed description of the device and driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.1   hk     04/18/14 Increase sleep for eMMC switch command.
+*                       Add sleep for microblaze designs. CR# 781117.
+* 2.3   sk     09/23/14 Use XSdPs_Change_ClkFreq API whenever changing
+*						clock.CR# 816586.
+* 2.5 	sg	   07/09/15 Added SD 3.0 features
+*       kvn    07/15/15 Modified the code according to MISRAC-2012.
+* 2.7   sk     01/08/16 Added workaround for issue in auto tuning mode
+*                       of SDR50, SDR104 and HS200.
+*       sk     02/16/16 Corrected the Tuning logic.
+*       sk     03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
+* 2.8   sk     04/20/16 Added new workaround for auto tuning.
+* 3.0   sk     07/07/16 Used usleep API for both arm and microblaze.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+* 3.1   mi     09/07/16 Removed compilation warnings with extra compiler flags.
+*       sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+*       sk     11/16/16 Issue DLL reset at 31 iteration to load new zero value.
+* 3.2   sk     02/01/17 Added HSD and DDR mode support for eMMC.
+*       sk     02/01/17 Consider bus width parameter from design for switching
+*       vns    02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
+*       vns    03/13/17 Fixed MISRAC mandatory violation
+*       sk     03/20/17 Add support for EL1 non-secure mode.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xsdps.h"
+#include "sleep.h"
+#if defined (__aarch64__)
+#include "xil_smc.h"
+#endif
+/************************** Constant Definitions *****************************/
+#define UHS_SDR12_SUPPORT	0x1U
+#define UHS_SDR25_SUPPORT	0x2U
+#define UHS_SDR50_SUPPORT	0x4U
+#define UHS_SDR104_SUPPORT	0x8U
+#define UHS_DDR50_SUPPORT	0x10U
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
+static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr);
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
+static void XSdPs_sdr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_SetTapDelay(XSdPs *InstancePtr);
+static void XSdPs_DllReset(XSdPs *InstancePtr);
+#endif
+
+/*****************************************************************************/
+/**
+* Update Block size for read/write operations.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	BlkSize - Block size passed by the user.
+*
+* @return	None
+*
+******************************************************************************/
+s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize)
+{
+	s32 Status;
+	u32 PresentStateReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_PRES_STATE_OFFSET);
+
+	if ((PresentStateReg & ((u32)XSDPS_PSR_INHIBIT_CMD_MASK |
+			(u32)XSDPS_PSR_INHIBIT_DAT_MASK |
+			(u32)XSDPS_PSR_WR_ACTIVE_MASK | (u32)XSDPS_PSR_RD_ACTIVE_MASK)) != 0U) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+
+	/* Send block write command */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD16, BlkSize, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	/* Set block size to the value passed */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
+			 BlkSize & XSDPS_BLK_SIZE_MASK);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get bus width support by card.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	SCR - buffer to store SCR register returned by card.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR)
+{
+	s32 Status;
+	u32 StatusReg;
+	u16 BlkCnt;
+	u16 BlkSize;
+	s32 LoopCnt;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	for (LoopCnt = 0; LoopCnt < 8; LoopCnt++) {
+		SCR[LoopCnt] = 0U;
+	}
+
+	/* Send block write command */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
+			InstancePtr->RelCardAddr, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	BlkCnt = XSDPS_SCR_BLKCNT;
+	BlkSize = XSDPS_SCR_BLKSIZE;
+
+	/* Set block size to the value passed */
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, SCR);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+
+	Xil_DCacheInvalidateRange((INTPTR)SCR, 8);
+
+	Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0U, BlkCnt);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set bus width to 4-bit in card and host
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr)
+{
+	s32 Status;
+	u32 StatusReg;
+	u32 Arg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	/*
+	 * check for bus width for 3.0 controller and return if
+	 * bus width is <4
+	 */
+	if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
+			(InstancePtr->Config.BusWidth < XSDPS_WIDTH_4)) {
+		Status = XST_SUCCESS;
+		goto RETURN_PATH;
+	}
+
+	if (InstancePtr->CardType == XSDPS_CARD_SD) {
+
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD55, InstancePtr->RelCardAddr,
+				0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH;
+
+		Arg = ((u32)InstancePtr->BusWidth);
+
+		Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, Arg, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} else {
+
+		if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
+				&& (InstancePtr->CardType == XSDPS_CHIP_EMMC) &&
+				(InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) {
+			/* in case of eMMC data width 8-bit */
+			InstancePtr->BusWidth = XSDPS_8_BIT_WIDTH;
+		} else {
+			InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH;
+		}
+
+		if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
+			if (InstancePtr->Mode == XSDPS_DDR52_MODE)
+				Arg = XSDPS_MMC_DDR_8_BIT_BUS_ARG;
+			else
+				Arg = XSDPS_MMC_8_BIT_BUS_ARG;
+		} else {
+			if (InstancePtr->Mode == XSDPS_DDR52_MODE)
+				Arg = XSDPS_MMC_DDR_4_BIT_BUS_ARG;
+			else
+				Arg = XSDPS_MMC_4_BIT_BUS_ARG;
+		}
+
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/* Check for transfer complete */
+		do {
+			StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_NORM_INTR_STS_OFFSET);
+			if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+				/* Write to clear error bits */
+				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_ERR_INTR_STS_OFFSET,
+						XSDPS_ERROR_INTR_ALL_MASK);
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		} while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+		/* Write to clear bit */
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+	}
+
+	usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
+
+	StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+					XSDPS_HOST_CTRL1_OFFSET);
+
+	/* Width setting in controller */
+	if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
+		StatusReg |= XSDPS_HC_EXT_BUS_WIDTH;
+	} else {
+		StatusReg |= XSDPS_HC_WIDTH_MASK;
+	}
+
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL1_OFFSET,
+			(u8)StatusReg);
+
+	if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_HOST_CTRL2_OFFSET);
+		StatusReg &= (u16)(~XSDPS_HC2_UHS_MODE_MASK);
+		StatusReg |= InstancePtr->Mode;
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_HOST_CTRL2_OFFSET, StatusReg);
+	}
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get bus speed supported by card.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	ReadBuff - buffer to store function group support data
+*		returned by card.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff)
+{
+	s32 Status;
+	u32 StatusReg;
+	u32 Arg;
+	u16 BlkCnt;
+	u16 BlkSize;
+	s32 LoopCnt;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	for (LoopCnt = 0; LoopCnt < 64; LoopCnt++) {
+		ReadBuff[LoopCnt] = 0U;
+	}
+
+	BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
+	BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+
+	Arg = XSDPS_SWITCH_CMD_HS_GET;
+
+	Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 64);
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set high speed in card and host. Changes clock in host accordingly.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
+{
+	s32 Status;
+	u32 StatusReg;
+	u32 Arg;
+	u16 BlkCnt;
+	u16 BlkSize;
+	u8 ReadBuff[64] = {0U};
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if (InstancePtr->CardType == XSDPS_CARD_SD) {
+
+		BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
+		BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
+		BlkSize &= XSDPS_BLK_SIZE_MASK;
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+		XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+		Xil_DCacheFlushRange((INTPTR)ReadBuff, 64);
+
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_XFER_MODE_OFFSET,
+				XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+
+		Arg = XSDPS_SWITCH_CMD_HS_SET;
+
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/*
+		 * Check for transfer complete
+		 * Polling for response for now
+		 */
+		do {
+			StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_NORM_INTR_STS_OFFSET);
+			if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+				/* Write to clear error bits */
+				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_ERR_INTR_STS_OFFSET,
+						XSDPS_ERROR_INTR_ALL_MASK);
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+		/* Write to clear bit */
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+		/* Change the clock frequency to 50 MHz */
+		InstancePtr->BusSpeed = XSDPS_CLK_50_MHZ;
+		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+		if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+		}
+
+	} else if (InstancePtr->CardType == XSDPS_CARD_MMC) {
+		Arg = XSDPS_MMC_HIGH_SPEED_ARG;
+
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/*
+		 * Check for transfer complete
+		 */
+		do {
+			StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_NORM_INTR_STS_OFFSET);
+			if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+				/*
+				 * Write to clear error bits
+				 */
+				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_ERR_INTR_STS_OFFSET,
+						XSDPS_ERROR_INTR_ALL_MASK);
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+		/*
+		 * Write to clear bit
+		 */
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+		/* Change the clock frequency to 52 MHz */
+		InstancePtr->BusSpeed = XSDPS_CLK_52_MHZ;
+		Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_52_MHZ);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} else {
+		if (InstancePtr->Mode == XSDPS_HS200_MODE) {
+			Arg = XSDPS_MMC_HS200_ARG;
+			InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK;
+		} else if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
+			Arg = XSDPS_MMC_HIGH_SPEED_ARG;
+			InstancePtr->BusSpeed = XSDPS_MMC_DDR_MAX_CLK;
+		} else {
+			Arg = XSDPS_MMC_HIGH_SPEED_ARG;
+			InstancePtr->BusSpeed = XSDPS_MMC_HSD_MAX_CLK;
+		}
+
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/*
+		 * Check for transfer complete
+		 */
+		do {
+			StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_NORM_INTR_STS_OFFSET);
+			if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+				/*
+				 * Write to clear error bits
+				 */
+				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_ERR_INTR_STS_OFFSET,
+						XSDPS_ERROR_INTR_ALL_MASK);
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+		/*
+		 * Write to clear bit
+		 */
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		if (InstancePtr->Mode == XSDPS_HS200_MODE) {
+			Status = XSdPs_Execute_Tuning(InstancePtr);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	}
+
+	usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
+
+	StatusReg = (s32)XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+					XSDPS_HOST_CTRL1_OFFSET);
+	StatusReg |= XSDPS_HC_SPEED_MASK;
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL1_OFFSET, (u8)StatusReg);
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to change clock freq to given value.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	SelFreq - Clock frequency in Hz.
+*
+* @return	None
+*
+* @note		This API will change clock frequency to the value less than
+*		or equal to the given value using the permissible dividors.
+*
+******************************************************************************/
+s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq)
+{
+	u16 ClockReg;
+	u16 DivCnt;
+	u16 Divisor = 0U;
+	u16 ExtDivisor;
+	s32 Status;
+	u16 ReadReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Disable clock */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	ClockReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET, ClockReg);
+
+	if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+	if ((InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) &&
+			(InstancePtr->Mode != XSDPS_UHS_SPEED_MODE_SDR12))
+		/* Program the Tap delays */
+		XSdPs_SetTapDelay(InstancePtr);
+#endif
+		/* Calculate divisor */
+		for (DivCnt = 0x1U; DivCnt <= XSDPS_CC_EXT_MAX_DIV_CNT;DivCnt++) {
+			if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) {
+				Divisor = DivCnt >> 1;
+				break;
+			}
+		}
+
+		if (DivCnt > XSDPS_CC_EXT_MAX_DIV_CNT) {
+			/* No valid divisor found for given frequency */
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} else {
+		/* Calculate divisor */
+		DivCnt = 0x1U;
+		while (DivCnt <= XSDPS_CC_MAX_DIV_CNT) {
+			if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) {
+				Divisor = DivCnt / 2U;
+				break;
+			}
+			DivCnt = DivCnt << 1U;
+		}
+
+		if (DivCnt > XSDPS_CC_MAX_DIV_CNT) {
+			/* No valid divisor found for given frequency */
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	}
+
+	/* Set clock divisor */
+	if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
+		ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_CLK_CTRL_OFFSET);
+		ClockReg &= ~(XSDPS_CC_SDCLK_FREQ_SEL_MASK |
+		XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK);
+
+		ExtDivisor = Divisor >> 8;
+		ExtDivisor <<= XSDPS_CC_EXT_DIV_SHIFT;
+		ExtDivisor &= XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK;
+
+		Divisor <<= XSDPS_CC_DIV_SHIFT;
+		Divisor &= XSDPS_CC_SDCLK_FREQ_SEL_MASK;
+		ClockReg |= Divisor | ExtDivisor | (u16)XSDPS_CC_INT_CLK_EN_MASK;
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+				ClockReg);
+	} else {
+		ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_CLK_CTRL_OFFSET);
+		ClockReg &= (~XSDPS_CC_SDCLK_FREQ_SEL_MASK);
+
+		Divisor <<= XSDPS_CC_DIV_SHIFT;
+		Divisor &= XSDPS_CC_SDCLK_FREQ_SEL_MASK;
+		ClockReg |= Divisor | (u16)XSDPS_CC_INT_CLK_EN_MASK;
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+				ClockReg);
+	}
+
+	/* Wait for internal clock to stabilize */
+	ReadReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_CLK_CTRL_OFFSET);
+	while((ReadReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
+		ReadReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_CLK_CTRL_OFFSET);;
+	}
+
+	/* Enable SD clock */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET,
+			ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to send pullup command to card before using DAT line 3(using 4-bit bus)
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Pullup(XSdPs *InstancePtr)
+{
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
+			InstancePtr->RelCardAddr, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XSdPs_CmdTransfer(InstancePtr, ACMD42, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get EXT_CSD register of eMMC.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	ReadBuff - buffer to store EXT_CSD
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff)
+{
+	s32 Status;
+	u32 StatusReg;
+	u32 Arg = 0U;
+	u16 BlkCnt;
+	u16 BlkSize;
+	s32 LoopCnt;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	for (LoopCnt = 0; LoopCnt < 512; LoopCnt++) {
+		ReadBuff[LoopCnt] = 0U;
+	}
+
+	BlkCnt = XSDPS_EXT_CSD_CMD_BLKCNT;
+	BlkSize = XSDPS_EXT_CSD_CMD_BLKSIZE;
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+	Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 512U);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+
+
+	/* Send SEND_EXT_CSD command */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD8, Arg, 1U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to write EXT_CSD register of eMMC.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	Arg is the argument to be sent along with the command
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg)
+{
+	s32 Status;
+	u32 StatusReg;
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/*
+			 * Write to clear error bits
+			 */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+/*****************************************************************************/
+/**
+*
+* API to Identify the supported UHS mode. This API will assign the
+* corresponding tap delay API to the Config_TapDelay pointer based on the
+* supported bus speed.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	ReadBuff contains the response for CMD6
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff)
+{
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	if (((ReadBuff[13] & UHS_SDR104_SUPPORT) != 0U) &&
+		(InstancePtr->Config.InputClockHz >= XSDPS_MMC_HS200_MAX_CLK)) {
+		InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR104;
+		InstancePtr->Config_TapDelay = XSdPs_sdr104_hs200_tapdelay;
+	}
+	else if (((ReadBuff[13] & UHS_SDR50_SUPPORT) != 0U) &&
+		(InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR50_MAX_CLK)) {
+		InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR50;
+		InstancePtr->Config_TapDelay = XSdPs_sdr50_tapdelay;
+	}
+	else if (((ReadBuff[13] & UHS_DDR50_SUPPORT) != 0U) &&
+		(InstancePtr->Config.InputClockHz >= XSDPS_SD_DDR50_MAX_CLK)) {
+		InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_DDR50;
+		InstancePtr->Config_TapDelay = XSdPs_ddr50_tapdelay;
+	}
+	else if (((ReadBuff[13] & UHS_SDR25_SUPPORT) != 0U) &&
+		(InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR25_MAX_CLK)) {
+		InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR25;
+		InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay;
+	}
+	else
+		InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR12;
+}
+
+/*****************************************************************************/
+/**
+*
+* API to UHS-I mode initialization
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	Mode UHS-I mode
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode)
+{
+	s32 Status;
+	u16 StatusReg;
+	u16 CtrlReg;
+	u32 Arg;
+	u16 BlkCnt;
+	u16 BlkSize;
+	u8 ReadBuff[64] = {0U};
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Drive strength */
+
+	/* Bus speed mode selection */
+	BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
+	BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
+			BlkSize);
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+	Xil_DCacheFlushRange((INTPTR)ReadBuff, 64);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+
+	switch (Mode) {
+	case 0U:
+		Arg = XSDPS_SWITCH_CMD_SDR12_SET;
+		InstancePtr->BusSpeed = XSDPS_SD_SDR12_MAX_CLK;
+		break;
+	case 1U:
+		Arg = XSDPS_SWITCH_CMD_SDR25_SET;
+		InstancePtr->BusSpeed = XSDPS_SD_SDR25_MAX_CLK;
+		break;
+	case 2U:
+		Arg = XSDPS_SWITCH_CMD_SDR50_SET;
+		InstancePtr->BusSpeed = XSDPS_SD_SDR50_MAX_CLK;
+		break;
+	case 3U:
+		Arg = XSDPS_SWITCH_CMD_SDR104_SET;
+		InstancePtr->BusSpeed = XSDPS_SD_SDR104_MAX_CLK;
+		break;
+	case 4U:
+		Arg = XSDPS_SWITCH_CMD_DDR50_SET;
+		InstancePtr->BusSpeed = XSDPS_SD_DDR50_MAX_CLK;
+		break;
+	default:
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+		break;
+	}
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+
+	/* Current limit */
+
+	/* Set UHS mode in controller */
+	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL2_OFFSET);
+	CtrlReg &= (u16)(~XSDPS_HC2_UHS_MODE_MASK);
+	CtrlReg |= Mode;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL2_OFFSET, CtrlReg);
+
+	/* Change the clock frequency */
+	Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+	if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+	}
+
+	if((Mode == XSDPS_UHS_SPEED_MODE_SDR104) ||
+			(Mode == XSDPS_UHS_SPEED_MODE_SDR50)) {
+		/* Send tuning pattern */
+		Status = XSdPs_Execute_Tuning(InstancePtr);
+		if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+		}
+	}
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+}
+#endif
+
+static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr)
+{
+	s32 Status;
+	u16 BlkSize;
+	u16 CtrlReg;
+	u8 TuningCount;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	BlkSize = XSDPS_TUNING_CMD_BLKSIZE;
+	if(InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH)
+	{
+		BlkSize = BlkSize*2U;
+	}
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
+			BlkSize);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_DAT_DIR_SEL_MASK);
+
+	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_HOST_CTRL2_OFFSET);
+	CtrlReg |= XSDPS_HC2_EXEC_TNG_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_HOST_CTRL2_OFFSET, CtrlReg);
+
+	/*
+	 * workaround which can work for 1.0/2.0 silicon for auto tuning.
+	 * This can be revisited for 3.0 silicon if necessary.
+	 */
+	/* Wait for ~60 clock cycles to reset the tap values */
+	(void)usleep(1U);
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+	/* Issue DLL Reset to load new SDHC tuned tap values */
+	XSdPs_DllReset(InstancePtr);
+#endif
+
+	for (TuningCount = 0U; TuningCount < MAX_TUNING_COUNT; TuningCount++) {
+
+		if (InstancePtr->CardType == XSDPS_CARD_SD) {
+			Status = XSdPs_CmdTransfer(InstancePtr, CMD19, 0U, 1U);
+		} else {
+			Status = XSdPs_CmdTransfer(InstancePtr, CMD21, 0U, 1U);
+		}
+
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_EXEC_TNG_MASK) == 0U) {
+			break;
+		}
+
+		if (TuningCount == 31) {
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+			/* Issue DLL Reset to load new SDHC tuned tap values */
+			XSdPs_DllReset(InstancePtr);
+#endif
+		}
+	}
+
+	if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_SAMP_CLK_SEL_MASK) == 0U) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/* Wait for ~12 clock cycles to synchronize the new tap values */
+	(void)usleep(1U);
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+	/* Issue DLL Reset to load new SDHC tuned tap values */
+	XSdPs_DllReset(InstancePtr);
+#endif
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH: return Status;
+
+}
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay for SDR104 and HS200 modes
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
+{
+	u32 TapDelay;
+	(void) CardType;
+
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	if (DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)TapDelay;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) |
+				((u64)SD0_OTAPDLYENA << 32), (u64)SD0_OTAPDLYENA,
+				0, 0, 0, 0, 0);
+		if (Bank == 2)
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+					(u64)SD0_OTAPDLYSEL_HS200_B2, 0, 0, 0, 0, 0);
+		else
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+					(u64)SD0_OTAPDLYSEL_HS200_B0, 0, 0, 0, 0, 0);
+#else
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay |= SD0_OTAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+		if (Bank == 2)
+			TapDelay |= SD0_OTAPDLYSEL_HS200_B2;
+		else
+			TapDelay |= SD0_OTAPDLYSEL_HS200_B0;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+	} else {
+#endif
+		(void) DeviceId;
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)TapDelay;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) |
+				((u64)SD1_OTAPDLYENA << 32), (u64)SD1_OTAPDLYENA,
+				0, 0, 0, 0, 0);
+		if (Bank == 2)
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+					(u64)SD1_OTAPDLYSEL_HS200_B2, 0, 0, 0, 0, 0);
+		else
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+					(u64)SD1_OTAPDLYSEL_HS200_B0, 0, 0, 0, 0, 0);
+#else
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay |= SD1_OTAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+		if (Bank == 2)
+			TapDelay |= SD1_OTAPDLYSEL_HS200_B2;
+		else
+			TapDelay |= SD1_OTAPDLYSEL_HS200_B0;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	}
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay for SDR50 mode
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_sdr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
+{
+	u32 TapDelay;
+	(void) Bank;
+	(void) CardType;
+
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	if (DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)TapDelay;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) |
+				((u64)SD0_OTAPDLYENA << 32), (u64)SD0_OTAPDLYENA,
+				0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) |
+				((u64)SD0_OTAPDLY_SEL_MASK << 32), (u64)SD0_OTAPDLYSEL_SD50,
+				0, 0, 0, 0, 0);
+#else
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay |= SD0_OTAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+		TapDelay |= SD0_OTAPDLYSEL_SD50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+	} else {
+#endif
+		(void) DeviceId;
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)TapDelay;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) |
+				((u64)SD1_OTAPDLYENA << 32), (u64)SD1_OTAPDLYENA,
+				0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) |
+				((u64)SD1_OTAPDLY_SEL_MASK << 32), (u64)SD1_OTAPDLYSEL_SD50,
+				0, 0, 0, 0, 0);
+#else
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay |= SD1_OTAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+		TapDelay |= SD1_OTAPDLYSEL_SD50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	}
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay for DDR50 mode
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
+{
+	u32 TapDelay;
+	(void) Bank;
+
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	if (DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)TapDelay;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD0_ITAPCHGWIN << 32), (u64)SD0_ITAPCHGWIN,
+				0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD0_ITAPDLYENA << 32), (u64)SD0_ITAPDLYENA,
+				0, 0, 0, 0, 0);
+		if (CardType== XSDPS_CARD_SD)
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_ITAPDLY) | ((u64)SD0_ITAPDLY_SEL_MASK << 32),
+					(u64)SD0_ITAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0);
+		else
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_ITAPDLY) | ((u64)SD0_ITAPDLY_SEL_MASK << 32),
+					(u64)SD0_ITAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD0_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) |
+				((u64)SD0_OTAPDLYENA << 32), (u64)SD0_OTAPDLYENA,
+				0, 0, 0, 0, 0);
+		if (CardType == XSDPS_CARD_SD)
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+					(u64)SD0_OTAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0);
+		else
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+					(u64)SD0_OTAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0);
+#else
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+		TapDelay |= SD0_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the ITAPDLY */
+		TapDelay |= SD0_ITAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		if (CardType== XSDPS_CARD_SD)
+			TapDelay |= SD0_ITAPDLYSEL_SD_DDR50;
+		else
+			TapDelay |= SD0_ITAPDLYSEL_EMMC_DDR50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay &= ~SD0_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay |= SD0_OTAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+		if (CardType == XSDPS_CARD_SD)
+			TapDelay |= SD0_OTAPDLYSEL_SD_DDR50;
+		else
+			TapDelay |= SD0_OTAPDLYSEL_EMMC_DDR50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+	} else {
+#endif
+		(void) DeviceId;
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)TapDelay;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD1_ITAPCHGWIN << 32), (u64)SD1_ITAPCHGWIN,
+				0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD1_ITAPDLYENA << 32), (u64)SD1_ITAPDLYENA,
+				0, 0, 0, 0, 0);
+		if (CardType== XSDPS_CARD_SD)
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_ITAPDLY) | ((u64)SD1_ITAPDLY_SEL_MASK << 32),
+					(u64)SD1_ITAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0);
+		else
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_ITAPDLY) | ((u64)SD1_ITAPDLY_SEL_MASK << 32),
+					(u64)SD1_ITAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+				SD_ITAPDLY) | ((u64)SD1_ITAPCHGWIN << 32),
+				(u64)0x0, 0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+				SD_OTAPDLY) | ((u64)SD1_OTAPDLYENA << 32), (u64)SD1_OTAPDLYENA,
+				0, 0, 0, 0, 0);
+		if (CardType == XSDPS_CARD_SD)
+			Xil_Smc(MMIO_WRITE_SMC_FID,(u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+					(u64)SD1_OTAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0);
+		else
+			Xil_Smc(MMIO_WRITE_SMC_FID,(u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+					(u64)SD1_OTAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0);
+#else
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+		TapDelay |= SD1_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the ITAPDLY */
+		TapDelay |= SD1_ITAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		if (CardType == XSDPS_CARD_SD)
+			TapDelay |= SD1_ITAPDLYSEL_SD_DDR50;
+		else
+			TapDelay |= SD1_ITAPDLYSEL_EMMC_DDR50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay &= ~SD1_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay |= SD1_OTAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+		if (CardType == XSDPS_CARD_SD)
+			TapDelay |= SD1_OTAPDLYSEL_SD_DDR50;
+		else
+			TapDelay |= SD1_OTAPDLYSEL_EMMC_DDR50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	}
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay for HSD and SDR25 mode
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
+{
+	u32 TapDelay;
+	(void) Bank;
+
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	if (DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)TapDelay;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD0_ITAPCHGWIN << 32), (u64)SD0_ITAPCHGWIN,
+				0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD0_ITAPDLYENA << 32), (u64)SD0_ITAPDLYENA,
+				0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD0_ITAPDLY_SEL_MASK << 32), (u64)SD0_ITAPDLYSEL_HSD,
+				0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD0_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) |
+				((u64)SD0_OTAPDLYENA << 32), (u64)SD0_OTAPDLYENA,
+				0, 0, 0, 0, 0);
+		if (CardType == XSDPS_CARD_SD)
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+					(u64)SD0_OTAPDLYSEL_SD_HSD, 0, 0, 0, 0, 0);
+		else
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+					(u64)SD0_OTAPDLYSEL_EMMC_HSD, 0, 0, 0, 0, 0);
+#else
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+		TapDelay |= SD0_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the ITAPDLY */
+		TapDelay |= SD0_ITAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay |= SD0_ITAPDLYSEL_HSD;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay &= ~SD0_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay |= SD0_OTAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+		if (CardType == XSDPS_CARD_SD)
+			TapDelay |= SD0_OTAPDLYSEL_SD_HSD;
+		else
+			TapDelay |= SD0_OTAPDLYSEL_EMMC_HSD;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+	} else {
+#endif
+		(void) DeviceId;
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)TapDelay;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD1_ITAPCHGWIN << 32), (u64)SD1_ITAPCHGWIN,
+				0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD1_ITAPDLYENA << 32), (u64)SD1_ITAPDLYENA,
+				0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD1_ITAPDLY_SEL_MASK << 32), (u64)SD1_ITAPDLYSEL_HSD,
+				0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD1_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) |
+				((u64)SD1_OTAPDLYENA << 32), (u64)SD1_OTAPDLYENA,
+				0, 0, 0, 0, 0);
+		if (CardType == XSDPS_CARD_SD)
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+					(u64)SD1_OTAPDLYSEL_SD_HSD, 0, 0, 0, 0, 0);
+		else
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+					(u64)SD1_OTAPDLYSEL_EMMC_HSD, 0, 0, 0, 0, 0);
+#else
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+		TapDelay |= SD1_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the ITAPDLY */
+		TapDelay |= SD1_ITAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay |= SD1_ITAPDLYSEL_HSD;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay &= ~SD1_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay |= SD1_OTAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+		if (CardType == XSDPS_CARD_SD)
+			TapDelay |= SD1_OTAPDLYSEL_SD_HSD;
+		else
+			TapDelay |= SD1_OTAPDLYSEL_EMMC_HSD;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	}
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay w.r.t speed modes
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_SetTapDelay(XSdPs *InstancePtr)
+{
+	u32 DllCtrl, BankNum, DeviceId, CardType;
+
+	BankNum = InstancePtr->Config.BankNumber;
+	DeviceId = InstancePtr->Config.DeviceId ;
+	CardType = InstancePtr->CardType ;
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	if (DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)DllCtrl;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+				SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32),
+				(u64)SD0_DLL_RST, 0, 0, 0, 0, 0);
+#else
+		DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+		DllCtrl |= SD0_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+		InstancePtr->Config_TapDelay(BankNum, DeviceId, CardType);
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)DllCtrl;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+				SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32),
+				(u64)0x0, 0, 0, 0, 0, 0);
+#else
+		DllCtrl &= ~SD0_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+	} else {
+#endif
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)DllCtrl;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+				SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32),
+				(u64)SD1_DLL_RST, 0, 0, 0, 0, 0);
+#else
+		DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+		DllCtrl |= SD1_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+		InstancePtr->Config_TapDelay(BankNum, DeviceId, CardType);
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)DllCtrl;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+				SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32),
+				(u64)0x0, 0, 0, 0, 0, 0);
+#else
+		DllCtrl &= ~SD1_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	}
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to reset the DLL
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void XSdPs_DllReset(XSdPs *InstancePtr)
+{
+	u32 ClockReg, DllCtrl;
+
+	/* Disable clock */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	ClockReg &= ~XSDPS_CC_SD_CLK_EN_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET, ClockReg);
+
+	/* Issue DLL Reset to load zero tap values */
+	DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+	if (InstancePtr->Config.DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)DllCtrl;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+				SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32),
+				(u64)SD0_DLL_RST, 0, 0, 0, 0, 0);
+#else
+		DllCtrl |= SD0_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+	} else {
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)DllCtrl;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+				SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32),
+				(u64)SD1_DLL_RST, 0, 0, 0, 0, 0);
+#else
+		DllCtrl |= SD1_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+	}
+
+	/* Wait for 2 micro seconds */
+	(void)usleep(2U);
+
+	/* Release the DLL out of reset */
+	DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+	if (InstancePtr->Config.DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)DllCtrl;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+				SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32),
+				(u64)0x0, 0, 0, 0, 0, 0);
+#else
+		DllCtrl &= ~SD0_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+	} else {
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)DllCtrl;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+				SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32),
+				(u64)0x0, 0, 0, 0, 0, 0);
+#else
+		DllCtrl &= ~SD1_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+	}
+
+	/* Wait for internal clock to stabilize */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_CLK_CTRL_OFFSET);
+	while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
+		ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_CLK_CTRL_OFFSET);
+	}
+
+	/* Enable SD clock */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET,
+			ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+}
+#endif
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps_sinit.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..e0936b30876ba6af6342a75eecf5056e30fd824e
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/sdps_v3_2/src/xsdps_sinit.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_sinit.c
+* @addtogroup sdps_v2_5
+* @{
+*
+* The implementation of the XSdPs component's static initialization
+* functionality.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+*       kvn    07/15/15 Modified the code according to MISRAC-2012.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xstatus.h"
+#include "xsdps.h"
+#include "xparameters.h"
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XSdPs_Config XSdPs_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device to look up the
+*		configuration for.
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xsdps.h for the definition of XSdPs_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId)
+{
+	XSdPs_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XSDPS_NUM_INSTANCES; Index++) {
+		if (XSdPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XSdPs_ConfigTable[Index];
+			break;
+		}
+	}
+	return (XSdPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/Makefile b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..0f23775de3471f625d6512d03ed2d0aef0eb60fc
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/Makefile
@@ -0,0 +1,87 @@
+###############################################################################
+#
+# Copyright (C) 2011 - 2015 Xilinx, Inc.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+###############################################################################
+
+include config.make
+
+CC=$(COMPILER)
+AR=$(ARCHIVER)
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS))
+ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS))
+
+ifeq (($(notdir $(CC))) , arm-xilinx-eabi-gcc)
+ECC_FLAGS	+= -nostartfiles\
+		  -march=armv7-a \
+		  -mfloat-abi=soft \
+		  -mfpu=neon
+endif
+
+ifeq (($(notdir $(CC))) , arm-none-eabi-gcc)
+ECC_FLAGS	+= -nostartfiles
+endif
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+ASSEMBLY_OBJECTS  = $(addsuffix .o, $(basename $(wildcard *.S)))
+INCLUDEFILES=*.h
+
+libs: $(LIBS)
+
+standalone_libs: $(LIBSOURCES)
+	echo "Compiling standalone"
+	$(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^
+	$(AR) -r ${RELEASEDIR}/${LIB} ${OUTS}
+
+profile_libs:
+	$(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" libs
+
+.PHONY: include
+include: standalone_includes profile_includes
+
+standalone_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+profile_includes:
+	$(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" include
+
+clean:
+	rm -rf ${OBJECTS}
+	rm -rf ${ASSEMBLY_OBJECTS}
+	$(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" clean
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/_exit.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/_exit.c
new file mode 100644
index 0000000000000000000000000000000000000000..cf598882be91ac2d785f8bd8d3dc757b308ac775
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/_exit.c
@@ -0,0 +1,44 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include <unistd.h>
+#include "xil_types.h"
+
+/* _exit - Simple implementation. Does not return.
+*/
+__attribute__((weak)) void _exit (sint32 status)
+{
+  (void)status;
+  while (1) {
+	;
+  }
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/_exit.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/_exit.o
new file mode 100644
index 0000000000000000000000000000000000000000..91c446cb679a476393d169d21eaa0b30d86da1fa
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/_exit.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/_open.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/_open.c
new file mode 100644
index 0000000000000000000000000000000000000000..a108b771620def28d60cda4cd26204429a2a9a18
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/_open.c
@@ -0,0 +1,54 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#ifndef UNDEFINE_FILE_OPS
+#include <errno.h>
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode);
+}
+#endif
+
+/*
+ * _open -- open a file descriptor. We don't have a filesystem, so
+ *         we return an error.
+ */
+__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode)
+{
+  (void)buf;
+  (void)flags;
+  (void)mode;
+  errno = EIO;
+  return (-1);
+}
+#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/_open.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/_open.o
new file mode 100644
index 0000000000000000000000000000000000000000..1103faf84014a5d14c7cd5c7ac4f81bd7b455383
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/_open.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/_sbrk.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/_sbrk.c
new file mode 100644
index 0000000000000000000000000000000000000000..2a069ec06565e0a79ea0dd0ef10fa5d0831d47d6
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/_sbrk.c
@@ -0,0 +1,70 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include <sys/types.h>
+#include "xil_types.h"
+
+extern u8 _heap_start[];
+extern u8 _heap_end[];
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) caddr_t _sbrk ( s32 incr );
+}
+#endif
+
+__attribute__((weak)) caddr_t _sbrk ( s32 incr )
+{
+  static u8 *heap = NULL;
+  u8 *prev_heap;
+  static u8 *HeapEndPtr = (u8 *)&_heap_end;
+  caddr_t Status;
+
+  if (heap == NULL) {
+    heap = (u8 *)&_heap_start;
+  }
+  prev_heap = heap;
+
+  heap += incr;
+
+  if (heap > HeapEndPtr){
+	  Status = (caddr_t) -1;
+  }
+  else if (prev_heap != NULL) {
+	  Status = (caddr_t) ((void *)prev_heap);
+  }
+  else {
+	  Status = (caddr_t) -1;
+  }
+
+  return Status;
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/_sbrk.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/_sbrk.o
new file mode 100644
index 0000000000000000000000000000000000000000..a6ae80229664e280e17ea08207b5d31c3fed1be7
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/_sbrk.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/abort.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/abort.c
new file mode 100644
index 0000000000000000000000000000000000000000..e8988c04818685c56287b2de514e6c96cc2d6cb4
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/abort.c
@@ -0,0 +1,42 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include <stdlib.h>
+#include <unistd.h>
+
+/*
+ * abort -- go out via exit...
+ */
+__attribute__((weak)) void abort(void)
+{
+  _exit(1);
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/abort.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/abort.o
new file mode 100644
index 0000000000000000000000000000000000000000..bee48a5d330305ecae2d2f08d8c4864bca57ca50
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/abort.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/asm_vectors.S b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/asm_vectors.S
new file mode 100644
index 0000000000000000000000000000000000000000..1752548d73bcd9ba920579f417180fd06bf8ea7e
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/asm_vectors.S
@@ -0,0 +1,198 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file asm_vectors.s
+*
+* This file contains the initial vector table for the Cortex A9 processor
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 10/20/09 Initial version
+* 3.05a sdm	02/02/12 Save lr when profiling is enabled
+* 3.10a srt     04/18/13 Implemented ARM Erratas. Please refer to file
+*			 'xil_errata.h' for errata description
+* 4.00a pkp	22/01/14 Modified return addresses for interrupt
+*			 handlers (DataAbortHandler and SVCHandler)
+*			 to fix CR#767251
+* 5.1	pkp	05/13/15 Saved the addresses of instruction causing data
+*			 abort and prefetch abort into DataAbortAddr and
+*			 PrefetchAbortAddr for further use to fix CR#854523
+* 5.4	pkp	12/03/15 Added handler for undefined exception
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+#include "xil_errata.h"
+
+#define __ARM_NEON__ 1
+
+.org 0
+.text
+
+.globl _vector_table
+
+.section .vectors
+_vector_table:
+	B	_boot
+	B	Undefined
+	B	SVCHandler
+	B	PrefetchAbortHandler
+	B	DataAbortHandler
+	NOP	/* Placeholder for address exception vector*/
+	B	IRQHandler
+	B	FIQHandler
+
+
+IRQHandler:					/* IRQ vector handler */
+
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code*/
+#ifdef __ARM_NEON__
+	vpush {d0-d7}
+	vpush {d16-d31}
+	vmrs r1, FPSCR
+	push {r1}
+	vmrs r1, FPEXC
+	push {r1}
+#endif
+
+#ifdef PROFILING
+	ldr	r2, =prof_pc
+	subs	r3, lr, #0
+	str	r3, [r2]
+#endif
+
+	bl	IRQInterrupt			/* IRQ vector */
+
+#ifdef __ARM_NEON__
+	pop 	{r1}
+	vmsr    FPEXC, r1
+	pop 	{r1}
+	vmsr    FPSCR, r1
+	vpop    {d16-d31}
+	vpop    {d0-d7}
+#endif
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+
+
+	subs	pc, lr, #4			/* adjust return */
+
+
+FIQHandler:					/* FIQ vector handler */
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
+#ifdef __ARM_NEON__
+	vpush {d0-d7}
+	vpush {d16-d31}
+	vmrs r1, FPSCR
+	push {r1}
+	vmrs r1, FPEXC
+	push {r1}
+#endif
+
+FIQLoop:
+	bl	FIQInterrupt			/* FIQ vector */
+
+#ifdef __ARM_NEON__
+	pop 	{r1}
+	vmsr    FPEXC, r1
+	pop 	{r1}
+	vmsr    FPSCR, r1
+	vpop    {d16-d31}
+	vpop    {d0-d7}
+#endif
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+	subs	pc, lr, #4			/* adjust return */
+
+
+Undefined:					/* Undefined handler */
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
+	ldr     r0, =UndefinedExceptionAddr
+	sub     r1, lr, #4
+	str     r1, [r0]            		/* Store address of instruction causing undefined exception */
+
+	bl	UndefinedException		/* UndefinedException: call C function here */
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+	movs	pc, lr
+
+SVCHandler:					/* SWI handler */
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
+
+	tst	r0, #0x20			/* check the T bit */
+	ldrneh	r0, [lr,#-2]			/* Thumb mode */
+	bicne	r0, r0, #0xff00			/* Thumb mode */
+	ldreq	r0, [lr,#-4]			/* ARM mode */
+	biceq	r0, r0, #0xff000000		/* ARM mode */
+
+	bl	SWInterrupt			/* SWInterrupt: call C function here */
+
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+
+	movs	pc, lr		/*return to the next instruction after the SWI instruction */
+
+
+DataAbortHandler:				/* Data Abort handler */
+#ifdef CONFIG_ARM_ERRATA_775420
+	dsb
+#endif
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
+	ldr     r0, =DataAbortAddr
+	sub     r1, lr, #8
+	str     r1, [r0]            		/* Stores instruction causing data abort */
+
+	bl	DataAbortInterrupt		/*DataAbortInterrupt :call C function here */
+
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+
+	subs	pc, lr, #8			/* points to the instruction that caused the Data Abort exception */
+
+PrefetchAbortHandler:				/* Prefetch Abort handler */
+#ifdef CONFIG_ARM_ERRATA_775420
+	dsb
+#endif
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
+	ldr     r0, =PrefetchAbortAddr
+	sub     r1, lr, #4
+	str     r1, [r0]            		/* Stores instruction causing prefetch abort */
+
+	bl	PrefetchAbortInterrupt		/* PrefetchAbortInterrupt: call C function here */
+
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+
+	subs	pc, lr, #4			/* points to the instruction that caused the Prefetch Abort exception */
+
+.end
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/asm_vectors.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/asm_vectors.o
new file mode 100644
index 0000000000000000000000000000000000000000..f41404704dfd7aab6067c71aec1e82374c458f38
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/asm_vectors.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/boot.S b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/boot.S
new file mode 100644
index 0000000000000000000000000000000000000000..5dfe5c2e74410aa368f16a6a053523a5e390a4d5
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/boot.S
@@ -0,0 +1,496 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file boot.S
+*
+* @addtogroup a9_boot_code Cortex A9 Processor Boot Code
+* @{
+* <h2> boot.S </h2>
+* The boot code performs minimum configuration which is required for an
+* application to run starting from processor's reset state. Below is a
+* sequence illustrating what all configuration is performed before control
+* reaches to main function.
+*
+* 1. Program vector table base for exception handling
+* 2. Invalidate instruction cache, data cache and TLBs
+* 3. Program stack pointer for various modes (IRQ, FIQ, supervisor, undefine,
+*    abort, system)
+* 4. Configure MMU with short descriptor translation table format and program
+*    base address of translation table
+* 5. Enable data cache, instruction cache and MMU
+* 6. Enable Floating point unit
+* 7. Transfer control to _start which clears BSS sections, initializes
+*    global timer and runs global constructor before jumping to main
+*    application
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 10/20/09 Initial version
+* 3.06a sgd     05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control
+*			 register settings.
+* 3.06a asa 	06/17/12 Modified the TTBR settings and L2 Cache auxiliary
+*		         register settings.
+* 3.07a asa     07/16/12 Modified the L2 Cache controller settings to improve
+*			 performance. Changed the property of the ".boot"
+*			 section.
+* 3.07a sgd     08/21/12 Modified the L2 Cache controller and cp15 Aux Control
+*               Register settings
+* 3.09a sgd     02/06/13 Updated SLCR l2c Ram Control register to a
+*               value of 0x00020202. Fix for CR 697094 (SI#687034).
+* 3.10a srt     04/18/13 Implemented ARM Erratas. Please refer to file
+*			 'xil_errata.h' for errata description
+* 4.2   pkp	06/19/14 Enabled asynchronous abort exception
+* 5.0	pkp	16/15/14 Modified initialization code to enable scu after
+*			 MMU is enabled
+* 5.1   pkp	05/13/15 Changed the initialization order so to first invalidate
+*			 caches and TLB, enable MMU and caches, then enable SMP
+*			 bit in ACTLR. L2Cache invalidation and enabling of L2Cache
+*			 is done later.
+* 5.4   asa     12/6/15  Added code to initialize SPSR for all relevant modes.
+* 6.0   mus     08/04/16 Added code to detect zynq-7000 base silicon configuration and
+*                        attempt to enable dual core behavior on single cpu zynq-7000s
+*                        devices is prevented from corrupting system behavior.
+* 6.0   mus     08/24/16 Check CPU core before putting cpu1 to reset for single core
+*                        zynq-7000s devices
+*
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#include "xparameters.h"
+#include "xil_errata.h"
+
+.globl MMUTable
+.global _prestart
+.global _boot
+.global __stack
+.global __irq_stack
+.global __supervisor_stack
+.global __abort_stack
+.global __fiq_stack
+.global __undef_stack
+.global _vector_table
+
+.set PSS_L2CC_BASE_ADDR, 0xF8F02000
+.set PSS_SLCR_BASE_ADDR, 0xF8000000
+
+.set RESERVED,		0x0fffff00
+.set TblBase ,		MMUTable
+.set LRemap,		0xFE00000F		/* set the base address of the peripheral block as not shared */
+.set L2CCWay,		(PSS_L2CC_BASE_ADDR + 0x077C)	/*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_INVLD_WAY_OFFSET)*/
+.set L2CCSync,		(PSS_L2CC_BASE_ADDR + 0x0730)	/*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_SYNC_OFFSET)*/
+.set L2CCCrtl,		(PSS_L2CC_BASE_ADDR + 0x0100)	/*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CNTRL_OFFSET)*/
+.set L2CCAuxCrtl,	(PSS_L2CC_BASE_ADDR + 0x0104)	/*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_AUX_CNTRL_OFFSET)*/
+.set L2CCTAGLatReg,	(PSS_L2CC_BASE_ADDR + 0x0108)	/*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_TAG_RAM_CNTRL_OFFSET)*/
+.set L2CCDataLatReg,	(PSS_L2CC_BASE_ADDR + 0x010C)	/*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_DATA_RAM_CNTRL_OFFSET)*/
+.set L2CCIntClear,	(PSS_L2CC_BASE_ADDR + 0x0220)	/*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_IAR_OFFSET)*/
+.set L2CCIntRaw,	(PSS_L2CC_BASE_ADDR + 0x021C)	/*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_ISR_OFFSET)*/
+
+.set SLCRlockReg,	    (PSS_SLCR_BASE_ADDR + 0x04)	/*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_LOCK_OFFSET)*/
+.set SLCRUnlockReg,     (PSS_SLCR_BASE_ADDR + 0x08)	/*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_UNLOCK_OFFSET)*/
+.set SLCRL2cRamReg,     (PSS_SLCR_BASE_ADDR + 0xA1C) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_L2C_RAM_OFFSET)*/
+.set SLCRCPURSTReg,     (0xF8000000 + 0x244)           /*(XPS_SYS_CTRL_BASEADDR + A9_CPU_RST_CTRL_OFFSET)*/
+.set EFUSEStaus,        (0xF800D000 + 0x10)            /*(XPS_EFUSE_BASEADDR + EFUSE_STATUS_OFFSET)*/
+
+/* workaround for simulation not working when L1 D and I caches,MMU and  L2 cache enabled - DT568997 */
+.if SIM_MODE == 1
+.set CRValMmuCac,	0b00000000000000	/* Disable IDC, and MMU */
+.else
+.set CRValMmuCac,	0b01000000000101	/* Enable IDC, and MMU */
+.endif
+
+.set CRValHiVectorAddr,	0b10000000000000	/* Set the Vector address to high, 0xFFFF0000 */
+
+.set L2CCAuxControl,	0x72360000		/* Enable all prefetching, Cache replacement policy, Parity enable,
+                                        Event monitor bus enable and Way Size (64 KB) */
+.set L2CCControl,	0x01			/* Enable L2CC */
+.set L2CCTAGLatency,	0x0111			/* latency for TAG RAM */
+.set L2CCDataLatency,	0x0121			/* latency for DATA RAM */
+
+.set SLCRlockKey,	        0x767B			/* SLCR lock key */
+.set SLCRUnlockKey,	        0xDF0D			/* SLCR unlock key */
+.set SLCRL2cRamConfig,      0x00020202      /* SLCR L2C ram configuration */
+
+/* Stack Pointer locations for boot code */
+.set Undef_stack,	__undef_stack
+.set FIQ_stack,		__fiq_stack
+.set Abort_stack,	__abort_stack
+.set SPV_stack,		__supervisor_stack
+.set IRQ_stack,		__irq_stack
+.set SYS_stack,		__stack
+
+.set vector_base,	_vector_table
+
+.set FPEXC_EN,		0x40000000		/* FPU enable bit, (1 << 30) */
+
+.section .boot,"ax"
+
+
+/* this initializes the various processor modes */
+
+_prestart:
+_boot:
+
+#if XPAR_CPU_ID==0
+        /* only allow cpu0 through */
+	mrc	p15,0,r1,c0,c0,5
+	and	r1, r1, #0xf
+        cmp	r1, #0
+	beq	CheckEFUSE
+	EndlessLoop0:
+		wfe
+	b	EndlessLoop0
+
+CheckEFUSE:
+        ldr r0,=EFUSEStaus
+        ldr r1,[r0]                             /* Read eFuse setting */
+        ands r1,r1,#0x80                        /* Check whether device is having single core */
+	beq OKToRun
+
+ /* single core device, reset cpu1 */
+        ldr     r0,=SLCRUnlockReg               /* Load SLCR base address base + unlock register */
+        ldr     r1,=SLCRUnlockKey               /* set unlock key */
+        str     r1, [r0]                        /* Unlock SLCR */
+
+	ldr r0,=SLCRCPURSTReg
+	ldr r1,[r0]                             /* Read CPU Software Reset Control register */
+	orr r1,r1,#0x22
+        str r1,[r0]                             /* Reset CPU1 */
+
+        ldr	r0,=SLCRlockReg         	/* Load SLCR base address base + lock register */
+	ldr	r1,=SLCRlockKey	        	/* set lock key */
+	str	r1, [r0]	        	/* lock SLCR */
+
+#elif XPAR_CPU_ID==1
+	/* only allow cpu1 through */
+       mrc	p15,0,r1,c0,c0,5
+       and	r1, r1, #0xf
+       cmp	r1, #1
+       beq	CheckEFUSE1
+       b        EndlessLoop1
+
+CheckEFUSE1:
+        ldr r0,=EFUSEStaus
+        ldr r1,[r0]                             /* Read eFuse setting */
+        ands r1,r1,#0x80                        /* Check whether device is having single core */
+	beq OKToRun
+	EndlessLoop1:
+	        wfe
+	b	EndlessLoop1
+#endif
+
+OKToRun:
+	mrc     p15, 0, r0, c0, c0, 0		/* Get the revision */
+	and     r5, r0, #0x00f00000
+	and     r6, r0, #0x0000000f
+	orr     r6, r6, r5, lsr #20-4
+
+#ifdef CONFIG_ARM_ERRATA_742230
+        cmp     r6, #0x22                       /* only present up to r2p2 */
+        mrcle   p15, 0, r10, c15, c0, 1         /* read diagnostic register */
+        orrle   r10, r10, #1 << 4               /* set bit #4 */
+        mcrle   p15, 0, r10, c15, c0, 1         /* write diagnostic register */
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_743622
+	teq     r5, #0x00200000                 /* only present in r2p* */
+	mrceq   p15, 0, r10, c15, c0, 1         /* read diagnostic register */
+	orreq   r10, r10, #1 << 6               /* set bit #6 */
+	mcreq   p15, 0, r10, c15, c0, 1         /* write diagnostic register */
+#endif
+
+	/* set VBAR to the _vector_table address in linker script */
+	ldr	r0, =vector_base
+	mcr	p15, 0, r0, c12, c0, 0
+
+	/*invalidate scu*/
+	ldr	r7, =0xf8f0000c
+	ldr	r6, =0xffff
+	str	r6, [r7]
+
+	/* Invalidate caches and TLBs */
+	mov	r0,#0				/* r0 = 0  */
+	mcr	p15, 0, r0, c8, c7, 0		/* invalidate TLBs */
+	mcr	p15, 0, r0, c7, c5, 0		/* invalidate icache */
+	mcr	p15, 0, r0, c7, c5, 6		/* Invalidate branch predictor array */
+	bl	invalidate_dcache		/* invalidate dcache */
+
+	/* Disable MMU, if enabled */
+	mrc	p15, 0, r0, c1, c0, 0		/* read CP15 register 1 */
+	bic	r0, r0, #0x1			/* clear bit 0 */
+	mcr	p15, 0, r0, c1, c0, 0		/* write value back */
+
+#ifdef SHAREABLE_DDR
+	/* Mark the entire DDR memory as shareable */
+	ldr	r3, =0x3ff			/* 1024 entries to cover 1G DDR */
+	ldr	r0, =TblBase			/* MMU Table address in memory */
+	ldr	r2, =0x15de6			/* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
+shareable_loop:
+	str	r2, [r0]			/* write the entry to MMU table */
+	add	r0, r0, #0x4			/* next entry in the table */
+	add	r2, r2, #0x100000		/* next section */
+	subs	r3, r3, #1
+	bge	shareable_loop			/* loop till 1G is covered */
+#endif
+
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the irq stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x12			/* IRQ mode */
+	msr	cpsr, r2
+	ldr	r13,=IRQ_stack			/* IRQ stack pointer */
+	bic r2, r2, #(0x1 << 9)    		 /* Set EE bit to little-endian */
+	msr spsr_fsxc,r2
+
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the supervisor stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x13			/* supervisor mode */
+	msr	cpsr, r2
+	ldr	r13,=SPV_stack			/* Supervisor stack pointer */
+	bic r2, r2, #(0x1 << 9)     		/* Set EE bit to little-endian */
+	msr spsr_fsxc,r2
+
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the Abort  stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x17			/* Abort mode */
+	msr	cpsr, r2
+	ldr	r13,=Abort_stack		/* Abort stack pointer */
+	bic r2, r2, #(0x1 << 9)     		/* Set EE bit to little-endian */
+	msr spsr_fsxc,r2
+
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the FIQ stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x11			/* FIQ mode */
+	msr	cpsr, r2
+	ldr	r13,=FIQ_stack			/* FIQ stack pointer */
+	bic r2, r2, #(0x1 << 9)    		/* Set EE bit to little-endian */
+	msr spsr_fsxc,r2
+
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the Undefine stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x1b			/* Undefine mode */
+	msr	cpsr, r2
+	ldr	r13,=Undef_stack		/* Undefine stack pointer */
+	bic r2, r2, #(0x1 << 9)     		/* Set EE bit to little-endian */
+	msr spsr_fsxc,r2
+
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the system stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x1F			/* SYS mode */
+	msr	cpsr, r2
+	ldr	r13,=SYS_stack			/* SYS stack pointer */
+
+	/*set scu enable bit in scu*/
+	ldr	r7, =0xf8f00000
+	ldr	r0, [r7]
+	orr	r0, r0, #0x1
+	str	r0, [r7]
+
+	/* enable MMU and cache */
+
+	ldr	r0,=TblBase			/* Load MMU translation table base */
+	orr	r0, r0, #0x5B			/* Outer-cacheable, WB */
+	mcr	15, 0, r0, c2, c0, 0		/* TTB0 */
+
+	mvn	r0,#0				/* Load MMU domains -- all ones=manager */
+	mcr	p15,0,r0,c3,c0,0
+
+	/* Enable mmu, icahce and dcache */
+	ldr	r0,=CRValMmuCac
+	mcr	p15,0,r0,c1,c0,0		/* Enable cache and MMU */
+	dsb					/* dsb	allow the MMU to start up */
+	isb					/* isb	flush prefetch buffer */
+
+	/* Write to ACTLR */
+	mrc	p15, 0, r0, c1, c0, 1		/* Read ACTLR*/
+	orr	r0, r0, #(0x01 << 6)		/* set SMP bit */
+	orr	r0, r0, #(0x01 )		/* Cache/TLB maintenance broadcast */
+	mcr	p15, 0, r0, c1, c0, 1		/* Write ACTLR*/
+
+/* Invalidate L2 Cache and enable L2 Cache*/
+/* For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux) */
+#if USE_AMP!=1
+	ldr	r0,=L2CCCrtl			/* Load L2CC base address base + control register */
+	mov	r1, #0				/* force the disable bit */
+	str	r1, [r0]			/* disable the L2 Caches */
+
+	ldr	r0,=L2CCAuxCrtl			/* Load L2CC base address base + Aux control register */
+	ldr	r1,[r0]				/* read the register */
+	ldr	r2,=L2CCAuxControl		/* set the default bits */
+	orr	r1,r1,r2
+	str	r1, [r0]			/* store the Aux Control Register */
+
+	ldr	r0,=L2CCTAGLatReg		/* Load L2CC base address base + TAG Latency address */
+	ldr	r1,=L2CCTAGLatency		/* set the latencies for the TAG*/
+	str	r1, [r0]			/* store the TAG Latency register Register */
+
+	ldr	r0,=L2CCDataLatReg		/* Load L2CC base address base + Data Latency address */
+	ldr	r1,=L2CCDataLatency		/* set the latencies for the Data*/
+	str	r1, [r0]			/* store the Data Latency register Register */
+
+	ldr	r0,=L2CCWay			/* Load L2CC base address base + way register*/
+	ldr	r2, =0xFFFF
+	str	r2, [r0]			/* force invalidate */
+
+	ldr	r0,=L2CCSync			/* need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET */
+						/* Load L2CC base address base + sync register*/
+	/* poll for completion */
+Sync:	ldr	r1, [r0]
+	cmp	r1, #0
+	bne	Sync
+
+	ldr	r0,=L2CCIntRaw			/* clear pending interrupts */
+	ldr	r1,[r0]
+	ldr	r0,=L2CCIntClear
+	str	r1,[r0]
+
+	ldr	r0,=SLCRUnlockReg		/* Load SLCR base address base + unlock register */
+	ldr	r1,=SLCRUnlockKey	    	/* set unlock key */
+	str	r1, [r0]		    	/* Unlock SLCR */
+
+	ldr	r0,=SLCRL2cRamReg		/* Load SLCR base address base + l2c Ram Control register */
+	ldr	r1,=SLCRL2cRamConfig        	/* set the configuration value */
+	str	r1, [r0]	        	/* store the L2c Ram Control Register */
+
+	ldr	r0,=SLCRlockReg         	/* Load SLCR base address base + lock register */
+	ldr	r1,=SLCRlockKey	        	/* set lock key */
+	str	r1, [r0]	        	/* lock SLCR */
+
+	ldr	r0,=L2CCCrtl			/* Load L2CC base address base + control register */
+	ldr	r1,[r0]				/* read the register */
+	mov	r2, #L2CCControl		/* set the enable bit */
+	orr	r1,r1,r2
+	str	r1, [r0]			/* enable the L2 Caches */
+#endif
+
+	mov	r0, r0
+	mrc	p15, 0, r1, c1, c0, 2		/* read cp access control register (CACR) into r1 */
+	orr	r1, r1, #(0xf << 20)		/* enable full access for p10 & p11 */
+	mcr	p15, 0, r1, c1, c0, 2		/* write back into CACR */
+
+	/* enable vfp */
+	fmrx	r1, FPEXC			/* read the exception register */
+	orr	r1,r1, #FPEXC_EN		/* set VFP enable bit, leave the others in orig state */
+	fmxr	FPEXC, r1			/* write back the exception register */
+
+	mrc	p15,0,r0,c1,c0,0		/* flow prediction enable */
+	orr	r0, r0, #(0x01 << 11)		/* #0x8000 */
+	mcr	p15,0,r0,c1,c0,0
+
+	mrc	p15,0,r0,c1,c0,1		/* read Auxiliary Control Register */
+	orr	r0, r0, #(0x1 << 2)		/* enable Dside prefetch */
+	orr	r0, r0, #(0x1 << 1)		/* enable L2 Prefetch hint */
+	mcr	p15,0,r0,c1,c0,1		/* write Auxiliary Control Register */
+
+	mrs	r0, cpsr			/* get the current PSR */
+	bic	r0, r0, #0x100			/* enable asynchronous abort exception */
+	msr	cpsr_xsf, r0
+
+
+	b	_start				/* jump to C startup code */
+	and	r0, r0, r0			/* no op */
+
+.Ldone:	b	.Ldone				/* Paranoia: we should never get here */
+
+
+/*
+ *************************************************************************
+ *
+ * invalidate_dcache - invalidate the entire d-cache by set/way
+ *
+ * Note: for Cortex-A9, there is no cp instruction for invalidating
+ * the whole D-cache. Need to invalidate each line.
+ *
+ *************************************************************************
+ */
+invalidate_dcache:
+	mrc	p15, 1, r0, c0, c0, 1		/* read CLIDR */
+	ands	r3, r0, #0x7000000
+	mov	r3, r3, lsr #23			/* cache level value (naturally aligned) */
+	beq	finished
+	mov	r10, #0				/* start with level 0 */
+loop1:
+	add	r2, r10, r10, lsr #1		/* work out 3xcachelevel */
+	mov	r1, r0, lsr r2			/* bottom 3 bits are the Cache type for this level */
+	and	r1, r1, #7			/* get those 3 bits alone */
+	cmp	r1, #2
+	blt	skip				/* no cache or only instruction cache at this level */
+	mcr	p15, 2, r10, c0, c0, 0		/* write the Cache Size selection register */
+	isb					/* isb to sync the change to the CacheSizeID reg */
+	mrc	p15, 1, r1, c0, c0, 0		/* reads current Cache Size ID register */
+	and	r2, r1, #7			/* extract the line length field */
+	add	r2, r2, #4			/* add 4 for the line length offset (log2 16 bytes) */
+	ldr	r4, =0x3ff
+	ands	r4, r4, r1, lsr #3		/* r4 is the max number on the way size (right aligned) */
+	clz	r5, r4				/* r5 is the bit position of the way size increment */
+	ldr	r7, =0x7fff
+	ands	r7, r7, r1, lsr #13		/* r7 is the max number of the index size (right aligned) */
+loop2:
+	mov	r9, r4				/* r9 working copy of the max way size (right aligned) */
+loop3:
+	orr	r11, r10, r9, lsl r5		/* factor in the way number and cache number into r11 */
+	orr	r11, r11, r7, lsl r2		/* factor in the index number */
+	mcr	p15, 0, r11, c7, c6, 2		/* invalidate by set/way */
+	subs	r9, r9, #1			/* decrement the way number */
+	bge	loop3
+	subs	r7, r7, #1			/* decrement the index */
+	bge	loop2
+skip:
+	add	r10, r10, #2			/* increment the cache number */
+	cmp	r3, r10
+	bgt	loop1
+
+finished:
+	mov	r10, #0				/* swith back to cache level 0 */
+	mcr	p15, 2, r10, c0, c0, 0		/* select current cache level in cssr */
+	dsb
+	isb
+
+	bx	lr
+
+.end
+/**
+* @} End of "addtogroup a9_boot_code".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/boot.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/boot.o
new file mode 100644
index 0000000000000000000000000000000000000000..b8641a36177a34b6ff0c231c21c6570c00d3fea6
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/boot.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/bspconfig.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/bspconfig.h
new file mode 100644
index 0000000000000000000000000000000000000000..87363749e348f1100d7bfdb61d6d5221c3260a14
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/bspconfig.h
@@ -0,0 +1,40 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Configurations for Standalone BSP
+*
+*******************************************************************/
+
+#define MICROBLAZE_PVR_NONE
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/changelog.txt b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/changelog.txt
new file mode 100644
index 0000000000000000000000000000000000000000..eb58ff2171f2efb807f5895c5d2b540000fd4b2e
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/changelog.txt
@@ -0,0 +1,461 @@
+/*****************************************************************************
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- ---------------------------------------------------
+  * 3.02a sdm  05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+ * 3.02a sdm  06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs
+ * 3.02a sdm  07/07/11 Updated ppc440 boot.S to set guarded bit for all but
+ *                     cacheable regions
+ *                     Update ppc440/xil_cache.c to use CACHEABLE_REGION_MASK
+ *                     generated by the cpu driver, for enabling caches
+ * 3.02a sdm  07/08/11 Updated microblaze cache flush APIs based on write-back/
+ *                     write-thru caches
+ * 3.03a sdm  08/20/11 Updated the tag/data RAM latency values for L2CC
+ *		       Updated the MMU table to mark OCM in high address space
+ *		       as inner cacheable and reserved space as Invalid
+ * 3.03a sdm  08/20/11 Changes to support FreeRTOS
+ *		       Updated the MMU table to mark upper half of the DDR as
+ *		       non-cacheable
+ *		       Setup supervisor and abort mode stacks
+ *		       Do not initialize/enable L2CC in case of AMP
+ *		       Initialize UART1 for 9600bps in case of AMP
+ * 3.03a sdm  08/27/11 Setup abort and supervisor mode stacks and don't init SMC
+ *		       in case of AMP
+ * 3.03a sdm  09/14/11 Added code for performance monitor and L2CC event
+ *		       counters
+ * 3.03a sdm  11/08/11 Updated microblaze xil_cache.h file to include
+ *		       xparameters.h file for CR630532 -  Xil_DCacheFlush()/
+ *		       Xil_DCacheFlushRange() functions in standalone BSP v3_02a
+ *		       for MicroBlaze will invalidate data in the cache instead
+ *		       of flushing it for writeback caches
+ * 3.04a sdm  11/21/11 Updated to initialize stdio device for 115200bps, for PS7
+ * 3.04a sdm  01/02/12 Updated to clear cp15 regs with unknown reset values
+ *		       Remove redundant dsb/dmb instructions in cache maintenance
+ *		       APIs
+ *		       Remove redundant dsb in mcr instruction
+ * 3.04a sdm  01/13/12 Updated MMU table to mark DDR memory as Shareable
+ * 3.05a sdm  02/02/12 Removed some of the defines as they are being generated through
+ *                     driver tcl in xparameters.h. Update the gcc/translationtable.s
+ *                     for the QSPI complete address range - DT644567
+ *                     Removed profile directory for armcc compiler and changed
+ *                     profiling setting to false in standalone_v2_1_0.tcl file
+ *                     Deleting boot.S file after preprocessing for armcc compiler
+ * 3.05a asa  03/11/12 Updated the function Xil_EnableMMU in file xil_mmu.c to
+ *		       invalidate the caches before enabling back the MMU and
+ *		       D cache.
+ * 3.05a asa  04/15/12 Updated the function Xil_SetTlbAttributes in file
+ *		       xil_mmu.c. Now we invalidate UTLB, Branch predictor
+ *		       array, flush the D-cache before changing the attributes
+ *		       in translation table. The user need not call Xil_DisableMMU
+ *		       before calling Xil_SetTlbAttributes.
+ * 3.06a asa/ 06/17/12 Removed the UART initialization for Zynq. For PEEP, the UART
+ *	 sgd	       initialization is present. Changes for this were done in
+ *		       uart.c and xil-crt0.s.
+ *		       Made changes in xil_io.c to use volatile pointers.
+ *		       Made changes in xil_mmu.c to correct the function
+ *		       Xil_SetTlbAttributes.
+ *		       Changes are made xil-crt0.s to initialize the static
+ *		       C++ constructors.
+ *		       Changes are made in boot.s, to fix the TTBR settings,
+ *		       correct the L2 Cache Auxiliary register settings, L2 cache
+ *		       latency settings.
+ * 3.07a asa/ 07/16/12 Made changes in cortexa9/xtime_l.c, xtime_l.h, sleep.c
+ *	 sgd	       usleep.c to use global timer intstead of CP15.
+ *		       Made changes in cortexa9/gcc/translation_table.s to map
+ *		       the peripheral devices as shareable device memory.
+ *		       Made changes in cortexa9/gcc/xil-crt0.s to initialize
+ *		       the global timer.
+ *		       Made changes in cortexa9/armcc/boot.S to initialize
+ *		       the global timer.
+ *		       Made changes in cortexa9/armcc/translation_table.s to
+ *		       map the peripheral devices as shareable device memory.
+ *		       Made changes in cortexa9/gcc/boot.S to optimize the
+ *		       L2 cache settings. Changes the section properties for
+ *		       ".mmu_tbl" and ".boot" sections in cortexa9/gcc/boot.S
+ *			and cortexa9/gcc/translation_table.S.
+ *		       Made changes in cortexa9/xil_cache.c to change the
+ *		       cache invalidation order.
+ * 3.07a asa  08/17/12 Made changes across files for Cortexa9 to remove
+ *		       compilation/linking issues for C++ compiler.
+ *		       Made changes in mb_interface.h to remove compilation/
+ *		       linking issues for C++ compiler.
+ *		       Added macros for swapb and swaph microblaze instructions
+ *		       mb_interface.h
+ *		       Remove barrier usage (SYNCHRONIZE_IO) from xil_io.c
+ *		       for CortexA9.
+ * 3.07a asa  08/30/12 Updated for CR 675636 to provide the L2 Base Address
+ * 3.07a asa  08/31/12 Added xil_printf.h include
+ * 3.07a sgd  09/18/12 Corrected the L2 cache enable settings
+ *				Corrected L2 cache sequence disable sequence
+ * 3.07a sgd  10/19/12 SMC NOR and SRAM initialization with compiler option
+ * 3.09a asa  01/25/13 Updated to push and pop neon registers into stack for
+ *		       irq/fiq handling.
+ *		       Relocated COUNTS_PER_SECOND from sleep.c to xtime_l.h. This
+ *		       fixes the CR #692094.
+ * 3.09a sgd  02/14/13 Fix for CRs 697094 (SI#687034) and 675552.
+ * 3.10a srt  04/18/13 Implemented ARM Erratas.
+ *		       Cortex A9 Errata - 742230, 743622, 775420, 794073
+ *		       L2Cache PL310 Errata - 588369, 727915, 759370
+ *		       Please refer to file 'xil_errata.h' for errata
+ *		       description.
+ * 3.10a asa  05/04/13 Added support for L2 cache in MicroBlaze BSP. The older
+ *		       cache APIs were corresponding to only Layer 1 cache
+ *		       memories. New APIs were now added and the existing cache
+ *		       related APIs were changed to provide a uniform interface
+ *		       to flush/invalidate/enable/disable the complete cache
+ *		       system which includes both L1 and L2 caches. The changes
+ *		       for these were done in:
+ *		       src/microblaze/xil_cache.c and src/microblaze/xil_cache.h
+ *		       files.
+ *		       Four new files were added for supporting L2 cache. They are:
+ *		       microblaze_flush_cache_ext.S-> Flushes L2 cache
+ *		       microblaze_flush_cache_ext_range.S -> Flushes a range of
+ *		       memory in L2 cache.
+ *		       microblaze_invalidate_cache_ext.S-> Invalidates L2 cache
+ *		       microblaze_invalidate_cache_ext_range -> Invalidates a
+ *		       range of memory in L2 cache.
+ *		       These changes are done to implement PR #697214.
+ * 3.10a  asa 05/13/13 Modified cache disable APIs at src/cortexa9/xil_cache.c to
+ *		       fix the CR #706464. L2 cache disabling happens independent
+ *		       of L1 data cache disable operation. Changes are done in the
+ *		       same file in cache handling APIs to do a L2 cache sync
+ *		       (poll reg7_?cache_?sync). This fixes CR #700542.
+ * 3.10a asa  05/20/13 Added API/Macros for enabling and disabling nested
+ *		       interrupts for ARM. These are done to fix the CR#699680.
+ * 3.10a srt  05/20/13 Made changes in cache maintenance APIs to do a proper cach
+ *		       sync operation. This fixes the CR# 716781.
+ * 3.11a asa  09/07/13 Updated armcc specific BSP files to have proper support
+ *		       for armcc toolchain.
+ *		       Modified asm_vectors.S (gcc) and asm_vectors.s (armcc) to
+ *		       fix issues related to NEON context saving. The assembly
+ *		       routines for IRQ and FIQ handling are modified.
+ *		       Deprecated the older BSP (3.10a).
+ * 3.11a asa  09/22/13 Fix for CR#732704. Cache APIs are modified to avoid
+ *		       various potential issues. Made changes in the function
+ *		       Xil_SetAttributes in file xil_mmu.c.
+ * 3.11a asa  09/23/13 Added files xil_misc_psreset_api.c and xil_misc_psreset_api.h
+ *		       in src\cortexa9 and src\microblaze folders.
+ * 3.11a asa  09/28/13 Modified the cache APIs (src\cortexa9) to fix handling of
+ *		       L2 cache sync operation and to fix issues around complete
+ *		       L2 cache flush/invalidation by ways.
+ * 3.12a asa  10/22/13 Modified the files xpseudo_asm_rvct.c and xpseudo_asm_rvct.h
+ *		       to fix linking issues with armcc/DS-5. Modified the armcc
+ *		       makefile to fix issues.
+ * 3.12a asa  11/15/13 Fix for CR#754800. It fixes issues around profiling for MB.
+ * 4.0   hk   12/13/13 Added check for STDOUT_BASEADDRESS where outbyte is used.
+ * 4.0 	 pkp  22/01/14 Modified return addresses for interrupt handlers (DataAbortHandler
+ *		       and SWIHandler) in asm_vector.S (src\cortexa9\gcc\ and
+ *		       src\cortexa9\armcc\) to fix CR#767251
+ * 4.0	 pkp  24/01/14 Modified cache APIs (Xil_DCacheInvalidateRange and
+ *		       Xil_L1DCacheInvalidate) in xil_cache.c (src\cortexa9) to fix the bugs.
+ *		       Few cache lines were missed to invalidate when unaligned address
+ *		       invalidation was accommodated in Xil_DCacheInvalidateRange.
+ *		       In Xil_L1DCacheInvalidate, while invalidating all L1D cache
+ *		       stack memory (which contains return address) was invalidated. So
+ *		       stack memory is flushed first and then L1D cache is invalidated.
+ *		       This is done to fix CR #763829
+ * 4.0 adk   22/02/2014 Fixed the CR:775379 removed unnecessay _t(unit32_t etc) from
+ *			mblaze_nt_types.h file and replace uint32_t with u32 in the
+ *			profile_hist.c to fix the above CR.
+ * 4.1 bss   04/14/14  Updated driver tcl to remove _interrupt_handler.o from libgloss.a
+ * 		       instead of libxil.a and added prototypes for
+ *		       microblaze_invalidate_cache_ext and microblaze_flush_cache_ext in
+ *		       mb_interface.h
+ * 4.1 hk    04/18/14  Add sleep function.
+ * 4.1 asa   04/21/14  Fix for CR#764881. Added support for msrset and msrclr. Renamed
+ *		       some of the *.s files inMB BSP source to *.S.
+ * 4.1 asa   04/28/14  Fix for CR#772280. Made changes in file cortexa9/gcc/read.c.
+ * 4.1 bss   04/29/14  Modified driver tcl to use libxil.a if libgloss.a does not exist
+ *			CR#794205
+ * 4.1 asa   05/09/14  Fix for CR#798230. Made changes in cortexa9/xil_cache.c and
+ *		       common/xil_testcache.c
+ *	               Fix for CR#764881.
+ * 4.1 srt   06/27/14  Remove '#undef DEBUG' from src/common/xdebug.h, which allows to
+ *                     output the DEBUG logs when -DDEBUG flag is enabled in BSP.
+ * 4.2 pkp   06/27/14  Added support for IAR compiler in src/cortexa9/iccarm.
+ *		       Also added explanatory notes in cortexa9/xil_cache.c for CR#785243.
+ * 4.2 pkp   06/19/14  Asynchronous abort has been enabled into cortexa9/gcc/boot.s and
+ *		       cortexa9/armcc/boot.s. Added default exception handlers for data
+ *		       abort and prefetch abort using handlers called
+ *		       DataAbortHandler and PrefetchAbortHandler respectively in
+ *		       cortexa9/xil_exception.c to fix CR#802862.
+ * 4.2 pkp   06/30/14  MakeFile for cortexa9/armcc has been changed to fixes the
+ *		       issue of improper linking of translation_table.s
+ * 4.2 pkp   07/04/14  added weak attribute for the function in BSP which are also present
+ *		       in tool chain to avoid conflicts into some special cases
+ * 4.2 pkp   07/21/14  Corrected reset value of event counter in function
+ *		       Xpm_ResetEventCounters in src/cortexa9/xpm_counter.c to fix CR#796275
+ * 4.2 pkp   07/21/14  Included xil_types.h file in xil_mmu.h which had contained a function
+ * 		       containing type def u32 defined in xil_types.g to resolve issue of
+ *		       CR#805869
+ * 4.2 pkp   08/04/14  Removed unimplemented nanosleep routine from cortexa9/usleep.c as
+ *		       it is not possible to generate timer in nanosecond due to limited
+ *		       cpu frequency
+ * 4.2 pkp   08/04/14  Removed PEEP board related code which contained initialization of
+ *		       uart, smc nor and sram from cortexa9/gcc/xil-crt0.s and armcc/boot.s
+ *		       and iccarm/boot.s. Also uart.c and smc.c have been removed. Also
+ *		       removed function definition of XSmc_NorInit and XSmc_NorInit from
+ *		       cortexa9/smc.h
+ * 4.2 bss   08/11/14  Added microblaze_flush_cache_ext_range and microblaze_invalidate_
+ *		       cache_ext_range declarations in mb_interface.h CR#783821.
+ *		       Modified profile_mcount_mb.S to fix CR#808412.
+ * 4.2 pkp   08/21/14  modified makefile of iccarm for proper linking of objectfiles in
+ *		       cortexa9/iccarm to fix CR#816701
+ * 4.2 pkp   09/02/14  modified translation table entries in cortexa9/gcc/translation_table.s,
+ *		       armcc/translation_table.s and iccarm/translation_table.s
+ *		       to properly defined reserved entries according to address map for
+ *		       fixing CR#820146
+ * 4.2 pkp   09/11/14  modified translation table entries in cortexa9/iccarm/translation_table.s
+ *		       and  cortexa9/armcc/translation_table.s to resolve compilation
+ *		       error for solving CR#822897
+ * 5.0 kvn   12/9/14   Support for Zync Ultrascale Mp.Also modified code for
+ *                     MISRA-C:2012 compliance.
+ * 5.0 pkp   12/15/14  Added APIs to get information about the platforms running the code by
+ *		       adding src/common/xplatform_info.*s
+ * 5.0 pkp   16/12/14  Modified boot code to enable scu after MMU is enabled and
+ *		       removed incorrect initialization of TLB lockdown register to fix
+ *		       CR#830580 in cortexa9/gcc/boot.S & cpu_init.S, armcc/boot.S
+ *		       and iccarm/boot.s
+ * 5.0 pkp   25/02/15  Modified floating point flag to vfpv3 from vfpv3_d16 in BSP MakeFile
+ *		       for iccarm and armcc compiler of cortexA9
+ * 5.1 pkp   05/13/15  Changed the initialization order in cortexa9/gcc/boot.S, iccarm/boot.s
+ *		       and armcc/boot.s so to first invalidate caches and TLB, enable MMU and
+ *		       caches, then enable SMP bit in ACTLR. L2Cache invalidation and enabling
+ *		       of L2Cache is done later.
+ * 5.1 pkp   12/05/15  Modified cortexa9/xil_cache.c to modify Xil_DCacheInvalidateRange and
+ *		       Xil_DCacheFlushRange to remove unnecessary dsb which is unnecessarily
+ *		       taking long time to fix CR#853097. L2CacheSync is added into
+ *		       Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate and
+ *		       Xil_L2CacheInvalidate APIs are modified to flush the complete stack
+ *		       instead of just System Stack
+ * 5.1 pkp   14/05/15  Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
+ *		       to update ECC_FLAGS and also take the compiler and archiver as specified
+ *		       in settings instead of hardcoding it.
+ * 5.2 pkp   06/08/15  Modified cortexa9/gcc/translation_table.S to put a check for
+ *		       XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm if DDR is present or not and
+ *		       accordingly generate the	translation table
+ * 5.2 pkp   23/07/15  Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
+ *		       to update ECC_FLAGS to fix a bug introduced during new version creation
+ *		       of BSP.
+ * 5.3 pkp   10/07/15  Modified cortexa9/xil_cache.c file to change cache API so that L2 Cache
+ *		       functionalities are avoided for the OpenAMP slave application(when
+ *		       USE_AMP flag is defined for BSP) as master CPU would be utilizing L2
+ *		       cache for its operation. Also file operations such as read, write,
+ *		       close, open are also avoided for OpenAMP support(when USE_AMP flag is
+ *		       defined for BSP) because XilOpenAMP library contains own file operation.
+ *		       The xil-crt0.S file is modified for not initializing global timer for
+ *		       OpenAMP application as it might be already in use by master CPU
+ * 5.3 pkp   10/09/15  Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to change function
+ *		       definition for dsb, isb and dmb to fix the compilation error when used
+ *     kvn   16/10/15  Encapsulated assembly code into macros for R5 xil_cache file.
+ * 5.4 pkp   09/11/15  Modified cortexr5/gcc/boot.S to disable ACTLR.DBWR bit to avoid potential
+ *		       R5 deadlock for errata 780125
+ * 5.4 pkp   09/11/15  Modified cortexa53/32bit/gcc/boot.S to enable I-Cache and D-Cache for a53
+ *		       32 bit BSP in the initialization
+ * 5.4 pkp   09/11/15  Modified cortexa9/xil_misc_psreset_api.c file to change the description
+ *		       for XOcm_Remap function
+ * 5.4 pkp   16/11/15  Modified microblaze/xil_misc_psreset_api.c file to change the description
+ *		       for XOcm_Remap function
+ *     kvn   21/11/15  Added volatile keyword for ADDR varibles in Xil_Out API
+ *     kvn   21/11/15  Changed ADDR variable type from u32 to UINTPTR. This is
+ *                     required for MISRA-C:2012 Compliance.
+ * 5.4 pkp   23/11/15  Added attribute definitions for Xil_SetTlbAttributes API of Cortex-A9
+ *		       in cortexa9/xil_mmu.h
+ * 5.4 pkp   23/11/15  Added default undefined exception handler for Cortex-A9
+ * 5.4 pkp   11/12/15  Modified common/xplatform_info.h to add #defines for silicon for
+ *		       checking the current executing platform
+ * 5.4 pkp   18/12/15  Modified cortexa53/32bit/gcc/xil-crt0.S and 64bit/gcc/xil-crt0.S
+ *		       to initialize global constructor for C++ applications
+ * 5.4 pkp   18/12/15  Modified cortexr5/gcc/xil-crt0.S to initialize global constructor for
+ *		       C++ applications
+ * 5.4 pkp   18/12/15  Modified cortexa53/32bit/gcc/translation_table.S and 64bit/gcc/
+ *		       translation_table.S to update the translation table according to proper
+ *		       address map
+ * 5.4 pkp   18/12/15  Modified cortexar5/mpu.c to initialize the MPU according to proper
+ *		       address map
+ * 5.4	pkp  05/01/16  Modified cortexa53/64bit/boot.S to set the reset vector register RVBAR
+ *		       equivalent to vector table base address
+ * 5.4 pkp   08/01/16  Modified cortexa9/gcc/Makefile to update the extra compiler flag
+ *		       as per the toolchain update
+ * 5.4 pkp   12/01/16  Changed common/xplatform_info.* to add platform information support
+ *		       for Cortex-A53 32bit mode
+ * 5.4 pkp   28/01/16  Modified cortexa53/32bit/sleep.c and usleep.c & cortexa53/64bit/sleep.c
+ *		       and usleep.c to correct routines to avoid hardcoding the timer frequency,
+ *		       instead take it from xparameters.h to properly configure the timestamp
+ *		       clock frequency
+ * 5.4 asa   29/01/16  Modified microblaze/mb_interface.h to add macros that support the
+ *		       new instructions for MB address extension feature
+ * 5.4 kvn   30/01/16  Modified xparameters_ps.h file to add interrupt ID number for
+ *		       system monitor.
+ * 5.4 pkp   04/02/16  Modified cortexr5/gcc/boot.S to enable fault log for lock-step mode
+ * 5.4 pkp   19/02/16  Modified cortexr5/xtime_l.c to add an API XTime_StartTimer and updated
+ *		       cortexr5/xil-crt0.S to configure the TTC3 timer when present. Modified
+ *		       cortexr5/sleep.c, cortexr5/usleep.c to use TTC3 when present otherwise
+ *		       use set of assembly instructions to provide required delay to fix
+ *		       CR#913249.
+ * 5.4 asa   25/02/16  Made changes in xil-crt0.S for R5, A53 64 and 32 bit BSPs, to replace
+ *		       _exit with exit. We should not be directly calling _exit and should
+ *		       always use the library exit. This fixes the CR#937036.
+ * 5.4 pkp   25/02/16  Made change to cortexr5/gcc/boot.S to initialize the floating point
+ *		       registers, banked registers for various modes and enabled
+ *		       the cache ECC check before enabling the fault log for lock step mode
+ *		       Also modified the cortexr5/gcc/Makefile to support floating point
+ *		       registers initialization in boot code.
+ * 5.4 pkp   03/01/16  Updated the exit function in cortexr5/gcc/_exit.c to enable the debug
+ *		       logic in case of lock-step mode when fault log is enabled to fix
+ *		       CR#938281
+ * 5.4 pkp   03/02/16  Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to include
+ *		       header file instrinsics.h which contains assembly instructions
+ *		       definitions which can be used by C
+ * 5.4 asa   03/02/16  Added print.c in MB BSP. Made other cosmetic changes to have uniform
+ *                     proto for all print.c across the BSPs. This patch fixes CR#938738.
+ * 5.4 pkp   03/09/16  Modified cortexr5/sleep.c and usleep.c to avoid disabling the
+ *		       interrupts when sleep/usleep is being executed using assembly
+ *		       instructions to fix CR#913249.
+ * 5.4 pkp   03/11/16  Modified cortexr5/xtime_l.c to avoid enabling overflow interrupt,
+ *		       instead modified cortexr5/sleep.c and usleep.c to poll the counter
+ *		       value and compare it with previous value to detect the overflow
+ *		       to fix CR#940209.
+ * 5.4 pkp   03/24/16  Modified cortexr5/boot.S to reset the dbg_lpd_reset before enabling
+ *		       the fault log to avoid intervention for lock-step mode and cortexr5/
+ *		       _exit.c to enable the dbg_lpd_reset once the fault log is disabled
+ *		       to fix CR#947335
+ * 5.5 pkp   04/11/16  Modified cortexr5/boot.S to enable comparators for non-JTAG bootmode
+ *		       in lock-step to avoid resetting the debug logic which restricts the
+ *		       access for debugger and removed enabling back of debug modules in
+ *		       cortexr5/_exit.c
+ * 5.5 pkp   04/13/16  Modified cortexa9/gcc/read.c to return correct number of bytes when
+ *		       read buffer is filled and removed the redundant NULL checking for
+ *		       buffer to simplify the code
+ * 5.5 pkp   04/13/16  Modified cortexa53/64bit/gcc/read.c and cortexa53/32bit/gcc/read.c
+ *		       to return correct number of bytes when read buffer is filled and
+ *		       removed the redundant NULL checking for buffer to simplify the code
+ * 5.5 pkp   04/13/16  Modified cortexr5/gcc/read.c to return correct number of bytes when
+ *		       read buffer is filled and removed the redundant NULL checking for
+ *		       buffer to simplify the code
+ * 5.5 pkp   04/13/16  Modified cortexa53/64bit/xpseudo_asm_gcc.h to add volatile to asm
+ *		       instruction macros to disable certain optimizations which may move
+ *		       code out of loops if optimizers believe that the code will always
+ *		       return the same result or discard asm statements if optimizers
+ *		       determine there is no need for the output variables
+ * 5.5 pkp   04/13/16  Modified cortexa53/64bit/xtime_l.c to add XTime_StartTimer which
+ *		       starts the timer if it is disabled and modified XTime_GetTime to
+ *		       enable the timer if it is not enabled. Also modified cortexa53/64bit/
+ *		       sleep.c and cortexa53/64bit/usleep.c to enable the timer if it is
+ *		       disabled and read the counter value directly from register instead
+ *		       of using XTime_GetTime for optimization
+ * 5.5 pkp   04/13/16  Modified cortexa53/32bit/xtime_l.c to add XTime_StartTimer which
+ *		       starts the timer if it is disabled and modified XTime_GetTime to
+ *		       enable the timer if it is not enabled. Also modified cortexa53/32bit/
+ *		       sleep.c and cortexa53/32bit/usleep.c to enable the timer if it is
+ *		       disabled and read the counter value directly from register instead
+ *		       of using XTime_GetTime for optimization
+ * 5.5 pkp   04/13/16  Modified cortexa53/32bit/xil_cache.c and cortexa53/64bit/xil_cache.c
+ *		       to update the Xil_DCacheInvalidate, Xil_DCacheInvalidateLine and
+ * 		       Xil_DCacheInvalidateRange functions description for proper
+ *		       explaination to fix CR#949801
+ * 5.5 asa   04/20/16  Added missing macros for hibernate and suspend in Microblaze BSP
+ *                     file mb_interface.h. This fixes the CR#949503.
+ * 5.5 asa   04/29/16  Fix for CR#951080. Updated cache APIs for HW designs where cache
+ *                     memory is not included for MicroBlaze.
+ * 5.5 pkp   05/06/16  Modified the cortexa9/xil_exception.h to update the macros
+ *		       Xil_EnableNestedInterrupts and Xil_DisableNestedInterrupts for fixing
+ *		       the issue of lr being corrupted to resolve CR#950468
+ * 5.5 pkp   05/06/16  Modified the cortexr5/xil_exception.h to update the macros
+ *		       Xil_EnableNestedInterrupts and Xil_DisableNestedInterrupts for fixing
+ *		       the issue of lr being corrupted to resolve CR#950468
+ * 6.0 kvn   05/31/16  Make Xil_AsserWait a global variable
+ * 6.0 pkp   06/27/16  Updated cortexr5/mpu.c to move the code related to Init_MPU to .boot
+ *		       section since it is part of boot process to fix CR#949555
+ *     hk    07/12/16  Correct masks for IOU SLCR GEM registers
+ * 6.0 pkp   07/25/16  Program the counter frequency in boot code for CortexA53
+ * 6.0 asa   08/03/16  Updated sleep_common function in microblaze_sleep.c to improve the
+ *                     the accuracy of MB sleep functionality. This fixes the CR#954191.
+ * 6.0 mus   08/03/16  Restructured the BSP to avoid code duplication across all BSPs.
+ *                     Source code directories specific to ARM processor's are moved to src/arm
+ *                     directory(i.e. src/cortexa53,src/cortexa9 and src/cortexr5 moved to src/arm/cortexa53,
+ *                     src/arm/cortexa9 and src/arm/cortexr5 respectively).Files xil_printf.c,xil_printf.h,
+ *                     print.c,xil_io.c and xil_io.h are consolidated across all BSPs into common file each and
+ *                     consolidated files are kept at src/common directory.Files putnum.c,vectors.c,vectors.h,
+ *                     xil_exception.c and xil_exception.h are consolidated across all ARM BSPs
+ *                     into common file each and consolidated files are kept at src/arm/common directory.
+ *                     GCC source files related to file  operations are consolidated and kept
+ *                     at src/arm/common/gcc directory.
+ *                     All io interfacing functions (i.e. All variants of xil_out, xil_in )
+ *                     are made as static inline and implementation is kept in consolidated common/xil_io.h,
+ *                     xil_io.h must be included as a header file to access io interfacing functions.
+ *                     Added undefined exception handler for A53 32 bit and R5 processor
+ * 6.0 mus   08/11/16  Updated xtime_l.c in R5 BSP to remove implementation of XTime_SetTime API, since
+ *                     TTC counter value register is read only.
+ * 6.0 asa   08/15/16  Modified the signatures for functions sleep and usleep. This fixes
+ *                     the CR#956899.
+ * 6.0 mus   08/18/16  Defined ARMA53_32 flag in cortexa53/32bit/xparameters_ps.h and ARMR5 flag
+ *                     in cortexr5/xparameters_ps.h
+ * 6.0 mus   08/18/16  Added support for the the Zynq 7000s devices
+ * 6.0 mus   08/18/16  Removed unused variables from xil_printf.c and xplatform_info.c
+ * 6.0 mus   08/19/16  Modified xil_io.h to remove __LITTLE_ENDIAN__ flag check for all ARM processors
+ * 6.1 mus   11/03/16  Added APIs handle_stdin_parameter and handle_stdout_parameter in standalone tcl.
+ *                     ::hsi::utils::handle_stdin and ::hsi::utils::handle_stdout are taken as a base for
+ *                     these APIs and modifications are done on top of it to handle stdout/stdin
+ *                     parameters for design which doesnt have UART.It fixes CR#953681
+ * 6.1 nsk   11/07/16  Added two new files xil_mem.c and xil_mem.h for xil_memcpy
+ * 6.2 pkp   12/14/16  Updated cortexa53/64bit/translation_table.S for upper ps DDR. The 0x800000000 -
+ *		       0xFFFFFFFFF range is marked normal memory for the DDR size defined in hdf
+ *		       and rest of the memory in that 32GB region is marked as reserved to avoid
+ *		       any speculative access
+ * 6.2 pkp   12/23/16  Added support for floating point operation to Cortex-A53 64bit mode. It modified
+ *		       asm_vectors.S to implement lazy floating point context saving i.e. floating point
+ *		       access is enabled if there is any floating point operation, it is disabled by
+ *		       default. Also FPU is initally disabled for IRQ and none of the floating point
+ *		       registers are saved during normal context saving. If IRQ handler does not require
+ *		       floating point operation, the floating point registers are untouched and no need
+ *		       for saving/restoring. If IRQ handler uses any floating point operation, then floating
+ *		       point registers are saved and FPU is enabled for IRQ handler. Then floating point
+ *		       registers are restored back after servicing IRQ during normal context restoring.
+ * 6.2 mus   01/01/17  Updated makefiles of R5 and a53 64 bit/32 bit processors to fix error in clean
+ *                     target.It fixes the CR#966900
+ * 6.2 pkp   01/22/17  Added support for EL1 non-secure execution and Hypervisor Baremetal for Cortex-A53
+ *		       64bit Mode. If Hypervisor_guest is selected as true in BSP settings, BSP will be built
+ *		       for EL1 Non-secure, else BSP will be built for EL3. By default hypervisor_guest is
+ *		       as false i.e. default bsp is EL3.
+ * 6.2 pkp   01/24/17  Updated cortexa53/64bit/boot.S to clear FPUStatus variable to make sure that it
+ *		       contains initial status of FPU i.e. disabled. In case of a warm restart execution
+ *		       when bss sections are not cleared, it may contain previously updated value which
+ *		       does not hold true once processor resumes. This fixes CR#966826.
+ * 6.2 asa   01/31/17  The existing Xil_DCacheDisable API first flushes the
+ *		       D caches and then disables it. The problem with that is,
+ *		       potentially there will be a small window after the cache
+ *		       flush operation and before the we disable D caches where
+ *		       we might have valid data in cache lines. In such a
+ *		       scenario disabling the D cache can lead to unknown behavior.
+ *		       The ideal solution to this is to use assembly code for
+ *		       the complete API and avoid any memory accesses. But with
+ *		       that we will end up having a huge amount on assembly code
+ *		       which is not maintainable. Changes are done to use a mix
+ *		       of assembly and C code. All local variables are put in
+ *		       registers. Also function calls are avoided in the API to
+ *		       avoid using stack memory.
+ * 6.2 mus   02/13/17 A53 CPU cache system can pre-fetch catch lines.So there are
+ *                    scenarios when an invalidated cache line can get pre fetched to cache.
+ *                    If that happens, the coherency between cache and memory is lost
+ *                    resulting in lost data. To avoid this kind of issue either
+ *                    user has to use dsb() or disable pre-fetching for L1 cache
+ *                    or else reduce maximum number of outstanding data prefetches allowed.
+ *                    Using dsb() while comparing data costing more performance compared to
+ *                    disabling pre-fetching/reducing maximum number of outstanding data
+ *                    prefetches for L1 Cache.The new api Xil_ConfigureL1Prefetch is added
+ *                    to disable pre-fetching/configure maximum number of outstanding data
+ *                    prefetches allowed in L1 cache system.This fixes CR#967864.
+ * 6.2 pkp   02/16/17 Added xil_smc.c file to provide a C wrapper for smc calling which can be
+ *		      used by cortex-A53 64bit EL1 Non-secure application.
+ * 6.2 kvn   03/03/17 Added support thumb mode
+ * 6.2 mus   03/13/17 Fixed MISRA C mandatory standard violations in ARM cortexr5 and cortexa53 BSP.
+ *                    It fixes CR#970543
+ * 6.2 asa   03/16/17 Fix for CR#970859. For Mcroblaze BSP, when we enable intrusive
+ *                    profiling we see a crash. That is because the the tcl uses invalid
+ *                    HSI command. This change fixes it.
+ * 6.2 mus   03/22/17 Updated standalone tcl to generate xparameter XPAR_FPD_IS_CACHE_COHERENT, if
+ *                    any FPD peripheral is configured to use CCI.It fixes CR#972638
+ *
+ *****************************************************************************************/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/close.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/close.c
new file mode 100644
index 0000000000000000000000000000000000000000..dbbe0d4fd06f59e1cdd29e8bfa7f6d87db119537
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/close.c
@@ -0,0 +1,49 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#ifndef UNDEFINE_FILE_OPS
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _close(s32 fd);
+}
+#endif
+
+/*
+ * close -- We don't need to do anything, but pretend we did.
+ */
+
+__attribute__((weak)) s32 _close(s32 fd)
+{
+  (void)fd;
+  return (0);
+}
+#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/close.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/close.o
new file mode 100644
index 0000000000000000000000000000000000000000..7243c674dc29794520301e634e5a4ec7fbf4bc45
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/close.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/config.make b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/config.make
new file mode 100644
index 0000000000000000000000000000000000000000..2668199bfdf5ebf427fd279c95c8ece05f0e450f
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/config.make
@@ -0,0 +1,3 @@
+LIBSOURCES = *.c *.S
+PROFILE_ARCH_OBJS = profile_mcount_arm.o
+LIBS = standalone_libs
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/cpu_init.S b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/cpu_init.S
new file mode 100644
index 0000000000000000000000000000000000000000..2b4048f3b3c89234397b7bb51bd539007cccb537
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/cpu_init.S
@@ -0,0 +1,80 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file cpu_init.s
+*
+* This file contains CPU specific initialization. Invoked from main CRT
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 10/20/09 Initial version
+* 3.04a sdm	01/02/12 Updated to clear cp15 regs with unknown reset values
+* 5.0   pkp	12/16/14 removed incorrect initialization of TLB lockdown
+*			 register to fix CR#830580
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+	.text
+	.global __cpu_init
+	.align 2
+__cpu_init:
+
+/* Clear cp15 regs with unknown reset values */
+	mov	r0, #0x0
+	mcr	p15, 0, r0, c5, c0, 0	/* DFSR */
+	mcr	p15, 0, r0, c5, c0, 1	/* IFSR */
+	mcr	p15, 0, r0, c6, c0, 0	/* DFAR */
+	mcr	p15, 0, r0, c6, c0, 2	/* IFAR */
+	mcr	p15, 0, r0, c9, c13, 2	/* PMXEVCNTR */
+	mcr	p15, 0, r0, c13, c0, 2	/* TPIDRURW */
+	mcr	p15, 0, r0, c13, c0, 3	/* TPIDRURO */
+
+/* Reset and start Cycle Counter */
+	mov	r2, #0x80000000		/* clear overflow */
+	mcr	p15, 0, r2, c9, c12, 3
+	mov	r2, #0xd		/* D, C, E */
+	mcr	p15, 0, r2, c9, c12, 0
+	mov	r2, #0x80000000		/* enable cycle counter */
+	mcr	p15, 0, r2, c9, c12, 1
+
+	bx	lr
+
+.end
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/cpu_init.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/cpu_init.o
new file mode 100644
index 0000000000000000000000000000000000000000..ec06122e57698ac855d04edcfc9ebab8f68b759e
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diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/errno.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/errno.c
new file mode 100644
index 0000000000000000000000000000000000000000..df0218e865194a13e2fec8e1bca030fb2d8574ad
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/errno.c
@@ -0,0 +1,51 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/* The errno variable is stored in the reentrancy structure.  This
+   function returns its address for use by the macro errno defined in
+   errno.h.  */
+
+#include <errno.h>
+#include <reent.h>
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) sint32 * __errno (void);
+}
+#endif
+
+__attribute__((weak)) sint32 *
+__errno (void)
+{
+  return &_REENT->_errno;
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/errno.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/errno.o
new file mode 100644
index 0000000000000000000000000000000000000000..0f78e60ef1b15109d051952470bb699373e63ddb
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/errno.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/fcntl.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/fcntl.c
new file mode 100644
index 0000000000000000000000000000000000000000..e58221a14039f3333e6512081f8e69b9f0e7ab6d
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/fcntl.c
@@ -0,0 +1,46 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include <stdio.h>
+#include "xil_types.h"
+
+/*
+ * fcntl -- Manipulate a file descriptor.
+ *          We don't have a filesystem, so we do nothing.
+ */
+__attribute__((weak)) sint32 fcntl (sint32 fd, sint32 cmd, long arg)
+{
+  (void)fd;
+  (void)cmd;
+  (void)arg;
+  return 0;
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/fcntl.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/fcntl.o
new file mode 100644
index 0000000000000000000000000000000000000000..13b3830a84b843478384e83763d6632774fd410e
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/fcntl.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/fstat.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/fstat.c
new file mode 100644
index 0000000000000000000000000000000000000000..c5a31f31ba16956a039eb9f88817541bf55d76a1
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/fstat.c
@@ -0,0 +1,50 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include <sys/stat.h>
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf);
+}
+#endif
+/*
+ * fstat -- Since we have no file system, we just return an error.
+ */
+__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf)
+{
+  (void)fd;
+  buf->st_mode = S_IFCHR; /* Always pretend to be a tty */
+
+  return (0);
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/fstat.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/fstat.o
new file mode 100644
index 0000000000000000000000000000000000000000..d97b151f8597fab855db7701fbf440b5392ab82d
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/fstat.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/getpid.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/getpid.c
new file mode 100644
index 0000000000000000000000000000000000000000..d02df5ce2eaaf24db17fc25ec219bb53ec1cc625
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/getpid.c
@@ -0,0 +1,51 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "xil_types.h"
+/*
+ * getpid -- only one process, so just return 1.
+ */
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _getpid(void);
+}
+#endif
+
+__attribute__((weak)) s32 getpid(void)
+{
+  return 1;
+}
+
+__attribute__((weak)) s32 _getpid(void)
+{
+  return 1;
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/getpid.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/getpid.o
new file mode 100644
index 0000000000000000000000000000000000000000..f183906d10bbe783b4969463cdc703c1d291cab0
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/getpid.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/inbyte.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/inbyte.c
new file mode 100644
index 0000000000000000000000000000000000000000..0036459e40288e21e8d2017d9d8aee0e43a40a76
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/inbyte.c
@@ -0,0 +1,14 @@
+#include "xparameters.h"
+#include "xuartps_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+char inbyte(void);
+#ifdef __cplusplus
+}
+#endif 
+
+char inbyte(void) {
+	 return XUartPs_RecvByte(STDIN_BASEADDRESS);
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/inbyte.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/inbyte.o
new file mode 100644
index 0000000000000000000000000000000000000000..efe658ab65024298fe95ab5bc1467e4e8224dae7
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/inbyte.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/isatty.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/isatty.c
new file mode 100644
index 0000000000000000000000000000000000000000..f142515110adffb71ef1c92aa10925066ce61ef5
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/isatty.c
@@ -0,0 +1,56 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#include <unistd.h>
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) sint32 _isatty(sint32 fd);
+}
+#endif
+
+/*
+ * isatty -- returns 1 if connected to a terminal device,
+ *           returns 0 if not. Since we're hooked up to a
+ *           serial port, we'll say yes _AND return a 1.
+ */
+__attribute__((weak)) sint32 isatty(sint32 fd)
+{
+  (void)fd;
+  return (1);
+}
+
+__attribute__((weak)) sint32 _isatty(sint32 fd)
+{
+  (void)fd;
+  return (1);
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/isatty.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/isatty.o
new file mode 100644
index 0000000000000000000000000000000000000000..5498c7d93d8c3a61deae2375a235e53bf4162ac3
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/isatty.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/kill.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/kill.c
new file mode 100644
index 0000000000000000000000000000000000000000..fc2f89d6cc6c9f6194a1a950f7f9e30219c1ea9c
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/kill.c
@@ -0,0 +1,60 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#include <signal.h>
+#include <unistd.h>
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) int _kill(pid_t pid, int sig);
+}
+#endif
+
+/*
+ * kill -- go out via exit...
+ */
+
+__attribute__((weak)) int kill(pid_t pid, int sig)
+{
+  if(pid == 1) {
+    _exit(sig);
+  }
+  return 0;
+}
+
+__attribute__((weak)) int _kill(pid_t pid, int sig)
+{
+  if(pid == 1) {
+    _exit(sig);
+  }
+  return 0;
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/kill.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/kill.o
new file mode 100644
index 0000000000000000000000000000000000000000..135ee9a82c6d52c86a2d065ec7f7b2ee65d4154d
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/kill.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/lseek.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/lseek.c
new file mode 100644
index 0000000000000000000000000000000000000000..106c45c891d86912e4c527e4a735773c0a829a08
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/lseek.c
@@ -0,0 +1,61 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include <sys/types.h>
+#include <errno.h>
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence);
+}
+#endif
+/*
+ * lseek --  Since a serial port is non-seekable, we return an error.
+ */
+__attribute__((weak)) off_t lseek(s32 fd, off_t offset, s32 whence)
+{
+  (void)fd;
+  (void)offset;
+  (void)whence;
+  errno = ESPIPE;
+  return ((off_t)-1);
+}
+
+__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence)
+{
+  (void)fd;
+  (void)offset;
+  (void)whence;
+  errno = ESPIPE;
+  return ((off_t)-1);
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/lseek.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/lseek.o
new file mode 100644
index 0000000000000000000000000000000000000000..99374185ebdb3dd9b68a0cdafad93dadd2cb4f26
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/lseek.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/open.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/open.c
new file mode 100644
index 0000000000000000000000000000000000000000..85e9ce4022c5e8dff64f391e7c2a3cadc6d4515e
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/open.c
@@ -0,0 +1,53 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#ifndef UNDEFINE_FILE_OPS
+#include <errno.h>
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode);
+}
+#endif
+/*
+ * open -- open a file descriptor. We don't have a filesystem, so
+ *         we return an error.
+ */
+__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode)
+{
+  (void)buf;
+  (void)flags;
+  (void)mode;
+  errno = EIO;
+  return (-1);
+}
+#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/open.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/open.o
new file mode 100644
index 0000000000000000000000000000000000000000..7f1c39c54526e918818dda229b7e933c00d360e2
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/open.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/outbyte.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/outbyte.c
new file mode 100644
index 0000000000000000000000000000000000000000..8b56036b7677518b290df22d590cdad568fbdad4
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/outbyte.c
@@ -0,0 +1,15 @@
+#include "xparameters.h"
+#include "xuartps_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+void outbyte(char c); 
+
+#ifdef __cplusplus
+}
+#endif 
+
+void outbyte(char c) {
+	 XUartPs_SendByte(STDOUT_BASEADDRESS, c);
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/outbyte.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/outbyte.o
new file mode 100644
index 0000000000000000000000000000000000000000..09d21b609edd6c3b1af0b8fbb8802ea23eab632f
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/outbyte.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/print.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/print.c
new file mode 100644
index 0000000000000000000000000000000000000000..74d70ee4a12b8fe8de39f6b3fb32482971906c46
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/print.c
@@ -0,0 +1,32 @@
+/* print.c -- print a string on the output device.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ *
+ */
+
+/*
+ * print -- do a raw print of a string
+ */
+#include "xil_printf.h"
+
+void print(const char8 *ptr)
+{
+#ifdef STDOUT_BASEADDRESS
+  while (*ptr != (char8)0) {
+    outbyte (*ptr);
+	ptr++;
+  }
+#else
+(void)ptr;
+#endif
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/print.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/print.o
new file mode 100644
index 0000000000000000000000000000000000000000..de7aa660a01e727760913b5a4f15381f63f7ed5d
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/print.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/Makefile b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..891fdf64304026ff2b06af604514161fe9f3b2b0
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/Makefile
@@ -0,0 +1,78 @@
+###############################################################################
+#
+# Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+###############################################################################
+#
+# Makefile for profiler
+#
+#######################################################################
+
+# PROFILE_ARCH_OBJS - Processor Architecture Dependent files defined here
+include ../config.make
+
+AS=mb-as
+COMPILER = mb-gcc
+ARCHIVER = mb-ar
+CP = cp
+COMPILER_FLAGS=-O2
+EXTRA_COMPILER_FLAGS=
+LIB = libxil.a
+DUMMYLIB = libxilprofile.a
+
+CC_FLAGS = $(subst -pg, , $(COMPILER_FLAGS))
+ECC_FLAGS = $(subst -pg, , $(EXTRA_COMPILER_FLAGS))
+
+RELEASEDIR = ../../../../lib
+INCLUDEDIR = ../../../../include
+INCLUDES = -I./. -I${INCLUDEDIR}
+
+OBJS = _profile_init.o _profile_clean.o _profile_timer_hw.o profile_hist.o profile_cg.o
+DUMMYOBJ = dummy.o
+INCLUDEFILES = profile.h mblaze_nt_types.h _profile_timer_hw.h
+
+libs : reallibs dummylibs
+
+reallibs : $(OBJS) $(PROFILE_ARCH_OBJS)
+	$(ARCHIVER) -r $(RELEASEDIR)/$(LIB) $(OBJS) $(PROFILE_ARCH_OBJS)
+
+dummylibs : $(DUMMYOBJ)
+	$(ARCHIVER) -r $(RELEASEDIR)/$(DUMMYLIB) $(DUMMYOBJ)
+
+%.o:%.c
+	$(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES)
+
+%.o:%.S
+	$(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES)
+
+include:
+	$(CP) -rf $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -f $(OBJS) $(PROFILE_ARCH_OBJS) $(LIB)
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/_profile_clean.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/_profile_clean.c
new file mode 100644
index 0000000000000000000000000000000000000000..1d8aada04d7e1eec3fd97fe7cbfc1d23772a39b2
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/_profile_clean.c
@@ -0,0 +1,47 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+#include "xil_exception.h"
+
+void _profile_clean( void );
+
+/*
+ * This function is the exit routine and is called by the crtinit, when the
+ * program terminates. The name needs to be changed later..
+ */
+void _profile_clean( void )
+{
+	Xil_ExceptionDisable();
+	disable_timer();
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/_profile_init.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/_profile_init.c
new file mode 100644
index 0000000000000000000000000000000000000000..0ac51b1750e1149011f0c50c6372ab707bbbbb9d
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/_profile_init.c
@@ -0,0 +1,90 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************
+*
+* _program_init.c:
+*	Initialize the Profiling Structures.
+*
+******************************************************************************/
+
+#include "profile.h"
+
+/* XMD Initializes the following Global Variables Value during Program
+ *  Download with appropriate values. */
+
+#ifdef PROC_MICROBLAZE
+
+extern s32 microblaze_init(void);
+
+#elif defined PROC_PPC
+
+extern s32 powerpc405_init(void);
+
+#else
+
+extern s32 cortexa9_init(void);
+
+#endif
+
+s32 profile_version = 1;	/* Version of S/W Intrusive Profiling library */
+
+u32 binsize = (u32)BINSIZE;    			/* Histogram Bin Size */
+u32 cpu_clk_freq = (u32)CPU_FREQ_HZ ;	/* CPU Clock Frequency */
+u32 sample_freq_hz = (u32)SAMPLE_FREQ_HZ ;	/* Histogram Sampling Frequency */
+u32 timer_clk_ticks = (u32)TIMER_CLK_TICKS ;/* Timer Clock Ticks for the Timer */
+
+/* Structure for Storing the Profiling Data */
+struct gmonparam *_gmonparam = (struct gmonparam *)(0xffffffffU);
+s32 n_gmon_sections = 1;
+
+/* This is the initialization code, which is called from the crtinit. */
+
+void _profile_init( void )
+{
+/* 	print("Gmon Init called....\r\n")  */
+/* 	putnum(n_gmon_sections) , print("\r\n")   */
+/* 	if( _gmonparam == 0xffffffff ) */
+/* 		printf("Gmonparam is NULL !!\r\n")  */
+/* 	for( i = 0, i < n_gmon_sections, i++ )[ */
+/* 		putnum( _gmonparam[i].lowpc) , print("\t")   */
+/* 		putnum( _gmonparam[i].highpc) , print("\r\n")  */
+/* 		putnum( _gmonparam[i].textsize ), print("\r\n")  */
+/* 		putnum( _gmonparam[i].kcountsize * sizeof(unsigned short)), print("\r\n")  */
+/* 	] */
+
+#ifdef PROC_MICROBLAZE
+	(void)microblaze_init();
+#elif defined PROC_PPC
+	powerpc405_init();
+#else
+	(void)cortexa9_init();
+#endif
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/_profile_timer_hw.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/_profile_timer_hw.c
new file mode 100644
index 0000000000000000000000000000000000000000..e85fb5c2d3cea521c419b5600530173448694702
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/_profile_timer_hw.c
@@ -0,0 +1,387 @@
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************
+*
+*  _program_timer_hw.c:
+*	Timer related functions
+*
+******************************************************************************/
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+
+#include "xil_exception.h"
+
+#ifdef PROC_PPC
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#endif
+
+#ifdef TIMER_CONNECT_INTC
+#include "xintc_l.h"
+#include "xintc.h"
+#endif	/* TIMER_CONNECT_INTC */
+
+/* #ifndef PPC_PIT_INTERRUPT */
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+#include "xtmrctr_l.h"
+#endif
+
+/* extern u32 timer_clk_ticks, */
+
+#ifdef PROC_PPC405
+#ifdef PPC_PIT_INTERRUPT
+s32 ppc_pit_init( void );
+#endif
+s32 powerpc405_init()
+#endif	/* PROC_CORTEXA9 */
+
+#ifdef PROC_PPC440
+#ifdef PPC_PIT_INTERRUPT
+s32 ppc_dec_init( void );
+#endif
+s32 powerpc405_init(void);
+#endif	/* PROC_PPC440 */
+
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+s32 opb_timer_init( void );
+#endif
+
+#ifdef PROC_MICROBLAZE
+s32 microblaze_init(void);
+#endif	/* PROC_MICROBLAZE */
+
+#ifdef PROC_CORTEXA9
+s32 scu_timer_init( void );
+s32 cortexa9_init(void);
+#endif	/* PROC_CORTEXA9 */
+
+
+/*--------------------------------------------------------------------
+  * PowerPC Target - Timer related functions
+  *-------------------------------------------------------------------- */
+#ifdef PROC_PPC405
+
+
+/*--------------------------------------------------------------------
+* PowerPC PIT Timer Init.
+*	Defined only if PIT Timer is used for Profiling
+*
+*-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+int ppc_pit_init( void )
+{
+	/* 1. Register Profile_intr_handler as Interrupt handler */
+	/* 2. Set PIT Timer Interrupt and Enable it. */
+	Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_PIT_INT,
+			    (Xil_ExceptionHandler)profile_intr_handler,NULL);
+	XTime_PITSetInterval( timer_clk_ticks ) ;
+	XTime_PITEnableAutoReload() ;
+	return 0;
+}
+#endif
+
+
+/* --------------------------------------------------------------------
+* PowerPC Timer Initialization functions.
+*	For PowerPC, PIT and opb_timer can be used for Profiling. This
+*	is selected by the user in standalone BSP
+*
+*-------------------------------------------------------------------- */
+s32 powerpc405_init()
+{
+	Xil_ExceptionInit() ;
+	Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
+
+	/* Initialize the Timer.
+	  * 1. If PowerPC PIT Timer has to be used, initialize PIT timer.
+	  * 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC */
+#ifdef PPC_PIT_INTERRUPT
+	ppc_pit_init();
+#else
+#ifdef TIMER_CONNECT_INTC
+	Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+			      (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
+	XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
+			     (XInterruptHandler)profile_intr_handler,NULL);
+#else
+	Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+			      (Xil_ExceptionHandler)profile_intr_handler,NULL);
+#endif
+	/* Initialize the timer with Timer Ticks */
+	opb_timer_init() ;
+#endif
+
+	/* Enable Interrupts in the System, if Profile Timer is the only Interrupt
+	  * in the System. */
+#ifdef ENABLE_SYS_INTR
+#ifdef PPC_PIT_INTERRUPT
+	XTime_PITEnableInterrupt() ;
+#elif TIMER_CONNECT_INTC
+	XIntc_MasterEnable( INTC_BASEADDR );
+	XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
+	XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
+#endif
+	Xil_ExceptionEnableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
+#endif
+	return 0;
+}
+
+#endif	/* PROC_PPC */
+
+
+
+/*--------------------------------------------------------------------
+  * PowerPC440 Target - Timer related functions
+  * -------------------------------------------------------------------- */
+#ifdef PROC_PPC440
+
+
+/*--------------------------------------------------------------------
+ * PowerPC DEC Timer Init.
+ *	Defined only if DEC Timer is used for Profiling
+ *
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+s32 ppc_dec_init( void )
+{
+	/* 1. Register Profile_intr_handler as Interrupt handler */
+	/* 2. Set DEC Timer Interrupt and Enable it. */
+	Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_DEC_INT,
+			    (Xil_ExceptionHandler)profile_intr_handler,NULL);
+	XTime_DECSetInterval( timer_clk_ticks ) ;
+	XTime_DECEnableAutoReload() ;
+	return 0;
+}
+#endif
+
+
+/*--------------------------------------------------------------------
+ * PowerPC Timer Initialization functions.
+ *	For PowerPC, DEC and opb_timer can be used for Profiling. This
+ *	is selected by the user in standalone BSP
+ *
+ *-------------------------------------------------------------------- */
+s32 powerpc405_init(void)
+{
+	Xil_ExceptionInit();
+	Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
+
+	/* Initialize the Timer.
+	 * 1. If PowerPC DEC Timer has to be used, initialize DEC timer.
+	 * 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC */
+#ifdef PPC_PIT_INTERRUPT
+	ppc_dec_init();
+#else
+#ifdef TIMER_CONNECT_INTC
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+				     (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
+
+	XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
+			     (XInterruptHandler)profile_intr_handler,NULL);
+#else
+	Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+			      (Xil_ExceptionHandler)profile_intr_handler,NULL);
+	Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+			      (Xil_ExceptionHandler)profile_intr_handler,NULL);
+#endif
+	/* Initialize the timer with Timer Ticks */
+	opb_timer_init() ;
+#endif
+
+	/* Enable Interrupts in the System, if Profile Timer is the only Interrupt
+	 * in the System. */
+#ifdef ENABLE_SYS_INTR
+#ifdef PPC_PIT_INTERRUPT
+	XTime_DECEnableInterrupt() ;
+#elif TIMER_CONNECT_INTC
+	XIntc_MasterEnable( INTC_BASEADDR );
+	XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
+	XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
+#endif
+	Xil_ExceptionEnableMask( XEXC_NON_CRITICAL ) ;
+#endif
+	return 0;
+}
+
+#endif	/* PROC_PPC440 */
+
+/* --------------------------------------------------------------------
+ * opb_timer Initialization for PowerPC and MicroBlaze. This function
+ * is not needed if DEC timer is used in PowerPC
+ *
+ *-------------------------------------------------------------------- */
+/* #ifndef PPC_PIT_INTERRUPT */
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+s32 opb_timer_init( void )
+{
+	/* set the number of cycles the timer counts before interrupting */
+	XTmrCtr_SetLoadReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)timer_clk_ticks);
+
+	/* reset the timers, and clear interrupts */
+	XTmrCtr_SetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0,
+				     (u32)XTC_CSR_INT_OCCURED_MASK | (u32)XTC_CSR_LOAD_MASK );
+
+	/* start the timers */
+	XTmrCtr_SetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)XTC_CSR_ENABLE_TMR_MASK
+			     | (u32)XTC_CSR_ENABLE_INT_MASK | (u32)XTC_CSR_AUTO_RELOAD_MASK | (u32)XTC_CSR_DOWN_COUNT_MASK);
+	return 0;
+}
+#endif
+
+
+/*--------------------------------------------------------------------
+ * MicroBlaze Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_MICROBLAZE
+
+/* --------------------------------------------------------------------
+ * Initialize the Profile Timer for MicroBlaze Target.
+ *	For MicroBlaze, opb_timer is used. The opb_timer can be directly
+ *	connected to MicroBlaze or connected through Interrupt Controller.
+ *
+ *-------------------------------------------------------------------- */
+s32 microblaze_init(void)
+{
+	/* Register profile_intr_handler
+	 * 1. If timer is connected to Interrupt Controller, register the handler
+	 *    to Interrupt Controllers vector table.
+	 * 2. If timer is directly connected to MicroBlaze, register the handler
+	 *    as Interrupt handler */
+	Xil_ExceptionInit();
+
+#ifdef TIMER_CONNECT_INTC
+	XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
+			     (XInterruptHandler)profile_intr_handler,NULL);
+#else
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+				     (Xil_ExceptionHandler)profile_intr_handler,
+				     NULL) ;
+#endif
+
+	/* Initialize the timer with Timer Ticks */
+	(void)opb_timer_init() ;
+
+	/* Enable Interrupts in the System, if Profile Timer is the only Interrupt
+	 * in the System. */
+#ifdef ENABLE_SYS_INTR
+#ifdef TIMER_CONNECT_INTC
+	XIntc_MasterEnable((u32)INTC_BASEADDR );
+	XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
+	XIntc_EnableIntr( (u32)INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+				     (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
+#endif
+
+#endif
+
+	Xil_ExceptionEnable();
+
+	return 0;
+
+}
+
+#endif	/* PROC_MICROBLAZE */
+
+
+
+/* --------------------------------------------------------------------
+ * Cortex A9 Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_CORTEXA9
+
+/* --------------------------------------------------------------------
+ * Initialize the Profile Timer for Cortex A9 Target.
+ *	The scu private timer is connected to the Scu GIC controller.
+ *
+ *-------------------------------------------------------------------- */
+s32 scu_timer_init( void )
+{
+	/* set the number of cycles the timer counts before interrupting
+	 * scu timer runs at half the cpu clock */
+	XScuTimer_SetLoadReg(PROFILE_TIMER_BASEADDR, timer_clk_ticks/2U);
+
+	/* clear any pending interrupts */
+	XScuTimer_SetIntrReg(PROFILE_TIMER_BASEADDR, 1U);
+
+	/* enable interrupts, auto-reload mode and start the timer */
+	XScuTimer_SetControlReg(PROFILE_TIMER_BASEADDR, XSCUTIMER_CONTROL_IRQ_ENABLE_MASK |
+				XSCUTIMER_CONTROL_AUTO_RELOAD_MASK | XSCUTIMER_CONTROL_ENABLE_MASK);
+
+	return 0;
+}
+
+s32 cortexa9_init(void)
+{
+
+	Xil_ExceptionInit();
+
+	XScuGic_DeviceInitialize(0);
+
+	/*
+	 * Connect the interrupt controller interrupt handler to the hardware
+	 * interrupt handling logic in the processor.
+	 */
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
+				(Xil_ExceptionHandler)XScuGic_DeviceInterruptHandler,
+				NULL);
+
+	/*
+	 * Connect the device driver handler that will be called when an
+	 * interrupt for the device occurs, the handler defined above performs
+	 * the specific interrupt processing for the device.
+	 */
+	XScuGic_RegisterHandler(SCUGIC_CPU_BASEADDR,
+				PROFILE_TIMER_INTR_ID,
+				(Xil_ExceptionHandler)profile_intr_handler,
+				NULL);
+
+	/*
+	 * Enable the interrupt for scu timer.
+	 */
+	XScuGic_EnableIntr(SCUGIC_DIST_BASEADDR, PROFILE_TIMER_INTR_ID);
+
+	/*
+	 * Enable interrupts in the Processor.
+	 */
+	Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
+
+	/*
+	 * Initialize the timer with Timer Ticks
+	 */
+	(void)scu_timer_init() ;
+
+	Xil_ExceptionEnable();
+
+	return 0;
+}
+
+#endif	/* PROC_CORTEXA9 */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/_profile_timer_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/_profile_timer_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..2cee66b09ec02849f667a2e6731e44e6ab6163e4
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/_profile_timer_hw.h
@@ -0,0 +1,312 @@
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************
+*
+* _program_timer_hw.h:
+*	Timer related functions
+*
+******************************************************************************/
+
+#ifndef PROFILE_TIMER_HW_H
+#define PROFILE_TIMER_HW_H
+
+#include "profile.h"
+
+#ifdef PROC_PPC
+#if defined __GNUC__
+#  define SYNCHRONIZE_IO __asm__ volatile ("eieio")
+#elif defined __DCC__
+#  define SYNCHRONIZE_IO __asm volatile(" eieio")
+#else
+#  define SYNCHRONIZE_IO
+#endif
+#endif
+
+#ifdef PROC_PPC
+#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; }
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
+#else
+#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); }
+#endif
+
+#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
+	ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] +	\
+			   (u32)(RegOffset)), (u32)(ValueToWrite))
+
+#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset)	\
+	ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset))
+
+#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
+	ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET,     \
+					   (RegisterValue))
+
+#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber)		\
+	ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef PROC_PPC
+#include "xexception_l.h"
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#endif
+
+#ifdef TIMER_CONNECT_INTC
+#include "xintc_l.h"
+#include "xintc.h"
+#endif	/* TIMER_CONNECT_INTC */
+
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+#include "xtmrctr_l.h"
+#endif
+
+#ifdef PROC_CORTEXA9
+#include "xscutimer_hw.h"
+#include "xscugic.h"
+#endif
+
+extern u32 timer_clk_ticks ;
+
+/*--------------------------------------------------------------------
+ * PowerPC Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_PPC
+
+#ifdef PPC_PIT_INTERRUPT
+u32 timer_lo_clk_ticks ;	/* Clk ticks when Timer is disabled in CG */
+#endif
+
+#ifdef PROC_PPC440
+#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
+#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
+#define XREG_SPR_PIT XREG_SPR_DEC
+#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
+#endif
+
+/* --------------------------------------------------------------------
+ * Disable the Timer - During Profiling
+ *
+ * For PIT Timer -
+ *	1. XTime_PITDisableInterrupt() ;
+ *	2. Store the remaining timer clk tick
+ *	3. Stop the PIT Timer
+ *-------------------------------------------------------------------- */
+
+#ifdef PPC_PIT_INTERRUPT
+#define disable_timer() 		\
+	{				\
+		u32 val;	\
+		val=mfspr(XREG_SPR_TCR);	\
+		mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE));	\
+		timer_lo_clk_ticks = mfspr(XREG_SPR_PIT);			\
+		mtspr(XREG_SPR_PIT, 0);	\
+	}
+#else
+#define disable_timer() 	\
+   { \
+      u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+      u32 tmp_v = ProfIo_In32(addr); \
+      tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \
+      ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+   }
+#endif
+
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer
+ *
+ * For PIT Timer -
+ *	1. Load the remaining timer clk ticks
+ *	2. XTime_PITEnableInterrupt() ;
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+#define enable_timer()				\
+	{					\
+		u32 val;		\
+		val=mfspr(XREG_SPR_TCR);	\
+		mtspr(XREG_SPR_PIT, timer_lo_clk_ticks);	\
+		mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
+	}
+#else
+#define enable_timer()						\
+	{							\
+      u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+      u32 tmp_v = ProfIo_In32(addr); \
+      tmp_v = tmp_v |  XTC_CSR_ENABLE_TMR_MASK; \
+      ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+	}
+#endif
+
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ * For PIT Timer -
+ * 	1. Load the timer clk ticks
+ *	2. Enable AutoReload and Interrupt
+ *	3. Clear PIT Timer Status bits
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+#define timer_ack()							\
+	{								\
+		u32 val;					\
+		mtspr(XREG_SPR_PIT, timer_clk_ticks);			\
+		mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS);	\
+		val=mfspr(XREG_SPR_TCR);				\
+		mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
+	}
+#else
+#define timer_ack()				\
+	{						\
+		u32 csr;			\
+		csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0);	\
+		ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr);	\
+	}
+#endif
+
+/*-------------------------------------------------------------------- */
+#endif	/* PROC_PPC */
+/* -------------------------------------------------------------------- */
+
+
+
+
+/* --------------------------------------------------------------------
+ * MicroBlaze Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_MICROBLAZE
+
+/* --------------------------------------------------------------------
+ * Disable the Timer during Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define disable_timer()					\
+	{						\
+      u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
+	  Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+	  Addr += (u32)XTC_TCSR_OFFSET; \
+      u32 tmp_v = ProfIo_In32(Addr); \
+      tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \
+      u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \
+      OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+      OutAddr += (u32)XTC_TCSR_OFFSET; \
+      ProfIo_Out32(OutAddr, (u32)tmp_v); \
+    }
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer after Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define enable_timer()					\
+	{						\
+      u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
+	  Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+	  Addr += (u32)XTC_TCSR_OFFSET; \
+      u32 tmp_v = (u32)ProfIo_In32(Addr); \
+      tmp_v = tmp_v |  (u32)XTC_CSR_ENABLE_TMR_MASK; \
+      ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \
+	}
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ *-------------------------------------------------------------------- */
+#define timer_ack()				\
+	{						\
+		u32 csr;			\
+		csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0);	\
+		ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr);	\
+	}
+
+/*-------------------------------------------------------------------- */
+#endif	/* PROC_MICROBLAZE */
+/*-------------------------------------------------------------------- */
+
+/* --------------------------------------------------------------------
+ * Cortex A9 Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_CORTEXA9
+
+/* --------------------------------------------------------------------
+ * Disable the Timer during Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define disable_timer()							\
+{								\
+	u32 Reg;							\
+	Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+	Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\
+	Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer after Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define enable_timer()							\
+{								\
+	u32 Reg;							\
+	Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+	Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
+	Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ *-------------------------------------------------------------------- */
+#define timer_ack()						\
+{							\
+	Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \
+		(u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\
+}
+
+/*-------------------------------------------------------------------- */
+#endif	/* PROC_CORTEXA9 */
+/*-------------------------------------------------------------------- */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/dummy.S b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/dummy.S
new file mode 100644
index 0000000000000000000000000000000000000000..d28646d6dd63c9171888d94fadfd2d219d6b8c48
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/dummy.S
@@ -0,0 +1,64 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+	.globl dummy_f
+
+#ifdef PROC_MICROBLAZE
+	.text
+	.align 2
+	.ent dummy_f
+
+dummy_f:
+	nop
+
+	.end dummy_f
+#endif
+
+#ifdef PROC_PPC
+	.section .text
+	.align 2
+	.type dummy_f@function
+
+dummy_f:
+	b dummy_f
+
+#endif
+
+#ifdef PROC_CORTEXA9
+	.section .text
+	.align 2
+	.type dummy_f, %function
+
+dummy_f:
+	b dummy_f
+
+#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/mblaze_nt_types.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/mblaze_nt_types.h
new file mode 100644
index 0000000000000000000000000000000000000000..7096a92d804e8cbd2a660b78a32d5ea3a7256862
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/mblaze_nt_types.h
@@ -0,0 +1,54 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+
+#ifndef _MBLAZE_NT_TYPES_H
+#define _MBLAZE_NT_TYPES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef char            byte;
+typedef short           half;
+typedef int             word;
+typedef unsigned char   ubyte;
+typedef unsigned short  uhalf;
+typedef unsigned int    uword;
+typedef ubyte           boolean;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile.h
new file mode 100644
index 0000000000000000000000000000000000000000..4cb07a7d3e230e647f9e6c5dbcb1447be4bfed5a
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile.h
@@ -0,0 +1,131 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#ifndef	PROFILE_H
+#define	PROFILE_H	1
+
+#include <stdio.h>
+#include "xil_types.h"
+#include "profile_config.h"
+
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void _system_init( void ) ;
+void _system_clean( void ) ;
+void mcount(u32 frompc, u32 selfpc);
+void profile_intr_handler( void ) ;
+void _profile_init( void );
+
+
+
+/****************************************************************************
+ * Profiling on hardware - Hash table maintained on hardware and data sent
+ * to xmd for gmon.out generation.
+ ****************************************************************************/
+/*
+ * histogram counters are unsigned shorts (according to the kernel).
+ */
+#define	HISTCOUNTER	u16
+
+struct tostruct {
+	u32  selfpc;
+	s32	 count;
+	s16  link;
+	u16	 pad;
+};
+
+struct fromstruct {
+	u32 frompc ;
+	s16 link ;
+	u16 pad ;
+} ;
+
+/*
+ * general rounding functions.
+ */
+#define ROUNDDOWN(x,y)	(((x)/(y))*(y))
+#define ROUNDUP(x,y)	((((x)+(y)-1)/(y))*(y))
+
+/*
+ * The profiling data structures are housed in this structure.
+ */
+struct gmonparam {
+	s32		state;
+
+	/* Histogram Information */
+	u16		*kcount;	/* No. of bins in histogram */
+	u32		kcountsize;	/* Histogram samples */
+
+	/* Call-graph Information */
+	struct fromstruct	*froms;
+	u32		fromssize;
+	struct tostruct		*tos;
+	u32		tossize;
+
+	/* Initialization I/Ps */
+	u32    	lowpc;
+	u32		highpc;
+	u32		textsize;
+	/* u32 		cg_froms, */
+	/* u32 		cg_tos, */
+};
+extern struct gmonparam *_gmonparam;
+extern s32 n_gmon_sections;
+
+/*
+ * Possible states of profiling.
+ */
+#define	GMON_PROF_ON	0
+#define	GMON_PROF_BUSY	1
+#define	GMON_PROF_ERROR	2
+#define	GMON_PROF_OFF	3
+
+/*
+ * Sysctl definitions for extracting profiling information from the kernel.
+ */
+#define	GPROF_STATE	0	/* int: profiling enabling variable */
+#define	GPROF_COUNT	1	/* struct: profile tick count buffer */
+#define	GPROF_FROMS	2	/* struct: from location hash bucket */
+#define	GPROF_TOS	3	/* struct: destination/count structure */
+#define	GPROF_GMONPARAM	4	/* struct: profiling parameters (see above) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 		/* PROFILE_H */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_cg.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_cg.c
new file mode 100644
index 0000000000000000000000000000000000000000..2539ce61aa9c4aac388d3cbf0c6dea0621752add
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_cg.c
@@ -0,0 +1,171 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+/*
+ * The mcount fucntion is excluded from the library, if the user defines
+ * PROFILE_NO_GRAPH.
+ */
+#ifndef PROFILE_NO_GRAPH
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#ifdef PROFILE_NO_FUNCPTR
+s32 searchpc(const struct fromto_struct *cgtable, s32 cgtable_size, u32 frompc );
+#else
+s32 searchpc(const struct fromstruct *froms, s32 fromssize, u32 frompc );
+#endif
+
+/*extern struct gmonparam *_gmonparam, */
+
+#ifdef PROFILE_NO_FUNCPTR
+s32 searchpc(const struct fromto_struct *cgtable, s32 cgtable_size, u32 frompc )
+{
+	s32 index = 0 ;
+
+	while( (index < cgtable_size) && (cgtable[index].frompc != frompc) ){
+		index++ ;
+	}
+	if( index == cgtable_size ) {
+		return -1 ;
+	} else {
+		return index ;
+	}
+}
+#else
+s32 searchpc(const struct fromstruct *froms, s32 fromssize, u32 frompc )
+{
+	s32 index = 0 ;
+	s32 Status;
+
+	while( (index < fromssize) && (froms[index].frompc != frompc) ){
+		index++ ;
+	}
+	if( index == fromssize ) {
+		Status = -1 ;
+	} else {
+		Status = index ;
+	}
+	return Status;
+}
+#endif		/* PROFILE_NO_FUNCPTR */
+
+
+void mcount( u32 frompc, u32 selfpc )
+{
+	register struct gmonparam *p = NULL;
+	register s32 toindex, fromindex;
+	s32 j;
+
+	disable_timer();
+
+	/*print("CG: "), putnum(frompc), print("->"), putnum(selfpc), print("\r\n") ,
+	 * check that frompcindex is a reasonable pc value.
+	 * for example:	signal catchers get called from the stack,
+	 *		not from text space.  too bad.
+	*/
+	for(j = 0; j < n_gmon_sections; j++ ){
+		if((frompc >= _gmonparam[j].lowpc) && (frompc < _gmonparam[j].highpc)) {
+			p = &_gmonparam[j];
+			break;
+		}
+	}
+	if( j == n_gmon_sections ) {
+		goto done;
+	}
+
+#ifdef PROFILE_NO_FUNCPTR
+	fromindex = searchpc( p->cgtable, p->cgtable_size, frompc ) ;
+	if( fromindex == -1 ) {
+		fromindex = p->cgtable_size ;
+		p->cgtable_size++ ;
+		p->cgtable[fromindex].frompc = frompc ;
+		p->cgtable[fromindex].selfpc = selfpc ;
+		p->cgtable[fromindex].count = 1 ;
+		goto done ;
+	}
+	p->cgtable[fromindex].count++ ;
+#else
+	fromindex = (s32)searchpc( p->froms, ((s32)p->fromssize), frompc ) ;
+	if( fromindex == -1 ) {
+		fromindex = (s32)p->fromssize ;
+		p->fromssize++ ;
+		/*if( fromindex >= N_FROMS ) {
+		* print("Error : From PC table overflow\r\n")
+		* goto overflow
+		*}*/
+		p->froms[fromindex].frompc = frompc ;
+		p->froms[fromindex].link = -1 ;
+	}else {
+		toindex = ((s32)(p->froms[fromindex].link));
+		while(toindex != -1) {
+			toindex = (((s32)p->tossize) - toindex)-1 ;
+			if( p->tos[toindex].selfpc == selfpc ) {
+				p->tos[toindex].count++ ;
+				goto done ;
+			}
+			toindex = ((s32)(p->tos[toindex].link)) ;
+		}
+	}
+
+	/*if( toindex == -1 ) { */
+	p->tos-- ;
+	p->tossize++ ;
+	/* if( toindex >= N_TOS ) {
+	* print("Error : To PC table overflow\r\n")
+	* goto overflow
+	*} */
+	p->tos[0].selfpc = selfpc ;
+	p->tos[0].count = 1 ;
+	p->tos[0].link = p->froms[fromindex].link ;
+	p->froms[fromindex].link = ((s32)(p->tossize))-((s32)1);
+#endif
+
+ done:
+	p->state = GMON_PROF_ON;
+	goto enable_timer_label ;
+ /* overflow: */
+	/*p->state = GMON_PROF_ERROR */
+ enable_timer_label:
+	enable_timer();
+	return ;
+}
+
+
+#endif		/* PROFILE_NO_GRAPH */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_config.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_config.h
new file mode 100644
index 0000000000000000000000000000000000000000..550c60b449b990de20009d14b095b2331274547e
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_config.h
@@ -0,0 +1,48 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+
+#ifndef _PROFILE_CONFIG_H
+#define _PROFILE_CONFIG_H
+
+#define BINSIZE 4U
+#define SAMPLE_FREQ_HZ 100000U
+#define TIMER_CLK_TICKS 1000U
+
+#define PROFILE_NO_FUNCPTR_FLAG 0
+
+#define PROFILE_TIMER_BASEADDR 0x00608000U
+#define PROFILE_TIMER_INTR_ID 0U
+
+#define TIMER_CONNECT_INTC
+
+#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_hist.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_hist.c
new file mode 100644
index 0000000000000000000000000000000000000000..c8ee9cef91928d58505b1bc1d22b54bedd2694f3
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_hist.c
@@ -0,0 +1,71 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+#ifdef PROC_PPC
+#include "xpseudo_asm.h"
+#define SPR_SRR0 0x01A
+#endif
+
+#include "xil_types.h"
+
+extern u32 binsize ;
+u32 prof_pc ;
+
+void profile_intr_handler( void )
+{
+
+	s32 j;
+
+#ifdef PROC_MICROBLAZE
+	asm( "swi r14, r0, prof_pc" ) ;
+#elif defined PROC_PPC
+	prof_pc = mfspr(SPR_SRR0);
+#else
+	/* for cortexa9, lr is saved in asm interrupt handler */
+#endif
+	/* print("PC: "), putnum(prof_pc), print("\r\n"), */
+	for(j = 0; j < n_gmon_sections; j++ ){
+		if((prof_pc >= ((u32)_gmonparam[j].lowpc)) && (prof_pc < ((u32)_gmonparam[j].highpc))) {
+			_gmonparam[j].kcount[(prof_pc-_gmonparam[j].lowpc)/((u32)4 * binsize)]++;
+			break;
+		}
+	}
+	/* Ack the Timer Interrupt */
+	timer_ack();
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_mcount_arm.S b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_mcount_arm.S
new file mode 100644
index 0000000000000000000000000000000000000000..e62cec0bd54f5d28e04b8950f563745565f3be93
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_mcount_arm.S
@@ -0,0 +1,45 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+// based on "ARM Profiling Implementation" from Sourcery G++ Lite for ARM EABI
+
+.globl __gnu_mcount_nc
+.type __gnu_mcount_nc, %function
+
+__gnu_mcount_nc:
+	push	{r0, r1, r2, r3, lr}
+	subs	r1, lr, #0			/* callee - current lr */
+	ldr	r0, [sp, #20]			/* caller - at the top of the stack */
+	bl	mcount				/* when __gnu_mcount_nc is called */
+	pop	{r0, r1, r2, r3, ip, lr}
+	bx	ip
+
+	.end __gnu_mcount_nc
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_mcount_mb.S b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_mcount_mb.S
new file mode 100644
index 0000000000000000000000000000000000000000..bea2726b66d847c6b19cc262a9f83177062a74d0
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_mcount_mb.S
@@ -0,0 +1,69 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+	.globl _mcount
+	.text
+	.align 2
+	.ent _mcount
+
+	#ifndef PROFILE_NO_GRAPH
+
+_mcount:
+	addi r1, r1, -48
+	swi r11, r1, 44
+	swi r12, r1, 40
+	swi r5, r1, 36
+	swi r6, r1, 32
+	swi r7, r1, 28
+	swi r8, r1, 24
+	swi r9, r1, 20
+	swi r10, r1, 16
+	swi r15, r1, 12
+	add r5, r0, r15
+	brlid r15, mcount
+	add r6, r0, r16
+
+	lwi r11, r1, 44
+	lwi r12, r1, 40
+	lwi r5, r1, 36
+	lwi r6, r1, 32
+	lwi r7, r1, 28
+	lwi r8, r1, 24
+	lwi r9, r1, 20
+	lwi r10, r1, 16
+	lwi r15, r1, 12
+	rtsd r15, 4
+	addi r1, r1, 48
+
+	#endif	/* PROFILE_NO_GRAPH */
+
+	.end _mcount
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_mcount_ppc.S b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_mcount_ppc.S
new file mode 100644
index 0000000000000000000000000000000000000000..39bb92f774a18c45dcbfe972b2bd6bde0f9305ac
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/profile/profile_mcount_ppc.S
@@ -0,0 +1,71 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+	.globl _mcount
+
+	#define _MCOUNT_STACK_FRAME 48
+	.section .text
+	.align 2
+	.type _mcount@function
+
+
+_mcount:
+	stwu 1,	-_MCOUNT_STACK_FRAME(1)
+	stw 3, 8(1)
+	stw 4, 12(1)
+	stw 5, 16(1)
+	stw 6, 20(1)
+	stw 7, 24(1)
+	stw 8, 28(1)
+	stw 9, 32(1)
+	stw 10, 36(1)
+	stw 11, 40(1)
+	stw 12, 44(1)
+	mflr 4
+	stw 4, (_MCOUNT_STACK_FRAME+4)(1)
+	lwz 3, (_MCOUNT_STACK_FRAME)(1)
+	lwz 3, 4(3)
+	bl mcount
+	lwz 4, (_MCOUNT_STACK_FRAME+4)(1)
+	mtlr 4
+	lwz 12, 44(1)
+	lwz 11, 40(1)
+	lwz 10, 36(1)
+	lwz 9, 32(1)
+	lwz 8, 28(1)
+	lwz 7, 24(1)
+	lwz 6, 20(1)
+	lwz 5, 16(1)
+	lwz 4, 12(1)
+	lwz 3, 8(1)
+	addi 1,1, _MCOUNT_STACK_FRAME
+	blr
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/putnum.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/putnum.c
new file mode 100644
index 0000000000000000000000000000000000000000..aaf9edee7e1d66620949e3d97c75e989eaced499
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/putnum.c
@@ -0,0 +1,59 @@
+/* putnum.c -- put a hex number on the output device.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+ * putnum -- print a 32 bit number in hex
+ */
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Function Prototypes ******************************/
+extern void print (const char8 *ptr);
+void putnum(u32 num);
+
+void putnum(u32 num)
+{
+  char8  buf[9];
+  s32  cnt;
+  s32 i;
+  char8  *ptr;
+  u32  digit;
+  for(i = 0; i<9; i++) {
+	buf[i] = '0';
+  }
+
+  ptr = buf;
+  for (cnt = 7 ; cnt >= 0 ; cnt--) {
+    digit = (num >> (cnt * 4U)) & 0x0000000fU;
+
+    if ((digit <= 9U) && (ptr != NULL)) {
+		digit += (u32)'0';
+		*ptr = ((char8) digit);
+		ptr += 1;
+	} else if (ptr != NULL) {
+		digit += ((u32)'a' - (u32)10);
+		*ptr = ((char8)digit);
+		ptr += 1;
+	} else {
+		/*Made for MisraC Compliance*/;
+	}
+  }
+
+  if(ptr != NULL) {
+	  *ptr = (char8) 0;
+  }
+  print (buf);
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/putnum.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/putnum.o
new file mode 100644
index 0000000000000000000000000000000000000000..874410b13688f36ae812d5a9fdaa0597c30c9981
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/putnum.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/read.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/read.c
new file mode 100644
index 0000000000000000000000000000000000000000..7f7b7d26152c6f8eab88ea49ec886e949580d9e6
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/read.c
@@ -0,0 +1,104 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/* read.c -- read bytes from a input device.
+ */
+#ifndef UNDEFINE_FILE_OPS
+#include "xil_printf.h"
+#include "xparameters.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _read (s32 fd, char8* buf, s32 nbytes);
+}
+#endif
+
+/*
+ * read  -- read bytes from the serial port. Ignore fd, since
+ *          we only have stdin.
+ */
+__attribute__((weak)) s32
+read (s32 fd, char8* buf, s32 nbytes)
+{
+#ifdef STDIN_BASEADDRESS
+  s32 i;
+  s32 numbytes = 0;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  if(LocalBuf != NULL) {
+	for (i = 0; i < nbytes; i++) {
+		numbytes++;
+		*(LocalBuf + i) = inbyte();
+		if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
+			break;
+		}
+	}
+  }
+
+  return numbytes;
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
+
+__attribute__((weak)) s32
+_read (s32 fd, char8* buf, s32 nbytes)
+{
+#ifdef STDIN_BASEADDRESS
+  s32 i;
+  s32 numbytes = 0;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  if(LocalBuf != NULL) {
+	for (i = 0; i < nbytes; i++) {
+		numbytes++;
+		*(LocalBuf + i) = inbyte();
+		if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
+			break;
+		}
+	}
+  }
+
+  return numbytes;
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
+#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/read.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/read.o
new file mode 100644
index 0000000000000000000000000000000000000000..820720112b48dab751448b0fd733e97bb8a01580
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/read.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/sbrk.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/sbrk.c
new file mode 100644
index 0000000000000000000000000000000000000000..64d5156afdf83b66825e3af85fec8563a84d9ec8
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/sbrk.c
@@ -0,0 +1,65 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include <errno.h>
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) char8 *sbrk (s32 nbytes);
+}
+#endif
+
+extern u8 _heap_start[];
+extern u8 _heap_end[];
+extern char8 HeapBase[];
+extern char8 HeapLimit[];
+
+
+
+__attribute__((weak)) char8 *sbrk (s32 nbytes)
+{
+  char8 *base;
+  static char8 *heap_ptr = HeapBase;
+
+  base = heap_ptr;
+  if(heap_ptr != NULL) {
+	heap_ptr += nbytes;
+  }
+
+/*  if (heap_ptr <= ((char8 *)&_heap_end + 1)) */
+  if (heap_ptr <= ((char8 *)&HeapLimit + 1)) {
+    return base;
+  }	else {
+    errno = ENOMEM;
+    return ((char8 *)-1);
+  }
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/sbrk.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/sbrk.o
new file mode 100644
index 0000000000000000000000000000000000000000..cea5deb98d5155b08a99c6edd390d9d43434be4f
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/sbrk.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/sleep.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/sleep.c
new file mode 100644
index 0000000000000000000000000000000000000000..039fa61bda08591a4fe3d09799b8f775abf51d2b
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/sleep.c
@@ -0,0 +1,80 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************
+*
+* @file sleep.c
+*
+* This function provides a second delay using the Global Timer register in
+* the ARM Cortex A9 MP core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  11/11/09 First release
+* 3.07a sgd      07/05/12 Updated sleep function to make use Global
+* 6.0   asa      08/15/16 Updated the sleep signature. Fix for CR#956899.
+* </pre>
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "sleep.h"
+#include "xtime_l.h"
+#include "xparameters.h"
+
+/*****************************************************************************/
+/*
+*
+* This API is used to provide delays in seconds
+*
+* @param	seconds requested
+*
+* @return	0 always
+*
+* @note		None.
+*
+****************************************************************************/
+unsigned sleep(unsigned int seconds)
+{
+  XTime tEnd, tCur;
+
+  XTime_GetTime(&tCur);
+  tEnd  = tCur + (((XTime) seconds) * COUNTS_PER_SECOND);
+  do
+  {
+    XTime_GetTime(&tCur);
+  } while (tCur < tEnd);
+
+  return 0;
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/sleep.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/sleep.h
new file mode 100644
index 0000000000000000000000000000000000000000..27add66057b8dcbf8e137ed34844d58969fcb12f
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/sleep.h
@@ -0,0 +1,50 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#ifndef SLEEP_H
+#define SLEEP_H
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int usleep(unsigned long useconds);
+unsigned sleep(unsigned int seconds);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/sleep.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/sleep.o
new file mode 100644
index 0000000000000000000000000000000000000000..27416d0dc02658ec5b57fecf10a20586a9d485ed
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/sleep.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/smc.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/smc.h
new file mode 100644
index 0000000000000000000000000000000000000000..5a4d33608256f53d59b1c6470b9627803ea20b55
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/smc.h
@@ -0,0 +1,114 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file smc.h
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  11/03/09 Initial release.
+* 4.2	pkp	 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
+*					  as smc.c is removed
+* </pre>
+*
+* @note		None.
+*
+******************************************************************************/
+
+#ifndef SMC_H /* prevent circular inclusions */
+#define SMC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xil_io.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Memory controller configuration register offset */
+#define XSMCPSS_MC_STATUS		0x000U	/* Controller status reg, RO */
+#define XSMCPSS_MC_INTERFACE_CONFIG	0x004U	/* Interface config reg, RO */
+#define XSMCPSS_MC_SET_CONFIG		0x008U	/* Set configuration reg, WO */
+#define XSMCPSS_MC_CLR_CONFIG		0x00CU	/* Clear config reg, WO */
+#define XSMCPSS_MC_DIRECT_CMD		0x010U	/* Direct command reg, WO */
+#define XSMCPSS_MC_SET_CYCLES		0x014U	/* Set cycles register, WO */
+#define XSMCPSS_MC_SET_OPMODE		0x018U	/* Set opmode register, WO */
+#define XSMCPSS_MC_REFRESH_PERIOD_0	0x020U	/* Refresh period_0 reg, RW */
+#define XSMCPSS_MC_REFRESH_PERIOD_1	0x024U	/* Refresh period_1 reg, RW */
+
+/* Chip select configuration register offset */
+#define XSMCPSS_CS_IF0_CHIP_0_OFFSET	0x100U	/* Interface 0 chip 0 config */
+#define XSMCPSS_CS_IF0_CHIP_1_OFFSET	0x120U	/* Interface 0 chip 1 config */
+#define XSMCPSS_CS_IF0_CHIP_2_OFFSET	0x140U	/* Interface 0 chip 2 config */
+#define XSMCPSS_CS_IF0_CHIP_3_OFFSET	0x160U	/* Interface 0 chip 3 config */
+#define XSMCPSS_CS_IF1_CHIP_0_OFFSET	0x180U	/* Interface 1 chip 0 config */
+#define XSMCPSS_CS_IF1_CHIP_1_OFFSET	0x1A0U	/* Interface 1 chip 1 config */
+#define XSMCPSS_CS_IF1_CHIP_2_OFFSET	0x1C0U	/* Interface 1 chip 2 config */
+#define XSMCPSS_CS_IF1_CHIP_3_OFFSET	0x1E0U	/* Interface 1 chip 3 config */
+
+/* User configuration register offset */
+#define XSMCPSS_UC_STATUS_OFFSET	0x200U	/* User status reg, RO */
+#define XSMCPSS_UC_CONFIG_OFFSET	0x204U	/* User config reg, WO */
+
+/* Integration test register offset */
+#define XSMCPSS_IT_OFFSET		0xE00U
+
+/* ID configuration register offset */
+#define XSMCPSS_ID_PERIP_0_OFFSET	0xFE0U
+#define XSMCPSS_ID_PERIP_1_OFFSET	0xFE4U
+#define XSMCPSS_ID_PERIP_2_OFFSET	0xFE8U
+#define XSMCPSS_ID_PERIP_3_OFFSET	0xFECU
+#define XSMCPSS_ID_PCELL_0_OFFSET	0xFF0U
+#define XSMCPSS_ID_PCELL_1_OFFSET	0xFF4U
+#define XSMCPSS_ID_PCELL_2_OFFSET	0xFF8U
+#define XSMCPSS_ID_PCELL_3_OFFSET	0xFFCU
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* SMC_H */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/translation_table.S b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/translation_table.S
new file mode 100644
index 0000000000000000000000000000000000000000..ade44de2bfadf6adb25ba416aafb4a05a261d552
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/translation_table.S
@@ -0,0 +1,223 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file translation_table.s
+*
+* @addtogroup a9_boot_code
+* @{
+* <h2> translation_table.S </h2>
+* translation_table.S contains a static page table required by MMU for
+* cortex-A9. This translation table is flat mapped (input address = output
+* address) with default memory attributes defined for zynq architecture. It
+* utilizes short descriptor translation table format with each section defining
+* 1MB of memory.
+*
+* The overview of translation table memory attributes is described below.
+*
+*|                       | Memory Range            | Definition in Translation Table   |
+*|-----------------------|-------------------------|-----------------------------------|
+*| DDR                   | 0x00000000 - 0x3FFFFFFF | Normal write-back Cacheable       |
+*| PL                    | 0x40000000 - 0xBFFFFFFF | Strongly Ordered                  |
+*| Reserved              | 0xC0000000 - 0xDFFFFFFF | Unassigned                        |
+*| Memory mapped devices | 0xE0000000 - 0xE02FFFFF | Device Memory                     |
+*| Reserved              | 0xE0300000 - 0xE0FFFFFF | Unassigned                        |
+*| NAND, NOR             | 0xE1000000 - 0xE3FFFFFF | Device memory                     |
+*| SRAM                  | 0xE4000000 - 0xE5FFFFFF | Normal write-back Cacheable       |
+*| Reserved              | 0xE6000000 - 0xF7FFFFFF | Unassigned                        |
+*| AMBA APB Peripherals  | 0xF8000000 - 0xF8FFFFFF | Device Memory                     |
+*| Reserved              | 0xF9000000 - 0xFBFFFFFF | Unassigned                        |
+*| Linear QSPI - XIP     | 0xFC000000 - 0xFDFFFFFF | Normal write-through cacheable    |
+*| Reserved              | 0xFE000000 - 0xFFEFFFFF | Unassigned                        |
+*| OCM                   | 0xFFF00000 - 0xFFFFFFFF | Normal inner write-back cacheable |
+*
+* @note
+*
+* For region 0x00000000 - 0x3FFFFFFF, a system where DDR is less than 1GB,
+* region after DDR and before PL is marked as undefined/reserved in translation
+* table. In 0xF8000000 - 0xF8FFFFFF, 0xF8000C00 - 0xF8000FFF, 0xF8010000 -
+* 0xF88FFFFF and 0xF8F03000 to 0xF8FFFFFF are reserved  but due to granual size
+* of 1MB, it is not possible to define separate regions for them. For region
+* 0xFFF00000 - 0xFFFFFFFF, 0xFFF00000 to 0xFFFB0000 is reserved but due to 1MB
+* granual size, it is not possible to define separate region for it
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/09 Initial version
+* 3.04a sdm  01/13/12 Updated MMU table to mark DDR memory as Shareable
+* 3.07a sgd  07/05/2012 Configuring device address spaces as shareable device
+*		       instead of strongly-ordered.
+* 3.07a asa  07/17/2012 Changed the property of the ".mmu_tbl" section.
+* 4.2	pkp  09/02/2014 added entries for 0xfe000000 to 0xffefffff as reserved
+*			and  0xe0000000 - 0xe1ffffff is broken down into
+*			0xe0000000 - 0xe02fffff (memory mapped devides)
+*			0xe0300000 - 0xe0ffffff (reserved) and
+*			0xe1000000 - 0xe1ffffff (NAND)
+* 5.2	pkp  06/08/2015 put a check for XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm
+*			if DDR is present or not and accordingly generate the
+*			translation table
+* 6.1	pkp  07/11/2016 Corrected comments for memory attributes
+* </pre>
+*
+*
+******************************************************************************/
+#include "xparameters.h"
+	.globl  MMUTable
+
+	.section .mmu_tbl,"a"
+
+MMUTable:
+	/* Each table entry occupies one 32-bit word and there are
+	 * 4096 entries, so the entire table takes up 16KB.
+	 * Each entry covers a 1MB section.
+	 */
+.set SECT, 0
+
+#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR
+.set DDR_START, XPAR_PS7_DDR_0_S_AXI_BASEADDR
+.set DDR_END, XPAR_PS7_DDR_0_S_AXI_HIGHADDR
+.set DDR_SIZE, (DDR_END - DDR_START)+1
+.set DDR_REG, DDR_SIZE/0x100000
+#else
+.set DDR_REG, 0
+#endif
+
+.set UNDEF_REG, 0x3FF - DDR_REG
+
+				/*0x00000000 - 0x00100000 (cacheable )*/
+.word	SECT + 0x15de6		/* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
+.set	SECT, SECT+0x100000
+
+.rept	DDR_REG			/*  (DDR Cacheable) */
+.word	SECT + 0x15de6		/* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	UNDEF_REG			/*  (unassigned/reserved).
+				 * Generates a translation fault if accessed */
+.word	SECT + 0x0		/* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
+.set	SECT, SECT+0x100000
+.endr
+
+
+.rept	0x0400			/* 0x40000000 - 0x7fffffff (FPGA slave0) */
+.word	SECT + 0xc02		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x0400			/* 0x80000000 - 0xbfffffff (FPGA slave1) */
+.word	SECT + 0xc02		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x0200			/* 0xc0000000 - 0xdfffffff (unassigned/reserved).
+				 * Generates a translation fault if accessed */
+.word	SECT + 0x0		/* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x003			/* 0xe0000000 - 0xe02fffff (Memory mapped devices)
+				 * UART/USB/IIC/SPI/CAN/GEM/GPIO/QSPI/SD/NAND */
+.word	SECT + 0xc06		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x0D			/* 0xe0300000 - 0xe0ffffff (unassigned/reserved).
+				 * Generates a translation fault if accessed */
+.word	SECT + 0x0		/* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x0010			/* 0xe1000000 - 0xe1ffffff (NAND) */
+.word	SECT + 0xc06		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x0020			/* 0xe2000000 - 0xe3ffffff (NOR) */
+.word	SECT + 0xc06		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x0020			/* 0xe4000000 - 0xe5ffffff (SRAM) */
+.word	SECT + 0xc0e		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x0120			/* 0xe6000000 - 0xf7ffffff (unassigned/reserved).
+				 * Generates a translation fault if accessed */
+.word	SECT + 0x0		/* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
+.set	SECT, SECT+0x100000
+.endr
+
+/* 0xf8000c00 to 0xf8000fff, 0xf8010000 to 0xf88fffff and
+   0xf8f03000 to 0xf8ffffff are reserved  but due to granual size of
+   1MB, it is not possible to define separate regions for them */
+
+.rept	0x0010			/* 0xf8000000 - 0xf8ffffff (AMBA APB Peripherals) */
+
+.word	SECT + 0xc06		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x0030			/* 0xf9000000 - 0xfbffffff (unassigned/reserved).
+				 * Generates a translation fault if accessed */
+.word	SECT + 0x0		/* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x0020			/* 0xfc000000 - 0xfdffffff (Linear QSPI - XIP) */
+.word	SECT + 0xc0a		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b0 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x001F			/* 0xfe000000 - 0xffefffff (unassigned/reserved).
+				 * Generates a translation fault if accessed */
+.word	SECT + 0x0		/* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
+.set	SECT, SECT+0x100000
+.endr
+
+/* 0xfff00000 to 0xfffb0000 is reserved but due to granual size of
+   1MB, it is not possible to define separate region for  it
+
+ 0xfff00000 - 0xffffffff
+   256K OCM when mapped to high address space
+   inner-cacheable */
+.word	SECT + 0x4c0e		/* S=b0 TEX=b100 AP=b11, Domain=b0, C=b1, B=b1 */
+.set	SECT, SECT+0x100000
+
+.end
+/**
+* @} End of "addtogroup a9_boot_code".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/translation_table.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/translation_table.o
new file mode 100644
index 0000000000000000000000000000000000000000..8b62f8ef2c45b03ea2cc328cd71b3a2790b43bfc
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diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/unlink.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/unlink.c
new file mode 100644
index 0000000000000000000000000000000000000000..d0cc6807ba9061e8a1fa85e632587d23880980fe
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/unlink.c
@@ -0,0 +1,50 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include <errno.h>
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) sint32 unlink(char8 *path);
+}
+#endif
+/*
+ * unlink -- since we have no file system,
+ *           we just return an error.
+ */
+__attribute__((weak)) sint32 unlink(char8 *path)
+{
+  (void) path;
+  errno = EIO;
+  return (-1);
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/unlink.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/unlink.o
new file mode 100644
index 0000000000000000000000000000000000000000..c8687b4328cf925ba6e9e2eea7c1823cdab5797a
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diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/usleep.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/usleep.c
new file mode 100644
index 0000000000000000000000000000000000000000..9171d43822137cd044e37b8a0b358e77cefef48c
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/usleep.c
@@ -0,0 +1,91 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file usleep.c
+*
+* This function provides a microsecond delay using the Global Timer register in
+* the ARM Cortex A9 MP core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  11/11/09 First release
+* 3.07a sgd      07/05/12 Upadted micro sleep function to make use Global Timer
+* 4.2	pkp		 08/04/14 Removed unimplemented nanosleep routine as it is not
+*						  possible to generate timer in nanosecond due to
+*						  limited cpu frequency
+* 6.0   asa      08/15/16 Updated the usleep signature. Fix for CR#956899.
+* </pre>
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "sleep.h"
+#include "xtime_l.h"
+#include "xparameters.h"
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+#include "xreg_cortexa9.h"
+
+/* Global Timer is always clocked at half of the CPU frequency */
+#define COUNTS_PER_USECOND  (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ / (2U*1000000U))
+
+/*****************************************************************************/
+/**
+*
+* This API gives a delay in microseconds
+*
+* @param	useconds requested
+*
+* @return	0 if the delay can be achieved, -1 if the requested delay
+*		is out of range
+*
+* @note		None.
+*
+****************************************************************************/
+int usleep(unsigned long useconds)
+{
+	XTime tEnd, tCur;
+
+	XTime_GetTime(&tCur);
+	tEnd = tCur + (((XTime) useconds) * COUNTS_PER_USECOND);
+	do
+	{
+		XTime_GetTime(&tCur);
+	} while (tCur < tEnd);
+
+	return 0;
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/usleep.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/usleep.o
new file mode 100644
index 0000000000000000000000000000000000000000..1d60cf2786e936a6e2d636ca76678cfd88a27522
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diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/vectors.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/vectors.c
new file mode 100644
index 0000000000000000000000000000000000000000..0a3616328f7dee51d1eceb7a780938a8a8e18dd6
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/vectors.c
@@ -0,0 +1,231 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file vectors.c
+*
+* This file contains the C level vectors for the ARM Cortex A9 core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/09 Initial version, moved over from bsp area
+* 6.0   mus  27/07/16 Consolidated vectors for a53,a9 and r5 processor
+*                     and added UndefinedException for a53 32 bit and r5
+*                     processor
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "xil_exception.h"
+#include "vectors.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+typedef struct {
+	Xil_ExceptionHandler Handler;
+	void *Data;
+} XExc_VectorTableEntry;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+extern XExc_VectorTableEntry XExc_VectorTable[];
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the FIQ interrupt called from the vectors.s
+* file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void FIQInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_FIQ_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_FIQ_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the IRQ interrupt called from the vectors.s
+* file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void IRQInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_IRQ_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_IRQ_INT].Data);
+}
+
+#if !defined (__aarch64__)
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the Undefined exception called from the
+* vectors.s file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void UndefinedException(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_UNDEFINED_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_UNDEFINED_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the SW Interrupt called from the vectors.s
+* file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void SWInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_SWI_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_SWI_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the DataAbort Interrupt called from the
+* vectors.s file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void DataAbortInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Handler(
+		XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the PrefetchAbort Interrupt called from the
+* vectors.s file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void PrefetchAbortInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Handler(
+		XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Data);
+}
+#else
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the Synchronous Interrupt called from the vectors.s
+* file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void SynchronousInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_SYNC_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_SYNC_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the SError Interrupt called from the
+* vectors.s file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void SErrorInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Handler(
+		XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Data);
+}
+
+#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/vectors.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/vectors.h
new file mode 100644
index 0000000000000000000000000000000000000000..bb599b5602601d799de56541046a0530075fedff
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/vectors.h
@@ -0,0 +1,88 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file vectors.h
+*
+* This file contains the C level vector prototypes for the ARM Cortex A9 core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/10 Initial version, moved over from bsp area
+* 6.0   mus  07/27/16 Consolidated vectors for a9,a53 and r5 processors
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _VECTORS_H_
+#define _VECTORS_H_
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void FIQInterrupt(void);
+void IRQInterrupt(void);
+#if !defined (__aarch64__)
+void SWInterrupt(void);
+void DataAbortInterrupt(void);
+void PrefetchAbortInterrupt(void);
+void UndefinedException(void);
+#else
+void SynchronousInterrupt(void);
+void SErrorInterrupt(void);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/vectors.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/vectors.o
new file mode 100644
index 0000000000000000000000000000000000000000..d212a569f86e8204ce871fb9703ee30b3f54351e
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/vectors.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/write.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/write.c
new file mode 100644
index 0000000000000000000000000000000000000000..aaa879e737436c5e057731371dd19b6e1297d693
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/write.c
@@ -0,0 +1,112 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/* write.c -- write bytes to an output device.
+ */
+#ifndef UNDEFINE_FILE_OPS
+#include "xil_printf.h"
+#include "xparameters.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) sint32 _write (sint32 fd, char8* buf, sint32 nbytes);
+}
+#endif
+
+/*
+ * write -- write bytes to the serial port. Ignore fd, since
+ *          stdout and stderr are the same. Since we have no filesystem,
+ *          open will only return an error.
+ */
+__attribute__((weak)) sint32
+write (sint32 fd, char8* buf, sint32 nbytes)
+
+{
+#ifdef STDOUT_BASEADDRESS
+  s32 i;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  for (i = 0; i < nbytes; i++) {
+	if(LocalBuf != NULL) {
+		LocalBuf += i;
+	}
+	if(LocalBuf != NULL) {
+	    if (*LocalBuf == '\n') {
+	      outbyte ('\r');
+	    }
+	    outbyte (*LocalBuf);
+	}
+	if(LocalBuf != NULL) {
+		LocalBuf -= i;
+	}
+  }
+  return (nbytes);
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
+
+__attribute__((weak)) sint32
+_write (sint32 fd, char8* buf, sint32 nbytes)
+{
+#ifdef STDOUT_BASEADDRESS
+  s32 i;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  for (i = 0; i < nbytes; i++) {
+	if(LocalBuf != NULL) {
+		LocalBuf += i;
+	}
+	if(LocalBuf != NULL) {
+	    if (*LocalBuf == '\n') {
+	      outbyte ('\r');
+	    }
+	    outbyte (*LocalBuf);
+	}
+	if(LocalBuf != NULL) {
+		LocalBuf -= i;
+	}
+  }
+  return (nbytes);
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
+#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/write.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/write.o
new file mode 100644
index 0000000000000000000000000000000000000000..d70c9e2e6c9201688e6e3673d9a0dbe403622a1a
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/write.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xbasic_types.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xbasic_types.h
new file mode 100644
index 0000000000000000000000000000000000000000..787212ca75ff368e405799266b103f095b0b22a1
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xbasic_types.h
@@ -0,0 +1,119 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xbasic_types.h
+*
+*
+* @note  Dummy File for backwards compatibility
+*
+
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a adk   1/31/14  Added in bsp common folder for backward compatibility
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XBASIC_TYPES_H	/* prevent circular inclusions */
+#define XBASIC_TYPES_H	/* by using protection macros */
+
+/** @name Legacy types
+ * Deprecated legacy types.
+ * @{
+ */
+typedef unsigned char	Xuint8;		/**< unsigned 8-bit */
+typedef char		Xint8;		/**< signed 8-bit */
+typedef unsigned short	Xuint16;	/**< unsigned 16-bit */
+typedef short		Xint16;		/**< signed 16-bit */
+typedef unsigned long	Xuint32;	/**< unsigned 32-bit */
+typedef long		Xint32;		/**< signed 32-bit */
+typedef float		Xfloat32;	/**< 32-bit floating point */
+typedef double		Xfloat64;	/**< 64-bit double precision FP */
+typedef unsigned long	Xboolean;	/**< boolean (XTRUE or XFALSE) */
+
+#if !defined __XUINT64__
+typedef struct
+{
+	Xuint32 Upper;
+	Xuint32 Lower;
+} Xuint64;
+#endif
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XIL_TYPES_H
+typedef Xuint32         u32;
+typedef Xuint16         u16;
+typedef Xuint8          u8;
+#endif
+#else
+#include <linux/types.h>
+#endif
+
+#ifndef TRUE
+#  define TRUE		1U
+#endif
+
+#ifndef FALSE
+#  define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+/*
+ * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
+ * Please use NULL, TRUE and FALSE
+ */
+#define XNULL		NULL
+#define XTRUE		TRUE
+#define XFALSE		FALSE
+
+/*
+ * This file is deprecated and users
+ * should use xil_types.h and xil_assert.h\n\r
+ */
+#warning  The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
+#warning  Please refer the Standalone BSP UG647 for further details
+
+
+#endif	/* end of protection macro */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xdebug.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xdebug.h
new file mode 100644
index 0000000000000000000000000000000000000000..650946bd01f4555daaeaf12db9919130e4aecf7d
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xdebug.h
@@ -0,0 +1,32 @@
+#ifndef XDEBUG  /* prevent circular inclusions */
+#define XDEBUG  /* by using protection macros */
+
+#if defined(DEBUG) && !defined(NDEBUG)
+
+#ifndef XDEBUG_WARNING
+#define XDEBUG_WARNING
+#warning DEBUG is enabled
+#endif
+
+int printf(const char *format, ...);
+
+#define XDBG_DEBUG_ERROR             0x00000001U    /* error  condition messages */
+#define XDBG_DEBUG_GENERAL           0x00000002U    /* general debug  messages */
+#define XDBG_DEBUG_ALL               0xFFFFFFFFU    /* all debugging data */
+
+#define xdbg_current_types (XDBG_DEBUG_GENERAL)
+
+#define xdbg_stmnt(x)  x
+
+#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
+
+
+#else /* defined(DEBUG) && !defined(NDEBUG) */
+
+#define xdbg_stmnt(x)
+
+#define xdbg_printf(...)
+
+#endif /* defined(DEBUG) && !defined(NDEBUG) */
+
+#endif /* XDEBUG */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xenv.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xenv.h
new file mode 100644
index 0000000000000000000000000000000000000000..3d97bebd450eda76d8221c8a9b012bb723c9b6ca
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xenv.h
@@ -0,0 +1,187 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv.h
+*
+* Defines common services that are typically found in a host operating.
+* environment. This include file simply includes an OS specific file based
+* on the compile-time constant BUILD_ENV_*, where * is the name of the target
+* environment.
+*
+* All services are defined as macros.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b ch   10/24/02 Added XENV_LINUX
+* 1.00a rmm  04/17/02 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XENV_H /* prevent circular inclusions */
+#define XENV_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Select which target environment we are operating under
+ */
+
+/* VxWorks target environment */
+#if defined XENV_VXWORKS
+#include "xenv_vxworks.h"
+
+/* Linux target environment */
+#elif defined XENV_LINUX
+#include "xenv_linux.h"
+
+/* Unit test environment */
+#elif defined XENV_UNITTEST
+#include "ut_xenv.h"
+
+/* Integration test environment */
+#elif defined XENV_INTTEST
+#include "int_xenv.h"
+
+/* Standalone environment selected */
+#else
+#include "xenv_standalone.h"
+#endif
+
+
+/*
+ * The following comments specify the types and macro wrappers that are
+ * expected to be defined by the target specific header files
+ */
+
+/**************************** Type Definitions *******************************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP
+ *
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param   DestPtr is the destination address to copy data to.
+ * @param   SrcPtr is the source address to copy data from.
+ * @param   Bytes is the number of bytes to copy.
+ *
+ * @return  None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param   DestPtr is the destination address to set.
+ * @param   Data contains the value to set.
+ * @param   Bytes is the number of bytes to set.
+ *
+ * @return  None
+ */
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ *
+ * Samples the processor's or external timer's time base counter.
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param   Stamp1Ptr - First sampled time stamp.
+ * @param   Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return  An unsigned int value with units of microseconds.
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param   Stamp1Ptr - First sampled time stamp.
+ * @param   Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return  An unsigned int value with units of milliseconds.
+ */
+
+/*****************************************************************************//**
+ *
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds.
+ *
+ * @param   delay is the number of microseconds to delay.
+ *
+ * @return  None
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xenv_standalone.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xenv_standalone.h
new file mode 100644
index 0000000000000000000000000000000000000000..f18601874bb5b8a84f10954730b4aca1bc988598
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xenv_standalone.h
@@ -0,0 +1,368 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv_standalone.h
+*
+* Defines common services specified by xenv.h.
+*
+* @note
+* 	This file is not intended to be included directly by driver code.
+* 	Instead, the generic xenv.h file is intended to be included by driver
+* 	code.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr  02/28/07 Added cache handling macros.
+* 1.00a wgr  02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a rmm  01/24/06 Implemented XENV_USLEEP. Assume implementation is being
+*                     used under Xilinx standalone BSP.
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* 1.00a rmm  03/21/02 First release
+* 1.00a wgr  03/22/07 Converted to new coding style.
+* 1.00a rpm  06/29/07 Added udelay macro for standalone
+* 1.00a xd   07/19/07 Included xparameters.h as XPAR_ constants are referred
+*                     to in MICROBLAZE section
+* 1.00a ecm  09/19/08 updated for v7.20 of Microblaze, new functionality
+*
+* </pre>
+*
+*
+******************************************************************************/
+
+#ifndef XENV_STANDALONE_H
+#define XENV_STANDALONE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+/******************************************************************************
+ *
+ * Get the processor dependent includes
+ *
+ ******************************************************************************/
+
+#include <string.h>
+
+#if defined __MICROBLAZE__
+#  include "mb_interface.h"
+#  include "xparameters.h"   /* XPAR constants used below in MB section */
+
+#elif defined __PPC__
+#  include "sleep.h"
+#  include "xcache_l.h"      /* also include xcache_l.h for caching macros */
+#endif
+
+/******************************************************************************
+ *
+ * MEMCPY / MEMSET related macros.
+ *
+ * The following are straight forward implementations of memset and memcpy.
+ *
+ * NOTE: memcpy may not work if source and target memory area are overlapping.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	SrcPtr
+ * 		Source address to copy data from.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note
+ * 		The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
+ *
+ * @note
+ * 		This implemention MAY BREAK work if source and target memory
+ * 		area are overlapping.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
+	memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
+
+
+
+/*****************************************************************************/
+/**
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	Data
+ * 		Value to set.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note
+ * 		The use of XENV_MEM_FILL is deprecated. Use memset() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
+	memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
+
+
+
+/******************************************************************************
+ *
+ * TIME related macros
+ *
+ ******************************************************************************/
+
+/**
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+typedef s32 XENV_TIME_STAMP;
+
+/*****************************************************************************/
+/**
+ *
+ * Time is derived from the 64 bit PPC timebase register
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None.
+ *
+ * @note
+ *
+ * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ * <br><br>
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_GET(StampPtr)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds. Not implemented without OS
+ * support.
+ *
+ * @param	delay
+ * 		Number of microseconds to delay.
+ *
+ * @return	None.
+ *
+ *****************************************************************************/
+
+#ifdef __PPC__
+#define XENV_USLEEP(delay)	usleep(delay)
+#define udelay(delay)	usleep(delay)
+#else
+#define XENV_USLEEP(delay)
+#define udelay(delay)
+#endif
+
+
+/******************************************************************************
+ *
+ * CACHE handling macros / mappings
+ *
+ ******************************************************************************/
+/******************************************************************************
+ *
+ * Processor independent macros
+ *
+ ******************************************************************************/
+
+#define XCACHE_ENABLE_CACHE()	\
+		{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
+
+#define XCACHE_DISABLE_CACHE()	\
+		{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
+
+
+/******************************************************************************
+ *
+ * MicroBlaze case
+ *
+ * NOTE: Currently the following macros will only work on systems that contain
+ * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
+ * system is built using a xparameters.h file.
+ *
+ ******************************************************************************/
+
+#if defined __MICROBLAZE__
+
+/* Check if MicroBlaze data cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
+#  define XCACHE_ENABLE_DCACHE()		microblaze_enable_dcache()
+#  define XCACHE_DISABLE_DCACHE()		microblaze_disable_dcache()
+#  define XCACHE_INVALIDATE_DCACHE()  	microblaze_invalidate_dcache()
+
+#  define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+
+#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
+#  define XCACHE_FLUSH_DCACHE()  		microblaze_flush_dcache()
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+			microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
+#else
+#  define XCACHE_FLUSH_DCACHE()  		microblaze_invalidate_dcache()
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+#endif	/*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
+
+#else
+#  define XCACHE_ENABLE_DCACHE()
+#  define XCACHE_DISABLE_DCACHE()
+#  define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
+#endif	/*XPAR_MICROBLAZE_USE_DCACHE*/
+
+
+/* Check if MicroBlaze instruction cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
+#  define XCACHE_ENABLE_ICACHE()		microblaze_enable_icache()
+#  define XCACHE_DISABLE_ICACHE()		microblaze_disable_icache()
+
+#  define XCACHE_INVALIDATE_ICACHE()  	microblaze_invalidate_icache()
+
+#  define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
+
+#else
+#  define XCACHE_ENABLE_ICACHE()
+#  define XCACHE_DISABLE_ICACHE()
+#endif	/*XPAR_MICROBLAZE_USE_ICACHE*/
+
+
+/******************************************************************************
+ *
+ * PowerPC case
+ *
+ *   Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
+ *   specific memory region (0x80000001). Each bit (0-30) in the regions
+ *   bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
+ *   range.
+ *
+ *   regions    --> cached address range
+ *   ------------|--------------------------------------------------
+ *   0x80000000  | [0, 0x7FFFFFF]
+ *   0x00000001  | [0xF8000000, 0xFFFFFFFF]
+ *   0x80000001  | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
+ *
+ ******************************************************************************/
+
+#elif defined __PPC__
+
+#define XCACHE_ENABLE_DCACHE()		XCache_EnableDCache(0x80000001)
+#define XCACHE_DISABLE_DCACHE()		XCache_DisableDCache()
+#define XCACHE_ENABLE_ICACHE()		XCache_EnableICache(0x80000001)
+#define XCACHE_DISABLE_ICACHE()		XCache_DisableICache()
+
+#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+		XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+		XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_INVALIDATE_ICACHE()	XCache_InvalidateICache()
+
+
+/******************************************************************************
+ *
+ * Unknown processor / architecture
+ *
+ ******************************************************************************/
+
+#else
+/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* #ifndef XENV_STANDALONE_H */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil-crt0.S b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil-crt0.S
new file mode 100644
index 0000000000000000000000000000000000000000..64175fef9612626b70016d15fee22d5769d89f5c
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil-crt0.S
@@ -0,0 +1,150 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil-crt0.S
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/09 Initial version
+* 3.05a sdm  02/02/12 Added code for profiling
+* 3.06a sgd  05/16/12 Added global constructors and cleanup code
+*                     Uart initialization based on compiler flag
+* 3.07a sgd  07/05/12 Updated with reset and start Global Timer
+* 3.07a sgd  10/19/12 SMC NOR and SRAM initialization with build option
+* 4.2	pkp  08/04/14 Removed PEEP board related code which contained
+*		      initialization of uart smc nor and sram
+* 5.3	pkp  10/07/15 Added support for OpenAMP by not initializing global
+*		      timer when USE_AMP flag is defined
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+	.file	"xil-crt0.S"
+	.section ".got2","aw"
+	.align	2
+
+	.text
+.Lsbss_start:
+	.long	__sbss_start
+
+.Lsbss_end:
+	.long	__sbss_end
+
+.Lbss_start:
+	.long	__bss_start
+
+.Lbss_end:
+	.long	__bss_end
+
+.Lstack:
+	.long	__stack
+
+
+	.globl	_start
+_start:
+	bl      __cpu_init		/* Initialize the CPU first (BSP provides this) */
+
+	mov	r0, #0
+
+	/* clear sbss */
+	ldr 	r1,.Lsbss_start		/* calculate beginning of the SBSS */
+	ldr	r2,.Lsbss_end		/* calculate end of the SBSS */
+
+.Lloop_sbss:
+	cmp	r1,r2
+	bge	.Lenclsbss		/* If no SBSS, no clearing required */
+	str	r0, [r1], #4
+	b	.Lloop_sbss
+
+.Lenclsbss:
+	/* clear bss */
+	ldr	r1,.Lbss_start		/* calculate beginning of the BSS */
+	ldr	r2,.Lbss_end		/* calculate end of the BSS */
+
+.Lloop_bss:
+	cmp	r1,r2
+	bge	.Lenclbss		/* If no BSS, no clearing required */
+	str	r0, [r1], #4
+	b	.Lloop_bss
+
+.Lenclbss:
+
+	/* set stack pointer */
+	ldr	r13,.Lstack		/* stack address */
+
+    /* Reset and start Global Timer */
+	mov	r0, #0x0
+	mov	r1, #0x0
+
+#if USE_AMP != 1
+	bl XTime_SetTime
+#endif
+
+#ifdef PROFILING			/* defined in Makefile */
+	/* Setup profiling stuff */
+	bl	_profile_init
+#endif /* PROFILING */
+
+   /* run global constructors */
+   bl __libc_init_array
+
+	/* make sure argc and argv are valid */
+	mov	r0, #0
+	mov	r1, #0
+
+	/* Let her rip */
+	bl	main
+
+   /* Cleanup global constructors */
+   bl __libc_fini_array
+
+#ifdef PROFILING
+	/* Cleanup profiling stuff */
+	bl	_profile_clean
+#endif /* PROFILING */
+
+        /* All done */
+	bl	exit
+
+.Lexit:	/* should never get here */
+	b .Lexit
+
+.Lstart:
+	.size	_start,.Lstart-_start
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil-crt0.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil-crt0.o
new file mode 100644
index 0000000000000000000000000000000000000000..a955917946c070a2d36459e3a1119035a789ded0
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil-crt0.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_assert.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_assert.c
new file mode 100644
index 0000000000000000000000000000000000000000..59b3c1c98be72a13c998fb13b2ea66892d4dbc88
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_assert.c
@@ -0,0 +1,147 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.c
+*
+* This file contains basic assert related functions for Xilinx software IP.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 Initial release
+* 6.0   kvn  05/31/16 Make Xil_AsserWait a global variable
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/**
+ * This variable allows testing to be done easier with asserts. An assert
+ * sets this variable such that a driver can evaluate this variable
+ * to determine if an assert occurred.
+ */
+u32 Xil_AssertStatus;
+
+/**
+ * This variable allows the assert functionality to be changed for testing
+ * such that it does not wait infinitely. Use the debugger to disable the
+ * waiting during testing of asserts.
+ */
+s32 Xil_AssertWait = 1;
+
+/* The callback function to be invoked when an assert is taken */
+static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* @brief    Implement assert. Currently, it calls a user-defined callback
+*           function if one has been set.  Then, it potentially enters an
+*           infinite loop depending on the value of the Xil_AssertWait
+*           variable.
+*
+* @param    file: filename of the source
+* @param    line: linenumber within File
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+void Xil_Assert(const char8 *File, s32 Line)
+{
+	/* if the callback has been set then invoke it */
+	if (Xil_AssertCallbackRoutine != 0) {
+		(*Xil_AssertCallbackRoutine)(File, Line);
+	}
+
+	/* if specified, wait indefinitely such that the assert will show up
+	 * in testing
+	 */
+	while (Xil_AssertWait != 0) {
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Set up a callback function to be invoked when an assert occurs.
+*           If a callback is already installed, then it will be replaced.
+*
+* @param    routine: callback to be invoked when an assert is taken
+*
+* @return   None.
+*
+* @note     This function has no effect if NDEBUG is set
+*
+******************************************************************************/
+void Xil_AssertSetCallback(Xil_AssertCallback Routine)
+{
+	Xil_AssertCallbackRoutine = Routine;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Null handler function. This follows the XInterruptHandler
+*           signature for interrupt handlers. It can be used to assign a null
+*           handler (a stub) to an interrupt controller vector table.
+*
+* @param    NullParameter: arbitrary void pointer and not used.
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+void XNullHandler(void *NullParameter)
+{
+	(void) NullParameter;
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_assert.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_assert.h
new file mode 100644
index 0000000000000000000000000000000000000000..add4124e2c0c48a8844dfb3aad307c8ec5ae6e38
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_assert.h
@@ -0,0 +1,195 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.h
+*
+* @addtogroup common_assert_apis Assert APIs and Macros
+*
+* The xil_assert.h file contains assert related functions and macros.
+* Assert APIs/Macros specifies that a application program satisfies certain
+* conditions at particular points in its execution. These function can be
+* used by application programs to ensure that, application code is satisfying
+* certain conditions.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* 6.0   kvn  05/31/16 Make Xil_AsserWait a global variable
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_ASSERT_H	/* prevent circular inclusions */
+#define XIL_ASSERT_H	/* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+
+/************************** Constant Definitions *****************************/
+
+#define XIL_ASSERT_NONE     0U
+#define XIL_ASSERT_OCCURRED 1U
+#define XNULL NULL
+
+extern u32 Xil_AssertStatus;
+extern s32 Xil_AssertWait;
+extern void Xil_Assert(const char8 *File, s32 Line);
+void XNullHandler(void *NullParameter);
+
+/**
+ * This data type defines a callback to be invoked when an
+ * assert occurs. The callback is invoked only when asserts are enabled
+ */
+typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#ifndef NDEBUG
+
+/*****************************************************************************/
+/**
+* @brief    This assert macro is to be used for void functions. This in
+*           conjunction with the Xil_AssertWait boolean can be used to
+*           accomodate tests so that asserts which fail allow execution to
+*           continue.
+*
+* @param    Expression: expression to be evaluated. If it evaluates to
+*           false, the assert occurs.
+*
+* @return   Returns void unless the Xil_AssertWait variable is true, in which
+*           case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertVoid(Expression)                \
+{                                                  \
+    if (Expression) {                              \
+        Xil_AssertStatus = XIL_ASSERT_NONE;       \
+    } else {                                       \
+        Xil_Assert(__FILE__, __LINE__);            \
+        Xil_AssertStatus = XIL_ASSERT_OCCURRED;   \
+        return;                                    \
+    }                                              \
+}
+
+/*****************************************************************************/
+/**
+* @brief    This assert macro is to be used for functions that do return a
+*           value. This in conjunction with the Xil_AssertWait boolean can be
+*           used to accomodate tests so that asserts which fail allow execution
+*           to continue.
+*
+* @param    Expression: expression to be evaluated. If it evaluates to false,
+*           the assert occurs.
+*
+* @return   Returns 0 unless the Xil_AssertWait variable is true, in which
+* 	        case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertNonvoid(Expression)             \
+{                                                  \
+    if (Expression) {                              \
+        Xil_AssertStatus = XIL_ASSERT_NONE;       \
+    } else {                                       \
+        Xil_Assert(__FILE__, __LINE__);            \
+        Xil_AssertStatus = XIL_ASSERT_OCCURRED;   \
+        return 0;                                  \
+    }                                              \
+}
+
+/*****************************************************************************/
+/**
+* @brief     Always assert. This assert macro is to be used for void functions.
+*            Use for instances where an assert should always occur.
+*
+* @return    Returns void unless the Xil_AssertWait variable is true, in which
+*	         case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertVoidAlways()                   \
+{                                                  \
+   Xil_Assert(__FILE__, __LINE__);                 \
+   Xil_AssertStatus = XIL_ASSERT_OCCURRED;        \
+   return;                                         \
+}
+
+/*****************************************************************************/
+/**
+* @brief   Always assert. This assert macro is to be used for functions that
+*          do return a value. Use for instances where an assert should always
+*          occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+*	      case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertNonvoidAlways()                \
+{                                                  \
+   Xil_Assert(__FILE__, __LINE__);                 \
+   Xil_AssertStatus = XIL_ASSERT_OCCURRED;        \
+   return 0;                                       \
+}
+
+
+#else
+
+#define Xil_AssertVoid(Expression)
+#define Xil_AssertVoidAlways()
+#define Xil_AssertNonvoid(Expression)
+#define Xil_AssertNonvoidAlways()
+
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_AssertSetCallback(Xil_AssertCallback Routine);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/**
+* @} End of "addtogroup common_assert_apis".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_assert.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_assert.o
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index 0000000000000000000000000000000000000000..f756230a2d8d978f90eb88456f33752790a1d889
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_assert.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_cache.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_cache.c
new file mode 100644
index 0000000000000000000000000000000000000000..83f68352f11278b4fcbe9371b3e9193e12f80801
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_cache.c
@@ -0,0 +1,1621 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.c
+*
+* Contains required functions for the ARM cache functionality.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver    Who Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a  ecm 01/29/10 First release
+* 1.00a  ecm 06/24/10 Moved the L1 and L2 specific function prototypes
+*		      		  to xil_cache_mach.h to give access to sophisticated users
+* 3.02a  sdm 04/07/11 Updated Flush/InvalidateRange APIs to flush/invalidate
+*		      		  L1 and L2 caches in a single loop and used dsb, L2 sync
+*		      		  at the end of the loop.
+* 3.04a  sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
+*		      		  APIs.
+* 3.07a  asa 07/16/12 Corrected the L1 and L2 cache invalidation order.
+* 3.07a  sgd 09/18/12 Corrected the L2 cache enable and disable sequence.
+* 3.10a  srt 04/18/13 Implemented ARM Erratas. Please refer to file
+*		      		  'xil_errata.h' for errata description
+* 3.10a  asa 05/13/13 Modified cache disable APIs. The L2 cache disable
+*			  		  operation was being done with L1 Data cache disabled. This is
+*			  		  fixed so that L2 cache disable operation happens independent of
+*			  		  L1 cache disable operation. This fixes CR #706464.
+*			  		  Changes are done to do a L2 cache sync (poll reg7_?cache_?sync).
+*			  		  This is done to fix the CR #700542.
+* 3.11a  asa 09/23/13 Modified the Xil_DCacheFlushRange and
+*			 		  Xil_DCacheInvalidateRange to fix potential issues. Fixed other
+*			 		  relevant cache APIs to disable and enable back the interrupts.
+*			 		  This fixes CR #663885.
+* 3.11a  asa 09/28/13 Made changes for L2 cache sync operation. It is found
+*			 		  out that for L2 cache flush/clean/invalidation by cache lines
+*			 		  does not need a cache sync as these are atomic nature. Similarly
+*			 		  figured out that for complete L2 cache flush/invalidation by way
+*			 		  we need to wait for some more time in a loop till the status
+*			 		  shows that the cache operation is completed.
+* 4.00	 pkp 24/01/14 Modified Xil_DCacheInvalidateRange to fix the bug. Few
+*			 		  cache lines were missed to invalidate when unaligned address
+*			 		  invalidation was accommodated. That fixes CR #766768.
+*			 		  Also in Xil_L1DCacheInvalidate, while invalidating all L1D cache
+*			 		  stack memory which contains return address was invalidated. So
+*			 		  stack memory was flushed first and then L1D cache is invalidated.
+*			 		  This is done to fix CR #763829
+* 4.01   asa 05/09/14 Made changes in cortexa9/xil_cache.c to fix CR# 798230.
+* 4.02	 pkp 06/27/14 Added notes to Xil_L1DCacheInvalidateRange function for
+*					  explanation of CR#785243
+* 5.00   kvn 12/15/14 Xil_L2CacheInvalidate was modified to fix CR# 838835. L2 Cache
+*					  has stack memory which has return address. Before invalidating
+*					  cache, stack memory was flushed first and L2 Cache is invalidated.
+* 5.01	 pkp 05/12/15 Xil_DCacheInvalidateRange and Xil_DCacheFlushRange is modified
+*					  to remove unnecessary dsb in the APIs. Instead of using dsb
+*					  for L2 Cache, L2CacheSync has been used for each L2 cache line
+*					  and single dsb has been used for L1 cache. Also L2CacheSync is
+*					  added into Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate
+*					  and Xil_L2CacheInvalidate APIs are modified to flush the complete
+*					  stack instead of just System Stack
+* 5.03	 pkp 10/07/15 L2 Cache functionalities are avoided for the OpenAMP slave
+*					  application(when USE_AMP flag is defined for BSP) as master CPU
+*					  would be utilizing L2 cache for its operation
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xil_cache_l.h"
+#include "xil_io.h"
+#include "xpseudo_asm.h"
+#include "xparameters.h"
+#include "xreg_cortexa9.h"
+#include "xl2cc.h"
+#include "xil_errata.h"
+#include "xil_exception.h"
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#define IRQ_FIQ_MASK 0xC0U	/* Mask IRQ and FIQ interrupts in cpsr */
+
+#ifdef __GNUC__
+	extern s32  _stack_end;
+	extern s32  __undef_stack;
+#endif
+
+#ifndef USE_AMP
+/****************************************************************************
+*
+* Access L2 Debug Control Register.
+*
+* @param	Value, value to be written to Debug Control Register.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+#ifdef __GNUC__
+static inline void Xil_L2WriteDebugCtrl(u32 Value)
+#else
+static void Xil_L2WriteDebugCtrl(u32 Value)
+#endif
+{
+#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DEBUG_CTRL_OFFSET, Value);
+#else
+	(void)(Value);
+#endif
+}
+
+/****************************************************************************
+*
+* Perform L2 Cache Sync Operation.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+#ifdef __GNUC__
+static inline void Xil_L2CacheSync(void)
+#else
+static void Xil_L2CacheSync(void)
+#endif
+{
+#ifdef CONFIG_PL310_ERRATA_753970
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET, 0x0U);
+#else
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_SYNC_OFFSET, 0x0U);
+#endif
+}
+#endif
+/****************************************************************************/
+/**
+* @brief	Enable the Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheEnable(void)
+{
+	Xil_L1DCacheEnable();
+#ifndef USE_AMP
+	Xil_L2CacheEnable();
+#endif
+}
+
+/****************************************************************************/
+/**
+* @brief	Disable the Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheDisable(void)
+{
+#ifndef USE_AMP
+	Xil_L2CacheDisable();
+#endif
+	Xil_L1DCacheDisable();
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate the entire Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheInvalidate(void)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+#ifndef USE_AMP
+	Xil_L2CacheInvalidate();
+#endif
+	Xil_L1DCacheInvalidate();
+
+	mtcpsr(currmask);
+}
+
+/*****************************************************************************/
+/**
+* @brief	Invalidate a Data cache line. If the byte specified by the address
+* 			(adr) is cached by the Data cache, the cacheline containing that
+* 			byte is invalidated. If the cacheline is modified (dirty), the
+* 			modified contents are lost and are NOT written to the system memory
+* 			before the line is invalidated.
+*
+* @param	adr: 32bit address of the data to be flushed.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheInvalidateLine(u32 adr)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+#ifndef USE_AMP
+	Xil_L2CacheInvalidateLine(adr);
+#endif
+	Xil_L1DCacheInvalidateLine(adr);
+
+	mtcpsr(currmask);
+}
+
+
+/*****************************************************************************/
+/**
+* @brief	Invalidate the Data cache for the given address range.
+* 			If the bytes specified by the address range are cached by the Data
+*			cache, the cachelines containing those bytes are invalidated. If
+*			the cachelines are modified (dirty), the modified contents are lost
+*			and NOT written to the system memory before the lines are
+*			invalidated.
+*
+* 			In this function, if start address or end address is not aligned to
+* 			cache-line, particular cache-line containing unaligned start or end
+* 			address is flush first and then invalidated the others as
+* 			invalidating the same unaligned cache line may result into loss of
+*			data. This issue raises few possibilities.
+*
+* 			If the address to be invalidated is not cache-line aligned, the
+* 			following choices are available:
+* 			1. Invalidate the cache line when required and do not bother much
+* 			for the side effects. Though it sounds good, it can result in
+* 			hard-to-debug issues. The problem is, if some other variable are
+* 			allocated in the same cache line and had been recently updated
+* 			(in cache), the invalidation would result in loss of data.
+* 			2. Flush the cache line first. This will ensure that if any other
+* 			variable present in the same cache line and updated recently are
+* 			flushed out to memory. Then it can safely be invalidated. Again it
+* 			sounds good, but this can result in issues. For example, when the
+* 			invalidation happens in a typical ISR (after a DMA transfer has
+* 			updated the memory), then flushing the cache line means, loosing
+* 			data that were updated recently before the ISR got invoked.
+*
+* 			Linux prefers the second one. To have uniform implementation
+* 			(across standalone and Linux), the second option is implemented.
+* 			This being the case, follwoing needs to be taken care of:
+* 			1. Whenever possible, the addresses must be cache line aligned.
+* 			Please nore that, not just start address, even the end address must
+* 			be cache line aligned. If that is taken care of, this will always
+*			work.
+* 			2. Avoid situations where invalidation has to be done after the
+* 			data is updated by peripheral/DMA directly into the memory. It is
+* 			not tough to achieve (may be a bit risky). The common use case to
+* 			do invalidation is when a DMA happens. Generally for such use
+*			cases, buffers can be allocated first and then start the DMA. The
+* 			practice that needs to be followed here is, immediately after
+* 			buffer allocation and before starting the DMA, do the invalidation.
+* 			With this approach, invalidation need not to be done after the DMA
+*			transfer is over.
+*
+* 			This is going to always work if done carefully.
+* 			However, the concern is, there is no guarantee that invalidate has
+* 			not needed to be done after DMA is complete. For example, because
+* 			of some reasons if the first cache line or last cache line
+* 			(assuming the buffer in question comprises of multiple cache lines)
+*			are brought into cache (between the time it is invalidated and DMA
+* 			completes) because of some speculative prefetching or reading data
+* 			for a variable present in the same cache line, then we will have to
+*			invalidate the cache after DMA is complete.
+*
+*
+* @param	adr: 32bit start address of the range to be invalidated.
+* @param	len: Length of the range to be invalidated in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
+{
+	const u32 cacheline = 32U;
+	u32 end;
+	u32 tempadr = adr;
+	u32 tempend;
+	u32 currmask;
+	volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+				    XPS_L2CC_CACHE_INVLD_PA_OFFSET);
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0U) {
+		end = tempadr + len;
+		tempend = end;
+		/* Select L1 Data cache in CSSR */
+		mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+
+		if ((tempadr & (cacheline-1U)) != 0U) {
+			tempadr &= (~(cacheline - 1U));
+
+			Xil_L1DCacheFlushLine(tempadr);
+#ifndef USE_AMP
+			/* Disable Write-back and line fills */
+			Xil_L2WriteDebugCtrl(0x3U);
+			Xil_L2CacheFlushLine(tempadr);
+			/* Enable Write-back and line fills */
+			Xil_L2WriteDebugCtrl(0x0U);
+			Xil_L2CacheSync();
+#endif
+			tempadr += cacheline;
+		}
+		if ((tempend & (cacheline-1U)) != 0U) {
+			tempend &= (~(cacheline - 1U));
+
+			Xil_L1DCacheFlushLine(tempend);
+#ifndef USE_AMP
+			/* Disable Write-back and line fills */
+			Xil_L2WriteDebugCtrl(0x3U);
+			Xil_L2CacheFlushLine(tempend);
+			/* Enable Write-back and line fills */
+			Xil_L2WriteDebugCtrl(0x0U);
+			Xil_L2CacheSync();
+#endif
+		}
+
+		while (tempadr < tempend) {
+#ifndef USE_AMP
+			/* Invalidate L2 cache line */
+			*L2CCOffset = tempadr;
+			Xil_L2CacheSync();
+#endif
+
+	/* Invalidate L1 Data cache line */
+#if defined (__GNUC__) || defined (__ICCARM__)
+			asm_cp15_inval_dc_line_mva_poc(tempadr);
+#else
+			{ volatile register u32 Reg
+				__asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
+			  Reg = tempadr; }
+#endif
+			tempadr += cacheline;
+		}
+	}
+
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Flush the entire Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheFlush(void)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+	Xil_L1DCacheFlush();
+#ifndef USE_AMP
+	Xil_L2CacheFlush();
+#endif
+	mtcpsr(currmask);
+}
+
+
+/****************************************************************************/
+/**
+* @brief	Flush a Data cache line. If the byte specified by the address (adr)
+* 			is cached by the Data cache, the cacheline containing that byte is
+* 			invalidated. If the cacheline is modified (dirty), the entire
+* 			contents of the cacheline are written to system memory before the
+* 			line is invalidated.
+*
+* @param	adr: 32bit address of the data to be flushed.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheFlushLine(u32 adr)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+	Xil_L1DCacheFlushLine(adr);
+#ifndef USE_AMP
+	/* Disable Write-back and line fills */
+	Xil_L2WriteDebugCtrl(0x3U);
+
+	Xil_L2CacheFlushLine(adr);
+
+	/* Enable Write-back and line fills */
+	Xil_L2WriteDebugCtrl(0x0U);
+	Xil_L2CacheSync();
+#endif
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Flush the Data cache for the given address range.
+* 			If the bytes specified by the address range are cached by the
+* 			data cache, the cachelines containing those bytes are invalidated.
+* 			If the cachelines are modified (dirty), they are written to the
+* 			system memory before the lines are invalidated.
+*
+* @param	adr: 32bit start address of the range to be flushed.
+* @param	len: Length of the range to be flushed in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheFlushRange(INTPTR adr, u32 len)
+{
+	u32 LocalAddr = adr;
+	const u32 cacheline = 32U;
+	u32 end;
+	u32 currmask;
+	volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+				    XPS_L2CC_CACHE_INV_CLN_PA_OFFSET);
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0U) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = LocalAddr + len;
+		LocalAddr &= ~(cacheline - 1U);
+
+		while (LocalAddr < end) {
+
+	/* Flush L1 Data cache line */
+#if defined (__GNUC__) || defined (__ICCARM__)
+			asm_cp15_clean_inval_dc_line_mva_poc(LocalAddr);
+#else
+			{ volatile register u32 Reg
+				__asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
+			  Reg = LocalAddr; }
+#endif
+#ifndef USE_AMP
+			/* Flush L2 cache line */
+			*L2CCOffset = LocalAddr;
+			Xil_L2CacheSync();
+#endif
+			LocalAddr += cacheline;
+		}
+	}
+	dsb();
+	mtcpsr(currmask);
+}
+/****************************************************************************/
+/**
+* @brief	Store a Data cache line. If the byte specified by the address (adr)
+* 			is cached by the Data cache and the cacheline is modified (dirty),
+* 			the entire contents of the cacheline are written to system memory.
+* 			After the store completes, the cacheline is marked as unmodified
+* 			(not dirty).
+*
+* @param	adr: 32bit address of the data to be stored.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheStoreLine(u32 adr)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	Xil_L1DCacheStoreLine(adr);
+#ifndef USE_AMP
+	Xil_L2CacheStoreLine(adr);
+#endif
+	mtcpsr(currmask);
+}
+
+/***************************************************************************/
+/**
+* @brief	Enable the instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ICacheEnable(void)
+{
+	Xil_L1ICacheEnable();
+#ifndef USE_AMP
+	Xil_L2CacheEnable();
+#endif
+}
+
+/***************************************************************************/
+/**
+* @brief	Disable the instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ICacheDisable(void)
+{
+#ifndef USE_AMP
+	Xil_L2CacheDisable();
+#endif
+	Xil_L1ICacheDisable();
+}
+
+
+/****************************************************************************/
+/**
+* @brief	Invalidate the entire instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ICacheInvalidate(void)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+#ifndef USE_AMP
+	Xil_L2CacheInvalidate();
+#endif
+	Xil_L1ICacheInvalidate();
+
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate an instruction cache line. If the instruction specified
+*			by the address is cached by the instruction cache, the cacheline
+*			containing that instruction is invalidated.
+*
+* @param	adr: 32bit address of the instruction to be invalidated.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_ICacheInvalidateLine(u32 adr)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+#ifndef USE_AMP
+	Xil_L2CacheInvalidateLine(adr);
+#endif
+	Xil_L1ICacheInvalidateLine(adr);
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate the instruction cache for the given address range.
+* 			If the instructions specified by the address range are cached by
+* 			the instrunction cache, the cachelines containing those
+*			instructions are invalidated.
+*
+* @param	adr: 32bit start address of the range to be invalidated.
+* @param	len: Length of the range to be invalidated in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
+{
+	u32 LocalAddr = adr;
+	const u32 cacheline = 32U;
+	u32 end;
+	volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+				    XPS_L2CC_CACHE_INVLD_PA_OFFSET);
+
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+	if (len != 0U) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = LocalAddr + len;
+		LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+		/* Select cache L0 I-cache in CSSR */
+		mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+
+		while (LocalAddr < end) {
+#ifndef USE_AMP
+		/* Invalidate L2 cache line */
+		*L2CCOffset = LocalAddr;
+		dsb();
+#endif
+
+		/* Invalidate L1 I-cache line */
+#if defined (__GNUC__) || defined (__ICCARM__)
+			asm_cp15_inval_ic_line_mva_pou(LocalAddr);
+#else
+			{ volatile register u32 Reg
+				__asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
+			  Reg = LocalAddr; }
+#endif
+
+			LocalAddr += cacheline;
+		}
+	}
+
+	/* Wait for L1 and L2 invalidate to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Enable the level 1 Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1DCacheEnable(void)
+{
+	register u32 CtrlReg;
+
+	/* enable caches only if they are disabled */
+#ifdef __GNUC__
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+	mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+#else
+	{ volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
+	  CtrlReg = Reg; }
+#endif
+	if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) {
+		return;
+	}
+
+	/* clean and invalidate the Data cache */
+	Xil_L1DCacheInvalidate();
+
+	/* enable the Data cache */
+	CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+
+	mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/***************************************************************************/
+/**
+* @brief	Disable the level 1 Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1DCacheDisable(void)
+{
+	register u32 CtrlReg;
+
+	/* clean and invalidate the Data cache */
+	Xil_L1DCacheFlush();
+
+#ifdef __GNUC__
+	/* disable the Data cache */
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+	mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+#else
+	{ volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
+	  CtrlReg = Reg; }
+#endif
+
+	CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+
+	mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate the level 1 Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		In Cortex A9, there is no cp instruction for invalidating
+*			the whole D-cache. This function invalidates each line by
+*			set/way.
+*
+****************************************************************************/
+void Xil_L1DCacheInvalidate(void)
+{
+	register u32 CsidReg, C7Reg;
+	u32 CacheSize, LineSize, NumWays;
+	u32 Way, WayIndex, Set, SetIndex, NumSet;
+	u32 currmask;
+
+#ifdef __GNUC__
+	u32 stack_start,stack_end,stack_size;
+#endif
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+#ifdef __GNUC__
+	stack_end = (u32)&_stack_end;
+	stack_start = (u32)&__undef_stack;
+	stack_size=stack_start-stack_end;
+
+	/*Flush stack memory to save return address*/
+	Xil_DCacheFlushRange(stack_end, stack_size);
+#endif
+
+	/* Select cache level 0 and D cache in CSSR */
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+
+#ifdef __GNUC__
+	CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
+#elif defined (__ICCARM__)
+	mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg);
+#else
+	{ volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID);
+	  CsidReg = Reg; }
+#endif
+	/* Determine Cache Size */
+	CacheSize = (CsidReg >> 13U) & 0x1FFU;
+	CacheSize +=1U;
+	CacheSize *=128U;    /* to get number of bytes */
+
+	/* Number of Ways */
+	NumWays = (CsidReg & 0x3ffU) >> 3U;
+	NumWays += 1U;
+
+	/* Get the cacheline size, way size, index size from csidr */
+	LineSize = (CsidReg & 0x07U) + 4U;
+
+	NumSet = CacheSize/NumWays;
+	NumSet /= (0x00000001U << LineSize);
+
+	Way = 0U;
+	Set = 0U;
+
+	/* Invalidate all the cachelines */
+	for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
+		for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
+			C7Reg = Way | Set;
+
+		/* Invalidate by Set/Way */
+#if defined (__GNUC__) || defined (__ICCARM__)
+			asm_cp15_inval_dc_line_sw(C7Reg);
+#else
+			/*mtcp(XREG_CP15_INVAL_DC_LINE_SW, C7Reg), */
+			{ volatile register u32 Reg
+				__asm(XREG_CP15_INVAL_DC_LINE_SW);
+			  Reg = C7Reg; }
+#endif
+			Set += (0x00000001U << LineSize);
+		}
+		Set=0U;
+		Way += 0x40000000U;
+	}
+
+	/* Wait for L1 invalidate to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate a level 1 Data cache line. If the byte specified by the
+* 			address (Addr) is cached by the Data cache, the cacheline
+* 			containing that byte is invalidated. If the cacheline is modified
+* 			(dirty), the modified contents are lost and are NOT written to
+*			system memory before the line is invalidated.
+*
+* @param	adr: 32bit address of the data to be invalidated.
+*
+* @return	None.
+*
+* @note		The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1DCacheInvalidateLine(u32 adr)
+{
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+	mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU)));
+
+	/* Wait for L1 invalidate to complete */
+	dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate the level 1 Data cache for the given address range.
+* 			If the bytes specified by the address range are cached by the Data
+* 			cache, the cachelines containing those bytes are invalidated. If the
+* 			cachelines are modified (dirty), the modified contents are lost and
+* 			NOT written to the system memory before the lines are invalidated.
+*
+* @param	adr: 32bit start address of the range to be invalidated.
+* @param	len: Length of the range to be invalidated in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1DCacheInvalidateRange(u32 adr, u32 len)
+{
+	u32 LocalAddr = adr;
+	const u32 cacheline = 32U;
+	u32 end;
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0U) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = LocalAddr + len;
+		LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+		/* Select cache L0 D-cache in CSSR */
+		mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+		while (LocalAddr < end) {
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+			asm_cp15_inval_dc_line_mva_poc(LocalAddr);
+#else
+			{ volatile register u32 Reg
+				__asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
+			  Reg = LocalAddr; }
+#endif
+			LocalAddr += cacheline;
+		}
+	}
+
+	/* Wait for L1 invalidate to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Flush the level 1 Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		In Cortex A9, there is no cp instruction for flushing
+*			the whole D-cache. Need to flush each line.
+*
+****************************************************************************/
+void Xil_L1DCacheFlush(void)
+{
+	register u32 CsidReg, C7Reg;
+	u32 CacheSize, LineSize, NumWays;
+	u32 Way;
+	u32 WayIndex, Set, SetIndex, NumSet;
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	/* Select cache level 0 and D cache in CSSR */
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+#ifdef __GNUC__
+	CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
+#elif defined (__ICCARM__)
+	mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg);
+#else
+	{ volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID);
+	  CsidReg = Reg; }
+#endif
+
+	/* Determine Cache Size */
+
+	CacheSize = (CsidReg >> 13U) & 0x1FFU;
+	CacheSize +=1U;
+	CacheSize *=128U;    /* to get number of bytes */
+
+	/* Number of Ways */
+	NumWays = (CsidReg & 0x3ffU) >> 3U;
+	NumWays += 1U;
+
+	/* Get the cacheline size, way size, index size from csidr */
+	LineSize = (CsidReg & 0x07U) + 4U;
+
+	NumSet = CacheSize/NumWays;
+	NumSet /= (0x00000001U << LineSize);
+
+	Way = 0U;
+	Set = 0U;
+
+	/* Invalidate all the cachelines */
+	for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
+		for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
+			C7Reg = Way | Set;
+			/* Flush by Set/Way */
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+			asm_cp15_clean_inval_dc_line_sw(C7Reg);
+#else
+			{ volatile register u32 Reg
+				__asm(XREG_CP15_CLEAN_INVAL_DC_LINE_SW);
+			  Reg = C7Reg; }
+#endif
+			Set += (0x00000001U << LineSize);
+		}
+		Set = 0U;
+		Way += 0x40000000U;
+	}
+
+	/* Wait for L1 flush to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Flush a level 1 Data cache line. If the byte specified by the
+*			address (adr) is cached by the Data cache, the cacheline containing
+*			that byte is invalidated. If the cacheline is modified (dirty), the
+* 			entire contents of the cacheline are written to system memory
+*			before the line is invalidated.
+*
+* @param	adr: 32bit address of the data to be flushed.
+*
+* @return	None.
+*
+* @note		The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1DCacheFlushLine(u32 adr)
+{
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+	mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU)));
+
+	/* Wait for L1 flush to complete */
+	dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief	Flush the level 1  Data cache for the given address range.
+* 			If the bytes specified by the address range are cached by the Data
+* 			cache, the cacheline containing those bytes are invalidated. If the
+* 			cachelines are modified (dirty), they are written to system memory
+* 			before the lines are invalidated.
+*
+* @param	adr: 32bit start address of the range to be flushed.
+* @param	len: Length of the range to be flushed in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1DCacheFlushRange(u32 adr, u32 len)
+{
+	u32 LocalAddr = adr;
+	const u32 cacheline = 32U;
+	u32 end;
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0U) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = LocalAddr + len;
+		LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+		/* Select cache L0 D-cache in CSSR */
+		mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+
+		while (LocalAddr < end) {
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+			asm_cp15_clean_inval_dc_line_mva_poc(LocalAddr);
+#else
+			{ volatile register u32 Reg
+				__asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
+			  Reg = LocalAddr; }
+#endif
+			LocalAddr += cacheline;
+		}
+	}
+
+	/* Wait for L1 flush to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Store a level 1  Data cache line. If the byte specified by the
+* 			address (adr) is cached by the Data cache and the cacheline is
+* 			modified (dirty), the entire contents of the cacheline are written
+* 			to system memory. After the store completes, the cacheline is
+*			marked as unmodified (not dirty).
+*
+* @param	Address to be stored.
+*
+* @return	None.
+*
+* @note		The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1DCacheStoreLine(u32 adr)
+{
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+	mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1FU)));
+
+	/* Wait for L1 store to complete */
+	dsb();
+}
+
+
+/****************************************************************************/
+/**
+* @brief	Enable the level 1 instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1ICacheEnable(void)
+{
+	register u32 CtrlReg;
+
+	/* enable caches only if they are disabled */
+#ifdef __GNUC__
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+	mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+#else
+	{ volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
+	  CtrlReg = Reg; }
+#endif
+	if ((CtrlReg & (XREG_CP15_CONTROL_I_BIT)) != 0U) {
+		return;
+	}
+
+	/* invalidate the instruction cache */
+	mtcp(XREG_CP15_INVAL_IC_POU, 0U);
+
+	/* enable the instruction cache */
+	CtrlReg |= (XREG_CP15_CONTROL_I_BIT);
+
+	mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************/
+/**
+* @brief	Disable level 1 the instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1ICacheDisable(void)
+{
+	register u32 CtrlReg;
+
+	dsb();
+
+	/* invalidate the instruction cache */
+	mtcp(XREG_CP15_INVAL_IC_POU, 0U);
+
+	/* disable the instruction cache */
+#ifdef __GNUC__
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+	mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+#else
+	{ volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
+	  CtrlReg = Reg; }
+#endif
+	CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT);
+
+	mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate the entire level 1 instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1ICacheInvalidate(void)
+{
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+	/* invalidate the instruction cache */
+	mtcp(XREG_CP15_INVAL_IC_POU, 0U);
+
+	/* Wait for L1 invalidate to complete */
+	dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate a level 1  instruction cache line. If the instruction
+*			specified by the address is cached by the instruction cache, the
+*			cacheline containing that instruction is invalidated.
+*
+* @param	adr: 32bit address of the instruction to be invalidated.
+*
+* @return	None.
+*
+* @note		The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1ICacheInvalidateLine(u32 adr)
+{
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+	mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1FU)));
+
+	/* Wait for L1 invalidate to complete */
+	dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate the level 1 instruction cache for the given address
+* 			range. If the instrucions specified by the address range are cached
+*			by the instruction cache, the cacheline containing those bytes are
+*			invalidated.
+*
+* @param	adr: 32bit start address of the range to be invalidated.
+* @param	len: Length of the range to be invalidated in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1ICacheInvalidateRange(u32 adr, u32 len)
+{
+	u32 LocalAddr = adr;
+	const u32 cacheline = 32U;
+	u32 end;
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0U) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = LocalAddr + len;
+		LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+		/* Select cache L0 I-cache in CSSR */
+		mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+
+		while (LocalAddr < end) {
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+			asm_cp15_inval_ic_line_mva_pou(LocalAddr);
+#else
+			{ volatile register u32 Reg
+				__asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
+			  Reg = LocalAddr; }
+#endif
+			LocalAddr += cacheline;
+		}
+	}
+
+	/* Wait for L1 invalidate to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+#ifndef USE_AMP
+/****************************************************************************/
+/**
+* @brief	Enable the L2 cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L2CacheEnable(void)
+{
+	register u32 L2CCReg;
+
+	L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+
+	/* only enable if L2CC is currently disabled */
+	if ((L2CCReg & 0x01U) == 0U) {
+		/* set up the way size and latencies */
+		L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
+				   XPS_L2CC_AUX_CNTRL_OFFSET);
+		L2CCReg &= XPS_L2CC_AUX_REG_ZERO_MASK;
+		L2CCReg |= XPS_L2CC_AUX_REG_DEFAULT_MASK;
+		Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_AUX_CNTRL_OFFSET,
+			  L2CCReg);
+		Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_TAG_RAM_CNTRL_OFFSET,
+			  XPS_L2CC_TAG_RAM_DEFAULT_MASK);
+		Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DATA_RAM_CNTRL_OFFSET,
+			  XPS_L2CC_DATA_RAM_DEFAULT_MASK);
+
+		/* Clear the pending interrupts */
+		L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
+				   XPS_L2CC_ISR_OFFSET);
+		Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_IAR_OFFSET, L2CCReg);
+
+		Xil_L2CacheInvalidate();
+		/* Enable the L2CC */
+		L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
+				   XPS_L2CC_CNTRL_OFFSET);
+		Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET,
+			  (L2CCReg | (0x01U)));
+
+        Xil_L2CacheSync();
+        /* synchronize the processor */
+	    dsb();
+
+    }
+}
+
+/****************************************************************************/
+/**
+* @brief	Disable the L2 cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L2CacheDisable(void)
+{
+    register u32 L2CCReg;
+
+	L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+
+    if((L2CCReg & 0x1U) != 0U) {
+
+        /* Clean and Invalidate L2 Cache */
+        Xil_L2CacheFlush();
+
+	    /* Disable the L2CC */
+	L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+	    Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET,
+		      (L2CCReg & (~0x01U)));
+		/* Wait for the cache operations to complete */
+
+		dsb();
+    }
+}
+
+/*****************************************************************************/
+/**
+* @brief	Invalidate the entire level 2 cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L2CacheInvalidate(void)
+{
+	#ifdef __GNUC__
+	u32 stack_start,stack_end,stack_size;
+	stack_end = (u32)&_stack_end;
+	stack_start = (u32)&__undef_stack;
+	stack_size=stack_start-stack_end;
+
+	/*Flush stack memory to save return address*/
+	Xil_DCacheFlushRange(stack_end, stack_size);
+	#endif
+	u32 ResultDCache;
+	/* Invalidate the caches */
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET,
+		  0x0000FFFFU);
+	ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET)
+							& 0x0000FFFFU;
+	while(ResultDCache != (u32)0U) {
+		ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET)
+							& 0x0000FFFFU;
+	}
+
+	/* Wait for the invalidate to complete */
+	Xil_L2CacheSync();
+
+	/* synchronize the processor */
+	dsb();
+}
+
+/*****************************************************************************/
+/**
+* @brief	Invalidate a level 2 cache line. If the byte specified by the
+*			address (adr) is cached by the Data cache, the cacheline containing
+*			that byte is invalidated. If the cacheline is modified (dirty),
+*			the modified contents are lost and are NOT written to system memory
+*			before the line is invalidated.
+*
+* @param	adr: 32bit address of the data/instruction to be invalidated.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L2CacheInvalidateLine(u32 adr)
+{
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, (u32)adr);
+	/* synchronize the processor */
+	dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate the level 2 cache for the given address range.
+* 			If the bytes specified by the address range are cached by the L2
+* 			cache, the cacheline containing those bytes are invalidated. If the
+* 			cachelines are modified (dirty), the modified contents are lost and
+* 			are NOT written to system memory before the lines are invalidated.
+*
+* @param	adr: 32bit start address of the range to be invalidated.
+* @param	len: Length of the range to be invalidated in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L2CacheInvalidateRange(u32 adr, u32 len)
+{
+	u32 LocalAddr = adr;
+	const u32 cacheline = 32U;
+	u32 end;
+	volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+				    XPS_L2CC_CACHE_INVLD_PA_OFFSET);
+
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0U) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = LocalAddr + len;
+		LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+		/* Disable Write-back and line fills */
+		Xil_L2WriteDebugCtrl(0x3U);
+
+		while (LocalAddr < end) {
+			*L2CCOffset = LocalAddr;
+			Xil_L2CacheSync();
+			LocalAddr += cacheline;
+		}
+
+		/* Enable Write-back and line fills */
+		Xil_L2WriteDebugCtrl(0x0U);
+	}
+
+	/* synchronize the processor */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Flush the entire level 2 cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L2CacheFlush(void)
+{
+	u32 ResultL2Cache;
+
+	/* Flush the caches */
+
+	/* Disable Write-back and line fills */
+	Xil_L2WriteDebugCtrl(0x3U);
+
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET,
+		  0x0000FFFFU);
+	ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET)
+							& 0x0000FFFFU;
+
+	while(ResultL2Cache != (u32)0U) {
+		ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET)
+									& 0x0000FFFFU;
+	}
+
+	Xil_L2CacheSync();
+	/* Enable Write-back and line fills */
+	Xil_L2WriteDebugCtrl(0x0U);
+
+	/* synchronize the processor */
+	dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief	Flush a level 2 cache line. If the byte specified by the address
+* 			(adr) is cached by the L2 cache, the cacheline containing that
+* 			byte is invalidated. If the cacheline is modified (dirty), the
+* 			entire contents of the cacheline are written to system memory
+* 			before the line is invalidated.
+*
+* @param	adr: 32bit address of the data/instruction to be flushed.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L2CacheFlushLine(u32 adr)
+{
+#ifdef CONFIG_PL310_ERRATA_588369
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr);
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, adr);
+#else
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_PA_OFFSET, adr);
+#endif
+	/* synchronize the processor */
+	dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief	Flush the level 2 cache for the given address range.
+* 			If the bytes specified by the address range are cached by the L2
+* 			cache, the cacheline containing those bytes are invalidated. If the
+* 			cachelines are modified (dirty), they are written to the system
+* 			memory before the lines are invalidated.
+*
+* @param	adr: 32bit start address of the range to be flushed.
+* @param	len: Length of the range to be flushed in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L2CacheFlushRange(u32 adr, u32 len)
+{
+	u32 LocalAddr = adr;
+	const u32 cacheline = 32U;
+	u32 end;
+	volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+				    XPS_L2CC_CACHE_INV_CLN_PA_OFFSET);
+
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+	if (len != 0U) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = LocalAddr + len;
+		LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+		/* Disable Write-back and line fills */
+		Xil_L2WriteDebugCtrl(0x3U);
+
+		while (LocalAddr < end) {
+			*L2CCOffset = LocalAddr;
+			Xil_L2CacheSync();
+			LocalAddr += cacheline;
+		}
+
+		/* Enable Write-back and line fills */
+		Xil_L2WriteDebugCtrl(0x0U);
+	}
+	/* synchronize the processor */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Store a level 2 cache line. If the byte specified by the address
+* 			(adr) is cached by the L2 cache and the cacheline is modified
+* 			(dirty), the entire contents of the cacheline are written to
+*			system memory. After the store completes, the cacheline is marked
+*			as unmodified (not dirty).
+*
+* @param	adr: 32bit address of the data/instruction to be stored.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L2CacheStoreLine(u32 adr)
+{
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr);
+	/* synchronize the processor */
+	dsb();
+}
+#endif
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_cache.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_cache.h
new file mode 100644
index 0000000000000000000000000000000000000000..b6614d5f992709379ce97da6e8be0cfb9eb80d8b
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_cache.h
@@ -0,0 +1,121 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.h
+*
+* @addtogroup a9_cache_apis Cortex A9 Processor Cache Functions
+*
+* Cache functions provide access to cache related operations such as flush
+* and invalidate for instruction and data caches. It gives option to perform
+* the cache operations on a single cacheline, a range of memory and an entire
+* cache.
+*
+* @{
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  01/29/10 First release
+* 3.04a sdm  01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
+*		      APIs.
+* </pre>
+*
+******************************************************************************/
+#ifndef XIL_CACHE_H
+#define XIL_CACHE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __GNUC__
+
+#define asm_cp15_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+			XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+			XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \
+			XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
+
+#define asm_cp15_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
+			XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
+			XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
+
+#elif defined (__ICCARM__)
+
+#define asm_cp15_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
+			XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
+			XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_inval_ic_line_mva_pou(param) __asm volatile ("mcr " \
+			XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
+
+#define asm_cp15_inval_dc_line_sw(param) __asm volatile ("mcr " \
+			XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_sw(param) __asm volatile ("mcr " \
+			XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
+
+#endif
+
+void Xil_DCacheEnable(void);
+void Xil_DCacheDisable(void);
+void Xil_DCacheInvalidate(void);
+void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
+void Xil_DCacheFlush(void);
+void Xil_DCacheFlushRange(INTPTR adr, u32 len);
+
+void Xil_ICacheEnable(void);
+void Xil_ICacheDisable(void);
+void Xil_ICacheInvalidate(void);
+void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_cache_apis".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_cache.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_cache.o
new file mode 100644
index 0000000000000000000000000000000000000000..fcdf1b4eea2812e156f77c4c6bd2bfa4b75aef0d
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_cache.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_cache_l.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_cache_l.h
new file mode 100644
index 0000000000000000000000000000000000000000..fa92c6b1c4087b05b80e256770a5c0d023d99fe2
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_cache_l.h
@@ -0,0 +1,100 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_l.h
+*
+* Contains L1 and L2 specific functions for the ARM cache functionality
+* used by xcache.c. This functionality is being made available here for
+* more sophisticated users.
+*
+* @addtogroup a9_cache_apis
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  01/24/10 First release
+* </pre>
+*
+******************************************************************************/
+#ifndef XIL_CACHE_MACH_H
+#define XIL_CACHE_MACH_H
+
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_DCacheInvalidateLine(u32 adr);
+void Xil_DCacheFlushLine(u32 adr);
+void Xil_DCacheStoreLine(u32 adr);
+void Xil_ICacheInvalidateLine(u32 adr);
+
+void Xil_L1DCacheEnable(void);
+void Xil_L1DCacheDisable(void);
+void Xil_L1DCacheInvalidate(void);
+void Xil_L1DCacheInvalidateLine(u32 adr);
+void Xil_L1DCacheInvalidateRange(u32 adr, u32 len);
+void Xil_L1DCacheFlush(void);
+void Xil_L1DCacheFlushLine(u32 adr);
+void Xil_L1DCacheFlushRange(u32 adr, u32 len);
+void Xil_L1DCacheStoreLine(u32 adr);
+
+void Xil_L1ICacheEnable(void);
+void Xil_L1ICacheDisable(void);
+void Xil_L1ICacheInvalidate(void);
+void Xil_L1ICacheInvalidateLine(u32 adr);
+void Xil_L1ICacheInvalidateRange(u32 adr, u32 len);
+
+void Xil_L2CacheEnable(void);
+void Xil_L2CacheDisable(void);
+void Xil_L2CacheInvalidate(void);
+void Xil_L2CacheInvalidateLine(u32 adr);
+void Xil_L2CacheInvalidateRange(u32 adr, u32 len);
+void Xil_L2CacheFlush(void);
+void Xil_L2CacheFlushLine(u32 adr);
+void Xil_L2CacheFlushRange(u32 adr, u32 len);
+void Xil_L2CacheStoreLine(u32 adr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_cache_apis".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_cache_vxworks.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_cache_vxworks.h
new file mode 100644
index 0000000000000000000000000000000000000000..6e8cfa75fbfaa26744b0f9f9bf3114753dc9b5f8
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_cache_vxworks.h
@@ -0,0 +1,93 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_vxworks.h
+*
+* Contains the cache related functions for VxWorks that is wrapped by
+* xil_cache.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  12/11/09 Initial release
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_CACHE_VXWORKS_H
+#define XIL_CACHE_VXWORKS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "vxWorks.h"
+#include "vxLib.h"
+#include "sysLibExtra.h"
+#include "cacheLib.h"
+
+#if (CPU_FAMILY==PPC)
+
+#define Xil_DCacheEnable()		cacheEnable(DATA_CACHE)
+
+#define Xil_DCacheDisable()		cacheDisable(DATA_CACHE)
+
+#define Xil_DCacheInvalidateRange(Addr, Len) \
+		cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_DCacheFlushRange(Addr, Len) \
+		cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_ICacheEnable()		cacheEnable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheDisable()		cacheDisable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheInvalidateRange(Addr, Len) \
+		cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
+
+
+#else
+#error "Unknown processor / architecture. Must be PPC for VxWorks."
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_errata.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_errata.h
new file mode 100644
index 0000000000000000000000000000000000000000..800fcd562e8e32ec28ce4494ce37dcdf167396f8
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_errata.h
@@ -0,0 +1,127 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_errata.h
+*
+* @addtogroup a9_errata Cortex A9 Processor and pl310 Errata Support
+* @{
+* Various ARM errata are handled in the standalone BSP. The implementation for
+* errata handling follows ARM guidelines and is based on the open source Linux
+* support for these errata.
+*
+* @note
+* The errata handling is enabled by default. To disable handling of all the
+* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
+* disable errata on a per-erratum basis, un-define relevant macros in
+* xil_errata.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a srt  04/18/13 First release
+* </pre>
+*
+******************************************************************************/
+#ifndef XIL_ERRATA_H
+#define XIL_ERRATA_H
+
+/**
+ * @name errata_definitions
+ *
+ * The errata conditions handled in the standalone BSP are listed below
+ * @{
+ */
+
+#define ENABLE_ARM_ERRATA 1
+
+#ifdef ENABLE_ARM_ERRATA
+
+/**
+ *  Errata No: 	 742230
+ *  Description: DMB operation may be faulty
+ */
+#define CONFIG_ARM_ERRATA_742230 1
+
+/**
+ *  Errata No: 	 743622
+ *  Description: Faulty hazard checking in the Store Buffer may lead
+ *	         	 to data corruption.
+ */
+#define CONFIG_ARM_ERRATA_743622 1
+
+/**
+ *  Errata No: 	 775420
+ *  Description: A data cache maintenance operation which aborts,
+ *		 		 might lead to deadlock
+ */
+#define CONFIG_ARM_ERRATA_775420 1
+
+/**
+ *  Errata No: 	 794073
+ *  Description: Speculative instruction fetches with MMU disabled
+ *               might not comply with architectural requirements
+ */
+#define CONFIG_ARM_ERRATA_794073 1
+
+
+/** PL310 L2 Cache Errata */
+
+/**
+ *  Errata No: 	 588369
+ *  Description: Clean & Invalidate maintenance operations do not
+ *	   	 		 invalidate clean lines
+ */
+#define CONFIG_PL310_ERRATA_588369 1
+
+/**
+ *  Errata No: 	 727915
+ *  Description: Background Clean and Invalidate by Way operation
+ *		 can cause data corruption
+ */
+#define CONFIG_PL310_ERRATA_727915 1
+
+/**
+ *  Errata No: 	 753970
+ *  Description: Cache sync operation may be faulty
+ */
+#define CONFIG_PL310_ERRATA_753970 1
+/*@}*/
+#endif  /* ENABLE_ARM_ERRATA */
+
+#endif  /* XIL_ERRATA_H */
+/**
+* @} End of "addtogroup a9_errata".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_exception.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_exception.c
new file mode 100644
index 0000000000000000000000000000000000000000..a1dfdf6eb8a55c1c1613ef50dd4e68cbb032f954
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_exception.c
@@ -0,0 +1,332 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xil_exception.c
+*
+* This file contains low-level driver functions for the Cortex A53,A9,R5 exception
+* Handler.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.2	pkp  	 28/05/15 First release
+* 6.0   mus      27/07/16 Consolidated exceptions for a53,a9 and r5
+*                         processors and added Xil_UndefinedExceptionHandler
+*                         for a53 32 bit and r5 as well.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xpseudo_asm.h"
+#include "xdebug.h"
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+typedef struct {
+	Xil_ExceptionHandler Handler;
+	void *Data;
+} XExc_VectorTableEntry;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+static void Xil_ExceptionNullHandler(void *Data);
+/************************** Variable Definitions *****************************/
+/*
+ * Exception vector table to store handlers for each exception vector.
+ */
+#if defined (__aarch64__)
+XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
+{
+        {Xil_ExceptionNullHandler, NULL},
+        {Xil_SyncAbortHandler, NULL},
+        {Xil_ExceptionNullHandler, NULL},
+        {Xil_ExceptionNullHandler, NULL},
+        {Xil_SErrorAbortHandler, NULL},
+
+};
+#else
+XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
+{
+	{Xil_ExceptionNullHandler, NULL},
+	{Xil_UndefinedExceptionHandler, NULL},
+	{Xil_ExceptionNullHandler, NULL},
+	{Xil_PrefetchAbortHandler, NULL},
+	{Xil_DataAbortHandler, NULL},
+	{Xil_ExceptionNullHandler, NULL},
+	{Xil_ExceptionNullHandler, NULL},
+};
+#endif
+#if !defined (__aarch64__)
+u32 DataAbortAddr;       /* Address of instruction causing data abort */
+u32 PrefetchAbortAddr;   /* Address of instruction causing prefetch abort */
+u32 UndefinedExceptionAddr;   /* Address of instruction causing Undefined
+							     exception */
+#endif
+
+/*****************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* This function is a stub Handler that is the default Handler that gets called
+* if the application has not setup a Handler for a specific  exception. The
+* function interface has to match the interface specified for a Handler even
+* though none of the arguments are used.
+*
+* @param	Data is unused by this function.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void Xil_ExceptionNullHandler(void *Data)
+{
+	(void) Data;
+DieLoop: goto DieLoop;
+}
+
+/****************************************************************************/
+/**
+* @brief	The function is a common API used to initialize exception handlers
+*			across all supported arm processors. For ARM Cortex-A53, Cortex-R5,
+*			and Cortex-A9, the exception handlers are being initialized
+*			statically and this function does not do anything.
+* 			However, it is still present to take care of backward compatibility
+*			issues (in earlier versions of BSPs, this API was being used to
+*			initialize exception handlers).
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xil_ExceptionInit(void)
+{
+	return;
+}
+
+/*****************************************************************************/
+/**
+* @brief	Register a handler for a specific exception. This handler is being
+*			called when the processor encounters the specified exception.
+*
+* @param	exception_id contains the ID of the exception source and should
+*			be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+*			See xil_exception.h for further information.
+* @param	Handler to the Handler for that exception.
+* @param	Data is a reference to Data that will be passed to the
+*			Handler when it gets called.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ExceptionRegisterHandler(u32 Exception_id,
+				    Xil_ExceptionHandler Handler,
+				    void *Data)
+{
+	XExc_VectorTable[Exception_id].Handler = Handler;
+	XExc_VectorTable[Exception_id].Data = Data;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief	Removes the Handler for a specific exception Id. The stub Handler
+*			is then registered for this exception Id.
+*
+* @param	exception_id contains the ID of the exception source and should
+*			be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+*			See xil_exception.h for further information.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ExceptionRemoveHandler(u32 Exception_id)
+{
+	Xil_ExceptionRegisterHandler(Exception_id,
+				       Xil_ExceptionNullHandler,
+				       NULL);
+}
+
+#if defined (__aarch64__)
+/*****************************************************************************/
+/**
+*
+* Default Synchronous abort handler which prints a debug message on console if
+* Debug flag is enabled
+*
+* @param        None
+*
+* @return       None.
+*
+* @note         None.
+*
+****************************************************************************/
+
+void Xil_SyncAbortHandler(void *CallBackRef){
+	(void) CallBackRef;
+	xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
+	while(1) {
+		;
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Default SError abort handler which prints a debug message on console if
+* Debug flag is enabled
+*
+* @param        None
+*
+* @return       None.
+*
+* @note         None.
+*
+****************************************************************************/
+void Xil_SErrorAbortHandler(void *CallBackRef){
+	(void) CallBackRef;
+	xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
+	while(1) {
+		;
+	}
+}
+#else
+/*****************************************************************************/
+/*
+*
+* Default Data abort handler which prints data fault status register through
+* which information about data fault can be acquired
+*
+* @param	None
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+
+void Xil_DataAbortHandler(void *CallBackRef){
+	(void) CallBackRef;
+#ifdef DEBUG
+	u32 FaultStatus;
+
+        xdbg_printf(XDBG_DEBUG_ERROR, "Data abort \n");
+        #ifdef __GNUC__
+	FaultStatus = mfcp(XREG_CP15_DATA_FAULT_STATUS);
+	    #elif defined (__ICCARM__)
+	        mfcp(XREG_CP15_DATA_FAULT_STATUS,FaultStatus);
+	    #else
+	        { volatile register u32 Reg __asm(XREG_CP15_DATA_FAULT_STATUS);
+	        FaultStatus = Reg; }
+	    #endif
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register  %x\n",FaultStatus);
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instrcution causing Data abort %x\n",DataAbortAddr);
+#endif
+	while(1) {
+		;
+	}
+}
+
+/*****************************************************************************/
+/*
+*
+* Default Prefetch abort handler which prints prefetch fault status register through
+* which information about instruction prefetch fault can be acquired
+*
+* @param	None
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_PrefetchAbortHandler(void *CallBackRef){
+	(void) CallBackRef;
+#ifdef DEBUG
+	u32 FaultStatus;
+
+    xdbg_printf(XDBG_DEBUG_ERROR, "Prefetch abort \n");
+        #ifdef __GNUC__
+	FaultStatus = mfcp(XREG_CP15_INST_FAULT_STATUS);
+	    #elif defined (__ICCARM__)
+			mfcp(XREG_CP15_INST_FAULT_STATUS,FaultStatus);
+	    #else
+			{ volatile register u32 Reg __asm(XREG_CP15_INST_FAULT_STATUS);
+			FaultStatus = Reg; }
+		#endif
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register  %x\n",FaultStatus);
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instrcution causing Prefetch abort %x\n",PrefetchAbortAddr);
+#endif
+	while(1) {
+		;
+	}
+}
+/*****************************************************************************/
+/*
+*
+* Default undefined exception handler which prints address of the undefined
+* instruction if debug prints are enabled
+*
+* @param	None
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_UndefinedExceptionHandler(void *CallBackRef){
+	(void) CallBackRef;
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Address of the undefined instruction %x\n",UndefinedExceptionAddr);
+	while(1) {
+		;
+	}
+}
+#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_exception.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_exception.h
new file mode 100644
index 0000000000000000000000000000000000000000..ad48222058678dde33905835a16816fb2b834dea
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_exception.h
@@ -0,0 +1,256 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_exception.h
+*
+* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.
+* For exception related functions that can be used across all Xilinx supported
+* processors, please use xil_exception.h.
+*
+* @addtogroup arm_exception_apis ARM Processor Exception Handling
+* @{
+* ARM processors specific exception related APIs for cortex A53,A9 and R5 can
+* utilized for enabling/disabling IRQ, registering/removing handler for
+* exceptions or initializing exception vector table with null handler.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.2	pkp  	 28/05/15 First release
+* 6.0   mus      27/07/16 Consolidated file for a53,a9 and r5 processors
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
+#define XIL_EXCEPTION_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions ****************************/
+
+#define XIL_EXCEPTION_FIQ	XREG_CPSR_FIQ_ENABLE
+#define XIL_EXCEPTION_IRQ	XREG_CPSR_IRQ_ENABLE
+#define XIL_EXCEPTION_ALL	(XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
+
+#define XIL_EXCEPTION_ID_FIRST			0U
+#if defined (__aarch64__)
+#define XIL_EXCEPTION_ID_SYNC_INT		1U
+#define XIL_EXCEPTION_ID_IRQ_INT		2U
+#define XIL_EXCEPTION_ID_FIQ_INT		3U
+#define XIL_EXCEPTION_ID_SERROR_ABORT_INT		4U
+#define XIL_EXCEPTION_ID_LAST			5U
+#else
+#define XIL_EXCEPTION_ID_RESET			0U
+#define XIL_EXCEPTION_ID_UNDEFINED_INT		1U
+#define XIL_EXCEPTION_ID_SWI_INT		2U
+#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT	3U
+#define XIL_EXCEPTION_ID_DATA_ABORT_INT		4U
+#define XIL_EXCEPTION_ID_IRQ_INT		5U
+#define XIL_EXCEPTION_ID_FIQ_INT		6U
+#define XIL_EXCEPTION_ID_LAST			6U
+#endif
+
+/*
+ * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
+ */
+#define XIL_EXCEPTION_ID_INT	XIL_EXCEPTION_ID_IRQ_INT
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef is the exception handler function.
+ */
+typedef void (*Xil_ExceptionHandler)(void *data);
+typedef void (*Xil_InterruptHandler)(void *data);
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* @brief	Enable Exceptions.
+*
+* @param	Mask: Value for enabling the exceptions.
+*
+* @return	None.
+*
+* @note		If bit is 0, exception is enabled.
+*			C-Style signature: void Xil_ExceptionEnableMask(Mask)
+*
+******************************************************************************/
+#if defined (__GNUC__) || defined (__ICCARM__)
+#define Xil_ExceptionEnableMask(Mask)	\
+		mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionEnableMask(Mask)	\
+		{								\
+		  register u32 Reg __asm("cpsr"); \
+		  mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
+		}
+#endif
+/****************************************************************************/
+/**
+* @brief	Enable the IRQ exception.
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+#define Xil_ExceptionEnable() \
+		Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
+
+/****************************************************************************/
+/**
+* @brief	Disable Exceptions.
+*
+* @param	Mask: Value for disabling the exceptions.
+*
+* @return	None.
+*
+* @note		If bit is 1, exception is disabled.
+*			C-Style signature: Xil_ExceptionDisableMask(Mask)
+*
+******************************************************************************/
+#if defined (__GNUC__) || defined (__ICCARM__)
+#define Xil_ExceptionDisableMask(Mask)	\
+		mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionDisableMask(Mask)	\
+		{									\
+		  register u32 Reg __asm("cpsr"); \
+		  mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
+		}
+#endif
+/****************************************************************************/
+/**
+* Disable the IRQ exception.
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+#define Xil_ExceptionDisable() \
+		Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
+
+#if !defined (__aarch64__) && !defined (ARMA53_32)
+/****************************************************************************/
+/**
+* @brief	Enable nested interrupts by clearing the I and F bits in CPSR. This
+* 			API is defined for cortex-a9 and cortex-r5.
+*
+* @return   None.
+*
+* @note     This macro is supposed to be used from interrupt handlers. In the
+*			interrupt handler the interrupts are disabled by default (I and F
+*			are 1). To allow nesting of interrupts, this macro should be
+*			used. It clears the I and F bits by changing the ARM mode to
+*			system mode. Once these bits are cleared and provided the
+*			preemption of interrupt conditions are met in the GIC, nesting of
+*			interrupts will start happening.
+*			Caution: This macro must be used with caution. Before calling this
+*			macro, the user must ensure that the source of the current IRQ
+*			is appropriately cleared. Otherwise, as soon as we clear the I and
+*			F bits, there can be an infinite loop of interrupts with an
+*			eventual crash (all the stack space getting consumed).
+******************************************************************************/
+#define Xil_EnableNestedInterrupts() \
+		__asm__ __volatile__ ("stmfd   sp!, {lr}"); \
+		__asm__ __volatile__ ("mrs     lr, spsr");  \
+		__asm__ __volatile__ ("stmfd   sp!, {lr}"); \
+		__asm__ __volatile__ ("msr     cpsr_c, #0x1F"); \
+		__asm__ __volatile__ ("stmfd   sp!, {lr}");
+
+/****************************************************************************/
+/**
+* @brief	Disable the nested interrupts by setting the I and F bits. This API
+*			is defined for cortex-a9 and cortex-r5.
+*
+* @return   None.
+*
+* @note     This macro is meant to be called in the interrupt service routines.
+*			This macro cannot be used independently. It can only be used when
+*			nesting of interrupts have been enabled by using the macro
+*			Xil_EnableNestedInterrupts(). In a typical flow, the user first
+*			calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
+*			point. The user then must call this macro before exiting the interrupt
+*			service routine. This macro puts the ARM back in IRQ/FIQ mode and
+*			hence sets back the I and F bits.
+******************************************************************************/
+#define Xil_DisableNestedInterrupts() \
+		__asm__ __volatile__ ("ldmfd   sp!, {lr}");   \
+		__asm__ __volatile__ ("msr     cpsr_c, #0x92"); \
+		__asm__ __volatile__ ("ldmfd   sp!, {lr}"); \
+		__asm__ __volatile__ ("msr     spsr_cxsf, lr"); \
+		__asm__ __volatile__ ("ldmfd   sp!, {lr}"); \
+
+#endif
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
+					 Xil_ExceptionHandler Handler,
+					 void *Data);
+
+extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
+
+extern void Xil_ExceptionInit(void);
+#if defined (__aarch64__)
+void Xil_SyncAbortHandler(void *CallBackRef);
+void Xil_SErrorAbortHandler(void *CallBackRef);
+#else
+extern void Xil_DataAbortHandler(void *CallBackRef);
+extern void Xil_PrefetchAbortHandler(void *CallBackRef);
+extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_EXCEPTION_H */
+/**
+* @} End of "addtogroup arm_exception_apis".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_exception.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_exception.o
new file mode 100644
index 0000000000000000000000000000000000000000..c9ee1278191466d7e4b10eb8587e099fcda96983
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_exception.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_hal.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_hal.h
new file mode 100644
index 0000000000000000000000000000000000000000..d4434d07fa748457f2f476ebf82f9f8b20c93c91
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_hal.h
@@ -0,0 +1,61 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_hal.h
+*
+* Contains all the HAL header files.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/28/09 Initial release
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_HAL_H
+#define XIL_HAL_H
+
+#include "xil_cache.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xil_types.h"
+
+#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_io.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_io.c
new file mode 100644
index 0000000000000000000000000000000000000000..90bfc81dc190a506078fa5ec12c27db7c466a0a1
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_io.c
@@ -0,0 +1,102 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.c
+*
+* Contains I/O functions for memory-mapped or non-memory-mapped I/O
+* architectures.
+*
+* @note
+*
+* This file contains architecture-dependent code.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* </pre>
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/*****************************************************************************/
+/**
+*
+* @brief    Perform a 16-bit endian converion.
+*
+* @param	Data: 16 bit value to be converted
+*
+* @return	16 bit Data with converted endianess
+*
+******************************************************************************/
+u16 Xil_EndianSwap16(u16 Data)
+{
+	return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Perform a 32-bit endian converion.
+*
+* @param	Data: 32 bit value to be converted
+*
+* @return	32 bit data with converted endianess
+*
+******************************************************************************/
+u32 Xil_EndianSwap32(u32 Data)
+{
+	u16 LoWord;
+	u16 HiWord;
+
+	/* get each of the half words from the 32 bit word */
+
+	LoWord = (u16) (Data & 0x0000FFFFU);
+	HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
+
+	/* byte swap each of the 16 bit half words */
+
+	LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
+	HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
+
+	/* swap the half words before returning the value */
+
+	return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_io.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_io.h
new file mode 100644
index 0000000000000000000000000000000000000000..99bf4d05d92aff0610e8e442f9183c030d53f523
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_io.h
@@ -0,0 +1,345 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.h
+*
+* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
+*
+* The xil_io.h file contains the interface for the general I/O component, which
+* encapsulates the Input/Output functions for the processors that do not
+* require any special I/O handling.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 6.00  mus      08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
+*                         ARM processors
+* </pre>
+******************************************************************************/
+
+#ifndef XIL_IO_H           /* prevent circular inclusions */
+#define XIL_IO_H           /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_printf.h"
+
+#if defined (__MICROBLAZE__)
+#include "mb_interface.h"
+#else
+#include "xpseudo_asm.h"
+#endif
+
+/************************** Function Prototypes ******************************/
+u16 Xil_EndianSwap16(u16 Data);
+u32 Xil_EndianSwap32(u32 Data);
+#ifdef ENABLE_SAFETY
+extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
+#endif
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#if defined __GNUC__
+#if defined (__MICROBLAZE__)
+#  define INST_SYNC		mbar(0)
+#  define DATA_SYNC		mbar(1)
+# else
+#  define SYNCHRONIZE_IO	dmb()
+#  define INST_SYNC		isb()
+#  define DATA_SYNC		dsb()
+# endif
+#else
+# define SYNCHRONIZE_IO
+# define INST_SYNC
+# define DATA_SYNC
+# define INST_SYNC
+# define DATA_SYNC
+#endif
+
+#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
+#define INLINE inline
+#else
+#define INLINE __inline
+#endif
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an input operation for a memory location by reading
+*           from the specified address and returning the 8 bit Value read from
+*            that address.
+*
+* @param	Addr: contains the address to perform the input operation
+*
+* @return	The 8 bit Value read from the specified input address.
+
+*
+******************************************************************************/
+static INLINE u8 Xil_In8(UINTPTR Addr)
+{
+	return *(volatile u8 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an input operation for a memory location by reading from
+*           the specified address and returning the 16 bit Value read from that
+*           address.
+*
+* @param	Addr: contains the address to perform the input operation
+*
+* @return	The 16 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u16 Xil_In16(UINTPTR Addr)
+{
+	return *(volatile u16 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an input operation for a memory location by
+*           reading from the specified address and returning the 32 bit Value
+*           read  from that address.
+*
+* @param	Addr: contains the address to perform the input operation
+*
+* @return	The 32 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u32 Xil_In32(UINTPTR Addr)
+{
+	return *(volatile u32 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief     Performs an input operation for a memory location by reading the
+*            64 bit Value read  from that address.
+*
+*
+* @param	Addr: contains the address to perform the input operation
+*
+* @return	The 64 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u64 Xil_In64(UINTPTR Addr)
+{
+	return *(volatile u64 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an output operation for an memory location by
+*           writing the 8 bit Value to the the specified address.
+*
+* @param	Addr: contains the address to perform the output operation
+* @param	Value: contains the 8 bit Value to be written at the specified
+*           address.
+*
+* @return	None.
+*
+******************************************************************************/
+static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
+{
+	volatile u8 *LocalAddr = (volatile u8 *)Addr;
+	*LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an output operation for a memory location by writing the
+*            16 bit Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+* @param	Value contains the Value to be written at the specified address.
+*
+* @return	None.
+*
+******************************************************************************/
+static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
+{
+	volatile u16 *LocalAddr = (volatile u16 *)Addr;
+	*LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an output operation for a memory location by writing the
+*           32 bit Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+* @param	Value contains the 32 bit Value to be written at the specified
+*           address.
+*
+* @return	None.
+*
+******************************************************************************/
+static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
+{
+#ifndef ENABLE_SAFETY
+	volatile u32 *LocalAddr = (volatile u32 *)Addr;
+	*LocalAddr = Value;
+#else
+	XStl_RegUpdate(Addr, Value);
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an output operation for a memory location by writing the
+*           64 bit Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+* @param	Value contains 64 bit Value to be written at the specified address.
+*
+* @return	None.
+*
+******************************************************************************/
+static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
+{
+	volatile u64 *LocalAddr = (volatile u64 *)Addr;
+	*LocalAddr = Value;
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+# define Xil_In16LE	Xil_In16
+# define Xil_In32LE	Xil_In32
+# define Xil_Out16LE	Xil_Out16
+# define Xil_Out32LE	Xil_Out32
+# define Xil_Htons	Xil_EndianSwap16
+# define Xil_Htonl	Xil_EndianSwap32
+# define Xil_Ntohs	Xil_EndianSwap16
+# define Xil_Ntohl	Xil_EndianSwap32
+# else
+# define Xil_In16BE	Xil_In16
+# define Xil_In32BE	Xil_In32
+# define Xil_Out16BE	Xil_Out16
+# define Xil_Out32BE	Xil_Out32
+# define Xil_Htons(Data) (Data)
+# define Xil_Htonl(Data) (Data)
+# define Xil_Ntohs(Data) (Data)
+# define Xil_Ntohl(Data) (Data)
+#endif
+#else
+# define Xil_In16LE	Xil_In16
+# define Xil_In32LE	Xil_In32
+# define Xil_Out16LE	Xil_Out16
+# define Xil_Out32LE	Xil_Out32
+# define Xil_Htons	Xil_EndianSwap16
+# define Xil_Htonl	Xil_EndianSwap32
+# define Xil_Ntohs	Xil_EndianSwap16
+# define Xil_Ntohl	Xil_EndianSwap32
+#endif
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#else
+static INLINE u16 Xil_In16LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#endif
+{
+	u16 value = Xil_In16(Addr);
+	return Xil_EndianSwap16(value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#else
+static INLINE u32 Xil_In32LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#endif
+{
+	u16 value = Xil_In32(Addr);
+	return Xil_EndianSwap32(value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#else
+static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
+#endif
+#else
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#endif
+{
+	Value = Xil_EndianSwap16(Value);
+	Xil_Out16(Addr, Value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#else
+static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
+#endif
+#else
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#endif
+{
+	Value = Xil_EndianSwap32(Value);
+	Xil_Out32(Addr, Value);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_io_interfacing_apis".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_io.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_io.o
new file mode 100644
index 0000000000000000000000000000000000000000..11349a04aa119e4aa87ed7b8bb589cbc5bba8940
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_io.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_macroback.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_macroback.h
new file mode 100644
index 0000000000000000000000000000000000000000..ebafde87d7ff8a38bd28724a08ecca7701ea4f58
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_macroback.h
@@ -0,0 +1,1052 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*********************************************************************/
+/**
+ * @file xil_macroback.h
+ *
+ * This header file is meant to bring back the removed _m macros.
+ * This header file must be included last.
+ * The following macros are not defined here due to the driver change:
+ *   XGpio_mSetDataDirection
+ *   XGpio_mGetDataReg
+ *   XGpio_mSetDataReg
+ *   XIIC_RESET
+ *   XIIC_CLEAR_STATS
+ *   XSpi_mReset
+ *   XSysAce_mSetCfgAddr
+ *   XSysAce_mIsCfgDone
+ *   XTft_mSetPixel
+ *   XTft_mGetPixel
+ *   XWdtTb_mEnableWdt
+ *   XWdtTb_mDisbleWdt
+ *   XWdtTb_mRestartWdt
+ *   XWdtTb_mGetTimebaseReg
+ *   XWdtTb_mHasReset
+ *
+ * Please refer the corresonding driver document for replacement.
+ *
+ *********************************************************************/
+
+#ifndef XIL_MACROBACK_H
+#define XIL_MACROBACK_H
+
+/*********************************************************************/
+/**
+ * Macros for Driver XCan
+ *
+ *********************************************************************/
+#ifndef XCan_mReadReg
+#define XCan_mReadReg XCan_ReadReg
+#endif
+
+#ifndef XCan_mWriteReg
+#define XCan_mWriteReg XCan_WriteReg
+#endif
+
+#ifndef XCan_mIsTxDone
+#define XCan_mIsTxDone XCan_IsTxDone
+#endif
+
+#ifndef XCan_mIsTxFifoFull
+#define XCan_mIsTxFifoFull XCan_IsTxFifoFull
+#endif
+
+#ifndef XCan_mIsHighPriorityBufFull
+#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull
+#endif
+
+#ifndef XCan_mIsRxEmpty
+#define XCan_mIsRxEmpty XCan_IsRxEmpty
+#endif
+
+#ifndef XCan_mIsAcceptFilterBusy
+#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy
+#endif
+
+#ifndef XCan_mCreateIdValue
+#define XCan_mCreateIdValue XCan_CreateIdValue
+#endif
+
+#ifndef XCan_mCreateDlcValue
+#define XCan_mCreateDlcValue XCan_CreateDlcValue
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDmaCentral
+ *
+ *********************************************************************/
+#ifndef XDmaCentral_mWriteReg
+#define XDmaCentral_mWriteReg XDmaCentral_WriteReg
+#endif
+
+#ifndef XDmaCentral_mReadReg
+#define XDmaCentral_mReadReg XDmaCentral_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsAdc
+ *
+ *********************************************************************/
+#ifndef XDsAdc_mWriteReg
+#define XDsAdc_mWriteReg XDsAdc_WriteReg
+#endif
+
+#ifndef XDsAdc_mReadReg
+#define XDsAdc_mReadReg XDsAdc_ReadReg
+#endif
+
+#ifndef XDsAdc_mIsEmpty
+#define XDsAdc_mIsEmpty XDsAdc_IsEmpty
+#endif
+
+#ifndef XDsAdc_mSetFstmReg
+#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg
+#endif
+
+#ifndef XDsAdc_mGetFstmReg
+#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg
+#endif
+
+#ifndef XDsAdc_mEnableConversion
+#define XDsAdc_mEnableConversion XDsAdc_EnableConversion
+#endif
+
+#ifndef XDsAdc_mDisableConversion
+#define XDsAdc_mDisableConversion XDsAdc_DisableConversion
+#endif
+
+#ifndef XDsAdc_mGetFifoOccyReg
+#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsDac
+ *
+ *********************************************************************/
+#ifndef XDsDac_mWriteReg
+#define XDsDac_mWriteReg XDsDac_WriteReg
+#endif
+
+#ifndef XDsDac_mReadReg
+#define XDsDac_mReadReg XDsDac_ReadReg
+#endif
+
+#ifndef XDsDac_mIsEmpty
+#define XDsDac_mIsEmpty XDsDac_IsEmpty
+#endif
+
+#ifndef XDsDac_mFifoIsFull
+#define XDsDac_mFifoIsFull XDsDac_FifoIsFull
+#endif
+
+#ifndef XDsDac_mGetVacancy
+#define XDsDac_mGetVacancy XDsDac_GetVacancy
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XEmacLite
+ *
+ *********************************************************************/
+#ifndef XEmacLite_mReadReg
+#define XEmacLite_mReadReg XEmacLite_ReadReg
+#endif
+
+#ifndef XEmacLite_mWriteReg
+#define XEmacLite_mWriteReg XEmacLite_WriteReg
+#endif
+
+#ifndef XEmacLite_mGetTxStatus
+#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus
+#endif
+
+#ifndef XEmacLite_mSetTxStatus
+#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus
+#endif
+
+#ifndef XEmacLite_mGetRxStatus
+#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus
+#endif
+
+#ifndef XEmacLite_mSetRxStatus
+#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus
+#endif
+
+#ifndef XEmacLite_mIsTxDone
+#define XEmacLite_mIsTxDone XEmacLite_IsTxDone
+#endif
+
+#ifndef XEmacLite_mIsRxEmpty
+#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty
+#endif
+
+#ifndef XEmacLite_mNextTransmitAddr
+#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr
+#endif
+
+#ifndef XEmacLite_mNextReceiveAddr
+#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr
+#endif
+
+#ifndef XEmacLite_mIsMdioConfigured
+#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured
+#endif
+
+#ifndef XEmacLite_mIsLoopbackConfigured
+#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured
+#endif
+
+#ifndef XEmacLite_mGetReceiveDataLength
+#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength
+#endif
+
+#ifndef XEmacLite_mGetTxActive
+#define XEmacLite_mGetTxActive XEmacLite_GetTxActive
+#endif
+
+#ifndef XEmacLite_mSetTxActive
+#define XEmacLite_mSetTxActive XEmacLite_SetTxActive
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XGpio
+ *
+ *********************************************************************/
+#ifndef XGpio_mWriteReg
+#define XGpio_mWriteReg XGpio_WriteReg
+#endif
+
+#ifndef XGpio_mReadReg
+#define XGpio_mReadReg XGpio_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XHwIcap
+ *
+ *********************************************************************/
+#ifndef XHwIcap_mFifoWrite
+#define XHwIcap_mFifoWrite XHwIcap_FifoWrite
+#endif
+
+#ifndef XHwIcap_mFifoRead
+#define XHwIcap_mFifoRead XHwIcap_FifoRead
+#endif
+
+#ifndef XHwIcap_mSetSizeReg
+#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg
+#endif
+
+#ifndef XHwIcap_mGetControlReg
+#define XHwIcap_mGetControlReg XHwIcap_GetControlReg
+#endif
+
+#ifndef XHwIcap_mStartConfig
+#define XHwIcap_mStartConfig XHwIcap_StartConfig
+#endif
+
+#ifndef XHwIcap_mStartReadBack
+#define XHwIcap_mStartReadBack XHwIcap_StartReadBack
+#endif
+
+#ifndef XHwIcap_mGetStatusReg
+#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg
+#endif
+
+#ifndef XHwIcap_mIsTransferDone
+#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone
+#endif
+
+#ifndef XHwIcap_mIsDeviceBusy
+#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy
+#endif
+
+#ifndef XHwIcap_mIntrGlobalEnable
+#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable
+#endif
+
+#ifndef XHwIcap_mIntrGlobalDisable
+#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable
+#endif
+
+#ifndef XHwIcap_mIntrGetStatus
+#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus
+#endif
+
+#ifndef XHwIcap_mIntrDisable
+#define XHwIcap_mIntrDisable XHwIcap_IntrDisable
+#endif
+
+#ifndef XHwIcap_mIntrEnable
+#define XHwIcap_mIntrEnable XHwIcap_IntrEnable
+#endif
+
+#ifndef XHwIcap_mIntrGetEnabled
+#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled
+#endif
+
+#ifndef XHwIcap_mIntrClear
+#define XHwIcap_mIntrClear XHwIcap_IntrClear
+#endif
+
+#ifndef XHwIcap_mGetWrFifoVacancy
+#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy
+#endif
+
+#ifndef XHwIcap_mGetRdFifoOccupancy
+#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy
+#endif
+
+#ifndef XHwIcap_mSliceX2Col
+#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col
+#endif
+
+#ifndef XHwIcap_mSliceY2Row
+#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row
+#endif
+
+#ifndef XHwIcap_mSliceXY2Slice
+#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice
+#endif
+
+#ifndef XHwIcap_mReadReg
+#define XHwIcap_mReadReg XHwIcap_ReadReg
+#endif
+
+#ifndef XHwIcap_mWriteReg
+#define XHwIcap_mWriteReg XHwIcap_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIic
+ *
+ *********************************************************************/
+#ifndef XIic_mReadReg
+#define XIic_mReadReg XIic_ReadReg
+#endif
+
+#ifndef XIic_mWriteReg
+#define XIic_mWriteReg XIic_WriteReg
+#endif
+
+#ifndef XIic_mEnterCriticalRegion
+#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIic_mExitCriticalRegion
+#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_GINTR_DISABLE
+#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIIC_GINTR_ENABLE
+#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_IS_GINTR_ENABLED
+#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled
+#endif
+
+#ifndef XIIC_WRITE_IISR
+#define XIIC_WRITE_IISR XIic_WriteIisr
+#endif
+
+#ifndef XIIC_READ_IISR
+#define XIIC_READ_IISR XIic_ReadIisr
+#endif
+
+#ifndef XIIC_WRITE_IIER
+#define XIIC_WRITE_IIER XIic_WriteIier
+#endif
+
+#ifndef XIic_mClearIisr
+#define XIic_mClearIisr XIic_ClearIisr
+#endif
+
+#ifndef XIic_mSend7BitAddress
+#define XIic_mSend7BitAddress XIic_Send7BitAddress
+#endif
+
+#ifndef XIic_mDynSend7BitAddress
+#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress
+#endif
+
+#ifndef XIic_mDynSendStartStopAddress
+#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress
+#endif
+
+#ifndef XIic_mDynSendStop
+#define XIic_mDynSendStop XIic_DynSendStop
+#endif
+
+#ifndef XIic_mSend10BitAddrByte1
+#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1
+#endif
+
+#ifndef XIic_mSend10BitAddrByte2
+#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2
+#endif
+
+#ifndef XIic_mSend7BitAddr
+#define XIic_mSend7BitAddr XIic_Send7BitAddr
+#endif
+
+#ifndef XIic_mDisableIntr
+#define XIic_mDisableIntr XIic_DisableIntr
+#endif
+
+#ifndef XIic_mEnableIntr
+#define XIic_mEnableIntr XIic_EnableIntr
+#endif
+
+#ifndef XIic_mClearIntr
+#define XIic_mClearIntr XIic_ClearIntr
+#endif
+
+#ifndef XIic_mClearEnableIntr
+#define XIic_mClearEnableIntr XIic_ClearEnableIntr
+#endif
+
+#ifndef XIic_mFlushRxFifo
+#define XIic_mFlushRxFifo XIic_FlushRxFifo
+#endif
+
+#ifndef XIic_mFlushTxFifo
+#define XIic_mFlushTxFifo XIic_FlushTxFifo
+#endif
+
+#ifndef XIic_mReadRecvByte
+#define XIic_mReadRecvByte XIic_ReadRecvByte
+#endif
+
+#ifndef XIic_mWriteSendByte
+#define XIic_mWriteSendByte XIic_WriteSendByte
+#endif
+
+#ifndef XIic_mSetControlRegister
+#define XIic_mSetControlRegister XIic_SetControlRegister
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIntc
+ *
+ *********************************************************************/
+#ifndef XIntc_mMasterEnable
+#define XIntc_mMasterEnable XIntc_MasterEnable
+#endif
+
+#ifndef XIntc_mMasterDisable
+#define XIntc_mMasterDisable XIntc_MasterDisable
+#endif
+
+#ifndef XIntc_mEnableIntr
+#define XIntc_mEnableIntr XIntc_EnableIntr
+#endif
+
+#ifndef XIntc_mDisableIntr
+#define XIntc_mDisableIntr XIntc_DisableIntr
+#endif
+
+#ifndef XIntc_mAckIntr
+#define XIntc_mAckIntr XIntc_AckIntr
+#endif
+
+#ifndef XIntc_mGetIntrStatus
+#define XIntc_mGetIntrStatus XIntc_GetIntrStatus
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XLlDma
+ *
+ *********************************************************************/
+#ifndef XLlDma_mBdRead
+#define XLlDma_mBdRead XLlDma_BdRead
+#endif
+
+#ifndef XLlDma_mBdWrite
+#define XLlDma_mBdWrite XLlDma_BdWrite
+#endif
+
+#ifndef XLlDma_mWriteReg
+#define XLlDma_mWriteReg XLlDma_WriteReg
+#endif
+
+#ifndef XLlDma_mReadReg
+#define XLlDma_mReadReg XLlDma_ReadReg
+#endif
+
+#ifndef XLlDma_mBdClear
+#define XLlDma_mBdClear XLlDma_BdClear
+#endif
+
+#ifndef XLlDma_mBdSetStsCtrl
+#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdGetStsCtrl
+#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdSetLength
+#define XLlDma_mBdSetLength XLlDma_BdSetLength
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mBdSetId
+#define XLlDma_mBdSetId XLlDma_BdSetId
+#endif
+
+#ifndef XLlDma_mBdGetId
+#define XLlDma_mBdGetId XLlDma_BdGetId
+#endif
+
+#ifndef XLlDma_mBdSetBufAddr
+#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetBufAddr
+#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mGetTxRing
+#define XLlDma_mGetTxRing XLlDma_GetTxRing
+#endif
+
+#ifndef XLlDma_mGetRxRing
+#define XLlDma_mGetRxRing XLlDma_GetRxRing
+#endif
+
+#ifndef XLlDma_mGetCr
+#define XLlDma_mGetCr XLlDma_GetCr
+#endif
+
+#ifndef XLlDma_mSetCr
+#define XLlDma_mSetCr XLlDma_SetCr
+#endif
+
+#ifndef XLlDma_mBdRingCntCalc
+#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc
+#endif
+
+#ifndef XLlDma_mBdRingMemCalc
+#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc
+#endif
+
+#ifndef XLlDma_mBdRingGetCnt
+#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt
+#endif
+
+#ifndef XLlDma_mBdRingGetFreeCnt
+#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt
+#endif
+
+#ifndef XLlDma_mBdRingSnapShotCurrBd
+#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd
+#endif
+
+#ifndef XLlDma_mBdRingNext
+#define XLlDma_mBdRingNext XLlDma_BdRingNext
+#endif
+
+#ifndef XLlDma_mBdRingPrev
+#define XLlDma_mBdRingPrev XLlDma_BdRingPrev
+#endif
+
+#ifndef XLlDma_mBdRingGetSr
+#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr
+#endif
+
+#ifndef XLlDma_mBdRingSetSr
+#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr
+#endif
+
+#ifndef XLlDma_mBdRingGetCr
+#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr
+#endif
+
+#ifndef XLlDma_mBdRingSetCr
+#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr
+#endif
+
+#ifndef XLlDma_mBdRingBusy
+#define XLlDma_mBdRingBusy XLlDma_BdRingBusy
+#endif
+
+#ifndef XLlDma_mBdRingIntEnable
+#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable
+#endif
+
+#ifndef XLlDma_mBdRingIntDisable
+#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable
+#endif
+
+#ifndef XLlDma_mBdRingIntGetEnabled
+#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled
+#endif
+
+#ifndef XLlDma_mBdRingGetIrq
+#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq
+#endif
+
+#ifndef XLlDma_mBdRingAckIrq
+#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMbox
+ *
+ *********************************************************************/
+#ifndef XMbox_mWriteReg
+#define XMbox_mWriteReg XMbox_WriteReg
+#endif
+
+#ifndef XMbox_mReadReg
+#define XMbox_mReadReg XMbox_ReadReg
+#endif
+
+#ifndef XMbox_mWriteMBox
+#define XMbox_mWriteMBox XMbox_WriteMBox
+#endif
+
+#ifndef XMbox_mReadMBox
+#define XMbox_mReadMBox XMbox_ReadMBox
+#endif
+
+#ifndef XMbox_mFSLReadMBox
+#define XMbox_mFSLReadMBox XMbox_FSLReadMBox
+#endif
+
+#ifndef XMbox_mFSLWriteMBox
+#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox
+#endif
+
+#ifndef XMbox_mFSLIsEmpty
+#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty
+#endif
+
+#ifndef XMbox_mFSLIsFull
+#define XMbox_mFSLIsFull XMbox_FSLIsFull
+#endif
+
+#ifndef XMbox_mIsEmpty
+#define XMbox_mIsEmpty XMbox_IsEmptyHw
+#endif
+
+#ifndef XMbox_mIsFull
+#define XMbox_mIsFull XMbox_IsFullHw
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMpmc
+ *
+ *********************************************************************/
+#ifndef XMpmc_mReadReg
+#define XMpmc_mReadReg XMpmc_ReadReg
+#endif
+
+#ifndef XMpmc_mWriteReg
+#define XMpmc_mWriteReg XMpmc_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMutex
+ *
+ *********************************************************************/
+#ifndef XMutex_mWriteReg
+#define XMutex_mWriteReg XMutex_WriteReg
+#endif
+
+#ifndef XMutex_mReadReg
+#define XMutex_mReadReg XMutex_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XPcie
+ *
+ *********************************************************************/
+#ifndef XPcie_mReadReg
+#define XPcie_mReadReg XPcie_ReadReg
+#endif
+
+#ifndef XPcie_mWriteReg
+#define XPcie_mWriteReg XPcie_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSpi
+ *
+ *********************************************************************/
+#ifndef XSpi_mIntrGlobalEnable
+#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable
+#endif
+
+#ifndef XSpi_mIntrGlobalDisable
+#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable
+#endif
+
+#ifndef XSpi_mIsIntrGlobalEnabled
+#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled
+#endif
+
+#ifndef XSpi_mIntrGetStatus
+#define XSpi_mIntrGetStatus XSpi_IntrGetStatus
+#endif
+
+#ifndef XSpi_mIntrClear
+#define XSpi_mIntrClear XSpi_IntrClear
+#endif
+
+#ifndef XSpi_mIntrEnable
+#define XSpi_mIntrEnable XSpi_IntrEnable
+#endif
+
+#ifndef XSpi_mIntrDisable
+#define XSpi_mIntrDisable XSpi_IntrDisable
+#endif
+
+#ifndef XSpi_mIntrGetEnabled
+#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled
+#endif
+
+#ifndef XSpi_mSetControlReg
+#define XSpi_mSetControlReg XSpi_SetControlReg
+#endif
+
+#ifndef XSpi_mGetControlReg
+#define XSpi_mGetControlReg XSpi_GetControlReg
+#endif
+
+#ifndef XSpi_mGetStatusReg
+#define XSpi_mGetStatusReg XSpi_GetStatusReg
+#endif
+
+#ifndef XSpi_mSetSlaveSelectReg
+#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mGetSlaveSelectReg
+#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mEnable
+#define XSpi_mEnable XSpi_Enable
+#endif
+
+#ifndef XSpi_mDisable
+#define XSpi_mDisable XSpi_Disable
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysAce
+ *
+ *********************************************************************/
+#ifndef XSysAce_mGetControlReg
+#define XSysAce_mGetControlReg XSysAce_GetControlReg
+#endif
+
+#ifndef XSysAce_mSetControlReg
+#define XSysAce_mSetControlReg XSysAce_SetControlReg
+#endif
+
+#ifndef XSysAce_mOrControlReg
+#define XSysAce_mOrControlReg XSysAce_OrControlReg
+#endif
+
+#ifndef XSysAce_mAndControlReg
+#define XSysAce_mAndControlReg XSysAce_AndControlReg
+#endif
+
+#ifndef XSysAce_mGetErrorReg
+#define XSysAce_mGetErrorReg XSysAce_GetErrorReg
+#endif
+
+#ifndef XSysAce_mGetStatusReg
+#define XSysAce_mGetStatusReg XSysAce_GetStatusReg
+#endif
+
+#ifndef XSysAce_mWaitForLock
+#define XSysAce_mWaitForLock XSysAce_WaitForLock
+#endif
+
+#ifndef XSysAce_mEnableIntr
+#define XSysAce_mEnableIntr XSysAce_EnableIntr
+#endif
+
+#ifndef XSysAce_mDisableIntr
+#define XSysAce_mDisableIntr XSysAce_DisableIntr
+#endif
+
+#ifndef XSysAce_mIsReadyForCmd
+#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd
+#endif
+
+#ifndef XSysAce_mIsMpuLocked
+#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked
+#endif
+
+#ifndef XSysAce_mIsIntrEnabled
+#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysMon
+ *
+ *********************************************************************/
+#ifndef XSysMon_mIsEventSamplingModeSet
+#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet
+#endif
+
+#ifndef XSysMon_mIsDrpBusy
+#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy
+#endif
+
+#ifndef XSysMon_mIsDrpLocked
+#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked
+#endif
+
+#ifndef XSysMon_mRawToTemperature
+#define XSysMon_mRawToTemperature XSysMon_RawToTemperature
+#endif
+
+#ifndef XSysMon_mRawToVoltage
+#define XSysMon_mRawToVoltage XSysMon_RawToVoltage
+#endif
+
+#ifndef XSysMon_mTemperatureToRaw
+#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw
+#endif
+
+#ifndef XSysMon_mVoltageToRaw
+#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw
+#endif
+
+#ifndef XSysMon_mReadReg
+#define XSysMon_mReadReg XSysMon_ReadReg
+#endif
+
+#ifndef XSysMon_mWriteReg
+#define XSysMon_mWriteReg XSysMon_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XTmrCtr
+ *
+ *********************************************************************/
+#ifndef XTimerCtr_mReadReg
+#define XTimerCtr_mReadReg XTimerCtr_ReadReg
+#endif
+
+#ifndef XTmrCtr_mWriteReg
+#define XTmrCtr_mWriteReg XTmrCtr_WriteReg
+#endif
+
+#ifndef XTmrCtr_mSetControlStatusReg
+#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetControlStatusReg
+#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetTimerCounterReg
+#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mSetLoadReg
+#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg
+#endif
+
+#ifndef XTmrCtr_mGetLoadReg
+#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg
+#endif
+
+#ifndef XTmrCtr_mEnable
+#define XTmrCtr_mEnable XTmrCtr_Enable
+#endif
+
+#ifndef XTmrCtr_mDisable
+#define XTmrCtr_mDisable XTmrCtr_Disable
+#endif
+
+#ifndef XTmrCtr_mEnableIntr
+#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr
+#endif
+
+#ifndef XTmrCtr_mDisableIntr
+#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr
+#endif
+
+#ifndef XTmrCtr_mLoadTimerCounterReg
+#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mHasEventOccurred
+#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartLite
+ *
+ *********************************************************************/
+#ifndef XUartLite_mUpdateStats
+#define XUartLite_mUpdateStats XUartLite_UpdateStats
+#endif
+
+#ifndef XUartLite_mWriteReg
+#define XUartLite_mWriteReg XUartLite_WriteReg
+#endif
+
+#ifndef XUartLite_mReadReg
+#define XUartLite_mReadReg XUartLite_ReadReg
+#endif
+
+#ifndef XUartLite_mClearStats
+#define XUartLite_mClearStats XUartLite_ClearStats
+#endif
+
+#ifndef XUartLite_mSetControlReg
+#define XUartLite_mSetControlReg XUartLite_SetControlReg
+#endif
+
+#ifndef XUartLite_mGetStatusReg
+#define XUartLite_mGetStatusReg XUartLite_GetStatusReg
+#endif
+
+#ifndef XUartLite_mIsReceiveEmpty
+#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty
+#endif
+
+#ifndef XUartLite_mIsTransmitFull
+#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull
+#endif
+
+#ifndef XUartLite_mIsIntrEnabled
+#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled
+#endif
+
+#ifndef XUartLite_mEnableIntr
+#define XUartLite_mEnableIntr XUartLite_EnableIntr
+#endif
+
+#ifndef XUartLite_mDisableIntr
+#define XUartLite_mDisableIntr XUartLite_DisableIntr
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartNs550
+ *
+ *********************************************************************/
+#ifndef XUartNs550_mUpdateStats
+#define XUartNs550_mUpdateStats XUartNs550_UpdateStats
+#endif
+
+#ifndef XUartNs550_mReadReg
+#define XUartNs550_mReadReg XUartNs550_ReadReg
+#endif
+
+#ifndef XUartNs550_mWriteReg
+#define XUartNs550_mWriteReg XUartNs550_WriteReg
+#endif
+
+#ifndef XUartNs550_mClearStats
+#define XUartNs550_mClearStats XUartNs550_ClearStats
+#endif
+
+#ifndef XUartNs550_mGetLineStatusReg
+#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg
+#endif
+
+#ifndef XUartNs550_mGetLineControlReg
+#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg
+#endif
+
+#ifndef XUartNs550_mSetLineControlReg
+#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg
+#endif
+
+#ifndef XUartNs550_mEnableIntr
+#define XUartNs550_mEnableIntr XUartNs550_EnableIntr
+#endif
+
+#ifndef XUartNs550_mDisableIntr
+#define XUartNs550_mDisableIntr XUartNs550_DisableIntr
+#endif
+
+#ifndef XUartNs550_mIsReceiveData
+#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData
+#endif
+
+#ifndef XUartNs550_mIsTransmitEmpty
+#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUsb
+ *
+ *********************************************************************/
+#ifndef XUsb_mReadReg
+#define XUsb_mReadReg XUsb_ReadReg
+#endif
+
+#ifndef XUsb_mWriteReg
+#define XUsb_mWriteReg XUsb_WriteReg
+#endif
+
+#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_mem.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_mem.c
new file mode 100644
index 0000000000000000000000000000000000000000..0929a6878ff746123ebbd285804913712a1ba879
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_mem.c
@@ -0,0 +1,83 @@
+/******************************************************************************/
+/**
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* @file xil_mem.c
+*
+* This file contains xil mem copy function to use in case of word aligned
+* data copies.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.1   nsk      11/07/16 First release.
+*
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+
+/***************** Inline Functions Definitions ********************/
+/*****************************************************************************/
+/**
+* @brief       This  function copies memory from once location to other.
+*
+* @param       dst: pointer pointing to destination memory
+*
+* @param       src: pointer pointing to source memory
+*
+* @param       cnt: 32 bit length of bytes to be copied
+*
+*****************************************************************************/
+void Xil_MemCpy(void* dst, const void* src, u32 cnt)
+{
+	char *d = (char*)(void *)dst;
+	const char *s = src;
+
+	while (cnt >= sizeof (int)) {
+		*(int*)d = *(int*)s;
+		d += sizeof (int);
+		s += sizeof (int);
+		cnt -= sizeof (int);
+	}
+	while ((cnt) > 0U){
+		*d = *s;
+		d += 1U;
+		s += 1U;
+		cnt -= 1U;
+	}
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_mem.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_mem.h
new file mode 100644
index 0000000000000000000000000000000000000000..a2d5e6681d9b82f40e81baa106789d512da27f6b
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_mem.h
@@ -0,0 +1,59 @@
+/******************************************************************************/
+/**
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* @file xil_mem.h
+*
+* @addtogroup common_mem_operation_api Customized APIs for Memory Operations
+*
+* The xil_mem.h file contains prototype for functions related
+* to memory operations. These APIs are applicable for all processors supported
+* by Xilinx.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.1   nsk      11/07/16 First release.
+*
+* </pre>
+*
+*****************************************************************************/
+
+/************************** Function Prototypes *****************************/
+
+void Xil_MemCpy(void* dst, const void* src, u32 cnt);
+/**
+* @} End of "addtogroup common_mem_operation_api".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_mem.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_mem.o
new file mode 100644
index 0000000000000000000000000000000000000000..4b28af0a63cd689ba0e6ddad3f693126739a8c48
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_mem.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_misc_psreset_api.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_misc_psreset_api.c
new file mode 100644
index 0000000000000000000000000000000000000000..e114d142d2a9c1bfafa4060fea861721afc2fce7
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_misc_psreset_api.c
@@ -0,0 +1,524 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_misc_reset.c
+*
+* This file contains the implementation of the reset sequence for various
+* zynq ps devices like DDR,OCM,Slcr,Ethernet,Usb.. controllers. The reset
+* sequence provided to the interfaces is based on the provision in
+* slcr reset functional blcok.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00b kpc   03/07/13 First release
+* 5.4	pkp	  09/11/15 Change the description for XOcm_Remap function
+* </pre>
+*
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "xil_misc_psreset_api.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for ddr reset.
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XDdr_ResetHw(void)
+{
+	u32 RegVal;
+
+	/* Unlock the slcr register access lock */
+	 Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert and deassert the ddr softreset bit */
+     RegVal = 	Xil_In32(XDDRC_CTRL_BASEADDR);
+	 RegVal &= (u32)(~XDDRPS_CTRL_RESET_MASK);
+	 Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
+	 RegVal |= ((u32)XDDRPS_CTRL_RESET_MASK);
+	 Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
+
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for remapping the ocm memory region
+* to postbootrom state.
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XOcm_Remap(void)
+{
+	u32 RegVal;
+
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Map the ocm region to postbootrom state */
+	RegVal = Xil_In32(XSLCR_OCM_CFG_ADDR);
+	RegVal = (RegVal & (u32)(~XSLCR_OCM_CFG_HIADDR_MASK)) | (u32)XSLCR_OCM_CFG_RESETVAL;
+	Xil_Out32(XSLCR_OCM_CFG_ADDR, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for SMC reset sequence
+*
+* @param   BaseAddress of the interface
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSmc_ResetHw(u32 BaseAddress)
+{
+	u32 RegVal;
+
+	/* Clear the interuupts */
+	RegVal = Xil_In32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET);
+	RegVal = RegVal | (u32)XSMC_MEMC_CLR_CONFIG_MASK;
+	Xil_Out32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET, RegVal);
+	/* Clear the idle counter registers */
+	Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_0_OFFSET, 0x0U);
+	Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_1_OFFSET, 0x0U);
+	/* Update the ecc registers with reset values */
+	Xil_Out32(BaseAddress + XSMC_ECC_MEMCFG1_OFFSET,
+							XSMC_ECC_MEMCFG1_RESET_VAL);
+	Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD1_OFFSET,
+							XSMC_ECC_MEMCMD1_RESET_VAL);
+	Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD2_OFFSET,
+							XSMC_ECC_MEMCMD2_RESET_VAL);
+
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for updating the slcr mio registers
+* with reset values
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_MioWriteResetValues(void)
+{
+	u32 i;
+
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Update all the MIO registers with reset values */
+    for (i=0U; i<=1U;i++)
+	{
+		Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
+								XSLCR_MIO_PIN_00_RESET_VAL);
+	}
+	for (; i<=8U;i++)
+	{
+		Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
+								XSLCR_MIO_PIN_02_RESET_VAL);
+	}
+	for (; i<=53U ;i++)
+	{
+		Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
+								XSLCR_MIO_PIN_00_RESET_VAL);
+	}
+
+
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for updating the slcr pll registers
+* with reset values
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_PllWriteResetValues(void)
+{
+
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+
+	/* update the pll control registers with reset values */
+	Xil_Out32(XSLCR_IO_PLL_CTRL_ADDR, XSLCR_IO_PLL_CTRL_RESET_VAL);
+	Xil_Out32(XSLCR_ARM_PLL_CTRL_ADDR, XSLCR_ARM_PLL_CTRL_RESET_VAL);
+	Xil_Out32(XSLCR_DDR_PLL_CTRL_ADDR, XSLCR_DDR_PLL_CTRL_RESET_VAL);
+	/* update the pll config registers with reset values */
+	Xil_Out32(XSLCR_IO_PLL_CFG_ADDR, XSLCR_IO_PLL_CFG_RESET_VAL);
+	Xil_Out32(XSLCR_ARM_PLL_CFG_ADDR, XSLCR_ARM_PLL_CFG_RESET_VAL);
+	Xil_Out32(XSLCR_DDR_PLL_CFG_ADDR, XSLCR_DDR_PLL_CFG_RESET_VAL);
+	/* update the clock control registers with reset values */
+	Xil_Out32(XSLCR_ARM_CLK_CTRL_ADDR, XSLCR_ARM_CLK_CTRL_RESET_VAL);
+	Xil_Out32(XSLCR_DDR_CLK_CTRL_ADDR, XSLCR_DDR_CLK_CTRL_RESET_VAL);
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for disabling the level shifters
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_DisableLevelShifters(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Disable the level shifters */
+	RegVal = Xil_In32(XSLCR_LVL_SHFTR_EN_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_LVL_SHFTR_EN_MASK);
+	Xil_Out32(XSLCR_LVL_SHFTR_EN_ADDR, RegVal);
+
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for OCM software reset from the
+* slcr
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_OcmReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_OCM_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_OCM_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for Ethernet software reset from
+* the slcr
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_EmacPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_GEM_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_GEM_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for USB software reset from the
+* slcr
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_UsbPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_USB_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_USB_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for QSPI software reset from the
+* slcr
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_QspiPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_QSPI_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_QSPI_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for SPI software reset from the
+* slcr
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_SpiPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_SPI_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_SPI_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for i2c software reset from the slcr
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_I2cPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_I2C_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_I2C_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for UART software reset from the
+* slcr
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_UartPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_UART_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_UART_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for CAN software reset from slcr
+* registers
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_CanPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_CAN_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_CAN_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for SMC software reset from the slcr
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_SmcPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_SMC_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_SMC_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for DMA controller software reset
+* from the slcr
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_DmaPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_DMAC_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_DMAC_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for Gpio AMBA software reset from
+* the slcr
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_GpioPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_GPIO_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_GPIO_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_misc_psreset_api.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_misc_psreset_api.h
new file mode 100644
index 0000000000000000000000000000000000000000..c228c988eb3035912db6e0d906d41609afac4b38
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_misc_psreset_api.h
@@ -0,0 +1,277 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_misc_psreset_api.h
+*
+* This file contains the various register defintions and function prototypes for
+* implementing the reset functionality of zynq ps devices
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00b kpc   03/07/13 First release.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_MISC_RESET_H		/* prevent circular inclusions */
+#define XIL_MISC_RESET_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+#define XDDRC_CTRL_BASEADDR				0xF8006000U
+#define XSLCR_BASEADDR					0xF8000000U
+/**< OCM configuration register */
+#define XSLCR_OCM_CFG_ADDR				(XSLCR_BASEADDR + 0x00000910U)
+/**< SLCR unlock register */
+#define XSLCR_UNLOCK_ADDR				(XSLCR_BASEADDR + 0x00000008U)
+/**< SLCR GEM0 rx clock control register */
+#define XSLCR_GEM0_RCLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x00000138U)
+/**< SLCR GEM1 rx clock control register */
+#define XSLCR_GEM1_RCLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x0000013CU)
+/**< SLCR GEM0 clock control register */
+#define XSLCR_GEM0_CLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x00000140U)
+/**< SLCR GEM1 clock control register */
+#define XSLCR_GEM1_CLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x00000144U)
+/**< SLCR SMC clock control register */
+#define XSLCR_SMC_CLK_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000148U)
+/**< SLCR GEM reset control register */
+#define XSLCR_GEM_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000214U)
+/**< SLCR USB0 clock control register */
+#define XSLCR_USB0_CLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x00000130U)
+/**< SLCR USB1 clock control register */
+#define XSLCR_USB1_CLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x00000134U)
+/**< SLCR USB1 reset control register */
+#define XSLCR_USB_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000210U)
+/**< SLCR SMC reset control register */
+#define XSLCR_SMC_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000234U)
+/**< SLCR Level shifter enable register */
+#define XSLCR_LVL_SHFTR_EN_ADDR			(XSLCR_BASEADDR + 0x00000900U)
+/**< SLCR ARM pll control register */
+#define XSLCR_ARM_PLL_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000100U)
+/**< SLCR DDR pll control register */
+#define XSLCR_DDR_PLL_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000104U)
+/**< SLCR IO pll control register */
+#define XSLCR_IO_PLL_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000108U)
+/**< SLCR ARM pll configuration register */
+#define XSLCR_ARM_PLL_CFG_ADDR			(XSLCR_BASEADDR + 0x00000110U)
+/**< SLCR DDR pll configuration register */
+#define XSLCR_DDR_PLL_CFG_ADDR			(XSLCR_BASEADDR + 0x00000114U)
+/**< SLCR IO pll configuration register */
+#define XSLCR_IO_PLL_CFG_ADDR			(XSLCR_BASEADDR + 0x00000118U)
+/**< SLCR ARM clock control register */
+#define XSLCR_ARM_CLK_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000120U)
+/**< SLCR DDR clock control register */
+#define XSLCR_DDR_CLK_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000124U)
+/**< SLCR MIO pin address register */
+#define XSLCR_MIO_PIN_00_ADDR			(XSLCR_BASEADDR + 0x00000700U)
+/**< SLCR DMAC reset control address register */
+#define XSLCR_DMAC_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x0000020CU)
+/**< SLCR USB reset control address register */
+/*#define XSLCR_USB_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000210U)*/
+/**< SLCR GEM reset control address register */
+/*#define XSLCR_GEM_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000214U)*/
+/**< SLCR SDIO reset control address register */
+#define XSLCR_SDIO_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000218U)
+/**< SLCR SPI reset control address register */
+#define XSLCR_SPI_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x0000021CU)
+/**< SLCR CAN reset control address register */
+#define XSLCR_CAN_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000220U)
+/**< SLCR I2C reset control address register */
+#define XSLCR_I2C_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000224U)
+/**< SLCR UART reset control address register */
+#define XSLCR_UART_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000228U)
+/**< SLCR GPIO reset control address register */
+#define XSLCR_GPIO_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x0000022CU)
+/**< SLCR LQSPI reset control address register */
+#define XSLCR_LQSPI_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000230U)
+/**< SLCR SMC reset control address register */
+/*#define XSLCR_SMC_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000234U)*/
+/**< SLCR OCM reset control address register */
+#define XSLCR_OCM_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000238U)
+
+/**< SMC mem controller clear config register */
+#define XSMC_MEMC_CLR_CONFIG_OFFSET			0x0000000CU
+/**< SMC idlecount configuration register */
+#define XSMC_REFRESH_PERIOD_0_OFFSET		0x00000020U
+#define XSMC_REFRESH_PERIOD_1_OFFSET		0x00000024U
+/**< SMC ECC configuration register */
+#define XSMC_ECC_MEMCFG1_OFFSET				0x00000404U
+/**< SMC ECC command 1 register */
+#define XSMC_ECC_MEMCMD1_OFFSET				0x00000404U
+/**< SMC ECC command 2 register */
+#define XSMC_ECC_MEMCMD2_OFFSET				0x00000404U
+
+/**< SLCR unlock code */
+#define XSLCR_UNLOCK_CODE		0x0000DF0DU
+
+/**< SMC mem clear configuration mask */
+#define XSMC_MEMC_CLR_CONFIG_MASK 	0x000005FU
+/**< SMC ECC memconfig 1 reset value */
+#define XSMC_ECC_MEMCFG1_RESET_VAL 	0x0000043U
+/**< SMC ECC memcommand 1 reset value */
+#define XSMC_ECC_MEMCMD1_RESET_VAL 	0x01300080U
+/**< SMC ECC memcommand 2 reset value */
+#define XSMC_ECC_MEMCMD2_RESET_VAL 	0x01E00585U
+
+/**< DDR controller reset bit mask */
+#define XDDRPS_CTRL_RESET_MASK 		0x00000001U
+/**< SLCR OCM configuration reset value*/
+#define XSLCR_OCM_CFG_RESETVAL		0x00000008U
+/**< SLCR OCM bank selection mask*/
+#define XSLCR_OCM_CFG_HIADDR_MASK	0x0000000FU
+/**< SLCR level shifter enable mask*/
+#define XSLCR_LVL_SHFTR_EN_MASK		0x0000000FU
+
+/**< SLCR PLL register reset values */
+#define XSLCR_ARM_PLL_CTRL_RESET_VAL	0x0001A008U
+#define XSLCR_DDR_PLL_CTRL_RESET_VAL	0x0001A008U
+#define XSLCR_IO_PLL_CTRL_RESET_VAL		0x0001A008U
+#define XSLCR_ARM_PLL_CFG_RESET_VAL		0x00177EA0U
+#define XSLCR_DDR_PLL_CFG_RESET_VAL		0x00177EA0U
+#define XSLCR_IO_PLL_CFG_RESET_VAL		0x00177EA0U
+#define XSLCR_ARM_CLK_CTRL_RESET_VAL	0x1F000400U
+#define XSLCR_DDR_CLK_CTRL_RESET_VAL	0x18400003U
+
+/**< SLCR MIO register default values */
+#define XSLCR_MIO_PIN_00_RESET_VAL		0x00001601U
+#define XSLCR_MIO_PIN_02_RESET_VAL		0x00000601U
+
+/**< SLCR Reset control registers default values */
+#define XSLCR_DMAC_RST_CTRL_VAL			0x00000001U
+#define XSLCR_GEM_RST_CTRL_VAL			0x000000F3U
+#define XSLCR_USB_RST_CTRL_VAL			0x00000003U
+#define XSLCR_I2C_RST_CTRL_VAL			0x00000003U
+#define XSLCR_SPI_RST_CTRL_VAL			0x0000000FU
+#define XSLCR_UART_RST_CTRL_VAL			0x0000000FU
+#define XSLCR_QSPI_RST_CTRL_VAL			0x00000003U
+#define XSLCR_GPIO_RST_CTRL_VAL			0x00000001U
+#define XSLCR_SMC_RST_CTRL_VAL			0x00000003U
+#define XSLCR_OCM_RST_CTRL_VAL			0x00000001U
+#define XSLCR_SDIO_RST_CTRL_VAL			0x00000033U
+#define XSLCR_CAN_RST_CTRL_VAL			0x00000003U
+/**************************** Type Definitions *******************************/
+
+/* the following data type is used to hold a null terminated version string
+ * consisting of the following format, "X.YYX"
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+/*
+ * Performs reset operation to the ddr interface
+ */
+void XDdr_ResetHw(void);
+/*
+ * Map the ocm region to post bootrom state
+ */
+void XOcm_Remap(void);
+/*
+ * Performs the smc interface reset
+ */
+void XSmc_ResetHw(u32 BaseAddress);
+/*
+ * updates the MIO registers with reset values
+ */
+void XSlcr_MioWriteResetValues(void);
+/*
+ * updates the PLL and clock registers with reset values
+ */
+void XSlcr_PllWriteResetValues(void);
+/*
+ * Disables the level shifters
+ */
+void XSlcr_DisableLevelShifters(void);
+/*
+ * provides softreset to the GPIO interface
+ */
+void XSlcr_GpioPsReset(void);
+/*
+ * provides softreset to the DMA interface
+ */
+void XSlcr_DmaPsReset(void);
+/*
+ * provides softreset to the SMC interface
+ */
+void XSlcr_SmcPsReset(void);
+/*
+ * provides softreset to the CAN interface
+ */
+void XSlcr_CanPsReset(void);
+/*
+ * provides softreset to the Uart interface
+ */
+void XSlcr_UartPsReset(void);
+/*
+ * provides softreset to the I2C interface
+ */
+void XSlcr_I2cPsReset(void);
+/*
+ * provides softreset to the SPI interface
+ */
+void XSlcr_SpiPsReset(void);
+/*
+ * provides softreset to the QSPI interface
+ */
+void XSlcr_QspiPsReset(void);
+/*
+ * provides softreset to the USB interface
+ */
+void XSlcr_UsbPsReset(void);
+/*
+ * provides softreset to the GEM interface
+ */
+void XSlcr_EmacPsReset(void);
+/*
+ * provides softreset to the OCM interface
+ */
+void XSlcr_OcmReset(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XIL_MISC_RESET_H */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_misc_psreset_api.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_misc_psreset_api.o
new file mode 100644
index 0000000000000000000000000000000000000000..0a1c629fd37949aa8cf0a4adee2ef0a39ebb3633
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_misc_psreset_api.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_mmu.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_mmu.c
new file mode 100644
index 0000000000000000000000000000000000000000..1f58d906b88a3de11364214191ffe89be161486e
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_mmu.c
@@ -0,0 +1,190 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.c
+*
+* This file provides APIs for enabling/disabling MMU and setting the memory
+* attributes for sections, in the MMU translation table.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  01/12/12 Initial version
+* 3.05a asa  03/10/12 Modified the Xil_EnableMMU to invalidate the caches
+*		      before enabling back.
+* 3.05a asa  04/15/12 Modified the Xil_SetTlbAttributes routine so that
+*		      translation table and branch predictor arrays are
+*		      invalidated, D-cache flushed before the attribute
+*		      change is applied. This is done so that the user
+*		      need not call Xil_DisableMMU before calling
+*		      Xil_SetTlbAttributes.
+* 3.10a  srt 04/18/13 Implemented ARM Erratas. Please refer to file
+*		      'xil_errata.h' for errata description
+* 3.11a  asa 09/23/13 Modified Xil_SetTlbAttributes to flush the complete
+*			 D cache after the translation table update. Removed the
+*			 redundant TLB invalidation in the same API at the beginning.
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+#include "xil_mmu.h"
+#include "xil_errata.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+extern u32 MMUTable;
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* @brief	This function sets the memory attributes for a section covering 1MB
+*			of memory in the translation table.
+*
+* @param	Addr: 32-bit address for which memory attributes need to be set.
+* @param	attrib: Attribute for the given memory region. xil_mmu.h contains
+*			definitions of commonly used memory attributes which can be
+*			utilized for this function.
+*
+*
+* @return	None.
+*
+* @note		The MMU or D-cache does not need to be disabled before changing a
+*			translation table entry.
+*
+******************************************************************************/
+void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib)
+{
+	u32 *ptr;
+	u32 section;
+
+	section = Addr / 0x100000U;
+	ptr = &MMUTable;
+	ptr += section;
+	if(ptr != NULL) {
+		*ptr = (Addr & 0xFFF00000U) | attrib;
+	}
+
+	Xil_DCacheFlush();
+
+	mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
+	/* Invalidate all branch predictors */
+	mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
+
+	dsb(); /* ensure completion of the BP and TLB invalidation */
+    isb(); /* synchronize context on this processor */
+}
+
+/*****************************************************************************/
+/**
+* @brief	Enable MMU for cortex A9 processor. This function invalidates the
+*			instruction and data caches, and then enables MMU.
+*
+* @param	None.
+* @return	None.
+*
+******************************************************************************/
+void Xil_EnableMMU(void)
+{
+	u32 Reg;
+	Xil_DCacheInvalidate();
+	Xil_ICacheInvalidate();
+
+#ifdef __GNUC__
+	Reg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+	mfcp(XREG_CP15_SYS_CONTROL, Reg);
+#else
+	{ volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
+	  Reg = Cp15Reg; }
+#endif
+	Reg |= (u32)0x05U;
+	mtcp(XREG_CP15_SYS_CONTROL, Reg);
+
+	dsb();
+	isb();
+}
+
+/*****************************************************************************/
+/**
+* @brief	Disable MMU for Cortex A9 processors. This function invalidates
+*			the TLBs, Branch Predictor Array and flushed the D Caches before
+*			disabling the MMU.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		When the MMU is disabled, all the memory accesses are treated as
+*			strongly ordered.
+******************************************************************************/
+void Xil_DisableMMU(void)
+{
+	u32 Reg;
+
+	mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
+	mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
+	Xil_DCacheFlush();
+
+#ifdef __GNUC__
+	Reg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+	mfcp(XREG_CP15_SYS_CONTROL, Reg);
+#else
+	{ volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
+	  Reg = Cp15Reg; }
+#endif
+	Reg &= (u32)(~0x05U);
+#ifdef CONFIG_ARM_ERRATA_794073
+	/* Disable Branch Prediction */
+	Reg &= (u32)(~0x800U);
+#endif
+	mtcp(XREG_CP15_SYS_CONTROL, Reg);
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_mmu.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_mmu.h
new file mode 100644
index 0000000000000000000000000000000000000000..dd14b63b7057e38c5df9eadbab636379d684e30e
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_mmu.h
@@ -0,0 +1,108 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.h
+*
+* @addtogroup a9_mmu_apis Cortex A9 Processor MMU Functions
+*
+* MMU functions equip users to enable MMU, disable MMU and modify default
+* memory attributes of MMU table as per the need.
+*
+* @{
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  01/12/12 Initial version
+* 4.2	pkp	 07/21/14 Included xil_types.h file which contains definition for
+*					  u32 which resolves issue of CR#805869
+* 5.4	pkp	 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API
+* </pre>
+*
+*
+******************************************************************************/
+
+#ifndef XIL_MMU_H
+#define XIL_MMU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Memory type */
+#define NORM_NONCACHE 0x11DE2 	/* Normal Non-cacheable */
+#define STRONG_ORDERED 0xC02	/* Strongly ordered */
+#define DEVICE_MEMORY 0xC06		/* Device memory */
+#define RESERVED 0x0			/* reserved memory */
+
+/* Normal write-through cacheable shareable */
+#define NORM_WT_CACHE 0x16DEA
+
+/* Normal write back cacheable shareable */
+#define NORM_WB_CACHE 0x15DE6
+
+/* shareability attribute */
+#define SHAREABLE (0x1 << 16)
+#define NON_SHAREABLE	(~(0x1 << 16))
+
+/* Execution type */
+#define EXECUTE_NEVER ((0x1 << 4) | (0x1 << 0))
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);
+void Xil_EnableMMU(void);
+void Xil_DisableMMU(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_MMU_H */
+/**
+* @} End of "addtogroup a9_mmu_apis".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_mmu.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_mmu.o
new file mode 100644
index 0000000000000000000000000000000000000000..bd0034f7b8d78ba1a5f870b6f3eba33c2c78b5f9
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_mmu.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_printf.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_printf.c
new file mode 100644
index 0000000000000000000000000000000000000000..9dffed148d920ea60b5322a5f6d5321243c52659
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_printf.c
@@ -0,0 +1,438 @@
+/*---------------------------------------------------*/
+/* Modified from :                                   */
+/* Public Domain version of printf                   */
+/* Rud Merriam, Compsult, Inc. Houston, Tx.          */
+/* For Embedded Systems Programming, 1991            */
+/*                                                   */
+/*---------------------------------------------------*/
+#include "xil_printf.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include <ctype.h>
+#include <string.h>
+#include <stdarg.h>
+
+static void padding( const s32 l_flag,const struct params_s *par);
+static void outs(const charptr lp, struct params_s *par);
+static s32 getnum( charptr* linep);
+
+typedef struct params_s {
+    s32 len;
+    s32 num1;
+    s32 num2;
+    char8 pad_character;
+    s32 do_padding;
+    s32 left_flag;
+    s32 unsigned_flag;
+} params_t;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the  */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and   */
+/* that is unacceptable in most embedded systems.    */
+/*---------------------------------------------------*/
+
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine puts pad characters into the output  */
+/* buffer.                                           */
+/*                                                   */
+static void padding( const s32 l_flag, const struct params_s *par)
+{
+    s32 i;
+
+    if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) {
+		i=(par->len);
+        for (; i<(par->num1); i++) {
+#ifdef STDOUT_BASEADDRESS
+            outbyte( par->pad_character);
+#endif
+		}
+    }
+}
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine moves a string to the output buffer  */
+/* as directed by the padding and positioning flags. */
+/*                                                   */
+static void outs(const charptr lp, struct params_s *par)
+{
+    charptr LocalPtr;
+	LocalPtr = lp;
+    /* pad on left if needed                         */
+	if(LocalPtr != NULL) {
+		par->len = (s32)strlen( LocalPtr);
+	}
+    padding( !(par->left_flag), par);
+
+    /* Move string to the buffer                     */
+    while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) {
+		(par->num2)--;
+#ifdef STDOUT_BASEADDRESS
+        outbyte(*LocalPtr);
+		LocalPtr += 1;
+#endif
+}
+
+    /* Pad on right if needed                        */
+    /* CR 439175 - elided next stmt. Seemed bogus.   */
+    /* par->len = strlen( lp)                      */
+    padding( par->left_flag, par);
+}
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine moves a number to the output buffer  */
+/* as directed by the padding and positioning flags. */
+/*                                                   */
+
+static void outnum( const s32 n, const s32 base, struct params_s *par)
+{
+    s32 negative;
+	s32 i;
+    char8 outbuf[32];
+    const char8 digits[] = "0123456789ABCDEF";
+    u32 num;
+    for(i = 0; i<32; i++) {
+	outbuf[i] = '0';
+    }
+
+    /* Check if number is negative                   */
+    if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
+        negative = 1;
+		num =(-(n));
+    }
+    else{
+        num = n;
+        negative = 0;
+    }
+
+    /* Build number (backwards) in outbuf            */
+    i = 0;
+    do {
+		outbuf[i] = digits[(num % base)];
+		i++;
+		num /= base;
+    } while (num > 0);
+
+    if (negative != 0) {
+		outbuf[i] = '-';
+		i++;
+	}
+
+    outbuf[i] = 0;
+    i--;
+
+    /* Move the converted number to the buffer and   */
+    /* add in the padding where needed.              */
+    par->len = (s32)strlen(outbuf);
+    padding( !(par->left_flag), par);
+    while (&outbuf[i] >= outbuf) {
+#ifdef STDOUT_BASEADDRESS
+	outbyte( outbuf[i] );
+		i--;
+#endif
+}
+    padding( par->left_flag, par);
+}
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine moves a 64-bit number to the output  */
+/* buffer as directed by the padding and positioning */
+/* flags. 											 */
+/*                                                   */
+#if defined (__aarch64__)
+static void outnum1( const s64 n, const s32 base, params_t *par)
+{
+    s32 negative;
+	s32 i;
+    char8 outbuf[64];
+    const char8 digits[] = "0123456789ABCDEF";
+    u64 num;
+    for(i = 0; i<64; i++) {
+	outbuf[i] = '0';
+    }
+
+    /* Check if number is negative                   */
+    if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
+        negative = 1;
+		num =(-(n));
+    }
+    else{
+        num = (n);
+        negative = 0;
+    }
+
+    /* Build number (backwards) in outbuf            */
+    i = 0;
+    do {
+		outbuf[i] = digits[(num % base)];
+		i++;
+		num /= base;
+    } while (num > 0);
+
+    if (negative != 0) {
+		outbuf[i] = '-';
+		i++;
+	}
+
+    outbuf[i] = 0;
+    i--;
+
+    /* Move the converted number to the buffer and   */
+    /* add in the padding where needed.              */
+    par->len = (s32)strlen(outbuf);
+    padding( !(par->left_flag), par);
+    while (&outbuf[i] >= outbuf) {
+	outbyte( outbuf[i] );
+		i--;
+}
+    padding( par->left_flag, par);
+}
+#endif
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine gets a number from the format        */
+/* string.                                           */
+/*                                                   */
+static s32 getnum( charptr* linep)
+{
+    s32 n;
+    s32 ResultIsDigit = 0;
+    charptr cptr;
+    n = 0;
+    cptr = *linep;
+	if(cptr != NULL){
+		ResultIsDigit = isdigit(((s32)*cptr));
+	}
+    while (ResultIsDigit != 0) {
+		if(cptr != NULL){
+			n = ((n*10) + (((s32)*cptr) - (s32)'0'));
+			cptr += 1;
+			if(cptr != NULL){
+				ResultIsDigit = isdigit(((s32)*cptr));
+			}
+		}
+		ResultIsDigit = isdigit(((s32)*cptr));
+	}
+    *linep = ((charptr )(cptr));
+    return(n);
+}
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine operates just like a printf/sprintf  */
+/* routine. It outputs a set of data under the       */
+/* control of a formatting string. Not all of the    */
+/* standard C format control are supported. The ones */
+/* provided are primarily those needed for embedded  */
+/* systems work. Primarily the floating point        */
+/* routines are omitted. Other formats could be      */
+/* added easily by following the examples shown for  */
+/* the supported formats.                            */
+/*                                                   */
+
+/* void esp_printf( const func_ptr f_ptr,
+   const charptr ctrl1, ...) */
+void xil_printf( const char8 *ctrl1, ...)
+{
+	s32 Check;
+#if defined (__aarch64__)
+    s32 long_flag;
+#endif
+    s32 dot_flag;
+
+    params_t par;
+
+    char8 ch;
+    va_list argp;
+    char8 *ctrl = (char8 *)ctrl1;
+
+    va_start( argp, ctrl1);
+
+    while ((ctrl != NULL) && (*ctrl != (char8)0)) {
+
+        /* move format string chars to buffer until a  */
+        /* format control is found.                    */
+        if (*ctrl != '%') {
+#ifdef STDOUT_BASEADDRESS
+            outbyte(*ctrl);
+			ctrl += 1;
+#endif
+            continue;
+        }
+
+        /* initialize all the flags for this format.   */
+        dot_flag = 0;
+#if defined (__aarch64__)
+		long_flag = 0;
+#endif
+        par.unsigned_flag = 0;
+		par.left_flag = 0;
+		par.do_padding = 0;
+        par.pad_character = ' ';
+        par.num2=32767;
+		par.num1=0;
+		par.len=0;
+
+ try_next:
+		if(ctrl != NULL) {
+			ctrl += 1;
+		}
+		if(ctrl != NULL) {
+			ch = *ctrl;
+		}
+		else {
+			ch = *ctrl;
+		}
+
+        if (isdigit((s32)ch) != 0) {
+            if (dot_flag != 0) {
+                par.num2 = getnum(&ctrl);
+			}
+            else {
+                if (ch == '0') {
+                    par.pad_character = '0';
+				}
+				if(ctrl != NULL) {
+			par.num1 = getnum(&ctrl);
+				}
+                par.do_padding = 1;
+            }
+            if(ctrl != NULL) {
+			ctrl -= 1;
+			}
+            goto try_next;
+        }
+
+        switch (tolower((s32)ch)) {
+            case '%':
+#ifdef STDOUT_BASEADDRESS
+                outbyte( '%');
+#endif
+                Check = 1;
+                break;
+
+            case '-':
+                par.left_flag = 1;
+                Check = 0;
+                break;
+
+            case '.':
+                dot_flag = 1;
+                Check = 0;
+                break;
+
+            case 'l':
+            #if defined (__aarch64__)
+                long_flag = 1;
+            #endif
+                Check = 0;
+                break;
+
+            case 'u':
+                par.unsigned_flag = 1;
+                /* fall through */
+            case 'i':
+            case 'd':
+                #if defined (__aarch64__)
+                if (long_flag != 0){
+			        outnum1((s64)va_arg(argp, s64), 10L, &par);
+                }
+                else {
+                    outnum( va_arg(argp, s32), 10L, &par);
+                }
+                #else
+                    outnum( va_arg(argp, s32), 10L, &par);
+                #endif
+				Check = 1;
+                break;
+            case 'p':
+                #if defined (__aarch64__)
+                par.unsigned_flag = 1;
+			    outnum1((s64)va_arg(argp, s64), 16L, &par);
+			    Check = 1;
+                break;
+                #endif
+            case 'X':
+            case 'x':
+                par.unsigned_flag = 1;
+                #if defined (__aarch64__)
+                if (long_flag != 0) {
+				    outnum1((s64)va_arg(argp, s64), 16L, &par);
+				}
+				else {
+				    outnum((s32)va_arg(argp, s32), 16L, &par);
+                }
+                #else
+                outnum((s32)va_arg(argp, s32), 16L, &par);
+                #endif
+                Check = 1;
+                break;
+
+            case 's':
+                outs( va_arg( argp, char *), &par);
+                Check = 1;
+                break;
+
+            case 'c':
+#ifdef STDOUT_BASEADDRESS
+                outbyte( va_arg( argp, s32));
+#endif
+                Check = 1;
+                break;
+
+            case '\\':
+                switch (*ctrl) {
+                    case 'a':
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( ((char8)0x07));
+#endif
+                        break;
+                    case 'h':
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( ((char8)0x08));
+#endif
+                        break;
+                    case 'r':
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( ((char8)0x0D));
+#endif
+                        break;
+                    case 'n':
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( ((char8)0x0D));
+                        outbyte( ((char8)0x0A));
+#endif
+                        break;
+                    default:
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( *ctrl);
+#endif
+                        break;
+                }
+                ctrl += 1;
+                Check = 0;
+                break;
+
+            default:
+		Check = 1;
+		break;
+        }
+        if(Check == 1) {
+			if(ctrl != NULL) {
+				ctrl += 1;
+			}
+                continue;
+        }
+        goto try_next;
+    }
+    va_end( argp);
+}
+
+/*---------------------------------------------------*/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_printf.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_printf.h
new file mode 100644
index 0000000000000000000000000000000000000000..2be5c5734c7c9a2b1fe7ee657cb1cca328e16e77
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_printf.h
@@ -0,0 +1,44 @@
+ #ifndef XIL_PRINTF_H
+ #define XIL_PRINTF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <ctype.h>
+#include <string.h>
+#include <stdarg.h>
+#include "xil_types.h"
+#include "xparameters.h"
+
+/*----------------------------------------------------*/
+/* Use the following parameter passing structure to   */
+/* make xil_printf re-entrant.                        */
+/*----------------------------------------------------*/
+
+struct params_s;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the  */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and   */
+/* that is unacceptable in most embedded systems.    */
+/*---------------------------------------------------*/
+
+typedef char8* charptr;
+typedef s32 (*func_ptr)(int c);
+
+/*                                                   */
+
+void xil_printf( const char8 *ctrl1, ...);
+void print( const char8 *ptr);
+extern void outbyte (char8 c);
+extern char8 inbyte(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_printf.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_printf.o
new file mode 100644
index 0000000000000000000000000000000000000000..ba9b65b3f0748d86c362631a14115b49a590bd1c
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_printf.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testcache.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testcache.c
new file mode 100644
index 0000000000000000000000000000000000000000..157ad08369f66a3a1d68212c5204e77713d4dfd3
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testcache.c
@@ -0,0 +1,371 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testcache.c
+*
+* Contains utility functions to test cache.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/28/09 Initial release
+* 4.1   asa  05/09/14 Ensured that the address uses for cache test is aligned
+*				      cache line.
+* </pre>
+*
+* @note
+* This file contain functions that all operate on HAL.
+*
+******************************************************************************/
+#ifdef __ARM__
+#include "xil_cache.h"
+#include "xil_testcache.h"
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+#ifdef __aarch64__
+#include "xreg_cortexa53.h"
+#else
+#include "xreg_cortexr5.h"
+#endif
+
+#include "xil_types.h"
+
+extern void xil_printf(const char8 *ctrl1, ...);
+
+#define DATA_LENGTH 128
+
+#ifdef __aarch64__
+static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64)));
+#else
+static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32)));
+#endif
+
+
+/*****************************************************************************/
+/**
+*
+* @brief    Perform DCache range related API test such as Xil_DCacheFlushRange
+*           and Xil_DCacheInvalidateRange. This test function writes a constant
+*           value to the Data array, flushes the range, writes a new value, then
+*           invalidates the corresponding range.
+* @param	None
+*
+* @return
+*      - -1 is returned for a failure
+*      - 0 is returned for a pass
+*
+*****************************************************************************/
+s32 Xil_TestDCacheRange(void)
+{
+	s32 Index;
+	s32 Status = 0;
+	u32 CtrlReg;
+	INTPTR Value;
+
+	xil_printf("-- Cache Range Test --\n\r");
+
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0xA0A00505;
+
+	xil_printf("    initialize Data done:\r\n");
+
+	Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+	xil_printf("    flush range done\r\n");
+
+	dsb();
+	#ifdef __aarch64__
+			CtrlReg = mfcp(SCTLR_EL3);
+			CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+			mtcp(SCTLR_EL3,CtrlReg);
+	#else
+			CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+
+	Status = 0;
+
+	for (Index = 0; Index < DATA_LENGTH; Index++) {
+		Value = Data[Index];
+		if (Value != 0xA0A00505) {
+			Status = -1;
+			xil_printf("Data[%d] = %x\r\n", Index, Value);
+			break;
+		}
+	}
+
+	if (!Status) {
+		xil_printf("	Flush worked\r\n");
+	}
+	else {
+		xil_printf("Error: flush dcache range not working\r\n");
+	}
+	dsb();
+	#ifdef __aarch64__
+			CtrlReg = mfcp(SCTLR_EL3);
+			CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+			mtcp(SCTLR_EL3,CtrlReg);
+		#else
+			CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+		#endif
+	dsb();
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0xA0A0C505;
+
+
+
+	Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = Index + 3;
+
+	Xil_DCacheInvalidateRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+	xil_printf("    invalidate dcache range done\r\n");
+	dsb();
+	#ifdef __aarch64__
+			CtrlReg = mfcp(SCTLR_EL3);
+			CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+			mtcp(SCTLR_EL3,CtrlReg);
+	#else
+			CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0xA0A0A05;
+	dsb();
+	#ifdef __aarch64__
+			CtrlReg = mfcp(SCTLR_EL3);
+			CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+			mtcp(SCTLR_EL3,CtrlReg);
+	#else
+			CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+
+	Status = 0;
+
+	for (Index = 0; Index < DATA_LENGTH; Index++) {
+		Value = Data[Index];
+		if (Value != 0xA0A0A05) {
+			Status = -1;
+			xil_printf("Data[%d] = %x\r\n", Index, Value);
+			break;
+		}
+	}
+
+
+	if (!Status) {
+		xil_printf("    Invalidate worked\r\n");
+	}
+	else {
+		xil_printf("Error: Invalidate dcache range not working\r\n");
+	}
+	xil_printf("-- Cache Range Test Complete --\r\n");
+	return Status;
+
+}
+
+/*****************************************************************************/
+/**
+* @brief    Perform DCache all related API test such as Xil_DCacheFlush and
+*           Xil_DCacheInvalidate. This test function writes a constant value
+*           to the Data array, flushes the DCache, writes a new value,
+*           then invalidates the DCache.
+*
+* @return
+*          - 0 is returned for a pass
+*          - -1 is returned for a failure
+*****************************************************************************/
+s32 Xil_TestDCacheAll(void)
+{
+	s32 Index;
+	s32 Status;
+	INTPTR Value;
+	u32 CtrlReg;
+
+	xil_printf("-- Cache All Test --\n\r");
+
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0x50500A0A;
+	xil_printf("    initialize Data done:\r\n");
+
+	Xil_DCacheFlush();
+	xil_printf("    flush all done\r\n");
+	dsb();
+	#ifdef __aarch64__
+		CtrlReg = mfcp(SCTLR_EL3);
+		CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+		mtcp(SCTLR_EL3,CtrlReg);
+	#else
+		CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+		CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+		mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	Status = 0;
+
+	for (Index = 0; Index < DATA_LENGTH; Index++) {
+		Value = Data[Index];
+
+		if (Value != 0x50500A0A) {
+			Status = -1;
+			xil_printf("Data[%d] = %x\r\n", Index, Value);
+			break;
+		}
+	}
+
+	if (!Status) {
+		xil_printf("    Flush all worked\r\n");
+	}
+	else {
+		xil_printf("Error: Flush dcache all not working\r\n");
+	}
+	dsb();
+	#ifdef __aarch64__
+		CtrlReg = mfcp(SCTLR_EL3);
+		CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+		mtcp(SCTLR_EL3,CtrlReg);
+	#else
+		CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0x505FFA0A;
+
+	Xil_DCacheFlush();
+
+
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = Index + 3;
+
+	Xil_DCacheInvalidate();
+
+	xil_printf("    invalidate all done\r\n");
+	dsb();
+	#ifdef __aarch64__
+		CtrlReg = mfcp(SCTLR_EL3);
+		CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+		mtcp(SCTLR_EL3,CtrlReg);
+	#else
+		CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+		CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+		mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0x50CFA0A;
+	dsb();
+	#ifdef __aarch64__
+		CtrlReg = mfcp(SCTLR_EL3);
+		CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+		mtcp(SCTLR_EL3,CtrlReg);
+	#else
+		CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+		CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+		mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	Status = 0;
+
+	for (Index = 0; Index < DATA_LENGTH; Index++) {
+		Value = Data[Index];
+		if (Value != 0x50CFA0A) {
+			Status = -1;
+			xil_printf("Data[%d] = %x\r\n", Index, Value);
+			break;
+		}
+	}
+
+	if (!Status) {
+		xil_printf("    Invalidate all worked\r\n");
+	}
+	else {
+			xil_printf("Error: Invalidate dcache all not working\r\n");
+	}
+
+	xil_printf("-- DCache all Test Complete --\n\r");
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+* @brief   Perform Xil_ICacheInvalidateRange() on a few function pointers.
+*
+* @return
+*     - 0 is returned for a pass
+* @note
+*     The function will hang if it fails.
+*****************************************************************************/
+s32 Xil_TestICacheRange(void)
+{
+
+	Xil_ICacheInvalidateRange((INTPTR)Xil_TestICacheRange, 1024);
+	Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheRange, 1024);
+	Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheAll, 1024);
+
+	xil_printf("-- Invalidate icache range done --\r\n");
+
+	return 0;
+}
+
+/*****************************************************************************/
+/**
+* @brief     Perform Xil_ICacheInvalidate() on a few function pointers.
+*
+* @return
+*           - 0 is returned for a pass
+* @note
+* The function will hang if it fails.
+*****************************************************************************/
+s32 Xil_TestICacheAll(void)
+{
+	Xil_ICacheInvalidate();
+	xil_printf("-- Invalidate icache all done --\r\n");
+	return 0;
+}
+#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testcache.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testcache.h
new file mode 100644
index 0000000000000000000000000000000000000000..c35e9a463f05d7fa7e176b96369f5af1493d3127
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testcache.h
@@ -0,0 +1,71 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testcache.h
+*
+* @addtogroup common_test_utils
+* <h2>Cache test </h2>
+* The xil_testcache.h file contains utility functions to test cache.
+*
+* @{
+* <pre>
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  07/29/09 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_TESTCACHE_H	/* prevent circular inclusions */
+#define XIL_TESTCACHE_H	/* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern s32 Xil_TestDCacheRange(void);
+extern s32 Xil_TestDCacheAll(void);
+extern s32 Xil_TestICacheRange(void);
+extern s32 Xil_TestICacheAll(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testcache.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testcache.o
new file mode 100644
index 0000000000000000000000000000000000000000..095b1597286fa28c25c18e88f6869e8e381d1a2c
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testcache.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testio.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testio.c
new file mode 100644
index 0000000000000000000000000000000000000000..e6a36807b3795050909953e93beffd87b0e4c1d3
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testio.c
@@ -0,0 +1,299 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testio.c
+*
+* Contains the memory test utility functions.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xil_testio.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+/************************** Function Prototypes *****************************/
+
+
+
+/**
+ *
+ * Endian swap a 16-bit word.
+ * @param	Data is the 16-bit word to be swapped.
+ * @return	The endian swapped value.
+ *
+ */
+static u16 Swap16(u16 Data)
+{
+	return ((Data >> 8U) & 0x00FFU) | ((Data << 8U) & 0xFF00U);
+}
+
+/**
+ *
+ * Endian swap a 32-bit word.
+ * @param	Data is the 32-bit word to be swapped.
+ * @return	The endian swapped value.
+ *
+ */
+static u32 Swap32(u32 Data)
+{
+	u16 Lo16;
+	u16 Hi16;
+
+	u16 Swap16Lo;
+	u16 Swap16Hi;
+
+	Hi16 = (u16)((Data >> 16U) & 0x0000FFFFU);
+	Lo16 = (u16)(Data & 0x0000FFFFU);
+
+	Swap16Lo = Swap16(Lo16);
+	Swap16Hi = Swap16(Hi16);
+
+	return (((u32)(Swap16Lo)) << 16U) | ((u32)Swap16Hi);
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Perform a destructive 8-bit wide register IO test where the
+*           register is accessed using Xil_Out8 and Xil_In8, and comparing
+*           the written values by reading them back.
+*
+* @param	Addr: a pointer to the region of memory to be tested.
+* @param	Length: Length of the block.
+* @param	Value: constant used for writting the memory.
+*
+* @return
+*           - -1 is returned for a failure
+*           - 0 is returned for a pass
+*
+*****************************************************************************/
+
+s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value)
+{
+	u8 ValueIn;
+	s32 Index;
+	s32 Status = 0;
+
+	for (Index = 0; Index < Length; Index++) {
+		Xil_Out8((INTPTR)Addr, Value);
+
+		ValueIn = Xil_In8((INTPTR)Addr);
+
+		if ((Value != ValueIn) && (Status == 0)) {
+			Status = -1;
+			break;
+		}
+	}
+	return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief   Perform a destructive 16-bit wide register IO test. Each location
+*          is tested by sequentially writing a 16-bit wide register, reading
+*          the register, and comparing value. This function tests three kinds
+*          of register IO functions, normal register IO, little-endian register
+*          IO, and big-endian register IO. When testing little/big-endian IO,
+*          the function performs the following sequence, Xil_Out16LE/Xil_Out16BE,
+*          Xil_In16, Compare In-Out values, Xil_Out16, Xil_In16LE/Xil_In16BE,
+*          Compare In-Out values. Whether to swap the read-in value before
+*          comparing is controlled by the 5th argument.
+*
+* @param	Addr: a pointer to the region of memory to be tested.
+* @param	Length: Length of the block.
+* @param	Value: constant used for writting the memory.
+* @param	Kind: Type of test. Acceptable values are:
+*		    XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
+* @param	Swap: indicates whether to byte swap the read-in value.
+*
+* @return
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+
+s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap)
+{
+	u16 *TempAddr16;
+	u16 ValueIn = 0U;
+	s32 Index;
+	TempAddr16 = Addr;
+	Xil_AssertNonvoid(TempAddr16 != NULL);
+
+	for (Index = 0; Index < Length; Index++) {
+		switch (Kind) {
+		case XIL_TESTIO_LE:
+			Xil_Out16LE((INTPTR)TempAddr16, Value);
+			break;
+		case XIL_TESTIO_BE:
+			Xil_Out16BE((INTPTR)TempAddr16, Value);
+			break;
+		default:
+			Xil_Out16((INTPTR)TempAddr16, Value);
+			break;
+		}
+
+		ValueIn = Xil_In16((INTPTR)TempAddr16);
+
+		if ((Kind != 0) && (Swap != 0)) {
+			ValueIn = Swap16(ValueIn);
+		}
+
+		if (Value != ValueIn) {
+			return -1;
+		}
+
+		/* second round */
+		Xil_Out16((INTPTR)TempAddr16, Value);
+
+		switch (Kind) {
+		case XIL_TESTIO_LE:
+			ValueIn = Xil_In16LE((INTPTR)TempAddr16);
+			break;
+		case XIL_TESTIO_BE:
+			ValueIn = Xil_In16BE((INTPTR)TempAddr16);
+			break;
+		default:
+			ValueIn = Xil_In16((INTPTR)TempAddr16);
+			break;
+		}
+
+
+		if ((Kind != 0) && (Swap != 0)) {
+			ValueIn = Swap16(ValueIn);
+		}
+
+		if (Value != ValueIn) {
+			return -1;
+		}
+		TempAddr16 += sizeof(u16);
+	}
+	return 0;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* @brief    Perform a destructive 32-bit wide register IO test. Each location
+*           is tested by sequentially writing a 32-bit wide regsiter, reading
+*           the register, and comparing value. This function tests three kinds
+*           of register IO functions, normal register IO, little-endian register IO,
+*           and big-endian register IO. When testing little/big-endian IO,
+*           the function perform the following sequence, Xil_Out32LE/
+*           Xil_Out32BE, Xil_In32, Compare, Xil_Out32, Xil_In32LE/Xil_In32BE, Compare.
+*           Whether to swap the read-in value *before comparing is controlled
+*           by the 5th argument.
+* @param	Addr: a pointer to the region of memory to be tested.
+* @param	Length: Length of the block.
+* @param	Value: constant used for writting the memory.
+* @param	Kind: type of test. Acceptable values are:
+*		    XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
+* @param	Swap: indicates whether to byte swap the read-in value.
+*
+* @return
+*           - -1 is returned for a failure
+*           - 0 is returned for a pass
+*
+*****************************************************************************/
+s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap)
+{
+	u32 *TempAddr;
+	u32 ValueIn = 0U;
+	s32 Index;
+	TempAddr = Addr;
+	Xil_AssertNonvoid(TempAddr != NULL);
+
+	for (Index = 0; Index < Length; Index++) {
+		switch (Kind) {
+		case XIL_TESTIO_LE:
+			Xil_Out32LE((INTPTR)TempAddr, Value);
+			break;
+		case XIL_TESTIO_BE:
+			Xil_Out32BE((INTPTR)TempAddr, Value);
+			break;
+		default:
+			Xil_Out32((INTPTR)TempAddr, Value);
+			break;
+		}
+
+		ValueIn = Xil_In32((INTPTR)TempAddr);
+
+		if ((Kind != 0) && (Swap != 0)) {
+			ValueIn = Swap32(ValueIn);
+		}
+
+		if (Value != ValueIn) {
+			return -1;
+		}
+
+		/* second round */
+		Xil_Out32((INTPTR)TempAddr, Value);
+
+
+		switch (Kind) {
+		case XIL_TESTIO_LE:
+			ValueIn = Xil_In32LE((INTPTR)TempAddr);
+			break;
+		case XIL_TESTIO_BE:
+			ValueIn = Xil_In32BE((INTPTR)TempAddr);
+			break;
+		default:
+			ValueIn = Xil_In32((INTPTR)TempAddr);
+			break;
+		}
+
+		if ((Kind != 0) && (Swap != 0)) {
+			ValueIn = Swap32(ValueIn);
+		}
+
+		if (Value != ValueIn) {
+			return -1;
+		}
+		TempAddr += sizeof(u32);
+	}
+	return 0;
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testio.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testio.h
new file mode 100644
index 0000000000000000000000000000000000000000..ad68ead6430fef3b1a961165119aca5b8c557652
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testio.h
@@ -0,0 +1,94 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testio.h
+*
+* @addtogroup common_test_utils Test Utilities
+* <h2>I/O test </h2>
+* The xil_testio.h file contains utility functions to test endian related memory
+* IO functions.
+*
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00 hbm  08/05/09 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_TESTIO_H	/* prevent circular inclusions */
+#define XIL_TESTIO_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+#define XIL_TESTIO_DEFAULT 	0
+#define XIL_TESTIO_LE		1
+#define XIL_TESTIO_BE		2
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value);
+extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap);
+extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testio.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testio.o
new file mode 100644
index 0000000000000000000000000000000000000000..aa5c2aa5a18c4d2eba4a0d4bc17f1804ecd0a310
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testio.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testmem.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testmem.c
new file mode 100644
index 0000000000000000000000000000000000000000..87426d17aa6312ce77ec592ad582e56f17d68d84
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testmem.c
@@ -0,0 +1,868 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmem.c
+*
+* Contains the memory test utility functions.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xil_testmem.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions ****************************/
+/************************** Function Prototypes *****************************/
+
+static u32 RotateLeft(u32 Input, u8 Width);
+
+/* define ROTATE_RIGHT to give access to this functionality */
+/* #define ROTATE_RIGHT */
+#ifdef ROTATE_RIGHT
+static u32 RotateRight(u32 Input, u8 Width);
+#endif /* ROTATE_RIGHT */
+
+
+/*****************************************************************************/
+/**
+*
+* @brief    Perform a destructive 32-bit wide memory test.
+*
+* @param    Addr: pointer to the region of memory to be tested.
+* @param    Words: length of the block.
+* @param    Pattern: constant used for the constant pattern test, if 0,
+*           0xDEADBEEF is used.
+* @param    Subtest: test type selected. See xil_testmem.h for possible
+*	        values.
+*
+* @return
+*           - 0 is returned for a pass
+*           - 1 is returned for a failure
+*
+* @note
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest)
+{
+	u32 I;
+	u32 j;
+	u32 Val;
+	u32 FirtVal;
+	u32 WordMem32;
+	s32 Status = 0;
+
+	Xil_AssertNonvoid(Words != (u32)0);
+	Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST);
+	Xil_AssertNonvoid(Addr != NULL);
+
+	/*
+	 * variable initialization
+	 */
+	Val = XIL_TESTMEM_INIT_VALUE;
+	FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+		/*
+		 * Fill the memory with incrementing
+		 * values starting from 'FirtVal'
+		 */
+		for (I = 0U; I < Words; I++) {
+			*(Addr+I) = Val;
+			Val++;
+		}
+
+		/*
+		 * Restore the reference 'Val' to the
+		 * initial value
+		 */
+		Val = FirtVal;
+
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the incrementing reference
+		 * Val
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			WordMem32 = *(Addr+I);
+
+			if (WordMem32 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+
+			Val++;
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+		/*
+		 * set up to cycle through all possible initial
+		 * test Patterns for walking ones test
+		 */
+
+		for (j = 0U; j < (u32)32; j++) {
+			/*
+			 * Generate an initial value for walking ones test
+			 * to test for bad data bits
+			 */
+
+			Val = (1U << j);
+
+			/*
+			 * START walking ones test
+			 * Write a one to each data bit indifferent locations
+			 */
+
+			for (I = 0U; I < (u32)32; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = (u32) RotateLeft(Val, 32U);
+			}
+
+			/*
+			 * Restore the reference 'val' to the
+			 * initial value
+			 */
+			Val = 1U << j;
+
+			/* Read the values from each location that was
+			 * written */
+			for (I = 0U; I < (u32)32; I++) {
+				/* read memory location */
+
+				WordMem32 = *(Addr+I);
+
+				if (WordMem32 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+
+				Val = (u32)RotateLeft(Val, 32U);
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+		/*
+		 * set up to cycle through all possible
+		 * initial test Patterns for walking zeros test
+		 */
+
+		for (j = 0U; j < (u32)32; j++) {
+
+			/*
+			 * Generate an initial value for walking ones test
+			 * to test for bad data bits
+			 */
+
+			Val = ~(1U << j);
+
+			/*
+			 * START walking zeros test
+			 * Write a one to each data bit indifferent locations
+			 */
+
+			for (I = 0U; I < (u32)32; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = ~((u32)RotateLeft(~Val, 32U));
+			}
+
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+
+			Val = ~(1U << j);
+
+			/* Read the values from each location that was
+			 * written */
+			for (I = 0U; I < (u32)32; I++) {
+				/* read memory location */
+				WordMem32 = *(Addr+I);
+				if (WordMem32 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+				Val = ~((u32)RotateLeft(~Val, 32U));
+			}
+
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+		/* Fill the memory with inverse of address */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			Val = (u32) (~((INTPTR) (&Addr[I])));
+			*(Addr+I) = Val;
+		}
+
+		/*
+		 * Check every word within the words
+		 * of tested memory
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* Read the location */
+			WordMem32 = *(Addr+I);
+			Val = (u32) (~((INTPTR) (&Addr[I])));
+
+			if ((WordMem32 ^ Val) != 0x00000000U) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+		/*
+		 * Generate an initial value for
+		 * memory testing
+		 */
+
+		if (Pattern == (u32)0) {
+			Val = 0xDEADBEEFU;
+		}
+		else {
+			Val = Pattern;
+		}
+
+		/*
+		 * Fill the memory with fixed Pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+		}
+
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the fixed Pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+
+			/* read memory location */
+
+			WordMem32 = *(Addr+I);
+			if (WordMem32 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+End_Label:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Perform a destructive 16-bit wide memory test.
+*
+* @param    Addr: pointer to the region of memory to be tested.
+* @param    Words: length of the block.
+* @param    Pattern: constant used for the constant Pattern test, if 0,
+*           0xDEADBEEF is used.
+* @param    Subtest: type of test selected. See xil_testmem.h for possible
+*	        values.
+*
+* @return
+*
+*           - -1 is returned for a failure
+*           - 0 is returned for a pass
+*
+* @note
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest)
+{
+	u32 I;
+	u32 j;
+	u16 Val;
+	u16 FirtVal;
+	u16 WordMem16;
+	s32 Status = 0;
+
+	Xil_AssertNonvoid(Words != (u32)0);
+	Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
+	Xil_AssertNonvoid(Addr != NULL);
+
+	/*
+	 * variable initialization
+	 */
+	Val = XIL_TESTMEM_INIT_VALUE;
+	FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+	/*
+	 * selectthe proper Subtest(s)
+	 */
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+		/*
+		 * Fill the memory with incrementing
+		 * values starting from 'FirtVal'
+		 */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+			Val++;
+		}
+		/*
+		 * Restore the reference 'Val' to the
+		 * initial value
+		 */
+		Val = FirtVal;
+
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the incrementing reference val
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem16 = *(Addr+I);
+			if (WordMem16 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+			Val++;
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+		/*
+		 * set up to cycle through all possible initial test
+		 * Patterns for walking ones test
+		 */
+
+		for (j = 0U; j < (u32)16; j++) {
+			/*
+			 * Generate an initial value for walking ones test
+			 * to test for bad data bits
+			 */
+
+			Val = (u16)((u32)1 << j);
+			/*
+			 * START walking ones test
+			 * Write a one to each data bit indifferent locations
+			 */
+
+			for (I = 0U; I < (u32)16; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = (u16)RotateLeft(Val, 16U);
+			}
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+			Val = (u16)((u32)1 << j);
+			/* Read the values from each location that was written */
+			for (I = 0U; I < (u32)16; I++) {
+				/* read memory location */
+				WordMem16 = *(Addr+I);
+				if (WordMem16 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+				Val = (u16)RotateLeft(Val, 16U);
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+		/*
+		 * set up to cycle through all possible initial
+		 * test Patterns for walking zeros test
+		 */
+
+		for (j = 0U; j < (u32)16; j++) {
+			/*
+			 * Generate an initial value for walking ones
+			 * test to test for bad
+			 * data bits
+			 */
+
+			Val = ~(1U << j);
+			/*
+			 * START walking zeros test
+			 * Write a one to each data bit indifferent locations
+			 */
+
+			for (I = 0U; I < (u32)16; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = ~((u16)RotateLeft(~Val, 16U));
+			}
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+			Val = ~(1U << j);
+			/* Read the values from each location that was written */
+			for (I = 0U; I < (u32)16; I++) {
+				/* read memory location */
+				WordMem16 = *(Addr+I);
+				if (WordMem16 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+				Val = ~((u16)RotateLeft(~Val, 16U));
+			}
+
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+		/* Fill the memory with inverse of address */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			Val = (u16) (~((INTPTR)(&Addr[I])));
+			*(Addr+I) = Val;
+		}
+		/*
+		 * Check every word within the words
+		 * of tested memory
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem16 = *(Addr+I);
+			Val = (u16) (~((INTPTR) (&Addr[I])));
+			if ((WordMem16 ^ Val) != 0x0000U) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+		/*
+		 * Generate an initial value for
+		 * memory testing
+		 */
+		if (Pattern == (u16)0) {
+			Val = 0xDEADU;
+		}
+		else {
+			Val = Pattern;
+		}
+
+		/*
+		 * Fill the memory with fixed pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+		}
+
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the fixed pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem16 = *(Addr+I);
+			if (WordMem16 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+End_Label:
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* @brief    Perform a destructive 8-bit wide memory test.
+*
+* @param    Addr: pointer to the region of memory to be tested.
+* @param    Words: length of the block.
+* @param    Pattern: constant used for the constant pattern test, if 0,
+*           0xDEADBEEF is used.
+* @param    Subtest: type of test selected. See xil_testmem.h for possible
+*	        values.
+*
+* @return
+*           - -1 is returned for a failure
+*           - 0 is returned for a pass
+*
+* @note
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest)
+{
+	u32 I;
+	u32 j;
+	u8 Val;
+	u8 FirtVal;
+	u8 WordMem8;
+	s32 Status = 0;
+
+	Xil_AssertNonvoid(Words != (u32)0);
+	Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
+	Xil_AssertNonvoid(Addr != NULL);
+
+	/*
+	 * variable initialization
+	 */
+	Val = XIL_TESTMEM_INIT_VALUE;
+	FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+	/*
+	 * select the proper Subtest(s)
+	 */
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+		/*
+		 * Fill the memory with incrementing
+		 * values starting from 'FirtVal'
+		 */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+			Val++;
+		}
+		/*
+		 * Restore the reference 'Val' to the
+		 * initial value
+		 */
+		Val = FirtVal;
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the incrementing reference
+		 * Val
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem8 = *(Addr+I);
+			if (WordMem8 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+			Val++;
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+		/*
+		 * set up to cycle through all possible initial
+		 * test Patterns for walking ones test
+		 */
+
+		for (j = 0U; j < (u32)8; j++) {
+			/*
+			 * Generate an initial value for walking ones test
+			 * to test for bad data bits
+			 */
+			Val = (u8)((u32)1 << j);
+			/*
+			 * START walking ones test
+			 * Write a one to each data bit indifferent locations
+			 */
+			for (I = 0U; I < (u32)8; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = (u8)RotateLeft(Val, 8U);
+			}
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+			Val = (u8)((u32)1 << j);
+			/* Read the values from each location that was written */
+			for (I = 0U; I < (u32)8; I++) {
+				/* read memory location */
+				WordMem8 = *(Addr+I);
+				if (WordMem8 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+				Val = (u8)RotateLeft(Val, 8U);
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+		/*
+		 * set up to cycle through all possible initial test
+		 * Patterns for walking zeros test
+		 */
+
+		for (j = 0U; j < (u32)8; j++) {
+			/*
+			 * Generate an initial value for walking ones test to test
+			 * for bad data bits
+			 */
+			Val = ~(1U << j);
+			/*
+			 * START walking zeros test
+			 * Write a one to each data bit indifferent locations
+			 */
+			for (I = 0U; I < (u32)8; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = ~((u8)RotateLeft(~Val, 8U));
+			}
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+			Val = ~(1U << j);
+			/* Read the values from each location that was written */
+			for (I = 0U; I < (u32)8; I++) {
+				/* read memory location */
+				WordMem8 = *(Addr+I);
+				if (WordMem8 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+
+				Val = ~((u8)RotateLeft(~Val, 8U));
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+		/* Fill the memory with inverse of address */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			Val = (u8) (~((INTPTR) (&Addr[I])));
+			*(Addr+I) = Val;
+		}
+
+		/*
+		 * Check every word within the words
+		 * of tested memory
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem8 = *(Addr+I);
+			Val = (u8) (~((INTPTR) (&Addr[I])));
+			if ((WordMem8 ^ Val) != 0x00U) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+		/*
+		 * Generate an initial value for
+		 * memory testing
+		 */
+
+		if (Pattern == (u8)0) {
+			Val = 0xA5U;
+		}
+		else {
+			Val = Pattern;
+		}
+		/*
+		 * Fill the memory with fixed Pattern
+		 */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+		}
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the fixed Pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem8 = *(Addr+I);
+			if (WordMem8 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+End_Label:
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* @brief   Rotates the provided value to the left one bit position
+*
+* @param    Input is value to be rotated to the left
+* @param    Width is the number of bits in the input data
+*
+* @return
+*           The resulting unsigned long value of the rotate left
+*
+*
+*****************************************************************************/
+static u32 RotateLeft(u32 Input, u8 Width)
+{
+	u32 Msb;
+	u32 ReturnVal;
+	u32 WidthMask;
+	u32 MsbMask;
+	u32 LocalInput = Input;
+
+	/*
+	 * set up the WidthMask and the MsbMask
+	 */
+
+	MsbMask = 1U << (Width - 1U);
+
+	WidthMask = (MsbMask << (u32)1) - (u32)1;
+
+	/*
+	 * set the Width of the Input to the correct width
+	 */
+
+	LocalInput = LocalInput & WidthMask;
+
+	Msb = LocalInput & MsbMask;
+
+	ReturnVal = LocalInput << 1U;
+
+	if (Msb != 0x00000000U) {
+		ReturnVal = ReturnVal | (u32)0x00000001;
+	}
+
+	ReturnVal = ReturnVal & WidthMask;
+
+	return ReturnVal;
+
+}
+
+#ifdef ROTATE_RIGHT
+/*****************************************************************************/
+/**
+*
+* @brief    Rotates the provided value to the right one bit position
+*
+* @param    Input: value to be rotated to the right
+* @param    Width: number of bits in the input data
+*
+* @return
+*           The resulting u32 value of the rotate right
+*
+*****************************************************************************/
+static u32 RotateRight(u32 Input, u8 Width)
+{
+	u32 Lsb;
+	u32 ReturnVal;
+	u32 WidthMask;
+	u32 MsbMask;
+	u32 LocalInput = Input;
+	/*
+	 * set up the WidthMask and the MsbMask
+	 */
+
+	MsbMask = 1U << (Width - 1U);
+
+	WidthMask = (MsbMask << 1U) - 1U;
+
+	/*
+	 * set the width of the input to the correct width
+	 */
+
+	LocalInput = LocalInput & WidthMask;
+
+	ReturnVal = LocalInput >> 1U;
+
+	Lsb = LocalInput & 0x00000001U;
+
+	if (Lsb != 0x00000000U) {
+		ReturnVal = ReturnVal | MsbMask;
+	}
+
+	ReturnVal = ReturnVal & WidthMask;
+
+	return ReturnVal;
+
+}
+#endif /* ROTATE_RIGHT */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testmem.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testmem.h
new file mode 100644
index 0000000000000000000000000000000000000000..c204728223b2c15e57d4e9f8afc944ad02a40c76
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testmem.h
@@ -0,0 +1,158 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmem.h
+* @addtogroup common_test_utils
+*
+* <h2>Memory test</h2>
+*
+* The xil_testmem.h file contains utility functions to test memory.
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+* Following list describes the supported memory tests:
+*
+*  - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests.
+*
+*  - XIL_TESTMEM_INCREMENT: This test
+* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the
+* test value for memory.
+*
+*  - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test
+* uses a walking '1' as the test value for memory.
+* @code
+*          location 1 = 0x00000001
+*          location 2 = 0x00000002
+*          ...
+* @endcode
+*
+*  - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test.
+* This test uses the inverse value of the walking ones test
+* as the test value for memory.
+* @code
+*       location 1 = 0xFFFFFFFE
+*       location 2 = 0xFFFFFFFD
+*       ...
+*@endcode
+*
+*  - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test.
+* This test uses the inverse of the address of the location under test
+* as the test value for memory.
+*
+*  - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test.
+* This test uses the provided patters as the test value for memory.
+* If zero is provided as the pattern the test uses '0xDEADBEEF".
+*
+* @warning
+* The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces
+* have been set up.
+* The address provided to the memory tests is not checked for
+* validity except for the NULL case. It is possible to provide a code-space
+* pointer for this test to start with and ultimately destroy executable code
+* causing random failures.
+*
+* @note
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_TESTMEM_H	/* prevent circular inclusions */
+#define XIL_TESTMEM_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* xutil_memtest defines */
+
+#define XIL_TESTMEM_INIT_VALUE	1U
+
+/** @name Memory subtests
+ * @{
+ */
+/**
+ * See the detailed description of the subtests in the file description.
+ */
+#define XIL_TESTMEM_ALLMEMTESTS     0x00U
+#define XIL_TESTMEM_INCREMENT       0x01U
+#define XIL_TESTMEM_WALKONES        0x02U
+#define XIL_TESTMEM_WALKZEROS       0x03U
+#define XIL_TESTMEM_INVERSEADDR     0x04U
+#define XIL_TESTMEM_FIXEDPATTERN    0x05U
+#define XIL_TESTMEM_MAXTEST         XIL_TESTMEM_FIXEDPATTERN
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/* xutil_testmem prototypes */
+
+extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
+extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
+extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testmem.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testmem.o
new file mode 100644
index 0000000000000000000000000000000000000000..5328a7eedd75007c2eb9baf9a4a83f5d4774dea0
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_testmem.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_types.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_types.h
new file mode 100644
index 0000000000000000000000000000000000000000..8143aff1ea4481ade21acf41eba4c361096081a9
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xil_types.h
@@ -0,0 +1,209 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_types.h
+*
+* @addtogroup common_types Basic Data types for Xilinx&reg; Software IP
+*
+* The xil_types.h file contains basic types for Xilinx software IP. These data types
+* are applicable for all processors supported by Xilinx.
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* 3.03a sdm  05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+* 5.00 	pkp  05/29/14 Made changes for 64 bit architecture
+*	srt  07/14/14 Use standard definitions from stdint.h and stddef.h
+*		      Define LONG and ULONG datatypes and mask values
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_TYPES_H	/* prevent circular inclusions */
+#define XIL_TYPES_H	/* by using protection macros */
+
+#include <stdint.h>
+#include <stddef.h>
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#  define TRUE		1U
+#endif
+
+#ifndef FALSE
+#  define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+#define XIL_COMPONENT_IS_READY     0x11111111U  /**< In device drivers, This macro will be
+                                                 assigend to "IsReady" member of driver
+												 instance to indicate that driver
+												 instance is initialized and ready to use. */
+#define XIL_COMPONENT_IS_STARTED   0x22222222U  /**< In device drivers, This macro will be assigend to
+                                                 "IsStarted" member of driver instance
+												 to indicate that driver instance is
+												 started and it can be enabled. */
+
+/* @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XBASIC_TYPES_H
+/*
+ * guarded against xbasic_types.h.
+ */
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+/** @}*/
+#define __XUINT64__
+typedef struct
+{
+	u32 Upper;
+	u32 Lower;
+} Xuint64;
+
+
+/*****************************************************************************/
+/**
+* @brief    Return the most significant half of the 64 bit data type.
+*
+* @param    x is the 64 bit word.
+*
+* @return   The upper 32 bits of the 64 bit word.
+*
+******************************************************************************/
+#define XUINT64_MSW(x) ((x).Upper)
+
+/*****************************************************************************/
+/**
+* @brief    Return the least significant half of the 64 bit data type.
+*
+* @param    x is the 64 bit word.
+*
+* @return   The lower 32 bits of the 64 bit word.
+*
+******************************************************************************/
+#define XUINT64_LSW(x) ((x).Lower)
+
+#endif /* XBASIC_TYPES_H */
+
+/*
+ * xbasic_types.h does not typedef s* or u64
+ */
+/** @{ */
+typedef char char8;
+typedef int8_t s8;
+typedef int16_t s16;
+typedef int32_t s32;
+typedef int64_t s64;
+typedef uint64_t u64;
+typedef int sint32;
+
+typedef intptr_t INTPTR;
+typedef uintptr_t UINTPTR;
+typedef ptrdiff_t PTRDIFF;
+/** @}*/
+#if !defined(LONG) || !defined(ULONG)
+typedef long LONG;
+typedef unsigned long ULONG;
+#endif
+
+#define ULONG64_HI_MASK	0xFFFFFFFF00000000U
+#define ULONG64_LO_MASK	~ULONG64_HI_MASK
+
+#else
+#include <linux/types.h>
+#endif
+
+/** @{ */
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/**
+ * This data type defines an exception handler for a processor.
+ * The argument points to the instance of the component
+ */
+typedef void (*XExceptionHandler) (void *InstancePtr);
+
+/**
+ * @brief  Returns 32-63 bits of a number.
+ * @param  n : Number being accessed.
+ * @return Bits 32-63 of number.
+ *
+ * @note    A basic shift-right of a 64- or 32-bit quantity.
+ *          Use this to suppress the "right shift count >= width of type"
+ *          warning when that quantity is 32-bits.
+ */
+#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
+
+/**
+ * @brief  Returns 0-31 bits of a number
+ * @param  n : Number being accessed.
+ * @return Bits 0-31 of number
+ */
+#define LOWER_32_BITS(n) ((u32)(n))
+
+
+
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#define TRUE		1U
+#endif
+
+#ifndef FALSE
+#define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+#endif	/* end of protection macro */
+/**
+* @} End of "addtogroup common_types".
+*/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xl2cc.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xl2cc.h
new file mode 100644
index 0000000000000000000000000000000000000000..735e26dd4df8663a93b4f22ce5eb5cd712bc6653
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xl2cc.h
@@ -0,0 +1,172 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xl2cc.h
+*
+* This file contains the address definitions for the PL310 Level-2 Cache
+* Controller.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  02/01/10 Initial version
+* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
+*		      'xil_errata.h' for errata description
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XL2CC_H_
+#define _XL2CC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+/* L2CC Register Offsets */
+#define XPS_L2CC_ID_OFFSET		0x0000U
+#define XPS_L2CC_TYPE_OFFSET		0x0004U
+#define XPS_L2CC_CNTRL_OFFSET		0x0100U
+#define XPS_L2CC_AUX_CNTRL_OFFSET	0x0104U
+#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET	0x0108U
+#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET	0x010CU
+
+#define XPS_L2CC_EVNT_CNTRL_OFFSET	0x0200U
+#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET	0x0204U
+#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET	0x0208U
+#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET	0x020CU
+#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET	0x0210U
+
+#define XPS_L2CC_IER_OFFSET		0x0214U		/* Interrupt Mask */
+#define XPS_L2CC_IPR_OFFSET		0x0218U		/* Masked interrupt status */
+#define XPS_L2CC_ISR_OFFSET		0x021CU		/* Raw Interrupt Status */
+#define XPS_L2CC_IAR_OFFSET		0x0220U		/* Interrupt Clear */
+
+#define XPS_L2CC_CACHE_SYNC_OFFSET		0x0730U		/* Cache Sync */
+#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET	0x0740U		/* Dummy Register for Cache Sync */
+#define XPS_L2CC_CACHE_INVLD_PA_OFFSET		0x0770U		/* Cache Invalid by PA */
+#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET		0x077CU		/* Cache Invalid by Way */
+#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET		0x07B0U		/* Cache Clean by PA */
+#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET	0x07B8U		/* Cache Clean by Index */
+#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET		0x07BCU		/* Cache Clean by Way */
+#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET	0x07F0U		/* Cache Invalidate and Clean by PA */
+#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET	0x07F8U		/* Cache Invalidate and Clean by Index */
+#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET	0x07FCU		/* Cache Invalidate and Clean by Way */
+
+#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET	0x0900U		/* Cache Data Lockdown 0 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET	0x0904U		/* Cache Instruction Lockdown 0 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET	0x0908U		/* Cache Data Lockdown 1 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET	0x090CU		/* Cache Instruction Lockdown 1 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET	0x0910U		/* Cache Data Lockdown 2 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET	0x0914U		/* Cache Instruction Lockdown 2 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET	0x0918U		/* Cache Data Lockdown 3 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET	0x091CU		/* Cache Instruction Lockdown 3 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET	0x0920U		/* Cache Data Lockdown 4 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET	0x0924U		/* Cache Instruction Lockdown 4 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET	0x0928U		/* Cache Data Lockdown 5 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET	0x092CU		/* Cache Instruction Lockdown 5 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET	0x0930U		/* Cache Data Lockdown 6 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET	0x0934U		/* Cache Instruction Lockdown 6 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET	0x0938U		/* Cache Data Lockdown 7 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET	0x093CU		/* Cache Instruction Lockdown 7 by Way */
+
+#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950U		/* Cache Lockdown Line Enable */
+#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET	0x0954U		/* Cache Unlock All Lines by Way */
+
+#define XPS_L2CC_ADDR_FILTER_START_OFFSET	0x0C00U		/* Start of address filtering */
+#define XPS_L2CC_ADDR_FILTER_END_OFFSET		0x0C04U		/* Start of address filtering */
+
+#define XPS_L2CC_DEBUG_CTRL_OFFSET		0x0F40U		/* Debug Control Register */
+
+/* XPS_L2CC_CNTRL_OFFSET bit masks */
+#define XPS_L2CC_ENABLE_MASK		0x00000001U	/* enables the L2CC */
+
+/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */
+#define XPS_L2CC_AUX_EBRESPE_MASK	0x40000000U	/* Early BRESP Enable */
+#define XPS_L2CC_AUX_IPFE_MASK		0x20000000U	/* Instruction Prefetch Enable */
+#define XPS_L2CC_AUX_DPFE_MASK		0x10000000U	/* Data Prefetch Enable */
+#define XPS_L2CC_AUX_NSIC_MASK		0x08000000U	/* Non-secure interrupt access control */
+#define XPS_L2CC_AUX_NSLE_MASK		0x04000000U	/* Non-secure lockdown enable */
+#define XPS_L2CC_AUX_CRP_MASK		0x02000000U	/* Cache replacement policy */
+#define XPS_L2CC_AUX_FWE_MASK		0x01800000U	/* Force write allocate */
+#define XPS_L2CC_AUX_SAOE_MASK		0x00400000U	/* Shared attribute override enable */
+#define XPS_L2CC_AUX_PE_MASK		0x00200000U	/* Parity enable */
+#define XPS_L2CC_AUX_EMBE_MASK		0x00100000U	/* Event monitor bus enable */
+#define XPS_L2CC_AUX_WAY_SIZE_MASK	0x000E0000U	/* Way-size */
+#define XPS_L2CC_AUX_ASSOC_MASK		0x00010000U	/* Associativity */
+#define XPS_L2CC_AUX_SAIE_MASK		0x00002000U	/* Shared attribute invalidate enable */
+#define XPS_L2CC_AUX_EXCL_CACHE_MASK	0x00001000U	/* Exclusive cache configuration */
+#define XPS_L2CC_AUX_SBDLE_MASK		0x00000800U	/* Store buffer device limitation Enable */
+#define XPS_L2CC_AUX_HPSODRE_MASK	0x00000400U	/* High Priority for SO and Dev Reads Enable */
+#define XPS_L2CC_AUX_FLZE_MASK		0x00000001U	/* Full line of zero enable */
+
+#define XPS_L2CC_AUX_REG_DEFAULT_MASK	0x72360000U	/* Enable all prefetching, */
+                                                    /* Cache replacement policy, Parity enable, */
+                                                    /* Event monitor bus enable and Way Size (64 KB) */
+#define XPS_L2CC_AUX_REG_ZERO_MASK	0xFFF1FFFFU	/* */
+
+#define XPS_L2CC_TAG_RAM_DEFAULT_MASK	0x00000111U	/* latency for TAG RAM */
+#define XPS_L2CC_DATA_RAM_DEFAULT_MASK	0x00000121U	/* latency for DATA RAM */
+
+/* Interrupt bit masks */
+#define XPS_L2CC_IXR_DECERR_MASK	0x00000100U	/* DECERR from L3 */
+#define XPS_L2CC_IXR_SLVERR_MASK	0x00000080U	/* SLVERR from L3 */
+#define XPS_L2CC_IXR_ERRRD_MASK		0x00000040U	/* Error on L2 data RAM (Read) */
+#define XPS_L2CC_IXR_ERRRT_MASK		0x00000020U	/* Error on L2 tag RAM (Read) */
+#define XPS_L2CC_IXR_ERRWD_MASK		0x00000010U	/* Error on L2 data RAM (Write) */
+#define XPS_L2CC_IXR_ERRWT_MASK		0x00000008U	/* Error on L2 tag RAM (Write) */
+#define XPS_L2CC_IXR_PARRD_MASK		0x00000004U	/* Parity Error on L2 data RAM (Read) */
+#define XPS_L2CC_IXR_PARRT_MASK		0x00000002U	/* Parity Error on L2 tag RAM (Read) */
+#define XPS_L2CC_IXR_ECNTR_MASK		0x00000001U	/* Event Counter1/0 Overflow Increment */
+
+/* Address filtering mask and enable bit */
+#define XPS_L2CC_ADDR_FILTER_VALID_MASK	0xFFF00000U	/* Address filtering valid bits*/
+#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001U	/* Address filtering enable bit*/
+
+/* Debug control bits */
+#define XPS_L2CC_DEBUG_SPIDEN_MASK	0x00000004U	/* Debug SPIDEN bit */
+#define XPS_L2CC_DEBUG_DWB_MASK		0x00000002U	/* Debug DWB bit, forces write through */
+#define XPS_L2CC_DEBUG_DCL_MASK		0x00000002U	/* Debug DCL bit, disables cache line fill */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xl2cc_counter.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xl2cc_counter.c
new file mode 100644
index 0000000000000000000000000000000000000000..d6b88cb3960871015e280d99552a83aedb857522
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xl2cc_counter.c
@@ -0,0 +1,169 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xl2cc_counter.c
+*
+* This file contains APIs for configuring and controlling the event counters
+* in PL310 L2 cache controller. For more information about the event counters,
+* see xl2cc_counter.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+* 3.07a asa  08/30/12 Updated for CR 675636 to provide the L2 Base Address
+*		      inside the APIs
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include <stdint.h>
+#include "xparameters_ps.h"
+#include "xl2cc_counter.h"
+#include "xl2cc.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void XL2cc_EventCtrReset(void);
+
+/******************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* @brief	This function initializes the event counters in L2 Cache controller
+*			with a set of event codes specified by the user.
+*
+* @param	Event0: Event code for counter 0.
+* @param	Event1: Event code for counter 1.
+*
+* @return	None.
+*
+* @note		The definitions for event codes XL2CC_* can be found in
+*			xl2cc_counter.h.
+*
+*****************************************************************************/
+void XL2cc_EventCtrInit(s32 Event0, s32 Event1)
+{
+
+	/* Write event code into cnt1 cfg reg */
+	*((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_CTRL_OFFSET)) = (((u32)Event1) << 2);
+
+	/* Write event code into cnt0 cfg reg */
+	*((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_CTRL_OFFSET)) = (((u32)Event0) << 2);
+
+	/* Reset counters */
+	XL2cc_EventCtrReset();
+}
+
+
+/****************************************************************************/
+/**
+*
+* @brief	This function starts the event counters in L2 Cache controller.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XL2cc_EventCtrStart(void)
+{
+	u32 *LocalPtr;
+	LocalPtr = (u32 *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET);
+	XL2cc_EventCtrReset();
+
+	/* Enable counter */
+	/* *((volatile u32*)((void *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET))) = 1 */
+	*LocalPtr = (u32)1;
+}
+
+/****************************************************************************/
+/**
+*
+* @brief	This function disables the event counters in L2 Cache controller,
+*			saves the counter values and resets the counters.
+*
+* @param	EveCtr0: Output parameter which is used to return the value
+*			in event counter 0.
+*			EveCtr1: Output parameter which is used to return the value
+*			in event counter 1.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1)
+{
+	/* Disable counter */
+	*((volatile u32*) (XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0U;
+
+	/* Save counter values */
+	*EveCtr1 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_VAL_OFFSET));
+	*EveCtr0 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_VAL_OFFSET));
+
+	XL2cc_EventCtrReset();
+}
+
+/****************************************************************************/
+/**
+*
+* @brief	This function resets the event counters in L2 Cache controller.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XL2cc_EventCtrReset(void)
+{
+	*((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0x6U;
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xl2cc_counter.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xl2cc_counter.h
new file mode 100644
index 0000000000000000000000000000000000000000..8d0a61f07d193f41dc887b73052a3be9b1b5b78f
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xl2cc_counter.h
@@ -0,0 +1,113 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xl2cc_counter.h
+*
+* @addtogroup l2_event_counter_apis PL310 L2 Event Counters Functions
+*
+* xl2cc_counter.h contains APIs for configuring and controlling the event
+* counters in PL310 L2 cache controller.
+* PL310 has two event counters which can be used to count variety of events
+* like DRHIT, DRREQ, DWHIT, DWREQ, etc. xl2cc_counter.h contains definitions
+* for different configurations which can be used for the event counters to
+* count a set of events.
+*
+*
+* @{
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+* 3.07a asa  08/30/12 Updated for CR 675636 to provide the L2 Base Address
+*		      inside the APIs
+* </pre>
+*
+******************************************************************************/
+
+#ifndef L2CCCOUNTER_H /* prevent circular inclusions */
+#define L2CCCOUNTER_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants define the event codes for the event counters.
+ */
+#define XL2CC_CO		0x1
+#define XL2CC_DRHIT		0x2
+#define XL2CC_DRREQ		0x3
+#define XL2CC_DWHIT		0x4
+#define XL2CC_DWREQ		0x5
+#define XL2CC_DWTREQ		0x6
+#define XL2CC_IRHIT		0x7
+#define XL2CC_IRREQ		0x8
+#define XL2CC_WA		0x9
+#define XL2CC_IPFALLOC		0xa
+#define XL2CC_EPFHIT		0xb
+#define XL2CC_EPFALLOC		0xc
+#define XL2CC_SRRCVD		0xd
+#define XL2CC_SRCONF		0xe
+#define XL2CC_EPFRCVD		0xf
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+void XL2cc_EventCtrInit(s32 Event0, s32 Event1);
+void XL2cc_EventCtrStart(void);
+void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* L2CCCOUNTER_H */
+/**
+* @} End of "addtogroup l2_event_counter_apis".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xl2cc_counter.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xl2cc_counter.o
new file mode 100644
index 0000000000000000000000000000000000000000..d4d1899a4c6f5d761bfc0a82f8261305d38c0209
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xl2cc_counter.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xparameters_ps.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xparameters_ps.h
new file mode 100644
index 0000000000000000000000000000000000000000..ea0d2bcde03758e67891424f21de0a56fc582b72
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xparameters_ps.h
@@ -0,0 +1,333 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xparameters_ps.h
+*
+* This file contains the address definitions for the hard peripherals
+* attached to the ARM Cortex A9 core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 02/01/10 Initial version
+* 3.04a sdm     02/02/12 Removed some of the defines as they are being generated through
+*                        driver tcl
+* 5.0	pkp		01/16/15 Added interrupt ID definition of ttc for TEST APP
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XPARAMETERS_PS_H_
+#define _XPARAMETERS_PS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock
+ */
+
+/* Canonical definitions for DDR MEMORY */
+#define XPAR_DDR_MEM_BASEADDR		0x00000000U
+#define XPAR_DDR_MEM_HIGHADDR		0x3FFFFFFFU
+
+/* Canonical definitions for Interrupts  */
+#define XPAR_XUARTPS_0_INTR		XPS_UART0_INT_ID
+#define XPAR_XUARTPS_1_INTR		XPS_UART1_INT_ID
+#define XPAR_XUSBPS_0_INTR		XPS_USB0_INT_ID
+#define XPAR_XUSBPS_1_INTR		XPS_USB1_INT_ID
+#define XPAR_XIICPS_0_INTR		XPS_I2C0_INT_ID
+#define XPAR_XIICPS_1_INTR		XPS_I2C1_INT_ID
+#define XPAR_XSPIPS_0_INTR		XPS_SPI0_INT_ID
+#define XPAR_XSPIPS_1_INTR		XPS_SPI1_INT_ID
+#define XPAR_XCANPS_0_INTR		XPS_CAN0_INT_ID
+#define XPAR_XCANPS_1_INTR		XPS_CAN1_INT_ID
+#define XPAR_XGPIOPS_0_INTR		XPS_GPIO_INT_ID
+#define XPAR_XEMACPS_0_INTR		XPS_GEM0_INT_ID
+#define XPAR_XEMACPS_0_WAKE_INTR	XPS_GEM0_WAKE_INT_ID
+#define XPAR_XEMACPS_1_INTR		XPS_GEM1_INT_ID
+#define XPAR_XEMACPS_1_WAKE_INTR	XPS_GEM1_WAKE_INT_ID
+#define XPAR_XSDIOPS_0_INTR		XPS_SDIO0_INT_ID
+#define XPAR_XQSPIPS_0_INTR		XPS_QSPI_INT_ID
+#define XPAR_XSDIOPS_1_INTR		XPS_SDIO1_INT_ID
+#define XPAR_XWDTPS_0_INTR		XPS_WDT_INT_ID
+#define XPAR_XDCFG_0_INTR		XPS_DVC_INT_ID
+#define XPAR_SCUTIMER_INTR		XPS_SCU_TMR_INT_ID
+#define XPAR_SCUWDT_INTR		XPS_SCU_WDT_INT_ID
+#define XPAR_XTTCPS_0_INTR		XPS_TTC0_0_INT_ID
+#define XPAR_XTTCPS_1_INTR		XPS_TTC0_1_INT_ID
+#define XPAR_XTTCPS_2_INTR		XPS_TTC0_2_INT_ID
+#define XPAR_XTTCPS_3_INTR		XPS_TTC1_0_INT_ID
+#define XPAR_XTTCPS_4_INTR		XPS_TTC1_1_INT_ID
+#define XPAR_XTTCPS_5_INTR		XPS_TTC1_2_INT_ID
+#define XPAR_XDMAPS_0_FAULT_INTR	XPS_DMA0_ABORT_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_0	XPS_DMA0_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_1	XPS_DMA1_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_2	XPS_DMA2_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_3	XPS_DMA3_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_4	XPS_DMA4_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_5	XPS_DMA5_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_6	XPS_DMA6_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_7	XPS_DMA7_INT_ID
+
+
+#define XPAR_XQSPIPS_0_LINEAR_BASEADDR	XPS_QSPI_LINEAR_BASEADDR
+#define XPAR_XPARPORTPS_CTRL_BASEADDR	XPS_PARPORT_CRTL_BASEADDR
+
+
+
+/* Canonical definitions for DMAC */
+
+
+/* Canonical definitions for WDT */
+
+/* Canonical definitions for SLCR */
+#define XPAR_XSLCR_NUM_INSTANCES	1U
+#define XPAR_XSLCR_0_DEVICE_ID		0U
+#define XPAR_XSLCR_0_BASEADDR		XPS_SYS_CTRL_BASEADDR
+
+/* Canonical definitions for SCU GIC */
+#define XPAR_SCUGIC_NUM_INSTANCES	1U
+#define XPAR_SCUGIC_SINGLE_DEVICE_ID	0U
+#define XPAR_SCUGIC_CPU_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00000100U)
+#define XPAR_SCUGIC_DIST_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00001000U)
+#define XPAR_SCUGIC_ACK_BEFORE		0U
+
+/* Canonical definitions for Global Timer */
+#define XPAR_GLOBAL_TMR_NUM_INSTANCES	1U
+#define XPAR_GLOBAL_TMR_DEVICE_ID	0U
+#define XPAR_GLOBAL_TMR_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00000200U)
+#define XPAR_GLOBAL_TMR_INTR		XPS_GLOBAL_TMR_INT_ID
+
+
+/* Xilinx Parallel Flash Library (XilFlash) User Settings */
+#define XPAR_AXI_EMC
+
+
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock. These have been put for bacwards compatibilty
+ */
+
+#define XPS_PERIPHERAL_BASEADDR		0xE0000000U
+#define XPS_UART0_BASEADDR		0xE0000000U
+#define XPS_UART1_BASEADDR		0xE0001000U
+#define XPS_USB0_BASEADDR		0xE0002000U
+#define XPS_USB1_BASEADDR		0xE0003000U
+#define XPS_I2C0_BASEADDR		0xE0004000U
+#define XPS_I2C1_BASEADDR		0xE0005000U
+#define XPS_SPI0_BASEADDR		0xE0006000U
+#define XPS_SPI1_BASEADDR		0xE0007000U
+#define XPS_CAN0_BASEADDR		0xE0008000U
+#define XPS_CAN1_BASEADDR		0xE0009000U
+#define XPS_GPIO_BASEADDR		0xE000A000U
+#define XPS_GEM0_BASEADDR		0xE000B000U
+#define XPS_GEM1_BASEADDR		0xE000C000U
+#define XPS_QSPI_BASEADDR		0xE000D000U
+#define XPS_PARPORT_CRTL_BASEADDR	0xE000E000U
+#define XPS_SDIO0_BASEADDR		0xE0100000U
+#define XPS_SDIO1_BASEADDR		0xE0101000U
+#define XPS_IOU_BUS_CFG_BASEADDR	0xE0200000U
+#define XPS_NAND_BASEADDR		0xE1000000U
+#define XPS_PARPORT0_BASEADDR		0xE2000000U
+#define XPS_PARPORT1_BASEADDR		0xE4000000U
+#define XPS_QSPI_LINEAR_BASEADDR	0xFC000000U
+#define XPS_SYS_CTRL_BASEADDR		0xF8000000U	/* AKA SLCR */
+#define XPS_TTC0_BASEADDR		0xF8001000U
+#define XPS_TTC1_BASEADDR		0xF8002000U
+#define XPS_DMAC0_SEC_BASEADDR		0xF8003000U
+#define XPS_DMAC0_NON_SEC_BASEADDR	0xF8004000U
+#define XPS_WDT_BASEADDR		0xF8005000U
+#define XPS_DDR_CTRL_BASEADDR		0xF8006000U
+#define XPS_DEV_CFG_APB_BASEADDR	0xF8007000U
+#define XPS_AFI0_BASEADDR		0xF8008000U
+#define XPS_AFI1_BASEADDR		0xF8009000U
+#define XPS_AFI2_BASEADDR		0xF800A000U
+#define XPS_AFI3_BASEADDR		0xF800B000U
+#define XPS_OCM_BASEADDR		0xF800C000U
+#define XPS_EFUSE_BASEADDR		0xF800D000U
+#define XPS_CORESIGHT_BASEADDR		0xF8800000U
+#define XPS_TOP_BUS_CFG_BASEADDR	0xF8900000U
+#define XPS_SCU_PERIPH_BASE		0xF8F00000U
+#define XPS_L2CC_BASEADDR		0xF8F02000U
+#define XPS_SAM_RAM_BASEADDR		0xFFFC0000U
+#define XPS_FPGA_AXI_S0_BASEADDR	0x40000000U
+#define XPS_FPGA_AXI_S1_BASEADDR	0x80000000U
+#define XPS_IOU_S_SWITCH_BASEADDR	0xE0000000U
+#define XPS_PERIPH_APB_BASEADDR		0xF8000000U
+
+/* Shared Peripheral Interrupts (SPI) */
+#define XPS_CORE_PARITY0_INT_ID		32U
+#define XPS_CORE_PARITY1_INT_ID		33U
+#define XPS_L2CC_INT_ID			34U
+#define XPS_OCMINTR_INT_ID		35U
+#define XPS_ECC_INT_ID			36U
+#define XPS_PMU0_INT_ID			37U
+#define XPS_PMU1_INT_ID			38U
+#define XPS_SYSMON_INT_ID		39U
+#define XPS_DVC_INT_ID			40U
+#define XPS_WDT_INT_ID			41U
+#define XPS_TTC0_0_INT_ID		42U
+#define XPS_TTC0_1_INT_ID		43U
+#define XPS_TTC0_2_INT_ID 		44U
+#define XPS_DMA0_ABORT_INT_ID		45U
+#define XPS_DMA0_INT_ID			46U
+#define XPS_DMA1_INT_ID			47U
+#define XPS_DMA2_INT_ID			48U
+#define XPS_DMA3_INT_ID			49U
+#define XPS_SMC_INT_ID			50U
+#define XPS_QSPI_INT_ID			51U
+#define XPS_GPIO_INT_ID			52U
+#define XPS_USB0_INT_ID			53U
+#define XPS_GEM0_INT_ID			54U
+#define XPS_GEM0_WAKE_INT_ID		55U
+#define XPS_SDIO0_INT_ID		56U
+#define XPS_I2C0_INT_ID			57U
+#define XPS_SPI0_INT_ID			58U
+#define XPS_UART0_INT_ID		59U
+#define XPS_CAN0_INT_ID			60U
+#define XPS_FPGA0_INT_ID		61U
+#define XPS_FPGA1_INT_ID		62U
+#define XPS_FPGA2_INT_ID		63U
+#define XPS_FPGA3_INT_ID		64U
+#define XPS_FPGA4_INT_ID		65U
+#define XPS_FPGA5_INT_ID		66U
+#define XPS_FPGA6_INT_ID		67U
+#define XPS_FPGA7_INT_ID		68U
+#define XPS_TTC1_0_INT_ID		69U
+#define XPS_TTC1_1_INT_ID		70U
+#define XPS_TTC1_2_INT_ID		71U
+#define XPS_DMA4_INT_ID			72U
+#define XPS_DMA5_INT_ID			73U
+#define XPS_DMA6_INT_ID			74U
+#define XPS_DMA7_INT_ID			75U
+#define XPS_USB1_INT_ID			76U
+#define XPS_GEM1_INT_ID			77U
+#define XPS_GEM1_WAKE_INT_ID		78U
+#define XPS_SDIO1_INT_ID		79U
+#define XPS_I2C1_INT_ID			80U
+#define XPS_SPI1_INT_ID			81U
+#define XPS_UART1_INT_ID		82U
+#define XPS_CAN1_INT_ID			83U
+#define XPS_FPGA8_INT_ID		84U
+#define XPS_FPGA9_INT_ID		85U
+#define XPS_FPGA10_INT_ID		86U
+#define XPS_FPGA11_INT_ID		87U
+#define XPS_FPGA12_INT_ID		88U
+#define XPS_FPGA13_INT_ID		89U
+#define XPS_FPGA14_INT_ID		90U
+#define XPS_FPGA15_INT_ID		91U
+
+/* Private Peripheral Interrupts (PPI) */
+#define XPS_GLOBAL_TMR_INT_ID		27U	/* SCU Global Timer interrupt */
+#define XPS_FIQ_INT_ID			28U	/* FIQ from FPGA fabric */
+#define XPS_SCU_TMR_INT_ID		29U	/* SCU Private Timer interrupt */
+#define XPS_SCU_WDT_INT_ID		30U	/* SCU Private WDT interrupt */
+#define XPS_IRQ_INT_ID			31U	/* IRQ from FPGA fabric */
+
+
+/* REDEFINES for TEST APP */
+/* Definitions for UART */
+#define XPAR_PS7_UART_0_INTR		XPS_UART0_INT_ID
+#define XPAR_PS7_UART_1_INTR		XPS_UART1_INT_ID
+#define XPAR_PS7_USB_0_INTR		XPS_USB0_INT_ID
+#define XPAR_PS7_USB_1_INTR		XPS_USB1_INT_ID
+#define XPAR_PS7_I2C_0_INTR		XPS_I2C0_INT_ID
+#define XPAR_PS7_I2C_1_INTR		XPS_I2C1_INT_ID
+#define XPAR_PS7_SPI_0_INTR		XPS_SPI0_INT_ID
+#define XPAR_PS7_SPI_1_INTR		XPS_SPI1_INT_ID
+#define XPAR_PS7_CAN_0_INTR		XPS_CAN0_INT_ID
+#define XPAR_PS7_CAN_1_INTR		XPS_CAN1_INT_ID
+#define XPAR_PS7_GPIO_0_INTR		XPS_GPIO_INT_ID
+#define XPAR_PS7_ETHERNET_0_INTR	XPS_GEM0_INT_ID
+#define XPAR_PS7_ETHERNET_0_WAKE_INTR	XPS_GEM0_WAKE_INT_ID
+#define XPAR_PS7_ETHERNET_1_INTR	XPS_GEM1_INT_ID
+#define XPAR_PS7_ETHERNET_1_WAKE_INTR	XPS_GEM1_WAKE_INT_ID
+#define XPAR_PS7_QSPI_0_INTR		XPS_QSPI_INT_ID
+#define XPAR_PS7_WDT_0_INTR		XPS_WDT_INT_ID
+#define XPAR_PS7_SCUWDT_0_INTR		XPS_SCU_WDT_INT_ID
+#define XPAR_PS7_SCUTIMER_0_INTR	XPS_SCU_TMR_INT_ID
+#define XPAR_PS7_XADC_0_INTR		XPS_SYSMON_INT_ID
+#define XPAR_PS7_TTC_0_INTR         XPS_TTC0_0_INT_ID
+#define XPAR_PS7_TTC_1_INTR         XPS_TTC0_1_INT_ID
+#define XPAR_PS7_TTC_2_INTR         XPS_TTC0_2_INT_ID
+#define XPAR_PS7_TTC_3_INTR         XPS_TTC1_0_INT_ID
+#define XPAR_PS7_TTC_4_INTR         XPS_TTC1_1_INT_ID
+#define XPAR_PS7_TTC_5_INTR         XPS_TTC1_2_INT_ID
+
+#define XPAR_XADCPS_INT_ID		XPS_SYSMON_INT_ID
+
+/* For backwards compatibilty */
+#define XPAR_XUARTPS_0_CLOCK_HZ		XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
+#define XPAR_XUARTPS_1_CLOCK_HZ		XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
+#define XPAR_XTTCPS_0_CLOCK_HZ		XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_1_CLOCK_HZ		XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_2_CLOCK_HZ		XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_3_CLOCK_HZ		XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_4_CLOCK_HZ		XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_5_CLOCK_HZ		XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
+#define XPAR_XIICPS_0_CLOCK_HZ		XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
+#define XPAR_XIICPS_1_CLOCK_HZ		XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
+
+#define XPAR_XQSPIPS_0_CLOCK_HZ		XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
+
+#ifdef XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+#endif
+
+#ifdef XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
+#endif
+
+#define XPAR_SCUTIMER_DEVICE_ID		0U
+#define XPAR_SCUWDT_DEVICE_ID		0U
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xplatform_info.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xplatform_info.c
new file mode 100644
index 0000000000000000000000000000000000000000..d196ceaa719c4e9c1281e66b6b72fba5f9406469
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xplatform_info.c
@@ -0,0 +1,129 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xplatform_info.c
+*
+* This file contains information about hardware for which the code is built
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 5.00  pkp  12/15/14 Initial release
+* 5.04  pkp  01/12/16 Added platform information support for Cortex-A53 32bit
+*					  mode
+* 6.00  mus  17/08/16 Removed unused variable from XGetPlatform_Info
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* @brief    This API is used to provide information about platform
+*
+* @param    None.
+*
+* @return   The information about platform defined in xplatform_info.h
+*
+******************************************************************************/
+u32 XGetPlatform_Info()
+{
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+	return XPLAT_ZYNQ_ULTRA_MP;
+#elif (__microblaze__)
+	return XPLAT_MICROBLAZE;
+#else
+	return XPLAT_ZYNQ;
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    This API is used to provide information about zynq ultrascale MP platform
+*
+* @param    None.
+*
+* @return   The information about zynq ultrascale MP platform defined in
+*			xplatform_info.h
+*
+******************************************************************************/
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGet_Zynq_UltraMp_Platform_info()
+{
+	u32 reg;
+	reg = ((Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET) >> 12U )& XPLAT_INFO_MASK);
+	return reg;
+}
+#endif
+
+/*****************************************************************************/
+/**
+*
+* @brief    This API is used to provide information about PS Silicon version
+*
+* @param    None.
+*
+* @return   The information about PS Silicon version.
+*
+******************************************************************************/
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGetPSVersion_Info()
+{
+	u32 reg;
+	reg = (Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET)
+			& XPS_VERSION_INFO_MASK);
+	return reg;
+}
+#endif
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xplatform_info.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xplatform_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..27c0b58510fb77da17a9e7d2727c7ef27c3ecad5
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xplatform_info.h
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xplatform_info.h
+*
+* @addtogroup common_platform_info APIs to Get Platform Information
+*
+* The xplatform_info.h file contains definitions for various available Xilinx&reg;
+* platforms. Also, it contains prototype of APIs, which can be used to get the
+* platform information.
+*
+* @{
+******************************************************************************/
+
+#ifndef XPLATFORM_INFO_H		/* prevent circular inclusions */
+#define XPLATFORM_INFO_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XPAR_CSU_BASEADDR 0xFFCA0000U
+#define	XPAR_CSU_VER_OFFSET 0x00000044U
+
+#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
+#define XPLAT_ZYNQ_ULTRA_MP 0x1
+#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2
+#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3
+#define XPLAT_ZYNQ 0x4
+#define XPLAT_MICROBLAZE 0x5
+
+#define XPS_VERSION_1 0x0
+#define XPS_VERSION_2 0x1
+
+#define XPLAT_INFO_MASK (0xF)
+#define XPS_VERSION_INFO_MASK (0xF)
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+u32 XGetPlatform_Info();
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGetPSVersion_Info();
+#endif
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGet_Zynq_UltraMp_Platform_info();
+#endif
+/************************** Function Prototypes ******************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_platform_info".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xplatform_info.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xplatform_info.o
new file mode 100644
index 0000000000000000000000000000000000000000..7df90af5f9dae8c63e9cddbee642224f49da6df3
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xplatform_info.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xpm_counter.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xpm_counter.c
new file mode 100644
index 0000000000000000000000000000000000000000..d0765b60076862a675c91d72797f82b86783d86f
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xpm_counter.c
@@ -0,0 +1,297 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpm_counter.c
+*
+* This file contains APIs for configuring and controlling the Cortex-A9
+* Performance Monitor Events. For more information about the event counters,
+* see xpm_counter.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+* 4.2	pkp	 07/21/14 Corrected reset value of event counter in function
+*					  Xpm_ResetEventCounters to fix CR#796275
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xpm_counter.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+typedef const u32 PmcrEventCfg32[XPM_CTRCOUNT];
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xpm_DisableEventCounters(void);
+void Xpm_EnableEventCounters (void);
+void Xpm_ResetEventCounters (void);
+
+/******************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* @brief	This function disables the Cortex A9 event counters.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_DisableEventCounters(void)
+{
+	/* Disable the event counters */
+	mtcp(XREG_CP15_COUNT_ENABLE_CLR, 0x3f);
+}
+
+/****************************************************************************/
+/**
+*
+* @brief	This function enables the Cortex A9 event counters.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_EnableEventCounters(void)
+{
+	/* Enable the event counters */
+	mtcp(XREG_CP15_COUNT_ENABLE_SET, 0x3f);
+}
+
+/****************************************************************************/
+/**
+*
+* @brief	This function resets the Cortex A9 event counters.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_ResetEventCounters(void)
+{
+	u32 Reg;
+#ifdef __GNUC__
+	Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL);
+#elif defined (__ICCARM__)
+	mfcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
+#else
+	{ register u32 C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL);
+	  Reg = C15Reg; }
+#endif
+	Reg |= (1U << 1U); /* reset event counters */
+	mtcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
+
+}
+
+/****************************************************************************/
+/**
+* @brief	This function configures the Cortex A9 event counters controller,
+*			with the event codes, in a configuration selected by the user and
+*			enables the counters.
+*
+* @param	PmcrCfg: Configuration value based on which the event counters
+*			are configured. XPM_CNTRCFG* values defined in xpm_counter.h can
+*			be utilized for setting configuration.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_SetEvents(s32 PmcrCfg)
+{
+	u32 Counter;
+	static PmcrEventCfg32 PmcrEvents[] = {
+	{
+		XPM_EVENT_SOFTINCR,
+		XPM_EVENT_INSRFETCH_CACHEREFILL,
+		XPM_EVENT_INSTRFECT_TLBREFILL,
+		XPM_EVENT_DATA_CACHEREFILL,
+		XPM_EVENT_DATA_CACHEACCESS,
+		XPM_EVENT_DATA_TLBREFILL
+	},
+	{
+		XPM_EVENT_DATA_READS,
+		XPM_EVENT_DATA_WRITE,
+		XPM_EVENT_EXCEPTION,
+		XPM_EVENT_EXCEPRETURN,
+		XPM_EVENT_CHANGECONTEXT,
+		XPM_EVENT_SW_CHANGEPC
+	},
+	{
+		XPM_EVENT_IMMEDBRANCH,
+		XPM_EVENT_UNALIGNEDACCESS,
+		XPM_EVENT_BRANCHMISS,
+		XPM_EVENT_CLOCKCYCLES,
+		XPM_EVENT_BRANCHPREDICT,
+		XPM_EVENT_JAVABYTECODE
+	},
+	{
+		XPM_EVENT_SWJAVABYTECODE,
+		XPM_EVENT_JAVABACKBRANCH,
+		XPM_EVENT_COHERLINEMISS,
+		XPM_EVENT_COHERLINEHIT,
+		XPM_EVENT_INSTRSTALL,
+		XPM_EVENT_DATASTALL
+	},
+	{
+		XPM_EVENT_MAINTLBSTALL,
+		XPM_EVENT_STREXPASS,
+		XPM_EVENT_STREXFAIL,
+		XPM_EVENT_DATAEVICT,
+		XPM_EVENT_NODISPATCH,
+		XPM_EVENT_ISSUEEMPTY
+	},
+	{
+		XPM_EVENT_INSTRRENAME,
+		XPM_EVENT_PREDICTFUNCRET,
+		XPM_EVENT_MAINEXEC,
+		XPM_EVENT_SECEXEC,
+		XPM_EVENT_LDRSTR,
+		XPM_EVENT_FLOATRENAME
+	},
+	{
+		XPM_EVENT_NEONRENAME,
+		XPM_EVENT_PLDSTALL,
+		XPM_EVENT_WRITESTALL,
+		XPM_EVENT_INSTRTLBSTALL,
+		XPM_EVENT_DATATLBSTALL,
+		XPM_EVENT_INSTR_uTLBSTALL
+	},
+	{
+		XPM_EVENT_DATA_uTLBSTALL,
+		XPM_EVENT_DMB_STALL,
+		XPM_EVENT_INT_CLKEN,
+		XPM_EVENT_DE_CLKEN,
+		XPM_EVENT_INSTRISB,
+		XPM_EVENT_INSTRDSB
+	},
+	{
+		XPM_EVENT_INSTRDMB,
+		XPM_EVENT_EXTINT,
+		XPM_EVENT_PLE_LRC,
+		XPM_EVENT_PLE_LRS,
+		XPM_EVENT_PLE_FLUSH,
+		XPM_EVENT_PLE_CMPL
+	},
+	{
+		XPM_EVENT_PLE_OVFL,
+		XPM_EVENT_PLE_PROG,
+		XPM_EVENT_PLE_LRC,
+		XPM_EVENT_PLE_LRS,
+		XPM_EVENT_PLE_FLUSH,
+		XPM_EVENT_PLE_CMPL
+	},
+	{
+		XPM_EVENT_DATASTALL,
+		XPM_EVENT_INSRFETCH_CACHEREFILL,
+		XPM_EVENT_INSTRFECT_TLBREFILL,
+		XPM_EVENT_DATA_CACHEREFILL,
+		XPM_EVENT_DATA_CACHEACCESS,
+		XPM_EVENT_DATA_TLBREFILL
+	},
+	};
+	const u32 *ptr = PmcrEvents[PmcrCfg];
+
+	Xpm_DisableEventCounters();
+
+	for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
+
+		/* Selecet event counter */
+		mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
+
+		/* Set the event */
+		mtcp(XREG_CP15_EVENT_TYPE_SEL, ptr[Counter]);
+	}
+
+	Xpm_ResetEventCounters();
+	Xpm_EnableEventCounters();
+}
+
+/****************************************************************************/
+/**
+*
+* @brief	This function disables the event counters and returns the counter
+*			values.
+*
+* @param	PmCtrValue: Pointer to an array of type u32 PmCtrValue[6].
+*			It is an output parameter which is used to return the PM
+*			counter values.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_GetEventCounters(u32 *PmCtrValue)
+{
+	u32 Counter;
+
+	Xpm_DisableEventCounters();
+
+	for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
+
+		mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
+#ifdef __GNUC__
+		PmCtrValue[Counter] = mfcp(XREG_CP15_PERF_MONITOR_COUNT);
+#elif defined (__ICCARM__)
+		mfcp(XREG_CP15_PERF_MONITOR_COUNT, PmCtrValue[Counter]);
+#else
+		{ register u32 Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT);
+		  PmCtrValue[Counter] = Cp15Reg; }
+#endif
+	}
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xpm_counter.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xpm_counter.h
new file mode 100644
index 0000000000000000000000000000000000000000..45f091982497d96d757ce80559712dbd227905e6
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xpm_counter.h
@@ -0,0 +1,575 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpm_counter.h
+*
+* @addtogroup a9_event_counter_apis Cortex A9 Event Counters Functions
+*
+* Cortex A9 event counter functions can be utilized to configure and control
+* the Cortex-A9 performance monitor events.
+*
+* Cortex-A9 performance monitor has six event counters which can be used to
+* count a variety of events described in Coretx-A9 TRM. xpm_counter.h defines
+* configurations XPM_CNTRCFGx which can be used to program the event counters
+* to count a set of events.
+*
+* @note
+* It doesn't handle the Cortex-A9 cycle counter, as the cycle counter is
+* being used for time keeping.
+*
+* @{
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XPMCOUNTER_H /* prevent circular inclusions */
+#define XPMCOUNTER_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include <stdint.h>
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/* Number of performance counters */
+#define XPM_CTRCOUNT 6U
+
+/* The following constants define the Cortex-A9 Performance Monitor Events */
+
+/*
+ * Software increment. The register is incremented only on writes to the
+ * Software Increment Register
+ */
+#define XPM_EVENT_SOFTINCR 0x00U
+
+/*
+ * Instruction fetch that causes a refill at (at least) the lowest level(s) of
+ * instruction or unified cache. Includes the speculative linefills in the
+ * count
+ */
+#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U
+
+/*
+ * Instruction fetch that causes a TLB refill at (at least) the lowest level of
+ * TLB. Includes the speculative requests in the count
+ */
+#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U
+
+/*
+ * Data read or write operation that causes a refill at (at least) the lowest
+ * level(s)of data or unified cache. Counts the number of allocations performed
+ * in the Data Cache due to a read or a write
+ */
+#define XPM_EVENT_DATA_CACHEREFILL 0x03U
+
+/*
+ * Data read or write operation that causes a cache access at (at least) the
+ * lowest level(s) of data or unified cache. This includes speculative reads
+ */
+#define XPM_EVENT_DATA_CACHEACCESS 0x04U
+
+/*
+ * Data read or write operation that causes a TLB refill at (at least) the
+ * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI,
+ * CP15 Cache operation by MVA and CP15 VA to PA operations
+ */
+#define XPM_EVENT_DATA_TLBREFILL 0x05U
+
+/*
+ * Data read architecturally executed. Counts the number of data read
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted LDR/LDM, as well as the reads due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_READS 0x06U
+
+/*
+ * Data write architecturally executed. Counts the number of data write
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted STR/STM, as well as the writes due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_WRITE 0x07U
+
+/* Exception taken. Counts the number of exceptions architecturally taken.*/
+#define XPM_EVENT_EXCEPTION 0x09U
+
+/* Exception return architecturally executed.*/
+#define XPM_EVENT_EXCEPRETURN 0x0AU
+
+/*
+ * Change to ContextID retired. Counts the number of instructions
+ * architecturally executed writing into the ContextID Register
+ */
+#define XPM_EVENT_CHANGECONTEXT 0x0BU
+
+/*
+ * Software change of PC, except by an exception, architecturally executed.
+ * Count the number of PC changes architecturally executed, excluding the PC
+ * changes due to taken exceptions
+ */
+#define XPM_EVENT_SW_CHANGEPC 0x0CU
+
+/*
+ * Immediate branch architecturally executed (taken or not taken). This includes
+ * the branches which are flushed due to a previous load/store which aborts
+ * late
+ */
+#define XPM_EVENT_IMMEDBRANCH 0x0DU
+
+/*
+ * Unaligned access architecturally executed. Counts the number of aborted
+ * unaligned accessed architecturally executed, and the number of not-aborted
+ * unaligned accesses, including the speculative ones
+ */
+#define XPM_EVENT_UNALIGNEDACCESS 0x0FU
+
+/*
+ * Branch mispredicted/not predicted. Counts the number of mispredicted or
+ * not-predicted branches executed. This includes the branches which are flushed
+ * due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHMISS 0x10U
+
+/*
+ * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This
+ * event is not exported on the PMUEVENT bus
+ */
+#define XPM_EVENT_CLOCKCYCLES 0x11U
+
+/*
+ * Branches or other change in program flow that could have been predicted by
+ * the branch prediction resources of the processor. This includes the branches
+ * which are flushed due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHPREDICT 0x12U
+
+/*
+ * Java bytecode execute. Counts the number of Java bytecodes being decoded,
+ * including speculative ones
+ */
+#define XPM_EVENT_JAVABYTECODE 0x40U
+
+/*
+ * Software Java bytecode executed. Counts the number of software java bytecodes
+ * being decoded, including speculative ones
+ */
+#define XPM_EVENT_SWJAVABYTECODE 0x41U
+
+/*
+ * Jazelle backward branches executed. Counts the number of Jazelle taken
+ * branches being executed. This includes the branches which are flushed due
+ * to a previous load/store which aborts late
+ */
+#define XPM_EVENT_JAVABACKBRANCH 0x42U
+
+/*
+ * Coherent linefill miss Counts the number of coherent linefill requests
+ * performed by the Cortex-A9 processor which also miss in all the other
+ * Cortex-A9 processors, meaning that the request is sent to the external
+ * memory
+ */
+#define XPM_EVENT_COHERLINEMISS 0x50U
+
+/*
+ * Coherent linefill hit. Counts the number of coherent linefill requests
+ * performed by the Cortex-A9 processor which hit in another Cortex-A9
+ * processor, meaning that the linefill data is fetched directly from the
+ * relevant Cortex-A9 cache
+ */
+#define XPM_EVENT_COHERLINEHIT 0x51U
+
+/*
+ * Instruction cache dependent stall cycles. Counts the number of cycles where
+ * the processor is ready to accept new instructions, but does not receive any
+ * due to the instruction side not being able to provide any and the
+ * instruction cache is currently performing at least one linefill
+ */
+#define XPM_EVENT_INSTRSTALL 0x60U
+
+/*
+ * Data cache dependent stall cycles. Counts the number of cycles where the core
+ * has some instructions that it cannot issue to any pipeline, and the Load
+ * Store unit has at least one pending linefill request, and no pending
+ */
+#define XPM_EVENT_DATASTALL 0x61U
+
+/*
+ * Main TLB miss stall cycles. Counts the number of cycles where the processor
+ * is stalled waiting for the completion of translation table walks from the
+ * main TLB. The processor stalls can be due to the instruction side not being
+ * able to provide the instructions, or to the data side not being able to
+ * provide the necessary data, due to them waiting for the main TLB translation
+ * table walk to complete
+ */
+#define XPM_EVENT_MAINTLBSTALL 0x62U
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * passed
+ */
+#define XPM_EVENT_STREXPASS 0x63U
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * failed
+ */
+#define XPM_EVENT_STREXFAIL 0x64U
+
+/*
+ * Data eviction. Counts the number of eviction requests due to a linefill in
+ * the data cache
+ */
+#define XPM_EVENT_DATAEVICT 0x65U
+
+/*
+ * Counts the number of cycles where the issue stage does not dispatch any
+ * instruction because it is empty or cannot dispatch any instructions
+ */
+#define XPM_EVENT_NODISPATCH 0x66U
+
+/*
+ * Counts the number of cycles where the issue stage is empty
+ */
+#define XPM_EVENT_ISSUEEMPTY 0x67U
+
+/*
+ * Counts the number of instructions going through the Register Renaming stage.
+ * This number is an approximate number of the total number of instructions
+ * speculatively executed, and even more approximate of the total number of
+ * instructions architecturally executed. The approximation depends mainly on
+ * the branch misprediction rate.
+ * The renaming stage can handle two instructions in the same cycle so the event
+ * is two bits long:
+ *    - b00 no instructions renamed
+ *    - b01 one instruction renamed
+ *    - b10 two instructions renamed
+ */
+#define XPM_EVENT_INSTRRENAME 0x68U
+
+/*
+ * Counts the number of procedure returns whose condition codes do not fail,
+ * excluding all returns from exception. This count includes procedure returns
+ * which are flushed due to a previous load/store which aborts late.
+ * Only the following instructions are reported:
+ * - BX R14
+ * - MOV PC LR
+ * - POP {..,pc}
+ * - LDR pc,[sp],#offset
+ * The following instructions are not reported:
+ * - LDMIA R9!,{..,PC} (ThumbEE state only)
+ * - LDR PC,[R9],#offset (ThumbEE state only)
+ * - BX R0 (Rm != R14)
+ * - MOV PC,R0 (Rm != R14)
+ * - LDM SP,{...,PC} (writeback not specified)
+ * - LDR PC,[SP,#offset] (wrong addressing mode)
+ */
+#define XPM_EVENT_PREDICTFUNCRET 0x6EU
+
+/*
+ * Counts the number of instructions being executed in the main execution
+ * pipeline of the processor, the multiply pipeline and arithmetic logic unit
+ * pipeline. The counted instructions are still speculative
+ */
+#define XPM_EVENT_MAINEXEC 0x70U
+
+/*
+ * Counts the number of instructions being executed in the processor second
+ * execution pipeline (ALU). The counted instructions are still speculative
+ */
+#define XPM_EVENT_SECEXEC 0x71U
+
+/*
+ * Counts the number of instructions being executed in the Load/Store unit. The
+ * counted instructions are still speculative
+ */
+#define XPM_EVENT_LDRSTR 0x72U
+
+/*
+ * Counts the number of Floating-point instructions going through the Register
+ * Rename stage. Instructions are still speculative in this stage.
+ *Two floating-point instructions can be renamed in the same cycle so the event
+ * is two bitslong:
+ *0b00 no floating-point instruction renamed
+ *0b01 one floating-point instruction renamed
+ *0b10 two floating-point instructions renamed
+ */
+#define XPM_EVENT_FLOATRENAME 0x73U
+
+/*
+ * Counts the number of Neon instructions going through the Register Rename
+ * stage.Instructions are still speculative in this stage.
+ * Two NEON instructions can be renamed in the same cycle so the event is two
+ * bits long:
+ *0b00 no NEON instruction renamed
+ *0b01 one NEON instruction renamed
+ *0b10 two NEON instructions renamed
+ */
+#define XPM_EVENT_NEONRENAME 0x74U
+
+/*
+ * Counts the number of cycles where the processor is stalled because PLD slots
+ * are all full
+ */
+#define XPM_EVENT_PLDSTALL 0x80U
+
+/*
+ * Counts the number of cycles when the processor is stalled and the data side
+ * is stalled too because it is full and executing writes to the external
+ * memory
+ */
+#define XPM_EVENT_WRITESTALL 0x81U
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the instruction side
+ */
+#define XPM_EVENT_INSTRTLBSTALL 0x82U
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the data side
+ */
+#define XPM_EVENT_DATATLBSTALL 0x83U
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the instruction
+ * side. This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_INSTR_uTLBSTALL 0x84U
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the data side.
+ * This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_DATA_uTLBSTALL 0x85U
+
+/*
+ * Counts the number of stall cycles because of the execution of a DMB memory
+ * barrier. This includes all DMB instructions being executed, even
+ * speculatively
+ */
+#define XPM_EVENT_DMB_STALL 0x86U
+
+/*
+ * Counts the number of cycles during which the integer core clock is enabled
+ */
+#define XPM_EVENT_INT_CLKEN 0x8AU
+
+/*
+ * Counts the number of cycles during which the Data Engine clock is enabled
+ */
+#define XPM_EVENT_DE_CLKEN 0x8BU
+
+/*
+ * Counts the number of ISB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRISB 0x90U
+
+/*
+ * Counts the number of DSB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRDSB 0x91U
+
+/*
+ * Counts the number of DMB instructions speculatively executed
+ */
+#define XPM_EVENT_INSTRDMB 0x92U
+
+/*
+ * Counts the number of external interrupts executed by the processor
+ */
+#define XPM_EVENT_EXTINT 0x93U
+
+/*
+ * PLE cache line request completed
+ */
+#define XPM_EVENT_PLE_LRC 0xA0U
+
+/*
+ * PLE cache line request skipped
+ */
+#define XPM_EVENT_PLE_LRS 0xA1U
+
+/*
+ * PLE FIFO flush
+ */
+#define XPM_EVENT_PLE_FLUSH 0xA2U
+
+/*
+ * PLE request complete
+ */
+#define XPM_EVENT_PLE_CMPL 0xA3U
+
+/*
+ * PLE FIFO overflow
+ */
+#define XPM_EVENT_PLE_OVFL 0xA4U
+
+/*
+ * PLE request programmed
+ */
+#define XPM_EVENT_PLE_PROG 0xA5U
+
+/*
+ * The following constants define the configurations for Cortex-A9 Performance
+ * Monitor Events. Each configuration configures the event counters for a set
+ * of events.
+ * -----------------------------------------------
+ * Config		PmCtr0... PmCtr5
+ * -----------------------------------------------
+ * XPM_CNTRCFG1		{ XPM_EVENT_SOFTINCR,
+ *			  XPM_EVENT_INSRFETCH_CACHEREFILL,
+ *			  XPM_EVENT_INSTRFECT_TLBREFILL,
+ *			  XPM_EVENT_DATA_CACHEREFILL,
+ *			  XPM_EVENT_DATA_CACHEACCESS,
+ *			  XPM_EVENT_DATA_TLBREFILL }
+ *
+ * XPM_CNTRCFG2		{ XPM_EVENT_DATA_READS,
+ *			  XPM_EVENT_DATA_WRITE,
+ *			  XPM_EVENT_EXCEPTION,
+ *			  XPM_EVENT_EXCEPRETURN,
+ *			  XPM_EVENT_CHANGECONTEXT,
+ *			  XPM_EVENT_SW_CHANGEPC }
+ *
+ * XPM_CNTRCFG3		{ XPM_EVENT_IMMEDBRANCH,
+ *			  XPM_EVENT_UNALIGNEDACCESS,
+ *			  XPM_EVENT_BRANCHMISS,
+ *			  XPM_EVENT_CLOCKCYCLES,
+ *			  XPM_EVENT_BRANCHPREDICT,
+ *			  XPM_EVENT_JAVABYTECODE }
+ *
+ * XPM_CNTRCFG4		{ XPM_EVENT_SWJAVABYTECODE,
+ *			  XPM_EVENT_JAVABACKBRANCH,
+ *			  XPM_EVENT_COHERLINEMISS,
+ *			  XPM_EVENT_COHERLINEHIT,
+ *			  XPM_EVENT_INSTRSTALL,
+ *			  XPM_EVENT_DATASTALL }
+ *
+ * XPM_CNTRCFG5		{ XPM_EVENT_MAINTLBSTALL,
+ *			  XPM_EVENT_STREXPASS,
+ *			  XPM_EVENT_STREXFAIL,
+ *			  XPM_EVENT_DATAEVICT,
+ *			  XPM_EVENT_NODISPATCH,
+ *			  XPM_EVENT_ISSUEEMPTY }
+ *
+ * XPM_CNTRCFG6		{ XPM_EVENT_INSTRRENAME,
+ *			  XPM_EVENT_PREDICTFUNCRET,
+ *			  XPM_EVENT_MAINEXEC,
+ *			  XPM_EVENT_SECEXEC,
+ *			  XPM_EVENT_LDRSTR,
+ *			  XPM_EVENT_FLOATRENAME }
+ *
+ * XPM_CNTRCFG7		{ XPM_EVENT_NEONRENAME,
+ *			  XPM_EVENT_PLDSTALL,
+ *			  XPM_EVENT_WRITESTALL,
+ *			  XPM_EVENT_INSTRTLBSTALL,
+ *			  XPM_EVENT_DATATLBSTALL,
+ *			  XPM_EVENT_INSTR_uTLBSTALL }
+ *
+ * XPM_CNTRCFG8		{ XPM_EVENT_DATA_uTLBSTALL,
+ *			  XPM_EVENT_DMB_STALL,
+ *			  XPM_EVENT_INT_CLKEN,
+ *			  XPM_EVENT_DE_CLKEN,
+ *			  XPM_EVENT_INSTRISB,
+ *			  XPM_EVENT_INSTRDSB }
+ *
+ * XPM_CNTRCFG9		{ XPM_EVENT_INSTRDMB,
+ *			  XPM_EVENT_EXTINT,
+ *			  XPM_EVENT_PLE_LRC,
+ *			  XPM_EVENT_PLE_LRS,
+ *			  XPM_EVENT_PLE_FLUSH,
+ *			  XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG10	{ XPM_EVENT_PLE_OVFL,
+ *			  XPM_EVENT_PLE_PROG,
+ *			  XPM_EVENT_PLE_LRC,
+ *			  XPM_EVENT_PLE_LRS,
+ *			  XPM_EVENT_PLE_FLUSH,
+ *			  XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG11	{ XPM_EVENT_DATASTALL,
+ *			  XPM_EVENT_INSRFETCH_CACHEREFILL,
+ *			  XPM_EVENT_INSTRFECT_TLBREFILL,
+ *			  XPM_EVENT_DATA_CACHEREFILL,
+ *			  XPM_EVENT_DATA_CACHEACCESS,
+ *			  XPM_EVENT_DATA_TLBREFILL }
+ */
+#define XPM_CNTRCFG1	0
+#define XPM_CNTRCFG2	1
+#define XPM_CNTRCFG3	2
+#define XPM_CNTRCFG4	3
+#define XPM_CNTRCFG5	4
+#define XPM_CNTRCFG6	5
+#define XPM_CNTRCFG7	6
+#define XPM_CNTRCFG8	7
+#define XPM_CNTRCFG9	8
+#define XPM_CNTRCFG10	9
+#define XPM_CNTRCFG11	10
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/* Interface fuctions to access perfromance counters from abstraction layer */
+void Xpm_SetEvents(s32 PmcrCfg);
+void Xpm_GetEventCounters(u32 *PmCtrValue);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_event_counter_apis".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xpm_counter.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xpm_counter.o
new file mode 100644
index 0000000000000000000000000000000000000000..0d35eb1596ec40a61dede4bfc1038e0f7ca7730e
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xpm_counter.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xpseudo_asm.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xpseudo_asm.h
new file mode 100644
index 0000000000000000000000000000000000000000..4ad9e5d73cf6aa041462b24325df210f40a23bd4
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xpseudo_asm.h
@@ -0,0 +1,77 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm.h
+*
+* @addtogroup a9_specific Cortex A9 Processor Specific Include Files
+*
+* The xpseudo_asm.h includes xreg_cortexa9.h and xpseudo_asm_gcc.h.
+*
+* The xreg_cortexa9.h file contains definitions for inline assembler code.
+* It provides inline definitions for Cortex A9 GPRs, SPRs, MPE registers,
+* co-processor registers and Debug registers.
+*
+* The xpseudo_asm_gcc.h contains the definitions for the most often used inline
+* assembler instructions, available as macros. These can be very useful for
+* tasks such as setting or getting special purpose registers, synchronization,
+* or cache manipulation etc. These inline assembler instructions can be used
+* from drivers and user applications written in C.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  10/18/09 First release
+* 3.04a sdm  01/02/12 Remove redundant dsb in mcr instruction.
+* </pre>
+*
+******************************************************************************/
+#ifndef XPSEUDO_ASM_H
+#define XPSEUDO_ASM_H
+
+#include "xreg_cortexa9.h"
+#ifdef __GNUC__
+ #include "xpseudo_asm_gcc.h"
+#elif defined (__ICCARM__)
+ #include "xpseudo_asm_iccarm.h"
+#else
+ #include "xpseudo_asm_rvct.h"
+#endif
+
+#endif /* XPSEUDO_ASM_H */
+/**
+* @} End of "addtogroup a9_specific".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xpseudo_asm_gcc.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xpseudo_asm_gcc.h
new file mode 100644
index 0000000000000000000000000000000000000000..1b67263940395d2ba4ce4fed0cc00c3327d9a44a
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xpseudo_asm_gcc.h
@@ -0,0 +1,249 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm_gcc.h
+*
+* This header file contains macros for using inline assembler code. It is
+* written specifically for the GNU compiler.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp		 05/21/14 First release
+* 6.0   mus      07/27/16 Consolidated file for a53,a9 and r5 processors
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XPSEUDO_ASM_GCC_H  /* prevent circular inclusions */
+#define XPSEUDO_ASM_GCC_H  /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/* necessary for pre-processor */
+#define stringify(s)	tostring(s)
+#define tostring(s)	#s
+
+#if defined (__aarch64__)
+/* pseudo assembler instructions */
+#define mfcpsr()	({u32 rval = 0U; \
+			   asm volatile("mrs %0,  DAIF" : "=r" (rval));\
+			  rval;\
+			 })
+
+#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v))
+
+#define cpsiei()	//__asm__ __volatile__("cpsie	i\n")
+#define cpsidi()	//__asm__ __volatile__("cpsid	i\n")
+
+#define cpsief()	//__asm__ __volatile__("cpsie	f\n")
+#define cpsidf()	//__asm__ __volatile__("cpsid	f\n")
+
+
+
+#define mtgpr(rn, v)	/*__asm__ __volatile__(\
+			  "mov r" stringify(rn) ", %0 \n"\
+			  : : "r" (v)\
+			)*/
+
+#define mfgpr(rn)	/*({u32 rval; \
+			  __asm__ __volatile__(\
+			    "mov %0,r" stringify(rn) "\n"\
+			    : "=r" (rval)\
+			  );\
+			  rval;\
+			 })*/
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb sy")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__("dsb sy")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__("dmb sy")
+
+
+/* Memory Operations */
+#define ldr(adr)	({u64 rval; \
+			  __asm__ __volatile__(\
+			    "ldr	%0,[%1]"\
+			    : "=r" (rval) : "r" (adr)\
+			  );\
+			  rval;\
+			 })
+
+#else
+
+/* pseudo assembler instructions */
+#define mfcpsr()	({u32 rval = 0U; \
+			  __asm__ __volatile__(\
+			    "mrs	%0, cpsr\n"\
+			    : "=r" (rval)\
+			  );\
+			  rval;\
+			 })
+
+#define mtcpsr(v)	__asm__ __volatile__(\
+			  "msr	cpsr,%0\n"\
+			  : : "r" (v)\
+			)
+
+#define cpsiei()	__asm__ __volatile__("cpsie	i\n")
+#define cpsidi()	__asm__ __volatile__("cpsid	i\n")
+
+#define cpsief()	__asm__ __volatile__("cpsie	f\n")
+#define cpsidf()	__asm__ __volatile__("cpsid	f\n")
+
+
+
+#define mtgpr(rn, v)	__asm__ __volatile__(\
+			  "mov r" stringify(rn) ", %0 \n"\
+			  : : "r" (v)\
+			)
+
+#define mfgpr(rn)	({u32 rval; \
+			  __asm__ __volatile__(\
+			    "mov %0,r" stringify(rn) "\n"\
+			    : "=r" (rval)\
+			  );\
+			  rval;\
+			 })
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
+
+
+/* Memory Operations */
+#define ldr(adr)	({u32 rval; \
+			  __asm__ __volatile__(\
+			    "ldr	%0,[%1]"\
+			    : "=r" (rval) : "r" (adr)\
+			  );\
+			  rval;\
+			 })
+
+#endif
+
+#define ldrb(adr)	({u8 rval; \
+			  __asm__ __volatile__(\
+			    "ldrb	%0,[%1]"\
+			    : "=r" (rval) : "r" (adr)\
+			  );\
+			  rval;\
+			 })
+
+#define str(adr, val)	__asm__ __volatile__(\
+			  "str	%0,[%1]\n"\
+			  : : "r" (val), "r" (adr)\
+			)
+
+#define strb(adr, val)	__asm__ __volatile__(\
+			  "strb	%0,[%1]\n"\
+			  : : "r" (val), "r" (adr)\
+			)
+
+/* Count leading zeroes (clz) */
+#define clz(arg)	({u8 rval; \
+			  __asm__ __volatile__(\
+			    "clz	%0,%1"\
+			    : "=r" (rval) : "r" (arg)\
+			  );\
+			  rval;\
+			 })
+
+#if defined (__aarch64__)
+#define mtcpdc(reg,val)	__asm__ __volatile__("dc " #reg ",%0"  : : "r" (val))
+#define mtcpic(reg,val)	__asm__ __volatile__("ic " #reg ",%0"  : : "r" (val))
+
+#define mtcpicall(reg)	__asm__ __volatile__("ic " #reg)
+#define mtcptlbi(reg)	__asm__ __volatile__("tlbi " #reg)
+#define mtcpat(reg,val)	__asm__ __volatile__("at " #reg ",%0"  : : "r" (val))
+/* CP15 operations */
+#define mfcp(reg)	({u64 rval = 0U;\
+			__asm__ __volatile__("mrs	%0, " #reg : "=r" (rval));\
+			rval;\
+			})
+
+#define mtcp(reg,val)	__asm__ __volatile__("msr " #reg ",%0"  : : "r" (val))
+
+#else
+/* CP15 operations */
+#define mtcp(rn, v)	__asm__ __volatile__(\
+			 "mcr " rn "\n"\
+			 : : "r" (v)\
+			);
+
+#define mfcp(rn)	({u32 rval = 0U; \
+			 __asm__ __volatile__(\
+			   "mrc " rn "\n"\
+			   : "=r" (rval)\
+			 );\
+			 rval;\
+			 })
+#endif
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XPSEUDO_ASM_GCC_H */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xreg_cortexa9.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xreg_cortexa9.h
new file mode 100644
index 0000000000000000000000000000000000000000..dc9a4ebd2c36ac3f03ad6816b05610129a6a7943
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xreg_cortexa9.h
@@ -0,0 +1,591 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xreg_cortexa9.h
+*
+* This header file contains definitions for using inline assembler code. It is
+* written specifically for the GNU, ARMCC compiler.
+*
+* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along
+* with the positions of the bits within the registers.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  10/20/09 First release
+* </pre>
+*
+******************************************************************************/
+#ifndef XREG_CORTEXA9_H
+#define XREG_CORTEXA9_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* GPRs */
+#define XREG_GPR0				r0
+#define XREG_GPR1				r1
+#define XREG_GPR2				r2
+#define XREG_GPR3				r3
+#define XREG_GPR4				r4
+#define XREG_GPR5				r5
+#define XREG_GPR6				r6
+#define XREG_GPR7				r7
+#define XREG_GPR8				r8
+#define XREG_GPR9				r9
+#define XREG_GPR10				r10
+#define XREG_GPR11				r11
+#define XREG_GPR12				r12
+#define XREG_GPR13				r13
+#define XREG_GPR14				r14
+#define XREG_GPR15				r15
+#define XREG_CPSR				cpsr
+
+/* Coprocessor number defines */
+#define XREG_CP0				0
+#define XREG_CP1				1
+#define XREG_CP2				2
+#define XREG_CP3				3
+#define XREG_CP4				4
+#define XREG_CP5				5
+#define XREG_CP6				6
+#define XREG_CP7				7
+#define XREG_CP8				8
+#define XREG_CP9				9
+#define XREG_CP10				10
+#define XREG_CP11				11
+#define XREG_CP12				12
+#define XREG_CP13				13
+#define XREG_CP14				14
+#define XREG_CP15				15
+
+/* Coprocessor control register defines */
+#define XREG_CR0				cr0
+#define XREG_CR1				cr1
+#define XREG_CR2				cr2
+#define XREG_CR3				cr3
+#define XREG_CR4				cr4
+#define XREG_CR5				cr5
+#define XREG_CR6				cr6
+#define XREG_CR7				cr7
+#define XREG_CR8				cr8
+#define XREG_CR9				cr9
+#define XREG_CR10				cr10
+#define XREG_CR11				cr11
+#define XREG_CR12				cr12
+#define XREG_CR13				cr13
+#define XREG_CR14				cr14
+#define XREG_CR15				cr15
+
+/* Current Processor Status Register (CPSR) Bits */
+#define XREG_CPSR_THUMB_MODE			0x20
+#define XREG_CPSR_MODE_BITS			0x1F
+#define XREG_CPSR_SYSTEM_MODE			0x1F
+#define XREG_CPSR_UNDEFINED_MODE		0x1B
+#define XREG_CPSR_DATA_ABORT_MODE		0x17
+#define XREG_CPSR_SVC_MODE			0x13
+#define XREG_CPSR_IRQ_MODE			0x12
+#define XREG_CPSR_FIQ_MODE			0x11
+#define XREG_CPSR_USER_MODE			0x10
+
+#define XREG_CPSR_IRQ_ENABLE			0x80
+#define XREG_CPSR_FIQ_ENABLE			0x40
+
+#define XREG_CPSR_N_BIT				0x80000000
+#define XREG_CPSR_Z_BIT				0x40000000
+#define XREG_CPSR_C_BIT				0x20000000
+#define XREG_CPSR_V_BIT				0x10000000
+
+
+/* CP15 defines */
+#if defined (__GNUC__) || defined (__ICCARM__)
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID			"p15, 0, %0,  c0,  c0, 0"
+#define XREG_CP15_CACHE_TYPE			"p15, 0, %0,  c0,  c0, 1"
+#define XREG_CP15_TCM_TYPE			"p15, 0, %0,  c0,  c0, 2"
+#define XREG_CP15_TLB_TYPE			"p15, 0, %0,  c0,  c0, 3"
+#define XREG_CP15_MULTI_PROC_AFFINITY		"p15, 0, %0,  c0,  c0, 5"
+
+#define XREG_CP15_PROC_FEATURE_0		"p15, 0, %0,  c0,  c1, 0"
+#define XREG_CP15_PROC_FEATURE_1		"p15, 0, %0,  c0,  c1, 1"
+#define XREG_CP15_DEBUG_FEATURE_0		"p15, 0, %0,  c0,  c1, 2"
+#define XREG_CP15_MEMORY_FEATURE_0		"p15, 0, %0,  c0,  c1, 4"
+#define XREG_CP15_MEMORY_FEATURE_1		"p15, 0, %0,  c0,  c1, 5"
+#define XREG_CP15_MEMORY_FEATURE_2		"p15, 0, %0,  c0,  c1, 6"
+#define XREG_CP15_MEMORY_FEATURE_3		"p15, 0, %0,  c0,  c1, 7"
+
+#define XREG_CP15_INST_FEATURE_0		"p15, 0, %0,  c0,  c2, 0"
+#define XREG_CP15_INST_FEATURE_1		"p15, 0, %0,  c0,  c2, 1"
+#define XREG_CP15_INST_FEATURE_2		"p15, 0, %0,  c0,  c2, 2"
+#define XREG_CP15_INST_FEATURE_3		"p15, 0, %0,  c0,  c2, 3"
+#define XREG_CP15_INST_FEATURE_4		"p15, 0, %0,  c0,  c2, 4"
+
+#define XREG_CP15_CACHE_SIZE_ID			"p15, 1, %0,  c0,  c0, 0"
+#define XREG_CP15_CACHE_LEVEL_ID		"p15, 1, %0,  c0,  c0, 1"
+#define XREG_CP15_AUXILARY_ID			"p15, 1, %0,  c0,  c0, 7"
+
+#define XREG_CP15_CACHE_SIZE_SEL		"p15, 2, %0,  c0,  c0, 0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL			"p15, 0, %0,  c1,  c0, 0"
+#define XREG_CP15_AUX_CONTROL			"p15, 0, %0,  c1,  c0, 1"
+#define XREG_CP15_CP_ACCESS_CONTROL		"p15, 0, %0,  c1,  c0, 2"
+
+#define XREG_CP15_SECURE_CONFIG			"p15, 0, %0,  c1,  c1, 0"
+#define XREG_CP15_SECURE_DEBUG_ENABLE		"p15, 0, %0,  c1,  c1, 1"
+#define XREG_CP15_NS_ACCESS_CONTROL		"p15, 0, %0,  c1,  c1, 2"
+#define XREG_CP15_VIRTUAL_CONTROL		"p15, 0, %0,  c1,  c1, 3"
+
+#else /* RVCT */
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID			"cp15:0:c0:c0:0"
+#define XREG_CP15_CACHE_TYPE			"cp15:0:c0:c0:1"
+#define XREG_CP15_TCM_TYPE			"cp15:0:c0:c0:2"
+#define XREG_CP15_TLB_TYPE			"cp15:0:c0:c0:3"
+#define XREG_CP15_MULTI_PROC_AFFINITY		"cp15:0:c0:c0:5"
+
+#define XREG_CP15_PROC_FEATURE_0		"cp15:0:c0:c1:0"
+#define XREG_CP15_PROC_FEATURE_1		"cp15:0:c0:c1:1"
+#define XREG_CP15_DEBUG_FEATURE_0		"cp15:0:c0:c1:2"
+#define XREG_CP15_MEMORY_FEATURE_0		"cp15:0:c0:c1:4"
+#define XREG_CP15_MEMORY_FEATURE_1		"cp15:0:c0:c1:5"
+#define XREG_CP15_MEMORY_FEATURE_2		"cp15:0:c0:c1:6"
+#define XREG_CP15_MEMORY_FEATURE_3		"cp15:0:c0:c1:7"
+
+#define XREG_CP15_INST_FEATURE_0		"cp15:0:c0:c2:0"
+#define XREG_CP15_INST_FEATURE_1		"cp15:0:c0:c2:1"
+#define XREG_CP15_INST_FEATURE_2		"cp15:0:c0:c2:2"
+#define XREG_CP15_INST_FEATURE_3		"cp15:0:c0:c2:3"
+#define XREG_CP15_INST_FEATURE_4		"cp15:0:c0:c2:4"
+
+#define XREG_CP15_CACHE_SIZE_ID			"cp15:1:c0:c0:0"
+#define XREG_CP15_CACHE_LEVEL_ID		"cp15:1:c0:c0:1"
+#define XREG_CP15_AUXILARY_ID			"cp15:1:c0:c0:7"
+
+#define XREG_CP15_CACHE_SIZE_SEL		"cp15:2:c0:c0:0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL			"cp15:0:c1:c0:0"
+#define XREG_CP15_AUX_CONTROL			"cp15:0:c1:c0:1"
+#define XREG_CP15_CP_ACCESS_CONTROL		"cp15:0:c1:c0:2"
+
+#define XREG_CP15_SECURE_CONFIG			"cp15:0:c1:c1:0"
+#define XREG_CP15_SECURE_DEBUG_ENABLE		"cp15:0:c1:c1:1"
+#define XREG_CP15_NS_ACCESS_CONTROL		"cp15:0:c1:c1:2"
+#define XREG_CP15_VIRTUAL_CONTROL		"cp15:0:c1:c1:3"
+#endif
+
+/* XREG_CP15_CONTROL bit defines */
+#define XREG_CP15_CONTROL_TE_BIT		0x40000000U
+#define XREG_CP15_CONTROL_AFE_BIT		0x20000000U
+#define XREG_CP15_CONTROL_TRE_BIT		0x10000000U
+#define XREG_CP15_CONTROL_NMFI_BIT		0x08000000U
+#define XREG_CP15_CONTROL_EE_BIT		0x02000000U
+#define XREG_CP15_CONTROL_HA_BIT		0x00020000U
+#define XREG_CP15_CONTROL_RR_BIT		0x00004000U
+#define XREG_CP15_CONTROL_V_BIT			0x00002000U
+#define XREG_CP15_CONTROL_I_BIT			0x00001000U
+#define XREG_CP15_CONTROL_Z_BIT			0x00000800U
+#define XREG_CP15_CONTROL_SW_BIT		0x00000400U
+#define XREG_CP15_CONTROL_B_BIT			0x00000080U
+#define XREG_CP15_CONTROL_C_BIT			0x00000004U
+#define XREG_CP15_CONTROL_A_BIT			0x00000002U
+#define XREG_CP15_CONTROL_M_BIT			0x00000001U
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+/* C2 Register Defines */
+#define XREG_CP15_TTBR0				"p15, 0, %0,  c2,  c0, 0"
+#define XREG_CP15_TTBR1				"p15, 0, %0,  c2,  c0, 1"
+#define XREG_CP15_TTB_CONTROL			"p15, 0, %0,  c2,  c0, 2"
+
+/* C3 Register Defines */
+#define XREG_CP15_DOMAIN_ACCESS_CTRL		"p15, 0, %0,  c3,  c0, 0"
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS		"p15, 0, %0,  c5,  c0, 0"
+#define XREG_CP15_INST_FAULT_STATUS		"p15, 0, %0,  c5,  c0, 1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS		"p15, 0, %0,  c5,  c1, 0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS		"p15, 0, %0,  c5,  c1, 1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS		"p15, 0, %0,  c6,  c0, 0"
+#define XREG_CP15_INST_FAULT_ADDRESS		"p15, 0, %0,  c6,  c0, 2"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP				"p15, 0, %0,  c7,  c0, 4"
+
+#define XREG_CP15_INVAL_IC_POU_IS		"p15, 0, %0,  c7,  c1, 0"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_IS		"p15, 0, %0,  c7,  c1, 6"
+
+#define XREG_CP15_PHYS_ADDR			"p15, 0, %0,  c7,  c4, 0"
+
+#define XREG_CP15_INVAL_IC_POU			"p15, 0, %0,  c7,  c5, 0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU		"p15, 0, %0,  c7,  c5, 1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex A9.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER		"p15, 0, %0,  c7,  c5, 4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY		"p15, 0, %0,  c7,  c5, 6"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC		"p15, 0, %0,  c7,  c6, 1"
+#define XREG_CP15_INVAL_DC_LINE_SW		"p15, 0, %0,  c7,  c6, 2"
+
+#define XREG_CP15_VA_TO_PA_CURRENT_0		"p15, 0, %0,  c7,  c8, 0"
+#define XREG_CP15_VA_TO_PA_CURRENT_1		"p15, 0, %0,  c7,  c8, 1"
+#define XREG_CP15_VA_TO_PA_CURRENT_2		"p15, 0, %0,  c7,  c8, 2"
+#define XREG_CP15_VA_TO_PA_CURRENT_3		"p15, 0, %0,  c7,  c8, 3"
+
+#define XREG_CP15_VA_TO_PA_OTHER_0		"p15, 0, %0,  c7,  c8, 4"
+#define XREG_CP15_VA_TO_PA_OTHER_1		"p15, 0, %0,  c7,  c8, 5"
+#define XREG_CP15_VA_TO_PA_OTHER_2		"p15, 0, %0,  c7,  c8, 6"
+#define XREG_CP15_VA_TO_PA_OTHER_3		"p15, 0, %0,  c7,  c8, 7"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC		"p15, 0, %0,  c7, c10, 1"
+#define XREG_CP15_CLEAN_DC_LINE_SW		"p15, 0, %0,  c7, c10, 2"
+
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex A9.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER		"p15, 0, %0,  c7, c10, 4"
+#define XREG_CP15_DATA_MEMORY_BARRIER		"p15, 0, %0,  c7, c10, 5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU		"p15, 0, %0,  c7, c11, 1"
+
+#define XREG_CP15_NOP2				"p15, 0, %0,  c7, c13, 1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC	"p15, 0, %0,  c7, c14, 1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW	"p15, 0, %0,  c7, c14, 2"
+
+/* C8 Register Defines */
+#define XREG_CP15_INVAL_TLB_IS			"p15, 0, %0,  c8,  c3, 0"
+#define XREG_CP15_INVAL_TLB_MVA_IS		"p15, 0, %0,  c8,  c3, 1"
+#define XREG_CP15_INVAL_TLB_ASID_IS		"p15, 0, %0,  c8,  c3, 2"
+#define XREG_CP15_INVAL_TLB_MVA_ASID_IS		"p15, 0, %0,  c8,  c3, 3"
+
+#define XREG_CP15_INVAL_ITLB_UNLOCKED		"p15, 0, %0,  c8,  c5, 0"
+#define XREG_CP15_INVAL_ITLB_MVA		"p15, 0, %0,  c8,  c5, 1"
+#define XREG_CP15_INVAL_ITLB_ASID		"p15, 0, %0,  c8,  c5, 2"
+
+#define XREG_CP15_INVAL_DTLB_UNLOCKED		"p15, 0, %0,  c8,  c6, 0"
+#define XREG_CP15_INVAL_DTLB_MVA		"p15, 0, %0,  c8,  c6, 1"
+#define XREG_CP15_INVAL_DTLB_ASID		"p15, 0, %0,  c8,  c6, 2"
+
+#define XREG_CP15_INVAL_UTLB_UNLOCKED		"p15, 0, %0,  c8,  c7, 0"
+#define XREG_CP15_INVAL_UTLB_MVA		"p15, 0, %0,  c8,  c7, 1"
+#define XREG_CP15_INVAL_UTLB_ASID		"p15, 0, %0,  c8,  c7, 2"
+#define XREG_CP15_INVAL_UTLB_MVA_ASID		"p15, 0, %0,  c8,  c7, 3"
+
+/* C9 Register Defines */
+#define XREG_CP15_PERF_MONITOR_CTRL		"p15, 0, %0,  c9, c12, 0"
+#define XREG_CP15_COUNT_ENABLE_SET		"p15, 0, %0,  c9, c12, 1"
+#define XREG_CP15_COUNT_ENABLE_CLR		"p15, 0, %0,  c9, c12, 2"
+#define XREG_CP15_V_FLAG_STATUS			"p15, 0, %0,  c9, c12, 3"
+#define XREG_CP15_SW_INC			"p15, 0, %0,  c9, c12, 4"
+#define XREG_CP15_EVENT_CNTR_SEL		"p15, 0, %0,  c9, c12, 5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER		"p15, 0, %0,  c9, c13, 0"
+#define XREG_CP15_EVENT_TYPE_SEL		"p15, 0, %0,  c9, c13, 1"
+#define XREG_CP15_PERF_MONITOR_COUNT		"p15, 0, %0,  c9, c13, 2"
+
+#define XREG_CP15_USER_ENABLE			"p15, 0, %0,  c9, c14, 0"
+#define XREG_CP15_INTR_ENABLE_SET		"p15, 0, %0,  c9, c14, 1"
+#define XREG_CP15_INTR_ENABLE_CLR		"p15, 0, %0,  c9, c14, 2"
+
+/* C10 Register Defines */
+#define XREG_CP15_TLB_LOCKDWN			"p15, 0, %0, c10,  c0, 0"
+
+#define XREG_CP15_PRI_MEM_REMAP			"p15, 0, %0, c10,  c2, 0"
+#define XREG_CP15_NORM_MEM_REMAP		"p15, 0, %0, c10,  c2, 1"
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+#define XREG_CP15_VEC_BASE_ADDR			"p15, 0, %0, c12,  c0, 0"
+#define XREG_CP15_MONITOR_VEC_BASE_ADDR		"p15, 0, %0, c12,  c0, 1"
+
+#define XREG_CP15_INTERRUPT_STATUS		"p15, 0, %0, c12,  c1, 0"
+#define XREG_CP15_VIRTUALIZATION_INTR		"p15, 0, %0, c12,  c1, 1"
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID			"p15, 0, %0, c13,  c0, 1"
+#define USER_RW_THREAD_PID			"p15, 0, %0, c13,  c0, 2"
+#define USER_RO_THREAD_PID			"p15, 0, %0, c13,  c0, 3"
+#define USER_PRIV_THREAD_PID			"p15, 0, %0, c13,  c0, 4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_POWER_CTRL			"p15, 0, %0, c15,  c0, 0"
+#define XREG_CP15_CONFIG_BASE_ADDR		"p15, 4, %0, c15,  c0, 0"
+
+#define XREG_CP15_READ_TLB_ENTRY		"p15, 5, %0, c15,  c4, 2"
+#define XREG_CP15_WRITE_TLB_ENTRY		"p15, 5, %0, c15,  c4, 4"
+
+#define XREG_CP15_MAIN_TLB_VA			"p15, 5, %0, c15,  c5, 2"
+
+#define XREG_CP15_MAIN_TLB_PA			"p15, 5, %0, c15,  c6, 2"
+
+#define XREG_CP15_MAIN_TLB_ATTR			"p15, 5, %0, c15,  c7, 2"
+
+#else
+/* C2 Register Defines */
+#define XREG_CP15_TTBR0				"cp15:0:c2:c0:0"
+#define XREG_CP15_TTBR1				"cp15:0:c2:c0:1"
+#define XREG_CP15_TTB_CONTROL			"cp15:0:c2:c0:2"
+
+/* C3 Register Defines */
+#define XREG_CP15_DOMAIN_ACCESS_CTRL		"cp15:0:c3:c0:0"
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS		"cp15:0:c5:c0:0"
+#define XREG_CP15_INST_FAULT_STATUS		"cp15:0:c5:c0:1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS		"cp15:0:c5:c1:0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS		"cp15:0:c5:c1:1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS		"cp15:0:c6:c0:0"
+#define XREG_CP15_INST_FAULT_ADDRESS		"cp15:0:c6:c0:2"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP				"cp15:0:c7:c0:4"
+
+#define XREG_CP15_INVAL_IC_POU_IS		"cp15:0:c7:c1:0"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_IS		"cp15:0:c7:c1:6"
+
+#define XREG_CP15_PHYS_ADDR			"cp15:0:c7:c4:0"
+
+#define XREG_CP15_INVAL_IC_POU			"cp15:0:c7:c5:0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU		"cp15:0:c7:c5:1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex A9.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER		"cp15:0:c7:c5:4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY		"cp15:0:c7:c5:6"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC		"cp15:0:c7:c6:1"
+#define XREG_CP15_INVAL_DC_LINE_SW		"cp15:0:c7:c6:2"
+
+#define XREG_CP15_VA_TO_PA_CURRENT_0		"cp15:0:c7:c8:0"
+#define XREG_CP15_VA_TO_PA_CURRENT_1		"cp15:0:c7:c8:1"
+#define XREG_CP15_VA_TO_PA_CURRENT_2		"cp15:0:c7:c8:2"
+#define XREG_CP15_VA_TO_PA_CURRENT_3		"cp15:0:c7:c8:3"
+
+#define XREG_CP15_VA_TO_PA_OTHER_0		"cp15:0:c7:c8:4"
+#define XREG_CP15_VA_TO_PA_OTHER_1		"cp15:0:c7:c8:5"
+#define XREG_CP15_VA_TO_PA_OTHER_2		"cp15:0:c7:c8:6"
+#define XREG_CP15_VA_TO_PA_OTHER_3		"cp15:0:c7:c8:7"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC		"cp15:0:c7:c10:1"
+#define XREG_CP15_CLEAN_DC_LINE_SW		"cp15:0:c7:c10:2"
+
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex A9.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER		"cp15:0:c7:c10:4"
+#define XREG_CP15_DATA_MEMORY_BARRIER		"cp15:0:c7:c10:5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU		"cp15:0:c7:c11:1"
+
+#define XREG_CP15_NOP2				"cp15:0:c7:c13:1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC	"cp15:0:c7:c14:1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW	"cp15:0:c7:c14:2"
+
+/* C8 Register Defines */
+#define XREG_CP15_INVAL_TLB_IS			"cp15:0:c8:c3:0"
+#define XREG_CP15_INVAL_TLB_MVA_IS		"cp15:0:c8:c3:1"
+#define XREG_CP15_INVAL_TLB_ASID_IS		"cp15:0:c8:c3:2"
+#define XREG_CP15_INVAL_TLB_MVA_ASID_IS		"cp15:0:c8:c3:3"
+
+#define XREG_CP15_INVAL_ITLB_UNLOCKED		"cp15:0:c8:c5:0"
+#define XREG_CP15_INVAL_ITLB_MVA		"cp15:0:c8:c5:1"
+#define XREG_CP15_INVAL_ITLB_ASID		"cp15:0:c8:c5:2"
+
+#define XREG_CP15_INVAL_DTLB_UNLOCKED		"cp15:0:c8:c6:0"
+#define XREG_CP15_INVAL_DTLB_MVA		"cp15:0:c8:c6:1"
+#define XREG_CP15_INVAL_DTLB_ASID		"cp15:0:c8:c6:2"
+
+#define XREG_CP15_INVAL_UTLB_UNLOCKED		"cp15:0:c8:c7:0"
+#define XREG_CP15_INVAL_UTLB_MVA		"cp15:0:c8:c7:1"
+#define XREG_CP15_INVAL_UTLB_ASID		"cp15:0:c8:c7:2"
+#define XREG_CP15_INVAL_UTLB_MVA_ASID		"cp15:0:c8:c7:3"
+
+/* C9 Register Defines */
+#define XREG_CP15_PERF_MONITOR_CTRL		"cp15:0:c9:c12:0"
+#define XREG_CP15_COUNT_ENABLE_SET		"cp15:0:c9:c12:1"
+#define XREG_CP15_COUNT_ENABLE_CLR		"cp15:0:c9:c12:2"
+#define XREG_CP15_V_FLAG_STATUS			"cp15:0:c9:c12:3"
+#define XREG_CP15_SW_INC			"cp15:0:c9:c12:4"
+#define XREG_CP15_EVENT_CNTR_SEL		"cp15:0:c9:c12:5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER		"cp15:0:c9:c13:0"
+#define XREG_CP15_EVENT_TYPE_SEL		"cp15:0:c9:c13:1"
+#define XREG_CP15_PERF_MONITOR_COUNT		"cp15:0:c9:c13:2"
+
+#define XREG_CP15_USER_ENABLE			"cp15:0:c9:c14:0"
+#define XREG_CP15_INTR_ENABLE_SET		"cp15:0:c9:c14:1"
+#define XREG_CP15_INTR_ENABLE_CLR		"cp15:0:c9:c14:2"
+
+/* C10 Register Defines */
+#define XREG_CP15_TLB_LOCKDWN			"cp15:0:c10:c0:0"
+
+#define XREG_CP15_PRI_MEM_REMAP			"cp15:0:c10:c2:0"
+#define XREG_CP15_NORM_MEM_REMAP		"cp15:0:c10:c2:1"
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+#define XREG_CP15_VEC_BASE_ADDR			"cp15:0:c12:c0:0"
+#define XREG_CP15_MONITOR_VEC_BASE_ADDR		"cp15:0:c12:c0:1"
+
+#define XREG_CP15_INTERRUPT_STATUS		"cp15:0:c12:c1:0"
+#define XREG_CP15_VIRTUALIZATION_INTR		"cp15:0:c12:c1:1"
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID			"cp15:0:c13:c0:1"
+#define USER_RW_THREAD_PID			"cp15:0:c13:c0:2"
+#define USER_RO_THREAD_PID			"cp15:0:c13:c0:3"
+#define USER_PRIV_THREAD_PID			"cp15:0:c13:c0:4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_POWER_CTRL			"cp15:0:c15:c0:0"
+#define XREG_CP15_CONFIG_BASE_ADDR		"cp15:4:c15:c0:0"
+
+#define XREG_CP15_READ_TLB_ENTRY		"cp15:5:c15:c4:2"
+#define XREG_CP15_WRITE_TLB_ENTRY		"cp15:5:c15:c4:4"
+
+#define XREG_CP15_MAIN_TLB_VA			"cp15:5:c15:c5:2"
+
+#define XREG_CP15_MAIN_TLB_PA			"cp15:5:c15:c6:2"
+
+#define XREG_CP15_MAIN_TLB_ATTR			"cp15:5:c15:c7:2"
+#endif
+
+
+/* MPE register definitions */
+#define XREG_FPSID				c0
+#define XREG_FPSCR				c1
+#define XREG_MVFR1				c6
+#define XREG_MVFR0				c7
+#define XREG_FPEXC				c8
+#define XREG_FPINST				c9
+#define XREG_FPINST2				c10
+
+/* FPSID bits */
+#define XREG_FPSID_IMPLEMENTER_BIT	(24)
+#define XREG_FPSID_IMPLEMENTER_MASK	(0xFF << FPSID_IMPLEMENTER_BIT)
+#define XREG_FPSID_SOFTWARE		(1<<23)
+#define XREG_FPSID_ARCH_BIT		(16)
+#define XREG_FPSID_ARCH_MASK		(0xF  << FPSID_ARCH_BIT)
+#define XREG_FPSID_PART_BIT		(8)
+#define XREG_FPSID_PART_MASK		(0xFF << FPSID_PART_BIT)
+#define XREG_FPSID_VARIANT_BIT		(4)
+#define XREG_FPSID_VARIANT_MASK		(0xF  << FPSID_VARIANT_BIT)
+#define XREG_FPSID_REV_BIT		(0)
+#define XREG_FPSID_REV_MASK		(0xF  << FPSID_REV_BIT)
+
+/* FPSCR bits */
+#define XREG_FPSCR_N_BIT		(1 << 31)
+#define XREG_FPSCR_Z_BIT		(1 << 30)
+#define XREG_FPSCR_C_BIT		(1 << 29)
+#define XREG_FPSCR_V_BIT		(1 << 28)
+#define XREG_FPSCR_QC			(1 << 27)
+#define XREG_FPSCR_AHP			(1 << 26)
+#define XREG_FPSCR_DEFAULT_NAN		(1 << 25)
+#define XREG_FPSCR_FLUSHTOZERO		(1 << 24)
+#define XREG_FPSCR_ROUND_NEAREST	(0 << 22)
+#define XREG_FPSCR_ROUND_PLUSINF	(1 << 22)
+#define XREG_FPSCR_ROUND_MINUSINF	(2 << 22)
+#define XREG_FPSCR_ROUND_TOZERO		(3 << 22)
+#define XREG_FPSCR_RMODE_BIT		(22)
+#define XREG_FPSCR_RMODE_MASK		(3 << FPSCR_RMODE_BIT)
+#define XREG_FPSCR_STRIDE_BIT		(20)
+#define XREG_FPSCR_STRIDE_MASK		(3 << FPSCR_STRIDE_BIT)
+#define XREG_FPSCR_LENGTH_BIT		(16)
+#define XREG_FPSCR_LENGTH_MASK		(7 << FPSCR_LENGTH_BIT)
+#define XREG_FPSCR_IDC			(1 << 7)
+#define XREG_FPSCR_IXC			(1 << 4)
+#define XREG_FPSCR_UFC			(1 << 3)
+#define XREG_FPSCR_OFC			(1 << 2)
+#define XREG_FPSCR_DZC			(1 << 1)
+#define XREG_FPSCR_IOC			(1 << 0)
+
+/* MVFR0 bits */
+#define XREG_MVFR0_RMODE_BIT		(28)
+#define XREG_MVFR0_RMODE_MASK		(0xF << XREG_MVFR0_RMODE_BIT)
+#define XREG_MVFR0_SHORT_VEC_BIT	(24)
+#define XREG_MVFR0_SHORT_VEC_MASK	(0xF << XREG_MVFR0_SHORT_VEC_BIT)
+#define XREG_MVFR0_SQRT_BIT		(20)
+#define XREG_MVFR0_SQRT_MASK		(0xF << XREG_MVFR0_SQRT_BIT)
+#define XREG_MVFR0_DIVIDE_BIT		(16)
+#define XREG_MVFR0_DIVIDE_MASK		(0xF << XREG_MVFR0_DIVIDE_BIT)
+#define XREG_MVFR0_EXEC_TRAP_BIT	(12)
+#define XREG_MVFR0_EXEC_TRAP_MASK	(0xF << XREG_MVFR0_EXEC_TRAP_BIT)
+#define XREG_MVFR0_DP_BIT		(8)
+#define XREG_MVFR0_DP_MASK		(0xF << XREG_MVFR0_DP_BIT)
+#define XREG_MVFR0_SP_BIT		(4)
+#define XREG_MVFR0_SP_MASK		(0xF << XREG_MVFR0_SP_BIT)
+#define XREG_MVFR0_A_SIMD_BIT		(0)
+#define XREG_MVFR0_A_SIMD_MASK		(0xF << MVFR0_A_SIMD_BIT)
+
+/* FPEXC bits */
+#define XREG_FPEXC_EX			(1 << 31)
+#define XREG_FPEXC_EN			(1 << 30)
+#define XREG_FPEXC_DEX			(1 << 29)
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XREG_CORTEXA9_H */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xstatus.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xstatus.h
new file mode 100644
index 0000000000000000000000000000000000000000..993747588d94aa9364dfacd1f14cd5970331d66a
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xstatus.h
@@ -0,0 +1,535 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xstatus.h
+*
+* @addtogroup common_status_codes Xilinx&reg; software status codes
+*
+* The xstatus.h file contains the Xilinx&reg; software status codes.These codes are
+* used throughout the Xilinx device drivers.
+*
+* @{
+******************************************************************************/
+
+#ifndef XSTATUS_H		/* prevent circular inclusions */
+#define XSTATUS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/*********************** Common statuses 0 - 500 *****************************/
+/**
+@name Common Status Codes for All Device Drivers
+@{
+*/
+#define XST_SUCCESS                     0L
+#define XST_FAILURE                     1L
+#define XST_DEVICE_NOT_FOUND            2L
+#define XST_DEVICE_BLOCK_NOT_FOUND      3L
+#define XST_INVALID_VERSION             4L
+#define XST_DEVICE_IS_STARTED           5L
+#define XST_DEVICE_IS_STOPPED           6L
+#define XST_FIFO_ERROR                  7L	/*!< An error occurred during an
+						   operation with a FIFO such as
+						   an underrun or overrun, this
+						   error requires the device to
+						   be reset */
+#define XST_RESET_ERROR                 8L	/*!< An error occurred which requires
+						   the device to be reset */
+#define XST_DMA_ERROR                   9L	/*!< A DMA error occurred, this error
+						   typically requires the device
+						   using the DMA to be reset */
+#define XST_NOT_POLLED                  10L	/*!< The device is not configured for
+						   polled mode operation */
+#define XST_FIFO_NO_ROOM                11L	/*!< A FIFO did not have room to put
+						   the specified data into */
+#define XST_BUFFER_TOO_SMALL            12L	/*!< The buffer is not large enough
+						   to hold the expected data */
+#define XST_NO_DATA                     13L	/*!< There was no data available */
+#define XST_REGISTER_ERROR              14L	/*!< A register did not contain the
+						   expected value */
+#define XST_INVALID_PARAM               15L	/*!< An invalid parameter was passed
+						   into the function */
+#define XST_NOT_SGDMA                   16L	/*!< The device is not configured for
+						   scatter-gather DMA operation */
+#define XST_LOOPBACK_ERROR              17L	/*!< A loopback test failed */
+#define XST_NO_CALLBACK                 18L	/*!< A callback has not yet been
+						   registered */
+#define XST_NO_FEATURE                  19L	/*!< Device is not configured with
+						   the requested feature */
+#define XST_NOT_INTERRUPT               20L	/*!< Device is not configured for
+						   interrupt mode operation */
+#define XST_DEVICE_BUSY                 21L	/*!< Device is busy */
+#define XST_ERROR_COUNT_MAX             22L	/*!< The error counters of a device
+						   have maxed out */
+#define XST_IS_STARTED                  23L	/*!< Used when part of device is
+						   already started i.e.
+						   sub channel */
+#define XST_IS_STOPPED                  24L	/*!< Used when part of device is
+						   already stopped i.e.
+						   sub channel */
+#define XST_DATA_LOST                   26L	/*!< Driver defined error */
+#define XST_RECV_ERROR                  27L	/*!< Generic receive error */
+#define XST_SEND_ERROR                  28L	/*!< Generic transmit error */
+#define XST_NOT_ENABLED                 29L	/*!< A requested service is not
+						   available because it has not
+						   been enabled */
+/** @} */
+/***************** Utility Component statuses 401 - 500  *********************/
+/**
+@name Utility Component Status Codes 401 - 500
+@{
+*/
+#define XST_MEMTEST_FAILED              401L	/*!< Memory test failed */
+
+/** @} */
+/***************** Common Components statuses 501 - 1000 *********************/
+/**
+@name Packet Fifo Status Codes 501 - 510
+@{
+*/
+/********************* Packet Fifo statuses 501 - 510 ************************/
+
+#define XST_PFIFO_LACK_OF_DATA          501L	/*!< Not enough data in FIFO   */
+#define XST_PFIFO_NO_ROOM               502L	/*!< Not enough room in FIFO   */
+#define XST_PFIFO_BAD_REG_VALUE         503L	/*!< Self test, a register value
+						   was invalid after reset */
+#define XST_PFIFO_ERROR                 504L	/*!< Generic packet FIFO error */
+#define XST_PFIFO_DEADLOCK              505L	/*!< Packet FIFO is reporting
+						 * empty and full simultaneously
+						 */
+/** @} */
+/**
+@name DMA Status Codes 511 - 530
+@{
+*/
+/************************** DMA statuses 511 - 530 ***************************/
+
+#define XST_DMA_TRANSFER_ERROR          511L	/*!< Self test, DMA transfer
+						   failed */
+#define XST_DMA_RESET_REGISTER_ERROR    512L	/*!< Self test, a register value
+						   was invalid after reset */
+#define XST_DMA_SG_LIST_EMPTY           513L	/*!< Scatter gather list contains
+						   no buffer descriptors ready
+						   to be processed */
+#define XST_DMA_SG_IS_STARTED           514L	/*!< Scatter gather not stopped */
+#define XST_DMA_SG_IS_STOPPED           515L	/*!< Scatter gather not running */
+#define XST_DMA_SG_LIST_FULL            517L	/*!< All the buffer desciptors of
+						   the scatter gather list are
+						   being used */
+#define XST_DMA_SG_BD_LOCKED            518L	/*!< The scatter gather buffer
+						   descriptor which is to be
+						   copied over in the scatter
+						   list is locked */
+#define XST_DMA_SG_NOTHING_TO_COMMIT    519L	/*!< No buffer descriptors have been
+						   put into the scatter gather
+						   list to be commited */
+#define XST_DMA_SG_COUNT_EXCEEDED       521L	/*!< The packet count threshold
+						   specified was larger than the
+						   total # of buffer descriptors
+						   in the scatter gather list */
+#define XST_DMA_SG_LIST_EXISTS          522L	/*!< The scatter gather list has
+						   already been created */
+#define XST_DMA_SG_NO_LIST              523L	/*!< No scatter gather list has
+						   been created */
+#define XST_DMA_SG_BD_NOT_COMMITTED     524L	/*!< The buffer descriptor which was
+						   being started was not committed
+						   to the list */
+#define XST_DMA_SG_NO_DATA              525L	/*!< The buffer descriptor to start
+						   has already been used by the
+						   hardware so it can't be reused
+						 */
+#define XST_DMA_SG_LIST_ERROR           526L	/*!< General purpose list access
+						   error */
+#define XST_DMA_BD_ERROR                527L	/*!< General buffer descriptor
+						   error */
+/** @} */
+/**
+@name IPIF Status Codes Codes 531 - 550
+@{
+*/
+/************************** IPIF statuses 531 - 550 ***************************/
+
+#define XST_IPIF_REG_WIDTH_ERROR        531L	/*!< An invalid register width
+						   was passed into the function */
+#define XST_IPIF_RESET_REGISTER_ERROR   532L	/*!< The value of a register at
+						   reset was not valid */
+#define XST_IPIF_DEVICE_STATUS_ERROR    533L	/*!< A write to the device interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_DEVICE_ACK_ERROR       534L	/*!< The device interrupt status
+						   register did not reset when
+						   acked */
+#define XST_IPIF_DEVICE_ENABLE_ERROR    535L	/*!< The device interrupt enable
+						   register was not updated when
+						   other registers changed */
+#define XST_IPIF_IP_STATUS_ERROR        536L	/*!< A write to the IP interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_IP_ACK_ERROR           537L	/*!< The IP interrupt status register
+						   did not reset when acked */
+#define XST_IPIF_IP_ENABLE_ERROR        538L	/*!< IP interrupt enable register was
+						   not updated correctly when other
+						   registers changed */
+#define XST_IPIF_DEVICE_PENDING_ERROR   539L	/*!< The device interrupt pending
+						   register did not indicate the
+						   expected value */
+#define XST_IPIF_DEVICE_ID_ERROR        540L	/*!< The device interrupt ID register
+						   did not indicate the expected
+						   value */
+#define XST_IPIF_ERROR                  541L	/*!< Generic ipif error */
+/** @} */
+
+/****************** Device specific statuses 1001 - 4095 *********************/
+/**
+@name Ethernet Status Codes 1001 - 1050
+@{
+*/
+/********************* Ethernet statuses 1001 - 1050 *************************/
+
+#define XST_EMAC_MEMORY_SIZE_ERROR  1001L	/*!< Memory space is not big enough
+						 * to hold the minimum number of
+						 * buffers or descriptors */
+#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L	/*!< Memory allocation failed */
+#define XST_EMAC_MII_READ_ERROR     1003L	/*!< MII read error */
+#define XST_EMAC_MII_BUSY           1004L	/*!< An MII operation is in progress */
+#define XST_EMAC_OUT_OF_BUFFERS     1005L	/*!< Driver is out of buffers */
+#define XST_EMAC_PARSE_ERROR        1006L	/*!< Invalid driver init string */
+#define XST_EMAC_COLLISION_ERROR    1007L	/*!< Excess deferral or late
+						 * collision on polled send */
+/** @} */
+/**
+@name UART Status Codes 1051 - 1075
+@{
+*/
+/*********************** UART statuses 1051 - 1075 ***************************/
+#define XST_UART
+
+#define XST_UART_INIT_ERROR         1051L
+#define XST_UART_START_ERROR        1052L
+#define XST_UART_CONFIG_ERROR       1053L
+#define XST_UART_TEST_FAIL          1054L
+#define XST_UART_BAUD_ERROR         1055L
+#define XST_UART_BAUD_RANGE         1056L
+
+/** @} */
+/**
+@name IIC Status Codes 1076 - 1100
+@{
+*/
+/************************ IIC statuses 1076 - 1100 ***************************/
+
+#define XST_IIC_SELFTEST_FAILED         1076	/*!< self test failed            */
+#define XST_IIC_BUS_BUSY                1077	/*!< bus found busy              */
+#define XST_IIC_GENERAL_CALL_ADDRESS    1078	/*!< mastersend attempted with   */
+					     /* general call address        */
+#define XST_IIC_STAND_REG_RESET_ERROR   1079	/*!< A non parameterizable reg   */
+					     /* value after reset not valid */
+#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080	/*!< Tx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081	/*!< Rx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_TBA_REG_RESET_ERROR     1082	/*!< 10 bit addr incl in design  */
+					     /* value after reset not valid */
+#define XST_IIC_CR_READBACK_ERROR       1083	/*!< Read of the control register */
+					     /* didn't return value written */
+#define XST_IIC_DTR_READBACK_ERROR      1084	/*!< Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_DRR_READBACK_ERROR      1085	/*!< Read of the data Receive reg */
+					     /* didn't return value written */
+#define XST_IIC_ADR_READBACK_ERROR      1086	/*!< Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_TBA_READBACK_ERROR      1087	/*!< Read of the 10 bit addr reg */
+					     /* didn't return written value */
+#define XST_IIC_NOT_SLAVE               1088	/*!< The device isn't a slave    */
+/** @} */
+/**
+@name ATMC Status Codes 1101 - 1125
+@{
+*/
+/*********************** ATMC statuses 1101 - 1125 ***************************/
+
+#define XST_ATMC_ERROR_COUNT_MAX    1101L	/*!< the error counters in the ATM
+						   controller hit the max value
+						   which requires the statistics
+						   to be cleared */
+/** @} */
+/**
+@name Flash Status Codes 1126 - 1150
+@{
+*/
+/*********************** Flash statuses 1126 - 1150 **************************/
+
+#define XST_FLASH_BUSY                1126L	/*!< Flash is erasing or programming
+						 */
+#define XST_FLASH_READY               1127L	/*!< Flash is ready for commands */
+#define XST_FLASH_ERROR               1128L	/*!< Flash had detected an internal
+						   error. Use XFlash_DeviceControl
+						   to retrieve device specific codes
+						 */
+#define XST_FLASH_ERASE_SUSPENDED     1129L	/*!< Flash is in suspended erase state
+						 */
+#define XST_FLASH_WRITE_SUSPENDED     1130L	/*!< Flash is in suspended write state
+						 */
+#define XST_FLASH_PART_NOT_SUPPORTED  1131L	/*!< Flash type not supported by
+						   driver */
+#define XST_FLASH_NOT_SUPPORTED       1132L	/*!< Operation not supported */
+#define XST_FLASH_TOO_MANY_REGIONS    1133L	/*!< Too many erase regions */
+#define XST_FLASH_TIMEOUT_ERROR       1134L	/*!< Programming or erase operation
+						   aborted due to a timeout */
+#define XST_FLASH_ADDRESS_ERROR       1135L	/*!< Accessed flash outside its
+						   addressible range */
+#define XST_FLASH_ALIGNMENT_ERROR     1136L	/*!< Write alignment error */
+#define XST_FLASH_BLOCKING_CALL_ERROR 1137L	/*!< Couldn't return immediately from
+						   write/erase function with
+						   XFL_NON_BLOCKING_WRITE/ERASE
+						   option cleared */
+#define XST_FLASH_CFI_QUERY_ERROR     1138L	/*!< Failed to query the device */
+/** @} */
+/**
+@name SPI Status Codes 1151 - 1175
+@{
+*/
+/*********************** SPI statuses 1151 - 1175 ****************************/
+
+#define XST_SPI_MODE_FAULT          1151	/*!< master was selected as slave */
+#define XST_SPI_TRANSFER_DONE       1152	/*!< data transfer is complete */
+#define XST_SPI_TRANSMIT_UNDERRUN   1153	/*!< slave underruns transmit register */
+#define XST_SPI_RECEIVE_OVERRUN     1154	/*!< device overruns receive register */
+#define XST_SPI_NO_SLAVE            1155	/*!< no slave has been selected yet */
+#define XST_SPI_TOO_MANY_SLAVES     1156	/*!< more than one slave is being
+						 * selected */
+#define XST_SPI_NOT_MASTER          1157	/*!< operation is valid only as master */
+#define XST_SPI_SLAVE_ONLY          1158	/*!< device is configured as slave-only
+						 */
+#define XST_SPI_SLAVE_MODE_FAULT    1159	/*!< slave was selected while disabled */
+#define XST_SPI_SLAVE_MODE          1160	/*!< device has been addressed as slave */
+#define XST_SPI_RECEIVE_NOT_EMPTY   1161	/*!< device received data in slave mode */
+
+#define XST_SPI_COMMAND_ERROR       1162	/*!< unrecognised command - qspi only */
+#define XST_SPI_POLL_DONE           1163        /*!< controller completed polling the
+						   device for status */
+/** @} */
+/**
+@name OPB Arbiter Status Codes 1176 - 1200
+@{
+*/
+/********************** OPB Arbiter statuses 1176 - 1200 *********************/
+
+#define XST_OPBARB_INVALID_PRIORITY  1176	/*!< the priority registers have either
+						 * one master assigned to two or more
+						 * priorities, or one master not
+						 * assigned to any priority
+						 */
+#define XST_OPBARB_NOT_SUSPENDED     1177	/*!< an attempt was made to modify the
+						 * priority levels without first
+						 * suspending the use of priority
+						 * levels
+						 */
+#define XST_OPBARB_PARK_NOT_ENABLED  1178	/*!< bus parking by id was enabled but
+						 * bus parking was not enabled
+						 */
+#define XST_OPBARB_NOT_FIXED_PRIORITY 1179	/*!< the arbiter must be in fixed
+						 * priority mode to allow the
+						 * priorities to be changed
+						 */
+/** @} */
+/**
+@name INTC Status Codes 1201 - 1225
+@{
+*/
+/************************ Intc statuses 1201 - 1225 **************************/
+
+#define XST_INTC_FAIL_SELFTEST      1201	/*!< self test failed */
+#define XST_INTC_CONNECT_ERROR      1202	/*!< interrupt already in use */
+/** @} */
+/**
+@name TmrCtr Status Codes 1226 - 1250
+@{
+*/
+/********************** TmrCtr statuses 1226 - 1250 **************************/
+
+#define XST_TMRCTR_TIMER_FAILED     1226	/*!< self test failed */
+/** @} */
+/**
+@name WdtTb Status Codes 1251 - 1275
+@{
+*/
+/********************** WdtTb statuses 1251 - 1275 ***************************/
+
+#define XST_WDTTB_TIMER_FAILED      1251L
+/** @} */
+/**
+@name PlbArb status Codes 1276 - 1300
+@{
+*/
+/********************** PlbArb statuses 1276 - 1300 **************************/
+
+#define XST_PLBARB_FAIL_SELFTEST    1276L
+/** @} */
+/**
+@name Plb2Opb Status Codes 1301 - 1325
+@{
+*/
+/********************** Plb2Opb statuses 1301 - 1325 *************************/
+
+#define XST_PLB2OPB_FAIL_SELFTEST   1301L
+/** @} */
+/**
+@name Opb2Plb Status 1326 - 1350
+@{
+*/
+/********************** Opb2Plb statuses 1326 - 1350 *************************/
+
+#define XST_OPB2PLB_FAIL_SELFTEST   1326L
+/** @} */
+/**
+@name SysAce Status Codes 1351 - 1360
+@{
+*/
+/********************** SysAce statuses 1351 - 1360 **************************/
+
+#define XST_SYSACE_NO_LOCK          1351L	/*!< No MPU lock has been granted */
+/** @} */
+/**
+@name PCI Bridge Status Codes 1361 - 1375
+@{
+*/
+/********************** PCI Bridge statuses 1361 - 1375 **********************/
+
+#define XST_PCI_INVALID_ADDRESS     1361L
+/** @} */
+/**
+@name FlexRay Constants 1400 - 1409
+@{
+*/
+/********************** FlexRay constants 1400 - 1409 *************************/
+
+#define XST_FR_TX_ERROR			1400
+#define XST_FR_TX_BUSY			1401
+#define XST_FR_BUF_LOCKED		1402
+#define XST_FR_NO_BUF			1403
+/** @} */
+/**
+@name USB constants 1410 - 1420
+@{
+*/
+/****************** USB constants 1410 - 1420  *******************************/
+
+#define XST_USB_ALREADY_CONFIGURED	1410
+#define XST_USB_BUF_ALIGN_ERROR		1411
+#define XST_USB_NO_DESC_AVAILABLE	1412
+#define XST_USB_BUF_TOO_BIG		1413
+#define XST_USB_NO_BUF			1414
+/** @} */
+/**
+@name HWICAP constants 1421 - 1429
+@{
+*/
+/****************** HWICAP constants 1421 - 1429  *****************************/
+
+#define XST_HWICAP_WRITE_DONE		1421
+
+/** @} */
+/**
+@name AXI VDMA constants 1430 - 1440
+@{
+*/
+/****************** AXI VDMA constants 1430 - 1440  *****************************/
+
+#define XST_VDMA_MISMATCH_ERROR		1430
+/** @} */
+/**
+@name NAND Flash Status Codes 1441 - 1459
+@{
+*/
+/*********************** NAND Flash statuses 1441 - 1459  *********************/
+
+#define XST_NAND_BUSY			1441L	/*!< Flash is erasing or
+						 * programming
+						 */
+#define XST_NAND_READY			1442L	/*!< Flash is ready for commands
+						 */
+#define XST_NAND_ERROR			1443L	/*!< Flash had detected an
+						 * internal error.
+						 */
+#define XST_NAND_PART_NOT_SUPPORTED	1444L	/*!< Flash type not supported by
+						 * driver
+						 */
+#define XST_NAND_OPT_NOT_SUPPORTED	1445L	/*!< Operation not supported
+						 */
+#define XST_NAND_TIMEOUT_ERROR		1446L	/*!< Programming or erase
+						 * operation aborted due to a
+						 * timeout
+						 */
+#define XST_NAND_ADDRESS_ERROR		1447L	/*!< Accessed flash outside its
+						 * addressible range
+						 */
+#define XST_NAND_ALIGNMENT_ERROR	1448L	/*!< Write alignment error
+						 */
+#define XST_NAND_PARAM_PAGE_ERROR	1449L	/*!< Failed to read parameter
+						 * page of the device
+						 */
+#define XST_NAND_CACHE_ERROR		1450L	/*!< Flash page buffer error
+						 */
+
+#define XST_NAND_WRITE_PROTECTED	1451L	/*!< Flash is write protected
+						 */
+/** @} */
+
+/**************************** Type Definitions *******************************/
+
+typedef s32 XStatus;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_status_codes".
+*/
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xtime_l.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xtime_l.c
new file mode 100644
index 0000000000000000000000000000000000000000..e81643f90b96461dbffec7b7a27dfdd234bd7dc5
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xtime_l.c
@@ -0,0 +1,122 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xtime_l.c
+*
+* This file contains low level functions to get/set time from the Global Timer
+* register in the ARM Cortex A9 MP core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.07a sgd    07/05/12 Upadted get/set time functions to make use Global Timer
+* </pre>
+*
+* @note		None.
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+/****************************************************************************/
+/**
+* @brief	Set the time in the Global Timer Counter Register.
+*
+* @param	Xtime_Global: 64-bit Value to be written to the Global Timer
+*			Counter Register.
+*
+* @return	None.
+*
+* @note		When this function is called by any one processor in a multi-
+*			processor environment, reference time will reset/lost for all
+*			processors.
+*
+****************************************************************************/
+void XTime_SetTime(XTime Xtime_Global)
+{
+	/* Disable Global Timer */
+	Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x0);
+
+	/* Updating Global Timer Counter Register */
+	Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_LOWER_OFFSET, (u32)Xtime_Global);
+	Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_UPPER_OFFSET,
+		(u32)((u32)(Xtime_Global>>32U)));
+
+	/* Enable Global Timer */
+	Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x1);
+}
+
+/****************************************************************************/
+/**
+* @brief	Get the time from the Global Timer Counter Register.
+*
+* @param	Xtime_Global: Pointer to the 64-bit location which will be
+*			updated with the current timer value.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XTime_GetTime(XTime *Xtime_Global)
+{
+	u32 low;
+	u32 high;
+
+	/* Reading Global Timer Counter Register */
+	do
+	{
+		high = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET);
+		low = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_LOWER_OFFSET);
+	} while(Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET) != high);
+
+	*Xtime_Global = (((XTime) high) << 32U) | (XTime) low;
+}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xtime_l.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xtime_l.h
new file mode 100644
index 0000000000000000000000000000000000000000..f939d84f616b72fffe1b7b097c01129243b177ed
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xtime_l.h
@@ -0,0 +1,96 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xtime_l.h
+* @addtogroup a9_time_apis Cortex A9 Time Functions
+*
+* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This
+* counter increases by one at every two processor cycles. These functions can
+* be used to get/set time in the global timer.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.06a sgd    05/15/12 Upadted get/set time functions to make use Global Timer
+* 3.06a asa    06/17/12 Reverted back the changes to make use Global Timer.
+* 3.07a sgd    07/05/12 Upadted get/set time functions to make use Global Timer
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XTIME_H /* prevent circular inclusions */
+#define XTIME_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xparameters.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+typedef u64 XTime;
+
+/************************** Constant Definitions *****************************/
+#define GLOBAL_TMR_BASEADDR               XPAR_GLOBAL_TMR_BASEADDR
+#define GTIMER_COUNTER_LOWER_OFFSET       0x00U
+#define GTIMER_COUNTER_UPPER_OFFSET       0x04U
+#define GTIMER_CONTROL_OFFSET             0x08U
+
+
+/* Global Timer is always clocked at half of the CPU frequency */
+#define COUNTS_PER_SECOND          (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2)
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void XTime_SetTime(XTime Xtime_Global);
+void XTime_GetTime(XTime *Xtime_Global);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XTIME_H */
+/**
+* @} End of "addtogroup a9_time_apis".
+*/
\ No newline at end of file
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xtime_l.o b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xtime_l.o
new file mode 100644
index 0000000000000000000000000000000000000000..0312ac997cc972fb354794e045498f1ba3112fb4
Binary files /dev/null and b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/standalone_v6_2/src/xtime_l.o differ
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/Makefile b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..35c277ddea0e9779f63a93344fbd05f88f45b45a
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner ttcps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling ttcps"
+
+ttcps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: ttcps_includes
+
+ttcps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps.c
new file mode 100644
index 0000000000000000000000000000000000000000..394262868b2353d58107162157ea3771a5a3df79
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps.c
@@ -0,0 +1,443 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps.c
+* @addtogroup ttcps_v3_0
+* @{
+*
+* This file contains the implementation of the XTtcPs driver. This driver
+* controls the operation of one timer counter in the Triple Timer Counter (TTC)
+* module in the Ps block. Refer to xttcps.h for more detailed description
+* of the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -------------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.01	pkp	   01/30/16 Modified XTtcPs_CfgInitialize to add XTtcps_Stop
+*						to stop the timer before configuring
+* 3.2   mus    10/28/16 Modified XTtcPs_CalcIntervalFromFreq to calculate
+*                       32 bit interval count for zynq ultrascale+mpsoc
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XTtcPs instance such that the driver is ready to use.
+* This function initializes a single timer counter in the triple timer counter
+* function block.
+*
+* The state of the device after initialization is:
+*  - Overflow Mode
+*  - Internal (pclk) selected
+*  - Counter disabled
+*  - All Interrupts disabled
+*  - Output waveforms disabled
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	ConfigPtr is a reference to a structure containing information
+*		about a specific TTC device.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, then use
+*		ConfigPtr->BaseAddress for this parameter, passing the physical
+*		address instead.
+*
+* @return
+*
+* 		- XST_SUCCESS if the initialization is successful.
+*		- XST_DEVICE_IS_STARTED if the device is started. It must be
+*		  stopped to re-initialize.
+*
+* @note		Device has to be stopped first to call this function to
+*		initialize it.
+*
+******************************************************************************/
+s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config *ConfigPtr,
+			      u32 EffectiveAddr)
+{
+	s32 Status;
+	u32 IsStartResult;
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * Set some default values
+	 */
+	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
+
+	IsStartResult = XTtcPs_IsStarted(InstancePtr);
+	/*
+	 * If the timer counter has already started, return an error
+	 * Device should be stopped first.
+	 */
+	if(IsStartResult == (u32)TRUE) {
+		Status = XST_DEVICE_IS_STARTED;
+	} else {
+
+		/*
+		 * stop the timer before configuring
+		 */
+		XTtcPs_Stop(InstancePtr);
+		/*
+		 * Reset the count control register to it's default value.
+		 */
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_CNT_CNTRL_OFFSET,
+				  XTTCPS_CNT_CNTRL_RESET_VALUE);
+
+		/*
+		 * Reset the rest of the registers to the default values.
+		 */
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_CLK_CNTRL_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_INTERVAL_VAL_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_MATCH_1_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_MATCH_2_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_MATCH_2_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_IER_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_ISR_OFFSET, XTTCPS_IXR_ALL_MASK);
+
+		InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+		/*
+		 * Reset the counter value
+		 */
+		XTtcPs_ResetCounterValue(InstancePtr);
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is used to set the match registers. There are three match
+* registers.
+*
+* The match 0 register is special. If the waveform output mode is enabled, the
+* waveform will change polarity when the count matches the value in the match 0
+* register. The polarity of the waveform output can also be set using the
+* XTtcPs_SetOptions() function.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	MatchIndex is the index to the match register to be set.
+*		Valid values are 0, 1, or 2.
+* @param	Value is the 16-bit value to be set in the match register.
+*
+* @return	None
+*
+* @note		None
+*
+****************************************************************************/
+void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value)
+{
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(MatchIndex < (u8)XTTCPS_NUM_MATCH_REG);
+
+	/*
+	 * Write the value to the correct match register with MatchIndex
+	 */
+	XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XTtcPs_Match_N_Offset(MatchIndex), Value);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is used to get the value of the match registers. There are
+* three match registers.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	MatchIndex is the index to the match register to be set.
+*		Valid values are 0, 1, or 2.
+*
+* @return	None
+*
+* @note		None
+*
+****************************************************************************/
+u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex)
+{
+	u32 MatchReg;
+
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(MatchIndex < XTTCPS_NUM_MATCH_REG);
+
+	MatchReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+			    XTtcPs_Match_N_Offset(MatchIndex));
+
+	return (u16) MatchReg;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the prescaler enable bit and if needed sets the prescaler
+* bits in the control register.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	PrescalerValue is a number from 0-16 that sets the prescaler
+*		to use.
+*		If the parameter is 0 - 15, use a prescaler on the clock of
+*		2^(PrescalerValue+1), or 2-65536.
+*		If the parameter is XTTCPS_CLK_CNTRL_PS_DISABLE, do not use a
+*		prescaler.
+*
+* @return	None
+*
+* @note		None
+*
+****************************************************************************/
+void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue)
+{
+	u32 ClockReg;
+
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(PrescalerValue <= XTTCPS_CLK_CNTRL_PS_DISABLE);
+
+	/*
+	 * Read the clock control register
+	 */
+	ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+			   XTTCPS_CLK_CNTRL_OFFSET);
+
+	/*
+	 * Clear all of the prescaler control bits in the register
+	 */
+	ClockReg &=
+		~(XTTCPS_CLK_CNTRL_PS_VAL_MASK | XTTCPS_CLK_CNTRL_PS_EN_MASK);
+
+	if (PrescalerValue < XTTCPS_CLK_CNTRL_PS_DISABLE) {
+		/*
+		 * Set the prescaler value and enable prescaler
+		 */
+		ClockReg |= (u32)(((u32)PrescalerValue << (u32)XTTCPS_CLK_CNTRL_PS_VAL_SHIFT) &
+			(u32)XTTCPS_CLK_CNTRL_PS_VAL_MASK);
+		ClockReg |= (u32)XTTCPS_CLK_CNTRL_PS_EN_MASK;
+	}
+
+	/*
+	 * Write the register with the new values.
+	 */
+	XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XTTCPS_CLK_CNTRL_OFFSET, ClockReg);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the input clock prescaler
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* <pre>
+* @return	The value(n) from which the prescalar value is calculated
+*		as 2^(n+1). Some example values are given below :
+*
+* 	Value		Prescaler
+* 	0		2
+* 	1		4
+* 	N		2^(n+1)
+* 	15		65536
+* 	16		1
+* </pre>
+*
+* @note		None.
+*
+****************************************************************************/
+u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr)
+{
+	u8 Status;
+	u32 ClockReg;
+
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the clock control register
+	 */
+	ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XTTCPS_CLK_CNTRL_OFFSET);
+
+	if (0 == (ClockReg & XTTCPS_CLK_CNTRL_PS_EN_MASK)) {
+		/*
+		 * Prescaler is disabled. Return the correct flag value
+		 */
+		Status = (u8)XTTCPS_CLK_CNTRL_PS_DISABLE;
+	}
+	else {
+
+		Status = (u8)((ClockReg & (u32)XTTCPS_CLK_CNTRL_PS_VAL_MASK) >>
+			(u32)XTTCPS_CLK_CNTRL_PS_VAL_SHIFT);
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function calculates the interval value as well as the prescaler value
+* for a given frequency.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	Freq is the requested output frequency for the device.
+* @param	Interval is the interval value for the given frequency,
+*		it is the output value for this function.
+* @param	Prescaler is the prescaler value for the given frequency,
+*		it is the output value for this function.
+*
+* @return	None.
+*
+* @note
+*  Upon successful calculation for the given frequency, Interval and Prescaler
+*  carry the settings for the timer counter; Upon unsuccessful calculation,
+*  Interval and Prescaler are set to 0xFF(FF) for their maximum values to
+*  signal the caller of failure. Therefore, caller needs to check the return
+*  interval or prescaler values for whether the function has succeeded.
+*
+****************************************************************************/
+void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
+        XInterval *Interval, u8 *Prescaler)
+{
+	u8 TmpPrescaler;
+	u32 TempValue;
+	u32 InputClock;
+
+	InputClock = InstancePtr->Config.InputClockHz;
+	/*
+	 * Find the smallest prescaler that will work for a given frequency. The
+	 * smaller the prescaler, the larger the count and the more accurate the
+	 *  PWM setting.
+	 */
+	TempValue = InputClock/ Freq;
+
+	if (TempValue < 4U) {
+		/*
+		 * The frequency is too high, it is too close to the input
+		 * clock value. Use maximum values to signal caller.
+		 */
+		*Interval = XTTCPS_MAX_INTERVAL_COUNT;
+		*Prescaler = 0xFFU;
+		return;
+	}
+
+	/*
+	 * First, do we need a prescaler or not?
+	 */
+	if (((u32)65536U) > TempValue) {
+		/*
+		 * We do not need a prescaler, so set the values appropriately
+		 */
+		*Interval = (XInterval)TempValue;
+		*Prescaler = XTTCPS_CLK_CNTRL_PS_DISABLE;
+		return;
+	}
+
+
+	for (TmpPrescaler = 0U; TmpPrescaler < XTTCPS_CLK_CNTRL_PS_DISABLE;
+	     TmpPrescaler++) {
+		TempValue =	InputClock/ (Freq * (1U << (TmpPrescaler + 1U)));
+
+		/*
+		 * The first value less than 2^16 is the best bet
+		 */
+		if (((u32)65536U) > TempValue) {
+			/*
+			 * Set the values appropriately
+			 */
+			*Interval = (XInterval)TempValue;
+			*Prescaler = TmpPrescaler;
+			return;
+		}
+	}
+
+	/* Can not find interval values that work for the given frequency.
+	 * Return maximum values to signal caller.
+	 */
+	*Interval = XTTCPS_MAX_INTERVAL_COUNT;
+	*Prescaler = 0XFFU;
+	return;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps.h
new file mode 100644
index 0000000000000000000000000000000000000000..bae9d28fecb14a37e90091fc0b5a359ea2b57fa8
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps.h
@@ -0,0 +1,466 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps.h
+* @addtogroup ttcps_v3_0
+* @{
+* @details
+*
+* This is the driver for one 16-bit timer counter in the Triple Timer Counter
+* (TTC) module in the Ps block.
+*
+* The TTC module provides three independent timer/counter modules that can each
+* be clocked using either the system clock (pclk) or an externally driven
+* clock (ext_clk). In addition, each counter can independently prescale its
+* selected clock input (divided by 2 to 65536). Counters can be set to
+* decrement or increment.
+*
+* Each of the counters can be programmed to generate interrupt pulses:
+*	. At a regular, predefined period, that is on a timed interval
+*	. When the counter registers overflow
+* 	. When the count matches any one of the three 'match' registers
+*
+* Therefore, up to six different events can trigger a timer interrupt: three
+* match interrupts, an overflow interrupt, an interval interrupt and an event
+* timer interrupt. Note that the overflow interrupt and the interval interrupt
+* are mutually exclusive.
+*
+* <b>Initialization & Configuration</b>
+*
+* An XTtcPs_Config structure is used to configure a driver instance.
+* Information in the XTtcPs_Config structure is the hardware properties
+* about the device.
+*
+* A driver instance is initialized through
+* XTtcPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr). Where CfgPtr
+* is a pointer to the XTtcPs_Config structure, it can be looked up statically
+* through XTtcPs_LookupConfig(DeviceID), or passed in by the caller. The
+* EffectiveAddr can be the static base address of the device or virtual
+* mapped address if address translation is supported.
+*
+* <b>Interrupts</b>
+*
+* Interrupt handler is not provided by the driver, as handling of interrupt
+* is application specific.
+*
+* @note
+* The default setting for a timer/counter is:
+*  - Overflow Mode
+*  - Internal clock (pclk) selected
+*  - Counter disabled
+*  - All Interrupts disabled
+*  - Output waveforms disabled
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -----------------------------------------------------
+* 1.00a drg/jz 01/20/10 First release..
+* 2.0   adk    12/10/13 Updated as per the New Tcl API's
+* 3.0	pkp    12/09/14 Added support for Zynq Ultrascale Mp.Also code
+*			modified for MISRA-C:2012 compliance.
+* 3.2   mus    10/28/16 Modified XTtcPs_GetCounterValue and XTtcPs_SetInterval
+*                       macros to return 32 bit values for zynq ultrascale+mpsoc
+*       ms   01/23/17 Modified xil_printf statement in main function for all
+*                     examples to ensure that "Successfully ran" and "Failed"
+*                     strings are available in all examples. This is a fix
+*                     for CR-965028.
+*       ms   03/17/17 Added readme.txt file in examples folder for doxygen
+*                     generation.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XTTCPS_H		/* prevent circular inclusions */
+#define XTTCPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xttcps_hw.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+/*
+ * Flag for a9 processor
+ */
+ #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
+ #define ARMA9
+ #endif
+
+/*
+ * Maximum Value for interval counter
+ */
+ #if defined(ARMA9)
+ #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFU
+ #else
+ #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFFFFFU
+ #endif
+
+/** @name Configuration options
+ *
+ * Options for the device. Each of the options is bit field, so more than one
+ * options can be specified.
+ *
+ * @{
+ */
+#define XTTCPS_OPTION_EXTERNAL_CLK	0x00000001U 	/**< External clock source */
+#define XTTCPS_OPTION_CLK_EDGE_NEG	0x00000002U	/**< Clock on trailing edge for
+						     external clock*/
+#define XTTCPS_OPTION_INTERVAL_MODE	0x00000004U	/**< Interval mode */
+#define XTTCPS_OPTION_DECREMENT		0x00000008U	/**< Decrement the counter */
+#define XTTCPS_OPTION_MATCH_MODE	0x00000010U	/**< Match mode */
+#define XTTCPS_OPTION_WAVE_DISABLE	0x00000020U 	/**< No waveform output */
+#define XTTCPS_OPTION_WAVE_POLARITY	0x00000040U	/**< Waveform polarity */
+/*@}*/
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;	  /**< Unique ID for device */
+	u32 BaseAddress;  /**< Base address for device */
+	u32 InputClockHz; /**< Input clock frequency */
+} XTtcPs_Config;
+
+/**
+ * The XTtcPs driver instance data. The user is required to allocate a
+ * variable of this type for each PS timer/counter device in the system. A
+ * pointer to a variable of this type is then passed to various driver API
+ * functions.
+ */
+typedef struct {
+	XTtcPs_Config Config;	/**< Configuration structure */
+	u32 IsReady;		/**< Device is initialized and ready */
+} XTtcPs;
+
+/**
+ * This typedef contains interval count
+ */
+#if defined(ARMA9)
+typedef u16 XInterval;
+#else
+typedef u32 XInterval;
+#endif
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*
+ * Internal helper macros
+ */
+#define InstReadReg(InstancePtr, RegOffset) \
+    (Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset)))
+
+#define InstWriteReg(InstancePtr, RegOffset, Data) \
+    (Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset), (u32)(Data)))
+
+/*****************************************************************************/
+/**
+*
+* This function starts the counter/timer without resetting the counter value.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	None
+*
+* @note		C-style signature:
+*		void XTtcPs_Start(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_Start(InstancePtr)	\
+		InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET,	\
+		(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) &	\
+		 ~XTTCPS_CNT_CNTRL_DIS_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function stops the counter/timer. This macro may be called at any time
+* to stop the counter. The counter holds the last value until it is reset,
+* restarted or enabled.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	None
+*
+* @note		C-style signature:
+*		void XTtcPs_Stop(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_Stop(InstancePtr)		\
+		InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET,	\
+		(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) |	\
+		 XTTCPS_CNT_CNTRL_DIS_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function checks whether the timer counter has already started.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance
+*
+* @return	Non-zero if the device has started, '0' otherwise.
+*
+* @note		C-style signature:
+*		int XTtcPs_IsStarted(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_IsStarted(InstancePtr) \
+     ((InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
+       XTTCPS_CNT_CNTRL_DIS_MASK) == 0U)
+
+/*****************************************************************************/
+/**
+*
+* This function returns the current 16-bit counter value. It may be called at
+* any time.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	zynq:16 bit counter value.
+*           zynq ultrascale+mpsoc:32 bit counter value.
+*
+* @note		C-style signature:
+*		zynq: u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
+*       zynq ultrascale+mpsoc: u32 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#if defined(ARMA9)
+/*
+ * ttc supports 16 bit counter for zynq
+ */
+#define XTtcPs_GetCounterValue(InstancePtr) \
+		(u16)InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
+#else
+/*
+ * ttc supports 32 bit counter for zynq ultrascale+mpsoc
+ */
+#define XTtcPs_GetCounterValue(InstancePtr) \
+               InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This function sets the interval value to be used in interval mode.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	Value is the 16-bit value to be set in the interval register.
+*
+* @return	None
+*
+* @note		C-style signature:
+*		void XTtcPs_SetInterval(XTtcPs *InstancePtr, u16 Value)
+*
+****************************************************************************/
+#define XTtcPs_SetInterval(InstancePtr, Value)	\
+		InstWriteReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET, (Value))
+
+/*****************************************************************************/
+/**
+*
+* This function gets the interval value from the interval register.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	zynq:16 bit interval value.
+*           zynq ultrascale+mpsoc:32 bit interval value.
+*
+* @note		C-style signature:
+*		zynq: u16 XTtcPs_GetInterval(XTtcPs *InstancePtr)
+*       zynq ultrascale+mpsoc: u32 XTtcPs_GetInterval(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#if defined(ARMA9)
+/*
+ * ttc supports 16 bit interval counter for zynq
+ */
+#define XTtcPs_GetInterval(InstancePtr) \
+		(u16)InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
+#else
+/*
+ * ttc supports 32 bit interval counter for zynq ultrascale+mpsoc
+ */
+#define XTtcPs_GetInterval(InstancePtr) \
+		InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
+#endif
+/*****************************************************************************/
+/**
+*
+* This macro resets the count register. It may be called at any time. The
+* counter is reset to either 0 or 0xFFFF, or the interval value, depending on
+* the increment/decrement mode. The state of the counter, as started or
+* stopped, is not affected by calling reset.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	None
+*
+* @note		C-style signature:
+*		void XTtcPs_ResetCounterValue(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_ResetCounterValue(InstancePtr) \
+		InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET,	\
+		(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
+		 (u32)XTTCPS_CNT_CNTRL_RST_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function enables the interrupts.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	InterruptMask defines which interrupt should be enabled.
+*		Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+*		This is a bit mask, all set bits will be enabled, cleared bits
+*		will not be disabled.
+*
+* @return	None.
+*
+* @note
+* C-style signature:
+*	void XTtcPs_EnableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_EnableInterrupts(InstancePtr, InterruptMask)		\
+		InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET,		\
+		(InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) |	\
+		 (InterruptMask)))
+
+/*****************************************************************************/
+/**
+*
+* This function disables the interrupts.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	InterruptMask defines which interrupt should be disabled.
+*		Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+*		This is a bit mask, all set bits will be disabled, cleared bits
+*		will not be disabled.
+*
+* @return	None.
+*
+* @note
+* C-style signature:
+*	void XTtcPs_DisableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_DisableInterrupts(InstancePtr, InterruptMask) \
+		InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET,	\
+		(InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) &	\
+		 ~(InterruptMask)))
+
+/*****************************************************************************/
+/**
+*
+* This function reads the interrupt status.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		u32 XTtcPs_GetInterruptStatus(XTtcPs *InstancePtr)
+*
+******************************************************************************/
+#define XTtcPs_GetInterruptStatus(InstancePtr)	 \
+		InstReadReg((InstancePtr), XTTCPS_ISR_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears the interrupt status.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	InterruptMask defines which interrupt should be cleared.
+*		Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+*		This is a bit mask, all set bits will be cleared, cleared bits
+*		will not be cleared.
+*
+* @return	None.
+*
+* @note
+* C-style signature:
+*	void XTtcPs_ClearInterruptStatus(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_ClearInterruptStatus(InstancePtr, InterruptMask) \
+		InstWriteReg((InstancePtr), XTTCPS_ISR_OFFSET, \
+		 (InterruptMask))
+
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization functions in xttcps_sinit.c
+ */
+XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Required functions, in xttcps.c
+ */
+s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr,
+         XTtcPs_Config * ConfigPtr, u32 EffectiveAddr);
+
+void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value);
+u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex);
+
+void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue);
+u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr);
+
+void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
+        XInterval *Interval, u8 *Prescaler);
+
+/*
+ * Functions for options, in file xttcps_options.c
+ */
+s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options);
+u32 XTtcPs_GetOptions(XTtcPs *InstancePtr);
+
+/*
+ * Function for self-test, in file xttcps_selftest.c
+ */
+s32 XTtcPs_SelfTest(XTtcPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_g.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..682ac817807829193f5f6d47ce8e8ced808d50ee
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_g.c
@@ -0,0 +1,66 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xttcps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XTtcPs_Config XTtcPs_ConfigTable[] =
+{
+	{
+		XPAR_PS7_TTC_0_DEVICE_ID,
+		XPAR_PS7_TTC_0_BASEADDR,
+		XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PS7_TTC_1_DEVICE_ID,
+		XPAR_PS7_TTC_1_BASEADDR,
+		XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PS7_TTC_2_DEVICE_ID,
+		XPAR_PS7_TTC_2_BASEADDR,
+		XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ
+	}
+};
+
+
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..af78bcd67c8d606674a4d268a62f1a60ada41ebc
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_hw.h
@@ -0,0 +1,212 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_hw.h
+* @addtogroup ttcps_v3_0
+* @{
+*
+* This file defines the hardware interface to one of the three timer counters
+* in the Ps block.
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -------------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XTTCPS_HW_H		/* prevent circular inclusions */
+#define XTTCPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of the device.
+ *
+ * @{
+ */
+#define XTTCPS_CLK_CNTRL_OFFSET		0x00000000U  /**< Clock Control Register */
+#define XTTCPS_CNT_CNTRL_OFFSET		0x0000000CU  /**< Counter Control Register*/
+#define XTTCPS_COUNT_VALUE_OFFSET	0x00000018U  /**< Current Counter Value */
+#define XTTCPS_INTERVAL_VAL_OFFSET	0x00000024U  /**< Interval Count Value */
+#define XTTCPS_MATCH_0_OFFSET		0x00000030U  /**< Match 1 value */
+#define XTTCPS_MATCH_1_OFFSET		0x0000003CU  /**< Match 2 value */
+#define XTTCPS_MATCH_2_OFFSET		0x00000048U  /**< Match 3 value */
+#define XTTCPS_ISR_OFFSET			0x00000054U  /**< Interrupt Status Register */
+#define XTTCPS_IER_OFFSET			0x00000060U  /**< Interrupt Enable Register */
+/* @} */
+
+/** @name Clock Control Register
+ * Clock Control Register definitions
+ * @{
+ */
+#define XTTCPS_CLK_CNTRL_PS_EN_MASK		0x00000001U  /**< Prescale enable */
+#define XTTCPS_CLK_CNTRL_PS_VAL_MASK	0x0000001EU  /**< Prescale value */
+#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT			 1U  /**< Prescale shift */
+#define XTTCPS_CLK_CNTRL_PS_DISABLE				16U  /**< Prescale disable */
+#define XTTCPS_CLK_CNTRL_SRC_MASK		0x00000020U  /**< Clock source */
+#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK	0x00000040U  /**< External Clock edge */
+/* @} */
+
+/** @name Counter Control Register
+ * Counter Control Register definitions
+ * @{
+ */
+#define XTTCPS_CNT_CNTRL_DIS_MASK		0x00000001U /**< Disable the counter */
+#define XTTCPS_CNT_CNTRL_INT_MASK		0x00000002U /**< Interval mode */
+#define XTTCPS_CNT_CNTRL_DECR_MASK		0x00000004U /**< Decrement mode */
+#define XTTCPS_CNT_CNTRL_MATCH_MASK		0x00000008U /**< Match mode */
+#define XTTCPS_CNT_CNTRL_RST_MASK		0x00000010U /**< Reset counter */
+#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK	0x00000020U /**< Enable waveform */
+#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK	0x00000040U /**< Waveform polarity */
+#define XTTCPS_CNT_CNTRL_RESET_VALUE	0x00000021U /**< Reset value */
+/* @} */
+
+/** @name Current Counter Value Register
+ * Current Counter Value Register definitions
+ * @{
+ */
+#define XTTCPS_COUNT_VALUE_MASK		0x0000FFFFU /**< 16-bit counter value */
+/* @} */
+
+/** @name Interval Value Register
+ * Interval Value Register is the maximum value the counter will count up or
+ * down to.
+ * @{
+ */
+#define XTTCPS_INTERVAL_VAL_MASK	0x0000FFFFU /**< 16-bit Interval value*/
+/* @} */
+
+/** @name Match Registers
+ * Definitions for Match registers, each timer counter has three match
+ * registers.
+ * @{
+ */
+#define XTTCPS_MATCH_MASK		0x0000FFFFU /**< 16-bit Match value */
+#define XTTCPS_NUM_MATCH_REG			 3U /**< Num of Match reg */
+/* @} */
+
+/** @name Interrupt Registers
+ * Following register bit mask is for all interrupt registers.
+ *
+ * @{
+ */
+#define XTTCPS_IXR_INTERVAL_MASK	0x00000001U  /**< Interval Interrupt */
+#define XTTCPS_IXR_MATCH_0_MASK		0x00000002U  /**< Match 1 Interrupt */
+#define XTTCPS_IXR_MATCH_1_MASK		0x00000004U  /**< Match 2 Interrupt */
+#define XTTCPS_IXR_MATCH_2_MASK		0x00000008U  /**< Match 3 Interrupt */
+#define XTTCPS_IXR_CNT_OVR_MASK		0x00000010U  /**< Counter Overflow */
+#define XTTCPS_IXR_ALL_MASK			0x0000001FU  /**< All valid Interrupts */
+/* @} */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given Timer Counter register.
+*
+* @param	BaseAddress is the base address of the timer counter device.
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note		C-style signature:
+*		u32 XTtcPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XTtcPs_ReadReg(BaseAddress, RegOffset) \
+    (Xil_In32((BaseAddress) + (u32)(RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Timer Counter register.
+*
+* @param	BaseAddress is the base address of the timer counter device.
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XTtcPs_WriteReg(XTtcPs BaseAddress, u32 RegOffset,
+*		u32 Data)
+*
+*****************************************************************************/
+#define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \
+    (Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)))
+
+/****************************************************************************/
+/**
+*
+* Calculate a match register offset using the Match Register index.
+*
+* @param	MatchIndex is the 0-2 value of the match register
+*
+* @return	MATCH_N_OFFSET.
+*
+* @note		C-style signature:
+*		u32 XTtcPs_Match_N_Offset(u8 MatchIndex)
+*
+*****************************************************************************/
+#define XTtcPs_Match_N_Offset(MatchIndex) \
+		((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex)))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_options.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_options.c
new file mode 100644
index 0000000000000000000000000000000000000000..532b235c5a92799a448f7cccf6ebe96d12044d86
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_options.c
@@ -0,0 +1,243 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_options.c
+* @addtogroup ttcps_v3_0
+* @{
+*
+* This file contains functions to get or set option features for the device.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 1.01a nm     03/05/2012 Removed break statement after return to remove
+*                         compilation warnings.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * Create the table of options which are processed to get/set the device
+ * options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+typedef struct {
+	u32 Option;
+	u32 Mask;
+	u32 Register;
+} OptionsMap;
+
+static OptionsMap TmrCtrOptionsTable[] = {
+	{XTTCPS_OPTION_EXTERNAL_CLK, XTTCPS_CLK_CNTRL_SRC_MASK,
+	 XTTCPS_CLK_CNTRL_OFFSET},
+	{XTTCPS_OPTION_CLK_EDGE_NEG, XTTCPS_CLK_CNTRL_EXT_EDGE_MASK,
+	 XTTCPS_CLK_CNTRL_OFFSET},
+	{XTTCPS_OPTION_INTERVAL_MODE, XTTCPS_CNT_CNTRL_INT_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+	{XTTCPS_OPTION_DECREMENT, XTTCPS_CNT_CNTRL_DECR_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+	{XTTCPS_OPTION_MATCH_MODE, XTTCPS_CNT_CNTRL_MATCH_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+	{XTTCPS_OPTION_WAVE_DISABLE, XTTCPS_CNT_CNTRL_EN_WAVE_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+	{XTTCPS_OPTION_WAVE_POLARITY, XTTCPS_CNT_CNTRL_POL_WAVE_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+};
+
+#define XTTCPS_NUM_TMRCTR_OPTIONS (sizeof(TmrCtrOptionsTable) / \
+				sizeof(OptionsMap))
+
+/*****************************************************************************/
+/**
+*
+* This function sets the options for the TTC device.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	Options contains the specified options to be set. This is a bit
+*		mask where a 1 means to turn the option on, and a 0 means to
+*		turn the option off. One or more bit values may be contained
+*		in the mask. See the bit definitions named XTTCPS_*_OPTION in
+*		the file xttcps.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_FAILURE if any of the options are unknown.
+*
+* @note		None
+*
+******************************************************************************/
+s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options)
+{
+	u32 CountReg;
+	u32 ClockReg;
+	u32 Index;
+	s32 Status = XST_SUCCESS;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XTTCPS_CLK_CNTRL_OFFSET);
+	CountReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XTTCPS_CNT_CNTRL_OFFSET);
+
+	/*
+	 * Loop through the options table, turning the option on or off
+	 * depending on whether the bit is set in the incoming options flag.
+	 */
+	for (Index = 0U; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) {
+		if(Status != (s32)XST_FAILURE) {
+			if ((Options & TmrCtrOptionsTable[Index].Option) != (u32)0) {
+
+			switch (TmrCtrOptionsTable[Index].Register) {
+
+			case XTTCPS_CLK_CNTRL_OFFSET:
+				/* Add option */
+				ClockReg |= TmrCtrOptionsTable[Index].Mask;
+				break;
+
+			case XTTCPS_CNT_CNTRL_OFFSET:
+				/* Add option */
+				CountReg |= TmrCtrOptionsTable[Index].Mask;
+				break;
+
+			default:
+				Status = XST_FAILURE;
+				break;
+			}
+		}
+		else {
+			switch (TmrCtrOptionsTable[Index].Register) {
+
+			case XTTCPS_CLK_CNTRL_OFFSET:
+				/* Remove option*/
+				ClockReg &= ~TmrCtrOptionsTable[Index].Mask;
+				break;
+
+			case XTTCPS_CNT_CNTRL_OFFSET:
+				/* Remove option*/
+				CountReg &= ~TmrCtrOptionsTable[Index].Mask;
+				break;
+
+			default:
+				Status = XST_FAILURE;
+				break;
+				}
+			}
+		}
+	}
+
+	/*
+	 * Now write the registers. Leave it to the upper layers to restart the
+	 * device.
+	 */
+	if (Status != (s32)XST_FAILURE ) {
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_CLK_CNTRL_OFFSET, ClockReg);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_CNT_CNTRL_OFFSET, CountReg);
+	}
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the settings for the options for the TTC device.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return
+*
+* The return u32 contains the specified options that are set. This is a bit
+* mask where a '1' means the option is on, and a'0' means the option is off.
+* One or more bit values may be contained in the mask. See the bit definitions
+* named XTTCPS_*_OPTION in the file xttcps.h.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XTtcPs_GetOptions(XTtcPs *InstancePtr)
+{
+	u32 OptionsFlag = 0U;
+	u32 Register;
+	u32 Index;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	/*
+	 * Loop through the options table to determine which options are set
+	 */
+	for (Index = 0U; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) {
+		/*
+		 * Get the control register to determine which options are
+		 * currently set.
+		 */
+		Register = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+					      TmrCtrOptionsTable[Index].
+					      Register);
+
+		if ((Register & TmrCtrOptionsTable[Index].Mask) != (u32)0) {
+			OptionsFlag |= TmrCtrOptionsTable[Index].Option;
+		}
+	}
+
+	return OptionsFlag;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_selftest.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_selftest.c
new file mode 100644
index 0000000000000000000000000000000000000000..4923df667d2426c1bac4c782bfaf0a7cba872811
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_selftest.c
@@ -0,0 +1,109 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_selftest.c
+* @addtogroup ttcps_v3_0
+* @{
+*
+* This file contains the implementation of self test function for the
+* XTtcPs driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Runs a self-test on the driver/device.
+*
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return
+*
+*	- XST_SUCCESS if successful
+*	- XST_FAILURE indicates a register did not read or write correctly
+*
+* @note		This test fails if it is not called right after initialization.
+*
+******************************************************************************/
+s32 XTtcPs_SelfTest(XTtcPs *InstancePtr)
+{
+	s32 Status;
+	u32 TempReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * All the TTC registers should be in their default state right now.
+	 */
+	TempReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XTTCPS_CNT_CNTRL_OFFSET);
+	if (XTTCPS_CNT_CNTRL_RESET_VALUE != (u32)TempReg) {
+		Status = XST_FAILURE;
+	}
+	else {
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_sinit.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..ef3c6ea6bed4c51e500bbcbad22f644746604b5d
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/ttcps_v3_3/src/xttcps_sinit.c
@@ -0,0 +1,98 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_sinit.c
+* @addtogroup ttcps_v3_0
+* @{
+*
+* The implementation of the XTtcPs driver's static initialization functionality.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XTtcPs_Config XTtcPs_ConfigTable[XPAR_XTTCPS_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the unique ID of the device
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xttcps.h for the definition of XTtcPs_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId)
+{
+	XTtcPs_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XTTCPS_NUM_INSTANCES; Index++) {
+		if (XTtcPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XTtcPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XTtcPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/Makefile b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..88b1e625cc135e2c0a0a0ebd6a3a5aca68ce7639
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xuartps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling uartps"
+
+xuartps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xuartps_includes
+
+xuartps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps.c
new file mode 100644
index 0000000000000000000000000000000000000000..1a2c708ba2e712faa07e498f1ca9ca8e816231c0
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps.c
@@ -0,0 +1,644 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps.c
+* @addtogroup uartps_v3_1
+* @{
+*
+* This file contains the implementation of the interface functions for XUartPs
+* driver. Refer to the header file xuartps.h for more detailed information.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	 Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	drg/jz 01/13/10 First Release
+* 2.2   hk     06/23/14 SW reset of RX and TX should be done when changing
+*                       baud rate. CR# 804281.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn    04/10/15 Modified code for latest RTL changes.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xuartps.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+
+/* The following constant defines the amount of error that is allowed for
+ * a specified baud rate. This error is the difference between the actual
+ * baud rate that will be generated using the specified clock and the
+ * desired baud rate.
+ */
+#define XUARTPS_MAX_BAUD_ERROR_RATE		 3U	/* max % error allowed */
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
+				 u32 ByteCount);
+
+u32  XUartPs_SendBuffer(XUartPs *InstancePtr);
+
+u32  XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
+
+/************************** Variable Definitions ****************************/
+
+/****************************************************************************/
+/**
+*
+* Initializes a specific XUartPs instance such that it is ready to be used.
+* The data format of the device is setup for 8 data bits, 1 stop bit, and no
+* parity by default. The baud rate is set to a default value specified by
+* Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The
+* receive FIFO threshold is set for 8 bytes. The default operating mode of the
+* driver is polled mode.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	Config is a reference to a structure containing information
+*		about a specific XUartPs driver.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, pass in the physical
+*		address instead.
+*
+* @return
+*
+*		- XST_SUCCESS if initialization was successful
+*		- XST_UART_BAUD_ERROR if the baud rate is not possible because
+*		  the inputclock frequency is not divisible with an acceptable
+*		  amount of error
+*
+* @note
+*
+* The default configuration for the UART after initialization is:
+*
+* - 19,200 bps or XPAR_DFT_BAUDRATE if defined
+* - 8 data bits
+* - 1 stop bit
+* - no parity
+* - FIFO's are enabled with a receive threshold of 8 bytes
+* - The RX timeout is enabled with a timeout of 1 (4 char times)
+*
+*   All interrupts are disabled.
+*
+*****************************************************************************/
+s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
+				   XUartPs_Config * Config, u32 EffectiveAddr)
+{
+	s32 Status;
+	u32 ModeRegister;
+	u32 BaudRate;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Config != NULL);
+
+	/* Setup the driver instance using passed in parameters */
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->Config.InputClockHz = Config->InputClockHz;
+	InstancePtr->Config.ModemPinsConnected = Config->ModemPinsConnected;
+
+	/* Initialize other instance data to default values */
+	InstancePtr->Handler = XUartPs_StubHandler;
+
+	InstancePtr->SendBuffer.NextBytePtr = NULL;
+	InstancePtr->SendBuffer.RemainingBytes = 0U;
+	InstancePtr->SendBuffer.RequestedBytes = 0U;
+
+	InstancePtr->ReceiveBuffer.NextBytePtr = NULL;
+	InstancePtr->ReceiveBuffer.RemainingBytes = 0U;
+	InstancePtr->ReceiveBuffer.RequestedBytes = 0U;
+
+	/* Initialize the platform data */
+	InstancePtr->Platform = XGetPlatform_Info();
+
+	InstancePtr->is_rxbs_error = 0U;
+
+	/* Flag that the driver instance is ready to use */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	/*
+	 * Set the default baud rate here, can be changed prior to
+	 * starting the device
+	 */
+	BaudRate = (u32)XUARTPS_DFT_BAUDRATE;
+	Status = XUartPs_SetBaudRate(InstancePtr, BaudRate);
+	if (Status != (s32)XST_SUCCESS) {
+		InstancePtr->IsReady = 0U;
+	} else {
+
+		/*
+		 * Set up the default data format: 8 bit data, 1 stop bit, no
+		 * parity
+		 */
+		ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XUARTPS_MR_OFFSET);
+
+		/* Mask off what's already there */
+		ModeRegister &= (~((u32)XUARTPS_MR_CHARLEN_MASK |
+						 (u32)XUARTPS_MR_STOPMODE_MASK |
+						 (u32)XUARTPS_MR_PARITY_MASK));
+
+		/* Set the register value to the desired data format */
+		ModeRegister |=	((u32)XUARTPS_MR_CHARLEN_8_BIT |
+						 (u32)XUARTPS_MR_STOPMODE_1_BIT |
+						 (u32)XUARTPS_MR_PARITY_NONE);
+
+		/* Write the mode register out */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+				   ModeRegister);
+
+		/* Set the RX FIFO trigger at 8 data bytes. */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_RXWM_OFFSET, 0x08U);
+
+		/* Set the RX timeout to 1, which will be 4 character time */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_RXTOUT_OFFSET, 0x01U);
+
+		/* Disable all interrupts, polled mode is the default */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+				   XUARTPS_IXR_MASK);
+
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sends the specified buffer using the device in either
+* polled or interrupt driven mode. This function is non-blocking, if the device
+* is busy sending data, it will return and indicate zero bytes were sent.
+* Otherwise, it fills the TX FIFO as much as it can, and return the number of
+* bytes sent.
+*
+* In a polled mode, this function will only send as much data as TX FIFO can
+* buffer. The application may need to call it repeatedly to send the entire
+* buffer.
+*
+* In interrupt mode, this function will start sending the specified buffer,
+* then the interrupt handler will continue sending data until the entire
+* buffer has been sent. A callback function, as specified by the application,
+* will be called to indicate the completion of sending.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	BufferPtr is pointer to a buffer of data to be sent.
+* @param  	NumBytes contains the number of bytes to be sent. A value of
+*		zero will stop a previous send operation that is in progress
+*		in interrupt mode. Any data that was already put into the
+*		transmit FIFO will be sent.
+*
+* @return	The number of bytes actually sent.
+*
+* @note
+*
+* The number of bytes is not asserted so that this function may be called with
+* a value of zero to stop an operation that is already in progress.
+* <br><br>
+*
+*****************************************************************************/
+u32 XUartPs_Send(XUartPs *InstancePtr, u8 *BufferPtr,
+			   u32 NumBytes)
+{
+	u32 BytesSent;
+
+	/* Asserts validate the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(BufferPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Disable the UART transmit interrupts to allow this call to stop a
+	 * previous operation that may be interrupt driven.
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+					  (XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_TXFULL));
+
+	/* Setup the buffer parameters */
+	InstancePtr->SendBuffer.RequestedBytes = NumBytes;
+	InstancePtr->SendBuffer.RemainingBytes = NumBytes;
+	InstancePtr->SendBuffer.NextBytePtr = BufferPtr;
+
+	/*
+	 * Transmit interrupts will be enabled in XUartPs_SendBuffer(), after
+	 * filling the TX FIFO.
+	 */
+	BytesSent = XUartPs_SendBuffer(InstancePtr);
+
+	return BytesSent;
+}
+
+/****************************************************************************/
+/**
+*
+* This function attempts to receive a specified number of bytes of data
+* from the device and store it into the specified buffer. This function works
+* for both polled or interrupt driven modes. It is non-blocking.
+*
+* In a polled mode, this function will only receive the data already in the
+* RX FIFO. The application may need to call it repeatedly to receive the
+* entire buffer. Polled mode is the default mode of operation for the device.
+*
+* In interrupt mode, this function will start the receiving, if not the entire
+* buffer has been received, the interrupt handler will continue receiving data
+* until the entire buffer has been received. A callback function, as specified
+* by the application, will be called to indicate the completion of the
+* receiving or error conditions.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	BufferPtr is pointer to buffer for data to be received into
+* @param	NumBytes is the number of bytes to be received. A value of zero
+*		will stop a previous receive operation that is in progress in
+*		interrupt mode.
+*
+* @return	The number of bytes received.
+*
+* @note
+*
+* The number of bytes is not asserted so that this function may be called
+* with a value of zero to stop an operation that is already in progress.
+*
+*****************************************************************************/
+u32 XUartPs_Recv(XUartPs *InstancePtr,
+			  u8 *BufferPtr, u32 NumBytes)
+{
+	u32 ReceivedCount;
+	u32 ImrRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(BufferPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Disable all the interrupts.
+	 * This stops a previous operation that may be interrupt driven
+	 */
+	ImrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_IMR_OFFSET);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+		XUARTPS_IXR_MASK);
+
+	/* Setup the buffer parameters */
+	InstancePtr->ReceiveBuffer.RequestedBytes = NumBytes;
+	InstancePtr->ReceiveBuffer.RemainingBytes = NumBytes;
+	InstancePtr->ReceiveBuffer.NextBytePtr = BufferPtr;
+
+	/* Receive the data from the device */
+	ReceivedCount = XUartPs_ReceiveBuffer(InstancePtr);
+
+	/* Restore the interrupt state */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET,
+		ImrRegister);
+
+	return ReceivedCount;
+}
+
+/****************************************************************************/
+/*
+*
+* This function sends a buffer that has been previously specified by setting
+* up the instance variables of the instance. This function is an internal
+* function for the XUartPs driver such that it may be called from a shell
+* function that sets up the buffer or from an interrupt handler.
+*
+* This function sends the specified buffer in either polled or interrupt
+* driven modes. This function is non-blocking.
+*
+* In a polled mode, this function only sends as much data as the TX FIFO
+* can buffer. The application may need to call it repeatedly to send the
+* entire buffer.
+*
+* In interrupt mode, this function starts the sending of the buffer, if not
+* the entire buffer has been sent, then the interrupt handler continues the
+* sending until the entire buffer has been sent. A callback function, as
+* specified by the application, will be called to indicate the completion of
+* sending.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	The number of bytes actually sent
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XUartPs_SendBuffer(XUartPs *InstancePtr)
+{
+	u32 SentCount = 0U;
+	u32 ImrRegister;
+
+	/*
+	 * If the TX FIFO is full, send nothing.
+	 * Otherwise put bytes into the TX FIFO unil it is full, or all of the
+	 * data has been put into the FIFO.
+	 */
+	while ((!XUartPs_IsTransmitFull(InstancePtr->Config.BaseAddress)) &&
+		   (InstancePtr->SendBuffer.RemainingBytes > SentCount)) {
+
+		/* Fill the FIFO from the buffer */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_FIFO_OFFSET,
+				   ((u32)InstancePtr->SendBuffer.
+				   NextBytePtr[SentCount]));
+
+		/* Increment the send count. */
+		SentCount++;
+	}
+
+	/* Update the buffer to reflect the bytes that were sent from it */
+	InstancePtr->SendBuffer.NextBytePtr += SentCount;
+	InstancePtr->SendBuffer.RemainingBytes -= SentCount;
+
+	/*
+	 * If interrupts are enabled as indicated by the receive interrupt, then
+	 * enable the TX FIFO empty interrupt, so further action can be taken
+	 * for this sending.
+	 */
+	ImrRegister =
+		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_IMR_OFFSET);
+	if (((ImrRegister & XUARTPS_IXR_RXFULL) != (u32)0) ||
+		((ImrRegister & XUARTPS_IXR_RXEMPTY) != (u32)0)||
+		((ImrRegister & XUARTPS_IXR_RXOVR) != (u32)0)) {
+
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+					   XUARTPS_IER_OFFSET,
+					   ImrRegister | (u32)XUARTPS_IXR_TXEMPTY);
+	}
+
+	return SentCount;
+}
+
+/****************************************************************************/
+/*
+*
+* This function receives a buffer that has been previously specified by setting
+* up the instance variables of the instance. This function is an internal
+* function, and it may be called from a shell function that sets up the buffer
+* or from an interrupt handler.
+*
+* This function attempts to receive a specified number of bytes from the
+* device and store it into the specified buffer. This function works for
+* either polled or interrupt driven modes. It is non-blocking.
+*
+* In polled mode, this function only receives as much data as in the RX FIFO.
+* The application may need to call it repeatedly to receive the entire buffer.
+* Polled mode is the default mode for the driver.
+*
+* In interrupt mode, this function starts the receiving, if not the entire
+* buffer has been received, the interrupt handler will continue until the
+* entire buffer has been received. A callback function, as specified by the
+* application, will be called to indicate the completion of the receiving or
+* error conditions.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	The number of bytes received.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr)
+{
+	u32 CsrRegister;
+	u32 ReceivedCount = 0U;
+	u32 ByteStatusValue, EventData;
+	u32 Event;
+
+	/*
+	 * Read the Channel Status Register to determine if there is any data in
+	 * the RX FIFO
+	 */
+	CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUARTPS_SR_OFFSET);
+
+	/*
+	 * Loop until there is no more data in RX FIFO or the specified
+	 * number of bytes has been received
+	 */
+	while((ReceivedCount <= InstancePtr->ReceiveBuffer.RemainingBytes)&&
+		(((CsrRegister & XUARTPS_SR_RXEMPTY) == (u32)0))){
+
+		if (InstancePtr->is_rxbs_error) {
+			ByteStatusValue = XUartPs_ReadReg(
+						InstancePtr->Config.BaseAddress,
+						XUARTPS_RXBS_OFFSET);
+			if((ByteStatusValue & XUARTPS_RXBS_MASK)!= (u32)0) {
+				EventData = ByteStatusValue;
+				Event = XUARTPS_EVENT_PARE_FRAME_BRKE;
+				/*
+				 * Call the application handler to indicate that there is a receive
+				 * error or a break interrupt, if the application cares about the
+				 * error it call a function to get the last errors.
+				 */
+				InstancePtr->Handler(InstancePtr->CallBackRef,
+							Event, EventData);
+			}
+		}
+
+		InstancePtr->ReceiveBuffer.NextBytePtr[ReceivedCount] =
+			XUartPs_ReadReg(InstancePtr->Config.
+				  BaseAddress,
+				  XUARTPS_FIFO_OFFSET);
+
+		ReceivedCount++;
+
+		CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+								XUARTPS_SR_OFFSET);
+	}
+	InstancePtr->is_rxbs_error = 0;
+	/*
+	 * Update the receive buffer to reflect the number of bytes just
+	 * received
+	 */
+	if(InstancePtr->ReceiveBuffer.NextBytePtr != NULL){
+		InstancePtr->ReceiveBuffer.NextBytePtr += ReceivedCount;
+	}
+	InstancePtr->ReceiveBuffer.RemainingBytes -= ReceivedCount;
+
+	return ReceivedCount;
+}
+
+/*****************************************************************************/
+/**
+*
+* Sets the baud rate for the device. Checks the input value for
+* validity and also verifies that the requested rate can be configured to
+* within the maximum error range specified by XUARTPS_MAX_BAUD_ERROR_RATE.
+* If the provided rate is not possible, the current setting is unchanged.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	BaudRate to be set
+*
+* @return
+*		- XST_SUCCESS if everything configured as expected
+*		- XST_UART_BAUD_ERROR if the requested rate is not available
+*		  because there was too much error
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate)
+{
+	u32 IterBAUDDIV;	/* Iterator for available baud divisor values */
+	u32 BRGR_Value;		/* Calculated value for baud rate generator */
+	u32 CalcBaudRate;	/* Calculated baud rate */
+	u32 BaudError;		/* Diff between calculated and requested baud rate */
+	u32 Best_BRGR = 0U;	/* Best value for baud rate generator */
+	u8 Best_BAUDDIV = 0U;	/* Best value for baud divisor */
+	u32 Best_Error = 0xFFFFFFFFU;
+	u32 PercentError;
+	u32 ModeReg;
+	u32 InputClk;
+
+	/* Asserts validate the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(BaudRate <= (u32)XUARTPS_MAX_RATE);
+	Xil_AssertNonvoid(BaudRate >= (u32)XUARTPS_MIN_RATE);
+
+	/*
+	 * Make sure the baud rate is not impossilby large.
+	 * Fastest possible baud rate is Input Clock / 2.
+	 */
+	if ((BaudRate * 2) > InstancePtr->Config.InputClockHz) {
+		return XST_UART_BAUD_ERROR;
+	}
+	/* Check whether the input clock is divided by 8 */
+	ModeReg = XUartPs_ReadReg( InstancePtr->Config.BaseAddress,
+				 XUARTPS_MR_OFFSET);
+
+	InputClk = InstancePtr->Config.InputClockHz;
+	if(ModeReg & XUARTPS_MR_CLKSEL) {
+		InputClk = InstancePtr->Config.InputClockHz / 8;
+	}
+
+	/*
+	 * Determine the Baud divider. It can be 4to 254.
+	 * Loop through all possible combinations
+	 */
+	for (IterBAUDDIV = 4; IterBAUDDIV < 255; IterBAUDDIV++) {
+
+		/* Calculate the value for BRGR register */
+		BRGR_Value = InputClk / (BaudRate * (IterBAUDDIV + 1));
+
+		/* Calculate the baud rate from the BRGR value */
+		CalcBaudRate = InputClk/ (BRGR_Value * (IterBAUDDIV + 1));
+
+		/* Avoid unsigned integer underflow */
+		if (BaudRate > CalcBaudRate) {
+			BaudError = BaudRate - CalcBaudRate;
+		}
+		else {
+			BaudError = CalcBaudRate - BaudRate;
+		}
+
+		/* Find the calculated baud rate closest to requested baud rate. */
+		if (Best_Error > BaudError) {
+
+			Best_BRGR = BRGR_Value;
+			Best_BAUDDIV = IterBAUDDIV;
+			Best_Error = BaudError;
+		}
+	}
+
+	/* Make sure the best error is not too large. */
+	PercentError = (Best_Error * 100) / BaudRate;
+	if (XUARTPS_MAX_BAUD_ERROR_RATE < PercentError) {
+		return XST_UART_BAUD_ERROR;
+	}
+
+	/* Disable TX and RX to avoid glitches when setting the baud rate. */
+	XUartPs_DisableUart(InstancePtr);
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_BAUDGEN_OFFSET, Best_BRGR);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_BAUDDIV_OFFSET, Best_BAUDDIV);
+
+	/* RX and TX SW reset */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_CR_OFFSET,
+				XUARTPS_CR_TXRST | XUARTPS_CR_RXRST);
+
+	/* Enable device */
+	XUartPs_EnableUart(InstancePtr);
+
+	InstancePtr->BaudRate = BaudRate;
+
+	return XST_SUCCESS;
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function is a stub handler that is the default handler such that if the
+* application has not set the handler when interrupts are enabled, this
+* function will be called.
+*
+* @param	CallBackRef is unused by this function.
+* @param	Event is unused by this function.
+* @param	ByteCount is unused by this function.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
+				 u32 ByteCount)
+{
+	(void) CallBackRef;
+	(void) Event;
+	(void) ByteCount;
+	/* Assert occurs always since this is a stub and should never be called */
+	Xil_AssertVoidAlways();
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps.h
new file mode 100644
index 0000000000000000000000000000000000000000..a5155940e6809d9ff6ae853a776e31686b604376
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps.h
@@ -0,0 +1,518 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps.h
+* @addtogroup uartps_v3_1
+* @{
+* @details
+*
+* This driver supports the following features:
+*
+* - Dynamic data format (baud rate, data bits, stop bits, parity)
+* - Polled mode
+* - Interrupt driven mode
+* - Transmit and receive FIFOs (32 byte FIFO depth)
+* - Access to the external modem control lines
+*
+* <b>Initialization & Configuration</b>
+*
+* The XUartPs_Config structure is used by the driver to configure itself.
+* Fields inside this structure are properties of XUartPs based on its hardware
+* build.
+*
+* To support multiple runtime loading and initialization strategies employed
+* by various operating systems, the driver instance can be initialized in the
+* following way:
+*
+*   - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+*	 configuration structure provided by the caller. If running in a system
+*	 with address translation, the parameter EffectiveAddr should be the
+* 	  virtual address.
+*
+* <b>Baud Rate</b>
+*
+* The UART has an internal baud rate generator, which furnishes the baud rate
+* clock for both the receiver and the transmitter. Ther input clock frequency
+* can be either the master clock or the master clock divided by 8, configured
+* through the mode register.
+*
+* Accompanied with the baud rate divider register, the baud rate is determined
+* by:
+* <pre>
+*	baud_rate = input_clock / (bgen * (bdiv + 1)
+* </pre>
+* where bgen is the value of the baud rate generator, and bdiv is the value of
+* baud rate divider.
+*
+* <b>Interrupts</b>
+*
+* The FIFOs are not flushed when the driver is initialized, but a function is
+* provided to allow the user to reset the FIFOs if desired.
+*
+* The driver defaults to no interrupts at initialization such that interrupts
+* must be enabled if desired. An interrupt is generated for one of the
+* following conditions.
+*
+* - A change in the modem signals
+* - Data in the receive FIFO for a configuable time without receiver activity
+* - A parity error
+* - A framing error
+* - An overrun error
+* - Transmit FIFO is full
+* - Transmit FIFO is empty
+* - Receive FIFO is full
+* - Receive FIFO is empty
+* - Data in the receive FIFO equal to the receive threshold
+*
+* The application can control which interrupts are enabled using the
+* XUartPs_SetInterruptMask() function.
+*
+* In order to use interrupts, it is necessary for the user to connect the
+* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt
+* system of the application. A separate handler should be provided by the
+* application to communicate with the interrupt system, and conduct
+* application specific interrupt handling. An application registers its own
+* handler through the XUartPs_SetHandler() function.
+*
+* <b>Data Transfer</b>
+*
+* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the
+* driver to allow data to be sent and received. They can be used in either
+* polled or interrupt mode.
+*
+* @note
+*
+* The default configuration for the UART after initialization is:
+*
+* - 9,600 bps or XPAR_DFT_BAUDRATE if defined
+* - 8 data bits
+* - 1 stop bit
+* - no parity
+* - FIFO's are enabled with a receive threshold of 8 bytes
+* - The RX timeout is enabled with a timeout of 1 (4 char times)
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00a	drg/jz 01/12/10 First Release
+* 1.00a sdm    09/27/11 Fixed compiler warnings and also a bug
+*		        in XUartPs_SetFlowDelay where the value was not
+*			being written to the register.
+* 1.01a sdm    12/20/11 Removed the InputClockHz parameter from the XUartPs
+*			instance structure and the driver is updated to use
+*			InputClockHz parameter from the XUartPs_Config config
+*			structure.
+*			Added a parameter to XUartPs_Config structure which
+*			specifies whether the user has selected Modem pins
+*			to be connected to MIO or FMIO.
+*			Added the tcl file to generate the xparameters.h
+* 1.02a sg     05/16/12	Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
+* 1.03a sg     07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
+*			with the correct values for CR 666724
+* 			Added defines for XUARTPS_IXR_TOVR,  XUARTPS_IXR_TNFUL
+*			and XUARTPS_IXR_TTRIG.
+*			Modified the name of these defines
+*			XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+*			XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+*			XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+*			XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk     08/22/13 Added API for uart reset and related
+*			constant definitions.
+* 2.0   hk      03/07/14 Version number revised.
+* 2.1   hk     04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
+* 2.2   hk     06/23/14 SW reset of RX and TX should be done when changing
+*                       baud rate. CR# 804281.
+* 3.0   vm     12/09/14 Modified source code according to misrac guideline.
+*			Support for Zynq Ultrascale Mp added.
+* 3.1	kvn    04/10/15 Modified code for latest RTL changes. Also added
+*						platform variable in driver instance structure.
+* 3.1   adk   14/03/16  Include interrupt examples in the peripheral test when
+*			uart is connected to a valid interrupt controller CR#946803.
+* 3.2   rk     07/20/16 Modified the logic for transmission break bit set
+* 3.4   ms     01/23/17 Added xil_printf statement in main function for all
+*                       examples to ensure that "Successfully ran" and "Failed"
+*                       strings are available in all examples. This is a fix
+*                       for CR-965028.
+*       ms     03/17/17 Added readme.txt file in examples folder for doxygen
+*                       generation.
+*
+* </pre>
+*
+*****************************************************************************/
+
+#ifndef XUARTPS_H		/* prevent circular inclusions */
+#define XUARTPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xuartps_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants indicate the max and min baud rates and these
+ * numbers are based only on the testing that has been done. The hardware
+ * is capable of other baud rates.
+ */
+#define XUARTPS_MAX_RATE	 921600U
+#define XUARTPS_MIN_RATE	 110U
+
+#define XUARTPS_DFT_BAUDRATE  115200U   /* Default baud rate */
+
+/** @name Configuration options
+ * @{
+ */
+/**
+ * These constants specify the options that may be set or retrieved
+ * with the driver, each is a unique bit mask such that multiple options
+ * may be specified.  These constants indicate the available options
+ * in active state.
+ *
+ */
+
+#define XUARTPS_OPTION_SET_BREAK	0x0080U /**< Starts break transmission */
+#define XUARTPS_OPTION_STOP_BREAK	0x0040U /**< Stops break transmission */
+#define XUARTPS_OPTION_RESET_TMOUT	0x0020U /**< Reset the receive timeout */
+#define XUARTPS_OPTION_RESET_TX		0x0010U /**< Reset the transmitter */
+#define XUARTPS_OPTION_RESET_RX		0x0008U /**< Reset the receiver */
+#define XUARTPS_OPTION_ASSERT_RTS	0x0004U /**< Assert the RTS bit */
+#define XUARTPS_OPTION_ASSERT_DTR	0x0002U /**< Assert the DTR bit */
+#define XUARTPS_OPTION_SET_FCM		0x0001U /**< Turn on flow control mode */
+/*@}*/
+
+
+/** @name Channel Operational Mode
+ *
+ * The UART can operate in one of four modes: Normal, Local Loopback, Remote
+ * Loopback, or automatic echo.
+ *
+ * @{
+ */
+
+#define XUARTPS_OPER_MODE_NORMAL		(u8)0x00U	/**< Normal Mode */
+#define XUARTPS_OPER_MODE_AUTO_ECHO		(u8)0x01U	/**< Auto Echo Mode */
+#define XUARTPS_OPER_MODE_LOCAL_LOOP	(u8)0x02U	/**< Local Loopback Mode */
+#define XUARTPS_OPER_MODE_REMOTE_LOOP	(u8)0x03U	/**< Remote Loopback Mode */
+
+/* @} */
+
+/** @name Data format values
+ *
+ * These constants specify the data format that the driver supports.
+ * The data format includes the number of data bits, the number of stop
+ * bits and parity.
+ *
+ * @{
+ */
+#define XUARTPS_FORMAT_8_BITS		0U /**< 8 data bits */
+#define XUARTPS_FORMAT_7_BITS		2U /**< 7 data bits */
+#define XUARTPS_FORMAT_6_BITS		3U /**< 6 data bits */
+
+#define XUARTPS_FORMAT_NO_PARITY	4U /**< No parity */
+#define XUARTPS_FORMAT_MARK_PARITY	3U /**< Mark parity */
+#define XUARTPS_FORMAT_SPACE_PARITY	2U /**< parity */
+#define XUARTPS_FORMAT_ODD_PARITY	1U /**< Odd parity */
+#define XUARTPS_FORMAT_EVEN_PARITY	0U /**< Even parity */
+
+#define XUARTPS_FORMAT_2_STOP_BIT	2U /**< 2 stop bits */
+#define XUARTPS_FORMAT_1_5_STOP_BIT	1U /**< 1.5 stop bits */
+#define XUARTPS_FORMAT_1_STOP_BIT	0U /**< 1 stop bit */
+/*@}*/
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that an application can handle
+ * using its specific handler function. Note that these constants are not bit
+ * mask, so only one event can be passed to an application at a time.
+ *
+ * @{
+ */
+#define XUARTPS_EVENT_RECV_DATA			1U /**< Data receiving done */
+#define XUARTPS_EVENT_RECV_TOUT			2U /**< A receive timeout occurred */
+#define XUARTPS_EVENT_SENT_DATA			3U /**< Data transmission done */
+#define XUARTPS_EVENT_RECV_ERROR		4U /**< A receive error detected */
+#define XUARTPS_EVENT_MODEM				5U /**< Modem status changed */
+#define XUARTPS_EVENT_PARE_FRAME_BRKE	6U /**< A receive parity, frame, break
+											 *	error detected */
+#define XUARTPS_EVENT_RECV_ORERR		7U /**< A receive overrun error detected */
+/*@}*/
+
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;	 /**< Unique ID  of device */
+	u32 BaseAddress; /**< Base address of device (IPIF) */
+	u32 InputClockHz;/**< Input clock frequency */
+	s32 ModemPinsConnected; /** Specifies whether modem pins are connected
+				 *  to MIO or FMIO */
+} XUartPs_Config;
+
+/* Keep track of state information about a data buffer in the interrupt mode. */
+typedef struct {
+	u8 *NextBytePtr;
+	u32 RequestedBytes;
+	u32 RemainingBytes;
+} XUartPsBuffer;
+
+/**
+ * Keep track of data format setting of a device.
+ */
+typedef struct {
+	u32 BaudRate;	/**< In bps, ie 1200 */
+	u32 DataBits;	/**< Number of data bits */
+	u32 Parity;		/**< Parity */
+	u8 StopBits;	/**< Number of stop bits */
+} XUartPsFormat;
+
+/******************************************************************************/
+/**
+ * This data type defines a handler that an application defines to communicate
+ * with interrupt system to retrieve state information about an application.
+ *
+ * @param	CallBackRef is a callback reference passed in by the upper layer
+ *		when setting the handler, and is passed back to the upper layer
+ *		when the handler is called. It is used to find the device driver
+ *		instance.
+ * @param	Event contains one of the event constants indicating events that
+ *		have occurred.
+ * @param	EventData contains the number of bytes sent or received at the
+ *		time of the call for send and receive events and contains the
+ *		modem status for modem events.
+ *
+ ******************************************************************************/
+typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event,
+				  u32 EventData);
+
+/**
+ * The XUartPs driver instance data structure. A pointer to an instance data
+ * structure is passed around by functions to refer to a specific driver
+ * instance.
+ */
+typedef struct {
+	XUartPs_Config Config;	/* Configuration data structure */
+	u32 InputClockHz;	/* Input clock frequency */
+	u32 IsReady;		/* Device is initialized and ready */
+	u32 BaudRate;		/* Current baud rate */
+
+	XUartPsBuffer SendBuffer;
+	XUartPsBuffer ReceiveBuffer;
+
+	XUartPs_Handler Handler;
+	void *CallBackRef;	/* Callback reference for event handler */
+	u32 Platform;
+	u8 is_rxbs_error;
+} XUartPs;
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Get the UART Channel Status Register.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetChannelStatus(InstancePtr)   \
+	Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET)
+
+/****************************************************************************/
+/**
+* Get the UART Mode Control Register.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_GetControl(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetModeControl(InstancePtr)  \
+	Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET)
+
+/****************************************************************************/
+/**
+* Set the UART Mode Control Register.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*	void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \
+   Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \
+			(u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Enable the transmitter and receiver of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XUartPs_EnableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_EnableUart(InstancePtr) \
+   Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
+	  ((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \
+	  (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN)))
+
+/****************************************************************************/
+/**
+* Disable the transmitter and receiver of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XUartPs_DisableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_DisableUart(InstancePtr) \
+   Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
+	  (((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \
+	  (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS)))
+
+/****************************************************************************/
+/**
+* Determine if the transmitter FIFO is empty.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*		- TRUE if a byte can be sent
+*		- FALSE if the Transmitter Fifo is not empty
+*
+* @note		C-Style signature:
+*		u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitEmpty(InstancePtr)				\
+	((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \
+	 (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY)
+
+
+/************************** Function Prototypes *****************************/
+
+/* Static lookup function implemented in xuartps_sinit.c */
+XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId);
+
+/* Interface functions implemented in xuartps.c */
+s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
+				  XUartPs_Config * Config, u32 EffectiveAddr);
+
+u32 XUartPs_Send(XUartPs *InstancePtr,u8 *BufferPtr,
+			   u32 NumBytes);
+
+u32 XUartPs_Recv(XUartPs *InstancePtr,u8 *BufferPtr,
+			   u32 NumBytes);
+
+s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate);
+
+/* Options functions in xuartps_options.c */
+void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options);
+
+u16 XUartPs_GetOptions(XUartPs *InstancePtr);
+
+void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel);
+
+u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr);
+
+u16 XUartPs_GetModemStatus(XUartPs *InstancePtr);
+
+u32 XUartPs_IsSending(XUartPs *InstancePtr);
+
+u8 XUartPs_GetOperMode(XUartPs *InstancePtr);
+
+void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode);
+
+u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr);
+
+void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue);
+
+u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr);
+
+void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout);
+
+s32 XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
+
+void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
+
+/* interrupt functions in xuartps_intr.c */
+u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr);
+
+void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask);
+
+void XUartPs_InterruptHandler(XUartPs *InstancePtr);
+
+void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
+			 void *CallBackRef);
+
+/* self-test functions in xuartps_selftest.c */
+s32 XUartPs_SelfTest(XUartPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_g.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..b76d00b2a6d8ab8ce88d60c322d27366f6404dc1
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_g.c
@@ -0,0 +1,63 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xuartps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_UART_0_DEVICE_ID,
+		XPAR_PS7_UART_0_BASEADDR,
+		XPAR_PS7_UART_0_UART_CLK_FREQ_HZ,
+		XPAR_PS7_UART_0_HAS_MODEM
+	},
+	{
+		XPAR_PS7_UART_1_DEVICE_ID,
+		XPAR_PS7_UART_1_BASEADDR,
+		XPAR_PS7_UART_1_UART_CLK_FREQ_HZ,
+		XPAR_PS7_UART_1_HAS_MODEM
+	}
+};
+
+
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_hw.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_hw.c
new file mode 100644
index 0000000000000000000000000000000000000000..299dd35aeaead88d3907a0f22b91cb297a606167
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_hw.c
@@ -0,0 +1,180 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_hw.c
+* @addtogroup uartps_v3_1
+* @{
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	drg/jz 01/12/10 First Release
+* 1.05a hk     08/22/13 Added reset function
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xuartps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* This function sends one byte using the device. This function operates in
+* polled mode and blocks until the data has been put into the TX FIFO register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	Data contains the byte to be sent.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SendByte(u32 BaseAddress, u8 Data)
+{
+	/* Wait until there is space in TX FIFO */
+	while (XUartPs_IsTransmitFull(BaseAddress)) {
+		;
+	}
+
+	/* Write the byte into the TX FIFO */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_FIFO_OFFSET, (u32)Data);
+}
+
+/****************************************************************************/
+/**
+*
+* This function receives a byte from the device. It operates in polled mode
+* and blocks until a byte has received.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	The data byte received.
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_RecvByte(u32 BaseAddress)
+{
+	u32 RecievedByte;
+	/* Wait until there is data */
+	while (!XUartPs_IsReceiveData(BaseAddress)) {
+		;
+	}
+	RecievedByte = XUartPs_ReadReg(BaseAddress, XUARTPS_FIFO_OFFSET);
+	/* Return the byte received */
+	return (u8)RecievedByte;
+}
+
+/****************************************************************************/
+/**
+*
+* This function resets UART
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	None
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_ResetHw(u32 BaseAddress)
+{
+
+	/* Disable interrupts */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_IDR_OFFSET, XUARTPS_IXR_MASK);
+
+	/* Disable receive and transmit */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+				((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS));
+
+	/*
+	 * Software reset of receive and transmit
+	 * This clears the FIFO.
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+				((u32)XUARTPS_CR_TXRST | (u32)XUARTPS_CR_RXRST));
+
+	/* Clear status flags - SW reset wont clear sticky flags. */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_ISR_OFFSET, XUARTPS_IXR_MASK);
+
+	/*
+	 * Mode register reset value : All zeroes
+	 * Normal mode, even parity, 1 stop bit
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_MR_OFFSET,
+				XUARTPS_MR_CHMODE_NORM);
+
+	/* Rx and TX trigger register reset values */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_RXWM_OFFSET,
+				XUARTPS_RXWM_RESET_VAL);
+	XUartPs_WriteReg(BaseAddress, XUARTPS_TXWM_OFFSET,
+				XUARTPS_TXWM_RESET_VAL);
+
+	/* Rx timeout disabled by default */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_RXTOUT_OFFSET,
+				XUARTPS_RXTOUT_DISABLE);
+
+	/* Baud rate generator and dividor reset values */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDGEN_OFFSET,
+				XUARTPS_BAUDGEN_RESET_VAL);
+	XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDDIV_OFFSET,
+				XUARTPS_BAUDDIV_RESET_VAL);
+
+	/*
+	 * Control register reset value -
+	 * RX and TX are disable by default
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+				((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS |
+						(u32)XUARTPS_CR_STOPBRK));
+
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..9f5f0b70010d82f4f26a161084a3d48d46504a3e
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_hw.h
@@ -0,0 +1,449 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xuartps_hw.h
+* @addtogroup uartps_v3_1
+* @{
+*
+* This header file contains the hardware interface of an XUartPs device.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	drg/jz 01/12/10 First Release
+* 1.03a sg     09/04/12 Added defines for XUARTPS_IXR_TOVR,  XUARTPS_IXR_TNFUL
+*			and XUARTPS_IXR_TTRIG.
+*			Modified the names of these defines
+*			XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+*			XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+*			XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+*			XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk     08/22/13 Added prototype for uart reset and related
+*			constant definitions.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn    04/10/15 Modified code for latest RTL changes.
+*
+* </pre>
+*
+******************************************************************************/
+#ifndef XUARTPS_HW_H		/* prevent circular inclusions */
+#define XUARTPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the UART.
+ * @{
+ */
+#define XUARTPS_CR_OFFSET		0x0000U  /**< Control Register [8:0] */
+#define XUARTPS_MR_OFFSET		0x0004U  /**< Mode Register [9:0] */
+#define XUARTPS_IER_OFFSET		0x0008U  /**< Interrupt Enable [12:0] */
+#define XUARTPS_IDR_OFFSET		0x000CU  /**< Interrupt Disable [12:0] */
+#define XUARTPS_IMR_OFFSET		0x0010U  /**< Interrupt Mask [12:0] */
+#define XUARTPS_ISR_OFFSET		0x0014U  /**< Interrupt Status [12:0]*/
+#define XUARTPS_BAUDGEN_OFFSET	0x0018U  /**< Baud Rate Generator [15:0] */
+#define XUARTPS_RXTOUT_OFFSET	0x001CU  /**< RX Timeout [7:0] */
+#define XUARTPS_RXWM_OFFSET		0x0020U  /**< RX FIFO Trigger Level [5:0] */
+#define XUARTPS_MODEMCR_OFFSET	0x0024U  /**< Modem Control [5:0] */
+#define XUARTPS_MODEMSR_OFFSET	0x0028U  /**< Modem Status [8:0] */
+#define XUARTPS_SR_OFFSET		0x002CU  /**< Channel Status [14:0] */
+#define XUARTPS_FIFO_OFFSET		0x0030U  /**< FIFO [7:0] */
+#define XUARTPS_BAUDDIV_OFFSET	0x0034U  /**< Baud Rate Divider [7:0] */
+#define XUARTPS_FLOWDEL_OFFSET	0x0038U  /**< Flow Delay [5:0] */
+#define XUARTPS_TXWM_OFFSET		0x0044U  /**< TX FIFO Trigger Level [5:0] */
+#define XUARTPS_RXBS_OFFSET		0x0048U  /**< RX FIFO Byte Status [11:0] */
+/* @} */
+
+/** @name Control Register
+ *
+ * The Control register (CR) controls the major functions of the device.
+ *
+ * Control Register Bit Definition
+ */
+
+#define XUARTPS_CR_STOPBRK	0x00000100U  /**< Stop transmission of break */
+#define XUARTPS_CR_STARTBRK	0x00000080U  /**< Set break */
+#define XUARTPS_CR_TORST	0x00000040U  /**< RX timeout counter restart */
+#define XUARTPS_CR_TX_DIS	0x00000020U  /**< TX disabled. */
+#define XUARTPS_CR_TX_EN	0x00000010U  /**< TX enabled */
+#define XUARTPS_CR_RX_DIS	0x00000008U  /**< RX disabled. */
+#define XUARTPS_CR_RX_EN	0x00000004U  /**< RX enabled */
+#define XUARTPS_CR_EN_DIS_MASK	0x0000003CU  /**< Enable/disable Mask */
+#define XUARTPS_CR_TXRST	0x00000002U  /**< TX logic reset */
+#define XUARTPS_CR_RXRST	0x00000001U  /**< RX logic reset */
+/* @}*/
+
+
+/** @name Mode Register
+ *
+ * The mode register (MR) defines the mode of transfer as well as the data
+ * format. If this register is modified during transmission or reception,
+ * data validity cannot be guaranteed.
+ *
+ * Mode Register Bit Definition
+ * @{
+ */
+#define XUARTPS_MR_CCLK				0x00000400U /**< Input clock selection */
+#define XUARTPS_MR_CHMODE_R_LOOP	0x00000300U /**< Remote loopback mode */
+#define XUARTPS_MR_CHMODE_L_LOOP	0x00000200U /**< Local loopback mode */
+#define XUARTPS_MR_CHMODE_ECHO		0x00000100U /**< Auto echo mode */
+#define XUARTPS_MR_CHMODE_NORM		0x00000000U /**< Normal mode */
+#define XUARTPS_MR_CHMODE_SHIFT				8U  /**< Mode shift */
+#define XUARTPS_MR_CHMODE_MASK		0x00000300U /**< Mode mask */
+#define XUARTPS_MR_STOPMODE_2_BIT	0x00000080U /**< 2 stop bits */
+#define XUARTPS_MR_STOPMODE_1_5_BIT	0x00000040U /**< 1.5 stop bits */
+#define XUARTPS_MR_STOPMODE_1_BIT	0x00000000U /**< 1 stop bit */
+#define XUARTPS_MR_STOPMODE_SHIFT			6U  /**< Stop bits shift */
+#define XUARTPS_MR_STOPMODE_MASK	0x000000A0U /**< Stop bits mask */
+#define XUARTPS_MR_PARITY_NONE		0x00000020U /**< No parity mode */
+#define XUARTPS_MR_PARITY_MARK		0x00000018U /**< Mark parity mode */
+#define XUARTPS_MR_PARITY_SPACE		0x00000010U /**< Space parity mode */
+#define XUARTPS_MR_PARITY_ODD		0x00000008U /**< Odd parity mode */
+#define XUARTPS_MR_PARITY_EVEN		0x00000000U /**< Even parity mode */
+#define XUARTPS_MR_PARITY_SHIFT				3U  /**< Parity setting shift */
+#define XUARTPS_MR_PARITY_MASK		0x00000038U /**< Parity mask */
+#define XUARTPS_MR_CHARLEN_6_BIT	0x00000006U /**< 6 bits data */
+#define XUARTPS_MR_CHARLEN_7_BIT	0x00000004U /**< 7 bits data */
+#define XUARTPS_MR_CHARLEN_8_BIT	0x00000000U /**< 8 bits data */
+#define XUARTPS_MR_CHARLEN_SHIFT			1U  /**< Data Length shift */
+#define XUARTPS_MR_CHARLEN_MASK		0x00000006U /**< Data length mask */
+#define XUARTPS_MR_CLKSEL			0x00000001U /**< Input clock selection */
+/* @} */
+
+
+/** @name Interrupt Registers
+ *
+ * Interrupt control logic uses the interrupt enable register (IER) and the
+ * interrupt disable register (IDR) to set the value of the bits in the
+ * interrupt mask register (IMR). The IMR determines whether to pass an
+ * interrupt to the interrupt status register (ISR).
+ * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
+ * interrupt. IMR and ISR are read only, and IER and IDR are write only.
+ * Reading either IER or IDR returns 0x00.
+ *
+ * All four registers have the same bit definitions.
+ *
+ * @{
+ */
+#define XUARTPS_IXR_RBRK	0x00002000U /**< Rx FIFO break detect interrupt */
+#define XUARTPS_IXR_TOVR	0x00001000U /**< Tx FIFO Overflow interrupt */
+#define XUARTPS_IXR_TNFUL	0x00000800U /**< Tx FIFO Nearly Full interrupt */
+#define XUARTPS_IXR_TTRIG	0x00000400U /**< Tx Trig interrupt */
+#define XUARTPS_IXR_DMS		0x00000200U /**< Modem status change interrupt */
+#define XUARTPS_IXR_TOUT	0x00000100U /**< Timeout error interrupt */
+#define XUARTPS_IXR_PARITY 	0x00000080U /**< Parity error interrupt */
+#define XUARTPS_IXR_FRAMING	0x00000040U /**< Framing error interrupt */
+#define XUARTPS_IXR_OVER	0x00000020U /**< Overrun error interrupt */
+#define XUARTPS_IXR_TXFULL 	0x00000010U /**< TX FIFO full interrupt. */
+#define XUARTPS_IXR_TXEMPTY	0x00000008U /**< TX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXFULL 	0x00000004U /**< RX FIFO full interrupt. */
+#define XUARTPS_IXR_RXEMPTY	0x00000002U /**< RX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXOVR  	0x00000001U /**< RX FIFO trigger interrupt. */
+#define XUARTPS_IXR_MASK	0x00003FFFU /**< Valid bit mask */
+/* @} */
+
+
+/** @name Baud Rate Generator Register
+ *
+ * The baud rate generator control register (BRGR) is a 16 bit register that
+ * controls the receiver bit sample clock and baud rate.
+ * Valid values are 1 - 65535.
+ *
+ * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
+ * in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDGEN_DISABLE		0x00000000U /**< Disable clock */
+#define XUARTPS_BAUDGEN_MASK		0x0000FFFFU /**< Valid bits mask */
+#define XUARTPS_BAUDGEN_RESET_VAL	0x0000028BU /**< Reset value */
+
+/** @name Baud Divisor Rate register
+ *
+ * The baud rate divider register (BDIV) controls how much the bit sample
+ * rate is divided by. It sets the baud rate.
+ * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
+ *
+ * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
+ * the MR_CCLK bit in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDDIV_MASK        0x000000FFU	/**< 8 bit baud divider mask */
+#define XUARTPS_BAUDDIV_RESET_VAL   0x0000000FU	/**< Reset value */
+/* @} */
+
+
+/** @name Receiver Timeout Register
+ *
+ * Use the receiver timeout register (RTR) to detect an idle condition on
+ * the receiver data line.
+ *
+ * @{
+ */
+#define XUARTPS_RXTOUT_DISABLE		0x00000000U  /**< Disable time out */
+#define XUARTPS_RXTOUT_MASK			0x000000FFU  /**< Valid bits mask */
+
+/** @name Receiver FIFO Trigger Level Register
+ *
+ * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
+ * which the RX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_RXWM_DISABLE	0x00000000U  /**< Disable RX trigger interrupt */
+#define XUARTPS_RXWM_MASK		0x0000003FU  /**< Valid bits mask */
+#define XUARTPS_RXWM_RESET_VAL	0x00000020U  /**< Reset value */
+/* @} */
+
+/** @name Transmit FIFO Trigger Level Register
+ *
+ * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
+ * which the TX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_TXWM_MASK		0x0000003FU  /**< Valid bits mask */
+#define XUARTPS_TXWM_RESET_VAL	0x00000020U  /**< Reset value */
+/* @} */
+
+/** @name Modem Control Register
+ *
+ * This register (MODEMCR) controls the interface with the modem or data set,
+ * or a peripheral device emulating a modem.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMCR_FCM	0x00000010U  /**< Flow control mode */
+#define XUARTPS_MODEMCR_RTS	0x00000002U  /**< Request to send */
+#define XUARTPS_MODEMCR_DTR	0x00000001U  /**< Data terminal ready */
+/* @} */
+
+/** @name Modem Status Register
+ *
+ * This register (MODEMSR) indicates the current state of the control lines
+ * from a modem, or another peripheral device, to the CPU. In addition, four
+ * bits of the modem status register provide change information. These bits
+ * are set to a logic 1 whenever a control input from the modem changes state.
+ *
+ * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
+ * status interrupt is generated and this is reflected in the modem status
+ * register.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMSR_FCMS	0x00000100U  /**< Flow control mode (FCMS) */
+#define XUARTPS_MODEMSR_DCD		0x00000080U  /**< Complement of DCD input */
+#define XUARTPS_MODEMSR_RI		0x00000040U  /**< Complement of RI input */
+#define XUARTPS_MODEMSR_DSR		0x00000020U  /**< Complement of DSR input */
+#define XUARTPS_MODEMSR_CTS		0x00000010U  /**< Complement of CTS input */
+#define XUARTPS_MODEMSR_DDCD	0x00000008U  /**< Delta DCD indicator */
+#define XUARTPS_MODEMSR_TERI  0x00000004U  /**< Trailing Edge Ring Indicator */
+#define XUARTPS_MODEMSR_DDSR	0x00000002U  /**< Change of DSR */
+#define XUARTPS_MODEMSR_DCTS	0x00000001U  /**< Change of CTS */
+/* @} */
+
+/** @name Channel Status Register
+ *
+ * The channel status register (CSR) is provided to enable the control logic
+ * to monitor the status of bits in the channel interrupt status register,
+ * even if these are masked out by the interrupt mask register.
+ *
+ * @{
+ */
+#define XUARTPS_SR_TNFUL	0x00004000U /**< TX FIFO Nearly Full Status */
+#define XUARTPS_SR_TTRIG	0x00002000U /**< TX FIFO Trigger Status */
+#define XUARTPS_SR_FLOWDEL	0x00001000U /**< RX FIFO fill over flow delay */
+#define XUARTPS_SR_TACTIVE	0x00000800U /**< TX active */
+#define XUARTPS_SR_RACTIVE	0x00000400U /**< RX active */
+#define XUARTPS_SR_TXFULL	0x00000010U /**< TX FIFO full */
+#define XUARTPS_SR_TXEMPTY	0x00000008U /**< TX FIFO empty */
+#define XUARTPS_SR_RXFULL	0x00000004U /**< RX FIFO full */
+#define XUARTPS_SR_RXEMPTY	0x00000002U /**< RX FIFO empty */
+#define XUARTPS_SR_RXOVR	0x00000001U /**< RX FIFO fill over trigger */
+/* @} */
+
+/** @name Flow Delay Register
+ *
+ * Operation of the flow delay register (FLOWDEL) is very similar to the
+ * receive FIFO trigger register. An internal trigger signal activates when the
+ * FIFO is filled to the level set by this register. This trigger will not
+ * cause an interrupt, although it can be read through the channel status
+ * register. In hardware flow control mode, RTS is deactivated when the trigger
+ * becomes active. RTS only resets when the FIFO level is four less than the
+ * level of the flow delay trigger and the flow delay trigger is not activated.
+ * A value less than 4 disables the flow delay.
+ * @{
+ */
+#define XUARTPS_FLOWDEL_MASK	XUARTPS_RXWM_MASK	/**< Valid bit mask */
+/* @} */
+
+/** @name Receiver FIFO Byte Status Register
+ *
+ * The Receiver FIFO Status register is used to have a continuous
+ * monitoring of the raw unmasked byte status information. The register
+ * contains frame, parity and break status information for the top
+ * four bytes in the RX FIFO.
+ *
+ * Receiver FIFO Byte Status Register Bit Definition
+ * @{
+ */
+#define XUARTPS_RXBS_BYTE3_BRKE		0x00000800U /**< Byte3 Break Error */
+#define XUARTPS_RXBS_BYTE3_FRME		0x00000400U /**< Byte3 Frame Error */
+#define XUARTPS_RXBS_BYTE3_PARE		0x00000200U /**< Byte3 Parity Error */
+#define XUARTPS_RXBS_BYTE2_BRKE		0x00000100U /**< Byte2 Break Error */
+#define XUARTPS_RXBS_BYTE2_FRME		0x00000080U /**< Byte2 Frame Error */
+#define XUARTPS_RXBS_BYTE2_PARE		0x00000040U /**< Byte2 Parity Error */
+#define XUARTPS_RXBS_BYTE1_BRKE		0x00000020U /**< Byte1 Break Error */
+#define XUARTPS_RXBS_BYTE1_FRME		0x00000010U /**< Byte1 Frame Error */
+#define XUARTPS_RXBS_BYTE1_PARE		0x00000008U /**< Byte1 Parity Error */
+#define XUARTPS_RXBS_BYTE0_BRKE		0x00000004U /**< Byte0 Break Error */
+#define XUARTPS_RXBS_BYTE0_FRME		0x00000002U /**< Byte0 Frame Error */
+#define XUARTPS_RXBS_BYTE0_PARE		0x00000001U /**< Byte0 Parity Error */
+#define XUARTPS_RXBS_MASK		0x00000007U /**< 3 bit RX byte status mask */
+/* @} */
+
+
+/*
+ * Defines for backwards compatabilty, will be removed
+ * in the next version of the driver
+ */
+#define XUARTPS_MEDEMSR_DCDX  XUARTPS_MODEMSR_DDCD
+#define XUARTPS_MEDEMSR_RIX   XUARTPS_MODEMSR_TERI
+#define XUARTPS_MEDEMSR_DSRX  XUARTPS_MODEMSR_DDSR
+#define	XUARTPS_MEDEMSR_CTSX  XUARTPS_MODEMSR_DCTS
+
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+* Read a UART register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the base address of the
+*		device.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset)
+*
+******************************************************************************/
+#define XUartPs_ReadReg(BaseAddress, RegOffset) \
+	Xil_In32((BaseAddress) + (u32)(RegOffset))
+
+/***************************************************************************/
+/**
+* Write a UART register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the base address of the
+*		device.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XUartPs_WriteReg(u32 BaseAddress, int RegOffset,
+*						   u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+	Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Determine if there is receive data in the receiver and/or FIFO.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	TRUE if there is receive data, FALSE otherwise.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_IsReceiveData(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsReceiveData(BaseAddress)			 \
+	!((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & 	\
+	(u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY)
+
+/****************************************************************************/
+/**
+* Determine if a byte of data can be sent with the transmitter.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	TRUE if the TX FIFO is full, FALSE if a byte can be put in the
+*		FIFO.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_IsTransmitFull(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitFull(BaseAddress)			 \
+	((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & 	\
+	 (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL)
+
+/************************** Function Prototypes ******************************/
+
+void XUartPs_SendByte(u32 BaseAddress, u8 Data);
+
+u8 XUartPs_RecvByte(u32 BaseAddress);
+
+void XUartPs_ResetHw(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_intr.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_intr.c
new file mode 100644
index 0000000000000000000000000000000000000000..3068ee79567f39ecf0a7a886af7acaa0b9cdeea9
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_intr.c
@@ -0,0 +1,450 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_intr.c
+* @addtogroup uartps_v3_1
+* @{
+*
+* This file contains the functions for interrupt handling
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00  drg/jz 01/13/10 First Release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn    04/10/15 Modified code for latest RTL changes.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+
+static void ReceiveDataHandler(XUartPs *InstancePtr);
+static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus);
+static void ReceiveErrorHandler(XUartPs *InstancePtr, u32 IsrStatus);
+static void ReceiveTimeoutHandler(XUartPs *InstancePtr);
+static void ModemHandler(XUartPs *InstancePtr);
+
+
+/* Internal function prototypes implemented in xuartps.c */
+extern u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
+extern u32 XUartPs_SendBuffer(XUartPs *InstancePtr);
+
+/************************** Variable Definitions ****************************/
+
+typedef void (*Handler)(XUartPs *InstancePtr);
+
+/****************************************************************************/
+/**
+*
+* This function gets the interrupt mask
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*		The current interrupt mask. The mask indicates which interupts
+*		are enabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr)
+{
+	/* Assert validates the input argument */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/* Read the Interrupt Mask register */
+	return (XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+			 XUARTPS_IMR_OFFSET));
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the interrupt mask.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	Mask contains the interrupts to be enabled or disabled.
+*		A '1' enables an interupt, and a '0' disables.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask)
+{
+	u32 TempMask = Mask;
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	TempMask &= (u32)XUARTPS_IXR_MASK;
+
+	/* Write the mask to the IER Register */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+		 XUARTPS_IER_OFFSET, TempMask);
+
+	/* Write the inverse of the Mask to the IDR register */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+		 XUARTPS_IDR_OFFSET, (~TempMask));
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the handler that will be called when an event (interrupt)
+* occurs that needs application's attention.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	FuncPtr is the pointer to the callback function.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+*
+* @return	None.
+*
+* @note
+*
+* There is no assert on the CallBackRef since the driver doesn't know what it
+* is (nor should it)
+*
+*****************************************************************************/
+void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
+		 void *CallBackRef)
+{
+	/*
+	 * Asserts validate the input arguments
+	 * CallBackRef not checked, no way to know what is valid
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FuncPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->Handler = FuncPtr;
+	InstancePtr->CallBackRef = CallBackRef;
+}
+
+/****************************************************************************/
+/**
+*
+* This function is the interrupt handler for the driver.
+* It must be connected to an interrupt system by the application such that it
+* can be called when an interrupt occurs.
+*
+* @param	InstancePtr contains a pointer to the driver instance
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XUartPs_InterruptHandler(XUartPs *InstancePtr)
+{
+	u32 IsrStatus;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the interrupt ID register to determine which
+	 * interrupt is active
+	 */
+	IsrStatus = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_IMR_OFFSET);
+
+	IsrStatus &= XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_ISR_OFFSET);
+
+	/* Dispatch an appropriate handler. */
+	if((IsrStatus & ((u32)XUARTPS_IXR_RXOVR | (u32)XUARTPS_IXR_RXEMPTY |
+			(u32)XUARTPS_IXR_RXFULL)) != (u32)0) {
+		/* Received data interrupt */
+		ReceiveDataHandler(InstancePtr);
+	}
+
+	if((IsrStatus & ((u32)XUARTPS_IXR_TXEMPTY | (u32)XUARTPS_IXR_TXFULL))
+									 != (u32)0) {
+		/* Transmit data interrupt */
+		SendDataHandler(InstancePtr, IsrStatus);
+	}
+
+	/* XUARTPS_IXR_RBRK is applicable only for Zynq Ultrascale+ MP */
+	if ((IsrStatus & ((u32)XUARTPS_IXR_OVER | (u32)XUARTPS_IXR_FRAMING |
+			(u32)XUARTPS_IXR_PARITY | (u32)XUARTPS_IXR_RBRK)) != (u32)0) {
+		/* Received Error Status interrupt */
+		ReceiveErrorHandler(InstancePtr, IsrStatus);
+	}
+
+	if((IsrStatus & ((u32)XUARTPS_IXR_TOUT)) != (u32)0) {
+		/* Received Timeout interrupt */
+		ReceiveTimeoutHandler(InstancePtr);
+	}
+
+	if((IsrStatus & ((u32)XUARTPS_IXR_DMS)) != (u32)0) {
+		/* Modem status interrupt */
+		ModemHandler(InstancePtr);
+	}
+
+	/* Clear the interrupt status. */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_ISR_OFFSET,
+		IsrStatus);
+
+}
+
+/****************************************************************************/
+/*
+*
+* This function handles interrupts for receive errors which include
+* overrun errors, framing errors, parity errors, and the break interrupt.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void ReceiveErrorHandler(XUartPs *InstancePtr, u32 IsrStatus)
+{
+	u32 EventData;
+	u32 Event;
+
+	InstancePtr->is_rxbs_error = 0;
+
+	if ((InstancePtr->Platform == XPLAT_ZYNQ_ULTRA_MP) &&
+		(IsrStatus & ((u32)XUARTPS_IXR_PARITY | (u32)XUARTPS_IXR_RBRK
+					| (u32)XUARTPS_IXR_FRAMING))) {
+		InstancePtr->is_rxbs_error = 1;
+	}
+	/*
+	 * If there are bytes still to be received in the specified buffer
+	 * go ahead and receive them. Removing bytes from the RX FIFO will
+	 * clear the interrupt.
+	 */
+
+	(void)XUartPs_ReceiveBuffer(InstancePtr);
+
+	if (!(InstancePtr->is_rxbs_error)) {
+		Event = XUARTPS_EVENT_RECV_ERROR;
+		EventData = InstancePtr->ReceiveBuffer.RequestedBytes -
+			InstancePtr->ReceiveBuffer.RemainingBytes;
+
+		/*
+		 * Call the application handler to indicate that there is a receive
+		 * error or a break interrupt, if the application cares about the
+		 * error it call a function to get the last errors.
+		 */
+		InstancePtr->Handler(InstancePtr->CallBackRef,
+					Event,
+					EventData);
+	}
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles the receive timeout interrupt. This interrupt occurs
+* whenever a number of bytes have been present in the RX FIFO and the receive
+* data line has been idle for at lease 4 or more character times, (the timeout
+* is set using XUartPs_SetrecvTimeout() function).
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void ReceiveTimeoutHandler(XUartPs *InstancePtr)
+{
+	u32 Event;
+
+	/*
+	 * If there are bytes still to be received in the specified buffer
+	 * go ahead and receive them. Removing bytes from the RX FIFO will
+	 * clear the interrupt.
+	 */
+	if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
+		(void)XUartPs_ReceiveBuffer(InstancePtr);
+	}
+
+	/*
+	 * If there are no more bytes to receive then indicate that this is
+	 * not a receive timeout but the end of the buffer reached, a timeout
+	 * normally occurs if # of bytes is not divisible by FIFO threshold,
+	 * don't rely on previous test of remaining bytes since receive
+	 * function updates it
+	 */
+	if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
+		Event = XUARTPS_EVENT_RECV_TOUT;
+	} else {
+		Event = XUARTPS_EVENT_RECV_DATA;
+	}
+
+	/*
+	 * Call the application handler to indicate that there is a receive
+	 * timeout or data event
+	 */
+	InstancePtr->Handler(InstancePtr->CallBackRef, Event,
+				 InstancePtr->ReceiveBuffer.RequestedBytes -
+				 InstancePtr->ReceiveBuffer.RemainingBytes);
+
+}
+/****************************************************************************/
+/**
+*
+* This function handles the interrupt when data is in RX FIFO.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void ReceiveDataHandler(XUartPs *InstancePtr)
+{
+	/*
+	 * If there are bytes still to be received in the specified buffer
+	 * go ahead and receive them. Removing bytes from the RX FIFO will
+	 * clear the interrupt.
+	 */
+	 if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
+		(void)XUartPs_ReceiveBuffer(InstancePtr);
+	}
+
+	 /* If the last byte of a message was received then call the application
+	 * handler, this code should not use an else from the previous check of
+	 * the number of bytes to receive because the call to receive the buffer
+	 * updates the bytes ramained
+	 */
+	if (InstancePtr->ReceiveBuffer.RemainingBytes == (u32)0) {
+		InstancePtr->Handler(InstancePtr->CallBackRef,
+				XUARTPS_EVENT_RECV_DATA,
+				(InstancePtr->ReceiveBuffer.RequestedBytes -
+				InstancePtr->ReceiveBuffer.RemainingBytes));
+	}
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles the interrupt when data has been sent, the transmit
+* FIFO is empty (transmitter holding register).
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	IsrStatus is the register value for channel status register
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus)
+{
+
+	/*
+	 * If there are not bytes to be sent from the specified buffer then disable
+	 * the transmit interrupt so it will stop interrupting as it interrupts
+	 * any time the FIFO is empty
+	 */
+	if (InstancePtr->SendBuffer.RemainingBytes == (u32)0) {
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUARTPS_IDR_OFFSET,
+				((u32)XUARTPS_IXR_TXEMPTY | (u32)XUARTPS_IXR_TXFULL));
+
+		/* Call the application handler to indicate the sending is done */
+		InstancePtr->Handler(InstancePtr->CallBackRef,
+					XUARTPS_EVENT_SENT_DATA,
+					InstancePtr->SendBuffer.RequestedBytes -
+					InstancePtr->SendBuffer.RemainingBytes);
+	}
+
+	/* If TX FIFO is empty, send more. */
+	else if((IsrStatus & ((u32)XUARTPS_IXR_TXEMPTY)) != (u32)0) {
+		(void)XUartPs_SendBuffer(InstancePtr);
+	}
+	else {
+		/* Else with dummy entry for MISRA-C Compliance.*/
+		;
+	}
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles modem interrupts.  It does not do any processing
+* except to call the application handler to indicate a modem event.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void ModemHandler(XUartPs *InstancePtr)
+{
+	u32 MsrRegister;
+
+	/*
+	 * Read the modem status register so that the interrupt is acknowledged
+	 * and it can be passed to the callback handler with the event
+	 */
+	MsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+			  XUARTPS_MODEMSR_OFFSET);
+
+	/*
+	 * Call the application handler to indicate the modem status changed,
+	 * passing the modem status and the event data in the call
+	 */
+	InstancePtr->Handler(InstancePtr->CallBackRef,
+				  XUARTPS_EVENT_MODEM,
+				  MsrRegister);
+
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_options.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_options.c
new file mode 100644
index 0000000000000000000000000000000000000000..9a699afa1f63724a8c5c703c645115b696114790
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_options.c
@@ -0,0 +1,764 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_options.c
+* @addtogroup uartps_v3_1
+* @{
+*
+* The implementation of the options functions for the XUartPs driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00  drg/jz 01/13/10 First Release
+* 1.00  sdm    09/27/11 Fixed a bug in XUartPs_SetFlowDelay where the input
+*			value was not being written to the register.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.2   rk     07/20/16 Modified the logic for transmission break bit set
+*
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+/*
+ * The following data type is a map from an option to the offset in the
+ * register to which it belongs as well as its bit mask in that register.
+ */
+typedef struct {
+	u16 Option;
+	u16 RegisterOffset;
+	u32 Mask;
+} Mapping;
+
+/*
+ * Create the table which contains options which are to be processed to get/set
+ * the options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+
+static Mapping OptionsTable[] = {
+	{XUARTPS_OPTION_SET_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STARTBRK},
+	{XUARTPS_OPTION_STOP_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STOPBRK},
+	{XUARTPS_OPTION_RESET_TMOUT, XUARTPS_CR_OFFSET, XUARTPS_CR_TORST},
+	{XUARTPS_OPTION_RESET_TX, XUARTPS_CR_OFFSET, XUARTPS_CR_TXRST},
+	{XUARTPS_OPTION_RESET_RX, XUARTPS_CR_OFFSET, XUARTPS_CR_RXRST},
+	{XUARTPS_OPTION_ASSERT_RTS, XUARTPS_MODEMCR_OFFSET,
+	 XUARTPS_MODEMCR_RTS},
+	{XUARTPS_OPTION_ASSERT_DTR, XUARTPS_MODEMCR_OFFSET,
+	 XUARTPS_MODEMCR_DTR},
+	{XUARTPS_OPTION_SET_FCM, XUARTPS_MODEMCR_OFFSET, XUARTPS_MODEMCR_FCM}
+};
+
+/* Create a constant for the number of entries in the table */
+
+#define XUARTPS_NUM_OPTIONS	  (sizeof(OptionsTable) / sizeof(Mapping))
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Gets the options for the specified driver instance. The options are
+* implemented as bit masks such that multiple options may be enabled or
+* disabled simulataneously.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The current options for the UART. The optionss are bit masks that are
+* contained in the file xuartps.h and named XUARTPS_OPTION_*.
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XUartPs_GetOptions(XUartPs *InstancePtr)
+{
+	u16 Options = 0U;
+	u32 Register;
+	u32 Index;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Loop thru the options table to map the physical options in the
+	 * registers of the UART to the logical options to be returned
+	 */
+	for (Index = 0U; Index < XUARTPS_NUM_OPTIONS; Index++) {
+		Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						 OptionsTable[Index].
+						 RegisterOffset);
+
+		/*
+		 * If the bit in the register which correlates to the option
+		 * is set, then set the corresponding bit in the options,
+		 * ignoring any bits which are zero since the options variable
+		 * is initialized to zero
+		 */
+		if ((Register & OptionsTable[Index].Mask) != (u32)0) {
+			Options |= OptionsTable[Index].Option;
+		}
+	}
+
+	return Options;
+}
+
+/****************************************************************************/
+/**
+*
+* Sets the options for the specified driver instance. The options are
+* implemented as bit masks such that multiple options may be enabled or
+* disabled simultaneously.
+*
+* The GetOptions function may be called to retrieve the currently enabled
+* options. The result is ORed in the desired new settings to be enabled and
+* ANDed with the inverse to clear the settings to be disabled. The resulting
+* value is then used as the options for the SetOption function call.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	Options contains the options to be set which are bit masks
+*		contained in the file xuartps.h and named XUARTPS_OPTION_*.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options)
+{
+	u32 Index;
+	u32 Register;
+
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Loop thru the options table to map the logical options to the
+	 * physical options in the registers of the UART.
+	 */
+	for (Index = 0U; Index < XUARTPS_NUM_OPTIONS; Index++) {
+
+		/*
+		 * Read the register which contains option so that the register
+		 * can be changed without destoying any other bits of the
+		 * register.
+		 */
+		Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						 OptionsTable[Index].
+						 RegisterOffset);
+
+		/*
+		 * If the option is set in the input, then set the corresponding
+		 * bit in the specified register, otherwise clear the bit in
+		 * the register.
+		 */
+		if ((Options & OptionsTable[Index].Option) != (u16)0) {
+			if(OptionsTable[Index].Option == XUARTPS_OPTION_SET_BREAK)
+				Register &= ~XUARTPS_CR_STOPBRK;
+			Register |= OptionsTable[Index].Mask;
+		}
+		else {
+			Register &= ~OptionsTable[Index].Mask;
+		}
+
+		/* Write the new value to the register to set the option */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   OptionsTable[Index].RegisterOffset,
+				   Register);
+	}
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the receive FIFO trigger level. The receive trigger
+* level indicates the number of bytes in the receive FIFO that cause a receive
+* data event (interrupt) to be generated.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The current receive FIFO trigger level. This is a value
+*		from 0-31.
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr)
+{
+	u8 RtrigRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the value of the FIFO control register so that the threshold
+	 * can be retrieved, this read takes special register processing
+	 */
+	RtrigRegister = (u8) XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						   XUARTPS_RXWM_OFFSET);
+
+	/* Return only the trigger level from the register value */
+
+	RtrigRegister &= (u8)XUARTPS_RXWM_MASK;
+	return RtrigRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sets the receive FIFO trigger level. The receive trigger
+* level specifies the number of bytes in the receive FIFO that cause a receive
+* data event (interrupt) to be generated.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	TriggerLevel contains the trigger level to set.
+*
+* @return	None
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel)
+{
+	u32 RtrigRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(TriggerLevel <= (u8)XUARTPS_RXWM_MASK);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	RtrigRegister = ((u32)TriggerLevel) & (u32)XUARTPS_RXWM_MASK;
+
+	/*
+	 * Write the new value for the FIFO control register to it such that the
+	 * threshold is changed
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_RXWM_OFFSET, RtrigRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the modem status from the specified UART. The modem
+* status indicates any changes of the modem signals. This function allows
+* the modem status to be read in a polled mode. The modem status is updated
+* whenever it is read such that reading it twice may not yield the same
+* results.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The modem status which are bit masks that are contained in the file
+* xuartps.h and named XUARTPS_MODEM_*.
+*
+* @note
+*
+* The bit masks used for the modem status are the exact bits of the modem
+* status register with no abstraction.
+*
+*****************************************************************************/
+u16 XUartPs_GetModemStatus(XUartPs *InstancePtr)
+{
+	u32 ModemStatusRegister;
+	u16 TmpRegister;
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Read the modem status register to return
+	 */
+	ModemStatusRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XUARTPS_MODEMSR_OFFSET);
+	TmpRegister = (u16)ModemStatusRegister;
+	return TmpRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function determines if the specified UART is sending data.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*		- TRUE if the UART is sending data
+*		- FALSE if UART is not sending data
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XUartPs_IsSending(XUartPs *InstancePtr)
+{
+	u32 ChanStatRegister;
+	u32 ChanTmpSRegister;
+	u32 ActiveResult;
+	u32 EmptyResult;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the channel status register to determine if the transmitter is
+	 * active
+	 */
+	ChanStatRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						 XUARTPS_SR_OFFSET);
+
+	/*
+	 * If the transmitter is active, or the TX FIFO is not empty, then indicate
+	 * that the UART is still sending some data
+	 */
+	ActiveResult = ChanStatRegister & ((u32)XUARTPS_SR_TACTIVE);
+	EmptyResult = ChanStatRegister & ((u32)XUARTPS_SR_TXEMPTY);
+	ChanTmpSRegister = (((u32)XUARTPS_SR_TACTIVE) == ActiveResult) ||
+		(((u32)XUARTPS_SR_TXEMPTY) != EmptyResult);
+
+	return ChanTmpSRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the operational mode of the UART. The UART can operate
+* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic
+* echo.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The operational mode is specified by constants defined in xuartps.h. The
+* constants are named XUARTPS_OPER_MODE_*
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_GetOperMode(XUartPs *InstancePtr)
+{
+	u32 ModeRegister;
+	u8 OperMode;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Read the Mode register. */
+	ModeRegister =
+		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_MR_OFFSET);
+
+	ModeRegister &= (u32)XUARTPS_MR_CHMODE_MASK;
+	/* Return the constant */
+	switch (ModeRegister) {
+	case XUARTPS_MR_CHMODE_NORM:
+		OperMode = XUARTPS_OPER_MODE_NORMAL;
+		break;
+	case XUARTPS_MR_CHMODE_ECHO:
+		OperMode = XUARTPS_OPER_MODE_AUTO_ECHO;
+		break;
+	case XUARTPS_MR_CHMODE_L_LOOP:
+		OperMode = XUARTPS_OPER_MODE_LOCAL_LOOP;
+		break;
+	case XUARTPS_MR_CHMODE_R_LOOP:
+		OperMode = XUARTPS_OPER_MODE_REMOTE_LOOP;
+		break;
+	default:
+		OperMode = (u8) ((ModeRegister & (u32)XUARTPS_MR_CHMODE_MASK) >>
+			XUARTPS_MR_CHMODE_SHIFT);
+		break;
+	}
+
+	return OperMode;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the operational mode of the UART. The UART can operate
+* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic
+* echo.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	OperationMode is the mode of the UART.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode)
+{
+	u32 ModeRegister;
+
+	/* Assert validates the input arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(OperationMode <= XUARTPS_OPER_MODE_REMOTE_LOOP);
+
+	/* Read the Mode register. */
+	ModeRegister =
+		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_MR_OFFSET);
+
+	/* Set the correct value by masking the bits, then ORing the const. */
+	ModeRegister &= (u32)(~XUARTPS_MR_CHMODE_MASK);
+
+	switch (OperationMode) {
+		case XUARTPS_OPER_MODE_NORMAL:
+			ModeRegister |= (u32)XUARTPS_MR_CHMODE_NORM;
+			break;
+		case XUARTPS_OPER_MODE_AUTO_ECHO:
+			ModeRegister |= (u32)XUARTPS_MR_CHMODE_ECHO;
+			break;
+		case XUARTPS_OPER_MODE_LOCAL_LOOP:
+			ModeRegister |= (u32)XUARTPS_MR_CHMODE_L_LOOP;
+			break;
+		case XUARTPS_OPER_MODE_REMOTE_LOOP:
+			ModeRegister |= (u32)XUARTPS_MR_CHMODE_R_LOOP;
+			break;
+		default:
+			/* Default case made for MISRA-C Compliance. */
+			break;
+	}
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+			   ModeRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Flow Delay.
+* 0 - 3: Flow delay inactive
+* 4 - 32: If Flow Control mode is enabled, UART_rtsN is deactivated when the
+* receive FIFO fills to this level.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The Flow Delay is specified by constants defined in xuartps_hw.h. The
+* constants are named XUARTPS_FLOWDEL*
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr)
+{
+	u32 FdelTmpRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Read the Mode register. */
+	FdelTmpRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+					 XUARTPS_FLOWDEL_OFFSET);
+
+	/* Return the contents of the flow delay register */
+	FdelTmpRegister = (u8)(FdelTmpRegister & (u32)XUARTPS_FLOWDEL_MASK);
+	return  FdelTmpRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Flow Delay.
+* 0 - 3: Flow delay inactive
+* 4 - 63: If Flow Control mode is enabled, UART_rtsN is deactivated when the
+* receive FIFO fills to this level.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	FlowDelayValue is the Setting for the flow delay.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue)
+{
+	u32 FdelRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FlowDelayValue > (u8)XUARTPS_FLOWDEL_MASK);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Set the correct value by shifting the input constant, then masking
+	 * the bits
+	 */
+	FdelRegister = ((u32)FlowDelayValue) & (u32)XUARTPS_FLOWDEL_MASK;
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_FLOWDEL_OFFSET, FdelRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the Receive Timeout of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The current setting for receive time out.
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr)
+{
+	u32 RtoRegister;
+	u8 RtoRTmpRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Read the Receive Timeout register. */
+	RtoRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XUARTPS_RXTOUT_OFFSET);
+
+	/* Return the contents of the mode register shifted appropriately */
+	RtoRTmpRegister = (u8)(RtoRegister & (u32)XUARTPS_RXTOUT_MASK);
+	return RtoRTmpRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Receive Timeout of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	RecvTimeout setting allows the UART to detect an idle connection
+*		on the reciever data line.
+*		Timeout duration = RecvTimeout x 4 x Bit Period. 0 disables the
+*		timeout function.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout)
+{
+	u32 RtoRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Set the correct value by masking the bits */
+	RtoRegister = ((u32)RecvTimeout & (u32)XUARTPS_RXTOUT_MASK);
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_RXTOUT_OFFSET, RtoRegister);
+
+	/* Configure CR to restart the receiver timeout counter */
+	RtoRegister =
+		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_CR_OFFSET);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_CR_OFFSET,
+			   (RtoRegister | XUARTPS_CR_TORST));
+
+}
+/****************************************************************************/
+/**
+*
+* Sets the data format for the device. The data format includes the
+* baud rate, number of data bits, number of stop bits, and parity. It is the
+* caller's responsibility to ensure that the UART is not sending or receiving
+* data when this function is called.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	FormatPtr is a pointer to a format structure containing the data
+*		format to be set.
+*
+* @return
+*		- XST_SUCCESS if the data format was successfully set.
+*		- XST_UART_BAUD_ERROR indicates the baud rate could not be
+*		set because of the amount of error with the baud rate and
+*		the input clock frequency.
+*		- XST_INVALID_PARAM if one of the parameters was not valid.
+*
+* @note
+*
+* The data types in the format type, data bits and parity, are 32 bit fields
+* to prevent a compiler warning.
+* The asserts in this function will cause a warning if these fields are
+* bytes.
+* <br><br>
+*
+*****************************************************************************/
+s32 XUartPs_SetDataFormat(XUartPs *InstancePtr,
+			XUartPsFormat * FormatPtr)
+{
+	s32 Status;
+	u32 ModeRegister;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(FormatPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Verify the inputs specified are valid */
+	if ((FormatPtr->DataBits > ((u32)XUARTPS_FORMAT_6_BITS)) ||
+		(FormatPtr->StopBits > ((u8)XUARTPS_FORMAT_2_STOP_BIT)) ||
+		(FormatPtr->Parity > ((u32)XUARTPS_FORMAT_NO_PARITY))) {
+		Status = XST_INVALID_PARAM;
+	} else {
+
+		/*
+		 * Try to set the baud rate and if it's not successful then don't
+		 * continue altering the data format, this is done first to avoid the
+		 * format from being altered when an error occurs
+		 */
+		Status = XUartPs_SetBaudRate(InstancePtr, FormatPtr->BaudRate);
+		if (Status != (s32)XST_SUCCESS) {
+			;
+		} else {
+
+			ModeRegister =
+				XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						  XUARTPS_MR_OFFSET);
+
+			/*
+			 * Set the length of data (8,7,6) by first clearing out the bits
+			 * that control it in the register, then set the length in the register
+			 */
+			ModeRegister &= (u32)(~XUARTPS_MR_CHARLEN_MASK);
+			ModeRegister |= (FormatPtr->DataBits << XUARTPS_MR_CHARLEN_SHIFT);
+
+			/*
+			 * Set the number of stop bits in the mode register by first clearing
+			 * out the bits that control it in the register, then set the number
+			 * of stop bits in the register.
+			 */
+			ModeRegister &= (u32)(~XUARTPS_MR_STOPMODE_MASK);
+			ModeRegister |= (((u32)FormatPtr->StopBits) << XUARTPS_MR_STOPMODE_SHIFT);
+
+			/*
+			 * Set the parity by first clearing out the bits that control it in the
+			 * register, then set the bits in the register, the default is no parity
+			 * after clearing the register bits
+			 */
+			ModeRegister &= (u32)(~XUARTPS_MR_PARITY_MASK);
+			ModeRegister |= (FormatPtr->Parity << XUARTPS_MR_PARITY_SHIFT);
+
+			/* Update the mode register */
+			XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+					   ModeRegister);
+
+			Status = XST_SUCCESS;
+		}
+	}
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Gets the data format for the specified UART. The data format includes the
+* baud rate, number of data bits, number of stop bits, and parity.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	FormatPtr is a pointer to a format structure that will contain
+*		the data format after this call completes.
+*
+* @return	None.
+*
+* @note		None.
+*
+*
+*****************************************************************************/
+void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr)
+{
+	u32 ModeRegister;
+
+
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FormatPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Get the baud rate from the instance, this is not retrieved from the
+	 * hardware because it is only kept as a divisor such that it is more
+	 * difficult to get back to the baud rate
+	 */
+	FormatPtr->BaudRate = InstancePtr->BaudRate;
+
+	ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_MR_OFFSET);
+
+	/* Get the length of data (8,7,6,5) */
+	FormatPtr->DataBits =
+		((ModeRegister & (u32)XUARTPS_MR_CHARLEN_MASK) >>
+		XUARTPS_MR_CHARLEN_SHIFT);
+
+	/* Get the number of stop bits */
+	FormatPtr->StopBits =
+		(u8)((ModeRegister & (u32)XUARTPS_MR_STOPMODE_MASK) >>
+		XUARTPS_MR_STOPMODE_SHIFT);
+
+	/* Determine what parity is */
+	FormatPtr->Parity =
+		(u32)((ModeRegister & (u32)XUARTPS_MR_PARITY_MASK) >>
+		XUARTPS_MR_PARITY_SHIFT);
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_selftest.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_selftest.c
new file mode 100644
index 0000000000000000000000000000000000000000..a1a7dd366b14e24f6bb16d82a46a2d9c0be739a3
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_selftest.c
@@ -0,0 +1,166 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_selftest.c
+* @addtogroup uartps_v3_1
+* @{
+*
+* This file contains the self-test functions for the XUartPs driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00	drg/jz 01/13/10 First Release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xuartps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XUARTPS_TOTAL_BYTES (u8)32
+
+/************************** Variable Definitions *****************************/
+
+static u8 TestString[XUARTPS_TOTAL_BYTES]="abcdefghABCDEFGH012345677654321";
+static u8 ReturnString[XUARTPS_TOTAL_BYTES];
+
+/************************** Function Prototypes ******************************/
+
+
+/****************************************************************************/
+/**
+*
+* This function runs a self-test on the driver and hardware device. This self
+* test performs a local loopback and verifies data can be sent and received.
+*
+* The time for this test is proportional to the baud rate that has been set
+* prior to calling this function.
+*
+* The mode and control registers are restored before return.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return
+*		 - XST_SUCCESS if the test was successful
+*		- XST_UART_TEST_FAIL if the test failed looping back the data
+*
+* @note
+*
+* This function can hang if the hardware is not functioning properly.
+*
+******************************************************************************/
+s32 XUartPs_SelfTest(XUartPs *InstancePtr)
+{
+	s32 Status = XST_SUCCESS;
+	u32 IntrRegister;
+	u32 ModeRegister;
+	u8 Index;
+	u32 ReceiveDataResult;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Disable all interrupts in the interrupt disable register */
+	IntrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_IMR_OFFSET);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+		XUARTPS_IXR_MASK);
+
+	/* Setup for local loopback */
+	ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_MR_OFFSET);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+			   ((ModeRegister & (u32)(~XUARTPS_MR_CHMODE_MASK)) |
+				(u32)XUARTPS_MR_CHMODE_L_LOOP));
+
+	/* Send a number of bytes and receive them, one at a time. */
+	for (Index = 0U; Index < XUARTPS_TOTAL_BYTES; Index++) {
+		/*
+		 * Send out the byte and if it was not sent then the failure
+		 * will be caught in the comparison at the end
+		 */
+		(void)XUartPs_Send(InstancePtr, &TestString[Index], 1U);
+
+		/*
+		 * Wait until the byte is received. This can hang if the HW
+		 * is broken. Watch for the FIFO empty flag to be false.
+		 */
+		ReceiveDataResult = Xil_In32((InstancePtr->Config.BaseAddress) + XUARTPS_SR_OFFSET) &
+				XUARTPS_SR_RXEMPTY;
+		while (ReceiveDataResult == XUARTPS_SR_RXEMPTY ) {
+			ReceiveDataResult = Xil_In32((InstancePtr->Config.BaseAddress) + XUARTPS_SR_OFFSET) &
+					XUARTPS_SR_RXEMPTY;
+		}
+
+		/* Receive the byte */
+		(void)XUartPs_Recv(InstancePtr, &ReturnString[Index], 1U);
+	}
+
+	/*
+	 * Compare the bytes received to the bytes sent to verify the exact data
+	 * was received
+	 */
+	for (Index = 0U; Index < XUARTPS_TOTAL_BYTES; Index++) {
+		if (TestString[Index] != ReturnString[Index]) {
+			Status = XST_UART_TEST_FAIL;
+		}
+	}
+
+	/*
+	 * Restore the registers which were altered to put into polling and
+	 * loopback modes so that this test is not destructive
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET,
+			   IntrRegister);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+			   ModeRegister);
+
+	return Status;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_sinit.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..8dc87dae3cc3d026efd4ae8b76f3201fff43227f
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/uartps_v3_4/src/xuartps_sinit.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_sinit.c
+* @addtogroup uartps_v3_1
+* @{
+*
+* The implementation of the XUartPs driver's static initialzation
+* functionality.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00  drg/jz 01/13/10 First Release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+extern XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES];
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device
+*
+* @return	A pointer to the configuration structure or NULL if the
+*		specified device is not in the system.
+*
+* @note		None.
+*
+******************************************************************************/
+XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId)
+{
+	XUartPs_Config *CfgPtr = NULL;
+
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XUARTPS_NUM_INSTANCES; Index++) {
+		if (XUartPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XUartPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XUartPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/Makefile b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..7cf97e2f02131dc8dcc848251f88cf637781f852
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/Makefile
@@ -0,0 +1,41 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xusbps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling usbps"
+
+xusbps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xusbps_includes
+
+xusbps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
+
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.c
new file mode 100644
index 0000000000000000000000000000000000000000..897c09497d2a874a4e131f447245ca486413d5ff
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.c
@@ -0,0 +1,364 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal 
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************/
+/**
+ * @file xusbps.c
+* @addtogroup usbps_v2_2
+* @{
+ *
+ * The XUsbPs driver. Functions in this file are the minimum required
+ * functions for this driver. See xusbps.h for a detailed description of the
+ * driver.
+ *
+ * @note	None.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- --------------------------------------------------------
+ * 1.00a jz  10/10/10 First release
+ * 2.1   kpc 04/28/14 Removed ununsed functions
+ * </pre>
+ ******************************************************************************/
+
+/***************************** Include Files **********************************/
+#include <stdio.h>
+#include "xusbps.h"
+
+/************************** Constant Definitions ******************************/
+
+/**************************** Type Definitions ********************************/
+
+/***************** Macros (Inline Functions) Definitions **********************/
+
+/************************** Variable Definitions ******************************/
+
+/************************** Function Prototypes *******************************/
+
+/*****************************************************************************/
+/**
+*
+* This function initializes a XUsbPs instance/driver.
+*
+* The initialization entails:
+* - Initialize all members of the XUsbPs structure.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	ConfigPtr is a pointer to a XUsbPs_Config configuration
+*		structure. This structure will contain the requested
+*		configuration for the device. Typically, this is a local
+*		structure and the content of which will be copied into the
+*		configuration structure within XUsbPs.
+* @param	VirtBaseAddress is the base address of the device. For systems
+*		with virtual memory, this address must be the virtual address
+*		of the device.
+* 		For systems that do not support virtual memory this address
+* 		should be the physical address of the device. For backwards
+* 		compatibilty NULL may be passed in systems that do not support
+* 		virtual memory (deprecated).
+*
+* @return
+*		- XST_SUCCESS no errors occured.
+*		- XST_FAILURE an error occured during initialization.
+*
+* @note
+*		After calling XUsbPs_CfgInitialize() the controller
+*		IS NOT READY for use. Before the controller can be used its
+*		DEVICE parameters must be configured. See xusbps.h
+*		for details.
+*
+******************************************************************************/
+int XUsbPs_CfgInitialize(XUsbPs *InstancePtr,
+			  const XUsbPs_Config *ConfigPtr, u32 VirtBaseAddress)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr   != NULL);
+
+	/* Copy the config structure. */
+	InstancePtr->Config = *ConfigPtr;
+
+	/* Check if the user provided a non-NULL base address. If so, we have
+	 * to overwrite the base address in the configuration structure.
+	 */
+	if (0 != VirtBaseAddress) {
+		InstancePtr->Config.BaseAddress = VirtBaseAddress;
+	}
+
+	/* Initialize the XUsbPs structure to default values. */
+	InstancePtr->CurrentAltSetting	= XUSBPS_DEFAULT_ALT_SETTING;
+
+	InstancePtr->HandlerFunc	= NULL;
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function performs device reset, device is stopped at the end.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @return	None.
+*
+* @note 	None.
+*
+******************************************************************************/
+void XUsbPs_DeviceReset(XUsbPs *InstancePtr)
+{
+	int Timeout;
+
+	/* Clear all setup token semaphores by reading the
+	 * XUSBPS_EPSTAT_OFFSET register and writing its value back to
+	 * itself.
+	 */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPSTAT_OFFSET,
+		XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XUSBPS_EPSTAT_OFFSET));
+
+	/* Clear all the endpoint complete status bits by reading the
+	 * XUSBPS_EPCOMPL_OFFSET register and writings its value back
+	 * to itself.
+	 */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPCOMPL_OFFSET,
+		XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XUSBPS_EPCOMPL_OFFSET));
+
+	/* Cancel all endpoint prime status by waiting until all bits
+	 * in XUSBPS_EPPRIME_OFFSET are 0 and then writing 0xFFFFFFFF
+	 * to XUSBPS_EPFLUSH_OFFSET.
+	 *
+	 * Avoid hanging here by using a Timeout counter...
+	 */
+	Timeout = XUSBPS_TIMEOUT_COUNTER;
+	while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_EPPRIME_OFFSET) &
+				XUSBPS_EP_ALL_MASK) && --Timeout) {
+		/* NOP */
+	}
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_EPFLUSH_OFFSET, 0xFFFFFFFF);
+
+	XUsbPs_Stop(InstancePtr);
+
+	/* Write to CR register for controller reset */
+ 	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET,
+		XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_CMD_OFFSET) | XUSBPS_CMD_RST_MASK);
+
+	/* Wait for reset to finish, hardware clears the reset bit once done  */
+	Timeout = 1000000;
+	while((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_CMD_OFFSET) &
+				XUSBPS_CMD_RST_MASK) && --Timeout) {
+		/* NOP */
+	}
+}
+/*****************************************************************************/
+/**
+*
+* This function resets the USB device. All the configuration registers are
+* reset to their default values. The function waits until the reset operation
+* is complete or for a certain duration within which the reset operation is
+* expected to be completed.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @return
+*		- XST_SUCCESS Reset operation completed successfully.
+*		- XST_FAILURE Reset operation timed out.
+*
+* @note 	None.
+*
+******************************************************************************/
+int XUsbPs_Reset(XUsbPs *InstancePtr)
+{
+	int Timeout;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/* Write a 1 to the RESET bit. The RESET bit is cleared by HW once the
+	 * RESET is complete.
+	 *
+	 * We are going to wait for the RESET bit to clear before we return
+	 * from this function. Unfortunately we do not have timers available at
+	 * this point to determine when we should report a Timeout.
+	 *
+	 * However, by using a large number for the poll loop we can assume
+	 * that the polling operation will take longer than the expected time
+	 * the HW needs to RESET. If the poll loop expires we can assume a
+	 * Timeout. The drawback is that on a slow system (and even on a fast
+	 * system) this can lead to _very_ long Timeout periods.
+	 */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_CMD_OFFSET, XUSBPS_CMD_RST_MASK);
+
+
+	/* Wait for the RESET bit to be cleared by HW. */
+	Timeout = XUSBPS_TIMEOUT_COUNTER;
+	while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_CMD_OFFSET) &
+				XUSBPS_CMD_RST_MASK) && --Timeout) {
+		/* NOP */
+	}
+
+	if (0 == Timeout) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * USB Suspend
+ *
+ * In order to conserve power, USB devices automatically enter the suspended
+ * state when the device has observed no bus traffic for a specified period.
+ * When suspended, the USB device maintains any internal status, including its
+ * address and configuration. Attached devices must be prepared to suspend at
+ * any time they are powered, regardless of if they have been assigned a
+ * non-default address, are configured, or neither. Bus activity may cease due
+ * to the host entering a suspend mode of its own. In addition, a USB device
+ * shall also enter the suspended state when the hub port it is attached to is
+ * disabled.
+ *
+ * A USB device exits suspend mode when there is bus activity. A USB device may
+ * also request the host to exit suspend mode or selective suspend by using
+ * electrical signaling to indicate remote wakeup. The ability of a device to
+ * signal remote wakeup is optional. If the USB device is capable of remote
+ * wakeup signaling, the device must support the ability of the host to enable
+ * and disable this capability. When the device is reset, remote wakeup
+ * signaling must be disabled.
+ *
+ * @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+ *
+ * @return
+ *		- XST_SUCCESS if the USB device has entered Suspend mode
+ *		successfully
+ *		- XST_FAILURE on any error
+ *
+ * @note 	None.
+ *
+ ******************************************************************************/
+int XUsbPs_Suspend(const XUsbPs *InstancePtr)
+{
+	(void) InstancePtr;
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* USB Resume
+*
+ If the USB controller is suspended, its operation is resumed when any
+* non-idle signaling is received on its upstream facing port.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @return
+*		- XST_SUCCESS if the USB device has Resumed successfully
+*		- XST_FAILURE on any error
+*
+* @note 	None.
+*
+******************************************************************************/
+int XUsbPs_Resume(const XUsbPs *InstancePtr)
+{
+	(void) InstancePtr;
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* USB Assert Resume
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @return
+*		- XST_SUCCESS if the USB device has Resumed successfully
+*		- XST_FAILURE on any error
+*
+* @note 	None.
+*
+******************************************************************************/
+
+int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr)
+{
+	(void) InstancePtr;
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* This functions sets the controller's DEVICE address. It also sets the
+* advance bit so the controller will wait for the next IN-ACK before the new
+* address takes effect.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	Address is the Address of the device.
+*
+* @return
+*		- XST_SUCCESS: Address set successfully.
+*		- XST_FAILURE: An error occured.
+*		- XST_INVALID_PARAM: Invalid parameter passed, e.g. address
+*		value too big.
+*
+* @note 	None.
+*
+*****************************************************************************/
+int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/* Check address range validity. */
+	if (Address > XUSBPS_DEVICEADDR_MAX) {
+		return XST_INVALID_PARAM;
+	}
+
+	/* Set the address register with the Address value provided. Also set
+	 * the Address Advance Bit. This will cause the address to be set only
+	 * after an IN occured and has been ACKed on the endpoint.
+	 */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_DEVICEADDR_OFFSET,
+			 	(Address << XUSBPS_DEVICEADDR_ADDR_SHIFT) |
+			 	XUSBPS_DEVICEADDR_DEVICEAADV_MASK);
+
+	return XST_SUCCESS;
+}
+
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.h
new file mode 100644
index 0000000000000000000000000000000000000000..4a4492cdc0af2d44d7063f4e04986b750d9a54c8
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.h
@@ -0,0 +1,1096 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal 
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xusbps.h
+* @addtogroup usbps_v2_2
+* @{
+* @details
+ *
+ * This file contains the implementation of the XUsbPs driver. It is the
+ * driver for an USB controller in DEVICE or HOST mode.
+ *
+ * <h2>Introduction</h2>
+ *
+ * The Spartan-3AF Embedded Peripheral Block contains a USB controller for
+ * communication with serial peripherals or hosts. The USB controller supports
+ * Host, Device and On the Go (OTG) applications.
+ *
+ * <h2>USB Controller Features</h2>
+ *
+ * - Supports Low Speed USB 1.1 (1.5Mbps), Full Speed USB 1.1 (12Mbps), and
+ *   High Speed USB 2.0 (480Mbps) data speeds
+ * - Supports Device, Host and OTG operational modes
+ * - ULPI transceiver interface for USB 2.0 operation
+ * - Integrated USB Full and Low speed serial transceiver interfaces for lowest
+ *   cost connections
+ *
+ * <h2>Initialization & Configuration</h2>
+ *
+ * The configuration of the USB driver happens in multiple stages:
+ *
+ * - (a) Configuration of the basic parameters:
+ *   In this stage the basic parameters for the driver are configured,
+ *   including the base address and the controller ID.
+ *
+ * - (b) Configuration of the DEVICE endpoints (if applicable):
+ *   If DEVICE mode is desired, the endpoints of the controller need to be
+ *   configured using the XUsbPs_DeviceConfig data structure. Once the
+ *   endpoint configuration is set up in the data structure, The user then
+ *   needs to allocate the required amount of DMAable memory and
+ *   finalize the configuration of the XUsbPs_DeviceConfig data structure,
+ *   e.g. setting the DMAMemVirt and DMAMemPhys members.
+ *
+ * - (c) Configuration of the DEVICE modes:
+ *   In the second stage the parameters for DEVICE are configured.
+ *   The caller only needs to configure the modes that are
+ *   actually used. Configuration is done with the:
+ *   	XUsbPs_ConfigureDevice()
+ * Configuration parameters are defined and passed
+ *   into these functions using the:
+ *      XUsbPs_DeviceConfig data structures.
+ *
+ *
+ * <h2>USB Device Endpoints</h2>
+ *
+ * The USB core supports up to 4 endpoints. Each endpoint has two directions,
+ * an OUT (RX) and an IN (TX) direction. Note that the direction is viewed from
+ * the host's perspective. Endpoint 0 defaults to be the control endpoint and
+ * does not need to be set up. Other endpoints need to be configured and set up
+ * depending on the application. Only endpoints that are actuelly used by the
+ * application need to be initialized.
+ * See the example code (xusbps_intr_example.c) for more information.
+ *
+ *
+ * <h2>Interrupt Handling</h2>
+ *
+ * The USB core uses one interrupt line to report interrupts to the CPU.
+ * Interrupts are handled by the driver's interrupt handler function
+ * XUsbPs_IntrHandler().
+ * It has to be registered with the OS's interrupt subsystem. The driver's
+ * interrupt handler divides incoming interrupts into two categories:
+ *
+ *  - General device interrupts
+ *  - Endopint related interrupts
+ *
+ * The user (typically the adapter layer) can register general interrupt
+ * handler fucntions and endpoint specific interrupt handler functions with the
+ * driver to receive those interrupts by calling the
+ *    XUsbPs_IntrSetHandler()
+ * and
+ *    XUsbPs_EpSetHandler()
+ * functions respectively. Calling these functions with a NULL pointer as the
+ * argument for the function pointer will "clear" the handler function.
+ *
+ * The user can register one handler function for the generic interrupts and
+ * two handler functions for each endpoint, one for the RX (OUT) and one for
+ * the TX (IN) direction. For some applications it may be useful to register a
+ * single endpoint handler function for muliple endpoints/directions.
+ *
+ * When a callback function is called by the driver, parameters identifying the
+ * type of the interrupt will be passed into the handler functions. For general
+ * interrupts the interrupt mask will be passed into the handler function. For
+ * endpoint interrupts the parameters include the number of the endpoint, the
+ * direction (OUT/IN) and the type of the interrupt.
+ *
+ *
+ * <h2>Data buffer handling</h2>
+ *
+ * Data buffers are sent to and received from endpoint using the
+ *    XUsbPs_EpBufferSend(), XUsbPs_EpBufferSendWithZLT()
+ * and
+ *    XUsbPs_EpBufferReceive()
+ * functions.
+ *
+ * User data buffer size is limited to 16 Kbytes. If the user wants to send a
+ * data buffer that is bigger than this limit it needs to break down the data
+ * buffer into multiple fragments and send the fragments individually.
+ *
+ * From the controller perspective Data buffers can be aligned at any boundary.
+ * if the buffers are from cache region then the buffer and buffer size should
+ * be aligned to cache line aligned
+ *
+ *
+ * <h3>Zero copy</h3>
+ *
+ * The driver uses a zero copy mechanism which imposes certain restrictions to
+ * the way the user can handle the data buffers.
+ *
+ * One restriction is that the user needs to release a buffer after it is done
+ * processing the data in the buffer.
+ *
+ * Similarly, when the user sends a data buffer it MUST not re-use the buffer
+ * until it is notified by the driver that the buffer has been transmitted. The
+ * driver will notify the user via the registered endpoint interrupt handling
+ * function by sending a XUSBPS_EP_EVENT_DATA_TX event.
+ *
+ *
+ * <h2>DMA</h2>
+ *
+ * The driver uses DMA internally to move data from/to memory. This behaviour
+ * is transparent to the user. Keeping the DMA handling hidden from the user
+ * has the advantage that the same API can be used with USB cores that do not
+ * support DMA.
+ *
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- ----------------------------------------------------------
+ * 1.00a wgr  10/10/10 First release
+ * 1.02a wgr  05/16/12 Removed comments as they are showing up in SDK
+ *		       Tabs for CR 657898
+ * 1.03a nm   09/21/12 Fixed CR#678977. Added proper sequence for setup packet
+ *                    handling.
+ * 1.04a nm   10/23/12 Fixed CR# 679106.
+ *	      11/02/12 Fixed CR# 683931. Mult bits are set properly in dQH.
+ * 2.00a kpc 04/03/14 Fixed CR#777763. Corrected the setup tripwire macro val.
+ * 2.1   kpc 04/28/14 Removed unused function prototypes
+ * 2.2   kpc 08/23/14 Exported XUsbPs_DeviceReset API as global for calling in
+ *                    code coverage tests.
+ * 2.3   kpc 02/19/14 Fixed CR#873972, CR#873974. Corrected the logic for proper
+ *                    moving of dTD Head/Tail Pointers. Invalidate the cache
+ *                    after buffer receive in Endpoint Buffer Handler.
+ * 2.4   sg  04/26/16 Fixed CR#949693, Corrected the logic for EP flush
+ *       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+ *                    generation.
+ * </pre>
+ *
+ ******************************************************************************/
+
+#ifndef XUSBPS_H
+#define XUSBPS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xusbps_hw.h"
+#include "xil_types.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+/**
+ * @name System hang prevention Timeout counter value.
+ *
+ * This value is used throughout the code to initialize a Timeout counter that
+ * is used when hard polling a register. The ides is to initialize the Timeout
+ * counter to a value that is longer than any expected Timeout but short enough
+ * so the system will continue to work and report an error while the user is
+ * still paying attention. A reasonable Timeout time would be about 10 seconds.
+ * The XUSBPS_TIMEOUT_COUNTER value should be chosen so a polling loop would
+ * run about 10 seconds before a Timeout is detected. For example:
+ *
+ * 	int Timeout = XUSBPS_TIMEOUT_COUNTER;
+ *	while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ *				XUSBPS_CMD_OFFSET) &
+ *				XUSBPS_CMD_RST_MASK) && --Timeout) {
+ *		;
+ *	}
+ *	if (0 == Timeout) {
+ *		return XST_FAILURE;
+ *	}
+ *
+ */
+#define XUSBPS_TIMEOUT_COUNTER		1000000
+
+
+/**
+ * @name Endpoint Direction (bitmask)
+ * Definitions to be used with Endpoint related function that require a
+ * 'Direction' parameter.
+ *
+ * NOTE:
+ *   The direction is always defined from the perspective of the HOST! This
+ *   means that an IN endpoint on the controller is used for sending data while
+ *   the OUT endpoint on the controller is used for receiving data.
+ * @{
+ */
+#define XUSBPS_EP_DIRECTION_IN		0x01 /**< Endpoint direction IN. */
+#define XUSBPS_EP_DIRECTION_OUT		0x02 /**< Endpoint direction OUT. */
+/* @} */
+
+
+/**
+ * @name Endpoint Type
+ * Definitions to be used with Endpoint related functions that require a 'Type'
+ * parameter.
+ * @{
+ */
+#define XUSBPS_EP_TYPE_NONE		0 /**< Endpoint is not used. */
+#define XUSBPS_EP_TYPE_CONTROL		1 /**< Endpoint for Control Transfers */
+#define XUSBPS_EP_TYPE_ISOCHRONOUS 	2 /**< Endpoint for isochronous data */
+#define XUSBPS_EP_TYPE_BULK		3 /**< Endpoint for BULK Transfers. */
+#define XUSBPS_EP_TYPE_INTERRUPT	4 /**< Endpoint for interrupt Transfers */
+/* @} */
+
+/**
+ * Endpoint Max Packet Length in DeviceConfig is a coded value, ch9.6.6.
+ *
+ * @{
+ */
+#define ENDPOINT_MAXP_LENGTH		0x400
+#define ENDPOINT_MAXP_MULT_MASK		0xC00
+#define ENDPOINT_MAXP_MULT_SHIFT	10
+/* @} */
+
+/**
+ * @name Field names for status retrieval
+ * Definitions for the XUsbPs_GetStatus() function call 'StatusType'
+ * parameter.
+ * @{
+ */
+#define XUSBPS_EP_STS_ADDRESS		1 /**< Address of controller. */
+#define XUSBPS_EP_STS_CONTROLLER_STATE	2 /**< Current controller state. */
+/* @} */
+
+
+
+/**
+ * @name USB Default alternate setting
+ *
+ * @{
+ */
+#define XUSBPS_DEFAULT_ALT_SETTING	0 /**< The default alternate setting is 0 */
+/* @} */
+
+/**
+ * @name Endpoint event types
+ * Definitions that are used to identify events that occur on endpoints. Passed
+ * to the endpoint event handler functions registered with
+ * XUsbPs_EpSetHandler().
+ * @{
+ */
+#define XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED	0x01
+			/**< Setup data has been received on the enpoint. */
+#define XUSBPS_EP_EVENT_DATA_RX		0x02
+			/**< Data frame has been received on the endpoint. */
+#define XUSBPS_EP_EVENT_DATA_TX		0x03
+			/**< Data frame has been sent on the endpoint. */
+/* @} */
+
+
+/*
+ * Maximum packet size for endpoint, 1024
+ * @{
+ */
+#define XUSBPS_MAX_PACKET_SIZE		1024
+				/**< Maximum value can be put into the queue head */
+/* @} */
+/**************************** Type Definitions *******************************/
+
+/******************************************************************************
+ * This data type defines the callback function to be used for Endpoint
+ * handlers.
+ *
+ * @param	CallBackRef is the Callback reference passed in by the upper
+ *		layer when setting the handler, and is passed back to the upper
+ *		layer when the handler is called.
+ * @param	EpNum is the Number of the endpoint that caused the event.
+ * @param	EventType is the type of the event that occured on the endpoint.
+ * @param	Data is a pointer to user data pointer specified when callback
+ *		was registered.
+ */
+typedef void (*XUsbPs_EpHandlerFunc)(void *CallBackRef,
+				      u8 EpNum, u8 EventType, void *Data);
+
+
+/******************************************************************************
+ * This data type defines the callback function to be used for the general
+ * interrupt handler.
+ *
+ * @param	CallBackRef is the Callback reference passed in by the upper
+ *		layer when setting the handler, and is passed back to the upper
+ *		layer when the handler is called.
+ * @param	IrqMask is the Content of the interrupt status register. This
+ *		value can be used by the callback function to distinguish the
+ *		individual interrupt types.
+ */
+typedef void (*XUsbPs_IntrHandlerFunc)(void *CallBackRef, u32 IrqMask);
+
+
+/******************************************************************************/
+
+/* The following type definitions are used for referencing Queue Heads and
+ * Transfer Descriptors. The structures themselves are not used, however, the
+ * types are used in the API to avoid using (void *) pointers.
+ */
+typedef u8	XUsbPs_dQH[XUSBPS_dQH_ALIGN];
+typedef u8	XUsbPs_dTD[XUSBPS_dTD_ALIGN];
+
+
+/**
+ * The following data structures are used internally by the L0/L1 driver.
+ * Their contents MUST NOT be changed by the upper layers.
+ */
+
+/**
+ * The following data structure represents OUT endpoint.
+ */
+typedef struct {
+	XUsbPs_dQH	*dQH;
+		/**< Pointer to the Queue Head structure of the endpoint. */
+
+	XUsbPs_dTD	*dTDs;
+		/**< Pointer to the first dTD of the dTD list for this
+		 * endpoint. */
+
+	XUsbPs_dTD	*dTDCurr;
+		/**< Buffer to the currently processed descriptor. */
+
+	u8	*dTDBufs;
+		/**< Pointer to the first buffer of the buffer list for this
+		 * endpoint. */
+
+	XUsbPs_EpHandlerFunc	HandlerFunc;
+		/**< Handler function for this endpoint. */
+	void			*HandlerRef;
+		/**< User data reference for the handler. */
+} XUsbPs_EpOut;
+
+
+/**
+ * The following data structure represents IN endpoint.
+ */
+typedef struct {
+	XUsbPs_dQH	*dQH;
+		/**< Pointer to the Queue Head structure of the endpoint. */
+
+	XUsbPs_dTD	*dTDs;
+		/**< List of pointers to the Transfer Descriptors of the
+		 * endpoint. */
+
+	XUsbPs_dTD	*dTDHead;
+		/**< Buffer to the next available descriptor in the list. */
+
+	XUsbPs_dTD	*dTDTail;
+		/**< Buffer to the last unsent descriptor in the list*/
+
+	XUsbPs_EpHandlerFunc	HandlerFunc;
+		/**< Handler function for this endpoint. */
+	void			*HandlerRef;
+		/**< User data reference for the handler. */
+} XUsbPs_EpIn;
+
+
+/**
+ * The following data structure represents an endpoint used internally
+ * by the L0/L1 driver.
+ */
+typedef struct {
+	/* Each endpoint has an OUT and an IN component.
+	 */
+	XUsbPs_EpOut	Out;	/**< OUT endpoint structure */
+	XUsbPs_EpIn	In;	/**< IN endpoint structure */
+} XUsbPs_Endpoint;
+
+
+
+/**
+ * The following structure is used by the user to receive Setup Data from an
+ * endpoint. Using this structure simplifies the process of interpreting the
+ * setup data in the core's data fields.
+ *
+ * The naming scheme for the members of this structure is different from the
+ * naming scheme found elsewhere in the code. The members of this structure are
+ * defined in the Chapter 9 USB reference guide. Using this naming scheme makes
+ * it easier for people familiar with the standard to read the code.
+ */
+typedef struct {
+	u8  bmRequestType;	/**< bmRequestType in setup data */
+	u8  bRequest;		/**< bRequest in setup data */
+	u16 wValue;		/**< wValue in setup data */
+	u16 wIndex;		/**< wIndex in setup data */
+	u16 wLength;		/**< wLength in setup data */
+}
+XUsbPs_SetupData;
+
+
+/**
+ * Data structures used to configure endpoints.
+ */
+typedef struct {
+	u32	Type;
+		/**< Endpoint type:
+			- XUSBPS_EP_TYPE_CONTROL
+			- XUSBPS_EP_TYPE_ISOCHRONOUS
+			- XUSBPS_EP_TYPE_BULK
+			- XUSBPS_EP_TYPE_INTERRUPT */
+
+	u32	NumBufs;
+		/**< Number of buffers to be handled by this endpoint. */
+	u32	BufSize;
+		/**< Buffer size. Only relevant for OUT (receive) Endpoints. */
+
+	u16	MaxPacketSize;
+		/**< Maximum packet size for this endpoint. This number will
+		 * define the maximum number of bytes sent on the wire per
+		 * transaction. Range: 0..1024 */
+} XUsbPs_EpSetup;
+
+
+/**
+ * Endpoint configuration structure.
+ */
+typedef struct {
+	XUsbPs_EpSetup		Out; /**< OUT component of endpoint. */
+	XUsbPs_EpSetup		In;  /**< IN component of endpoint. */
+} XUsbPs_EpConfig;
+
+
+/**
+ * The XUsbPs_DeviceConfig structure contains the configuration information to
+ * configure the USB controller for DEVICE mode. This data structure is used
+ * with the XUsbPs_ConfigureDevice() function call.
+ */
+typedef struct {
+	u8  NumEndpoints;	/**< Number of Endpoints for the controller.
+				  This number depends on the runtime
+				  configuration of driver. The driver may
+				  configure fewer endpoints than are available
+				  in the core. */
+
+	XUsbPs_EpConfig	EpCfg[XUSBPS_MAX_ENDPOINTS];
+				/**< List of endpoint configurations. */
+
+
+	u32 DMAMemPhys;		/**< Physical base address of DMAable memory
+				  allocated for the driver. */
+
+	/* The following members are used internally by the L0/L1 driver.  They
+	 * MUST NOT be accesses and/or modified in any way by the upper layers.
+	 *
+	 * The reason for having these members is that we generally try to
+	 * avoid allocating memory in the L0/L1 driver as we want to be OS
+	 * independent. In order to avoid allocating memory for this data
+	 * structure wihin L0/L1 we put it into the XUsbPs_DeviceConfig
+	 * structure which is allocated by the caller.
+	 */
+	XUsbPs_Endpoint	Ep[XUSBPS_MAX_ENDPOINTS];
+				/**< List of endpoint metadata structures. */
+
+	u32 PhysAligned;	/**< 64 byte aligned base address of the DMA
+				   memory block. Will be computed and set by
+				   the L0/L1 driver. */
+} XUsbPs_DeviceConfig;
+
+
+/**
+ * The XUsbPs_Config structure contains configuration information for the USB
+ * controller.
+ *
+ * This structure only contains the basic configuration for the controller. The
+ * caller also needs to initialize the controller for the DEVICE mode
+ * using the XUsbPs_DeviceConfig data structures with the
+ * XUsbPs_ConfigureDevice() function call
+ */
+typedef struct {
+	u16 DeviceID;		/**< Unique ID of controller. */
+	u32 BaseAddress;	/**< Core register base address. */
+} XUsbPs_Config;
+
+
+/**
+ * The XUsbPs driver instance data. The user is required to allocate a
+ * variable of this type for every USB controller in the system. A pointer to a
+ * variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XUsbPs_Config Config;	/**< Configuration structure */
+
+	int CurrentAltSetting;	/**< Current alternative setting of interface */
+
+	void *UserDataPtr;	/**< Data pointer to be used by upper layers to
+				  store application dependent data structures.
+				  The upper layers are responsible to allocated
+				  and free the memory. The driver will not
+				  mofidy this data pointer. */
+
+	/**
+	 * The following structures hold the configuration for DEVICE mode
+	 * of the controller. They are initialized using the
+	 * XUsbPs_ConfigureDevice() function call.
+	 */
+	XUsbPs_DeviceConfig	DeviceConfig;
+				/**< Configuration for the DEVICE mode. */
+
+	XUsbPs_IntrHandlerFunc	HandlerFunc;
+		/**< Handler function for the controller. */
+	void			*HandlerRef;
+		/**< User data reference for the handler. */
+	u32			HandlerMask;
+		/**< User interrupt mask. Defines which interrupts will cause
+		 * the callback to be called. */
+} XUsbPs;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/******************************************************************************
+ *
+ * USB CONTROLLER RELATED MACROS
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ * This macro returns the current frame number.
+ *
+ * @param	InstancePtr is a pointer to the XUsbPs instance of the
+ *		controller.
+ *
+ * @return	The current frame number.
+ *
+ * @note	C-style signature:
+ *		u32 XUsbPs_GetFrameNum(const XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_GetFrameNum(InstancePtr) \
+	XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, XUSBPS_FRAME_OFFSET)
+
+
+/*****************************************************************************/
+/**
+ * This macro starts the USB engine.
+ *
+ * @param	InstancePtr is a pointer to the XUsbPs instance of the
+ *		controller.
+ *
+ * @note	C-style signature:
+ * 		void XUsbPs_Start(XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_Start(InstancePtr) \
+	XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
+
+
+/*****************************************************************************/
+/**
+ * This macro stops the USB engine.
+ *
+ * @param	InstancePtr is a pointer to the XUsbPs instance of the
+ *		controller.
+ *
+ * @note	C-style signature:
+ * 		void XUsbPs_Stop(XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_Stop(InstancePtr) \
+	XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
+
+
+/*****************************************************************************/
+/**
+ * This macro forces the USB engine to be in Full Speed (FS) mode.
+ *
+ * @param	InstancePtr is a pointer to the XUsbPs instance of the
+ *		controller.
+ *
+ * @note	C-style signature:
+ * 		void XUsbPs_ForceFS(XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_ForceFS(InstancePtr)					\
+	XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET,		\
+ 		XUSBPS_PORTSCR_PFSC_MASK)
+
+
+/*****************************************************************************/
+/**
+ * This macro starts the USB Timer 0, with repeat option for period of
+ * one second.
+ *
+ * @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+ * @param	Interval is the interval for Timer0 to generate an interrupt
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_StartTimer0(XUsbPs *InstancePtr, u32 Interval)
+ *
+ ******************************************************************************/
+#define XUsbPs_StartTimer0(InstancePtr, Interval) 			\
+{									\
+	XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, 		\
+			XUSBPS_TIMER0_LD_OFFSET, (Interval));		\
+	XUsbPs_SetBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET,		\
+			XUSBPS_TIMER_RUN_MASK |			\
+			XUSBPS_TIMER_RESET_MASK |			\
+			XUSBPS_TIMER_REPEAT_MASK);			\
+}									\
+
+
+/*****************************************************************************/
+/**
+* This macro stops Timer 0.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note		C-style signature:
+*		void XUsbPs_StopTimer0(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_StopTimer0(InstancePtr) \
+	XUsbPs_ClrBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET,		\
+		XUSBPS_TIMER_RUN_MASK)
+
+
+/*****************************************************************************/
+/**
+* This macro reads Timer 0.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note		C-style signature:
+*		void XUsbPs_ReadTimer0(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_ReadTimer0(InstancePtr) 				\
+	XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress,		\
+			XUSBPS_TIMER0_CTL_OFFSET) & 			\
+					XUSBPS_TIMER_COUNTER_MASK
+
+
+/*****************************************************************************/
+/**
+* This macro force remote wakeup on host
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note		C-style signature:
+*  		void XUsbPs_RemoteWakeup(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_RemoteWakeup(InstancePtr) \
+	XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET,		 \
+			XUSBPS_PORTSCR_FPR_MASK)
+
+
+/******************************************************************************
+ *
+ * ENDPOINT RELATED MACROS
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+* This macro enables the given endpoint for the given direction.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	EpNum is number of the endpoint to enable.
+* @param	Dir is direction of the endpoint (bitfield):
+* 			- XUSBPS_EP_DIRECTION_OUT
+* 			- XUSBPS_EP_DIRECTION_IN
+*
+* @note		C-style signature:
+* 		void XUsbPs_EpEnable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpEnable(InstancePtr, EpNum, Dir) \
+	XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum),	 \
+	((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
+	((Dir) & XUSBPS_EP_DIRECTION_IN  ? XUSBPS_EPCR_TXE_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro disables the given endpoint for the given direction.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	EpNum is the number of the endpoint to disable.
+* @param	Dir is the direction of the endpoint (bitfield):
+* 		- XUSBPS_EP_DIRECTION_OUT
+* 		- XUSBPS_EP_DIRECTION_IN
+*
+* @note		C-style signature:
+* 		void XUsbPs_EpDisable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpDisable(InstancePtr, EpNum, Dir) \
+	XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum),		 \
+		((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
+		((Dir) & XUSBPS_EP_DIRECTION_IN  ? XUSBPS_EPCR_TXE_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro stalls the given endpoint for the given direction, and flush
+* the buffers.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	EpNum is number of the endpoint to stall.
+* @param	Dir is the direction of the endpoint (bitfield):
+* 			- XUSBPS_EP_DIRECTION_OUT
+* 			- XUSBPS_EP_DIRECTION_IN
+*
+* @note		C-style signature:
+*		void XUsbPs_EpStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpStall(InstancePtr, EpNum, Dir) \
+	XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum),	 \
+	((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
+	((Dir) & XUSBPS_EP_DIRECTION_IN  ? XUSBPS_EPCR_TXS_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro unstalls the given endpoint for the given direction.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	EpNum is the Number of the endpoint to unstall.
+* @param	Dir is the Direction of the endpoint (bitfield):
+* 		- XUSBPS_EP_DIRECTION_OUT
+* 		- XUSBPS_EP_DIRECTION_IN
+*
+* @note		C-style signature:
+* 		void XUsbPs_EpUnStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpUnStall(InstancePtr, EpNum, Dir) \
+	XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum),	 \
+	((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
+	((Dir) & XUSBPS_EP_DIRECTION_IN  ? XUSBPS_EPCR_TXS_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro flush an endpoint upon interface disable
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	EpNum is the number of the endpoint to flush.
+* @param	Dir is the direction of the endpoint (bitfield):
+* 			- XUSBPS_EP_DIRECTION_OUT
+* 			- XUSBPS_EP_DIRECTION_IN
+*
+* @note		C-style signature:
+*		void XUsbPs_EpFlush(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpFlush(InstancePtr, EpNum, Dir) \
+	XUsbPs_SetBits(InstancePtr, XUSBPS_EPFLUSH_OFFSET,	\
+		1 << (EpNum + ((Dir) & XUSBPS_EP_DIRECTION_OUT ?		\
+			XUSBPS_EPFLUSH_RX_SHIFT:XUSBPS_EPFLUSH_TX_SHIFT))) \
+
+/*****************************************************************************/
+/**
+* This macro enables the interrupts defined by the bit mask.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	IntrMask is the Bit mask of interrupts to be enabled.
+*
+* @note		C-style signature:
+*		void XUsbPs_IntrEnable(XUsbPs *InstancePtr, u32 IntrMask)
+*
+******************************************************************************/
+#define XUsbPs_IntrEnable(InstancePtr, IntrMask)	\
+		XUsbPs_SetBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
+
+
+/*****************************************************************************/
+/**
+* This function disables the interrupts defined by the bit mask.
+*
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	IntrMask is a Bit mask of interrupts to be disabled.
+*
+* @note		C-style signature:
+* 		void XUsbPs_IntrDisable(XUsbPs *InstancePtr, u32 IntrMask)
+*
+******************************************************************************/
+#define XUsbPs_IntrDisable(InstancePtr, IntrMask)	\
+		XUsbPs_ClrBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
+
+
+/*****************************************************************************/
+/**
+* This macro enables the endpoint NAK interrupts defined by the bit mask.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	NakIntrMask is the Bit mask of endpoint NAK interrupts to be
+*		enabled.
+* @note		C-style signature:
+* 		void XUsbPs_NakIntrEnable(XUsbPs *InstancePtr, u32 NakIntrMask)
+*
+******************************************************************************/
+#define XUsbPs_NakIntrEnable(InstancePtr, NakIntrMask)	\
+	XUsbPs_SetBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
+
+
+/*****************************************************************************/
+/**
+* This macro disables the endpoint NAK interrupts defined by the bit mask.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	NakIntrMask is a Bit mask of endpoint NAK interrupts to be
+*		disabled.
+*
+* @note
+* 	C-style signature:
+* 	void XUsbPs_NakIntrDisable(XUsbPs *InstancePtr, u32 NakIntrMask)
+*
+******************************************************************************/
+#define XUsbPs_NakIntrDisable(InstancePtr, NakIntrMask)	\
+	XUsbPs_ClrBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
+
+
+/*****************************************************************************/
+/**
+* This function clears the endpoint NAK interrupts status defined by the
+* bit mask.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	NakIntrMask is the Bit mask of endpoint NAK interrupts to be cleared.
+*
+* @note		C-style signature:
+* 		void XUsbPs_NakIntrClear(XUsbPs *InstancePtr, u32 NakIntrMask)
+*
+******************************************************************************/
+#define XUsbPs_NakIntrClear(InstancePtr, NakIntrMask)			\
+	XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress,		\
+				XUSBPS_EPNAKISR_OFFSET, NakIntrMask)
+
+
+
+/*****************************************************************************/
+/**
+* This macro sets the Interrupt Threshold value in the control register
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	Threshold is the Interrupt threshold to be set.
+* 		Allowed values:
+*			- XUSBPS_CMD_ITHRESHOLD_0 - Immediate interrupt
+*			- XUSBPS_CMD_ITHRESHOLD_1 - 1 Frame
+*			- XUSBPS_CMD_ITHRESHOLD_2 - 2 Frames
+*			- XUSBPS_CMD_ITHRESHOLD_4 - 4 Frames
+*			- XUSBPS_CMD_ITHRESHOLD_8 - 8 Frames
+*			- XUSBPS_CMD_ITHRESHOLD_16 - 16 Frames
+*			- XUSBPS_CMD_ITHRESHOLD_32 - 32 Frames
+*			- XUSBPS_CMD_ITHRESHOLD_64 - 64 Frames
+*
+* @note
+* 	C-style signature:
+*	void XUsbPs_SetIntrThreshold(XUsbPs *InstancePtr, u8 Threshold)
+*
+******************************************************************************/
+#define XUsbPs_SetIntrThreshold(InstancePtr, Threshold)		\
+		XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress,	\
+					XUSBPS_CMD_OFFSET, (Threshold))\
+
+
+/*****************************************************************************/
+/**
+* This macro sets the Tripwire bit in the USB command register.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note		C-style signature:
+*		void XUsbPs_SetTripwire(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_SetSetupTripwire(InstancePtr)				\
+		XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET,	\
+				XUSBPS_CMD_SUTW_MASK)
+
+
+/*****************************************************************************/
+/**
+* This macro clears the Tripwire bit in the USB command register.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note		C-style signature:
+*		void XUsbPs_ClrTripwire(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_ClrSetupTripwire(InstancePtr)				\
+		XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET,	\
+				XUSBPS_CMD_SUTW_MASK)
+
+
+/*****************************************************************************/
+/**
+* This macro checks if the Tripwire bit in the USB command register is set.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @return
+* 		- TRUE: The tripwire bit is still set.
+* 		- FALSE: The tripwire bit has been cleared.
+*
+* @note		C-style signature:
+*		int XUsbPs_TripwireIsSet(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_SetupTripwireIsSet(InstancePtr)				\
+		(XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, 	\
+				XUSBPS_CMD_OFFSET) &			\
+				XUSBPS_CMD_SUTW_MASK ? TRUE : FALSE)
+
+
+/******************************************************************************
+*
+* GENERAL REGISTER / BIT MANIPULATION MACROS
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* This macro sets the given bit mask in the register.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	RegOffset is the register offset to be written.
+* @param	Bits is the Bits to be set in the register
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XUsbPs_SetBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
+*
+*****************************************************************************/
+#define XUsbPs_SetBits(InstancePtr, RegOffset, Bits) \
+	XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset,	\
+		XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, 	\
+					RegOffset) | (Bits));
+
+
+/****************************************************************************/
+/**
+*
+* This macro clears the given bits in the register.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	RegOffset is the register offset to be written.
+* @param	Bits are the bits to be cleared in the register
+*
+* @return	None.
+*
+* @note
+* 	C-style signature:
+*	void XUsbPs_ClrBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
+*
+*****************************************************************************/
+#define XUsbPs_ClrBits(InstancePtr, RegOffset, Bits) \
+	XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset,	\
+		XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, 	\
+				RegOffset) & ~(Bits));
+
+
+/************************** Function Prototypes ******************************/
+
+/**
+ * Setup / Initialize functions.
+ *
+ * Implemented in file xusbps.c
+ */
+int XUsbPs_CfgInitialize(XUsbPs *InstancePtr,
+			  const XUsbPs_Config *ConfigPtr, u32 BaseAddress);
+
+int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr,
+				const XUsbPs_DeviceConfig *CfgPtr);
+
+/**
+ * Common functions used for DEVICE/HOST mode.
+ */
+int XUsbPs_Reset(XUsbPs *InstancePtr);
+
+void XUsbPs_DeviceReset(XUsbPs *InstancePtr);
+
+/**
+ * DEVICE mode specific functions.
+ */
+int XUsbPs_BusReset(XUsbPs *InstancePtr);
+int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address);
+
+
+/**
+ * Handling Suspend and Resume.
+ *
+ * Implemented in xusbps.c
+ */
+int XUsbPs_Suspend(const XUsbPs *InstancePtr);
+int XUsbPs_Resume(const XUsbPs *InstancePtr);
+int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr);
+
+
+/*
+ * Functions for managing Endpoints / Transfers
+ *
+ * Implemented in file xusbps_endpoint.c
+ */
+int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum,
+			const u8 *BufferPtr, u32 BufferLen);
+int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum,
+			const u8 *BufferPtr, u32 BufferLen);
+int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
+			u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle);
+void XUsbPs_EpBufferRelease(u32 Handle);
+
+int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
+			XUsbPs_EpHandlerFunc CallBackFunc,
+			void *CallBackRef);
+int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum,
+			XUsbPs_SetupData *SetupDataPtr);
+
+int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction);
+
+int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr,
+			int EpNum, unsigned short NewDirection, int DirectionChanged);
+
+/*
+ * Interrupt handling functions
+ *
+ * Implemented in file xusbps_intr.c
+ */
+void XUsbPs_IntrHandler(void *InstancePtr);
+
+int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr,
+			   XUsbPs_IntrHandlerFunc CallBackFunc,
+			   void *CallBackRef, u32 Mask);
+/*
+ * Helper functions for static configuration.
+ * Implemented in xusbps_sinit.c
+ */
+XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XUSBPS_H */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.c
new file mode 100644
index 0000000000000000000000000000000000000000..f93c4b8005f1eeca2e5974bf723aea4096db7f61
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.c
@@ -0,0 +1,1454 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************/
+/**
+ * @file xusbps_endpoint.c
+* @addtogroup usbps_v2_2
+* @{
+ *
+ * Endpoint specific function implementations.
+ *
+ * @note     None.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- --------------------------------------------------------
+ * 1.00a jz  10/10/10 First release
+ * 1.03a nm  09/21/12 Fixed CR#678977. Added proper sequence for setup packet
+ *                    handling.
+ * 1.04a nm  11/02/12 Fixed CR#683931. Mult bits are set properly in dQH.
+ * 2.00a kpc 04/03/14 Fixed CR#777763. Updated the macro names 
+ * 2.1   kpc 04/28/14 Added XUsbPs_EpBufferSendWithZLT api and merged common
+ *		      code to XUsbPs_EpQueueRequest.
+ * 2.3   bss 01/19/16 Modified XUsbPs_EpQueueRequest function to fix CR#873972
+ *            (moving of dTD Head/Tail Pointers)and CR#873974(invalidate
+ *            Caches After Buffer Receive in Endpoint Buffer Handler...)
+ * </pre>
+ ******************************************************************************/
+
+/***************************** Include Files **********************************/
+
+#include <string.h> /* for bzero() */
+#include <stdio.h>
+
+#include "xusbps.h"
+#include "xusbps_endpoint.h"
+
+/************************** Constant Definitions ******************************/
+
+/**************************** Type Definitions ********************************/
+
+/************************** Variable Definitions ******************************/
+
+/************************** Function Prototypes ******************************/
+
+static void XUsbPs_EpListInit(XUsbPs_DeviceConfig *DevCfgPtr);
+static void XUsbPs_dQHInit(XUsbPs_DeviceConfig *DevCfgPtr);
+static int  XUsbPs_dTDInit(XUsbPs_DeviceConfig *DevCfgPtr);
+static int  XUsbPs_dTDAttachBuffer(XUsbPs_dTD *dTDPtr,
+					const u8 *BufferPtr, u32 BufferLen);
+
+static void XUsbPs_dQHSetMaxPacketLenISO(XUsbPs_dQH *dQHPtr, u32 Len);
+
+/* Functions to reconfigure endpoint upon host's set alternate interface
+ * request.
+ */
+static void XUsbPs_dQHReinitEp(XUsbPs_DeviceConfig *DevCfgPtr,
+					int EpNum, unsigned short NewDirection);
+static int XUsbPs_dTDReinitEp(XUsbPs_DeviceConfig *DevCfgPtr,
+					int EpNum, unsigned short NewDirection);
+static int XUsbPs_EpQueueRequest(XUsbPs *InstancePtr, u8 EpNum,
+				const u8 *BufferPtr, u32 BufferLen, u8 ReqZero);
+
+/******************************* Functions ************************************/
+
+/*****************************************************************************/
+/**
+ *
+ * This function configures the DEVICE side of the controller. The caller needs
+ * to pass in the desired configuration (e.g. number of endpoints) and a
+ * DMAable buffer that will hold the Queue Head List and the Transfer
+ * Descriptors. The required size for this buffer can be obtained by the caller
+ * using the: XUsbPs_DeviceMemRequired() macro.
+ *
+ * @param	InstancePtr is a pointer to the XUsbPs instance of the
+ *		controller.
+ * @param	CfgPtr is a pointer to the configuration structure that contains
+ *		the desired DEVICE side configuration.
+ *
+ * @return
+ *		- XST_SUCCESS: The operation completed successfully.
+ *		- XST_FAILURE: An error occured.
+ *
+ * @note
+ * 		The caller may configure the controller for both, DEVICE and
+ * 		HOST side.
+ *
+ ******************************************************************************/
+int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr,
+			    const XUsbPs_DeviceConfig *CfgPtr)
+{
+	int	Status;
+	u32 ModeValue = 0x0;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(CfgPtr      != NULL);
+
+	/* Copy the configuration data over into the local instance structure */
+	InstancePtr->DeviceConfig = *CfgPtr;
+
+
+	/* Align the buffer to a 2048 byte (XUSBPS_dQH_BASE_ALIGN) boundary.*/
+	InstancePtr->DeviceConfig.PhysAligned =
+		(InstancePtr->DeviceConfig.DMAMemPhys +
+					 XUSBPS_dQH_BASE_ALIGN) &
+						~(XUSBPS_dQH_BASE_ALIGN -1);
+
+	/* Initialize the endpoint pointer list data structure. */
+	XUsbPs_EpListInit(&InstancePtr->DeviceConfig);
+
+
+	/* Initialize the Queue Head structures in DMA memory. */
+	XUsbPs_dQHInit(&InstancePtr->DeviceConfig);
+
+
+	/* Initialize the Transfer Descriptors in DMA memory.*/
+	Status = XUsbPs_dTDInit(&InstancePtr->DeviceConfig);
+	if (XST_SUCCESS != Status) {
+		return XST_FAILURE;
+	}
+
+	/* Changing the DEVICE mode requires a controller RESET. */
+	if (XST_SUCCESS != XUsbPs_Reset(InstancePtr)) {
+		return XST_FAILURE;
+	}
+
+	/* Set the Queue Head List address. */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_EPLISTADDR_OFFSET,
+				InstancePtr->DeviceConfig.PhysAligned);
+
+	/* Set the USB mode register to configure DEVICE mode.
+	 *
+	 * XUSBPS_MODE_SLOM_MASK note:
+	 *   Disable Setup Lockout. Setup Lockout is not required as we
+	 *   will be using the tripwire mechanism when handling setup
+	 *   packets.
+	 */
+	ModeValue = XUSBPS_MODE_CM_DEVICE_MASK | XUSBPS_MODE_SLOM_MASK;
+
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_MODE_OFFSET, ModeValue);
+
+	XUsbPs_SetBits(InstancePtr, XUSBPS_OTGCSR_OFFSET,
+				XUSBPS_OTGSC_OT_MASK);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* This function sends a given data buffer.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	EpNum is the number of the endpoint to receive data from.
+* @param	BufferPtr is a pointer to the buffer to send.
+* @param	BufferLen is the Buffer length.
+*
+* @return
+*		- XST_SUCCESS: The operation completed successfully.
+*		- XST_FAILURE: An error occured.
+*		- XST_USB_BUF_TOO_BIG: Provided buffer is too big (>16kB).
+*		- XST_USB_NO_DESC_AVAILABLE: No TX descriptor is available.
+*
+******************************************************************************/
+int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum,
+				const u8 *BufferPtr, u32 BufferLen)
+{
+	Xil_AssertNonvoid(InstancePtr  != NULL);
+	Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+	return XUsbPs_EpQueueRequest(InstancePtr, EpNum, BufferPtr,
+					BufferLen, FALSE);
+}
+
+/*****************************************************************************/
+/**
+* This function sends a given data buffer and also zero length packet if the
+* Bufferlen is in multiples of endpoint max packet size.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	EpNum is the number of the endpoint to receive data from.
+* @param	BufferPtr is a pointer to the buffer to send.
+* @param	BufferLen is the Buffer length.
+*
+* @return
+*		- XST_SUCCESS: The operation completed successfully.
+*		- XST_FAILURE: An error occured.
+*		- XST_USB_BUF_TOO_BIG: Provided buffer is too big (>16kB).
+*		- XST_USB_NO_DESC_AVAILABLE: No TX descriptor is available.
+*
+******************************************************************************/
+int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum,
+				const u8 *BufferPtr, u32 BufferLen)
+{
+	u8 ReqZero = FALSE;
+	XUsbPs_EpSetup *Ep;
+
+	Xil_AssertNonvoid(InstancePtr  != NULL);
+	Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+	Ep = &InstancePtr->DeviceConfig.EpCfg[EpNum].In;
+
+	if ((BufferLen >= Ep->MaxPacketSize) &&
+		(BufferLen % Ep->MaxPacketSize == 0)) {
+		ReqZero = TRUE;
+	}
+
+	return XUsbPs_EpQueueRequest(InstancePtr, EpNum, BufferPtr,
+						BufferLen, ReqZero);
+}
+
+/*****************************************************************************/
+/**
+* This function sends a given data buffer and also sends ZLT packet if it is
+* requested.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	EpNum is the number of the endpoint to receive data from.
+* @param	BufferPtr is a pointer to the buffer to send.
+* @param	BufferLen is the Buffer length.
+* @param	ReqZero is the
+*
+* @return
+*		- XST_SUCCESS: The operation completed successfully.
+*		- XST_FAILURE: An error occured.
+*		- XST_USB_BUF_TOO_BIG: Provided buffer is too big (>16kB).
+*		- XST_USB_NO_DESC_AVAILABLE: No TX descriptor is available.
+*
+******************************************************************************/
+static int XUsbPs_EpQueueRequest(XUsbPs *InstancePtr, u8 EpNum,
+				const u8 *BufferPtr, u32 BufferLen, u8 ReqZero)
+{
+	int		Status;
+	u32		Token;
+	XUsbPs_EpIn	*Ep;
+	XUsbPs_dTD	*DescPtr;
+	u32 		Length;
+	u32		PipeEmpty = 1;
+	u32		Mask = 0x00010000;
+	u32		BitMask = Mask << EpNum;
+	u32		RegValue;
+	u32		Temp;
+	u32 exit = 1;
+
+
+	/* Locate the next available buffer in the ring. A buffer is available
+	 * if its descriptor is not active.
+	 */
+	Ep = &InstancePtr->DeviceConfig.Ep[EpNum].In;
+
+	Xil_DCacheFlushRange((unsigned int)BufferPtr, BufferLen);
+
+	if(Ep->dTDTail != Ep->dTDHead) {
+		PipeEmpty = 0;
+	}
+	XUsbPs_dTDInvalidateCache(Ep->dTDHead);
+
+	/* Tell the caller if we do not have any descriptors available. */
+	if (XUsbPs_dTDIsActive(Ep->dTDHead)) {
+		return XST_USB_NO_DESC_AVAILABLE;
+	}
+
+	/* Remember the current head. */
+	DescPtr = Ep->dTDHead;
+
+	do {
+
+		/* Tell the caller if we do not have any descriptors available. */
+		if (XUsbPs_dTDIsActive(Ep->dTDHead)) {
+			return XST_USB_NO_DESC_AVAILABLE;
+		}
+
+		Length = (BufferLen > XUSBPS_dTD_BUF_MAX_SIZE) ? XUSBPS_dTD_BUF_MAX_SIZE : BufferLen;
+		/* Attach the provided buffer to the current descriptor.*/
+		Status = XUsbPs_dTDAttachBuffer(Ep->dTDHead, BufferPtr, Length);
+		if (XST_SUCCESS != Status) {
+			return XST_FAILURE;
+		}
+		BufferLen -= Length;
+		BufferPtr += Length;
+
+		XUsbPs_dTDSetActive(Ep->dTDHead);
+		if (BufferLen == 0 && (ReqZero == FALSE)) {
+			XUsbPs_dTDSetIOC(Ep->dTDHead);
+			exit = 0;
+		}
+		XUsbPs_dTDClrTerminate(Ep->dTDHead);
+		XUsbPs_dTDFlushCache(Ep->dTDHead);
+
+		/* Advance the head descriptor pointer to the next descriptor. */
+		Ep->dTDHead = XUsbPs_dTDGetNLP(Ep->dTDHead);
+		/* Terminate the next descriptor and flush the cache.*/
+		XUsbPs_dTDInvalidateCache(Ep->dTDHead);
+
+		if (ReqZero && BufferLen == 0) {
+			ReqZero = FALSE;
+		}
+
+	} while(BufferLen || exit);
+
+	XUsbPs_dTDSetTerminate(Ep->dTDHead);
+	XUsbPs_dTDFlushCache(Ep->dTDHead);
+
+	if(!PipeEmpty) {
+		/* Read the endpoint prime register. */
+		RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_EPPRIME_OFFSET);
+		if(RegValue & BitMask) {
+			return XST_SUCCESS;
+		}
+
+		do {
+			RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET);
+			XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET,
+						RegValue | XUSBPS_CMD_ATDTW_MASK);
+			Temp = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_EPRDY_OFFSET)
+						& BitMask;
+		} while(!(XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET) &
+				XUSBPS_CMD_ATDTW_MASK));
+
+		RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET);
+		XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET,
+					RegValue & ~XUSBPS_CMD_ATDTW_MASK);
+
+		if(Temp) {
+			return XST_SUCCESS;
+		}
+	}
+
+	/* Check, if the DMA engine is still running. If it is running, we do
+	 * not clear Queue Head fields.
+	 *
+	 * Same cache rule as for the Transfer Descriptor applies for the Queue
+	 * Head.
+	 */
+	XUsbPs_dQHInvalidateCache(Ep->dQH);
+	/* Add the dTD to the dQH */
+	XUsbPs_WritedQH(Ep->dQH, XUSBPS_dQHdTDNLP, DescPtr);
+	Token = XUsbPs_ReaddQH(Ep->dQH, XUSBPS_dQHdTDTOKEN);
+	Token &= ~(XUSBPS_dTDTOKEN_ACTIVE_MASK | XUSBPS_dTDTOKEN_HALT_MASK);
+	XUsbPs_WritedQH(Ep->dQH, XUSBPS_dQHdTDTOKEN, Token);
+
+	XUsbPs_dQHFlushCache(Ep->dQH);
+
+	Status = XUsbPs_EpPrime(InstancePtr, EpNum, XUSBPS_EP_DIRECTION_IN);
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * This function receives a data buffer from the endpoint of the given endpoint
+ * number.
+ *
+ * @param	InstancePtr is a pointer to the XUsbPs instance of the
+ *		controller.
+ * @param	EpNum is the number of the endpoint to receive data from.
+ * @param	BufferPtr (OUT param) is a pointer to the buffer pointer to hold
+ *		the reference of the data buffer.
+ * @param	BufferLenPtr (OUT param) is a pointer to the integer that will
+ *		hold the buffer length.
+ * @param	Handle is the opaque handle to be used when the buffer is
+ *		released.
+ *
+ * @return
+ *		- XST_SUCCESS: The operation completed successfully.
+ *		- XST_FAILURE: An error occured.
+ *		- XST_USB_NO_BUF: No buffer available.
+ *
+ * @note
+ * 		After handling the data in the buffer, the user MUST release
+ * 		the buffer using the Handle by calling the
+ * 		XUsbPs_EpBufferRelease() function.
+ *
+ ******************************************************************************/
+int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
+				u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle)
+{
+	XUsbPs_EpOut	*Ep;
+	XUsbPs_EpSetup	*EpSetup;
+	u32 length = 0;
+
+	Xil_AssertNonvoid(InstancePtr  != NULL);
+	Xil_AssertNonvoid(BufferPtr    != NULL);
+	Xil_AssertNonvoid(BufferLenPtr != NULL);
+	Xil_AssertNonvoid(Handle       != NULL);
+	Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+	/* Locate the next available buffer in the ring. A buffer is available
+	 * if its descriptor is not active.
+	 */
+	Ep = &InstancePtr->DeviceConfig.Ep[EpNum].Out;
+
+	XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
+
+	if (XUsbPs_dTDIsActive(Ep->dTDCurr)) {
+		return XST_USB_NO_BUF;
+	}
+
+	/* The buffer is not active which means that it has been processed by
+	 * the DMA engine and contains valid data.
+	 */
+	EpSetup = &InstancePtr->DeviceConfig.EpCfg[EpNum].Out;
+
+
+	/* Use the buffer pointer stored in the "user data" field of the
+	 * Transfer Descriptor.
+	 */
+	*BufferPtr = (u8 *) XUsbPs_ReaddTD(Ep->dTDCurr,
+						XUSBPS_dTDUSERDATA);
+
+	length = EpSetup->BufSize -
+			XUsbPs_dTDGetTransferLen(Ep->dTDCurr);
+
+	if(length > 0) {
+		*BufferLenPtr = length;
+	}else {
+		*BufferLenPtr = 0;
+	}
+
+	*Handle	= (u32) Ep->dTDCurr;
+
+
+	/* Reset the descriptor's BufferPointer0 and Transfer Length fields to
+	 * their original value. Note that we can not yet re-activate the
+	 * descriptor as the caller will be using the attached buffer. Once the
+	 * caller releases the buffer by calling XUsbPs_EpBufferRelease(), we
+	 * can re-activate the descriptor.
+	 */
+	XUsbPs_WritedTD(Ep->dTDCurr, XUSBPS_dTDBPTR0, *BufferPtr);
+	XUsbPs_dTDSetTransferLen(Ep->dTDCurr, EpSetup->BufSize);
+
+	XUsbPs_dTDFlushCache(Ep->dTDCurr);
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* This function returns a previously received data buffer to the driver.
+*
+* @param	Handle is a pointer to the buffer that is returned.
+*
+* @return	None.
+*
+******************************************************************************/
+void XUsbPs_EpBufferRelease(u32 Handle)
+{
+	XUsbPs_dTD		*dTDPtr;
+
+	/* Perform sanity check on Handle.*/
+	Xil_AssertVoid((0 != Handle) && (0 == (Handle % XUSBPS_dTD_ALIGN)));
+
+	/* Activate the descriptor and clear the Terminate bit. Make sure to do
+	 * the proper cache handling.
+	 */
+	dTDPtr = (XUsbPs_dTD *) Handle;
+
+	XUsbPs_dTDInvalidateCache(dTDPtr);
+
+	XUsbPs_dTDClrTerminate(dTDPtr);
+	XUsbPs_dTDSetActive(dTDPtr);
+	XUsbPs_dTDSetIOC(dTDPtr);
+
+	XUsbPs_dTDFlushCache(dTDPtr);
+
+}
+
+
+/*****************************************************************************/
+/**
+ * This function sets the handler for endpoint events.
+ *
+ * @param	InstancePtr is a pointer to the XUsbPs instance of the
+ *		controller.
+ * @param	EpNum is the number of the endpoint to receive data from.
+ * @param	Direction is the direction of the endpoint (bitfield):
+ * 			- XUSBPS_EP_DIRECTION_OUT
+ * 			- XUSBPS_EP_DIRECTION_IN
+ * @param	CallBackFunc is the Handler callback function.
+ *		Can be NULL if the user wants to disable the handler entry.
+ * @param	CallBackRef is the user definable data pointer that will be
+ *		passed back if the handler is called. May be NULL.
+ *
+ * @return
+ *		- XST_SUCCESS: The operation completed successfully.
+ *		- XST_FAILURE: An error occured.
+ *		- XST_INVALID_PARAM: Invalid parameter passed.
+ *
+ * @note
+ * 		The user can disable a handler by setting the callback function
+ * 		pointer to NULL.
+ *
+ ******************************************************************************/
+int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
+			 XUsbPs_EpHandlerFunc CallBackFunc,
+			 void *CallBackRef)
+{
+	XUsbPs_Endpoint	*Ep;
+
+	Xil_AssertNonvoid(InstancePtr  != NULL);
+	Xil_AssertNonvoid(CallBackFunc != NULL);
+	Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+	Ep = &InstancePtr->DeviceConfig.Ep[EpNum];
+
+	if(Direction & XUSBPS_EP_DIRECTION_OUT) {
+		Ep->Out.HandlerFunc	= CallBackFunc;
+		Ep->Out.HandlerRef	= CallBackRef;
+	}
+
+	if(Direction & XUSBPS_EP_DIRECTION_IN) {
+		Ep->In.HandlerFunc	= CallBackFunc;
+		Ep->In.HandlerRef	= CallBackRef;
+	}
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* This function primes an endpoint.
+*
+* @param	InstancePtr is pointer to the XUsbPs instance.
+* @param	EpNum is the number of the endpoint to receive data from.
+* @param	Direction is the direction of the endpoint (bitfield):
+* 			- XUSBPS_EP_DIRECTION_OUT
+* 			- XUSBPS_EP_DIRECTION_IN
+*
+* @return
+*		- XST_SUCCESS: The operation completed successfully.
+*		- XST_FAILURE: An error occured.
+*		- XST_INVALID_PARAM: Invalid parameter passed.
+*
+* @note		None.
+*
+******************************************************************************/
+int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction)
+{
+	u32	Mask;
+
+	Xil_AssertNonvoid(InstancePtr  != NULL);
+	Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+	/* Get the right bit mask for the endpoint direction. */
+	switch (Direction) {
+
+	case XUSBPS_EP_DIRECTION_OUT:
+		Mask = 0x00000001;
+		break;
+
+	case XUSBPS_EP_DIRECTION_IN:
+		Mask = 0x00010000;
+		break;
+
+	default:
+		return XST_INVALID_PARAM;
+	}
+
+	/* Write the endpoint prime register. */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_EPPRIME_OFFSET, Mask << EpNum);
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* This function extracts the Setup Data from a given endpoint.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	EpNum is the number of the endpoint to receive data from.
+* @param	SetupDataPtr is a pointer to the setup data structure to be
+*		filled.
+*
+* @return
+*		- XST_SUCCESS: The operation completed successfully.
+*		- XST_FAILURE: An error occured.
+*
+* @note		None.
+******************************************************************************/
+int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum,
+				XUsbPs_SetupData *SetupDataPtr)
+{
+	XUsbPs_EpOut	*Ep;
+
+	u32	Data[2];
+	u8	*p;
+
+	int Timeout;
+
+	Xil_AssertNonvoid(InstancePtr  != NULL);
+	Xil_AssertNonvoid(SetupDataPtr != NULL);
+	Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+	Ep = &InstancePtr->DeviceConfig.Ep[EpNum].Out;
+
+
+	/* Get the data from the Queue Heads Setup buffer into local variables
+	 * so we can extract the setup data values.
+	 */
+	do {
+		/* Arm the tripwire. The tripwire will tell us if a new setup
+		 * packet arrived (in which case the tripwire bit will be
+		 * cleared) while we were reading the buffer. If a new setup
+		 * packet arrived the buffer is corrupted and we continue
+		 * reading.
+		 */
+		XUsbPs_SetSetupTripwire(InstancePtr);
+
+		XUsbPs_dQHInvalidateCache(Ep->dQH);
+
+		Data[0] = XUsbPs_ReaddQH(Ep->dQH, XUSBPS_dQHSUB0);
+		Data[1] = XUsbPs_ReaddQH(Ep->dQH, XUSBPS_dQHSUB1);
+	} while (FALSE == XUsbPs_SetupTripwireIsSet(InstancePtr));
+
+	/* Clear the pending endpoint setup stat bit.
+	 */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_EPSTAT_OFFSET, 1 << EpNum);
+
+	/* Clear the Tripwire bit and continue.
+	 */
+	XUsbPs_ClrSetupTripwire(InstancePtr);
+
+
+	/* Data in the setup buffer is being converted by the core to big
+	 * endian format. We have to take care of proper byte swapping when
+	 * reading the setup data values.
+	 *
+	 * Need to check if there is a smarter way to do this and take the
+	 * processor/memory-controller endianess into account?
+	 */
+	p = (u8 *) Data;
+
+	SetupDataPtr->bmRequestType	= p[0];
+	SetupDataPtr->bRequest		= p[1];
+	SetupDataPtr->wValue		= (p[3] << 8) | p[2];
+	SetupDataPtr->wIndex		= (p[5] << 8) | p[4];
+	SetupDataPtr->wLength		= (p[7] << 8) | p[6];
+
+	/* Before we leave we need to make sure that the endpoint setup bit has
+	 * cleared. It needs to be 0 before the endpoint can be re-primed.
+	 *
+	 * Note: According to the documentation this endpoint setup bit should
+	 * clear within 1-2us after it has been written above. This means that
+	 * we should never catch it being 1 here. However, we still need to
+	 * poll it to make sure. Just in case, we use a counter 'Timeout' so we
+	 * won't hang here if the bit is stuck for some reason.
+	 */
+	Timeout = XUSBPS_TIMEOUT_COUNTER;
+	while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_EPSTAT_OFFSET) &
+				(1 << EpNum)) && --Timeout) {
+		/* NOP */
+	}
+	if (0 == Timeout) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function initializes the endpoint pointer data structure.
+*
+* The function sets up the local data structure with the aligned addresses for
+* the Queue Head and Transfer Descriptors.
+*
+* @param	DevCfgPtr is pointer to the XUsbPs DEVICE configuration
+*		structure.
+*
+* @return	none
+*
+* @note
+* 		Endpoints of type XUSBPS_EP_TYPE_NONE are not used in the
+* 		system. Therefore no memory is reserved for them.
+*
+******************************************************************************/
+static void XUsbPs_EpListInit(XUsbPs_DeviceConfig *DevCfgPtr)
+{
+	int	EpNum;
+	u8	*p;
+
+	XUsbPs_Endpoint	*Ep;
+	XUsbPs_EpConfig	*EpCfg;
+
+	/* Set up the XUsbPs_Endpoint array. This array is used to define the
+	 * location of the Queue Head list and the Transfer Descriptors in the
+	 * block of DMA memory that has been passed into the driver.
+	 *
+	 * 'p' is used to set the pointers in the local data structure.
+	 * Initially 'p' is pointed to the beginning of the DMAable memory
+	 * block. As pointers are assigned, 'p' is incremented by the size of
+	 * the respective object.
+	 */
+	Ep	= DevCfgPtr->Ep;
+	EpCfg	= DevCfgPtr->EpCfg;
+
+	/* Start off with 'p' pointing to the (aligned) beginning of the DMA
+	 * buffer.
+	 */
+	p = (u8 *) DevCfgPtr->PhysAligned;
+
+
+	/* Initialize the Queue Head pointer list.
+	 *
+	 * Each endpoint has two Queue Heads. One for the OUT direction and one
+	 * for the IN direction. An OUT Queue Head is always followed by an IN
+	 * Queue Head.
+	 *
+	 * Queue Head alignment is XUSBPS_dQH_ALIGN.
+	 *
+	 * Note that we have to reserve space here for unused endpoints.
+	 */
+	for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+		/* OUT Queue Head */
+		Ep[EpNum].Out.dQH = (XUsbPs_dQH *) p;
+		p += XUSBPS_dQH_ALIGN;
+
+		/* IN Queue Head */
+		Ep[EpNum].In.dQH = (XUsbPs_dQH *) p;
+		p += XUSBPS_dQH_ALIGN;
+	}
+
+
+	/* 'p' now points to the first address after the Queue Head list. The
+	 * Transfer Descriptors start here.
+	 *
+	 * Each endpoint has a variable number of Transfer Descriptors
+	 * depending on user configuration.
+	 *
+	 * Transfer Descriptor alignment is XUSBPS_dTD_ALIGN.
+	 */
+	for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+		/* OUT Descriptors.
+		 */
+		if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) {
+			Ep[EpNum].Out.dTDs		= (XUsbPs_dTD *) p;
+			Ep[EpNum].Out.dTDCurr	= (XUsbPs_dTD *) p;
+			p += XUSBPS_dTD_ALIGN * EpCfg[EpNum].Out.NumBufs;
+		}
+
+		/* IN Descriptors.
+		 */
+		if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].In.Type) {
+			Ep[EpNum].In.dTDs		= (XUsbPs_dTD *) p;
+			Ep[EpNum].In.dTDHead	= (XUsbPs_dTD *) p;
+			Ep[EpNum].In.dTDTail	= (XUsbPs_dTD *) p;
+			p += XUSBPS_dTD_ALIGN * EpCfg[EpNum].In.NumBufs;
+		}
+	}
+
+
+	/* 'p' now points to the first address after the Transfer Descriptors.
+	 * The data buffers for the OUT Transfer Desciptors start here.
+	 *
+	 * Note that IN (TX) Transfer Descriptors are not assigned buffers at
+	 * this point. Buffers will be assigned when the user calls the send()
+	 * function.
+	 */
+	for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+
+		if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) {
+			/* If BufSize for this endpoint is set to 0 it means
+			 * that we do not need to attach a buffer to this
+			 * descriptor. We also initialize it's buffer pointer
+			 * to NULL.
+			 */
+			if (0 == EpCfg[EpNum].Out.BufSize) {
+				Ep[EpNum].Out.dTDBufs = NULL;
+				continue;
+			}
+
+			Ep[EpNum].Out.dTDBufs = p;
+			p += EpCfg[EpNum].Out.BufSize * EpCfg[EpNum].Out.NumBufs;
+		}
+	}
+
+
+	/* Initialize the endpoint event handlers to NULL.
+	 */
+	for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+		Ep[EpNum].Out.HandlerFunc = NULL;
+		Ep[EpNum].In.HandlerFunc  = NULL;
+	}
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function initializes the Queue Head List in memory.
+*
+* @param	DevCfgPtr is a pointer to the XUsbPs DEVICE configuration
+*		structure.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void XUsbPs_dQHInit(XUsbPs_DeviceConfig *DevCfgPtr)
+{
+	int	EpNum;
+
+	XUsbPs_Endpoint	*Ep;
+	XUsbPs_EpConfig	*EpCfg;
+
+	/* Setup pointers for simpler access. */
+	Ep	= DevCfgPtr->Ep;
+	EpCfg	= DevCfgPtr->EpCfg;
+
+
+	/* Go through the list of Queue Head entries and:
+	 *
+	 * - Set Transfer Descriptor addresses
+	 * - Set Maximum Packet Size
+	 * - Disable Zero Length Termination (ZLT) for non-isochronous transfers
+	 * - Enable Interrupt On Setup (IOS)
+	 *
+	 */
+	for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+
+		/* OUT Queue Heads.*/
+		if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) {
+			XUsbPs_WritedQH(Ep[EpNum].Out.dQH,
+					XUSBPS_dQHCPTR, Ep[EpNum].Out.dTDs);
+
+			/* For isochronous, ep max packet size translates to different
+			 * values in queue head than other types.
+			 * Also	enable ZLT for isochronous.
+			 */
+			if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].Out.Type) {
+				XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].Out.dQH,
+                        EpCfg[EpNum].Out.MaxPacketSize);
+				XUsbPs_dQHEnableZLT(Ep[EpNum].Out.dQH);
+			}else {
+				XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].Out.dQH,
+					    EpCfg[EpNum].Out.MaxPacketSize);
+				XUsbPs_dQHDisableZLT(Ep[EpNum].Out.dQH);
+			}
+
+			/* Only control OUT needs this */
+			if(XUSBPS_EP_TYPE_CONTROL == EpCfg[EpNum].Out.Type) {
+				XUsbPs_dQHSetIOS(Ep[EpNum].Out.dQH);
+			}
+
+			/* Set up the overlay next dTD pointer. */
+			XUsbPs_WritedQH(Ep[EpNum].Out.dQH,
+					XUSBPS_dQHdTDNLP, Ep[EpNum].Out.dTDs);
+
+			XUsbPs_dQHFlushCache(Ep[EpNum].Out.dQH);
+		}
+
+
+		/* IN Queue Heads. */
+		if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].In.Type) {
+			XUsbPs_WritedQH(Ep[EpNum].In.dQH,
+				  XUSBPS_dQHCPTR, Ep[EpNum].In.dTDs);
+
+
+			/* Isochronous ep packet size can be larger than 1024.*/
+			if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].In.Type) {
+				XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].In.dQH,
+						EpCfg[EpNum].In.MaxPacketSize);
+				XUsbPs_dQHEnableZLT(Ep[EpNum].In.dQH);
+			}else {
+				XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].In.dQH,
+					    EpCfg[EpNum].In.MaxPacketSize);
+				XUsbPs_dQHDisableZLT(Ep[EpNum].In.dQH);
+			}
+
+			XUsbPs_dQHFlushCache(Ep[EpNum].In.dQH);
+		}
+	}
+}
+
+
+/*****************************************************************************/
+/**
+ *
+ * This function initializes the Transfer Descriptors lists in memory.
+ *
+ * @param	DevCfgPtr is a pointer to the XUsbPs DEVICE configuration
+ *		structure.
+ *
+ * @return
+ *		- XST_SUCCESS: The operation completed successfully.
+ *		- XST_FAILURE: An error occured.
+ *
+ ******************************************************************************/
+static int XUsbPs_dTDInit(XUsbPs_DeviceConfig *DevCfgPtr)
+{
+	int	EpNum;
+
+	XUsbPs_Endpoint	*Ep;
+	XUsbPs_EpConfig	*EpCfg;
+
+	/* Setup pointers for simpler access. */
+	Ep	= DevCfgPtr->Ep;
+	EpCfg	= DevCfgPtr->EpCfg;
+
+
+	/* Walk through the list of endpoints and initialize their Transfer
+	 * Descriptors.
+	 */
+	for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+		int	Td;
+		int	NumdTD;
+
+		XUsbPs_EpOut	*Out = &Ep[EpNum].Out;
+		XUsbPs_EpIn	*In  = &Ep[EpNum].In;
+
+
+		/* OUT Descriptors
+		 * ===============
+		 *
+		 * + Set the next link pointer
+		 * + Set the interrupt complete and the active bit
+		 * + Attach the buffer to the dTD
+		 */
+		if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) {
+			NumdTD = EpCfg[EpNum].Out.NumBufs;
+		}
+		else {
+			NumdTD = 0;
+		}
+
+		for (Td = 0; Td < NumdTD; ++Td) {
+			int	Status;
+
+			int NextTd = (Td + 1) % NumdTD;
+
+			XUsbPs_dTDInvalidateCache(&Out->dTDs[Td]);
+
+			/* Set NEXT link pointer. */
+			XUsbPs_WritedTD(&Out->dTDs[Td], XUSBPS_dTDNLP,
+					  &Out->dTDs[NextTd]);
+
+			/* Set the OUT descriptor ACTIVE and enable the
+			 * interrupt on complete.
+			 */
+			XUsbPs_dTDSetActive(&Out->dTDs[Td]);
+			XUsbPs_dTDSetIOC(&Out->dTDs[Td]);
+
+
+			/* Set up the data buffer with the descriptor. If the
+			 * buffer pointer is NULL it means that we do not need
+			 * to attach a buffer to this descriptor.
+			 */
+			if (NULL == Out->dTDBufs) {
+				XUsbPs_dTDFlushCache(&Out->dTDs[Td]);
+				continue;
+			}
+
+			Status = XUsbPs_dTDAttachBuffer(
+					&Out->dTDs[Td],
+					Out->dTDBufs +
+						(Td * EpCfg[EpNum].Out.BufSize),
+					EpCfg[EpNum].Out.BufSize);
+			if (XST_SUCCESS != Status) {
+				return XST_FAILURE;
+			}
+
+			XUsbPs_dTDFlushCache(&Out->dTDs[Td]);
+		}
+
+
+		/* IN Descriptors
+		 * ==============
+		 *
+		 * + Set the next link pointer
+		 * + Set the Terminate bit to mark it available
+		 */
+		if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].In.Type) {
+			NumdTD = EpCfg[EpNum].In.NumBufs;
+		}
+		else {
+			NumdTD = 0;
+		}
+
+		for (Td = 0; Td < NumdTD; ++Td) {
+			int NextTd = (Td + 1) % NumdTD;
+
+			XUsbPs_dTDInvalidateCache(&In->dTDs[Td]);
+
+			/* Set NEXT link pointer. */
+			XUsbPs_WritedTD(In->dTDs[Td], XUSBPS_dTDNLP,
+					  In->dTDs[NextTd]);
+
+			/* Set the IN descriptor's TERMINATE bits. */
+			XUsbPs_dTDSetTerminate(In->dTDs[Td]);
+
+			XUsbPs_dTDFlushCache(&In->dTDs[Td]);
+		}
+	}
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+ *
+ * This function associates a buffer with a Transfer Descriptor. The function
+ * will take care of splitting the buffer into multiple 4kB aligned segments if
+ * the buffer happens to span one or more 4kB pages.
+ *
+ * @param	dTDIndex is a pointer to the Transfer Descriptor
+ * @param	BufferPtr is pointer to the buffer to link to the descriptor.
+ * @param	BufferLen is the length of the buffer.
+ *
+ * @return
+ *		- XST_SUCCESS: The operation completed successfully.
+ *		- XST_FAILURE: An error occured.
+ *		- XST_USB_BUF_TOO_BIG: The provided buffer is bigger than tha
+ *		maximum allowed buffer size (16k).
+ *
+ * @note
+ * 		Cache invalidation and flushing needs to be handler by the
+ * 		caller of this function.
+ *
+ ******************************************************************************/
+static int XUsbPs_dTDAttachBuffer(XUsbPs_dTD *dTDPtr,
+					const u8 *BufferPtr, u32 BufferLen)
+{
+	u32	BufAddr;
+	u32	BufEnd;
+	u32	PtrNum;
+
+	Xil_AssertNonvoid(dTDPtr    != NULL);
+
+	/* Check if the buffer is smaller than 16kB. */
+	if (BufferLen > XUSBPS_dTD_BUF_MAX_SIZE) {
+		return XST_USB_BUF_TOO_BIG;
+	}
+
+	/* Get a u32 of the buffer pointer to avoid casting in the following
+	 * logic operations.
+	 */
+	BufAddr = (u32) BufferPtr;
+
+
+	/* Set the buffer pointer 0. Buffer pointer 0 can point to any location
+	 * in memory. It does not need to be 4kB aligned. However, if the
+	 * provided buffer spans one or more 4kB boundaries, we need to set up
+	 * the subsequent buffer pointers which must be 4kB aligned.
+	 */
+	XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDBPTR(0), BufAddr);
+
+	/* Check if the buffer spans a 4kB boundary.
+	 *
+	 * Only do this check, if we are not sending a 0-length buffer.
+	 */
+	if (BufferLen > 0) {
+		BufEnd = BufAddr + BufferLen -1;
+		PtrNum = 1;
+
+		while ((BufAddr & 0xFFFFF000) != (BufEnd & 0xFFFFF000)) {
+			/* The buffer spans at least one boundary, let's set
+			 * the next buffer pointer and repeat the procedure
+			 * until the end of the buffer and the pointer written
+			 * are in the same 4kB page.
+			 */
+			BufAddr = (BufAddr + 0x1000) & 0xFFFFF000;
+			XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDBPTR(PtrNum),
+								BufAddr);
+			PtrNum++;
+		}
+	}
+
+	/* Set the length of the buffer. */
+	XUsbPs_dTDSetTransferLen(dTDPtr, BufferLen);
+
+
+	/* We remember the buffer pointer in the user data field (reserved
+	 * field in the dTD). This makes it easier to reset the buffer pointer
+	 * after a buffer has been received on the endpoint. The buffer pointer
+	 * needs to be reset because the DMA engine modifies the buffer pointer
+	 * while receiving.
+	 */
+	XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDUSERDATA, BufferPtr);
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+ * This function set the Max PacketLen for the queue head for isochronous EP.
+ *
+ * If the max packet length is greater than XUSBPS_MAX_PACKET_SIZE, then
+ * Mult bits are set to reflect that.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ * @param	Len is the Length to be set.
+ *
+ ******************************************************************************/
+static void XUsbPs_dQHSetMaxPacketLenISO(XUsbPs_dQH *dQHPtr, u32 Len)
+{
+	u32 Mult = (Len & ENDPOINT_MAXP_MULT_MASK) >> ENDPOINT_MAXP_MULT_SHIFT;
+	u32 MaxPktSize = (Mult > 1) ? ENDPOINT_MAXP_LENGTH : Len;
+
+	if (MaxPktSize > XUSBPS_MAX_PACKET_SIZE) {
+		return;
+	}
+
+	if (Mult > 3) {
+		return;
+	}
+
+	/* Set Max packet size */
+	XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG,
+		(XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) &
+			~XUSBPS_dQHCFG_MPL_MASK) |
+			(MaxPktSize << XUSBPS_dQHCFG_MPL_SHIFT));
+
+	/* Set Mult to tell hardware how many transactions in each microframe */
+	XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG,
+		(XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) &
+			~XUSBPS_dQHCFG_MULT_MASK) |
+			(Mult << XUSBPS_dQHCFG_MULT_SHIFT));
+
+}
+
+/*****************************************************************************/
+/**
+* This function reconfigures one Ep corresponding to host's request of setting
+* alternate interface. The endpoint has been disabled before this call.
+*
+* Both QH and dTDs are updated for the new configuration.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	CfgPtr
+* 		Pointer to the updated XUsbPs DEVICE configuration structure.
+*
+* @param	EpNum
+*		The endpoint to be reconfigured.
+*
+* @param NewDirection
+*		The new transfer direction the endpoint.
+*
+* @param DirectionChanged
+*		A boolean value indicate whether the transfer direction has changed.
+*
+* @return
+*	XST_SUCCESS upon success, XST_FAILURE otherwise.
+*
+******************************************************************************/
+int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr,
+				int EpNum, unsigned short NewDirection,
+				int DirectionChanged) {
+
+	int Status = XST_SUCCESS;
+	XUsbPs_Endpoint *Ep;
+	XUsbPs_EpConfig *EpCfg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(CfgPtr      != NULL);
+
+	Ep = CfgPtr->Ep;
+	EpCfg = CfgPtr->EpCfg;
+
+	/* If transfer direction changes, dTDs has to be reset
+	 * Number of buffers are preset and should not to be changed.
+	 */
+	if(DirectionChanged) {
+		if(NewDirection == XUSBPS_EP_DIRECTION_OUT) {
+			u8 *p;
+
+			/* Swap the pointer to the dTDs.
+			 */
+			Ep[EpNum].Out.dTDs = Ep[EpNum].In.dTDs;
+			p = (u8 *)(Ep[EpNum].Out.dTDs + XUSBPS_dTD_ALIGN * EpCfg[EpNum].Out.NumBufs);
+
+			/* Set the OUT buffer if buffer size is not zero
+			 */
+			if(EpCfg[EpNum].Out.BufSize > 0) {
+				Ep[EpNum].Out.dTDBufs = p;
+			}
+		} else if(NewDirection == XUSBPS_EP_DIRECTION_IN) {
+			Ep[EpNum].In.dTDs = Ep[EpNum].Out.dTDs;
+		}
+	}
+
+	/* Reset dTD progress tracking pointers
+	 */
+	if(NewDirection == XUSBPS_EP_DIRECTION_IN) {
+		Ep[EpNum].In.dTDHead = Ep[EpNum].In.dTDTail = Ep[EpNum].In.dTDs;
+	} else if(NewDirection == XUSBPS_EP_DIRECTION_OUT) {
+		Ep[EpNum].Out.dTDCurr = Ep[EpNum].Out.dTDs;
+	}
+
+	/* Reinitialize information in QH
+	 */
+	XUsbPs_dQHReinitEp(CfgPtr, EpNum, NewDirection);
+
+	/* Reinitialize the dTD linked list, and flush the cache
+	 */
+	Status = XUsbPs_dTDReinitEp(CfgPtr, EpNum, NewDirection);
+	if(Status != XST_SUCCESS) {
+		return Status;
+	}
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+ * This function re-initializes the Queue Head List in memory.
+ * The endpoint 1 has been disabled before this call.
+ *
+ * @param	DevCfgPtr
+ * 		Pointer to the updated XUsbPs DEVICE configuration structure.
+ *
+ * @param	EpNum
+ *		The endpoint to be reconfigured.
+ *
+ * @param	NewDirection
+ *		The new transfer direction of endpoint 1
+ *
+ * @return	none
+ *
+ ******************************************************************************/
+static void XUsbPs_dQHReinitEp(XUsbPs_DeviceConfig *DevCfgPtr,
+int EpNum, unsigned short NewDirection)
+{
+	XUsbPs_Endpoint	*Ep;
+	XUsbPs_EpConfig	*EpCfg;
+
+	/* Setup pointers for simpler access.
+	 */
+	Ep	= DevCfgPtr->Ep;
+	EpCfg	= DevCfgPtr->EpCfg;
+
+
+	/* Go through the list of Queue Head entries and:
+	 *
+	 * - Set Transfer Descriptor addresses
+	 * - Set Maximum Packet Size
+	 * - Disable Zero Length Termination (ZLT) for non-isochronous transfers
+	 * - Enable Interrupt On Setup (IOS)
+	 *
+	 */
+	if(NewDirection == XUSBPS_EP_DIRECTION_OUT) {
+		/* OUT Queue Heads.
+		 */
+		XUsbPs_WritedQH(Ep[EpNum].Out.dQH,
+			XUSBPS_dQHCPTR, Ep[EpNum].Out.dTDs);
+
+		/* For isochronous, ep max packet size translates to different
+		 * values in queue head than other types.
+		 * Also	enable ZLT for isochronous.
+		 */
+		if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].Out.Type) {
+			XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].Out.dQH,
+   					EpCfg[EpNum].Out.MaxPacketSize);
+			XUsbPs_dQHEnableZLT(Ep[EpNum].Out.dQH);
+		}else {
+			XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].Out.dQH,
+				    EpCfg[EpNum].Out.MaxPacketSize);
+			XUsbPs_dQHDisableZLT(Ep[EpNum].Out.dQH);
+		}
+
+		XUsbPs_dQHSetIOS(Ep[EpNum].Out.dQH);
+
+		/* Set up the overlay next dTD pointer.
+		 */
+		XUsbPs_WritedQH(Ep[EpNum].Out.dQH,
+				XUSBPS_dQHdTDNLP, Ep[EpNum].Out.dTDs);
+
+		XUsbPs_dQHFlushCache(Ep[EpNum].Out.dQH);
+
+	} else if(NewDirection == XUSBPS_EP_DIRECTION_IN) {
+
+		/* IN Queue Heads.
+		 */
+		XUsbPs_WritedQH(Ep[EpNum].In.dQH,
+			  XUSBPS_dQHCPTR, Ep[EpNum].In.dTDs);
+
+		/* Isochronous ep packet size can be larger than 1024. */
+		if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].In.Type) {
+			XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].In.dQH,
+   				EpCfg[EpNum].In.MaxPacketSize);
+			XUsbPs_dQHEnableZLT(Ep[EpNum].In.dQH);
+		}else {
+			XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].In.dQH,
+			    EpCfg[EpNum].In.MaxPacketSize);
+			XUsbPs_dQHDisableZLT(Ep[EpNum].In.dQH);
+		}
+
+		XUsbPs_dQHSetIOS(Ep[EpNum].In.dQH);
+
+		XUsbPs_dQHFlushCache(Ep[EpNum].In.dQH);
+	}
+
+}
+
+/*****************************************************************************/
+/**
+ *
+ * This function re-initializes the Transfer Descriptors lists in memory.
+ * The endpoint has been disabled before the call. The transfer descriptors
+ * list pointer has been initialized too.
+ *
+ * @param	DevCfgPtr
+ * 		Pointer to the XUsbPs DEVICE configuration structure.
+ *
+ * @param	EpNum
+ *		The endpoint to be reconfigured.
+ *
+ * @param	NewDirection
+ *		The new transfer direction of endpoint 1
+ *
+ * @return
+ *		- XST_SUCCESS: The operation completed successfully.
+ *		- XST_FAILURE: An error occured.
+ *
+ ******************************************************************************/
+static int XUsbPs_dTDReinitEp(XUsbPs_DeviceConfig *DevCfgPtr,
+int EpNum, unsigned short NewDirection)
+{
+	XUsbPs_Endpoint	*Ep;
+	XUsbPs_EpConfig	*EpCfg;
+	int	Td;
+	int	NumdTD;
+
+
+	/* Setup pointers for simpler access.
+	 */
+	Ep	= DevCfgPtr->Ep;
+	EpCfg	= DevCfgPtr->EpCfg;
+
+
+	if(NewDirection == XUSBPS_EP_DIRECTION_OUT) {
+		XUsbPs_EpOut	*Out = &Ep[EpNum].Out;
+
+		/* OUT Descriptors
+		 * ===============
+		 *
+		 * + Set the next link pointer
+		 * + Set the interrupt complete and the active bit
+		 * + Attach the buffer to the dTD
+		 */
+		NumdTD = EpCfg[EpNum].Out.NumBufs;
+
+		for (Td = 0; Td < NumdTD; ++Td) {
+			int	Status;
+
+			int NextTd = (Td + 1) % NumdTD;
+
+			XUsbPs_dTDInvalidateCache(&Out->dTDs[Td]);
+
+			/* Set NEXT link pointer.
+			 */
+			XUsbPs_WritedTD(&Out->dTDs[Td], XUSBPS_dTDNLP,
+					  &Out->dTDs[NextTd]);
+
+			/* Set the OUT descriptor ACTIVE and enable the
+			 * interrupt on complete.
+			 */
+			XUsbPs_dTDSetActive(&Out->dTDs[Td]);
+			XUsbPs_dTDSetIOC(&Out->dTDs[Td]);
+
+			/* Set up the data buffer with the descriptor. If the
+			 * buffer pointer is NULL it means that we do not need
+			 * to attach a buffer to this descriptor.
+			 */
+			if (Out->dTDBufs != NULL) {
+
+				Status = XUsbPs_dTDAttachBuffer(
+						&Out->dTDs[Td],
+						Out->dTDBufs +
+							(Td * EpCfg[EpNum].Out.BufSize),
+						EpCfg[EpNum].Out.BufSize);
+				if (Status != XST_SUCCESS) {
+					return XST_FAILURE;
+				}
+			}
+			XUsbPs_dTDFlushCache(&Out->dTDs[Td]);
+		}
+	} else if(NewDirection == XUSBPS_EP_DIRECTION_IN) {
+		XUsbPs_EpIn	*In  = &Ep[EpNum].In;
+
+		/* IN Descriptors
+		 * ==============
+		 *
+		 * + Set the next link pointer
+		 * + Set the Terminate bit to mark it available
+		 */
+		NumdTD = EpCfg[EpNum].In.NumBufs;
+
+		for (Td = 0; Td < NumdTD; ++Td) {
+			int NextTd = (Td + 1) % NumdTD;
+
+			XUsbPs_dTDInvalidateCache(&In->dTDs[Td]);
+
+			/* Set NEXT link pointer.
+			 */
+			XUsbPs_WritedTD(&In->dTDs[Td], XUSBPS_dTDNLP,
+					  &In->dTDs[NextTd]);
+
+			/* Set the IN descriptor's TERMINATE bits.
+			 */
+			XUsbPs_dTDSetTerminate(&In->dTDs[Td]);
+
+			XUsbPs_dTDFlushCache(&In->dTDs[Td]);
+		}
+	}
+
+	return XST_SUCCESS;
+}
+
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.h
new file mode 100644
index 0000000000000000000000000000000000000000..b8b9ad685823a1e0da09516bd39632b198ec74f3
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.h
@@ -0,0 +1,515 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal 
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xusbps_endpoint.h
+* @addtogroup usbps_v2_2
+* @{
+ *
+ * This is an internal file containung the definitions for endpoints. It is
+ * included by the xusbps_endpoint.c which is implementing the endpoint
+ * functions and by xusbps_intr.c.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- --------------------------------------------------------
+ * 1.00a wgr  10/10/10 First release
+ * </pre>
+ *
+ ******************************************************************************/
+#ifndef XUSBPS_ENDPOINT_H
+#define XUSBPS_ENDPOINT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xusbps.h"
+#include "xil_types.h"
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+
+/**
+ * Endpoint Device Transfer Descriptor
+ *
+ * The dTD describes to the device controller the location and quantity of data
+ * to be sent/received for given transfer. The driver does not attempt to
+ * modify any field in an active dTD except the Next Link Pointer.
+ */
+#define XUSBPS_dTDNLP		0x00 /**< Pointer to the next descriptor */
+#define XUSBPS_dTDTOKEN	0x04 /**< Descriptor Token */
+#define XUSBPS_dTDBPTR0	0x08 /**< Buffer Pointer 0 */
+#define XUSBPS_dTDBPTR1	0x0C /**< Buffer Pointer 1 */
+#define XUSBPS_dTDBPTR2	0x10 /**< Buffer Pointer 2 */
+#define XUSBPS_dTDBPTR3	0x14 /**< Buffer Pointer 3 */
+#define XUSBPS_dTDBPTR4	0x18 /**< Buffer Pointer 4 */
+#define XUSBPS_dTDBPTR(n)	(XUSBPS_dTDBPTR0 + (n) * 0x04)
+#define XUSBPS_dTDRSRVD	0x1C /**< Reserved field */
+
+/* We use the reserved field in the dTD to store user data. */
+#define XUSBPS_dTDUSERDATA	XUSBPS_dTDRSRVD /**< Reserved field */
+
+
+/** @name dTD Next Link Pointer (dTDNLP) bit positions.
+ *  @{
+ */
+#define XUSBPS_dTDNLP_T_MASK		0x00000001
+				/**< USB dTD Next Link Pointer Terminate Bit */
+#define XUSBPS_dTDNLP_ADDR_MASK	0xFFFFFFE0
+				/**< USB dTD Next Link Pointer Address [31:5] */
+/* @} */
+
+
+/** @name dTD Token (dTDTOKEN) bit positions.
+ *  @{
+ */
+#define XUSBPS_dTDTOKEN_XERR_MASK	0x00000008 /**< dTD Transaction Error */
+#define XUSBPS_dTDTOKEN_BUFERR_MASK	0x00000020 /**< dTD Data Buffer Error */
+#define XUSBPS_dTDTOKEN_HALT_MASK	0x00000040 /**< dTD Halted Flag */
+#define XUSBPS_dTDTOKEN_ACTIVE_MASK	0x00000080 /**< dTD Active Bit */
+#define XUSBPS_dTDTOKEN_MULTO_MASK	0x00000C00 /**< Multiplier Override Field [1:0] */
+#define XUSBPS_dTDTOKEN_IOC_MASK	0x00008000 /**< Interrupt on Complete Bit */
+#define XUSBPS_dTDTOKEN_LEN_MASK	0x7FFF0000 /**< Transfer Length Field */
+/* @} */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ *
+ * IMPORTANT NOTE:
+ * ===============
+ *
+ * Many of the following macros modify Device Queue Head (dQH) data structures
+ * and Device Transfer Descriptor (dTD) data structures. Those structures can
+ * potentially reside in CACHED memory. Therefore, it's the callers
+ * responsibility to ensure cache coherency by using provided
+ *
+ * 	XUsbPs_dQHInvalidateCache()
+ * 	XUsbPs_dQHFlushCache()
+ * 	XUsbPs_dTDInvalidateCache()
+ * 	XUsbPs_dTDFlushCache()
+ *
+ * function calls.
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDInvalidateCache(dTDPtr) \
+		Xil_DCacheInvalidateRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
+
+#define XUsbPs_dTDFlushCache(dTDPtr) \
+		Xil_DCacheFlushRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
+
+#define XUsbPs_dQHInvalidateCache(dQHPtr) \
+		Xil_DCacheInvalidateRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
+
+#define XUsbPs_dQHFlushCache(dQHPtr) \
+		Xil_DCacheFlushRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Transfer Length for the given Transfer Descriptor.
+ *
+ * @param	dTDPtr is pointer to the dTD element.
+ * @param	Len is the length to be set. Range: 0..16384
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetTransferLen(dTDPtr, Len)				\
+		XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, 		\
+			(XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) &	\
+				~XUSBPS_dTDTOKEN_LEN_MASK) | ((Len) << 16))
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro gets the Next Link pointer of the given Transfer Descriptor.
+ *
+ * @param	dTDPtr is pointer to the dTD element.
+ *
+ * @return 	TransferLength field of the descriptor.
+ *
+ * @note	C-style signature:
+ *		u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDGetNLP(dTDPtr)					\
+		(XUsbPs_dTD *) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP)\
+					& XUSBPS_dTDNLP_ADDR_MASK))
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Next Link pointer of the given Transfer Descriptor.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ * @param	NLP is the Next Link Pointer
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetNLP(dTDPtr, NLP)					\
+		XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, 		\
+			(XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) &	\
+				~XUSBPS_dTDNLP_ADDR_MASK) |		\
+					((NLP) & XUSBPS_dTDNLP_ADDR_MASK))
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro gets the Transfer Length for the given Transfer Descriptor.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ *
+ * @return 	TransferLength field of the descriptor.
+ *
+ * @note	C-style signature:
+ *		u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDGetTransferLen(dTDPtr)				\
+		(u32) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) 	\
+				& XUSBPS_dTDTOKEN_LEN_MASK) >> 16)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Interrupt On Complete (IOC) bit for the given Transfer
+ * Descriptor.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dTDSetIOC(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetIOC(dTDPtr)					\
+		XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, 		\
+			XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) |	\
+						XUSBPS_dTDTOKEN_IOC_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Terminate bit for the given Transfer Descriptor.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dTDSetTerminate(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetTerminate(dTDPtr)				\
+		XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, 		\
+			XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) |	\
+						XUSBPS_dTDNLP_T_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro clears the Terminate bit for the given Transfer Descriptor.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dTDClrTerminate(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDClrTerminate(dTDPtr)				\
+		XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, 		\
+			XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) &	\
+						~XUSBPS_dTDNLP_T_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro checks if the given descriptor is active.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ *
+ * @return
+ * 		- TRUE: The buffer is active.
+ * 		- FALSE: The buffer is not active.
+ *
+ * @note	C-style signature:
+ *		int XUsbPs_dTDIsActive(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDIsActive(dTDPtr)					\
+		((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) &		\
+				XUSBPS_dTDTOKEN_ACTIVE_MASK) ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Active bit for the given Transfer Descriptor.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dTDSetActive(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetActive(dTDPtr)					\
+		XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, 		\
+			XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) |	\
+						XUSBPS_dTDTOKEN_ACTIVE_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro reads the content of a field in a Transfer Descriptor.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ * @param	Id is the field ID inside the dTD element to read.
+ *
+ * @note	C-style signature:
+ *		u32 XUsbPs_ReaddTD(u32 dTDPtr, u32 Id)
+ *
+ ******************************************************************************/
+#define XUsbPs_ReaddTD(dTDPtr, Id)	(*(u32 *)((u32)(dTDPtr) + (u32)(Id)))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro writes a value to a field in a Transfer Descriptor.
+ *
+ * @param	dTDPtr is pointer to the dTD element.
+ * @param	Id is the field ID inside the dTD element to read.
+ * @param	Val is the value to write to the field.
+ *
+ * @note	C-style signature:
+ *		u32 XUsbPs_WritedTD(u32 dTDPtr, u32 Id, u32 Val)
+ *
+ ******************************************************************************/
+#define XUsbPs_WritedTD(dTDPtr, Id, Val)	\
+			(*(u32 *) ((u32)(dTDPtr) + (u32)(Id)) = (u32)(Val))
+
+
+/******************************************************************************/
+/**
+ * Endpoint Device Queue Head
+ *
+ * Device queue heads are arranged in an array in a continuous area of memory
+ * pointed to by the ENDPOINTLISTADDR pointer. The device controller will index
+ * into this array based upon the endpoint number received from the USB bus.
+ * All information necessary to respond to transactions for all primed
+ * transfers is contained in this list so the Device Controller can readily
+ * respond to incoming requests without having to traverse a linked list.
+ *
+ * The device Endpoint Queue Head (dQH) is where all transfers are managed. The
+ * dQH is a 48-byte data structure, but must be aligned on a 64-byte boundary.
+ * During priming of an endpoint, the dTD (device transfer descriptor) is
+ * copied into the overlay area of the dQH, which starts at the nextTD pointer
+ * DWord and continues through the end of the buffer pointers DWords. After a
+ * transfer is complete, the dTD status DWord is updated in the dTD pointed to
+ * by the currentTD pointer. While a packet is in progress, the overlay area of
+ * the dQH is used as a staging area for the dTD so that the Device Controller
+ * can access needed information with little minimal latency.
+ *
+ * @note
+ *    Software must ensure that no interface data structure reachable by the
+ *    Device Controller spans a 4K-page boundary.  The first element of the
+ *    Endpoint Queue Head List must be aligned on a 4K boundary.
+ */
+#define XUSBPS_dQHCFG			0x00 /**< dQH Configuration */
+#define XUSBPS_dQHCPTR			0x04 /**< dQH Current dTD Pointer */
+#define XUSBPS_dQHdTDNLP		0x08 /**< dTD Next Link Ptr in dQH
+					       overlay */
+#define XUSBPS_dQHdTDTOKEN		0x0C /**< dTD Token in dQH overlay */
+#define XUSBPS_dQHSUB0			0x28 /**< USB dQH Setup Buffer 0 */
+#define XUSBPS_dQHSUB1			0x2C /**< USB dQH Setup Buffer 1 */
+
+
+/** @name dQH Configuration (dQHCFG) bit positions.
+ *  @{
+ */
+#define XUSBPS_dQHCFG_IOS_MASK		0x00008000
+					/**< USB dQH Interrupt on Setup Bit */
+#define XUSBPS_dQHCFG_MPL_MASK		0x07FF0000
+					/**< USB dQH Maximum Packet Length
+					 * Field [10:0] */
+#define XUSBPS_dQHCFG_MPL_SHIFT    16
+#define XUSBPS_dQHCFG_ZLT_MASK		0x20000000
+					/**< USB dQH Zero Length Termination
+					 * Select Bit */
+#define XUSBPS_dQHCFG_MULT_MASK		0xC0000000
+					/* USB dQH Number of Transactions Field
+					 * [1:0] */
+#define XUSBPS_dQHCFG_MULT_SHIFT       30
+/* @} */
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Maximum Packet Length field of the give Queue Head.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ * @param	Len is the length to be set.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dQHSetMaxPacketLen(u32 dQHPtr, u32 Len)
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHSetMaxPacketLen(dQHPtr, Len)			\
+		XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, 		\
+			(XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) &	\
+				~XUSBPS_dQHCFG_MPL_MASK) | ((Len) << 16))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Interrupt On Setup (IOS) bit for an endpoint.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dQHSetIOS(u32 dQHPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHSetIOS(dQHPtr)					\
+		XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, 		\
+			XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) |	\
+						XUSBPS_dQHCFG_IOS_MASK)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro clears the Interrupt On Setup (IOS) bit for an endpoint.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dQHClrIOS(u32 dQHPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHClrIOS(dQHPtr)					\
+		XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, 		\
+			XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) &	\
+						~XUSBPS_dQHCFG_IOS_MASK)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro enables Zero Length Termination for the endpoint.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dQHEnableZLT(u32 dQHPtr)
+ *
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHEnableZLT(dQHPtr)					\
+		XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, 		\
+			XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) &	\
+						~XUSBPS_dQHCFG_ZLT_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro disables Zero Length Termination for the endpoint.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dQHDisableZLT(u32 dQHPtr)
+ *
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHDisableZLT(dQHPtr)					\
+		XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, 		\
+			XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) |	\
+						XUSBPS_dQHCFG_ZLT_MASK)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro reads the content of a field in a Queue Head.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ * @param	Id is the Field ID inside the dQH element to read.
+ *
+ * @note	C-style signature:
+ *		u32 XUsbPs_ReaddQH(u32 dQHPtr, u32 Id)
+ *
+ ******************************************************************************/
+#define XUsbPs_ReaddQH(dQHPtr, Id)	(*(u32 *)((u32)(dQHPtr) + (u32) (Id)))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro writes a value to a field in a Queue Head.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ * @param	Id is the Field ID inside the dQH element to read.
+ * @param	Val is the Value to write to the field.
+ *
+ * @note	C-style signature:
+ *		u32 XUsbPs_WritedQH(u32 dQHPtr, u32 Id, u32 Val)
+ *
+ ******************************************************************************/
+#define XUsbPs_WritedQH(dQHPtr, Id, Val)	\
+			(*(u32 *) ((u32)(dQHPtr) + (u32)(Id)) = (u32)(Val))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XUSBPS_ENDPOINT_H */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..79b2959ca8dc9c528ae5519204bd8efcea433398
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xusbps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XUsbPs_Config XUsbPs_ConfigTable[XPAR_XUSBPS_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_USB_0_DEVICE_ID,
+		XPAR_PS7_USB_0_BASEADDR
+	}
+};
+
+
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.c
new file mode 100644
index 0000000000000000000000000000000000000000..105ad9321706fd69b5771d3e5132de85596abcd9
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.c
@@ -0,0 +1,122 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal 
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+ *
+ * @file xusbps_hw.c
+* @addtogroup usbps_v2_2
+* @{
+ *
+ * The implementation of the XUsbPs interface reset functionality
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.05a kpc  10/10/10 first version
+ * </pre>
+ *
+ *****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xusbps.h"
+#include "xparameters.h"
+
+
+/************************** Constant Definitions ****************************/
+#define XUSBPS_RESET_TIMEOUT 0xFFFFF
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+
+/************************** Function Prototypes *****************************/
+
+
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given usbps interface by 
+* configuring the appropriate control bits in the usbps specifc registers.
+* the usbps reset sequence involves the below steps
+* 	Disbale the interrupts
+*	Clear the status registers
+*	Apply the reset command and wait for reset complete status
+*	Update the relevant control registers with reset values
+* @param   BaseAddress of the interface
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XUsbPs_ResetHw(u32 BaseAddress)
+{
+	u32 RegVal;
+	u32 Timeout = 0;
+	
+	/* Host and device mode */
+	/* Disable the interrupts */
+	XUsbPs_WriteReg(BaseAddress,XUSBPS_IER_OFFSET,0x0);
+	/* Clear the interuupt status */
+	RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_ISR_OFFSET);
+	XUsbPs_WriteReg(BaseAddress,XUSBPS_ISR_OFFSET,RegVal);
+
+	/* Perform the reset operation using USB CMD register */	
+	RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_CMD_OFFSET);
+	RegVal = RegVal | XUSBPS_CMD_RST_MASK;
+	XUsbPs_WriteReg(BaseAddress,XUSBPS_CMD_OFFSET,RegVal);
+	RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_CMD_OFFSET);
+	/* Wait till the reset operation returns success */
+	/*
+	* FIX ME: right now no indication to the caller or user about
+	* timeout overflow
+	*/
+	while ((RegVal & XUSBPS_CMD_RST_MASK) && (Timeout < XUSBPS_RESET_TIMEOUT))
+	{
+		RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_CMD_OFFSET);	
+		Timeout++;
+	}
+	/* Update periodic list base address register with reset value */		
+	XUsbPs_WriteReg(BaseAddress,XUSBPS_LISTBASE_OFFSET,0x0);	
+	/* Update async/endpoint list base address register with reset value */		
+	XUsbPs_WriteReg(BaseAddress,XUSBPS_ASYNCLISTADDR_OFFSET,0x0);		
+	
+}
+
+
+
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..792fbdde5ba93c34498461a15c3858bb9cc71098
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.h
@@ -0,0 +1,526 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal 
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xusbps_hw.h
+* @addtogroup usbps_v2_2
+* @{
+ *
+ * This header file contains identifiers and low-level driver functions (or
+ * macros) that can be used to access the device. High-level driver functions
+ * are defined in xusbps.h.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a wgr  10/10/10 First release
+ * 1.04a nm   10/23/12 Fixed CR# 679106.
+ * 1.05a kpc  07/03/13 Added XUsbPs_ResetHw function prototype
+ * 2.00a kpc  04/03/14 Fixed CR#777764. Corrected max endpoint vale and masks 
+ * </pre>
+ *
+ ******************************************************************************/
+#ifndef XUSBPS_HW_H
+#define XUSBPS_HW_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+
+#define XUSBPS_REG_SPACING		4
+
+/** @name Timer 0 Register offsets
+ *
+ * @{
+ */
+#define XUSBPS_TIMER0_LD_OFFSET	0x00000080
+#define XUSBPS_TIMER0_CTL_OFFSET	0x00000084
+/* @} */
+
+/** @name Timer Control Register bit mask
+ *
+ * @{
+ */
+#define XUSBPS_TIMER_RUN_MASK		0x80000000
+#define XUSBPS_TIMER_STOP_MASK		0x80000000
+#define XUSBPS_TIMER_RESET_MASK	0x40000000
+#define XUSBPS_TIMER_REPEAT_MASK	0x01000000
+/* @} */
+
+/** @name Timer Control Register bit mask
+ *
+ * @{
+ */
+#define XUSBPS_TIMER_COUNTER_MASK	0x00FFFFFF
+/* @} */
+
+/** @name Device Hardware Parameters
+ *
+ * @{
+ */
+#define XUSBPS_HWDEVICE_OFFSET		0x0000000C
+
+#define XUSBPS_EP_NUM_MASK		0x3E
+#define XUSBPS_EP_NUM_SHIFT		1
+/* @} */
+
+/** @name Capability Regsiter offsets
+ */
+#define XUSBPS_HCSPARAMS_OFFSET		0x00000104
+
+/** @name Operational Register offsets.
+ * Register comments are tagged with "H:" and "D:" for Host and Device modes,
+ * respectively.
+ * Tags are only present for registers that have a different meaning DEVICE and
+ * HOST modes. Most registers are only valid for either DEVICE or HOST mode.
+ * Those registers don't have tags.
+ * @{
+ */
+#define XUSBPS_CMD_OFFSET		0x00000140 /**< Configuration */
+#define XUSBPS_ISR_OFFSET		0x00000144 /**< Interrupt Status */
+#define XUSBPS_IER_OFFSET		0x00000148 /**< Interrupt Enable */
+#define XUSBPS_FRAME_OFFSET		0x0000014C /**< USB Frame Index */
+#define XUSBPS_LISTBASE_OFFSET		0x00000154 /**< H: Periodic List Base Address */
+#define XUSBPS_DEVICEADDR_OFFSET	0x00000154 /**< D: Device Address */
+#define XUSBPS_ASYNCLISTADDR_OFFSET	0x00000158 /**< H: Async List Address */
+#define XUSBPS_EPLISTADDR_OFFSET	0x00000158 /**< D: Endpoint List Addr */
+#define XUSBPS_TTCTRL_OFFSET		0x0000015C /**< TT Control */
+#define XUSBPS_BURSTSIZE_OFFSET	0x00000160 /**< Burst Size */
+#define XUSBPS_TXFILL_OFFSET		0x00000164 /**< Tx Fill Tuning */
+#define XUSBPS_ULPIVIEW_OFFSET		0x00000170 /**< ULPI Viewport */
+#define XUSBPS_EPNAKISR_OFFSET		0x00000178 /**< Endpoint NAK IRQ Status */
+#define XUSBPS_EPNAKIER_OFFSET		0x0000017C /**< Endpoint NAK IRQ Enable */
+#define XUSBPS_PORTSCR1_OFFSET		0x00000184 /**< Port Control/Status 1 */
+
+/* NOTE: The Port Control / Status Register index is 1-based. */
+#define XUSBPS_PORTSCRn_OFFSET(n)	\
+		(XUSBPS_PORTSCR1_OFFSET + (((n)-1) * XUSBPS_REG_SPACING))
+
+
+#define XUSBPS_OTGCSR_OFFSET	0x000001A4 /**< OTG Status and Control */
+#define XUSBPS_MODE_OFFSET	0x000001A8 /**< USB Mode */
+#define XUSBPS_EPSTAT_OFFSET	0x000001AC /**< Endpoint Setup Status */
+#define XUSBPS_EPPRIME_OFFSET	0x000001B0 /**< Endpoint Prime */
+#define XUSBPS_EPFLUSH_OFFSET	0x000001B4 /**< Endpoint Flush */
+#define XUSBPS_EPRDY_OFFSET	0x000001B8 /**< Endpoint Ready */
+#define XUSBPS_EPCOMPL_OFFSET	0x000001BC /**< Endpoint Complete */
+#define XUSBPS_EPCR0_OFFSET	0x000001C0 /**< Endpoint Control 0 */
+#define XUSBPS_EPCR1_OFFSET	0x000001C4 /**< Endpoint Control 1 */
+#define XUSBPS_EPCR2_OFFSET	0x000001C8 /**< Endpoint Control 2 */
+#define XUSBPS_EPCR3_OFFSET	0x000001CC /**< Endpoint Control 3 */
+#define XUSBPS_EPCR4_OFFSET	0x000001D0 /**< Endpoint Control 4 */
+
+#define XUSBPS_MAX_ENDPOINTS	12	   /**< Number of supported Endpoints in
+					     *  this core. */
+#define XUSBPS_EP_OUT_MASK	0x00000FFF /**< OUR (RX) endpoint mask */
+#define XUSBPS_EP_IN_MASK	0x0FFF0000 /**< IN (TX) endpoint mask */
+#define XUSBPS_EP_ALL_MASK	0x0FFF0FFF /**< Mask used for endpoint control
+					     *  registers */
+#define XUSBPS_EPCRn_OFFSET(n)	\
+		(XUSBPS_EPCR0_OFFSET + ((n) * XUSBPS_REG_SPACING))
+
+#define  XUSBPS_EPFLUSH_RX_SHIFT   0
+#define  XUSBPS_EPFLUSH_TX_SHIFT  16
+
+/* @} */
+
+
+
+/** @name Endpoint Control Register (EPCR) bit positions.
+ *  @{
+ */
+
+/* Definitions for TX Endpoint bits */
+#define XUSBPS_EPCR_TXT_CONTROL_MASK	0x00000000 /**< Control Endpoint - TX */
+#define XUSBPS_EPCR_TXT_ISO_MASK	0x00040000 /**< Isochronous. Endpoint */
+#define XUSBPS_EPCR_TXT_BULK_MASK	0x00080000 /**< Bulk Endpoint - TX */
+#define XUSBPS_EPCR_TXT_INTR_MASK	0x000C0000 /**< Interrupt Endpoint */
+#define XUSBPS_EPCR_TXS_MASK		0x00010000 /**< Stall TX endpoint */
+#define XUSBPS_EPCR_TXE_MASK		0x00800000 /**< Transmit enable  - TX */
+#define XUSBPS_EPCR_TXR_MASK		0x00400000 /**< Data Toggle Reset Bit */
+
+
+/* Definitions for RX Endpoint bits */
+#define XUSBPS_EPCR_RXT_CONTROL_MASK	0x00000000 /**< Control Endpoint - RX */
+#define XUSBPS_EPCR_RXT_ISO_MASK	0x00000004 /**< Isochronous Endpoint */
+#define XUSBPS_EPCR_RXT_BULK_MASK	0x00000008 /**< Bulk Endpoint - RX */
+#define XUSBPS_EPCR_RXT_INTR_MASK	0x0000000C /**< Interrupt Endpoint */
+#define XUSBPS_EPCR_RXS_MASK		0x00000001 /**< Stall RX endpoint. */
+#define XUSBPS_EPCR_RXE_MASK		0x00000080 /**< Transmit enable. - RX */
+#define XUSBPS_EPCR_RXR_MASK		0x00000040 /**< Data Toggle Reset Bit */
+/* @} */
+
+
+/** @name USB Command Register (CR) bit positions.
+ *  @{
+ */
+#define XUSBPS_CMD_RS_MASK	0x00000001 /**< Run/Stop */
+#define XUSBPS_CMD_RST_MASK	0x00000002 /**< Controller RESET */
+#define XUSBPS_CMD_FS01_MASK	0x0000000C /**< Frame List Size bit 0,1 */
+#define XUSBPS_CMD_PSE_MASK	0x00000010 /**< Periodic Sched Enable */
+#define XUSBPS_CMD_ASE_MASK	0x00000020 /**< Async Sched Enable */
+#define XUSBPS_CMD_IAA_MASK	0x00000040 /**< IRQ Async Advance Doorbell */
+#define XUSBPS_CMD_ASP_MASK	0x00000300 /**< Async Sched Park Mode Cnt */
+#define XUSBPS_CMD_ASPE_MASK	0x00000800 /**< Async Sched Park Mode Enbl */
+#define XUSBPS_CMD_SUTW_MASK	0x00002000 /**< Setup TripWire */
+#define XUSBPS_CMD_ATDTW_MASK	0x00004000 /**< Add dTD TripWire */
+#define XUSBPS_CMD_FS2_MASK	0x00008000 /**< Frame List Size bit 2 */
+#define XUSBPS_CMD_ITC_MASK	0x00FF0000 /**< IRQ Threshold Control */
+/* @} */
+
+
+/**
+ * @name Interrupt Threshold
+ * These definitions are used by software to set the maximum rate at which the
+ * USB controller will generate interrupt requests. The interrupt interval is
+ * given in number of micro-frames.
+ *
+ * USB defines a full-speed 1 ms frame time indicated by a Start Of Frame (SOF)
+ * packet each and every 1ms. USB also defines a high-speed micro-frame with a
+ * 125us frame time. For each micro-frame a SOF (Start Of Frame) packet is
+ * generated. Data is sent in between the SOF packets. The interrupt threshold
+ * defines how many micro-frames the controller waits before issuing an
+ * interrupt after data has been received.
+ *
+ * For a threshold of 0 the controller will issue an interrupt immediately
+ * after the last byte of the data has been received. For a threshold n>0 the
+ * controller will wait for n micro-frames before issuing an interrupt.
+ *
+ * Therefore, a setting of 8 micro-frames (default) means that the controller
+ * will issue at most 1 interrupt per millisecond.
+ *
+ * @{
+ */
+#define XUSBPS_CMD_ITHRESHOLD_0	0x00 /**< Immediate interrupt. */
+#define XUSBPS_CMD_ITHRESHOLD_1	0x01 /**< 1 micro-frame */
+#define XUSBPS_CMD_ITHRESHOLD_2	0x02 /**< 2 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_4	0x04 /**< 4 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_8	0x08 /**< 8 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_16	0x10 /**< 16 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_32	0x20 /**< 32 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_64	0x40 /**< 64 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_MAX	XUSBPS_CMD_ITHRESHOLD_64
+#define XUSBPS_CMD_ITHRESHOLD_DEFAULT	XUSBPS_CMD_ITHRESHOLD_8
+/* @} */
+
+
+
+/** @name USB Interrupt Status Register (ISR) / Interrupt Enable Register (IER)
+ * bit positions.
+ *  @{
+ */
+#define XUSBPS_IXR_UI_MASK	0x00000001 /**< USB Transaction Complete */
+#define XUSBPS_IXR_UE_MASK	0x00000002 /**< Transaction Error */
+#define XUSBPS_IXR_PC_MASK	0x00000004 /**< Port Change Detect */
+#define XUSBPS_IXR_FRE_MASK	0x00000008 /**< Frame List Rollover */
+#define XUSBPS_IXR_AA_MASK	0x00000020 /**< Async Advance */
+#define XUSBPS_IXR_UR_MASK	0x00000040 /**< RESET Received */
+#define XUSBPS_IXR_SR_MASK	0x00000080 /**< Start of Frame */
+#define XUSBPS_IXR_SLE_MASK	0x00000100 /**< Device Controller Suspend */
+#define XUSBPS_IXR_ULPI_MASK	0x00000400 /**< ULPI IRQ */
+#define XUSBPS_IXR_HCH_MASK	0x00001000 /**< Host Controller Halted
+						* Read Only */
+#define XUSBPS_IXR_RCL_MASK	0x00002000 /**< USB Reclamation  Read Only */
+#define XUSBPS_IXR_PS_MASK	0x00004000 /**< Periodic Sched Status
+						* Read Only */
+#define XUSBPS_IXR_AS_MASK	0x00008000 /**< Async Sched Status Read only */
+#define XUSBPS_IXR_NAK_MASK	0x00010000 /**< NAK IRQ */
+#define XUSBPS_IXR_UA_MASK	0x00040000 /**< USB Host Async IRQ */
+#define XUSBPS_IXR_UP_MASK	0x00080000 /**< USB Host Periodic IRQ */
+#define XUSBPS_IXR_TI0_MASK	0x01000000 /**< Timer 0 Interrupt */
+#define XUSBPS_IXR_TI1_MASK	0x02000000 /**< Timer 1 Interrupt */
+
+#define XUSBPS_IXR_ALL			(XUSBPS_IXR_UI_MASK	| \
+					 XUSBPS_IXR_UE_MASK		| \
+					 XUSBPS_IXR_PC_MASK	| \
+					 XUSBPS_IXR_FRE_MASK	| \
+					 XUSBPS_IXR_AA_MASK	| \
+					 XUSBPS_IXR_UR_MASK		| \
+					 XUSBPS_IXR_SR_MASK		| \
+					 XUSBPS_IXR_SLE_MASK	| \
+					 XUSBPS_IXR_ULPI_MASK		| \
+					 XUSBPS_IXR_HCH_MASK	| \
+					 XUSBPS_IXR_RCL_MASK	| \
+					 XUSBPS_IXR_PS_MASK | \
+					 XUSBPS_IXR_AS_MASK		| \
+					 XUSBPS_IXR_NAK_MASK		| \
+					 XUSBPS_IXR_UA_MASK	| \
+					 XUSBPS_IXR_UP_MASK | \
+					 XUSBPS_IXR_TI0_MASK | \
+					 XUSBPS_IXR_TI1_MASK)
+					/**< Mask for ALL IRQ types */
+/* @} */
+
+
+/** @name USB Mode Register (MODE) bit positions.
+ *  @{
+ */
+#define XUSBPS_MODE_CM_MASK		0x00000003 /**< Controller Mode Select */
+#define XUSBPS_MODE_CM_IDLE_MASK	0x00000000
+#define XUSBPS_MODE_CM_DEVICE_MASK	0x00000002
+#define XUSBPS_MODE_CM_HOST_MASK	0x00000003
+#define XUSBPS_MODE_ES_MASK		0x00000004 /**< USB Endian Select */
+#define XUSBPS_MODE_SLOM_MASK		0x00000008 /**< USB Setup Lockout Mode Disable */
+#define XUSBPS_MODE_SDIS_MASK		0x00000010
+#define XUSBPS_MODE_VALID_MASK		0x0000001F
+
+/* @} */
+
+
+/** @name USB Device Address Register (DEVICEADDR) bit positions.
+ *  @{
+ */
+#define XUSBPS_DEVICEADDR_DEVICEAADV_MASK	0x01000000
+					/**< Device Addr Auto Advance */
+#define XUSBPS_DEVICEADDR_ADDR_MASK		0xFE000000
+					/**< Device Address */
+#define XUSBPS_DEVICEADDR_ADDR_SHIFT		25
+					/**< Address shift */
+#define XUSBPS_DEVICEADDR_MAX			127
+					/**< Biggest allowed address */
+/* @} */
+
+/** @name USB TT Control Register (TTCTRL) bit positions.
+ *  @{
+ */
+#define XUSBPS_TTCTRL_HUBADDR_MASK	0x7F000000 /**< TT Hub Address */
+/* @} */
+
+
+/** @name USB Burst Size Register (BURSTSIZE) bit posisions.
+ *  @{
+ */
+#define XUSBPS_BURSTSIZE_RX_MASK	0x000000FF /**< RX Burst Length */
+#define XUSBPS_BURSTSIZE_TX_MASK	0x0000FF00 /**< TX Burst Length */
+/* @} */
+
+
+/** @name USB Tx Fill Tuning Register (TXFILL) bit positions.
+ *  @{
+ */
+#define XUSBPS_TXFILL_OVERHEAD_MASK	0x000000FF
+					/**< Scheduler Overhead */
+#define XUSBPS_TXFILL_HEALTH_MASK	0x00001F00
+					/**< Scheduler Health Cntr */
+#define XUSBPS_TXFILL_BURST_MASK	0x003F0000
+					/**< FIFO Burst Threshold */
+/* @} */
+
+
+/** @name USB ULPI Viewport Register (ULPIVIEW) bit positions.
+ *  @{
+ */
+#define XUSBPS_ULPIVIEW_DATWR_MASK	0x000000FF /**< ULPI Data Write */
+#define XUSBPS_ULPIVIEW_DATRD_MASK	0x0000FF00 /**< ULPI Data Read */
+#define XUSBPS_ULPIVIEW_ADDR_MASK	0x00FF0000 /**< ULPI Data Address */
+#define XUSBPS_ULPIVIEW_PORT_MASK	0x07000000 /**< ULPI Port Number */
+#define XUSBPS_ULPIVIEW_SS_MASK	0x08000000 /**< ULPI Synchronous State */
+#define XUSBPS_ULPIVIEW_RW_MASK	0x20000000 /**< ULPI Read/Write Control */
+#define XUSBPS_ULPIVIEW_RUN_MASK	0x40000000 /**< ULPI Run */
+#define XUSBPS_ULPIVIEW_WU_MASK	0x80000000 /**< ULPI Wakeup */
+/* @} */
+
+
+/** @name Port Status Control Register bit positions.
+ *  @{
+ */
+#define XUSBPS_PORTSCR_CCS_MASK  0x00000001 /**< Current Connect Status */
+#define XUSBPS_PORTSCR_CSC_MASK  0x00000002 /**< Connect Status Change */
+#define XUSBPS_PORTSCR_PE_MASK	  0x00000004 /**< Port Enable/Disable */
+#define XUSBPS_PORTSCR_PEC_MASK  0x00000008 /**< Port Enable/Disable Change */
+#define XUSBPS_PORTSCR_OCA_MASK  0x00000010 /**< Over-current Active */
+#define XUSBPS_PORTSCR_OCC_MASK  0x00000020 /**< Over-current Change */
+#define XUSBPS_PORTSCR_FPR_MASK  0x00000040 /**< Force Port Resume */
+#define XUSBPS_PORTSCR_SUSP_MASK 0x00000080 /**< Suspend */
+#define XUSBPS_PORTSCR_PR_MASK	  0x00000100 /**< Port Reset */
+#define XUSBPS_PORTSCR_HSP_MASK  0x00000200 /**< High Speed Port */
+#define XUSBPS_PORTSCR_LS_MASK	  0x00000C00 /**< Line Status */
+#define XUSBPS_PORTSCR_PP_MASK	  0x00001000 /**< Port Power */
+#define XUSBPS_PORTSCR_PO_MASK	  0x00002000 /**< Port Owner */
+#define XUSBPS_PORTSCR_PIC_MASK  0x0000C000 /**< Port Indicator Control */
+#define XUSBPS_PORTSCR_PTC_MASK  0x000F0000 /**< Port Test Control */
+#define XUSBPS_PORTSCR_WKCN_MASK 0x00100000 /**< Wake on Connect Enable */
+#define XUSBPS_PORTSCR_WKDS_MASK 0x00200000 /**< Wake on Disconnect Enable */
+#define XUSBPS_PORTSCR_WKOC_MASK 0x00400000 /**< Wake on Over-current Enable */
+#define XUSBPS_PORTSCR_PHCD_MASK 0x00800000 /**< PHY Low Power Suspend -
+						* Clock Disable */
+#define XUSBPS_PORTSCR_PFSC_MASK 0x01000000 /**< Port Force Full Speed
+						* Connect */
+#define XUSBPS_PORTSCR_PSPD_MASK 0x0C000000 /**< Port Speed */
+/* @} */
+
+
+/** @name On-The-Go Status Control Register (OTGCSR) bit positions.
+ *  @{
+ */
+#define XUSBPS_OTGSC_VD_MASK	 0x00000001 /**< VBus Discharge Bit */
+#define XUSBPS_OTGSC_VC_MASK	 0x00000002 /**< VBus Charge Bit */
+#define XUSBPS_OTGSC_HAAR_MASK	 0x00000004 /**< HW Assist Auto Reset
+				 		       *  Enable Bit */
+#define XUSBPS_OTGSC_OT_MASK	 0x00000008 /**< OTG Termination Bit */
+#define XUSBPS_OTGSC_DP_MASK	 0x00000010 /**< Data Pulsing Pull-up
+				 		       *  Enable Bit */
+#define XUSBPS_OTGSC_IDPU_MASK	 0x00000020 /**< ID Pull-up Enable Bit */
+#define XUSBPS_OTGSC_HADP_MASK	 0x00000040 /**< HW Assist Data Pulse
+							* Enable Bit */
+#define XUSBPS_OTGSC_HABA_MASK	 0x00000080 /**< USB Hardware Assist
+						       *  B Disconnect to A
+						       *  Connect Enable Bit */
+#define XUSBPS_OTGSC_ID_MASK	 0x00000100 /**< ID Status Flag */
+#define XUSBPS_OTGSC_AVV_MASK	 0x00000200 /**< USB A VBus Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_ASV_MASK	 0x00000400 /**< USB A Session Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_BSV_MASK	 0x00000800 /**< USB B Session Valid Status Flag */
+#define XUSBPS_OTGSC_BSE_MASK	 0x00001000 /**< USB B Session End Status Flag */
+#define XUSBPS_OTGSC_1MST_MASK	 0x00002000 /**< USB 1 Millisecond Timer Status Flag */
+#define XUSBPS_OTGSC_DPS_MASK	 0x00004000 /**< Data Pulse Status Flag */
+#define XUSBPS_OTGSC_IDIS_MASK	 0x00010000 /**< USB ID Interrupt Status Flag */
+#define XUSBPS_OTGSC_AVVIS_MASK 0x00020000 /**< USB A VBus Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_ASVIS_MASK 0x00040000 /**< USB A Session Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_BSVIS_MASK 0x00080000 /**< USB B Session Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_BSEIS_MASK 0x00100000 /**< USB B Session End Interrupt Status Flag */
+#define XUSBPS_OTGSC_1MSS_MASK	 0x00200000 /**< 1 Millisecond Timer Interrupt Status Flag */
+#define XUSBPS_OTGSC_DPIS_MASK	 0x00400000 /**< Data Pulse Interrupt Status Flag */
+#define XUSBPS_OTGSC_IDIE_MASK	 0x01000000 /**< ID Interrupt Enable Bit */
+#define XUSBPS_OTGSC_AVVIE_MASK 0x02000000 /**< USB A VBus Valid Interrupt Enable Bit */
+#define XUSBPS_OTGSC_ASVIE_MASK 0x04000000 /**< USB A Session Valid Interrupt Enable Bit */
+#define XUSBPS_OTGSC_BSVIE_MASK 0x08000000 /**< USB B Session Valid Interrupt Enable Bit */
+#define XUSBPS_OTGSC_BSEE_MASK	 0x10000000 /**< USB B Session End Interrupt Enable Bit */
+#define XUSBPS_OTGSC_1MSE_MASK	 0x20000000 /**< 1 Millisecond Timer
+						* Interrupt Enable Bit */
+#define XUSBPS_OTGSC_DPIE_MASK	 0x40000000 /**< Data Pulse Interrupt
+							* Enable Bit */
+
+#define XUSBPS_OTG_ISB_ALL	(XUSBPS_OTGSC_IDIS_MASK |\
+				XUSBPS_OTGSC_AVVIS_MASK | \
+				XUSBPS_OTGSC_ASVIS_MASK | \
+				XUSBPS_OTGSC_BSVIS_MASK | \
+				XUSBPS_OTGSC_BSEIS_MASK | \
+				XUSBPS_OTGSC_1MSS_MASK | \
+				XUSBPS_OTGSC_DPIS_MASK)
+				/** Mask for All IRQ status masks */
+
+#define XUSBPS_OTG_IEB_ALL	(XUSBPS_OTGSC_IDIE_MASK |\
+				XUSBPS_OTGSC_AVVIE_MASK | \
+				XUSBPS_OTGSC_ASVIE_MASK | \
+				XUSBPS_OTGSC_BSVIE_MASK | \
+				XUSBPS_OTGSC_BSEE_IEB_MASK | \
+				XUSBPS_OTGSC_1MSE_MASK | \
+				XUSBPS_OTGSC_DPIE_MASK)
+				/** Mask for All IRQ Enable masks */
+/* @} */
+
+
+/**< Alignment of the Device Queue Head List BASE. */
+#define XUSBPS_dQH_BASE_ALIGN		2048
+
+/**< Alignment of a Device Queue Head structure. */
+#define XUSBPS_dQH_ALIGN		64
+
+/**< Alignment of a Device Transfer Descriptor structure. */
+#define XUSBPS_dTD_ALIGN		32
+
+/**< Size of one RX buffer for a OUT Transfer Descriptor. */
+#define XUSBPS_dTD_BUF_SIZE		4096
+
+/**< Maximum size of one RX/TX buffer. */
+#define XUSBPS_dTD_BUF_MAX_SIZE	16*1024
+
+/**< Alignment requirement for Transfer Descriptor buffers. */
+#define XUSBPS_dTD_BUF_ALIGN		4096
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param	BaseAddress is the base address for the USB registers.
+* @param	RegOffset is the register offset to be read.
+*
+* @return	The 32-bit value of the register.
+*
+* @note		C-style signature:
+*		u32 XUsbPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XUsbPs_ReadReg(BaseAddress, RegOffset) \
+				Xil_In32(BaseAddress + (RegOffset))
+
+
+/****************************************************************************/
+/**
+*
+* This macro writes the given register.
+*
+* @param	BaseAddress is the the base address for the USB registers.
+* @param	RegOffset is the register offset to be written.
+* @param	Data is the the 32-bit value to write to the register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XUsbPs_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+ *****************************************************************************/
+#define XUsbPs_WriteReg(BaseAddress, RegOffset, Data) \
+				Xil_Out32(BaseAddress + (RegOffset), (Data))
+
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the USB PS interface
+ */
+void XUsbPs_ResetHw(u32 BaseAddress);
+/************************** Variable Definitions ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XUSBPS_L_H */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_intr.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_intr.c
new file mode 100644
index 0000000000000000000000000000000000000000..94fd3dee6de15c58163f9e38e70c3733548926b4
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_intr.c
@@ -0,0 +1,472 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal 
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************/
+/**
+ * @file xusbps_intr.c
+* @addtogroup usbps_v2_2
+* @{
+ *
+ * This file contains the functions that are related to interrupt processing
+ * for the EPB USB driver.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- ----------------------------------------------------------
+ * 1.00a jz  10/10/10 First release
+ * 1.03a nm  09/21/12 Fixed CR#678977. Added proper sequence for setup packet
+ *                    handling.
+ * 2.3   bss 01/19/16 Modified XUsbPs_EpQueueRequest function to fix CR#873972
+ *            (moving of dTD Head/Tail Pointers properly).
+ * </pre>
+ ******************************************************************************/
+
+/***************************** Include Files **********************************/
+
+#include "xusbps.h"
+#include "xusbps_endpoint.h"
+
+/************************** Constant Definitions ******************************/
+
+/**************************** Type Definitions ********************************/
+
+/***************** Macros (Inline Functions) Definitions **********************/
+
+/************************** Variable Definitions ******************************/
+
+/************************** Function Prototypes *******************************/
+
+static void XUsbPs_IntrHandleTX(XUsbPs *InstancePtr, u32 EpCompl);
+static void XUsbPs_IntrHandleRX(XUsbPs *InstancePtr, u32 EpCompl);
+static void XUsbPs_IntrHandleReset(XUsbPs *InstancePtr, u32 IrqSts);
+static void XUsbPs_IntrHandleEp0Setup(XUsbPs *InstancePtr);
+
+/*****************************************************************************/
+/**
+* This function is the first-level interrupt handler for the USB core. All USB
+* interrupts will be handled here. Depending on the type of the interrupt,
+* second level interrupt handler may be called. Second level interrupt
+* handlers will be registered by the user using the:
+*    XUsbPs_IntrSetHandler()
+* and/or
+*    XUsbPs_EpSetHandler()
+* functions.
+*
+*
+* @param	HandlerRef is a Reference passed to the interrupt register
+*		function. In our case this will be a pointer to the XUsbPs
+*		instance.
+*
+* @return	None
+*
+* @note		None
+*
+******************************************************************************/
+void XUsbPs_IntrHandler(void *HandlerRef)
+{
+	XUsbPs	*InstancePtr;
+
+	u32	IrqSts;
+
+	Xil_AssertVoid(HandlerRef != NULL);
+
+	InstancePtr = (XUsbPs *) HandlerRef;
+
+	/* Handle controller (non-endpoint) related interrupts. */
+	IrqSts = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_ISR_OFFSET);
+
+	/* Clear the interrupt status register. */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_ISR_OFFSET, IrqSts);
+
+	/* Nak interrupt, used to respond to host's IN request */
+	if(IrqSts & XUSBPS_IXR_NAK_MASK) {
+		/* Ack the hardware	 */
+		XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+					XUSBPS_EPNAKISR_OFFSET,
+			XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XUSBPS_EPNAKISR_OFFSET));
+	}
+
+
+	/***************************************************************
+	 *
+	 * Handle general interrupts. Endpoint interrupts will be handler
+	 * later.
+	 *
+	 */
+
+	/* RESET interrupt.*/
+	if (IrqSts & XUSBPS_IXR_UR_MASK) {
+		XUsbPs_IntrHandleReset(InstancePtr, IrqSts);
+		return;
+	}
+
+	/* Check if we have a user handler that needs to be called. Note that
+	 * this is the handler for general interrupts. Endpoint interrupts will
+	 * be handled below.
+	 */
+	if ((IrqSts & InstancePtr->HandlerMask) && InstancePtr->HandlerFunc) {
+		(InstancePtr->HandlerFunc)(InstancePtr->HandlerRef, IrqSts);
+	}
+
+
+	/***************************************************************
+	 *
+	 * Handle Endpoint interrupts.
+	 *
+	 */
+	if (IrqSts & XUSBPS_IXR_UI_MASK) {
+		u32	EpStat;
+		u32	EpCompl;
+
+		/* ENDPOINT 0 SETUP PACKET HANDLING
+		 *
+		 * Check if we got a setup packet on endpoint 0. Currently we
+		 * only check for setup packets on endpoint 0 as we would not
+		 * expect setup packets on any other endpoint (even though it
+		 * is possible to send setup packets on other endpoints).
+		 */
+		EpStat = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XUSBPS_EPSTAT_OFFSET);
+		if (EpStat & 0x0001) {
+			/* Handle the setup packet */
+			XUsbPs_IntrHandleEp0Setup(InstancePtr);
+
+			/* Re-Prime the endpoint.
+			 * Endpoint is de-primed if a setup packet comes in.
+	 		 */
+			XUsbPs_EpPrime(InstancePtr, 0, XUSBPS_EP_DIRECTION_OUT);
+		}
+
+		/* Check for RX and TX complete interrupts. */
+		EpCompl = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XUSBPS_EPCOMPL_OFFSET);
+
+
+		/* ACK the complete interrupts. */
+		XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+					XUSBPS_EPCOMPL_OFFSET, EpCompl);
+
+		/* Check OUT (RX) endpoints. */
+		if (EpCompl & XUSBPS_EP_OUT_MASK) {
+			XUsbPs_IntrHandleRX(InstancePtr, EpCompl);
+		}
+
+		/* Check IN (TX) endpoints. */
+		if (EpCompl & XUSBPS_EP_IN_MASK) {
+			XUsbPs_IntrHandleTX(InstancePtr, EpCompl);
+		}
+	}
+}
+
+
+/*****************************************************************************/
+/**
+* This function registers the user callback handler for controller
+* (non-endpoint) interrupts.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	CallBackFunc is the Callback function to register.
+*		CallBackFunc may be NULL to clear the entry.
+* @param	CallBackRef is the user data reference passed to the
+*		callback function. CallBackRef may be NULL.
+* @param	Mask is the User interrupt mask. Defines which interrupts
+*		will cause the callback to be called.
+*
+* @return
+*		- XST_SUCCESS: Callback registered successfully.
+*		- XST_FAILURE: Callback could not be registered.
+*
+* @note		None.
+*
+******************************************************************************/
+int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr,
+			   XUsbPs_IntrHandlerFunc CallBackFunc,
+			   void *CallBackRef, u32 Mask)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	InstancePtr->HandlerFunc	= CallBackFunc;
+	InstancePtr->HandlerRef		= CallBackRef;
+	InstancePtr->HandlerMask	= Mask;
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* This function handles TX buffer interrupts. It is called by the interrupt
+* when a transmit complete interrupt occurs. It returns buffers of completed
+* descriptors to the caller.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	EpCompl is the Bit mask of endpoints that caused a transmit
+*		complete interrupt.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void XUsbPs_IntrHandleTX(XUsbPs *InstancePtr, u32 EpCompl)
+{
+	int Index;
+	u32 Mask;
+	int NumEp;
+
+	/* Check all endpoints for TX complete bits.
+	 */
+	Mask	= 0x00010000;
+	NumEp	= InstancePtr->DeviceConfig.NumEndpoints;
+
+	/* Check for every endpoint if its TX complete bit is
+	 * set.
+	 */
+	for (Index = 0; Index < NumEp; Index++, Mask <<= 1) {
+		XUsbPs_EpIn	*Ep;
+
+		if (!(EpCompl & Mask)) {
+			continue;
+		}
+		/* The TX complete bit for this endpoint is
+		 * set. Walk the list of descriptors to see
+		 * which ones are completed.
+		 */
+		Ep = &InstancePtr->DeviceConfig.Ep[Index].In;
+		do {
+
+			XUsbPs_dTDInvalidateCache(Ep->dTDTail);
+
+			/* If the descriptor is not active then the buffer has
+			 * not been sent yet.
+			 */
+			if (XUsbPs_dTDIsActive(Ep->dTDTail)) {
+				break;
+			}
+
+			if (Ep->HandlerFunc) {
+				void *BufPtr;
+
+				BufPtr = (void *) XUsbPs_ReaddTD(Ep->dTDTail,
+							XUSBPS_dTDUSERDATA);
+
+				Ep->HandlerFunc(Ep->HandlerRef, Index,
+						XUSBPS_EP_EVENT_DATA_TX,
+								BufPtr);
+			}
+
+			Ep->dTDTail = XUsbPs_dTDGetNLP(Ep->dTDTail);
+		} while(Ep->dTDTail != Ep->dTDHead);
+	}
+}
+
+
+/*****************************************************************************/
+/**
+ * This function handles RX buffer interrupts. It is called by the interrupt
+ * when a receive complete interrupt occurs. It notifies the callback functions
+ * that have been registered with the individual endpoints that data has been
+ * received.
+ *
+ * @param	InstancePtr
+ * 		Pointer to the XUsbPs instance of the controller.
+ *
+ * @param	EpCompl
+ * 		Bit mask of endpoints that caused a receive complete interrupt.
+ * @return
+ *		none
+ *
+ ******************************************************************************/
+static void XUsbPs_IntrHandleRX(XUsbPs *InstancePtr, u32 EpCompl)
+{
+	XUsbPs_EpOut	*Ep;
+	int		Index;
+	u32		Mask;
+	int		NumEp;
+
+	/* Check all endpoints for RX complete bits. */
+	Mask	= 0x00000001;
+	NumEp	= InstancePtr->DeviceConfig.NumEndpoints;
+
+
+	/* Check for every endpoint if its RX complete bit is set.*/
+	for (Index = 0; Index < NumEp; Index++, Mask <<= 1) {
+		int numP = 0;
+
+		if (!(EpCompl & Mask)) {
+			continue;
+		}
+		Ep = &InstancePtr->DeviceConfig.Ep[Index].Out;
+
+		XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
+
+		/* Handle all finished dTDs */
+		while (!XUsbPs_dTDIsActive(Ep->dTDCurr)) {
+			numP += 1;
+			if (Ep->HandlerFunc) {
+				Ep->HandlerFunc(Ep->HandlerRef, Index,
+						XUSBPS_EP_EVENT_DATA_RX, NULL);
+			}
+
+			Ep->dTDCurr = XUsbPs_dTDGetNLP(Ep->dTDCurr);
+			XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
+		}
+		/* Re-Prime the endpoint.*/
+		XUsbPs_EpPrime(InstancePtr, Index, XUSBPS_EP_DIRECTION_OUT);
+	}
+}
+
+
+/*****************************************************************************/
+/**
+* This function handles a RESET interrupt. It will notify the interrupt
+* handler callback of the RESET condition.
+*
+* @param	InstancePtr is pointer to the XUsbPs instance of the controller
+* @param	IrqSts is the Interrupt status register content.
+*		To be passed on to the user.
+*
+* @return	None
+*
+* @Note		None.
+*
+******************************************************************************/
+static void XUsbPs_IntrHandleReset(XUsbPs *InstancePtr, u32 IrqSts)
+{
+	int Timeout;
+
+	/* Clear all setup token semaphores by reading the
+	 * XUSBPS_EPSTAT_OFFSET register and writing its value back to
+	 * itself.
+	 */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPSTAT_OFFSET,
+		XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_EPSTAT_OFFSET));
+
+	/* Clear all the endpoint complete status bits by reading the
+	 * XUSBPS_EPCOMPL_OFFSET register and writings its value back
+	 * to itself.
+	 */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XUSBPS_EPCOMPL_OFFSET,
+		XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_EPCOMPL_OFFSET));
+
+	/* Cancel all endpoint prime status by waiting until all bits
+	 * in XUSBPS_EPPRIME_OFFSET are 0 and then writing 0xFFFFFFFF
+	 * to XUSBPS_EPFLUSH_OFFSET.
+	 *
+	 * Avoid hanging here by using a Timeout counter...
+	 */
+	Timeout = XUSBPS_TIMEOUT_COUNTER;
+	while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XUSBPS_EPPRIME_OFFSET) &
+					XUSBPS_EP_ALL_MASK) && --Timeout) {
+		/* NOP */
+	}
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_EPFLUSH_OFFSET, 0xFFFFFFFF);
+
+	/* Make sure that the reset bit in XUSBPS_PORTSCR1_OFFSET is
+	 * still set at this point. If the code gets to this point and
+	 * the reset bit has already been cleared we are in trouble and
+	 * hardware reset is necessary.
+	 */
+	if (!(XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_PORTSCR1_OFFSET) &
+				XUSBPS_PORTSCR_PR_MASK)) {
+		/* Send a notification to the user that a hardware
+		 * RESET is required. At this point we can only hope
+		 * that the user registered an interrupt handler and
+		 * will issue a hardware RESET.
+		 */
+		if (InstancePtr->HandlerFunc) {
+			(InstancePtr->HandlerFunc)(InstancePtr->HandlerRef,
+						   IrqSts);
+		}
+		else {
+			for (;;);
+		}
+
+		/* If we get here there is nothing more to do. The user
+		 * should have reset the core.
+		 */
+		return;
+	}
+
+	/* Check if we have a user handler that needs to be called.
+	 */
+	if (InstancePtr->HandlerFunc) {
+		(InstancePtr->HandlerFunc)(InstancePtr->HandlerRef, IrqSts);
+	}
+
+	/* We are done. After RESET we don't proceed in the interrupt
+	 * handler.
+	 */
+}
+
+
+/*****************************************************************************/
+/**
+* This function handles a Setup Packet interrupt. It will notify the interrupt
+* handler callback of the RESET condition.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+*
+* @return	None
+*
+* @Note 	None
+*
+******************************************************************************/
+static void XUsbPs_IntrHandleEp0Setup(XUsbPs *InstancePtr)
+{
+
+	XUsbPs_EpOut	*Ep;
+
+	/* Notifiy the user. */
+	Ep = &InstancePtr->DeviceConfig.Ep[0].Out;
+
+	if (Ep->HandlerFunc) {
+		Ep->HandlerFunc(Ep->HandlerRef, 0,
+				XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED, NULL);
+	}
+}
+
+
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_sinit.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..1da441db525cf0e4e92d8d97fde99dd2ce1298bd
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_sinit.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal 
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+ *
+ * @file xusbps_sinit.c
+* @addtogroup usbps_v2_2
+* @{
+ *
+ * The implementation of the XUsbPs driver's static initialzation
+ * functionality.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a wgr  10/10/10 First release
+ * </pre>
+ *
+ *****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xusbps.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+extern XUsbPs_Config XUsbPs_ConfigTable[];
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Looks up the controller configuration based on the unique controller ID. A
+* table contains the configuration info for each controller in the system.
+*
+* @param	DeviceID is the ID of the controller to look up the
+*		configuration for.
+*
+* @return
+*		A pointer to the configuration found or NULL if the specified
+*		controller ID was not found.
+*
+******************************************************************************/
+XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceID)
+{
+	XUsbPs_Config *CfgPtr = NULL;
+
+	int Index;
+
+	for (Index = 0; Index < XPAR_XUSBPS_NUM_INSTANCES; Index++) {
+		if (XUsbPs_ConfigTable[Index].DeviceID == DeviceID) {
+			CfgPtr = &XUsbPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/Makefile b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..837ca13624ab228e150dee23b0b07180f6f4de13
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xadcps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling xadcps"
+
+xadcps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xadcps_includes
+
+xadcps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.c
new file mode 100644
index 0000000000000000000000000000000000000000..92a86560bfe169b7172c2be80b5512f777f7f0a9
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.c
@@ -0,0 +1,1831 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps.c
+* @addtogroup xadcps_v2_2
+* @{
+*
+* This file contains the driver API functions that can be used to access
+* the XADC device.
+*
+* Refer to the xadcps.h header file for more information about this driver.
+*
+* @note 	None.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI xadc driver
+* 1.01a bss    02/18/13	Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
+*			XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
+*			to fix CR #693371
+* 2.1   bss    08/05/14	Modified Assert for XAdcPs_SetSingleChParams to fix
+*			CR #807563.
+* 2.2	bss	   04/27/14 Modified to use correct Device Config base address
+*						(CR#854437).
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xadcps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+
+void XAdcPs_WriteInternalReg(XAdcPs *InstancePtr, u32 RegOffset, u32 Data);
+u32 XAdcPs_ReadInternalReg(XAdcPs *InstancePtr, u32 RegOffset);
+
+
+/************************** Variable Definitions ****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* This function initializes a specific XAdcPs device/instance. This function
+* must be called prior to using the XADC device.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	ConfigPtr points to the XAdcPs device configuration structure.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. If the address translation is not used then the
+*		physical address is passed.
+*		Unexpected errors may occur if the address mapping is changed
+*		after this function is invoked.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*
+* @note		The user needs to first call the XAdcPs_LookupConfig() API
+*		which returns the Configuration structure pointer which is
+*		passed as a parameter to the XAdcPs_CfgInitialize() API.
+*
+******************************************************************************/
+int XAdcPs_CfgInitialize(XAdcPs *InstancePtr, XAdcPs_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+
+	u32 RegValue;
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+
+	/*
+	 * Set the values read from the device config and the base address.
+	 */
+	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+
+	/* Write Unlock value to Device Config Unlock register */
+	XAdcPs_WriteReg(XPAR_XDCFG_0_BASEADDR,
+				XADCPS_UNLK_OFFSET, XADCPS_UNLK_VALUE);
+
+	/* Enable the PS access of xadc and set FIFO thresholds */
+
+	RegValue = XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+			XADCPS_CFG_OFFSET);
+
+	RegValue = RegValue | XADCPS_CFG_ENABLE_MASK |
+			XADCPS_CFG_CFIFOTH_MASK | XADCPS_CFG_DFIFOTH_MASK;
+
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+					XADCPS_CFG_OFFSET, RegValue);
+
+	/* Release xadc from reset */
+
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+						XADCPS_MCTL_OFFSET, 0x00);
+
+	/*
+	 * Indicate the instance is now ready to use and
+	 * initialized without error.
+	 */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	return XST_SUCCESS;
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions sets the contents of the Config Register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Data is the 32 bit data to be written to the Register.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetConfigRegister(XAdcPs *InstancePtr, u32 Data)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_CFG_OFFSET, Data);
+
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions reads the contents of the Config Register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	A 32-bit value representing the contents of the Config Register.
+*		Use the XADCPS_SR_*_MASK constants defined in xadcps_hw.h to
+*		interpret the returned value.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetConfigRegister(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Config Register and return the value.
+	 */
+	return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_CFG_OFFSET);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions reads the contents of the Miscellaneous Status Register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	A 32-bit value representing the contents of the Miscellaneous
+*		Status Register. Use the XADCPS_MSTS_*_MASK constants defined
+*		in xadcps_hw.h to interpret the returned value.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetMiscStatus(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Miscellaneous Status Register and return the value.
+	 */
+	return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_MSTS_OFFSET);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions sets the contents of the Miscellaneous Control register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Data is the 32 bit data to be written to the Register.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetMiscCtrlRegister(XAdcPs *InstancePtr, u32 Data)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Write to the Miscellaneous control register Register.
+	 */
+	 XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_MCTL_OFFSET, Data);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions reads the contents of the Miscellaneous control register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	A 32-bit value representing the contents of the Config Register.
+*		Use the XADCPS_SR_*_MASK constants defined in xadcps_hw.h to
+*		interpret the returned value.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetMiscCtrlRegister(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Miscellaneous control register and return the value.
+	 */
+	return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_MCTL_OFFSET);
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function resets the XADC Hard Macro in the device.
+*
+* @param	InstancePtr is a pointer to the Xxadc instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XAdcPs_Reset(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Generate the reset by Control
+	 * register and release from reset
+	 */
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_MCTL_OFFSET, 0x10);
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_MCTL_OFFSET, 0x00);
+}
+
+
+/****************************************************************************/
+/**
+*
+* Get the ADC converted data for the specified channel.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Channel is the channel number. Use the XADCPS_CH_* defined in
+*		the file xadcps.h.
+*		The valid channels are
+*		- 0 to 6
+*		- 13 to 31
+*
+* @return	A 16-bit value representing the ADC converted data for the
+*		specified channel. The XADC Monitor/ADC device guarantees
+* 		a 10 bit resolution for the ADC converted data and data is the
+*		10 MSB bits of the 16 data read from the device.
+*
+* @note		The channels 7,8,9 are used for calibration of the device and
+*		hence there is no associated data with this channel.
+*
+*****************************************************************************/
+u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel)
+{
+
+	u32 RegData;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((Channel <= XADCPS_CH_VBRAM) ||
+			 ((Channel >= XADCPS_CH_VCCPINT) &&
+			 (Channel <= XADCPS_CH_AUX_MAX)));
+
+	RegData = XAdcPs_ReadInternalReg(InstancePtr,
+						(XADCPS_TEMP_OFFSET +
+						Channel));
+	return (u16) RegData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the calibration coefficient data for the specified
+* parameter.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	CoeffType specifies the calibration coefficient
+*		to be read. Use XADCPS_CALIB_* constants defined in xadcps.h to
+*		specify the calibration coefficient to be read.
+*
+* @return	A 16-bit value representing the calibration coefficient.
+*		The XADC device guarantees a 10 bit resolution for
+*		the ADC converted data and data is the 10 MSB bits of the 16
+*		data read from the device.
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType)
+{
+	u32 RegData;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(CoeffType <= XADCPS_CALIB_GAIN_ERROR_COEFF);
+
+	/*
+	 * Read the selected calibration coefficient.
+	 */
+	RegData = XAdcPs_ReadInternalReg(InstancePtr,
+					(XADCPS_ADC_A_SUPPLY_CALIB_OFFSET +
+					CoeffType));
+	return (u16) RegData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function reads the Minimum/Maximum measurement for one of the
+* specified parameters. Use XADCPS_MAX_* and XADCPS_MIN_* constants defined in
+* xadcps.h to specify the parameters (Temperature, VccInt, VccAux, VBram,
+* VccPInt, VccPAux and VccPDro).
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	MeasurementType specifies the parameter for which the
+*		Minimum/Maximum measurement has to be read.
+*		Use XADCPS_MAX_* and XADCPS_MIN_* constants defined in xadcps.h to
+*		specify the data to be read.
+*
+* @return	A 16-bit value representing the maximum/minimum measurement for
+*		specified parameter.
+*		The XADC device guarantees a 10 bit resolution for
+*		the ADC converted data and data is the 10 MSB bits of the 16
+*		data read from the device.
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType)
+{
+	u32 RegData;
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((MeasurementType <= XADCPS_MAX_VCCPDRO) ||
+			((MeasurementType >= XADCPS_MIN_VCCPINT) &&
+			(MeasurementType <= XADCPS_MIN_VCCPDRO)))
+
+	/*
+	 * Read and return the specified Minimum/Maximum measurement.
+	 */
+	RegData = XAdcPs_ReadInternalReg(InstancePtr,
+					(XADCPS_MAX_TEMP_OFFSET +
+					MeasurementType));
+	return (u16) RegData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the number of samples of averaging that is to be done for
+* all the channels in both the single channel mode and sequence mode of
+* operations.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Average is the number of samples of averaging programmed to the
+*		Configuration Register 0. Use the XADCPS_AVG_* definitions defined
+*		in xadcps.h file :
+*		- XADCPS_AVG_0_SAMPLES for no averaging
+*		- XADCPS_AVG_16_SAMPLES for 16 samples of averaging
+*		- XADCPS_AVG_64_SAMPLES for 64 samples of averaging
+*		- XADCPS_AVG_256_SAMPLES for 256 samples of averaging
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average)
+{
+	u32 RegData;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Average <= XADCPS_AVG_256_SAMPLES);
+
+	/*
+	 * Write the averaging value into the Configuration Register 0.
+	 */
+	RegData = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR0_OFFSET) &
+					(~XADCPS_CFR0_AVG_VALID_MASK);
+
+	RegData |=  (((u32) Average << XADCPS_CFR0_AVG_SHIFT));
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+					RegData);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the number of samples of averaging configured for all
+* the channels in the Configuration Register 0.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	The averaging read from the Configuration Register 0 is
+*		returned. Use the XADCPS_AVG_* bit definitions defined in
+*		xadcps.h file to interpret the returned value :
+*		- XADCPS_AVG_0_SAMPLES means no averaging
+*		- XADCPS_AVG_16_SAMPLES means 16 samples of averaging
+*		- XADCPS_AVG_64_SAMPLES means 64 samples of averaging
+*		- XADCPS_AVG_256_SAMPLES means 256 samples of averaging
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XAdcPs_GetAvg(XAdcPs *InstancePtr)
+{
+	u32 Average;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the averaging value from the Configuration Register 0.
+	 */
+	Average = XAdcPs_ReadInternalReg(InstancePtr,
+			XADCPS_CFR0_OFFSET) & XADCPS_CFR0_AVG_VALID_MASK;
+
+
+	return ((u8) (Average >> XADCPS_CFR0_AVG_SHIFT));
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the given parameters in the Configuration Register 0 in
+* the single channel mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Channel is the channel number for the singel channel mode.
+*		The valid channels are 0 to 6, 8, and 13 to 31.
+*		If the external Mux is used then this specifies the channel
+*		oonnected to the external Mux. Please read the Device Spec
+*		to know which channels are valid.
+* @param 	IncreaseAcqCycles is a boolean parameter which specifies whether
+*		the Acquisition time for the external channels has to be
+*		increased to 10 ADCCLK cycles (specify TRUE) or remain at the
+*		default 4 ADCCLK cycles (specify FALSE). This parameter is
+*		only valid for the external channels.
+* @param 	IsDifferentialMode is a boolean parameter which specifies
+*		unipolar(specify FALSE) or differential mode (specify TRUE) for
+*		the analog inputs. The 	input mode is only valid for the
+*		external channels.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the Configuration Register 0.
+*		- XST_FAILURE if the channel sequencer is enabled or the input
+*		parameters are not valid for the selected channel.
+*
+* @note
+*		- The number of samples for the averaging for all the channels
+*		is set by using the function XAdcPs_SetAvg.
+*		- The calibration of the device is done by doing a ADC
+*		conversion on the calibration channel(channel 8). The input
+*		parameters IncreaseAcqCycles, IsDifferentialMode and
+*		IsEventMode are not valid for this channel
+*
+*
+*****************************************************************************/
+int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
+				u8 Channel,
+				int IncreaseAcqCycles,
+				int IsEventMode,
+				int IsDifferentialMode)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((Channel <= XADCPS_CH_VBRAM) ||
+			(Channel == XADCPS_CH_ADC_CALIB) ||
+			((Channel >= XADCPS_CH_VCCPINT) &&
+			(Channel <= XADCPS_CH_AUX_MAX)));
+	Xil_AssertNonvoid((IncreaseAcqCycles == TRUE) ||
+			(IncreaseAcqCycles == FALSE));
+	Xil_AssertNonvoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
+	Xil_AssertNonvoid((IsDifferentialMode == TRUE) ||
+			(IsDifferentialMode == FALSE));
+
+	/*
+	 * Check if the device is in single channel mode else return failure
+	 */
+	if ((XAdcPs_GetSequencerMode(InstancePtr) !=
+		XADCPS_SEQ_MODE_SINGCHAN)) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Read the Configuration Register 0.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR0_OFFSET) &
+					XADCPS_CFR0_AVG_VALID_MASK;
+
+	/*
+	 * Select the number of acquisition cycles. The acquisition cycles is
+	 * only valid for the external channels.
+	 */
+	if (IncreaseAcqCycles == TRUE) {
+		if (((Channel >= XADCPS_CH_AUX_MIN) &&
+			(Channel <= XADCPS_CH_AUX_MAX)) ||
+			(Channel == XADCPS_CH_VPVN)){
+			RegValue |= XADCPS_CFR0_ACQ_MASK;
+		} else {
+			return XST_FAILURE;
+		}
+
+	}
+
+	/*
+	 * Select the input mode. The input mode is only valid for the
+	 * external channels.
+	 */
+	if (IsDifferentialMode == TRUE) {
+
+		if (((Channel >= XADCPS_CH_AUX_MIN) &&
+			(Channel <= XADCPS_CH_AUX_MAX)) ||
+			(Channel == XADCPS_CH_VPVN)){
+			RegValue |= XADCPS_CFR0_DU_MASK;
+		} else {
+			return XST_FAILURE;
+		}
+	}
+
+	/*
+	 * Select the ADC mode.
+	 */
+	if (IsEventMode == TRUE) {
+		RegValue |= XADCPS_CFR0_EC_MASK;
+	}
+
+	/*
+	 * Write the given values into the Configuration Register 0.
+	 */
+	RegValue |= (Channel & XADCPS_CFR0_CHANNEL_MASK);
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+				RegValue);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the alarm outputs for the specified alarms in the
+* Configuration Register 1.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	AlmEnableMask is the bit-mask of the alarm outputs to be enabled
+*		in the Configuration Register 1.
+*		Bit positions of 1 will be enabled. Bit positions of 0 will be
+*		disabled. This mask is formed by OR'ing XADCPS_CFR1_ALM_*_MASK and
+*		XADCPS_CFR1_OT_MASK masks defined in xadcps_hw.h.
+*
+* @return	None.
+*
+* @note		The implementation of the alarm enables in the Configuration
+*		register 1 is such that the alarms for bit positions of 1 will
+*		be disabled and alarms for bit positions of 0 will be enabled.
+*		The alarm outputs specified by the AlmEnableMask are negated
+*		before writing to the Configuration Register 1.
+*
+*
+*****************************************************************************/
+void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr, XADCPS_CFR1_OFFSET);
+
+	RegValue &= (u32)~XADCPS_CFR1_ALM_ALL_MASK;
+	RegValue |= (~AlmEnableMask & XADCPS_CFR1_ALM_ALL_MASK);
+
+	/*
+	 * Enable/disables the alarm enables for the specified alarm bits in the
+	 * Configuration Register 1.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
+				RegValue);
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the status of the alarm output enables in the
+* Configuration Register 1.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	This is the bit-mask of the enabled alarm outputs in the
+*		Configuration Register 1. Use the masks XADCPS_CFR1_ALM*_* and
+*		XADCPS_CFR1_OT_MASK defined in xadcps_hw.h to interpret the
+*		returned value.
+*		Bit positions of 1 indicate that the alarm output is enabled.
+*		Bit positions of 0 indicate that the alarm output is disabled.
+*
+*
+* @note		The implementation of the alarm enables in the Configuration
+*		register 1 is such that alarms for the bit positions of 1 will
+*		be disabled and alarms for bit positions of 0 will be enabled.
+*		The enabled alarm outputs returned by this function is the
+*		negated value of the the data read from the Configuration
+*		Register 1.
+*
+*****************************************************************************/
+u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the status of alarm output enables from the Configuration
+	 * Register 1.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+			XADCPS_CFR1_OFFSET) & XADCPS_CFR1_ALM_ALL_MASK;
+	return (u16) (~RegValue & XADCPS_CFR1_ALM_ALL_MASK);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified calibration in the Configuration
+* Register 1 :
+*
+* - XADCPS_CFR1_CAL_ADC_OFFSET_MASK : Calibration 0 -ADC offset correction
+* - XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK : Calibration 1 -ADC gain and offset
+*						correction
+* - XADCPS_CFR1_CAL_PS_OFFSET_MASK : Calibration 2 -Power Supply sensor
+*					offset correction
+* - XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK : Calibration 3 -Power Supply sensor
+*						gain and offset correction
+* - XADCPS_CFR1_CAL_DISABLE_MASK : No Calibration
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Calibration is the Calibration to be applied.
+*		Use XADCPS_CFR1_CAL*_* bits defined in xadcps_hw.h.
+*		Multiple calibrations can be enabled at a time by oring the
+*		XADCPS_CFR1_CAL_ADC_* and XADCPS_CFR1_CAL_PS_* bits.
+*		Calibration can be disabled by specifying
+		XADCPS_CFR1_CAL_DISABLE_MASK;
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(((Calibration >= XADCPS_CFR1_CAL_ADC_OFFSET_MASK) &&
+			(Calibration <= XADCPS_CFR1_CAL_VALID_MASK)) ||
+			(Calibration == XADCPS_CFR1_CAL_DISABLE_MASK));
+
+	/*
+	 * Set the specified calibration in the Configuration Register 1.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR1_OFFSET);
+
+	RegValue &= (~ XADCPS_CFR1_CAL_VALID_MASK);
+	RegValue |= (Calibration & XADCPS_CFR1_CAL_VALID_MASK);
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
+				RegValue);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function reads the value of the calibration enables from the
+* Configuration Register 1.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	The value of the calibration enables in the Configuration
+*		Register 1 :
+*		- XADCPS_CFR1_CAL_ADC_OFFSET_MASK : ADC offset correction
+*		- XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK : ADC gain and offset
+*				correction
+*		- XADCPS_CFR1_CAL_PS_OFFSET_MASK : Power Supply sensor offset
+*				correction
+*		- XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK : Power Supply sensor
+*				gain and offset correction
+*		- XADCPS_CFR1_CAL_DISABLE_MASK : No Calibration
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the calibration enables from the Configuration Register 1.
+	 */
+	return (u16) XAdcPs_ReadInternalReg(InstancePtr,
+			XADCPS_CFR1_OFFSET) & XADCPS_CFR1_CAL_VALID_MASK;
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the specified Channel Sequencer Mode in the Configuration
+* Register 1 :
+*		- Default safe mode (XADCPS_SEQ_MODE_SAFE)
+*		- One pass through sequence (XADCPS_SEQ_MODE_ONEPASS)
+*		- Continuous channel sequencing (XADCPS_SEQ_MODE_CONTINPASS)
+*		- Single Channel/Sequencer off (XADCPS_SEQ_MODE_SINGCHAN)
+*		- Simulataneous sampling mode (XADCPS_SEQ_MODE_SIMUL_SAMPLING)
+*		- Independent mode (XADCPS_SEQ_MODE_INDEPENDENT)
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	SequencerMode is the sequencer mode to be set.
+*		Use XADCPS_SEQ_MODE_* bits defined in xadcps.h.
+* @return	None.
+*
+* @note		Only one of the modes can be enabled at a time. Please
+*		read the Spec of the XADC for further information about the
+*		sequencer modes.
+*
+*
+*****************************************************************************/
+void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((SequencerMode <= XADCPS_SEQ_MODE_SIMUL_SAMPLING) ||
+			(SequencerMode == XADCPS_SEQ_MODE_INDEPENDENT));
+
+	/*
+	 * Set the specified sequencer mode in the Configuration Register 1.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR1_OFFSET);
+	RegValue &= (~ XADCPS_CFR1_SEQ_VALID_MASK);
+	RegValue |= ((SequencerMode  << XADCPS_CFR1_SEQ_SHIFT) &
+					XADCPS_CFR1_SEQ_VALID_MASK);
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
+				RegValue);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the channel sequencer mode from the Configuration
+* Register 1.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	The channel sequencer mode :
+*		- XADCPS_SEQ_MODE_SAFE : Default safe mode
+*		- XADCPS_SEQ_MODE_ONEPASS : One pass through sequence
+*		- XADCPS_SEQ_MODE_CONTINPASS : Continuous channel sequencing
+*		- XADCPS_SEQ_MODE_SINGCHAN : Single channel/Sequencer off
+*		- XADCPS_SEQ_MODE_SIMUL_SAMPLING : Simulataneous sampling mode
+*		- XADCPS_SEQ_MODE_INDEPENDENT : Independent mode
+*
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the channel sequencer mode from the Configuration Register 1.
+	 */
+	return ((u8) ((XAdcPs_ReadInternalReg(InstancePtr,
+			XADCPS_CFR1_OFFSET) & XADCPS_CFR1_SEQ_VALID_MASK) >>
+			XADCPS_CFR1_SEQ_SHIFT));
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the frequency of the ADCCLK by configuring the DCLK to
+* ADCCLK ratio in the Configuration Register #2
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Divisor is clock divisor used to derive ADCCLK from DCLK.
+*		Valid values of the divisor are
+*		 - 0 to 255. Values 0, 1, 2 are all mapped to 2.
+*		Refer to the device specification for more details
+*
+* @return	None.
+*
+* @note		- The ADCCLK is an internal clock used by the ADC and is
+*		  synchronized to the DCLK clock. The ADCCLK is equal to DCLK
+*		  divided by the user selection in the Configuration Register 2.
+*		- There is no Assert on the minimum value of the Divisor.
+*
+*****************************************************************************/
+void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Write the divisor value into the Configuration Register #2.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR2_OFFSET,
+			  Divisor << XADCPS_CFR2_CD_SHIFT);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function gets the ADCCLK divisor from the Configuration Register 2.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	The divisor read from the Configuration Register 2.
+*
+* @note		The ADCCLK is an internal clock used by the ADC and is
+*		synchronized to the DCLK clock. The ADCCLK is equal to DCLK
+*		divided by the user selection in the Configuration Register 2.
+*
+*****************************************************************************/
+u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr)
+{
+	u16 Divisor;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the divisor value from the Configuration Register 2.
+	 */
+	Divisor = (u16) XAdcPs_ReadInternalReg(InstancePtr,
+					 XADCPS_CFR2_OFFSET);
+
+	return (u8) (Divisor >> XADCPS_CFR2_CD_SHIFT);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified channels in the ADC Channel Selection
+* Sequencer Registers. The sequencer must be disabled before writing to these
+* regsiters.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	ChEnableMask is the bit mask of all the channels to be enabled.
+*		Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the Channel
+*		numbers. Bit masks of 1 will be enabled and bit mask of 0 will
+*		be disabled.
+*		The ChEnableMask is a 32 bit mask that is written to the two
+*		16 bit ADC Channel Selection Sequencer Registers.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the ADC Channel Selection Sequencer Registers.
+*		- XST_FAILURE if the channel sequencer is enabled.
+*
+* @note		None
+*
+*****************************************************************************/
+int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The sequencer must be disabled for writing any of these registers
+	 * Return XST_FAILURE if the channel sequencer is enabled.
+	 */
+	if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Enable the specified channels in the ADC Channel Selection Sequencer
+	 * Registers.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ00_OFFSET,
+				(ChEnableMask & XADCPS_SEQ00_CH_VALID_MASK));
+
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ01_OFFSET,
+				(ChEnableMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+				XADCPS_SEQ01_CH_VALID_MASK);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the channel enable bits status from the ADC Channel
+* Selection Sequencer Registers.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	Gets the channel enable bits. Use XADCPS_SEQ_CH__* defined in
+*		xadcps_hw.h to interpret the Channel numbers. Bit masks of 1
+*		are the channels that are enabled and bit mask of 0 are
+*		the channels that are disabled.
+*
+* @return	None
+*
+* @note		None
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr)
+{
+	u32 RegValEnable;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 *  Read the channel enable bits for all the channels from the ADC
+	 *  Channel Selection Register.
+	 */
+	RegValEnable = XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ00_OFFSET) &
+				XADCPS_SEQ00_CH_VALID_MASK;
+	RegValEnable |= (XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ01_OFFSET) &
+				XADCPS_SEQ01_CH_VALID_MASK) <<
+				XADCPS_SEQ_CH_AUX_SHIFT;
+
+
+	return RegValEnable;
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the averaging for the specified channels in the ADC
+* Channel Averaging Enable Sequencer Registers. The sequencer must be disabled
+* before writing to these regsiters.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	AvgEnableChMask is the bit mask of all the channels for which
+*		averaging is to be enabled. Use XADCPS_SEQ_CH__* defined in
+*		xadcps_hw.h to specify the Channel numbers. Averaging will be
+*		enabled for bit masks of 1 and disabled for bit mask of 0.
+*		The AvgEnableChMask is a 32 bit mask that is written to the two
+*		16 bit ADC Channel Averaging Enable Sequencer Registers.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the ADC Channel Averaging Enables Sequencer Registers.
+*		- XST_FAILURE if the channel sequencer is enabled.
+*
+* @note		None
+*
+*****************************************************************************/
+int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The sequencer must be disabled for writing any of these registers
+	 * Return XST_FAILURE if the channel sequencer is enabled.
+	 */
+	if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Enable/disable the averaging for the specified channels in the
+	 * ADC Channel Averaging Enables Sequencer Registers.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ02_OFFSET,
+				(AvgEnableChMask & XADCPS_SEQ02_CH_VALID_MASK));
+
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ03_OFFSET,
+				(AvgEnableChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+				XADCPS_SEQ03_CH_VALID_MASK);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the channels for which the averaging has been enabled
+* in the ADC Channel Averaging Enables Sequencer Registers.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @returns 	The status of averaging (enabled/disabled) for all the channels.
+*		Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to interpret the
+*		Channel numbers. Bit masks of 1 are the channels for which
+*		averaging is enabled and bit mask of 0 are the channels for
+*		averaging is disabled
+*
+* @note		None
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr)
+{
+	u32 RegValAvg;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the averaging enable status for all the channels from the
+	 * ADC Channel Averaging Enables Sequencer Registers.
+	 */
+	RegValAvg = XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ02_OFFSET) & XADCPS_SEQ02_CH_VALID_MASK;
+	RegValAvg |= (XAdcPs_ReadInternalReg(InstancePtr,
+			XADCPS_SEQ03_OFFSET) & XADCPS_SEQ03_CH_VALID_MASK) <<
+			XADCPS_SEQ_CH_AUX_SHIFT;
+
+	return RegValAvg;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Analog input mode for the specified channels in the ADC
+* Channel Analog-Input Mode Sequencer Registers. The sequencer must be disabled
+* before writing to these regsiters.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	InputModeChMask is the bit mask of all the channels for which
+*		the input mode is differential mode. Use XADCPS_SEQ_CH__* defined
+*		in xadcps_hw.h to specify the channel numbers. Differential
+*		input mode will be set for bit masks of 1 and unipolar input
+*		mode for bit masks of 0.
+*		The InputModeChMask is a 32 bit mask that is written to the two
+*		16 bit ADC Channel Analog-Input Mode Sequencer Registers.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the ADC Channel Analog-Input Mode Sequencer Registers.
+*		- XST_FAILURE if the channel sequencer is enabled.
+*
+* @note		None
+*
+*****************************************************************************/
+int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The sequencer must be disabled for writing any of these registers
+	 * Return XST_FAILURE if the channel sequencer is enabled.
+	 */
+	if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Set the input mode for the specified channels in the ADC Channel
+	 * Analog-Input Mode Sequencer Registers.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ04_OFFSET,
+				(InputModeChMask & XADCPS_SEQ04_CH_VALID_MASK));
+
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ05_OFFSET,
+				(InputModeChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+				XADCPS_SEQ05_CH_VALID_MASK);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the Analog input mode for all the channels from
+* the ADC Channel Analog-Input Mode Sequencer Registers.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @returns 	The input mode for all the channels.
+*		Use XADCPS_SEQ_CH_* defined in xadcps_hw.h to interpret the
+*		Channel numbers. Bit masks of 1 are the channels for which
+*		input mode is differential and bit mask of 0 are the channels
+*		for which input mode is unipolar.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr)
+{
+	u32 InputMode;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 *  Get the input mode for all the channels from the ADC Channel
+	 * Analog-Input Mode Sequencer Registers.
+	 */
+	InputMode = XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ04_OFFSET) &
+				XADCPS_SEQ04_CH_VALID_MASK;
+	InputMode |= (XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ05_OFFSET) &
+				XADCPS_SEQ05_CH_VALID_MASK) <<
+				XADCPS_SEQ_CH_AUX_SHIFT;
+
+	return InputMode;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the number of Acquisition cycles in the ADC Channel
+* Acquisition Time Sequencer Registers. The sequencer must be disabled
+* before writing to these regsiters.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	AcqCyclesChMask is the bit mask of all the channels for which
+*		the number of acquisition cycles is to be extended.
+*		Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the Channel
+*		numbers. Acquisition cycles will be extended to 10 ADCCLK cycles
+*		for bit masks of 1 and will be the default 4 ADCCLK cycles for
+*		bit masks of 0.
+*		The AcqCyclesChMask is a 32 bit mask that is written to the two
+*		16 bit ADC Channel Acquisition Time Sequencer Registers.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the Channel Sequencer Registers.
+*		- XST_FAILURE if the channel sequencer is enabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The sequencer must be disabled for writing any of these registers
+	 * Return XST_FAILURE if the channel sequencer is enabled.
+	 */
+	if ((XAdcPs_GetSequencerMode(InstancePtr) !=
+			XADCPS_SEQ_MODE_SAFE)) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Set the Acquisition time for the specified channels in the
+	 * ADC Channel Acquisition Time Sequencer Registers.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ06_OFFSET,
+				(AcqCyclesChMask & XADCPS_SEQ06_CH_VALID_MASK));
+
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ07_OFFSET,
+				(AcqCyclesChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+				XADCPS_SEQ07_CH_VALID_MASK);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the status of acquisition from the ADC Channel Acquisition
+* Time Sequencer Registers.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @returns 	The acquisition time for all the channels.
+*		Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to interpret the
+*		Channel numbers. Bit masks of 1 are the channels for which
+*		acquisition cycles are extended and bit mask of 0 are the
+*		channels for which acquisition cycles are not extended.
+*
+* @note		None
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr)
+{
+	u32 RegValAcq;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Get the Acquisition cycles for the specified channels from the ADC
+	 * Channel Acquisition Time Sequencer Registers.
+	 */
+	RegValAcq = XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ06_OFFSET) &
+				XADCPS_SEQ06_CH_VALID_MASK;
+	RegValAcq |= (XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ07_OFFSET) &
+				XADCPS_SEQ07_CH_VALID_MASK) <<
+				XADCPS_SEQ_CH_AUX_SHIFT;
+
+	return RegValAcq;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sets the contents of the given Alarm Threshold Register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	AlarmThrReg is the index of an Alarm Threshold Register to
+*		be set. Use XADCPS_ATR_* constants defined in xadcps.h to
+*		specify the index.
+* @param	Value is the 16-bit threshold value to write into the register.
+*
+* @return	None.
+*
+* @note		Use XAdcPs_SetOverTemp() to set the Over Temperature upper
+*		threshold value.
+*
+*****************************************************************************/
+void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value)
+{
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(AlarmThrReg <= XADCPS_ATR_VCCPDRO_LOWER);
+
+	/*
+	 * Write the value into the specified Alarm Threshold Register.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_ATR_TEMP_UPPER_OFFSET +
+					AlarmThrReg,Value);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the contents of the specified Alarm Threshold Register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	AlarmThrReg is the index of an Alarm Threshold Register
+*		to be read. Use XADCPS_ATR_* constants defined in 	xadcps_hw.h
+*		to specify the index.
+*
+* @return	A 16-bit value representing the contents of the selected Alarm
+*		Threshold Register.
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg)
+{
+	u32 RegData;
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(AlarmThrReg <= XADCPS_ATR_VCCPDRO_LOWER);
+
+	/*
+	 * Read the specified Alarm Threshold Register and return
+	 * the value
+	 */
+	RegData = XAdcPs_ReadInternalReg(InstancePtr,
+				(XADCPS_ATR_TEMP_UPPER_OFFSET + AlarmThrReg));
+
+	return (u16) RegData;
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function enables programming of the powerdown temperature for the
+* OverTemp signal in the OT Powerdown register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr)
+{
+	u16 OtUpper;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the OT upper Alarm Threshold Register.
+	 */
+	OtUpper = XAdcPs_ReadInternalReg(InstancePtr,
+				   XADCPS_ATR_OT_UPPER_OFFSET);
+	OtUpper &= ~(XADCPS_ATR_OT_UPPER_ENB_MASK);
+
+	/*
+	 * Preserve the powerdown value and write OT enable value the into the
+	 * OT Upper Alarm Threshold Register.
+	 */
+	OtUpper |= XADCPS_ATR_OT_UPPER_ENB_VAL;
+	XAdcPs_WriteInternalReg(InstancePtr,
+			  XADCPS_ATR_OT_UPPER_OFFSET, OtUpper);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables programming of the powerdown temperature for the
+* OverTemp signal in the OT Powerdown register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+*
+*****************************************************************************/
+void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr)
+{
+	u16 OtUpper;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the OT Upper Alarm Threshold Register.
+	 */
+	OtUpper = XAdcPs_ReadInternalReg(InstancePtr,
+					 XADCPS_ATR_OT_UPPER_OFFSET);
+	OtUpper &= ~(XADCPS_ATR_OT_UPPER_ENB_MASK);
+
+	XAdcPs_WriteInternalReg(InstancePtr,
+			  XADCPS_ATR_OT_UPPER_OFFSET, OtUpper);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The function enables the Event mode or Continuous mode in the sequencer mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	IsEventMode is a boolean parameter that specifies continuous
+*		sampling (specify FALSE) or event driven sampling mode (specify
+*		TRUE) for the given channel.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
+
+	/*
+	 * Read the Configuration Register 0.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR0_OFFSET) &
+					(~XADCPS_CFR0_EC_MASK);
+
+	/*
+	 * Set the ADC mode.
+	 */
+	if (IsEventMode == TRUE) {
+		RegValue |= XADCPS_CFR0_EC_MASK;
+	} else {
+		RegValue &= ~XADCPS_CFR0_EC_MASK;
+	}
+
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+					RegValue);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function returns the sampling mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	The sampling mode
+*		- 0 specifies continuous sampling
+*		- 1 specifies event driven sampling mode
+*
+* @note		None.
+*
+*****************************************************************************/
+int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr)
+{
+	u32 Mode;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the sampling mode from the Configuration Register 0.
+	 */
+	Mode = XAdcPs_ReadInternalReg(InstancePtr,
+				   XADCPS_CFR0_OFFSET) &
+				   XADCPS_CFR0_EC_MASK;
+	if (Mode) {
+
+		return 1;
+	}
+
+	return (0);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function sets the External Mux mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param 	MuxMode specifies whether External Mux is used
+*		- FALSE specifies NO external MUX
+*		- TRUE specifies External Mux is used
+* @param	Channel specifies the channel to be used for the
+*		external Mux. Please read the Device Spec for which
+*		channels are valid for which mode.
+*
+* @return	None.
+*
+* @note		There is no Assert in this function for checking the channel
+*		number if the external Mux is used. The user should provide a
+*		valid channel number.
+*
+*****************************************************************************/
+void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((MuxMode == TRUE) || (MuxMode == FALSE));
+
+	/*
+	 * Read the Configuration Register 0.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR0_OFFSET) &
+					(~XADCPS_CFR0_MUX_MASK);
+	/*
+	 * Select the Mux mode and the channel to be used.
+	 */
+	if (MuxMode == TRUE) {
+		RegValue |= XADCPS_CFR0_MUX_MASK;
+		RegValue |= (Channel & XADCPS_CFR0_CHANNEL_MASK);
+
+	}
+
+	/*
+	 * Write the mux mode into the Configuration Register 0.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+					RegValue);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function sets the Power Down mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param 	Mode specifies the Power Down Mode
+*		- XADCPS_PD_MODE_NONE specifies NO Power Down (Both ADC A and
+*		ADC B are enabled)
+*		- XADCPS_PD_MODE_ADCB specfies the Power Down of ADC B
+*		- XADCPS_PD_MODE_XADC specifies the Power Down of
+*		both ADC A and ADC B.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Mode < XADCPS_PD_MODE_XADC);
+
+
+	/*
+	 * Read the Configuration Register 2.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR2_OFFSET) &
+					(~XADCPS_CFR2_PD_MASK);
+	/*
+	 * Select the Power Down mode.
+	 */
+	RegValue |= (Mode << XADCPS_CFR2_PD_SHIFT);
+
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR2_OFFSET,
+					RegValue);
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the Power Down mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	Mode specifies the Power Down Mode
+*		- XADCPS_PD_MODE_NONE specifies NO Power Down (Both ADC A and
+*		ADC B are enabled)
+*		- XADCPS_PD_MODE_ADCB specfies the Power Down of ADC B
+*		- XADCPS_PD_MODE_XADC specifies the Power Down of
+*		both ADC A and ADC B.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Power Down Mode.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR2_OFFSET) &
+					(~XADCPS_CFR2_PD_MASK);
+	/*
+	 * Return the Power Down mode.
+	 */
+	return (RegValue >> XADCPS_CFR2_PD_SHIFT);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for writing to XADC Registers using the command FIFO.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	RegOffset is the offset of the XADC register to be written.
+* @param	Data is the data to be written.
+*
+* @return	None.
+*
+* @note		None.
+*
+*
+*****************************************************************************/
+void XAdcPs_WriteInternalReg(XAdcPs *InstancePtr, u32 RegOffset, u32 Data)
+{
+	u32 RegData;
+
+	/*
+	 * Write the Data into the FIFO Register.
+	 */
+	RegData = XAdcPs_FormatWriteData(RegOffset, Data, TRUE);
+
+	XAdcPs_WriteFifo(InstancePtr, RegData);
+
+	/* Read the Read FIFO after any write since for each write
+	 * one location of Read FIFO gets updated
+	 */
+	XAdcPs_ReadFifo(InstancePtr);
+
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function is used for reading from the XADC Registers using the Data FIFO.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	RegOffset is the offset of the XADC register to be read.
+*
+* @return	Data read from the FIFO
+*
+* @note		None.
+*
+*
+*****************************************************************************/
+u32 XAdcPs_ReadInternalReg(XAdcPs *InstancePtr, u32 RegOffset)
+{
+
+	u32 RegData;
+
+	RegData = XAdcPs_FormatWriteData(RegOffset, 0x0, FALSE);
+
+	/* Read cmd to FIFO*/
+	XAdcPs_WriteFifo(InstancePtr, RegData);
+
+	/* Do a Dummy read */
+	RegData = XAdcPs_ReadFifo(InstancePtr);
+
+	/* Do a Dummy write to get the actual read */
+	XAdcPs_WriteFifo(InstancePtr, RegData);
+
+	/* Do the Actual read */
+	RegData = XAdcPs_ReadFifo(InstancePtr);
+
+	return RegData;
+
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.h
new file mode 100644
index 0000000000000000000000000000000000000000..9b6737d3729f8b34b97c66fc97d503aa7facc9da
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.h
@@ -0,0 +1,589 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps.h
+* @addtogroup xadcps_v2_2
+* @{
+* @details
+*
+* The XAdcPs driver supports the Xilinx XADC/ADC device.
+*
+* The XADC/ADC device has the following features:
+*	- 10-bit, 200-KSPS (kilo samples per second)
+*		Analog-to-Digital Converter (ADC)
+*	- Monitoring of on-chip supply voltages and temperature
+*	- 1 dedicated differential analog-input pair and
+*	  16 auxiliary differential analog-input pairs
+*	- Automatic alarms based on user defined limits for the on-chip
+*	  supply voltages and temperature
+*	- Automatic Channel Sequencer, programmable averaging, programmable
+*	  acquisition time for the external inputs, unipolar or differential
+*	  input selection for the external inputs
+*	- Inbuilt Calibration
+*	- Optional interrupt request generation
+*
+*
+* The user should refer to the hardware device specification for detailed
+* information about the device.
+*
+* This header file contains the prototypes of driver functions that can
+* be used to access the XADC/ADC device.
+*
+*
+* <b> XADC Channel Sequencer Modes </b>
+*
+* The  XADC Channel Sequencer supports the following operating modes:
+*
+*   - <b> Default </b>: This is the default mode after power up.
+*		In this mode of operation the XADC operates in
+*		a sequence mode, monitoring the on chip sensors:
+*		Temperature, VCCINT, and VCCAUX.
+*   - <b> One pass through sequence </b>: In this mode the XADC
+*		converts the channels enabled in the Sequencer Channel Enable
+*		registers for a single pass and then stops.
+*   - <b> Continuous cycling of sequence </b>: In this mode the XADC
+*		converts the channels enabled in the Sequencer Channel Enable
+*		registers continuously.
+*   - <b> Single channel mode</b>: In this mode the XADC Channel
+*		Sequencer is disabled and the XADC operates in a
+*		Single Channel Mode.
+*		The XADC can operate either in a Continuous or Event
+*		driven sampling mode in the single channel mode.
+*   - <b> Simultaneous Sampling Mode</b>: In this mode the XADC Channel
+*		Sequencer will automatically sequence through eight fixed pairs
+*		of auxiliary analog input channels for simulataneous conversion.
+*   - <b> Independent ADC mode</b>: In this mode the first ADC (A) is used to
+*		is used to implement a fixed monitoring mode similar to the
+*		default mode but the alarm fucntions ar eenabled.
+*		The second ADC (B) is available to be used with external analog
+*		input channels only.
+*
+* Read the XADC spec for more information about the sequencer modes.
+*
+* <b> Initialization and Configuration </b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the XADC/ADC device.
+*
+* XAdcPs_CfgInitialize() API is used to initialize the XADC/ADC
+* device. The user needs to first call the XAdcPs_LookupConfig() API which
+* returns the Configuration structure pointer which is passed as a parameter to
+* the XAdcPs_CfgInitialize() API.
+*
+*
+* <b>Interrupts</b>
+*
+* The XADC/ADC device supports interrupt driven mode and the default
+* operation mode is polling mode.
+*
+* The interrupt mode is available only if hardware is configured to support
+* interrupts.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* device in interrupt mode.
+*
+*
+* <b> Virtual Memory </b>
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+*
+* <b> Threads </b>
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+*
+* <b> Asserts </b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+*
+* <b> Building the driver </b>
+*
+* The XAdcPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* <b> Limitations of the driver </b>
+*
+* XADC/ADC device can be accessed through the JTAG port and the PLB
+* interface. The driver implementation does not support the simultaneous access
+* of the device by both these interfaces. The user has to care of this situation
+* in the user application code.
+*
+* <br><br>
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI xadc driver
+* 1.01a bss    02/18/13	Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
+*			XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
+*			in xadcps.c to fix CR #693371
+* 1.03a bss    11/01/13 Modified xadcps_hw.h to use correct Register offsets
+*			CR#749687
+* 2.1   bss    08/05/14 Added declarations for XAdcPs_SetSequencerEvent,
+*			XAdcPs_GetSamplingMode, XAdcPs_SetMuxMode,
+*			XAdcPs_SetPowerdownMode and XAdcPs_GetPowerdownMode
+*			functions.
+*			Modified Assert for XAdcPs_SetSingleChParams in
+*			xadcps.c to fix CR #807563.
+* 2.2   bss    04/27/14 Modified to use correct Device Config base address in
+*						xadcps.c (CR#854437).
+*       ms     01/23/17 Added xil_printf statement in main function for all
+*                       examples to ensure that "Successfully ran" and "Failed"
+*                       strings are available in all examples. This is a fix
+*                       for CR-965028.
+*       ms     03/17/17 Added readme.txt file in examples folder for doxygen
+*                       generation.
+*
+*
+* </pre>
+*
+*****************************************************************************/
+#ifndef XADCPS_H /* Prevent circular inclusions */
+#define XADCPS_H /* by using protection macros  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xadcps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**
+ * @name Indexes for the different channels.
+ * @{
+ */
+#define XADCPS_CH_TEMP		0x0  /**< On Chip Temperature */
+#define XADCPS_CH_VCCINT	0x1  /**< VCCINT */
+#define XADCPS_CH_VCCAUX	0x2  /**< VCCAUX */
+#define XADCPS_CH_VPVN		0x3  /**< VP/VN Dedicated analog inputs */
+#define XADCPS_CH_VREFP		0x4  /**< VREFP */
+#define XADCPS_CH_VREFN		0x5  /**< VREFN */
+#define XADCPS_CH_VBRAM		0x6  /**< On-chip VBRAM Data Reg, 7 series */
+#define XADCPS_CH_SUPPLY_CALIB	0x07 /**< Supply Calib Data Reg */
+#define XADCPS_CH_ADC_CALIB	0x08 /**< ADC Offset Channel Reg */
+#define XADCPS_CH_GAINERR_CALIB 0x09 /**< Gain Error Channel Reg  */
+#define XADCPS_CH_VCCPINT	0x0D /**< On-chip PS VCCPINT Channel , Zynq */
+#define XADCPS_CH_VCCPAUX	0x0E /**< On-chip PS VCCPAUX Channel , Zynq */
+#define XADCPS_CH_VCCPDRO	0x0F /**< On-chip PS VCCPDRO Channel , Zynq */
+#define XADCPS_CH_AUX_MIN	 16 /**< Channel number for 1st Aux Channel */
+#define XADCPS_CH_AUX_MAX	 31 /**< Channel number for Last Aux channel */
+
+/*@}*/
+
+
+/**
+ * @name Indexes for reading the Calibration Coefficient Data.
+ * @{
+ */
+#define XADCPS_CALIB_SUPPLY_COEFF     0 /**< Supply Offset Calib Coefficient */
+#define XADCPS_CALIB_ADC_COEFF        1 /**< ADC Offset Calib Coefficient */
+#define XADCPS_CALIB_GAIN_ERROR_COEFF 2 /**< Gain Error Calib Coefficient*/
+/*@}*/
+
+
+/**
+ * @name Indexes for reading the Minimum/Maximum Measurement Data.
+ * @{
+ */
+#define XADCPS_MAX_TEMP		0 /**< Maximum Temperature Data */
+#define XADCPS_MAX_VCCINT	1 /**< Maximum VCCINT Data */
+#define XADCPS_MAX_VCCAUX	2 /**< Maximum VCCAUX Data */
+#define XADCPS_MAX_VBRAM	3 /**< Maximum VBRAM Data */
+#define XADCPS_MIN_TEMP		4 /**< Minimum Temperature Data */
+#define XADCPS_MIN_VCCINT	5 /**< Minimum VCCINT Data */
+#define XADCPS_MIN_VCCAUX	6 /**< Minimum VCCAUX Data */
+#define XADCPS_MIN_VBRAM	7 /**< Minimum VBRAM Data */
+#define XADCPS_MAX_VCCPINT	8 /**< Maximum VCCPINT Register , Zynq */
+#define XADCPS_MAX_VCCPAUX	9 /**< Maximum VCCPAUX Register , Zynq */
+#define XADCPS_MAX_VCCPDRO	0xA /**< Maximum VCCPDRO Register , Zynq */
+#define XADCPS_MIN_VCCPINT	0xC /**< Minimum VCCPINT Register , Zynq */
+#define XADCPS_MIN_VCCPAUX	0xD /**< Minimum VCCPAUX Register , Zynq */
+#define XADCPS_MIN_VCCPDRO	0xE /**< Minimum VCCPDRO Register , Zynq */
+
+/*@}*/
+
+
+/**
+ * @name Alarm Threshold(Limit) Register (ATR) indexes.
+ * @{
+ */
+#define XADCPS_ATR_TEMP_UPPER	 0 /**< High user Temperature */
+#define XADCPS_ATR_VCCINT_UPPER  1 /**< VCCINT high voltage limit register */
+#define XADCPS_ATR_VCCAUX_UPPER  2 /**< VCCAUX high voltage limit register */
+#define XADCPS_ATR_OT_UPPER	 3 /**< VCCAUX high voltage limit register */
+#define XADCPS_ATR_TEMP_LOWER	 4 /**< Upper Over Temperature limit Reg */
+#define XADCPS_ATR_VCCINT_LOWER	 5 /**< VCCINT high voltage limit register */
+#define XADCPS_ATR_VCCAUX_LOWER	 6 /**< VCCAUX low voltage limit register  */
+#define XADCPS_ATR_OT_LOWER	 7 /**< Lower Over Temperature limit */
+#define XADCPS_ATR_VBRAM_UPPER_  8 /**< VRBAM Upper Alarm Reg, 7 Series */
+#define XADCPS_ATR_VCCPINT_UPPER 9 /**< VCCPINT Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VCCPAUX_UPPER 0xA /**< VCCPAUX Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VCCPDRO_UPPER 0xB /**< VCCPDRO Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VBRAM_LOWER	 0xC /**< VRBAM Lower Alarm Reg, 7 Series */
+#define XADCPS_ATR_VCCPINT_LOWER 0xD /**< VCCPINT Lower Alarm Reg , Zynq */
+#define XADCPS_ATR_VCCPAUX_LOWER 0xE /**< VCCPAUX Lower Alarm Reg , Zynq */
+#define XADCPS_ATR_VCCPDRO_LOWER 0xF /**< VCCPDRO Lower Alarm Reg , Zynq */
+
+/*@}*/
+
+
+/**
+ * @name Averaging to be done for the channels.
+ * @{
+ */
+#define XADCPS_AVG_0_SAMPLES	0  /**< No Averaging */
+#define XADCPS_AVG_16_SAMPLES	1  /**< Average 16 samples */
+#define XADCPS_AVG_64_SAMPLES	2  /**< Average 64 samples */
+#define XADCPS_AVG_256_SAMPLES	3  /**< Average 256 samples */
+
+/*@}*/
+
+
+/**
+ * @name Channel Sequencer Modes of operation
+ * @{
+ */
+#define XADCPS_SEQ_MODE_SAFE		0  /**< Default Safe Mode */
+#define XADCPS_SEQ_MODE_ONEPASS		1  /**< Onepass through Sequencer */
+#define XADCPS_SEQ_MODE_CONTINPASS	2  /**< Continuous Cycling Sequencer */
+#define XADCPS_SEQ_MODE_SINGCHAN	3  /**< Single channel -No Sequencing */
+#define XADCPS_SEQ_MODE_SIMUL_SAMPLING	4  /**< Simultaneous sampling */
+#define XADCPS_SEQ_MODE_INDEPENDENT	8  /**< Independent mode */
+
+/*@}*/
+
+
+
+/**
+ * @name Power Down Modes
+ * @{
+ */
+#define XADCPS_PD_MODE_NONE		0  /**< No Power Down  */
+#define XADCPS_PD_MODE_ADCB		1  /**< Power Down ADC B */
+#define XADCPS_PD_MODE_XADC		2  /**< Power Down ADC A and ADC B */
+/*@}*/
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the XADC/ADC
+ * device.
+ */
+typedef struct {
+	u16  DeviceId;		/**< Unique ID of device */
+	u32  BaseAddress;	/**< Device base address */
+} XAdcPs_Config;
+
+
+/**
+ * The driver's instance data. The user is required to allocate a variable
+ * of this type for every XADC/ADC device in the system. A pointer to
+ * a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XAdcPs_Config Config;	/**< XAdcPs_Config of current device */
+	u32  IsReady;		/**< Device is initialized and ready  */
+
+} XAdcPs;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the XADC device is in Event Sampling mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+*		- TRUE if the device is in Event Sampling Mode.
+*		- FALSE if the device is in Continuous Sampling Mode.
+*
+* @note		C-Style signature:
+*		int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_IsEventSamplingModeSet(InstancePtr)			\
+	(((XAdcPs_ReadInternalReg(InstancePtr,	 			\
+			XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ?	\
+			TRUE : FALSE))
+
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the XADC device is in External Mux mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+*		- TRUE if the device is in External Mux Mode.
+*		- FALSE if the device is NOT in External Mux Mode.
+*
+* @note		C-Style signature:
+*		int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_IsExternalMuxModeSet(InstancePtr)			\
+	(((XAdcPs_ReadInternalReg(InstancePtr,	 			\
+			XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ?	\
+			TRUE : FALSE))
+
+/****************************************************************************/
+/**
+*
+* This macro converts XADC Raw Data to Temperature(centigrades).
+*
+* @param	AdcData is the Raw ADC Data from XADC.
+*
+* @return 	The Temperature in centigrades.
+*
+* @note		C-Style signature:
+*		float XAdcPs_RawToTemperature(u32 AdcData);
+*
+*****************************************************************************/
+#define XAdcPs_RawToTemperature(AdcData)				\
+	((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts XADC/ADC Raw Data to Voltage(volts).
+*
+* @param	AdcData is the XADC/ADC Raw Data.
+*
+* @return 	The Voltage in volts.
+*
+* @note		C-Style signature:
+*		float XAdcPs_RawToVoltage(u32 AdcData);
+*
+*****************************************************************************/
+#define XAdcPs_RawToVoltage(AdcData) 					\
+	((((float)(AdcData))* (3.0f))/65536.0f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts Temperature in centigrades to XADC/ADC Raw Data.
+*
+* @param	Temperature is the Temperature in centigrades to be
+*		converted to XADC/ADC Raw Data.
+*
+* @return 	The XADC/ADC Raw Data.
+*
+* @note		C-Style signature:
+*		int XAdcPs_TemperatureToRaw(float Temperature);
+*
+*****************************************************************************/
+#define XAdcPs_TemperatureToRaw(Temperature)				\
+	((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f))
+
+/****************************************************************************/
+/**
+*
+* This macro converts Voltage in Volts to XADC/ADC Raw Data.
+*
+* @param	Voltage is the Voltage in volts to be converted to
+*		XADC/ADC Raw Data.
+*
+* @return 	The XADC/ADC Raw Data.
+*
+* @note		C-Style signature:
+*		int XAdcPs_VoltageToRaw(float Voltage);
+*
+*****************************************************************************/
+#define XAdcPs_VoltageToRaw(Voltage)			 		\
+	((int)((Voltage)*65536.0f/3.0f))
+
+
+/****************************************************************************/
+/**
+*
+* This macro is used for writing to the XADC Registers using the
+* command FIFO.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data);
+*
+*****************************************************************************/
+#define XAdcPs_WriteFifo(InstancePtr, Data)				\
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,		\
+			  XADCPS_CMDFIFO_OFFSET, Data);
+
+
+/****************************************************************************/
+/**
+*
+* This macro is used for reading from the XADC Registers using the
+* data FIFO.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	Data read from the FIFO
+*
+* @note		C-Style signature:
+*		u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_ReadFifo(InstancePtr)				\
+	XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,	\
+			  XADCPS_RDFIFO_OFFSET);
+
+
+/************************** Function Prototypes *****************************/
+
+
+
+/**
+ * Functions in xadcps_sinit.c
+ */
+XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId);
+
+/**
+ * Functions in xadcps.c
+ */
+int XAdcPs_CfgInitialize(XAdcPs *InstancePtr,
+				XAdcPs_Config *ConfigPtr,
+				u32 EffectiveAddr);
+
+
+u32 XAdcPs_GetStatus(XAdcPs *InstancePtr);
+
+u32 XAdcPs_GetAlarmOutputStatus(XAdcPs *InstancePtr);
+
+void XAdcPs_StartAdcConversion(XAdcPs *InstancePtr);
+
+void XAdcPs_Reset(XAdcPs *InstancePtr);
+
+u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel);
+
+u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType);
+
+u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType);
+
+void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average);
+u8 XAdcPs_GetAvg(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
+				u8 Channel,
+				int IncreaseAcqCycles,
+				int IsEventMode,
+				int IsDifferentialMode);
+
+
+void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask);
+u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr);
+
+void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration);
+u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr);
+
+void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode);
+u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr);
+
+void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor);
+u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask);
+u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask);
+u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask);
+u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask);
+u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr);
+
+void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value);
+u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg);
+
+void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr);
+void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr);
+
+void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode);
+
+int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr);
+
+void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel);
+
+void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode);
+
+u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr);
+
+/**
+ * Functions in xadcps_selftest.c
+ */
+int XAdcPs_SelfTest(XAdcPs *InstancePtr);
+
+/**
+ * Functions in xadcps_intr.c
+ */
+void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask);
+void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask);
+u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr);
+
+u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr);
+void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* End of protection macro. */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c
new file mode 100644
index 0000000000000000000000000000000000000000..09c6b9d0651562382661a85718669f454814081b
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xadcps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XAdcPs_Config XAdcPs_ConfigTable[XPAR_XADCPS_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_XADC_0_DEVICE_ID,
+		XPAR_PS7_XADC_0_BASEADDR
+	}
+};
+
+
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_hw.h b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_hw.h
new file mode 100644
index 0000000000000000000000000000000000000000..55a47a440a6a9933952aa7d70ad73b5e198c689b
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_hw.h
@@ -0,0 +1,502 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps_hw.h
+* @addtogroup xadcps_v2_2
+* @{
+*
+* This header file contains identifiers and basic driver functions (or
+* macros) that can be used to access the XADC device through the Device
+* Config Interface of the Zynq.
+*
+*
+* Refer to the device specification for more information about this driver.
+*
+* @note	 None.
+*
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss    12/22/11 First release based on the XPS/AXI xadc driver
+* 1.03a bss    11/01/13 Modified macros to use correct Register offsets
+*			CR#749687
+*
+* </pre>
+*
+*****************************************************************************/
+#ifndef XADCPS_HW_H /* Prevent circular inclusions */
+#define XADCPS_HW_H /* by using protection macros  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**@name Register offsets of XADC in the Device Config
+ *
+ * The following constants provide access to each of the registers of the
+ * XADC device.
+ * @{
+ */
+
+#define XADCPS_CFG_OFFSET	 0x00 /**< Configuration Register */
+#define XADCPS_INT_STS_OFFSET	 0x04 /**< Interrupt Status Register */
+#define XADCPS_INT_MASK_OFFSET	 0x08 /**< Interrupt Mask Register */
+#define XADCPS_MSTS_OFFSET	 0x0C /**< Misc status register */
+#define XADCPS_CMDFIFO_OFFSET	 0x10 /**< Command FIFO Register */
+#define XADCPS_RDFIFO_OFFSET	 0x14 /**< Read FIFO Register */
+#define XADCPS_MCTL_OFFSET	 0x18 /**< Misc control register */
+
+/* @} */
+
+
+
+
+
+/** @name XADC Config Register Bit definitions
+  * @{
+ */
+#define XADCPS_CFG_ENABLE_MASK	 0x80000000 /**< Enable access from PS mask */
+#define XADCPS_CFG_CFIFOTH_MASK  0x00F00000 /**< Command FIFO Threshold mask */
+#define XADCPS_CFG_DFIFOTH_MASK  0x000F0000 /**< Data FIFO Threshold mask */
+#define XADCPS_CFG_WEDGE_MASK	 0x00002000 /**< Write Edge Mask */
+#define XADCPS_CFG_REDGE_MASK	 0x00001000 /**< Read Edge Mask */
+#define XADCPS_CFG_TCKRATE_MASK  0x00000300 /**< Clock freq control */
+#define XADCPS_CFG_IGAP_MASK	 0x0000001F /**< Idle Gap between
+						* successive commands */
+/* @} */
+
+
+/** @name XADC Interrupt Status/Mask Register Bit definitions
+  *
+  * The definitions are same for the Interrupt Status Register and
+  * Interrupt Mask Register. They are defined only once.
+  * @{
+ */
+#define XADCPS_INTX_ALL_MASK   	   0x000003FF /**< Alarm Signals Mask  */
+#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200 /**< CMD FIFO less than threshold */
+#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100 /**< Data FIFO greater than threshold */
+#define XADCPS_INTX_OT_MASK	   0x00000080 /**< Over temperature Alarm Status */
+#define XADCPS_INTX_ALM_ALL_MASK   0x0000007F /**< Alarm Signals Mask  */
+#define XADCPS_INTX_ALM6_MASK	   0x00000040 /**< Alarm 6 Mask  */
+#define XADCPS_INTX_ALM5_MASK	   0x00000020 /**< Alarm 5 Mask  */
+#define XADCPS_INTX_ALM4_MASK	   0x00000010 /**< Alarm 4 Mask  */
+#define XADCPS_INTX_ALM3_MASK	   0x00000008 /**< Alarm 3 Mask  */
+#define XADCPS_INTX_ALM2_MASK	   0x00000004 /**< Alarm 2 Mask  */
+#define XADCPS_INTX_ALM1_MASK	   0x00000002 /**< Alarm 1 Mask  */
+#define XADCPS_INTX_ALM0_MASK	   0x00000001 /**< Alarm 0 Mask  */
+
+/* @} */
+
+
+/** @name XADC Miscellaneous Register Bit definitions
+  * @{
+ */
+#define XADCPS_MSTS_CFIFO_LVL_MASK  0x000F0000 /**< Command FIFO Level mask */
+#define XADCPS_MSTS_DFIFO_LVL_MASK  0x0000F000 /**< Data FIFO Level Mask  */
+#define XADCPS_MSTS_CFIFOF_MASK     0x00000800 /**< Command FIFO Full Mask  */
+#define XADCPS_MSTS_CFIFOE_MASK     0x00000400 /**< Command FIFO Empty Mask  */
+#define XADCPS_MSTS_DFIFOF_MASK     0x00000200 /**< Data FIFO Full Mask  */
+#define XADCPS_MSTS_DFIFOE_MASK     0x00000100 /**< Data FIFO Empty Mask  */
+#define XADCPS_MSTS_OT_MASK	    0x00000080 /**< Over Temperature Mask */
+#define XADCPS_MSTS_ALM_MASK	    0x0000007F /**< Alarms Mask  */
+/* @} */
+
+
+/** @name XADC Miscellaneous Control Register Bit definitions
+  * @{
+ */
+#define XADCPS_MCTL_RESET_MASK      0x00000010 /**< Reset XADC */
+#define XADCPS_MCTL_FLUSH_MASK      0x00000001 /**< Flush the FIFOs */
+/* @} */
+
+
+/**@name Internal Register offsets of the XADC
+ *
+ * The following constants provide access to each of the internal registers of
+ * the XADC device.
+ * @{
+ */
+
+/*
+ * XADC Internal Channel Registers
+ */
+#define XADCPS_TEMP_OFFSET		  0x00 /**< On-chip Temperature Reg */
+#define XADCPS_VCCINT_OFFSET		  0x01 /**< On-chip VCCINT Data Reg */
+#define XADCPS_VCCAUX_OFFSET		  0x02 /**< On-chip VCCAUX Data Reg */
+#define XADCPS_VPVN_OFFSET		  0x03 /**< ADC out of VP/VN	   */
+#define XADCPS_VREFP_OFFSET		  0x04 /**< On-chip VREFP Data Reg */
+#define XADCPS_VREFN_OFFSET		  0x05 /**< On-chip VREFN Data Reg */
+#define XADCPS_VBRAM_OFFSET		  0x06 /**< On-chip VBRAM , 7 Series */
+#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET  0x08 /**< ADC A Supply Offset Reg */
+#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET  0x09 /**< ADC A Offset Data Reg */
+#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0A /**< ADC A Gain Error Reg  */
+#define XADCPS_VCCPINT_OFFSET		  0x0D /**< On-chip VCCPINT Reg, Zynq */
+#define XADCPS_VCCPAUX_OFFSET		  0x0E /**< On-chip VCCPAUX Reg, Zynq */
+#define XADCPS_VCCPDRO_OFFSET		  0x0F /**< On-chip VCCPDRO Reg, Zynq */
+
+/*
+ * XADC External Channel Registers
+ */
+#define XADCPS_AUX00_OFFSET	0x10 /**< ADC out of VAUXP0/VAUXN0 */
+#define XADCPS_AUX01_OFFSET	0x11 /**< ADC out of VAUXP1/VAUXN1 */
+#define XADCPS_AUX02_OFFSET	0x12 /**< ADC out of VAUXP2/VAUXN2 */
+#define XADCPS_AUX03_OFFSET	0x13 /**< ADC out of VAUXP3/VAUXN3 */
+#define XADCPS_AUX04_OFFSET	0x14 /**< ADC out of VAUXP4/VAUXN4 */
+#define XADCPS_AUX05_OFFSET	0x15 /**< ADC out of VAUXP5/VAUXN5 */
+#define XADCPS_AUX06_OFFSET	0x16 /**< ADC out of VAUXP6/VAUXN6 */
+#define XADCPS_AUX07_OFFSET	0x17 /**< ADC out of VAUXP7/VAUXN7 */
+#define XADCPS_AUX08_OFFSET	0x18 /**< ADC out of VAUXP8/VAUXN8 */
+#define XADCPS_AUX09_OFFSET	0x19 /**< ADC out of VAUXP9/VAUXN9 */
+#define XADCPS_AUX10_OFFSET	0x1A /**< ADC out of VAUXP10/VAUXN10 */
+#define XADCPS_AUX11_OFFSET	0x1B /**< ADC out of VAUXP11/VAUXN11 */
+#define XADCPS_AUX12_OFFSET	0x1C /**< ADC out of VAUXP12/VAUXN12 */
+#define XADCPS_AUX13_OFFSET	0x1D /**< ADC out of VAUXP13/VAUXN13 */
+#define XADCPS_AUX14_OFFSET	0x1E /**< ADC out of VAUXP14/VAUXN14 */
+#define XADCPS_AUX15_OFFSET	0x1F /**< ADC out of VAUXP15/VAUXN15 */
+
+/*
+ * XADC Registers for Maximum/Minimum data captured for the
+ * on chip Temperature/VCCINT/VCCAUX data.
+ */
+#define XADCPS_MAX_TEMP_OFFSET		0x20 /**< Max Temperature Reg */
+#define XADCPS_MAX_VCCINT_OFFSET	0x21 /**< Max VCCINT Register */
+#define XADCPS_MAX_VCCAUX_OFFSET	0x22 /**< Max VCCAUX Register */
+#define XADCPS_MAX_VCCBRAM_OFFSET	0x23 /**< Max BRAM Register, 7 series */
+#define XADCPS_MIN_TEMP_OFFSET		0x24 /**< Min Temperature Reg */
+#define XADCPS_MIN_VCCINT_OFFSET	0x25 /**< Min VCCINT Register */
+#define XADCPS_MIN_VCCAUX_OFFSET	0x26 /**< Min VCCAUX Register */
+#define XADCPS_MIN_VCCBRAM_OFFSET	0x27 /**< Min BRAM Register, 7 series */
+#define XADCPS_MAX_VCCPINT_OFFSET	0x28 /**< Max VCCPINT Register, Zynq */
+#define XADCPS_MAX_VCCPAUX_OFFSET	0x29 /**< Max VCCPAUX Register, Zynq */
+#define XADCPS_MAX_VCCPDRO_OFFSET	0x2A /**< Max VCCPDRO Register, Zynq */
+#define XADCPS_MIN_VCCPINT_OFFSET	0x2C /**< Min VCCPINT Register, Zynq */
+#define XADCPS_MIN_VCCPAUX_OFFSET	0x2D /**< Min VCCPAUX Register, Zynq */
+#define XADCPS_MIN_VCCPDRO_OFFSET	0x2E /**< Min VCCPDRO Register,Zynq */
+ /* Undefined 0x2F to 0x3E */
+#define XADCPS_FLAG_OFFSET		0x3F /**< Flag Register */
+
+/*
+ * XADC Configuration Registers
+ */
+#define XADCPS_CFR0_OFFSET	0x40	/**< Configuration Register 0 */
+#define XADCPS_CFR1_OFFSET	0x41	/**< Configuration Register 1 */
+#define XADCPS_CFR2_OFFSET	0x42	/**< Configuration Register 2 */
+
+/* Test Registers 0x43 to 0x47 */
+
+/*
+ * XADC Sequence Registers
+ */
+#define XADCPS_SEQ00_OFFSET	0x48 /**< Seq Reg 00 Adc Channel Selection */
+#define XADCPS_SEQ01_OFFSET	0x49 /**< Seq Reg 01 Adc Channel Selection */
+#define XADCPS_SEQ02_OFFSET	0x4A /**< Seq Reg 02 Adc Average Enable */
+#define XADCPS_SEQ03_OFFSET	0x4B /**< Seq Reg 03 Adc Average Enable */
+#define XADCPS_SEQ04_OFFSET	0x4C /**< Seq Reg 04 Adc Input Mode Select */
+#define XADCPS_SEQ05_OFFSET	0x4D /**< Seq Reg 05 Adc Input Mode Select */
+#define XADCPS_SEQ06_OFFSET	0x4E /**< Seq Reg 06 Adc Acquisition Select */
+#define XADCPS_SEQ07_OFFSET	0x4F /**< Seq Reg 07 Adc Acquisition Select */
+
+/*
+ * XADC Alarm Threshold/Limit Registers (ATR)
+ */
+#define XADCPS_ATR_TEMP_UPPER_OFFSET	0x50 /**< Temp Upper Alarm Register */
+#define XADCPS_ATR_VCCINT_UPPER_OFFSET	0x51 /**< VCCINT Upper Alarm Reg */
+#define XADCPS_ATR_VCCAUX_UPPER_OFFSET	0x52 /**< VCCAUX Upper Alarm Reg */
+#define XADCPS_ATR_OT_UPPER_OFFSET	0x53 /**< Over Temp Upper Alarm Reg */
+#define XADCPS_ATR_TEMP_LOWER_OFFSET	0x54 /**< Temp Lower Alarm Register */
+#define XADCPS_ATR_VCCINT_LOWER_OFFSET	0x55 /**< VCCINT Lower Alarm Reg */
+#define XADCPS_ATR_VCCAUX_LOWER_OFFSET	0x56 /**< VCCAUX Lower Alarm Reg */
+#define XADCPS_ATR_OT_LOWER_OFFSET	0x57 /**< Over Temp Lower Alarm Reg */
+#define XADCPS_ATR_VBRAM_UPPER_OFFSET	0x58 /**< VBRAM Upper Alarm, 7 series */
+#define XADCPS_ATR_VCCPINT_UPPER_OFFSET	0x59 /**< VCCPINT Upper Alarm, Zynq */
+#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET	0x5A /**< VCCPAUX Upper Alarm, Zynq */
+#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET	0x5B /**< VCCPDRO Upper Alarm, Zynq */
+#define XADCPS_ATR_VBRAM_LOWER_OFFSET	0x5C /**< VRBAM Lower Alarm, 7 Series */
+#define XADCPS_ATR_VCCPINT_LOWER_OFFSET	0x5D /**< VCCPINT Lower Alarm, Zynq */
+#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET	0x5E /**< VCCPAUX Lower Alarm, Zynq */
+#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET	0x5F /**< VCCPDRO Lower Alarm, Zynq */
+
+/* Undefined 0x60 to 0x7F */
+
+/*@}*/
+
+
+
+/**
+ * @name Configuration Register 0 (CFR0) mask(s)
+ * @{
+ */
+#define XADCPS_CFR0_CAL_AVG_MASK	0x8000 /**< Averaging enable Mask */
+#define XADCPS_CFR0_AVG_VALID_MASK	0x3000 /**< Averaging bit Mask */
+#define XADCPS_CFR0_AVG1_MASK		0x0000 /**< No Averaging */
+#define XADCPS_CFR0_AVG16_MASK		0x1000 /**< Average 16 samples */
+#define XADCPS_CFR0_AVG64_MASK	 	0x2000 /**< Average 64 samples */
+#define XADCPS_CFR0_AVG256_MASK 	0x3000 /**< Average 256 samples */
+#define XADCPS_CFR0_AVG_SHIFT	 	12     /**< Averaging bits shift */
+#define XADCPS_CFR0_MUX_MASK	 	0x0800 /**< External Mask Enable */
+#define XADCPS_CFR0_DU_MASK	 	0x0400 /**< Bipolar/Unipolar mode */
+#define XADCPS_CFR0_EC_MASK	 	0x0200 /**< Event driven/
+						 *  Continuous mode selection
+						 */
+#define XADCPS_CFR0_ACQ_MASK	 	0x0100 /**< Add acquisition by 6 ADCCLK */
+#define XADCPS_CFR0_CHANNEL_MASK	0x001F /**< Channel number bit Mask */
+
+/*@}*/
+
+/**
+ * @name Configuration Register 1 (CFR1) mask(s)
+ * @{
+ */
+#define XADCPS_CFR1_SEQ_VALID_MASK	  0xF000 /**< Sequence bit Mask */
+#define XADCPS_CFR1_SEQ_SAFEMODE_MASK	  0x0000 /**< Default Safe Mode */
+#define XADCPS_CFR1_SEQ_ONEPASS_MASK	  0x1000 /**< Onepass through Seq */
+#define XADCPS_CFR1_SEQ_CONTINPASS_MASK	     0x2000 /**< Continuous Cycling Seq */
+#define XADCPS_CFR1_SEQ_SINGCHAN_MASK	     0x3000 /**< Single channel - No Seq */
+#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK  0x4000 /**< Simulataneous Sampling Mask */
+#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK  0x8000 /**< Independent Mode */
+#define XADCPS_CFR1_SEQ_SHIFT		  12     /**< Sequence bit shift */
+#define XADCPS_CFR1_ALM_VCCPDRO_MASK	  0x0800 /**< Alm 6 - VCCPDRO, Zynq  */
+#define XADCPS_CFR1_ALM_VCCPAUX_MASK	  0x0400 /**< Alm 5 - VCCPAUX, Zynq */
+#define XADCPS_CFR1_ALM_VCCPINT_MASK	  0x0200 /**< Alm 4 - VCCPINT, Zynq */
+#define XADCPS_CFR1_ALM_VBRAM_MASK	  0x0100 /**< Alm 3 - VBRAM, 7 series */
+#define XADCPS_CFR1_CAL_VALID_MASK	  0x00F0 /**< Valid Calibration Mask */
+#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK  0x0080 /**< Calibration 3 -Power
+							Supply Gain/Offset
+							Enable */
+#define XADCPS_CFR1_CAL_PS_OFFSET_MASK	  0x0040 /**< Calibration 2 -Power
+							Supply Offset Enable */
+#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x0020 /**< Calibration 1 -ADC Gain
+							Offset Enable */
+#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK	 0x0010 /**< Calibration 0 -ADC Offset
+							Enable */
+#define XADCPS_CFR1_CAL_DISABLE_MASK	0x0000 /**< No Calibration */
+#define XADCPS_CFR1_ALM_ALL_MASK	0x0F0F /**< Mask for all alarms */
+#define XADCPS_CFR1_ALM_VCCAUX_MASK	0x0008 /**< Alarm 2 - VCCAUX Enable */
+#define XADCPS_CFR1_ALM_VCCINT_MASK	0x0004 /**< Alarm 1 - VCCINT Enable */
+#define XADCPS_CFR1_ALM_TEMP_MASK	0x0002 /**< Alarm 0 - Temperature */
+#define XADCPS_CFR1_OT_MASK		0x0001 /**< Over Temperature Enable */
+
+/*@}*/
+
+/**
+ * @name Configuration Register 2 (CFR2) mask(s)
+ * @{
+ */
+#define XADCPS_CFR2_CD_VALID_MASK	0xFF00  /**<Clock Divisor bit Mask   */
+#define XADCPS_CFR2_CD_SHIFT		8	/**<Num of shift on division */
+#define XADCPS_CFR2_CD_MIN		8	/**<Minimum value of divisor */
+#define XADCPS_CFR2_CD_MAX		255	/**<Maximum value of divisor */
+
+#define XADCPS_CFR2_CD_MIN		8	/**<Minimum value of divisor */
+#define XADCPS_CFR2_PD_MASK		0x0030	/**<Power Down Mask */
+#define XADCPS_CFR2_PD_XADC_MASK	0x0030	/**<Power Down XADC Mask */
+#define XADCPS_CFR2_PD_ADC1_MASK	0x0020	/**<Power Down ADC1 Mask */
+#define XADCPS_CFR2_PD_SHIFT		4	/**<Power Down Shift */
+/*@}*/
+
+/**
+ * @name Sequence Register (SEQ) Bit Definitions
+ * @{
+ */
+#define XADCPS_SEQ_CH_CALIB	0x00000001 /**< ADC Calibration Channel */
+#define XADCPS_SEQ_CH_VCCPINT	0x00000020 /**< VCCPINT, Zynq Only */
+#define XADCPS_SEQ_CH_VCCPAUX	0x00000040 /**< VCCPAUX, Zynq Only */
+#define XADCPS_SEQ_CH_VCCPDRO	0x00000080 /**< VCCPDRO, Zynq Only */
+#define XADCPS_SEQ_CH_TEMP	0x00000100 /**< On Chip Temperature Channel */
+#define XADCPS_SEQ_CH_VCCINT	0x00000200 /**< VCCINT Channel */
+#define XADCPS_SEQ_CH_VCCAUX	0x00000400 /**< VCCAUX Channel */
+#define XADCPS_SEQ_CH_VPVN	0x00000800 /**< VP/VN analog inputs Channel */
+#define XADCPS_SEQ_CH_VREFP	0x00001000 /**< VREFP Channel */
+#define XADCPS_SEQ_CH_VREFN	0x00002000 /**< VREFN Channel */
+#define XADCPS_SEQ_CH_VBRAM	0x00004000 /**< VBRAM Channel, 7 series */
+#define XADCPS_SEQ_CH_AUX00	0x00010000 /**< 1st Aux Channel */
+#define XADCPS_SEQ_CH_AUX01	0x00020000 /**< 2nd Aux Channel */
+#define XADCPS_SEQ_CH_AUX02	0x00040000 /**< 3rd Aux Channel */
+#define XADCPS_SEQ_CH_AUX03	0x00080000 /**< 4th Aux Channel */
+#define XADCPS_SEQ_CH_AUX04	0x00100000 /**< 5th Aux Channel */
+#define XADCPS_SEQ_CH_AUX05	0x00200000 /**< 6th Aux Channel */
+#define XADCPS_SEQ_CH_AUX06	0x00400000 /**< 7th Aux Channel */
+#define XADCPS_SEQ_CH_AUX07	0x00800000 /**< 8th Aux Channel */
+#define XADCPS_SEQ_CH_AUX08	0x01000000 /**< 9th Aux Channel */
+#define XADCPS_SEQ_CH_AUX09	0x02000000 /**< 10th Aux Channel */
+#define XADCPS_SEQ_CH_AUX10	0x04000000 /**< 11th Aux Channel */
+#define XADCPS_SEQ_CH_AUX11	0x08000000 /**< 12th Aux Channel */
+#define XADCPS_SEQ_CH_AUX12	0x10000000 /**< 13th Aux Channel */
+#define XADCPS_SEQ_CH_AUX13	0x20000000 /**< 14th Aux Channel */
+#define XADCPS_SEQ_CH_AUX14	0x40000000 /**< 15th Aux Channel */
+#define XADCPS_SEQ_CH_AUX15	0x80000000 /**< 16th Aux Channel */
+
+#define XADCPS_SEQ00_CH_VALID_MASK  0x7FE1 /**< Mask for the valid channels */
+#define XADCPS_SEQ01_CH_VALID_MASK  0xFFFF /**< Mask for the valid channels */
+
+#define XADCPS_SEQ02_CH_VALID_MASK  0x7FE0 /**< Mask for the valid channels */
+#define XADCPS_SEQ03_CH_VALID_MASK  0xFFFF /**< Mask for the valid channels */
+
+#define XADCPS_SEQ04_CH_VALID_MASK  0x0800 /**< Mask for the valid channels */
+#define XADCPS_SEQ05_CH_VALID_MASK  0xFFFF /**< Mask for the valid channels */
+
+#define XADCPS_SEQ06_CH_VALID_MASK  0x0800 /**< Mask for the valid channels */
+#define XADCPS_SEQ07_CH_VALID_MASK  0xFFFF /**< Mask for the valid channels */
+
+
+#define XADCPS_SEQ_CH_AUX_SHIFT	16 /**< Shift for the Aux Channel */
+
+/*@}*/
+
+/**
+ * @name OT Upper Alarm Threshold Register Bit Definitions
+ * @{
+ */
+
+#define XADCPS_ATR_OT_UPPER_ENB_MASK	0x000F /**< Mask for OT enable */
+#define XADCPS_ATR_OT_UPPER_VAL_MASK	0xFFF0 /**< Mask for OT value */
+#define XADCPS_ATR_OT_UPPER_VAL_SHIFT	4      /**< Shift for OT value */
+#define XADCPS_ATR_OT_UPPER_ENB_VAL	0x0003 /**< Value for OT enable */
+#define XADCPS_ATR_OT_UPPER_VAL_MAX	0x0FFF /**< Max OT value */
+
+/*@}*/
+
+
+/**
+ * @name JTAG DRP Bit Definitions
+ * @{
+ */
+#define XADCPS_JTAG_DATA_MASK		0x0000FFFF /**< Mask for the Data */
+#define XADCPS_JTAG_ADDR_MASK		0x03FF0000 /**< Mask for the Addr */
+#define XADCPS_JTAG_ADDR_SHIFT		16	   /**< Shift for the Addr */
+#define XADCPS_JTAG_CMD_MASK		0x3C000000 /**< Mask for the Cmd */
+#define XADCPS_JTAG_CMD_WRITE_MASK	0x08000000 /**< Mask for CMD Write */
+#define XADCPS_JTAG_CMD_READ_MASK	0x04000000 /**< Mask for CMD Read */
+#define XADCPS_JTAG_CMD_SHIFT		26	   /**< Shift for the Cmd */
+
+/*@}*/
+
+/** @name Unlock Register Definitions
+  * @{
+ */
+ #define XADCPS_UNLK_OFFSET	 0x034 /**< Unlock Register */
+ #define XADCPS_UNLK_VALUE	 0x757BDF0D /**< Unlock Value */
+
+ /* @} */
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+*
+* Read a register of the XADC device. This macro provides register
+* access to all registers using the register offsets defined above.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset is the offset of the register to read.
+*
+* @return	The contents of the register.
+*
+* @note		C-style Signature:
+*		u32 XAdcPs_ReadReg(u32 BaseAddress, u32 RegOffset);
+*
+******************************************************************************/
+#define XAdcPs_ReadReg(BaseAddress, RegOffset) \
+			(Xil_In32((BaseAddress) + (RegOffset)))
+
+/*****************************************************************************/
+/**
+*
+* Write a register of the XADC device. This macro provides
+* register access to all registers using the register offsets defined above.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset is the offset of the register to write.
+* @param	Data is the value to write to the register.
+*
+* @return	None.
+*
+* @note 	C-style Signature:
+*		void XAdcPs_WriteReg(u32 BaseAddress,
+*					u32 RegOffset,u32 Data)
+*
+******************************************************************************/
+#define XAdcPs_WriteReg(BaseAddress, RegOffset, Data) \
+		(Xil_Out32((BaseAddress) + (RegOffset), (Data)))
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Formats the data to be written to the the XADC registers.
+*
+* @param	RegOffset is the offset of the Register
+* @param	Data is the data to be written to the Register if it is
+*		a write.
+* @param	ReadWrite specifies whether it is a Read or a Write.
+*		Use 0 for Read, 1 for Write.
+*
+* @return	None.
+*
+* @note 	C-style Signature:
+*		void XAdcPs_FormatWriteData(u32 RegOffset,
+*					     u16 Data, int ReadWrite)
+*
+******************************************************************************/
+#define XAdcPs_FormatWriteData(RegOffset, Data, ReadWrite) 	    \
+    ((ReadWrite ? XADCPS_JTAG_CMD_WRITE_MASK : XADCPS_JTAG_CMD_READ_MASK ) | \
+     ((RegOffset << XADCPS_JTAG_ADDR_SHIFT) & XADCPS_JTAG_ADDR_MASK) | 	     \
+     (Data & XADCPS_JTAG_DATA_MASK))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* End of protection macro. */
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_intr.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_intr.c
new file mode 100644
index 0000000000000000000000000000000000000000..70a8697476baa4936baa7cdc16e3c9ca7b466b94
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_intr.c
@@ -0,0 +1,250 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xadcps_intr.c
+* @addtogroup xadcps_v2_2
+* @{
+*
+* This file contains interrupt handling API functions of the XADC
+* device.
+*
+* The device must be configured at hardware build time to support interrupt
+* for all the functions in this file to work.
+*
+* Refer to xadcps.h header file and device specification for more information.
+*
+* @note
+*
+* Calling the interrupt functions without including the interrupt component will
+* result in asserts if asserts are enabled, and will result in a unpredictable
+* behavior if the asserts are not enabled.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI xadc driver
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xadcps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified interrupts in the device.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Mask is the bit-mask of the interrupts to be enabled.
+*		Bit positions of 1 will be enabled. Bit positions of 0 will
+*		keep the previous setting. This mask is formed by OR'ing
+*		XADCPS_INTX_* bits defined in xadcps_hw.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Disable the specified interrupts in the IPIER.
+	 */
+	RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XADCPS_INT_MASK_OFFSET);
+	RegValue &= ~(Mask & XADCPS_INTX_ALL_MASK);
+	XAdcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XADCPS_INT_MASK_OFFSET,
+				RegValue);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function disables the specified interrupts in the device.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Mask is the bit-mask of the interrupts to be disabled.
+*		Bit positions of 1 will be disabled. Bit positions of 0 will
+*		keep the previous setting. This mask is formed by OR'ing
+*		XADCPS_INTX_* bits defined in xadcps_hw.h.
+*
+* @return	None.
+*
+* @note		None
+*
+*****************************************************************************/
+void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Enable the specified interrupts in the IPIER.
+	 */
+	RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XADCPS_INT_MASK_OFFSET);
+	RegValue |= (Mask & XADCPS_INTX_ALL_MASK);
+	XAdcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XADCPS_INT_MASK_OFFSET,
+				RegValue);
+}
+/****************************************************************************/
+/**
+*
+* This function returns the enabled interrupts read from the Interrupt Mask
+* Register (IPIER). Use the XADCPS_IPIXR_* constants defined in xadcps_hw.h to
+* interpret the returned value.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	A 32-bit value representing the contents of the I.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Return the value read from the Interrupt Enable Register.
+	 */
+	return (~ XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XADCPS_INT_MASK_OFFSET) & XADCPS_INTX_ALL_MASK);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the interrupt status read from Interrupt Status
+* Register(IPISR). Use the XADCPS_IPIXR_* constants defined in xadcps_hw.h
+* to interpret the returned value.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	A 32-bit value representing the contents of the IPISR.
+*
+* @note		The device must be configured at hardware build time to include
+*		interrupt component for this function to work.
+*
+*****************************************************************************/
+u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Return the value read from the Interrupt Status register.
+	 */
+	return XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XADCPS_INT_STS_OFFSET) & XADCPS_INTX_ALL_MASK;
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears the specified interrupts in the Interrupt Status
+* Register (IPISR).
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Mask is the bit-mask of the interrupts to be cleared.
+*		Bit positions of 1 will be cleared. Bit positions of 0 will not
+* 		change the previous interrupt status. This mask is formed by
+* 		OR'ing XADCPS_IPIXR_* bits which are defined in xadcps_hw.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Clear the specified interrupts in the Interrupt Status register.
+	 */
+	RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XADCPS_INT_STS_OFFSET);
+	RegValue &= (Mask & XADCPS_INTX_ALL_MASK);
+	XAdcPs_WriteReg(InstancePtr->Config.BaseAddress, XADCPS_INT_STS_OFFSET,
+			  RegValue);
+
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_selftest.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_selftest.c
new file mode 100644
index 0000000000000000000000000000000000000000..7f171b416b5b576416d5d71f25ed4952fffcd0cf
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_selftest.c
@@ -0,0 +1,141 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xadcps_selftest.c
+* @addtogroup xadcps_v2_2
+* @{
+*
+* This file contains a diagnostic self test function for the XAdcPs driver.
+* The self test function does a simple read/write test of the Alarm Threshold
+* Register.
+*
+* See xadcps.h for more information.
+*
+* @note	None.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI xadc driver
+*
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xadcps.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constant defines the test value to be written
+ * to the Alarm Threshold Register
+ */
+#define XADCPS_ATR_TEST_VALUE 		0x55
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Run a self-test on the driver/device. The test
+*	- Resets the device,
+*	- Writes a value into the Alarm Threshold register and reads it back
+*	for comparison.
+*	- Resets the device again.
+*
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+*		- XST_SUCCESS if the value read from the Alarm Threshold
+*		register is the same as the value written.
+*		- XST_FAILURE Otherwise
+*
+* @note		This is a destructive test in that resets of the device are
+*		performed. Refer to the device specification for the
+*		device status after the reset operation.
+*
+******************************************************************************/
+int XAdcPs_SelfTest(XAdcPs *InstancePtr)
+{
+	int Status;
+	u32 RegValue;
+
+	/*
+	 * Assert the argument
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	/*
+	 * Reset the device to get it back to its default state
+	 */
+	XAdcPs_Reset(InstancePtr);
+
+	/*
+	 * Write a value into the Alarm Threshold registers, read it back, and
+	 * do the comparison
+	 */
+	XAdcPs_SetAlarmThreshold(InstancePtr, XADCPS_ATR_VCCINT_UPPER,
+				  XADCPS_ATR_TEST_VALUE);
+	RegValue = XAdcPs_GetAlarmThreshold(InstancePtr, XADCPS_ATR_VCCINT_UPPER);
+
+	if (RegValue == XADCPS_ATR_TEST_VALUE) {
+		Status = XST_SUCCESS;
+	} else {
+		Status = XST_FAILURE;
+	}
+
+	/*
+	 * Reset the device again to its default state.
+	 */
+	XAdcPs_Reset(InstancePtr);
+	/*
+	 * Return the test result.
+	 */
+	return Status;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_sinit.c b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_sinit.c
new file mode 100644
index 0000000000000000000000000000000000000000..5fb7cdeadfa46d0e590913dd89d81925ade784cf
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_sinit.c
@@ -0,0 +1,103 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xadcps_sinit.c
+* @addtogroup xadcps_v2_2
+* @{
+*
+* This file contains the implementation of the XAdcPs driver's static
+* initialization functionality.
+*
+* @note	None.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI XADC driver
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xadcps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XAdcPs_Config XAdcPs_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* This function looks up the device configuration based on the unique device ID.
+* The table XAdcPs_ConfigTable contains the configuration info for each device
+* in the system.
+*
+* @param	DeviceId contains the ID of the device for which the
+*		device configuration pointer is to be returned.
+*
+* @return
+*		- A pointer to the configuration found.
+*		- NULL if the specified device ID was not found.
+*
+* @note		None.
+*
+******************************************************************************/
+XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId)
+{
+	XAdcPs_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index=0; Index < 1; Index++) {
+		if (XAdcPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XAdcPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}
+/** @} */
diff --git a/quad/xsdk_workspace_vivado/standalone_bsp_0/system.mss b/quad/xsdk_workspace_vivado/standalone_bsp_0/system.mss
new file mode 100644
index 0000000000000000000000000000000000000000..5f6ae5d992764a487e78ee208676c820afcb4d59
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/standalone_bsp_0/system.mss
@@ -0,0 +1,315 @@
+
+ PARAMETER VERSION = 2.2.0
+
+
+BEGIN OS
+ PARAMETER OS_NAME = standalone
+ PARAMETER OS_VER = 6.2
+ PARAMETER PROC_INSTANCE = ps7_cortexa9_0
+ PARAMETER stdin = ps7_uart_0
+ PARAMETER stdout = ps7_uart_0
+END
+
+
+BEGIN PROCESSOR
+ PARAMETER DRIVER_NAME = cpu_cortexa9
+ PARAMETER DRIVER_VER = 2.4
+ PARAMETER HW_INSTANCE = ps7_cortexa9_0
+END
+
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = gpio
+ PARAMETER DRIVER_VER = 4.3
+ PARAMETER HW_INSTANCE = axi_gpio_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = gpio
+ PARAMETER DRIVER_VER = 4.3
+ PARAMETER HW_INSTANCE = axi_gpio_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_afi_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_afi_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_afi_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_afi_3
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = coresightps_dcc
+ PARAMETER DRIVER_VER = 1.4
+ PARAMETER HW_INSTANCE = ps7_coresight_comp_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = ddrps
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = ps7_ddr_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_ddrc_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = devcfg
+ PARAMETER DRIVER_VER = 3.4
+ PARAMETER HW_INSTANCE = ps7_dev_cfg_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = dmaps
+ PARAMETER DRIVER_VER = 2.3
+ PARAMETER HW_INSTANCE = ps7_dma_ns
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = dmaps
+ PARAMETER DRIVER_VER = 2.3
+ PARAMETER HW_INSTANCE = ps7_dma_s
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = emacps
+ PARAMETER DRIVER_VER = 3.4
+ PARAMETER HW_INSTANCE = ps7_ethernet_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_globaltimer_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = gpiops
+ PARAMETER DRIVER_VER = 3.2
+ PARAMETER HW_INSTANCE = ps7_gpio_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_gpv_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = iicps
+ PARAMETER DRIVER_VER = 3.5
+ PARAMETER HW_INSTANCE = ps7_i2c_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = iicps
+ PARAMETER DRIVER_VER = 3.5
+ PARAMETER HW_INSTANCE = ps7_i2c_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_intc_dist_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_iop_bus_config_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_l2cachec_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_ocmc_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_pl310_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_pmu_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = qspips
+ PARAMETER DRIVER_VER = 3.3
+ PARAMETER HW_INSTANCE = ps7_qspi_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_qspi_linear_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_ram_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_ram_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_scuc_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = scugic
+ PARAMETER DRIVER_VER = 3.6
+ PARAMETER HW_INSTANCE = ps7_scugic_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = scutimer
+ PARAMETER DRIVER_VER = 2.1
+ PARAMETER HW_INSTANCE = ps7_scutimer_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = scuwdt
+ PARAMETER DRIVER_VER = 2.1
+ PARAMETER HW_INSTANCE = ps7_scuwdt_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = sdps
+ PARAMETER DRIVER_VER = 3.2
+ PARAMETER HW_INSTANCE = ps7_sd_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_slcr_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = ttcps
+ PARAMETER DRIVER_VER = 3.3
+ PARAMETER HW_INSTANCE = ps7_ttc_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = uartps
+ PARAMETER DRIVER_VER = 3.4
+ PARAMETER HW_INSTANCE = ps7_uart_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = uartps
+ PARAMETER DRIVER_VER = 3.4
+ PARAMETER HW_INSTANCE = ps7_uart_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = usbps
+ PARAMETER DRIVER_VER = 2.4
+ PARAMETER HW_INSTANCE = ps7_usb_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = xadcps
+ PARAMETER DRIVER_VER = 2.2
+ PARAMETER HW_INSTANCE = ps7_xadc_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = pwm_recorder
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = pwm_recorder_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = pwm_recorder
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = pwm_recorder_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = pwm_recorder
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = pwm_recorder_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = pwm_recorder
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = pwm_recorder_3
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = pwm_recorder
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = pwm_recorder_4
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = pwm_recorder
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = pwm_recorder_5
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = pwm_signal_out
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = pwm_signal_out_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = pwm_signal_out
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = pwm_signal_out_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = pwm_signal_out
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = pwm_signal_out_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = pwm_signal_out
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = pwm_signal_out_3
+END
+
+
diff --git a/quad/xsdk_workspace_vivado/system_bsp/.cproject b/quad/xsdk_workspace_vivado/system_bsp/.cproject
new file mode 100644
index 0000000000000000000000000000000000000000..040b9d963e6c7eee804b0497c303bfdfbcf989bb
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/system_bsp/.cproject
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="org.eclipse.cdt.core.default.config.208777439">
+			<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.208777439" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
+				<externalSettings/>
+				<extensions/>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="refreshScope"/>
+	<storageModule moduleId="org.eclipse.cdt.core.pathentry"/>
+</cproject>
diff --git a/quad/xsdk_workspace_vivado/Test_bsp/.project b/quad/xsdk_workspace_vivado/system_bsp/.project
similarity index 98%
rename from quad/xsdk_workspace_vivado/Test_bsp/.project
rename to quad/xsdk_workspace_vivado/system_bsp/.project
index 57582df5748d0ffbf1a2f5ba5ee012ecf0d1a194..0c80fba076d8b445af6d49bb5e52b3ba4b413c54 100644
--- a/quad/xsdk_workspace_vivado/Test_bsp/.project
+++ b/quad/xsdk_workspace_vivado/system_bsp/.project
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <projectDescription>
-	<name>Test_bsp</name>
+	<name>system_bsp</name>
 	<comment>Created by SDK v2017.1</comment>
 	<projects>
 	</projects>
diff --git a/quad/xsdk_workspace_vivado/system_bsp/.sdkproject b/quad/xsdk_workspace_vivado/system_bsp/.sdkproject
new file mode 100644
index 0000000000000000000000000000000000000000..6e301ca60b93be481ba7ea99c4fba9bd211a98a7
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/system_bsp/.sdkproject
@@ -0,0 +1,4 @@
+THIRPARTY=false
+HW_PROJECT_REFERENCE=quad_wrapper_hw_platform_0
+PROCESSOR=ps7_cortexa9_0
+MSS_FILE=system.mss
diff --git a/quad/xsdk_workspace_vivado/system_bsp/Makefile b/quad/xsdk_workspace_vivado/system_bsp/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..1ace345f6a38ecafefb9629dda2e2ad8a9fc5de7
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/system_bsp/Makefile
@@ -0,0 +1,35 @@
+# Makefile generated by Xilinx.
+
+PROCESSOR = ps7_cortexa9_0
+LIBRARIES = ${PROCESSOR}/lib/libxil.a
+BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile)
+SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES))
+
+ifneq (,$(findstring win,$(RDI_PLATFORM)))
+ SHELL = CMD
+endif
+
+all: libs
+	@echo 'Finished building libraries'
+
+include: $(addsuffix /make.include,$(SUBDIRS))
+
+libs: $(addsuffix /make.libs,$(SUBDIRS))
+
+clean: $(addsuffix /make.clean,$(SUBDIRS))
+
+$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a
+	cp -f $< $@
+
+%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,)
+	@echo "Running Make include in $(subst /make.include,,$@)"
+	$(MAKE) -C $(subst /make.include,,$@) -s include  "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -Wall -Wextra"
+
+%/make.libs: include
+	@echo "Running Make libs in $(subst /make.libs,,$@)"
+	$(MAKE) -C $(subst /make.libs,,$@) -s libs  "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -Wall -Wextra"
+
+%/make.clean: 
+	$(MAKE) -C $(subst /make.clean,,$@) -s clean 
+clean:
+	rm -f ${PROCESSOR}/lib/libxil.a
diff --git a/quad/xsdk_workspace_vivado/system_bsp/system.mss b/quad/xsdk_workspace_vivado/system_bsp/system.mss
new file mode 100644
index 0000000000000000000000000000000000000000..5f6ae5d992764a487e78ee208676c820afcb4d59
--- /dev/null
+++ b/quad/xsdk_workspace_vivado/system_bsp/system.mss
@@ -0,0 +1,315 @@
+
+ PARAMETER VERSION = 2.2.0
+
+
+BEGIN OS
+ PARAMETER OS_NAME = standalone
+ PARAMETER OS_VER = 6.2
+ PARAMETER PROC_INSTANCE = ps7_cortexa9_0
+ PARAMETER stdin = ps7_uart_0
+ PARAMETER stdout = ps7_uart_0
+END
+
+
+BEGIN PROCESSOR
+ PARAMETER DRIVER_NAME = cpu_cortexa9
+ PARAMETER DRIVER_VER = 2.4
+ PARAMETER HW_INSTANCE = ps7_cortexa9_0
+END
+
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = gpio
+ PARAMETER DRIVER_VER = 4.3
+ PARAMETER HW_INSTANCE = axi_gpio_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = gpio
+ PARAMETER DRIVER_VER = 4.3
+ PARAMETER HW_INSTANCE = axi_gpio_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_afi_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_afi_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_afi_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_afi_3
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = coresightps_dcc
+ PARAMETER DRIVER_VER = 1.4
+ PARAMETER HW_INSTANCE = ps7_coresight_comp_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = ddrps
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = ps7_ddr_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_ddrc_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = devcfg
+ PARAMETER DRIVER_VER = 3.4
+ PARAMETER HW_INSTANCE = ps7_dev_cfg_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = dmaps
+ PARAMETER DRIVER_VER = 2.3
+ PARAMETER HW_INSTANCE = ps7_dma_ns
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = dmaps
+ PARAMETER DRIVER_VER = 2.3
+ PARAMETER HW_INSTANCE = ps7_dma_s
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = emacps
+ PARAMETER DRIVER_VER = 3.4
+ PARAMETER HW_INSTANCE = ps7_ethernet_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_globaltimer_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = gpiops
+ PARAMETER DRIVER_VER = 3.2
+ PARAMETER HW_INSTANCE = ps7_gpio_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_gpv_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = iicps
+ PARAMETER DRIVER_VER = 3.5
+ PARAMETER HW_INSTANCE = ps7_i2c_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = iicps
+ PARAMETER DRIVER_VER = 3.5
+ PARAMETER HW_INSTANCE = ps7_i2c_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_intc_dist_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_iop_bus_config_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_l2cachec_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_ocmc_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_pl310_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_pmu_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = qspips
+ PARAMETER DRIVER_VER = 3.3
+ PARAMETER HW_INSTANCE = ps7_qspi_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_qspi_linear_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_ram_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_ram_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_scuc_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = scugic
+ PARAMETER DRIVER_VER = 3.6
+ PARAMETER HW_INSTANCE = ps7_scugic_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = scutimer
+ PARAMETER DRIVER_VER = 2.1
+ PARAMETER HW_INSTANCE = ps7_scutimer_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = scuwdt
+ PARAMETER DRIVER_VER = 2.1
+ PARAMETER HW_INSTANCE = ps7_scuwdt_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = sdps
+ PARAMETER DRIVER_VER = 3.2
+ PARAMETER HW_INSTANCE = ps7_sd_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_slcr_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = ttcps
+ PARAMETER DRIVER_VER = 3.3
+ PARAMETER HW_INSTANCE = ps7_ttc_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = uartps
+ PARAMETER DRIVER_VER = 3.4
+ PARAMETER HW_INSTANCE = ps7_uart_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = uartps
+ PARAMETER DRIVER_VER = 3.4
+ PARAMETER HW_INSTANCE = ps7_uart_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = usbps
+ PARAMETER DRIVER_VER = 2.4
+ PARAMETER HW_INSTANCE = ps7_usb_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = xadcps
+ PARAMETER DRIVER_VER = 2.2
+ PARAMETER HW_INSTANCE = ps7_xadc_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = pwm_recorder
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = pwm_recorder_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = pwm_recorder
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = pwm_recorder_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = pwm_recorder
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = pwm_recorder_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = pwm_recorder
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = pwm_recorder_3
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = pwm_recorder
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = pwm_recorder_4
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = pwm_recorder
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = pwm_recorder_5
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = pwm_signal_out
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = pwm_signal_out_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = pwm_signal_out
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = pwm_signal_out_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = pwm_signal_out
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = pwm_signal_out_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = pwm_signal_out
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = pwm_signal_out_3
+END
+
+
diff --git a/quad/xsdk_workspace_vivado/sytem_hw_platform_0/.project b/quad/xsdk_workspace_vivado/sytem_hw_platform_0/.project
deleted file mode 100644
index a884cf6f9b5bb2ff74c4e9b884ca61417ef62cef..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/sytem_hw_platform_0/.project
+++ /dev/null
@@ -1,12 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<projectDescription>
-	<name>sytem_hw_platform_0</name>
-	<comment></comment>
-	<projects>
-	</projects>
-	<buildSpec>
-	</buildSpec>
-	<natures>
-		<nature>com.xilinx.sdk.hw.HwProject</nature>
-	</natures>
-</projectDescription>
diff --git a/quad/xsdk_workspace_vivado/sytem_hw_platform_0/ps7_init.c b/quad/xsdk_workspace_vivado/sytem_hw_platform_0/ps7_init.c
deleted file mode 100644
index 2c7ad97ad33b532925df749643c5395076b72cfa..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/sytem_hw_platform_0/ps7_init.c
+++ /dev/null
@@ -1,12655 +0,0 @@
- /******************************************************************************
- * 
- * (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
- * 
- * This file contains confidential and proprietary information of Xilinx, Inc.
- * and is protected under U.S. and international copyright and other
- * intellectual property laws.
- * 
- * DISCLAIMER
- * This disclaimer is not a license and does not grant any rights to the
- * materials distributed herewith. Except as otherwise provided in a valid
- * license issued to you by Xilinx, and to the maximum extent permitted by
- * applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE \"AS IS\" AND WITH ALL
- * FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
- * IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
- * MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
- * and (2) Xilinx shall not be liable (whether in contract or tort, including
- * negligence, or under any other theory of liability) for any loss or damage
- * of any kind or nature related to, arising under or in connection with these
- * materials, including for any direct, or any indirect, special, incidental,
- * or consequential loss or damage (including loss of data, profits, goodwill,
- * or any type of loss or damage suffered as a result of any action brought by
- * a third party) even if such damage or loss was reasonably foreseeable or
- * Xilinx had been advised of the possibility of the same.
- *
- * CRITICAL APPLICATIONS
- * Xilinx products are not designed or intended to be fail-safe, or for use in
- * any application requiring fail-safe performance, such as life-support or
- * safety devices or systems, Class III medical devices, nuclear facilities,
- * applications related to the deployment of airbags, or any other applications
- * that could lead to death, personal injury, or severe property or
- * environmental damage (individually and collectively, \"Critical
- * Applications\"). Customer assumes the sole risk and liability of any use of
- * Xilinx products in Critical Applications, subject only to applicable laws
- * and regulations governing limitations on product liability.
- *
- * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
- * AT ALL TIMES.
- *
- ******************************************************************************/
- /****************************************************************************/
- /**
- *
- * @file ps7_init.c
- *
- * This file is automatically generated
- * 
- *****************************************************************************/
-
- #include "ps7_init.h"
-
-unsigned long ps7_pll_init_data_1_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // .. 
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: PLL SLCR REGISTERS
-    // .. .. START: ARM PLL INIT
-    // .. .. PLL_RES = 0xc
-    // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x177
-    // .. .. ==> 0XF8000110[21:12] = 0x00000177U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00177000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001772C0U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x1a
-    // .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001A000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001A000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. ARM_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. .. 
-    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. SRCSEL = 0x0
-    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. .. .. DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
-    // .. .. .. CPU_6OR4XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. .. .. CPU_3OR2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
-    // .. .. .. CPU_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. .. CPU_1XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. .. CPU_PERI_CLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
-    // .. .. FINISH: ARM PLL INIT
-    // .. .. START: DDR PLL INIT
-    // .. .. PLL_RES = 0xc
-    // .. .. ==> 0XF8000114[7:4] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x1db
-    // .. .. ==> 0XF8000114[21:12] = 0x000001DBU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x001DB000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x001DB2C0U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x15
-    // .. .. .. ==> 0XF8000104[18:12] = 0x00000015U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00015000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00015000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. DDR_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. .. 
-    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. DDR_3XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. .. DDR_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
-    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
-    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
-    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
-    // .. .. FINISH: DDR PLL INIT
-    // .. .. START: IO PLL INIT
-    // .. .. PLL_RES = 0xc
-    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x1f4
-    // .. .. ==> 0XF8000118[21:12] = 0x000001F4U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x001F4000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001F42C0U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x14
-    // .. .. .. ==> 0XF8000108[18:12] = 0x00000014U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00014000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00014000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. IO_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. .. .. 
-    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. FINISH: IO PLL INIT
-    // .. FINISH: PLL SLCR REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // .. 
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_clock_init_data_1_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // .. 
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: CLOCK CONTROL SLCR REGISTERS
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000128[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. DIVISOR0 = 0x34
-    // .. ==> 0XF8000128[13:8] = 0x00000034U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00003400U
-    // .. DIVISOR1 = 0x2
-    // .. ==> 0XF8000128[25:20] = 0x00000002U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00203401U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000138[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000138[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000140[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000140[6:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. DIVISOR = 0x8
-    // .. ==> 0XF8000140[13:8] = 0x00000008U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000140[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF800014C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF800014C[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF800014C[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // .. 
-    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
-    // .. CLKACT0 = 0x1
-    // .. ==> 0XF8000150[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. CLKACT1 = 0x0
-    // .. ==> 0XF8000150[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000150[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000150[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. 
-    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
-    // .. CLKACT0 = 0x1
-    // .. ==> 0XF8000154[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. CLKACT1 = 0x1
-    // .. ==> 0XF8000154[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000154[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000154[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. 
-    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // .. 
-    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0xa
-    // .. ==> 0XF8000170[13:8] = 0x0000000AU
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
-    // .. SRCSEL = 0x3
-    // .. ==> 0XF8000180[5:4] = 0x00000003U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000030U
-    // .. DIVISOR0 = 0x6
-    // .. ==> 0XF8000180[13:8] = 0x00000006U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000600U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100630U),
-    // .. SRCSEL = 0x2
-    // .. ==> 0XF8000190[5:4] = 0x00000002U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000020U
-    // .. DIVISOR0 = 0x35
-    // .. ==> 0XF8000190[13:8] = 0x00000035U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00003500U
-    // .. DIVISOR1 = 0x2
-    // .. ==> 0XF8000190[25:20] = 0x00000002U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00203520U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0xa
-    // .. ==> 0XF80001A0[13:8] = 0x0000000AU
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
-    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100A00U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
-    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[20:20] = 0x00000001U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00100000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FC044DU),
-    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
-    // .. START: THIS SHOULD BE BLANK
-    // .. FINISH: THIS SHOULD BE BLANK
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // .. 
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_ddr_init_data_1_0[] = {
-    // START: top
-    // .. START: DDR INITIALIZATION
-    // .. .. START: LOCK DDR
-    // .. .. reg_ddrc_soft_rstb = 0
-    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_powerdown_en = 0x0
-    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_data_bus_width = 0x0
-    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. .. reg_ddrc_burst8_refresh = 0x0
-    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
-    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_act_bypass = 0x0
-    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
-    // .. .. FINISH: LOCK DDR
-    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f
-    // .. .. ==> 0XF8006004[11:0] = 0x0000007FU
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x0000007FU
-    // .. .. reg_ddrc_active_ranks = 0x1
-    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
-    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
-    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_wr_odt_block = 0x1
-    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
-    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
-    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
-    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_open_bank = 0x0
-    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
-    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x0008107FU),
-    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
-    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
-    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
-    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
-    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
-    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
-    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
-    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
-    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
-    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
-    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_w_xact_run_length = 0x8
-    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
-    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
-    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
-    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
-    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
-    // .. .. reg_ddrc_t_rc = 0x1a
-    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
-    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
-    // .. .. reg_ddrc_t_rfc_min = 0x54
-    // .. .. ==> 0XF8006014[13:6] = 0x00000054U
-    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001500U
-    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
-    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
-    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004151AU),
-    // .. .. reg_ddrc_wr2pre = 0x12
-    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
-    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
-    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
-    // .. .. reg_ddrc_t_faw = 0x15
-    // .. .. ==> 0XF8006018[15:10] = 0x00000015U
-    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005400U
-    // .. .. reg_ddrc_t_ras_max = 0x23
-    // .. .. ==> 0XF8006018[21:16] = 0x00000023U
-    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00230000U
-    // .. .. reg_ddrc_t_ras_min = 0x13
-    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
-    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
-    // .. .. reg_ddrc_t_cke = 0x4
-    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E354D2U),
-    // .. .. reg_ddrc_write_latency = 0x5
-    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
-    // .. .. reg_ddrc_rd2wr = 0x7
-    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
-    // .. .. reg_ddrc_wr2rd = 0xe
-    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
-    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
-    // .. .. reg_ddrc_t_xp = 0x4
-    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
-    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
-    // .. .. reg_ddrc_pad_pd = 0x0
-    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd2pre = 0x4
-    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
-    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
-    // .. .. reg_ddrc_t_rcd = 0x7
-    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
-    // .. .. reg_ddrc_t_ccd = 0x4
-    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
-    // .. .. reg_ddrc_t_rrd = 0x6
-    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
-    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
-    // .. .. reg_ddrc_refresh_margin = 0x2
-    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. reg_ddrc_t_rp = 0x7
-    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
-    // .. .. reg_ddrc_refresh_to_x32 = 0x8
-    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
-    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
-    // .. .. reg_ddrc_sdram = 0x1
-    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. .. reg_ddrc_mobile = 0x0
-    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_clock_stop_en = 0x0
-    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
-    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_read_latency = 0x7
-    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
-    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
-    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
-    // .. .. reg_ddrc_dis_pad_pd = 0x0
-    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
-    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_loopback = 0x0
-    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
-    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
-    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
-    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_prefer_write = 0x0
-    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_max_rank_rd = 0xf
-    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
-    // .. .. reg_ddrc_mr_wr = 0x0
-    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_addr = 0x0
-    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_data = 0x0
-    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
-    // .. .. ddrc_reg_mr_wr_busy = 0x0
-    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_type = 0x0
-    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_rdata_valid = 0x0
-    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
-    // .. .. reg_ddrc_final_wait_x32 = 0x7
-    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
-    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
-    // .. .. reg_ddrc_t_mrd = 0x4
-    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
-    // .. .. reg_ddrc_emr2 = 0x8
-    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
-    // .. .. reg_ddrc_emr3 = 0x0
-    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
-    // .. .. reg_ddrc_mr = 0x930
-    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
-    // .. .. reg_ddrc_emr = 0x4
-    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
-    // .. .. reg_ddrc_burst_rdwr = 0x4
-    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x101
-    // .. .. ==> 0XF8006034[13:4] = 0x00000101U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001010U
-    // .. .. reg_ddrc_post_cke_x1024 = 0x1
-    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
-    // .. .. reg_ddrc_burstchop = 0x0
-    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011014U),
-    // .. .. reg_ddrc_force_low_pri_n = 0x0
-    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_dq = 0x0
-    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_debug_mode = 0x0
-    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_level_start = 0x0
-    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_level_start = 0x0
-    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_phy_dq0_wait_t = 0x0
-    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
-    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
-    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
-    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
-    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
-    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
-    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
-    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
-    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
-    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
-    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
-    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
-    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
-    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
-    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
-    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
-    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
-    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
-    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
-    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
-    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
-    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
-    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
-    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
-    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
-    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
-    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
-    // .. .. reg_ddrc_addrmap_row_b14 = 0xf
-    // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
-    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
-    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
-    // .. .. reg_ddrc_rank0_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank0_wr_odt = 0x1
-    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
-    // .. .. reg_ddrc_rank1_rd_odt = 0x1
-    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
-    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
-    // .. .. reg_ddrc_rank1_wr_odt = 0x1
-    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. .. reg_phy_rd_local_odt = 0x0
-    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_local_odt = 0x3
-    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
-    // .. .. reg_phy_idle_local_odt = 0x3
-    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
-    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
-    // .. .. reg_ddrc_rank2_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank2_wr_odt = 0x0
-    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank3_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank3_wr_odt = 0x0
-    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
-    // .. .. reg_phy_rd_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_phy_wr_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
-    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
-    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
-    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_phy_use_fixed_re = 0x1
-    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
-    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
-    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_phy_clk_stall_level = 0x0
-    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
-    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
-    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
-    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
-    // .. .. reg_ddrc_dis_dll_calib = 0x0
-    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
-    // .. .. reg_ddrc_rd_odt_delay = 0x3
-    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
-    // .. .. reg_ddrc_wr_odt_delay = 0x0
-    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd_odt_hold = 0x0
-    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_wr_odt_hold = 0x5
-    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
-    // .. .. reg_ddrc_pageclose = 0x0
-    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_lpr_num_entries = 0x1f
-    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
-    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
-    // .. .. reg_ddrc_auto_pre_en = 0x0
-    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. .. reg_ddrc_refresh_update_level = 0x0
-    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_wc = 0x0
-    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
-    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_ddrc_selfref_en = 0x0
-    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
-    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
-    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
-    // .. .. reg_arb_go2critical_en = 0x1
-    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
-    // .. .. reg_ddrc_wrlvl_ww = 0x41
-    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
-    // .. .. reg_ddrc_rdlvl_rr = 0x41
-    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
-    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
-    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
-    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
-    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
-    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
-    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
-    // .. .. 
-    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
-    // .. .. refresh_timer0_start_value_x32 = 0x0
-    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
-    // .. .. refresh_timer1_start_value_x32 = 0x8
-    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
-    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
-    // .. .. reg_ddrc_dis_auto_zq = 0x0
-    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_ddr3 = 0x1
-    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. reg_ddrc_t_mod = 0x200
-    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
-    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
-    // .. .. reg_ddrc_t_zq_long_nop = 0x200
-    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
-    // .. .. reg_ddrc_t_zq_short_nop = 0x40
-    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
-    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
-    // .. .. t_zq_short_interval_x1024 = 0xc845
-    // .. .. ==> 0XF80060A8[19:0] = 0x0000C845U
-    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000C845U
-    // .. .. dram_rstn_x1024 = 0x67
-    // .. .. ==> 0XF80060A8[27:20] = 0x00000067U
-    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06700000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0670C845U),
-    // .. .. deeppowerdown_en = 0x0
-    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. deeppowerdown_to_x1024 = 0xff
-    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
-    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
-    // .. .. 
-    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
-    // .. .. dfi_wrlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
-    // .. .. dfi_rdlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
-    // .. .. ddrc_reg_twrlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. .. ddrc_reg_trdlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
-    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
-    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
-    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
-    // .. .. reg_ddrc_2t_delay = 0x0
-    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
-    // .. .. reg_ddrc_skip_ocd = 0x1
-    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. .. reg_ddrc_dis_pre_bypass = 0x0
-    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
-    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
-    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
-    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
-    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
-    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
-    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. Clear_Correctable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. 
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
-    // .. FINISH: DDR INITIALIZATION
-    // .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
-    // .. ==> 0XF80060C4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. Clear_Correctable_DRAM_ECC_error = 0x0
-    // .. ==> 0XF80060C4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
-    // .. CORR_ECC_LOG_VALID = 0x0
-    // .. ==> 0XF80060C8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. ECC_CORRECTED_BIT_NUM = 0x0
-    // .. ==> 0XF80060C8[7:1] = 0x00000000U
-    // ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
-    // .. UNCORR_ECC_LOG_VALID = 0x0
-    // .. ==> 0XF80060DC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
-    // .. STAT_NUM_CORR_ERR = 0x0
-    // .. ==> 0XF80060F0[15:8] = 0x00000000U
-    // ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
-    // .. STAT_NUM_UNCORR_ERR = 0x0
-    // .. ==> 0XF80060F0[7:0] = 0x00000000U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
-    // .. reg_ddrc_ecc_mode = 0x0
-    // .. ==> 0XF80060F4[2:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
-    // .. reg_ddrc_dis_scrub = 0x1
-    // .. ==> 0XF80060F4[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. 
-    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
-    // .. reg_phy_dif_on = 0x0
-    // .. ==> 0XF8006114[3:0] = 0x00000000U
-    // ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. reg_phy_dif_off = 0x0
-    // .. ==> 0XF8006114[7:4] = 0x00000000U
-    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
-    // .. reg_phy_data_slice_in_use = 0x1
-    // .. ==> 0XF8006118[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. ==> 0XF8006118[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. ==> 0XF8006118[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. ==> 0XF8006118[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. reg_phy_board_lpbk_tx = 0x0
-    // .. ==> 0XF8006118[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. reg_phy_board_lpbk_rx = 0x0
-    // .. ==> 0XF8006118[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. reg_phy_bist_shift_dq = 0x0
-    // .. ==> 0XF8006118[14:6] = 0x00000000U
-    // ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. reg_phy_bist_err_clr = 0x0
-    // .. ==> 0XF8006118[23:15] = 0x00000000U
-    // ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. reg_phy_dq_offset = 0x40
-    // .. ==> 0XF8006118[30:24] = 0x00000040U
-    // ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
-    // .. reg_phy_data_slice_in_use = 0x1
-    // .. ==> 0XF800611C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. ==> 0XF800611C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. ==> 0XF800611C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. ==> 0XF800611C[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. reg_phy_board_lpbk_tx = 0x0
-    // .. ==> 0XF800611C[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. reg_phy_board_lpbk_rx = 0x0
-    // .. ==> 0XF800611C[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. reg_phy_bist_shift_dq = 0x0
-    // .. ==> 0XF800611C[14:6] = 0x00000000U
-    // ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. reg_phy_bist_err_clr = 0x0
-    // .. ==> 0XF800611C[23:15] = 0x00000000U
-    // ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. reg_phy_dq_offset = 0x40
-    // .. ==> 0XF800611C[30:24] = 0x00000040U
-    // ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
-    // .. reg_phy_data_slice_in_use = 0x1
-    // .. ==> 0XF8006120[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. ==> 0XF8006120[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. ==> 0XF8006120[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. ==> 0XF8006120[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. reg_phy_board_lpbk_tx = 0x0
-    // .. ==> 0XF8006120[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. reg_phy_board_lpbk_rx = 0x0
-    // .. ==> 0XF8006120[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. reg_phy_bist_shift_dq = 0x0
-    // .. ==> 0XF8006120[14:6] = 0x00000000U
-    // ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. reg_phy_bist_err_clr = 0x0
-    // .. ==> 0XF8006120[23:15] = 0x00000000U
-    // ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. reg_phy_dq_offset = 0x40
-    // .. ==> 0XF8006120[30:24] = 0x00000040U
-    // ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
-    // .. reg_phy_data_slice_in_use = 0x1
-    // .. ==> 0XF8006124[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. ==> 0XF8006124[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. ==> 0XF8006124[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. ==> 0XF8006124[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. reg_phy_board_lpbk_tx = 0x0
-    // .. ==> 0XF8006124[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. reg_phy_board_lpbk_rx = 0x0
-    // .. ==> 0XF8006124[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. reg_phy_bist_shift_dq = 0x0
-    // .. ==> 0XF8006124[14:6] = 0x00000000U
-    // ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. reg_phy_bist_err_clr = 0x0
-    // .. ==> 0XF8006124[23:15] = 0x00000000U
-    // ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. reg_phy_dq_offset = 0x40
-    // .. ==> 0XF8006124[30:24] = 0x00000040U
-    // ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
-    // .. reg_phy_wrlvl_init_ratio = 0x0
-    // .. ==> 0XF800612C[9:0] = 0x00000000U
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
-    // .. reg_phy_gatelvl_init_ratio = 0x8f
-    // .. ==> 0XF800612C[19:10] = 0x0000008FU
-    // ..     ==> MASK : 0x000FFC00U    VAL : 0x00023C00U
-    // .. 
-    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00023C00U),
-    // .. reg_phy_wrlvl_init_ratio = 0x0
-    // .. ==> 0XF8006130[9:0] = 0x00000000U
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
-    // .. reg_phy_gatelvl_init_ratio = 0x8a
-    // .. ==> 0XF8006130[19:10] = 0x0000008AU
-    // ..     ==> MASK : 0x000FFC00U    VAL : 0x00022800U
-    // .. 
-    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00022800U),
-    // .. reg_phy_wrlvl_init_ratio = 0x0
-    // .. ==> 0XF8006134[9:0] = 0x00000000U
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
-    // .. reg_phy_gatelvl_init_ratio = 0x8b
-    // .. ==> 0XF8006134[19:10] = 0x0000008BU
-    // ..     ==> MASK : 0x000FFC00U    VAL : 0x00022C00U
-    // .. 
-    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00022C00U),
-    // .. reg_phy_wrlvl_init_ratio = 0x0
-    // .. ==> 0XF8006138[9:0] = 0x00000000U
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
-    // .. reg_phy_gatelvl_init_ratio = 0x92
-    // .. ==> 0XF8006138[19:10] = 0x00000092U
-    // ..     ==> MASK : 0x000FFC00U    VAL : 0x00024800U
-    // .. 
-    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00024800U),
-    // .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. ==> 0XF8006140[9:0] = 0x00000035U
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. ==> 0XF8006140[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. ==> 0XF8006140[19:11] = 0x00000000U
-    // ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
-    // .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. ==> 0XF8006144[9:0] = 0x00000035U
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. ==> 0XF8006144[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. ==> 0XF8006144[19:11] = 0x00000000U
-    // ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
-    // .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. ==> 0XF8006148[9:0] = 0x00000035U
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. ==> 0XF8006148[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. ==> 0XF8006148[19:11] = 0x00000000U
-    // ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
-    // .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. ==> 0XF800614C[9:0] = 0x00000035U
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. ==> 0XF800614C[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. ==> 0XF800614C[19:11] = 0x00000000U
-    // ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
-    // .. reg_phy_wr_dqs_slave_ratio = 0x77
-    // .. ==> 0XF8006154[9:0] = 0x00000077U
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U
-    // .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. ==> 0XF8006154[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. ==> 0XF8006154[19:11] = 0x00000000U
-    // ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
-    // .. reg_phy_wr_dqs_slave_ratio = 0x7c
-    // .. ==> 0XF8006158[9:0] = 0x0000007CU
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU
-    // .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. ==> 0XF8006158[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. ==> 0XF8006158[19:11] = 0x00000000U
-    // ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU),
-    // .. reg_phy_wr_dqs_slave_ratio = 0x7c
-    // .. ==> 0XF800615C[9:0] = 0x0000007CU
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU
-    // .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. ==> 0XF800615C[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. ==> 0XF800615C[19:11] = 0x00000000U
-    // ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007CU),
-    // .. reg_phy_wr_dqs_slave_ratio = 0x75
-    // .. ==> 0XF8006160[9:0] = 0x00000075U
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x00000075U
-    // .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. ==> 0XF8006160[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. ==> 0XF8006160[19:11] = 0x00000000U
-    // ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000075U),
-    // .. reg_phy_fifo_we_slave_ratio = 0xe4
-    // .. ==> 0XF8006168[10:0] = 0x000000E4U
-    // ..     ==> MASK : 0x000007FFU    VAL : 0x000000E4U
-    // .. reg_phy_fifo_we_in_force = 0x0
-    // .. ==> 0XF8006168[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. reg_phy_fifo_we_in_delay = 0x0
-    // .. ==> 0XF8006168[20:12] = 0x00000000U
-    // ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000E4U),
-    // .. reg_phy_fifo_we_slave_ratio = 0xdf
-    // .. ==> 0XF800616C[10:0] = 0x000000DFU
-    // ..     ==> MASK : 0x000007FFU    VAL : 0x000000DFU
-    // .. reg_phy_fifo_we_in_force = 0x0
-    // .. ==> 0XF800616C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. reg_phy_fifo_we_in_delay = 0x0
-    // .. ==> 0XF800616C[20:12] = 0x00000000U
-    // ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000DFU),
-    // .. reg_phy_fifo_we_slave_ratio = 0xe0
-    // .. ==> 0XF8006170[10:0] = 0x000000E0U
-    // ..     ==> MASK : 0x000007FFU    VAL : 0x000000E0U
-    // .. reg_phy_fifo_we_in_force = 0x0
-    // .. ==> 0XF8006170[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. reg_phy_fifo_we_in_delay = 0x0
-    // .. ==> 0XF8006170[20:12] = 0x00000000U
-    // ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000E0U),
-    // .. reg_phy_fifo_we_slave_ratio = 0xe7
-    // .. ==> 0XF8006174[10:0] = 0x000000E7U
-    // ..     ==> MASK : 0x000007FFU    VAL : 0x000000E7U
-    // .. reg_phy_fifo_we_in_force = 0x0
-    // .. ==> 0XF8006174[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. reg_phy_fifo_we_in_delay = 0x0
-    // .. ==> 0XF8006174[20:12] = 0x00000000U
-    // ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000E7U),
-    // .. reg_phy_wr_data_slave_ratio = 0xb7
-    // .. ==> 0XF800617C[9:0] = 0x000000B7U
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U
-    // .. reg_phy_wr_data_slave_force = 0x0
-    // .. ==> 0XF800617C[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. reg_phy_wr_data_slave_delay = 0x0
-    // .. ==> 0XF800617C[19:11] = 0x00000000U
-    // ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
-    // .. reg_phy_wr_data_slave_ratio = 0xbc
-    // .. ==> 0XF8006180[9:0] = 0x000000BCU
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU
-    // .. reg_phy_wr_data_slave_force = 0x0
-    // .. ==> 0XF8006180[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. reg_phy_wr_data_slave_delay = 0x0
-    // .. ==> 0XF8006180[19:11] = 0x00000000U
-    // ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU),
-    // .. reg_phy_wr_data_slave_ratio = 0xbc
-    // .. ==> 0XF8006184[9:0] = 0x000000BCU
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU
-    // .. reg_phy_wr_data_slave_force = 0x0
-    // .. ==> 0XF8006184[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. reg_phy_wr_data_slave_delay = 0x0
-    // .. ==> 0XF8006184[19:11] = 0x00000000U
-    // ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BCU),
-    // .. reg_phy_wr_data_slave_ratio = 0xb5
-    // .. ==> 0XF8006188[9:0] = 0x000000B5U
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x000000B5U
-    // .. reg_phy_wr_data_slave_force = 0x0
-    // .. ==> 0XF8006188[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. reg_phy_wr_data_slave_delay = 0x0
-    // .. ==> 0XF8006188[19:11] = 0x00000000U
-    // ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B5U),
-    // .. reg_phy_loopback = 0x0
-    // .. ==> 0XF8006190[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. reg_phy_bl2 = 0x0
-    // .. ==> 0XF8006190[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. reg_phy_at_spd_atpg = 0x0
-    // .. ==> 0XF8006190[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. reg_phy_bist_enable = 0x0
-    // .. ==> 0XF8006190[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. reg_phy_bist_force_err = 0x0
-    // .. ==> 0XF8006190[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. reg_phy_bist_mode = 0x0
-    // .. ==> 0XF8006190[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. reg_phy_invert_clkout = 0x1
-    // .. ==> 0XF8006190[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. reg_phy_all_dq_mpr_rd_resp = 0x0
-    // .. ==> 0XF8006190[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. reg_phy_sel_logic = 0x0
-    // .. ==> 0XF8006190[9:9] = 0x00000000U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. reg_phy_ctrl_slave_ratio = 0x100
-    // .. ==> 0XF8006190[19:10] = 0x00000100U
-    // ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
-    // .. reg_phy_ctrl_slave_force = 0x0
-    // .. ==> 0XF8006190[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. reg_phy_ctrl_slave_delay = 0x0
-    // .. ==> 0XF8006190[27:21] = 0x00000000U
-    // ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
-    // .. reg_phy_use_rank0_delays = 0x1
-    // .. ==> 0XF8006190[28:28] = 0x00000001U
-    // ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. reg_phy_lpddr = 0x0
-    // .. ==> 0XF8006190[29:29] = 0x00000000U
-    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // .. reg_phy_cmd_latency = 0x0
-    // .. ==> 0XF8006190[30:30] = 0x00000000U
-    // ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. reg_phy_int_lpbk = 0x0
-    // .. ==> 0XF8006190[31:31] = 0x00000000U
-    // ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
-    // .. reg_phy_wr_rl_delay = 0x2
-    // .. ==> 0XF8006194[4:0] = 0x00000002U
-    // ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
-    // .. reg_phy_rd_rl_delay = 0x4
-    // .. ==> 0XF8006194[9:5] = 0x00000004U
-    // ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
-    // .. reg_phy_dll_lock_diff = 0xf
-    // .. ==> 0XF8006194[13:10] = 0x0000000FU
-    // ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
-    // .. reg_phy_use_wr_level = 0x1
-    // .. ==> 0XF8006194[14:14] = 0x00000001U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
-    // .. reg_phy_use_rd_dqs_gate_level = 0x1
-    // .. ==> 0XF8006194[15:15] = 0x00000001U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
-    // .. reg_phy_use_rd_data_eye_level = 0x1
-    // .. ==> 0XF8006194[16:16] = 0x00000001U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. reg_phy_dis_calib_rst = 0x0
-    // .. ==> 0XF8006194[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. reg_phy_ctrl_slave_delay = 0x0
-    // .. ==> 0XF8006194[19:18] = 0x00000000U
-    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
-    // .. reg_arb_page_addr_mask = 0x0
-    // .. ==> 0XF8006204[31:0] = 0x00000000U
-    // ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
-    // .. reg_arb_pri_wr_portn = 0x3ff
-    // .. ==> 0XF8006208[9:0] = 0x000003FFU
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. ==> 0XF8006208[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. ==> 0XF8006208[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. ==> 0XF8006208[18:18] = 0x00000000U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. reg_arb_dis_rmw_portn = 0x1
-    // .. ==> 0XF8006208[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
-    // .. reg_arb_pri_wr_portn = 0x3ff
-    // .. ==> 0XF800620C[9:0] = 0x000003FFU
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. ==> 0XF800620C[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. ==> 0XF800620C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. ==> 0XF800620C[18:18] = 0x00000000U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. reg_arb_dis_rmw_portn = 0x1
-    // .. ==> 0XF800620C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. 
-    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
-    // .. reg_arb_pri_wr_portn = 0x3ff
-    // .. ==> 0XF8006210[9:0] = 0x000003FFU
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. ==> 0XF8006210[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. ==> 0XF8006210[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. ==> 0XF8006210[18:18] = 0x00000000U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. reg_arb_dis_rmw_portn = 0x1
-    // .. ==> 0XF8006210[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
-    // .. reg_arb_pri_wr_portn = 0x3ff
-    // .. ==> 0XF8006214[9:0] = 0x000003FFU
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. ==> 0XF8006214[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. ==> 0XF8006214[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. ==> 0XF8006214[18:18] = 0x00000000U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. reg_arb_dis_rmw_portn = 0x1
-    // .. ==> 0XF8006214[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
-    // .. reg_arb_pri_rd_portn = 0x3ff
-    // .. ==> 0XF8006218[9:0] = 0x000003FFU
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. ==> 0XF8006218[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. ==> 0XF8006218[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. ==> 0XF8006218[18:18] = 0x00000000U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. ==> 0XF8006218[19:19] = 0x00000000U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
-    // .. reg_arb_pri_rd_portn = 0x3ff
-    // .. ==> 0XF800621C[9:0] = 0x000003FFU
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. ==> 0XF800621C[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. ==> 0XF800621C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. ==> 0XF800621C[18:18] = 0x00000000U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. ==> 0XF800621C[19:19] = 0x00000000U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
-    // .. reg_arb_pri_rd_portn = 0x3ff
-    // .. ==> 0XF8006220[9:0] = 0x000003FFU
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. ==> 0XF8006220[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. ==> 0XF8006220[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. ==> 0XF8006220[18:18] = 0x00000000U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. ==> 0XF8006220[19:19] = 0x00000000U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
-    // .. reg_arb_pri_rd_portn = 0x3ff
-    // .. ==> 0XF8006224[9:0] = 0x000003FFU
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. ==> 0XF8006224[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. ==> 0XF8006224[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. ==> 0XF8006224[18:18] = 0x00000000U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. ==> 0XF8006224[19:19] = 0x00000000U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
-    // .. reg_ddrc_lpddr2 = 0x0
-    // .. ==> 0XF80062A8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. reg_ddrc_per_bank_refresh = 0x0
-    // .. ==> 0XF80062A8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. reg_ddrc_derate_enable = 0x0
-    // .. ==> 0XF80062A8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. reg_ddrc_mr4_margin = 0x0
-    // .. ==> 0XF80062A8[11:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
-    // .. reg_ddrc_mr4_read_interval = 0x0
-    // .. ==> 0XF80062AC[31:0] = 0x00000000U
-    // ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
-    // .. reg_ddrc_min_stable_clock_x1 = 0x5
-    // .. ==> 0XF80062B0[3:0] = 0x00000005U
-    // ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
-    // .. reg_ddrc_idle_after_reset_x32 = 0x12
-    // .. ==> 0XF80062B0[11:4] = 0x00000012U
-    // ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
-    // .. reg_ddrc_t_mrw = 0x5
-    // .. ==> 0XF80062B0[21:12] = 0x00000005U
-    // ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
-    // .. 
-    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
-    // .. reg_ddrc_max_auto_init_x1024 = 0xa6
-    // .. ==> 0XF80062B4[7:0] = 0x000000A6U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x000000A6U
-    // .. reg_ddrc_dev_zqinit_x32 = 0x12
-    // .. ==> 0XF80062B4[17:8] = 0x00000012U
-    // ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
-    // .. 
-    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A6U),
-    // .. START: POLL ON DCI STATUS
-    // .. DONE = 1
-    // .. ==> 0XF8000B74[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. 
-    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
-    // .. FINISH: POLL ON DCI STATUS
-    // .. START: UNLOCK DDR
-    // .. reg_ddrc_soft_rstb = 0x1
-    // .. ==> 0XF8006000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. reg_ddrc_powerdown_en = 0x0
-    // .. ==> 0XF8006000[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. reg_ddrc_data_bus_width = 0x0
-    // .. ==> 0XF8006000[3:2] = 0x00000000U
-    // ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. reg_ddrc_burst8_refresh = 0x0
-    // .. ==> 0XF8006000[6:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. reg_ddrc_rdwr_idle_gap = 1
-    // .. ==> 0XF8006000[13:7] = 0x00000001U
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. ==> 0XF8006000[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. reg_ddrc_dis_act_bypass = 0x0
-    // .. ==> 0XF8006000[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. ==> 0XF8006000[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
-    // .. FINISH: UNLOCK DDR
-    // .. START: CHECK DDR STATUS
-    // .. ddrc_reg_operating_mode = 1
-    // .. ==> 0XF8006054[2:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
-    // .. 
-    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
-    // .. FINISH: CHECK DDR STATUS
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_mio_init_data_1_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // .. 
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: OCM REMAPPING
-    // .. VREF_EN = 0x1
-    // .. ==> 0XF8000B00[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. VREF_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B00[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. CLK_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B00[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. SRSTN_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B00[9:9] = 0x00000000U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
-    // .. FINISH: OCM REMAPPING
-    // .. START: DDRIOB SETTINGS
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B40[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B40[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B40[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B40[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B40[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B40[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B40[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B44[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B44[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B44[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B44[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B44[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B44[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B44[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B48[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B48[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B48[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B48[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B48[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B48[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B48[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B50[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B50[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B50[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B50[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B50[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B50[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B50[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B54[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B54[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B54[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B54[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B54[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B54[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B54[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B58[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B58[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B58[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B58[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B58[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B58[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B58[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x1a
-    // .. ==> 0XF8000B5C[18:14] = 0x0000001AU
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00068000U
-    // .. SLEW_N = 0x1a
-    // .. ==> 0XF8000B5C[23:19] = 0x0000001AU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00D00000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x00D6861CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x6
-    // .. ==> 0XF8000B60[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. SLEW_N = 0x1f
-    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B60[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B60[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x6
-    // .. ==> 0XF8000B64[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. SLEW_N = 0x1f
-    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B64[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B64[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x1a
-    // .. ==> 0XF8000B68[18:14] = 0x0000001AU
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00068000U
-    // .. SLEW_N = 0x1a
-    // .. ==> 0XF8000B68[23:19] = 0x0000001AU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00D00000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B68[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B68[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00D6861CU),
-    // .. VREF_INT_EN = 0x0
-    // .. ==> 0XF8000B6C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. VREF_SEL = 0x0
-    // .. ==> 0XF8000B6C[4:1] = 0x00000000U
-    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U
-    // .. VREF_EXT_EN = 0x3
-    // .. ==> 0XF8000B6C[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. VREF_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
-    // .. REFIO_EN = 0x1
-    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. REFIO_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DRST_B_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. CKE_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U),
-    // .. .. START: ASSERT RESET
-    // .. .. RESET = 1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
-    // .. .. FINISH: ASSERT RESET
-    // .. .. START: DEASSERT RESET
-    // .. .. RESET = 0
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
-    // .. .. FINISH: DEASSERT RESET
-    // .. .. RESET = 0x1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ENABLE = 0x1
-    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. VRP_TRI = 0x0
-    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. VRN_TRI = 0x0
-    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. VRP_OUT = 0x0
-    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. .. NREF_OPT1 = 0x0
-    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. .. NREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
-    // .. .. NREF_OPT4 = 0x1
-    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
-    // .. .. PREF_OPT1 = 0x0
-    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
-    // .. .. PREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
-    // .. .. UPDATE_CONTROL = 0x0
-    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. .. INIT_COMPLETE = 0x0
-    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. .. TST_CLK = 0x0
-    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. .. TST_HLN = 0x0
-    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
-    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. .. TST_HLP = 0x0
-    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. .. TST_RST = 0x0
-    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. INT_DCI_EN = 0x0
-    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
-    // .. FINISH: DDRIOB SETTINGS
-    // .. START: MIO PROGRAMMING
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000700[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000700[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000700[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000700[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000700[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000700[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000700[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000700[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000700[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000704[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000704[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000704[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000704[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000704[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000704[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000704[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000704[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000704[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000708[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000708[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000708[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000708[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000708[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000708[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000708[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000708[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000708[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800070C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800070C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800070C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800070C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800070C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800070C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF800070C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800070C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800070C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000710[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000710[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000710[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000710[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000710[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000710[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000710[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000710[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000710[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000714[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000714[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000714[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000714[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000714[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000714[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000714[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000714[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000714[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000718[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000718[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000718[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000718[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000718[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000718[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000718[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000718[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000718[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800071C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800071C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800071C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800071C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800071C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800071C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800071C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800071C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800071C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000720[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000720[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000720[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000720[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000720[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000720[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000720[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000720[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000720[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000724[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000724[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000724[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000724[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000724[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000724[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000724[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000724[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000724[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000728[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000728[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000728[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000728[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 2
-    // .. ==> 0XF8000728[7:5] = 0x00000002U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
-    // .. Speed = 0
-    // .. ==> 0XF8000728[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000728[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000728[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000728[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001640U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800072C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800072C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800072C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800072C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 2
-    // .. ==> 0XF800072C[7:5] = 0x00000002U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
-    // .. Speed = 0
-    // .. ==> 0XF800072C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800072C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 1
-    // .. ==> 0XF800072C[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800072C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001640U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000730[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000730[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000730[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000730[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 2
-    // .. ==> 0XF8000730[7:5] = 0x00000002U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
-    // .. Speed = 0
-    // .. ==> 0XF8000730[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000730[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000730[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000730[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001640U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000734[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000734[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000734[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000734[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 2
-    // .. ==> 0XF8000734[7:5] = 0x00000002U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
-    // .. Speed = 0
-    // .. ==> 0XF8000734[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000734[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000734[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000734[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001640U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000738[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000738[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000738[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000738[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000738[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000738[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000738[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000738[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000738[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800073C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800073C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800073C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800073C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800073C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800073C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800073C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800073C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800073C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000740[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000740[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000740[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000740[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000740[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000740[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000740[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000740[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000740[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002902U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000744[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000744[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000744[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000744[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000744[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000744[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000744[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000744[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000744[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002902U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000748[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000748[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000748[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000748[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000748[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000748[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000748[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000748[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000748[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002902U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800074C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800074C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800074C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800074C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800074C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800074C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF800074C[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF800074C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF800074C[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. 
-    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002902U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000750[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000750[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000750[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000750[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000750[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000750[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000750[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000750[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000750[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002902U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000754[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000754[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000754[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000754[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000754[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000754[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000754[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000754[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000754[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002902U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000758[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000758[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000758[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000758[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000758[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000758[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000758[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000758[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000758[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000903U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800075C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800075C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800075C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800075C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800075C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800075C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF800075C[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF800075C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800075C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000903U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000760[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000760[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000760[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000760[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000760[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000760[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000760[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000760[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000760[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000903U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000764[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000764[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000764[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000764[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000764[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000764[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000764[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000764[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000764[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000903U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000768[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000768[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000768[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000768[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000768[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000768[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000768[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000768[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000768[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000903U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800076C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800076C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800076C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800076C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800076C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800076C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF800076C[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF800076C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800076C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000903U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000770[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000770[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000770[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000770[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000770[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000770[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000770[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000770[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000770[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000774[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000774[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000774[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000774[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000774[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000774[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000774[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000774[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000774[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000778[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000778[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000778[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000778[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000778[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000778[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000778[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000778[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000778[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800077C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800077C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800077C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800077C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800077C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800077C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF800077C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800077C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800077C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000780[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000780[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000780[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000780[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000780[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000780[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000780[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000780[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000780[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000784[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000784[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000784[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000784[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000784[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000784[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000784[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000784[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000784[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000788[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000788[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000788[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000788[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000788[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000788[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000788[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000788[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000788[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800078C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800078C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800078C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800078C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800078C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800078C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF800078C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800078C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800078C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000790[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000790[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000790[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000790[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000790[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000790[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000790[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000790[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000790[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000794[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000794[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000794[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000794[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000794[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000794[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000794[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000794[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000794[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000798[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000798[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000798[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000798[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000798[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000798[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000798[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000798[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000798[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800079C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800079C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800079C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800079C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800079C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800079C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF800079C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800079C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800079C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007A0[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007A4[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A8[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007A8[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007AC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007AC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007AC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007AC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007AC[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007AC[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007AC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007AC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007AC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007B0[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007B4[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF80007B8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000200U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007BC[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. Speed = 0
-    // .. ==> 0XF80007BC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007BC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007BC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007BC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007C0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C0[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C4[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C8[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF80007C8[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF80007C8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007CC[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007CC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007CC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007CC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF80007CC[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF80007CC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007CC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007CC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007CC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
-    // .. SDIO0_CD_SEL = 47
-    // .. ==> 0XF8000830[21:16] = 0x0000002FU
-    // ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000830, 0x003F0000U ,0x002F0000U),
-    // .. FINISH: MIO PROGRAMMING
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // .. 
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_peripherals_init_data_1_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // .. 
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
-    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // .. 
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // .. START: SRAM/NOR SET OPMODE
-    // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // .. 
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // .. 
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. IRMODE = 0x0
-    // .. ==> 0XE0001004[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. UCLKEN = 0x0
-    // .. ==> 0XE0001004[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
-    // .. BDIV = 0x6
-    // .. ==> 0XE0000034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // .. 
-    EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0000018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // .. 
-    EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0000000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0000000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0000000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0000000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0000000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0000000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0000000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0000000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0000000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
-    EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
-    // .. IRMODE = 0x0
-    // .. ==> 0XE0000004[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. UCLKEN = 0x0
-    // .. ==> 0XE0000004[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0000004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0000004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0000004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0000004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0000004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
-    // .. START: PL POWER ON RESET REGISTERS
-    // .. PCFG_POR_CNT_4K = 0
-    // .. ==> 0XF8007000[29:29] = 0x00000000U
-    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
-    // .. FINISH: PL POWER ON RESET REGISTERS
-    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
-    // .. .. START: NAND SET CYCLE
-    // .. .. FINISH: NAND SET CYCLE
-    // .. .. START: OPMODE
-    // .. .. FINISH: OPMODE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: SRAM/NOR CS0 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS0 BASE ADDRESS
-    // .. .. FINISH: NOR CS0 BASE ADDRESS
-    // .. .. START: SRAM/NOR CS1 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS1 BASE ADDRESS
-    // .. .. FINISH: NOR CS1 BASE ADDRESS
-    // .. .. START: USB RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. DIRECTION_1 = 0x4000
-    // .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. DATA_1_LSW = 0x4000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. OP_ENABLE_1 = 0x4000
-    // .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. DATA_1_LSW = 0x0
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. DATA_1_LSW = 0x4000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. FINISH: USB RESET
-    // .. .. START: ENET RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. FINISH: ENET RESET
-    // .. .. START: I2C RESET
-    // .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. FINISH: I2C RESET
-    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_post_config_1_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // .. 
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: ENABLING LEVEL SHIFTER
-    // .. USER_INP_ICT_EN_0 = 3
-    // .. ==> 0XF8000900[1:0] = 0x00000003U
-    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
-    // .. USER_INP_ICT_EN_1 = 3
-    // .. ==> 0XF8000900[3:2] = 0x00000003U
-    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
-    // .. 
-    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
-    // .. FINISH: ENABLING LEVEL SHIFTER
-    // .. START: FPGA RESETS TO 1
-    // .. reserved_3 = 127
-    // .. ==> 0XF8000240[31:25] = 0x0000007FU
-    // ..     ==> MASK : 0xFE000000U    VAL : 0xFE000000U
-    // .. FPGA_ACP_RST = 1
-    // .. ==> 0XF8000240[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. FPGA_AXDS3_RST = 1
-    // .. ==> 0XF8000240[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. FPGA_AXDS2_RST = 1
-    // .. ==> 0XF8000240[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. FPGA_AXDS1_RST = 1
-    // .. ==> 0XF8000240[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. FPGA_AXDS0_RST = 1
-    // .. ==> 0XF8000240[20:20] = 0x00000001U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00100000U
-    // .. reserved_2 = 3
-    // .. ==> 0XF8000240[19:18] = 0x00000003U
-    // ..     ==> MASK : 0x000C0000U    VAL : 0x000C0000U
-    // .. FSSW1_FPGA_RST = 1
-    // .. ==> 0XF8000240[17:17] = 0x00000001U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
-    // .. FSSW0_FPGA_RST = 1
-    // .. ==> 0XF8000240[16:16] = 0x00000001U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. reserved_1 = 15
-    // .. ==> 0XF8000240[15:14] = 0x0000000FU
-    // ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
-    // .. FPGA_FMSW1_RST = 1
-    // .. ==> 0XF8000240[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. FPGA_FMSW0_RST = 1
-    // .. ==> 0XF8000240[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. FPGA_DMA3_RST = 1
-    // .. ==> 0XF8000240[11:11] = 0x00000001U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000800U
-    // .. FPGA_DMA2_RST = 1
-    // .. ==> 0XF8000240[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. FPGA_DMA1_RST = 1
-    // .. ==> 0XF8000240[9:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. FPGA_DMA0_RST = 1
-    // .. ==> 0XF8000240[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. reserved = 15
-    // .. ==> 0XF8000240[7:4] = 0x0000000FU
-    // ..     ==> MASK : 0x000000F0U    VAL : 0x000000F0U
-    // .. FPGA3_OUT_RST = 1
-    // .. ==> 0XF8000240[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. FPGA2_OUT_RST = 1
-    // .. ==> 0XF8000240[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. FPGA1_OUT_RST = 1
-    // .. ==> 0XF8000240[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. FPGA0_OUT_RST = 1
-    // .. ==> 0XF8000240[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
-    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0xFFFFFFFFU),
-    // .. FINISH: FPGA RESETS TO 1
-    // .. START: FPGA RESETS TO 0
-    // .. reserved_3 = 0
-    // .. ==> 0XF8000240[31:25] = 0x00000000U
-    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
-    // .. FPGA_ACP_RST = 0
-    // .. ==> 0XF8000240[24:24] = 0x00000000U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. FPGA_AXDS3_RST = 0
-    // .. ==> 0XF8000240[23:23] = 0x00000000U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. FPGA_AXDS2_RST = 0
-    // .. ==> 0XF8000240[22:22] = 0x00000000U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. FPGA_AXDS1_RST = 0
-    // .. ==> 0XF8000240[21:21] = 0x00000000U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. FPGA_AXDS0_RST = 0
-    // .. ==> 0XF8000240[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. reserved_2 = 0
-    // .. ==> 0XF8000240[19:18] = 0x00000000U
-    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. FSSW1_FPGA_RST = 0
-    // .. ==> 0XF8000240[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. FSSW0_FPGA_RST = 0
-    // .. ==> 0XF8000240[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reserved_1 = 0
-    // .. ==> 0XF8000240[15:14] = 0x00000000U
-    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
-    // .. FPGA_FMSW1_RST = 0
-    // .. ==> 0XF8000240[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. FPGA_FMSW0_RST = 0
-    // .. ==> 0XF8000240[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. FPGA_DMA3_RST = 0
-    // .. ==> 0XF8000240[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. FPGA_DMA2_RST = 0
-    // .. ==> 0XF8000240[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. FPGA_DMA1_RST = 0
-    // .. ==> 0XF8000240[9:9] = 0x00000000U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. FPGA_DMA0_RST = 0
-    // .. ==> 0XF8000240[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. reserved = 0
-    // .. ==> 0XF8000240[7:4] = 0x00000000U
-    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. FPGA3_OUT_RST = 0
-    // .. ==> 0XF8000240[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. FPGA2_OUT_RST = 0
-    // .. ==> 0XF8000240[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. FPGA1_OUT_RST = 0
-    // .. ==> 0XF8000240[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. FPGA0_OUT_RST = 0
-    // .. ==> 0XF8000240[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
-    // .. FINISH: FPGA RESETS TO 0
-    // .. START: AFI REGISTERS
-    // .. .. START: AFI0 REGISTERS
-    // .. .. FINISH: AFI0 REGISTERS
-    // .. .. START: AFI1 REGISTERS
-    // .. .. FINISH: AFI1 REGISTERS
-    // .. .. START: AFI2 REGISTERS
-    // .. .. FINISH: AFI2 REGISTERS
-    // .. .. START: AFI3 REGISTERS
-    // .. .. FINISH: AFI3 REGISTERS
-    // .. FINISH: AFI REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // .. 
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_pll_init_data_2_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // .. 
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: PLL SLCR REGISTERS
-    // .. .. START: ARM PLL INIT
-    // .. .. PLL_RES = 0xc
-    // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x177
-    // .. .. ==> 0XF8000110[21:12] = 0x00000177U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00177000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001772C0U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x1a
-    // .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001A000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001A000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. ARM_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. .. 
-    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. SRCSEL = 0x0
-    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. .. .. DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
-    // .. .. .. CPU_6OR4XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. .. .. CPU_3OR2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
-    // .. .. .. CPU_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. .. CPU_1XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. .. CPU_PERI_CLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
-    // .. .. FINISH: ARM PLL INIT
-    // .. .. START: DDR PLL INIT
-    // .. .. PLL_RES = 0xc
-    // .. .. ==> 0XF8000114[7:4] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x1db
-    // .. .. ==> 0XF8000114[21:12] = 0x000001DBU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x001DB000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x001DB2C0U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x15
-    // .. .. .. ==> 0XF8000104[18:12] = 0x00000015U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00015000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00015000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. DDR_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. .. 
-    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. DDR_3XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. .. DDR_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
-    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
-    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
-    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
-    // .. .. FINISH: DDR PLL INIT
-    // .. .. START: IO PLL INIT
-    // .. .. PLL_RES = 0xc
-    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x1f4
-    // .. .. ==> 0XF8000118[21:12] = 0x000001F4U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x001F4000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001F42C0U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x14
-    // .. .. .. ==> 0XF8000108[18:12] = 0x00000014U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00014000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00014000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. IO_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. .. .. 
-    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. FINISH: IO PLL INIT
-    // .. FINISH: PLL SLCR REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // .. 
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_clock_init_data_2_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // .. 
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: CLOCK CONTROL SLCR REGISTERS
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000128[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. DIVISOR0 = 0x34
-    // .. ==> 0XF8000128[13:8] = 0x00000034U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00003400U
-    // .. DIVISOR1 = 0x2
-    // .. ==> 0XF8000128[25:20] = 0x00000002U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00203401U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000138[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000138[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000140[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000140[6:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. DIVISOR = 0x8
-    // .. ==> 0XF8000140[13:8] = 0x00000008U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000140[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF800014C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF800014C[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF800014C[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // .. 
-    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
-    // .. CLKACT0 = 0x1
-    // .. ==> 0XF8000150[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. CLKACT1 = 0x0
-    // .. ==> 0XF8000150[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000150[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000150[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. 
-    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
-    // .. CLKACT0 = 0x1
-    // .. ==> 0XF8000154[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. CLKACT1 = 0x1
-    // .. ==> 0XF8000154[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000154[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000154[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. 
-    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // .. 
-    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0xa
-    // .. ==> 0XF8000170[13:8] = 0x0000000AU
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
-    // .. SRCSEL = 0x3
-    // .. ==> 0XF8000180[5:4] = 0x00000003U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000030U
-    // .. DIVISOR0 = 0x6
-    // .. ==> 0XF8000180[13:8] = 0x00000006U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000600U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100630U),
-    // .. SRCSEL = 0x2
-    // .. ==> 0XF8000190[5:4] = 0x00000002U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000020U
-    // .. DIVISOR0 = 0x35
-    // .. ==> 0XF8000190[13:8] = 0x00000035U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00003500U
-    // .. DIVISOR1 = 0x2
-    // .. ==> 0XF8000190[25:20] = 0x00000002U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00203520U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0xa
-    // .. ==> 0XF80001A0[13:8] = 0x0000000AU
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
-    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100A00U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
-    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[20:20] = 0x00000001U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00100000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FC044DU),
-    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
-    // .. START: THIS SHOULD BE BLANK
-    // .. FINISH: THIS SHOULD BE BLANK
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // .. 
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_ddr_init_data_2_0[] = {
-    // START: top
-    // .. START: DDR INITIALIZATION
-    // .. .. START: LOCK DDR
-    // .. .. reg_ddrc_soft_rstb = 0
-    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_powerdown_en = 0x0
-    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_data_bus_width = 0x0
-    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. .. reg_ddrc_burst8_refresh = 0x0
-    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
-    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_act_bypass = 0x0
-    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
-    // .. .. FINISH: LOCK DDR
-    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f
-    // .. .. ==> 0XF8006004[11:0] = 0x0000007FU
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x0000007FU
-    // .. .. reg_ddrc_active_ranks = 0x1
-    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
-    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
-    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_wr_odt_block = 0x1
-    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
-    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
-    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
-    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
-    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_open_bank = 0x0
-    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
-    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x0008107FU),
-    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
-    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
-    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
-    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
-    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
-    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
-    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
-    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
-    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
-    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
-    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_w_xact_run_length = 0x8
-    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
-    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
-    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
-    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
-    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
-    // .. .. reg_ddrc_t_rc = 0x1a
-    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
-    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
-    // .. .. reg_ddrc_t_rfc_min = 0x54
-    // .. .. ==> 0XF8006014[13:6] = 0x00000054U
-    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001500U
-    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
-    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
-    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004151AU),
-    // .. .. reg_ddrc_wr2pre = 0x12
-    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
-    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
-    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
-    // .. .. reg_ddrc_t_faw = 0x15
-    // .. .. ==> 0XF8006018[15:10] = 0x00000015U
-    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005400U
-    // .. .. reg_ddrc_t_ras_max = 0x23
-    // .. .. ==> 0XF8006018[21:16] = 0x00000023U
-    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00230000U
-    // .. .. reg_ddrc_t_ras_min = 0x13
-    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
-    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
-    // .. .. reg_ddrc_t_cke = 0x4
-    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E354D2U),
-    // .. .. reg_ddrc_write_latency = 0x5
-    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
-    // .. .. reg_ddrc_rd2wr = 0x7
-    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
-    // .. .. reg_ddrc_wr2rd = 0xe
-    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
-    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
-    // .. .. reg_ddrc_t_xp = 0x4
-    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
-    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
-    // .. .. reg_ddrc_pad_pd = 0x0
-    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd2pre = 0x4
-    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
-    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
-    // .. .. reg_ddrc_t_rcd = 0x7
-    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
-    // .. .. reg_ddrc_t_ccd = 0x4
-    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
-    // .. .. reg_ddrc_t_rrd = 0x6
-    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
-    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
-    // .. .. reg_ddrc_refresh_margin = 0x2
-    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. reg_ddrc_t_rp = 0x7
-    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
-    // .. .. reg_ddrc_refresh_to_x32 = 0x8
-    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
-    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
-    // .. .. reg_ddrc_sdram = 0x1
-    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. .. reg_ddrc_mobile = 0x0
-    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_clock_stop_en = 0x0
-    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
-    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_read_latency = 0x7
-    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
-    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
-    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
-    // .. .. reg_ddrc_dis_pad_pd = 0x0
-    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
-    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_loopback = 0x0
-    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
-    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
-    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
-    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_prefer_write = 0x0
-    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_max_rank_rd = 0xf
-    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
-    // .. .. reg_ddrc_mr_wr = 0x0
-    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_addr = 0x0
-    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_data = 0x0
-    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
-    // .. .. ddrc_reg_mr_wr_busy = 0x0
-    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_type = 0x0
-    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_rdata_valid = 0x0
-    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
-    // .. .. reg_ddrc_final_wait_x32 = 0x7
-    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
-    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
-    // .. .. reg_ddrc_t_mrd = 0x4
-    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
-    // .. .. reg_ddrc_emr2 = 0x8
-    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
-    // .. .. reg_ddrc_emr3 = 0x0
-    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
-    // .. .. reg_ddrc_mr = 0x930
-    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
-    // .. .. reg_ddrc_emr = 0x4
-    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
-    // .. .. reg_ddrc_burst_rdwr = 0x4
-    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x101
-    // .. .. ==> 0XF8006034[13:4] = 0x00000101U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001010U
-    // .. .. reg_ddrc_post_cke_x1024 = 0x1
-    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
-    // .. .. reg_ddrc_burstchop = 0x0
-    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011014U),
-    // .. .. reg_ddrc_force_low_pri_n = 0x0
-    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_dq = 0x0
-    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_debug_mode = 0x0
-    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_level_start = 0x0
-    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_level_start = 0x0
-    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_phy_dq0_wait_t = 0x0
-    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
-    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
-    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
-    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
-    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
-    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
-    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
-    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
-    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
-    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
-    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
-    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
-    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
-    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
-    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
-    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
-    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
-    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
-    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
-    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
-    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
-    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
-    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
-    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
-    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
-    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
-    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
-    // .. .. reg_ddrc_addrmap_row_b14 = 0xf
-    // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
-    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
-    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
-    // .. .. reg_ddrc_rank0_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank0_wr_odt = 0x1
-    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
-    // .. .. reg_ddrc_rank1_rd_odt = 0x1
-    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
-    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
-    // .. .. reg_ddrc_rank1_wr_odt = 0x1
-    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. .. reg_phy_rd_local_odt = 0x0
-    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_local_odt = 0x3
-    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
-    // .. .. reg_phy_idle_local_odt = 0x3
-    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
-    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
-    // .. .. reg_ddrc_rank2_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank2_wr_odt = 0x0
-    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank3_rd_odt = 0x0
-    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rank3_wr_odt = 0x0
-    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
-    // .. .. reg_phy_rd_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_phy_wr_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
-    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
-    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
-    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_phy_use_fixed_re = 0x1
-    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
-    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
-    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_phy_clk_stall_level = 0x0
-    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
-    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
-    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
-    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
-    // .. .. reg_ddrc_dis_dll_calib = 0x0
-    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
-    // .. .. reg_ddrc_rd_odt_delay = 0x3
-    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
-    // .. .. reg_ddrc_wr_odt_delay = 0x0
-    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd_odt_hold = 0x0
-    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_wr_odt_hold = 0x5
-    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
-    // .. .. reg_ddrc_pageclose = 0x0
-    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_lpr_num_entries = 0x1f
-    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
-    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
-    // .. .. reg_ddrc_auto_pre_en = 0x0
-    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. .. reg_ddrc_refresh_update_level = 0x0
-    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_wc = 0x0
-    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
-    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_ddrc_selfref_en = 0x0
-    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
-    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
-    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
-    // .. .. reg_arb_go2critical_en = 0x1
-    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
-    // .. .. reg_ddrc_wrlvl_ww = 0x41
-    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
-    // .. .. reg_ddrc_rdlvl_rr = 0x41
-    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
-    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
-    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
-    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
-    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
-    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
-    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
-    // .. .. 
-    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
-    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
-    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
-    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
-    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
-    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
-    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
-    // .. .. reg_ddrc_t_cksre = 0x6
-    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
-    // .. .. reg_ddrc_t_cksrx = 0x6
-    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
-    // .. .. reg_ddrc_t_ckesr = 0x4
-    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
-    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
-    // .. .. reg_ddrc_t_ckpde = 0x2
-    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
-    // .. .. reg_ddrc_t_ckpdx = 0x2
-    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. reg_ddrc_t_ckdpde = 0x2
-    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. reg_ddrc_t_ckdpdx = 0x2
-    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
-    // .. .. reg_ddrc_t_ckcsx = 0x3
-    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
-    // .. .. refresh_timer0_start_value_x32 = 0x0
-    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
-    // .. .. refresh_timer1_start_value_x32 = 0x8
-    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
-    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
-    // .. .. reg_ddrc_dis_auto_zq = 0x0
-    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_ddr3 = 0x1
-    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. reg_ddrc_t_mod = 0x200
-    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
-    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
-    // .. .. reg_ddrc_t_zq_long_nop = 0x200
-    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
-    // .. .. reg_ddrc_t_zq_short_nop = 0x40
-    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
-    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
-    // .. .. t_zq_short_interval_x1024 = 0xc845
-    // .. .. ==> 0XF80060A8[19:0] = 0x0000C845U
-    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000C845U
-    // .. .. dram_rstn_x1024 = 0x67
-    // .. .. ==> 0XF80060A8[27:20] = 0x00000067U
-    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06700000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0670C845U),
-    // .. .. deeppowerdown_en = 0x0
-    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. deeppowerdown_to_x1024 = 0xff
-    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
-    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
-    // .. .. 
-    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
-    // .. .. dfi_wrlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
-    // .. .. dfi_rdlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
-    // .. .. ddrc_reg_twrlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. .. ddrc_reg_trdlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
-    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
-    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
-    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
-    // .. .. reg_ddrc_2t_delay = 0x0
-    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
-    // .. .. reg_ddrc_skip_ocd = 0x1
-    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. .. reg_ddrc_dis_pre_bypass = 0x0
-    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
-    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
-    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
-    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
-    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
-    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
-    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. Clear_Correctable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. 
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
-    // .. FINISH: DDR INITIALIZATION
-    // .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
-    // .. ==> 0XF80060C4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. Clear_Correctable_DRAM_ECC_error = 0x0
-    // .. ==> 0XF80060C4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
-    // .. CORR_ECC_LOG_VALID = 0x0
-    // .. ==> 0XF80060C8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. ECC_CORRECTED_BIT_NUM = 0x0
-    // .. ==> 0XF80060C8[7:1] = 0x00000000U
-    // ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
-    // .. UNCORR_ECC_LOG_VALID = 0x0
-    // .. ==> 0XF80060DC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
-    // .. STAT_NUM_CORR_ERR = 0x0
-    // .. ==> 0XF80060F0[15:8] = 0x00000000U
-    // ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
-    // .. STAT_NUM_UNCORR_ERR = 0x0
-    // .. ==> 0XF80060F0[7:0] = 0x00000000U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
-    // .. reg_ddrc_ecc_mode = 0x0
-    // .. ==> 0XF80060F4[2:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
-    // .. reg_ddrc_dis_scrub = 0x1
-    // .. ==> 0XF80060F4[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. 
-    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
-    // .. reg_phy_dif_on = 0x0
-    // .. ==> 0XF8006114[3:0] = 0x00000000U
-    // ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. reg_phy_dif_off = 0x0
-    // .. ==> 0XF8006114[7:4] = 0x00000000U
-    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
-    // .. reg_phy_data_slice_in_use = 0x1
-    // .. ==> 0XF8006118[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. ==> 0XF8006118[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. ==> 0XF8006118[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. ==> 0XF8006118[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. reg_phy_board_lpbk_tx = 0x0
-    // .. ==> 0XF8006118[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. reg_phy_board_lpbk_rx = 0x0
-    // .. ==> 0XF8006118[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. reg_phy_bist_shift_dq = 0x0
-    // .. ==> 0XF8006118[14:6] = 0x00000000U
-    // ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. reg_phy_bist_err_clr = 0x0
-    // .. ==> 0XF8006118[23:15] = 0x00000000U
-    // ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. reg_phy_dq_offset = 0x40
-    // .. ==> 0XF8006118[30:24] = 0x00000040U
-    // ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
-    // .. reg_phy_data_slice_in_use = 0x1
-    // .. ==> 0XF800611C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. ==> 0XF800611C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. ==> 0XF800611C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. ==> 0XF800611C[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. reg_phy_board_lpbk_tx = 0x0
-    // .. ==> 0XF800611C[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. reg_phy_board_lpbk_rx = 0x0
-    // .. ==> 0XF800611C[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. reg_phy_bist_shift_dq = 0x0
-    // .. ==> 0XF800611C[14:6] = 0x00000000U
-    // ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. reg_phy_bist_err_clr = 0x0
-    // .. ==> 0XF800611C[23:15] = 0x00000000U
-    // ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. reg_phy_dq_offset = 0x40
-    // .. ==> 0XF800611C[30:24] = 0x00000040U
-    // ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
-    // .. reg_phy_data_slice_in_use = 0x1
-    // .. ==> 0XF8006120[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. ==> 0XF8006120[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. ==> 0XF8006120[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. ==> 0XF8006120[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. reg_phy_board_lpbk_tx = 0x0
-    // .. ==> 0XF8006120[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. reg_phy_board_lpbk_rx = 0x0
-    // .. ==> 0XF8006120[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. reg_phy_bist_shift_dq = 0x0
-    // .. ==> 0XF8006120[14:6] = 0x00000000U
-    // ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. reg_phy_bist_err_clr = 0x0
-    // .. ==> 0XF8006120[23:15] = 0x00000000U
-    // ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. reg_phy_dq_offset = 0x40
-    // .. ==> 0XF8006120[30:24] = 0x00000040U
-    // ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. reg_phy_data_slice_in_use = 0x1
-    // .. ==> 0XF8006120[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. ==> 0XF8006120[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. ==> 0XF8006120[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. ==> 0XF8006120[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. reg_phy_board_lpbk_tx = 0x0
-    // .. ==> 0XF8006120[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. reg_phy_board_lpbk_rx = 0x0
-    // .. ==> 0XF8006120[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. reg_phy_bist_shift_dq = 0x0
-    // .. ==> 0XF8006120[14:6] = 0x00000000U
-    // ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. reg_phy_bist_err_clr = 0x0
-    // .. ==> 0XF8006120[23:15] = 0x00000000U
-    // ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. reg_phy_dq_offset = 0x40
-    // .. ==> 0XF8006120[30:24] = 0x00000040U
-    // ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
-    // .. reg_phy_data_slice_in_use = 0x1
-    // .. ==> 0XF8006124[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. ==> 0XF8006124[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. ==> 0XF8006124[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. ==> 0XF8006124[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. reg_phy_board_lpbk_tx = 0x0
-    // .. ==> 0XF8006124[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. reg_phy_board_lpbk_rx = 0x0
-    // .. ==> 0XF8006124[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. reg_phy_bist_shift_dq = 0x0
-    // .. ==> 0XF8006124[14:6] = 0x00000000U
-    // ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. reg_phy_bist_err_clr = 0x0
-    // .. ==> 0XF8006124[23:15] = 0x00000000U
-    // ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. reg_phy_dq_offset = 0x40
-    // .. ==> 0XF8006124[30:24] = 0x00000040U
-    // ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
-    // .. reg_phy_wrlvl_init_ratio = 0x0
-    // .. ==> 0XF800612C[9:0] = 0x00000000U
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
-    // .. reg_phy_gatelvl_init_ratio = 0x8f
-    // .. ==> 0XF800612C[19:10] = 0x0000008FU
-    // ..     ==> MASK : 0x000FFC00U    VAL : 0x00023C00U
-    // .. 
-    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00023C00U),
-    // .. reg_phy_wrlvl_init_ratio = 0x0
-    // .. ==> 0XF8006130[9:0] = 0x00000000U
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
-    // .. reg_phy_gatelvl_init_ratio = 0x8a
-    // .. ==> 0XF8006130[19:10] = 0x0000008AU
-    // ..     ==> MASK : 0x000FFC00U    VAL : 0x00022800U
-    // .. 
-    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00022800U),
-    // .. reg_phy_wrlvl_init_ratio = 0x0
-    // .. ==> 0XF8006134[9:0] = 0x00000000U
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
-    // .. reg_phy_gatelvl_init_ratio = 0x8b
-    // .. ==> 0XF8006134[19:10] = 0x0000008BU
-    // ..     ==> MASK : 0x000FFC00U    VAL : 0x00022C00U
-    // .. 
-    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00022C00U),
-    // .. reg_phy_wrlvl_init_ratio = 0x0
-    // .. ==> 0XF8006138[9:0] = 0x00000000U
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
-    // .. reg_phy_gatelvl_init_ratio = 0x92
-    // .. ==> 0XF8006138[19:10] = 0x00000092U
-    // ..     ==> MASK : 0x000FFC00U    VAL : 0x00024800U
-    // .. 
-    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00024800U),
-    // .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. ==> 0XF8006140[9:0] = 0x00000035U
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. ==> 0XF8006140[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. ==> 0XF8006140[19:11] = 0x00000000U
-    // ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
-    // .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. ==> 0XF8006144[9:0] = 0x00000035U
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. ==> 0XF8006144[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. ==> 0XF8006144[19:11] = 0x00000000U
-    // ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
-    // .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. ==> 0XF8006148[9:0] = 0x00000035U
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. ==> 0XF8006148[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. ==> 0XF8006148[19:11] = 0x00000000U
-    // ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
-    // .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. ==> 0XF800614C[9:0] = 0x00000035U
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. ==> 0XF800614C[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. ==> 0XF800614C[19:11] = 0x00000000U
-    // ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
-    // .. reg_phy_wr_dqs_slave_ratio = 0x77
-    // .. ==> 0XF8006154[9:0] = 0x00000077U
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U
-    // .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. ==> 0XF8006154[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. ==> 0XF8006154[19:11] = 0x00000000U
-    // ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
-    // .. reg_phy_wr_dqs_slave_ratio = 0x7c
-    // .. ==> 0XF8006158[9:0] = 0x0000007CU
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU
-    // .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. ==> 0XF8006158[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. ==> 0XF8006158[19:11] = 0x00000000U
-    // ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU),
-    // .. reg_phy_wr_dqs_slave_ratio = 0x7c
-    // .. ==> 0XF800615C[9:0] = 0x0000007CU
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU
-    // .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. ==> 0XF800615C[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. ==> 0XF800615C[19:11] = 0x00000000U
-    // ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007CU),
-    // .. reg_phy_wr_dqs_slave_ratio = 0x75
-    // .. ==> 0XF8006160[9:0] = 0x00000075U
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x00000075U
-    // .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. ==> 0XF8006160[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. ==> 0XF8006160[19:11] = 0x00000000U
-    // ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000075U),
-    // .. reg_phy_fifo_we_slave_ratio = 0xe4
-    // .. ==> 0XF8006168[10:0] = 0x000000E4U
-    // ..     ==> MASK : 0x000007FFU    VAL : 0x000000E4U
-    // .. reg_phy_fifo_we_in_force = 0x0
-    // .. ==> 0XF8006168[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. reg_phy_fifo_we_in_delay = 0x0
-    // .. ==> 0XF8006168[20:12] = 0x00000000U
-    // ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000E4U),
-    // .. reg_phy_fifo_we_slave_ratio = 0xdf
-    // .. ==> 0XF800616C[10:0] = 0x000000DFU
-    // ..     ==> MASK : 0x000007FFU    VAL : 0x000000DFU
-    // .. reg_phy_fifo_we_in_force = 0x0
-    // .. ==> 0XF800616C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. reg_phy_fifo_we_in_delay = 0x0
-    // .. ==> 0XF800616C[20:12] = 0x00000000U
-    // ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000DFU),
-    // .. reg_phy_fifo_we_slave_ratio = 0xe0
-    // .. ==> 0XF8006170[10:0] = 0x000000E0U
-    // ..     ==> MASK : 0x000007FFU    VAL : 0x000000E0U
-    // .. reg_phy_fifo_we_in_force = 0x0
-    // .. ==> 0XF8006170[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. reg_phy_fifo_we_in_delay = 0x0
-    // .. ==> 0XF8006170[20:12] = 0x00000000U
-    // ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000E0U),
-    // .. reg_phy_fifo_we_slave_ratio = 0xe7
-    // .. ==> 0XF8006174[10:0] = 0x000000E7U
-    // ..     ==> MASK : 0x000007FFU    VAL : 0x000000E7U
-    // .. reg_phy_fifo_we_in_force = 0x0
-    // .. ==> 0XF8006174[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. reg_phy_fifo_we_in_delay = 0x0
-    // .. ==> 0XF8006174[20:12] = 0x00000000U
-    // ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000E7U),
-    // .. reg_phy_wr_data_slave_ratio = 0xb7
-    // .. ==> 0XF800617C[9:0] = 0x000000B7U
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U
-    // .. reg_phy_wr_data_slave_force = 0x0
-    // .. ==> 0XF800617C[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. reg_phy_wr_data_slave_delay = 0x0
-    // .. ==> 0XF800617C[19:11] = 0x00000000U
-    // ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
-    // .. reg_phy_wr_data_slave_ratio = 0xbc
-    // .. ==> 0XF8006180[9:0] = 0x000000BCU
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU
-    // .. reg_phy_wr_data_slave_force = 0x0
-    // .. ==> 0XF8006180[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. reg_phy_wr_data_slave_delay = 0x0
-    // .. ==> 0XF8006180[19:11] = 0x00000000U
-    // ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU),
-    // .. reg_phy_wr_data_slave_ratio = 0xbc
-    // .. ==> 0XF8006184[9:0] = 0x000000BCU
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU
-    // .. reg_phy_wr_data_slave_force = 0x0
-    // .. ==> 0XF8006184[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. reg_phy_wr_data_slave_delay = 0x0
-    // .. ==> 0XF8006184[19:11] = 0x00000000U
-    // ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BCU),
-    // .. reg_phy_wr_data_slave_ratio = 0xb5
-    // .. ==> 0XF8006188[9:0] = 0x000000B5U
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x000000B5U
-    // .. reg_phy_wr_data_slave_force = 0x0
-    // .. ==> 0XF8006188[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. reg_phy_wr_data_slave_delay = 0x0
-    // .. ==> 0XF8006188[19:11] = 0x00000000U
-    // ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B5U),
-    // .. reg_phy_loopback = 0x0
-    // .. ==> 0XF8006190[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. reg_phy_bl2 = 0x0
-    // .. ==> 0XF8006190[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. reg_phy_at_spd_atpg = 0x0
-    // .. ==> 0XF8006190[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. reg_phy_bist_enable = 0x0
-    // .. ==> 0XF8006190[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. reg_phy_bist_force_err = 0x0
-    // .. ==> 0XF8006190[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. reg_phy_bist_mode = 0x0
-    // .. ==> 0XF8006190[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. reg_phy_invert_clkout = 0x1
-    // .. ==> 0XF8006190[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. reg_phy_all_dq_mpr_rd_resp = 0x0
-    // .. ==> 0XF8006190[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. reg_phy_sel_logic = 0x0
-    // .. ==> 0XF8006190[9:9] = 0x00000000U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. reg_phy_ctrl_slave_ratio = 0x100
-    // .. ==> 0XF8006190[19:10] = 0x00000100U
-    // ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
-    // .. reg_phy_ctrl_slave_force = 0x0
-    // .. ==> 0XF8006190[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. reg_phy_ctrl_slave_delay = 0x0
-    // .. ==> 0XF8006190[27:21] = 0x00000000U
-    // ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
-    // .. reg_phy_use_rank0_delays = 0x1
-    // .. ==> 0XF8006190[28:28] = 0x00000001U
-    // ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. reg_phy_lpddr = 0x0
-    // .. ==> 0XF8006190[29:29] = 0x00000000U
-    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // .. reg_phy_cmd_latency = 0x0
-    // .. ==> 0XF8006190[30:30] = 0x00000000U
-    // ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. reg_phy_int_lpbk = 0x0
-    // .. ==> 0XF8006190[31:31] = 0x00000000U
-    // ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
-    // .. reg_phy_wr_rl_delay = 0x2
-    // .. ==> 0XF8006194[4:0] = 0x00000002U
-    // ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
-    // .. reg_phy_rd_rl_delay = 0x4
-    // .. ==> 0XF8006194[9:5] = 0x00000004U
-    // ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
-    // .. reg_phy_dll_lock_diff = 0xf
-    // .. ==> 0XF8006194[13:10] = 0x0000000FU
-    // ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
-    // .. reg_phy_use_wr_level = 0x1
-    // .. ==> 0XF8006194[14:14] = 0x00000001U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
-    // .. reg_phy_use_rd_dqs_gate_level = 0x1
-    // .. ==> 0XF8006194[15:15] = 0x00000001U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
-    // .. reg_phy_use_rd_data_eye_level = 0x1
-    // .. ==> 0XF8006194[16:16] = 0x00000001U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. reg_phy_dis_calib_rst = 0x0
-    // .. ==> 0XF8006194[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. reg_phy_ctrl_slave_delay = 0x0
-    // .. ==> 0XF8006194[19:18] = 0x00000000U
-    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
-    // .. reg_arb_page_addr_mask = 0x0
-    // .. ==> 0XF8006204[31:0] = 0x00000000U
-    // ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
-    // .. reg_arb_pri_wr_portn = 0x3ff
-    // .. ==> 0XF8006208[9:0] = 0x000003FFU
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. ==> 0XF8006208[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. ==> 0XF8006208[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. ==> 0XF8006208[18:18] = 0x00000000U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. reg_arb_dis_rmw_portn = 0x1
-    // .. ==> 0XF8006208[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
-    // .. reg_arb_pri_wr_portn = 0x3ff
-    // .. ==> 0XF800620C[9:0] = 0x000003FFU
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. ==> 0XF800620C[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. ==> 0XF800620C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. ==> 0XF800620C[18:18] = 0x00000000U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. reg_arb_dis_rmw_portn = 0x1
-    // .. ==> 0XF800620C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. 
-    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
-    // .. reg_arb_pri_wr_portn = 0x3ff
-    // .. ==> 0XF8006210[9:0] = 0x000003FFU
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. ==> 0XF8006210[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. ==> 0XF8006210[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. ==> 0XF8006210[18:18] = 0x00000000U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. reg_arb_dis_rmw_portn = 0x1
-    // .. ==> 0XF8006210[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
-    // .. reg_arb_pri_wr_portn = 0x3ff
-    // .. ==> 0XF8006214[9:0] = 0x000003FFU
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. ==> 0XF8006214[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. ==> 0XF8006214[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. ==> 0XF8006214[18:18] = 0x00000000U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. reg_arb_dis_rmw_portn = 0x1
-    // .. ==> 0XF8006214[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
-    // .. reg_arb_pri_rd_portn = 0x3ff
-    // .. ==> 0XF8006218[9:0] = 0x000003FFU
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. ==> 0XF8006218[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. ==> 0XF8006218[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. ==> 0XF8006218[18:18] = 0x00000000U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. ==> 0XF8006218[19:19] = 0x00000000U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
-    // .. reg_arb_pri_rd_portn = 0x3ff
-    // .. ==> 0XF800621C[9:0] = 0x000003FFU
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. ==> 0XF800621C[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. ==> 0XF800621C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. ==> 0XF800621C[18:18] = 0x00000000U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. ==> 0XF800621C[19:19] = 0x00000000U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
-    // .. reg_arb_pri_rd_portn = 0x3ff
-    // .. ==> 0XF8006220[9:0] = 0x000003FFU
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. ==> 0XF8006220[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. ==> 0XF8006220[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. ==> 0XF8006220[18:18] = 0x00000000U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. ==> 0XF8006220[19:19] = 0x00000000U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
-    // .. reg_arb_pri_rd_portn = 0x3ff
-    // .. ==> 0XF8006224[9:0] = 0x000003FFU
-    // ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. ==> 0XF8006224[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. ==> 0XF8006224[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. ==> 0XF8006224[18:18] = 0x00000000U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. ==> 0XF8006224[19:19] = 0x00000000U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
-    // .. reg_ddrc_lpddr2 = 0x0
-    // .. ==> 0XF80062A8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. reg_ddrc_per_bank_refresh = 0x0
-    // .. ==> 0XF80062A8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. reg_ddrc_derate_enable = 0x0
-    // .. ==> 0XF80062A8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. reg_ddrc_mr4_margin = 0x0
-    // .. ==> 0XF80062A8[11:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
-    // .. reg_ddrc_mr4_read_interval = 0x0
-    // .. ==> 0XF80062AC[31:0] = 0x00000000U
-    // ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
-    // .. reg_ddrc_min_stable_clock_x1 = 0x5
-    // .. ==> 0XF80062B0[3:0] = 0x00000005U
-    // ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
-    // .. reg_ddrc_idle_after_reset_x32 = 0x12
-    // .. ==> 0XF80062B0[11:4] = 0x00000012U
-    // ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
-    // .. reg_ddrc_t_mrw = 0x5
-    // .. ==> 0XF80062B0[21:12] = 0x00000005U
-    // ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
-    // .. 
-    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
-    // .. reg_ddrc_max_auto_init_x1024 = 0xa6
-    // .. ==> 0XF80062B4[7:0] = 0x000000A6U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x000000A6U
-    // .. reg_ddrc_dev_zqinit_x32 = 0x12
-    // .. ==> 0XF80062B4[17:8] = 0x00000012U
-    // ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
-    // .. 
-    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A6U),
-    // .. START: POLL ON DCI STATUS
-    // .. DONE = 1
-    // .. ==> 0XF8000B74[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. 
-    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
-    // .. FINISH: POLL ON DCI STATUS
-    // .. START: UNLOCK DDR
-    // .. reg_ddrc_soft_rstb = 0x1
-    // .. ==> 0XF8006000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. reg_ddrc_powerdown_en = 0x0
-    // .. ==> 0XF8006000[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. reg_ddrc_data_bus_width = 0x0
-    // .. ==> 0XF8006000[3:2] = 0x00000000U
-    // ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. reg_ddrc_burst8_refresh = 0x0
-    // .. ==> 0XF8006000[6:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. reg_ddrc_rdwr_idle_gap = 1
-    // .. ==> 0XF8006000[13:7] = 0x00000001U
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. ==> 0XF8006000[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. reg_ddrc_dis_act_bypass = 0x0
-    // .. ==> 0XF8006000[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. ==> 0XF8006000[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
-    // .. FINISH: UNLOCK DDR
-    // .. START: CHECK DDR STATUS
-    // .. ddrc_reg_operating_mode = 1
-    // .. ==> 0XF8006054[2:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
-    // .. 
-    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
-    // .. FINISH: CHECK DDR STATUS
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_mio_init_data_2_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // .. 
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: OCM REMAPPING
-    // .. VREF_EN = 0x1
-    // .. ==> 0XF8000B00[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. VREF_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B00[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. CLK_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B00[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. SRSTN_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B00[9:9] = 0x00000000U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
-    // .. FINISH: OCM REMAPPING
-    // .. START: DDRIOB SETTINGS
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B40[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B40[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B40[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B40[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B40[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B40[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B40[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B44[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B44[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B44[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B44[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B44[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B44[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B44[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B48[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B48[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B48[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B48[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B48[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B48[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B48[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B50[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B50[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B50[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B50[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B50[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B50[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B50[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B54[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B54[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B54[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B54[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCR_TYPE = 0x3
-    // .. ==> 0XF8000B54[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B54[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B54[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
-    // .. INP_POWER = 0x0
-    // .. ==> 0XF8000B58[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B58[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE = 0x0
-    // .. ==> 0XF8000B58[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B58[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCR_TYPE = 0x0
-    // .. ==> 0XF8000B58[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B58[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B58[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x1a
-    // .. ==> 0XF8000B5C[18:14] = 0x0000001AU
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00068000U
-    // .. SLEW_N = 0x1a
-    // .. ==> 0XF8000B5C[23:19] = 0x0000001AU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00D00000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x00D6861CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x6
-    // .. ==> 0XF8000B60[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. SLEW_N = 0x1f
-    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B60[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B60[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x6
-    // .. ==> 0XF8000B64[18:14] = 0x00000006U
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
-    // .. SLEW_N = 0x1f
-    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B64[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B64[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
-    // .. DRIVE_P = 0x1c
-    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
-    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
-    // .. DRIVE_N = 0xc
-    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
-    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
-    // .. SLEW_P = 0x1a
-    // .. ==> 0XF8000B68[18:14] = 0x0000001AU
-    // ..     ==> MASK : 0x0007C000U    VAL : 0x00068000U
-    // .. SLEW_N = 0x1a
-    // .. ==> 0XF8000B68[23:19] = 0x0000001AU
-    // ..     ==> MASK : 0x00F80000U    VAL : 0x00D00000U
-    // .. GTL = 0x0
-    // .. ==> 0XF8000B68[26:24] = 0x00000000U
-    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
-    // .. RTERM = 0x0
-    // .. ==> 0XF8000B68[31:27] = 0x00000000U
-    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00D6861CU),
-    // .. VREF_INT_EN = 0x0
-    // .. ==> 0XF8000B6C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. VREF_SEL = 0x0
-    // .. ==> 0XF8000B6C[4:1] = 0x00000000U
-    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U
-    // .. VREF_EXT_EN = 0x3
-    // .. ==> 0XF8000B6C[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. VREF_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
-    // .. REFIO_EN = 0x1
-    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. REFIO_TEST = 0x3
-    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
-    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
-    // .. REFIO_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DRST_B_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. CKE_PULLUP_EN = 0x0
-    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E60U),
-    // .. .. START: ASSERT RESET
-    // .. .. RESET = 1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
-    // .. .. FINISH: ASSERT RESET
-    // .. .. START: DEASSERT RESET
-    // .. .. RESET = 0
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
-    // .. .. FINISH: DEASSERT RESET
-    // .. .. RESET = 0x1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ENABLE = 0x1
-    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. VRP_TRI = 0x0
-    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. VRN_TRI = 0x0
-    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. VRP_OUT = 0x0
-    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. VRN_OUT = 0x1
-    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
-    // .. .. NREF_OPT1 = 0x0
-    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. .. NREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
-    // .. .. NREF_OPT4 = 0x1
-    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
-    // .. .. PREF_OPT1 = 0x0
-    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
-    // .. .. PREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
-    // .. .. UPDATE_CONTROL = 0x0
-    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. .. INIT_COMPLETE = 0x0
-    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. .. TST_CLK = 0x0
-    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. .. TST_HLN = 0x0
-    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
-    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. .. TST_HLP = 0x0
-    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. .. TST_RST = 0x0
-    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. INT_DCI_EN = 0x0
-    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
-    // .. FINISH: DDRIOB SETTINGS
-    // .. START: MIO PROGRAMMING
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000700[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000700[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000700[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000700[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000700[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000700[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000700[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000700[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000700[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000704[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000704[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000704[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000704[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000704[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000704[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000704[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000704[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000704[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000708[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000708[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000708[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000708[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000708[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000708[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000708[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000708[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000708[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800070C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800070C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800070C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800070C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800070C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800070C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF800070C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800070C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800070C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000710[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000710[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000710[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000710[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000710[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000710[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000710[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000710[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000710[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000714[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000714[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000714[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000714[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000714[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000714[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000714[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000714[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000714[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000718[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000718[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000718[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000718[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000718[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000718[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000718[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000718[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000718[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800071C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800071C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800071C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800071C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800071C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800071C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800071C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800071C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800071C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000720[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000720[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000720[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000720[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000720[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000720[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000720[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000720[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000720[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000724[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000724[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000724[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000724[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000724[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000724[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000724[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000724[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000724[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000728[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000728[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000728[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000728[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 2
-    // .. ==> 0XF8000728[7:5] = 0x00000002U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
-    // .. Speed = 0
-    // .. ==> 0XF8000728[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000728[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000728[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000728[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001640U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800072C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800072C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800072C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800072C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 2
-    // .. ==> 0XF800072C[7:5] = 0x00000002U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
-    // .. Speed = 0
-    // .. ==> 0XF800072C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800072C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 1
-    // .. ==> 0XF800072C[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800072C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001640U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000730[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000730[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000730[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000730[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 2
-    // .. ==> 0XF8000730[7:5] = 0x00000002U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
-    // .. Speed = 0
-    // .. ==> 0XF8000730[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000730[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000730[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000730[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001640U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000734[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000734[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000734[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000734[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 2
-    // .. ==> 0XF8000734[7:5] = 0x00000002U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
-    // .. Speed = 0
-    // .. ==> 0XF8000734[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000734[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000734[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000734[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001640U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000738[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000738[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000738[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000738[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000738[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000738[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000738[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000738[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000738[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800073C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800073C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800073C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800073C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800073C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800073C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800073C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800073C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800073C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000740[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000740[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000740[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000740[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000740[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000740[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000740[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000740[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000740[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002902U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000744[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000744[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000744[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000744[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000744[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000744[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000744[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000744[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000744[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002902U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000748[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000748[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000748[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000748[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000748[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000748[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000748[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000748[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000748[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002902U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800074C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800074C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800074C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800074C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800074C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800074C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF800074C[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF800074C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF800074C[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. 
-    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002902U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000750[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000750[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000750[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000750[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000750[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000750[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000750[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000750[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000750[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002902U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000754[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000754[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000754[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000754[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000754[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000754[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000754[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000754[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000754[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002902U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000758[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000758[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000758[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000758[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000758[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000758[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000758[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000758[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000758[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000903U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800075C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800075C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800075C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800075C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800075C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800075C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF800075C[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF800075C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800075C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000903U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000760[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000760[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000760[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000760[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000760[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000760[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000760[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000760[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000760[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000903U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000764[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000764[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000764[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000764[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000764[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000764[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000764[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000764[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000764[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000903U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000768[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000768[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000768[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000768[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000768[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000768[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000768[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000768[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000768[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000903U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800076C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800076C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800076C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800076C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800076C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800076C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF800076C[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF800076C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800076C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000903U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000770[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000770[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000770[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000770[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000770[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000770[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000770[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000770[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000770[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000774[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000774[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000774[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000774[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000774[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000774[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000774[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000774[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000774[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000778[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000778[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000778[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000778[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000778[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000778[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000778[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000778[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000778[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800077C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800077C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800077C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800077C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800077C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800077C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF800077C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800077C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800077C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000780[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000780[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000780[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000780[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000780[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000780[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000780[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000780[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000780[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000784[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000784[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000784[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000784[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000784[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000784[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000784[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000784[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000784[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000788[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000788[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000788[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000788[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000788[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000788[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000788[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000788[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000788[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800078C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800078C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800078C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800078C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800078C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800078C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF800078C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800078C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800078C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000790[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000790[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000790[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000790[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000790[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000790[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000790[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000790[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000790[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000794[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000794[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000794[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000794[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000794[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000794[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000794[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000794[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000794[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000798[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000798[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000798[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000798[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000798[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000798[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000798[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000798[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000798[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800079C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800079C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800079C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800079C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800079C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800079C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF800079C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800079C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800079C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007A0[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007A4[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A8[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007A8[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007AC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007AC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007AC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007AC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007AC[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007AC[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007AC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007AC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007AC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007B0[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007B4[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF80007B8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000200U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007BC[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. Speed = 0
-    // .. ==> 0XF80007BC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007BC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007BC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007BC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007C0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C0[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C4[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C8[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF80007C8[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF80007C8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007CC[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007CC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007CC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007CC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF80007CC[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF80007CC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007CC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007CC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007CC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
-    // .. SDIO0_CD_SEL = 47
-    // .. ==> 0XF8000830[21:16] = 0x0000002FU
-    // ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000830, 0x003F0000U ,0x002F0000U),
-    // .. FINISH: MIO PROGRAMMING
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // .. 
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_peripherals_init_data_2_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // .. 
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
-    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // .. 
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // .. START: SRAM/NOR SET OPMODE
-    // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // .. 
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // .. 
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. IRMODE = 0x0
-    // .. ==> 0XE0001004[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. UCLKEN = 0x0
-    // .. ==> 0XE0001004[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
-    // .. BDIV = 0x6
-    // .. ==> 0XE0000034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // .. 
-    EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0000018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // .. 
-    EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0000000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0000000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0000000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0000000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0000000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0000000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0000000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0000000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0000000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
-    EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
-    // .. IRMODE = 0x0
-    // .. ==> 0XE0000004[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. UCLKEN = 0x0
-    // .. ==> 0XE0000004[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0000004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0000004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0000004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0000004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0000004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
-    // .. START: QSPI REGISTERS
-    // .. Holdb_dr = 1
-    // .. ==> 0XE000D000[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. 
-    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
-    // .. FINISH: QSPI REGISTERS
-    // .. START: PL POWER ON RESET REGISTERS
-    // .. PCFG_POR_CNT_4K = 0
-    // .. ==> 0XF8007000[29:29] = 0x00000000U
-    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
-    // .. FINISH: PL POWER ON RESET REGISTERS
-    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
-    // .. .. START: NAND SET CYCLE
-    // .. .. FINISH: NAND SET CYCLE
-    // .. .. START: OPMODE
-    // .. .. FINISH: OPMODE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: SRAM/NOR CS0 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS0 BASE ADDRESS
-    // .. .. FINISH: NOR CS0 BASE ADDRESS
-    // .. .. START: SRAM/NOR CS1 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS1 BASE ADDRESS
-    // .. .. FINISH: NOR CS1 BASE ADDRESS
-    // .. .. START: USB RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. DIRECTION_1 = 0x4000
-    // .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. DATA_1_LSW = 0x4000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. OP_ENABLE_1 = 0x4000
-    // .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. DATA_1_LSW = 0x0
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. DATA_1_LSW = 0x4000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. FINISH: USB RESET
-    // .. .. START: ENET RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. FINISH: ENET RESET
-    // .. .. START: I2C RESET
-    // .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. FINISH: I2C RESET
-    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_post_config_2_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // .. 
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: ENABLING LEVEL SHIFTER
-    // .. USER_INP_ICT_EN_0 = 3
-    // .. ==> 0XF8000900[1:0] = 0x00000003U
-    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
-    // .. USER_INP_ICT_EN_1 = 3
-    // .. ==> 0XF8000900[3:2] = 0x00000003U
-    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
-    // .. 
-    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
-    // .. FINISH: ENABLING LEVEL SHIFTER
-    // .. START: FPGA RESETS TO 1
-    // .. reserved_3 = 127
-    // .. ==> 0XF8000240[31:25] = 0x0000007FU
-    // ..     ==> MASK : 0xFE000000U    VAL : 0xFE000000U
-    // .. FPGA_ACP_RST = 1
-    // .. ==> 0XF8000240[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. FPGA_AXDS3_RST = 1
-    // .. ==> 0XF8000240[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. FPGA_AXDS2_RST = 1
-    // .. ==> 0XF8000240[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. FPGA_AXDS1_RST = 1
-    // .. ==> 0XF8000240[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. FPGA_AXDS0_RST = 1
-    // .. ==> 0XF8000240[20:20] = 0x00000001U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00100000U
-    // .. reserved_2 = 3
-    // .. ==> 0XF8000240[19:18] = 0x00000003U
-    // ..     ==> MASK : 0x000C0000U    VAL : 0x000C0000U
-    // .. FSSW1_FPGA_RST = 1
-    // .. ==> 0XF8000240[17:17] = 0x00000001U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
-    // .. FSSW0_FPGA_RST = 1
-    // .. ==> 0XF8000240[16:16] = 0x00000001U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. reserved_1 = 15
-    // .. ==> 0XF8000240[15:14] = 0x0000000FU
-    // ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
-    // .. FPGA_FMSW1_RST = 1
-    // .. ==> 0XF8000240[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. FPGA_FMSW0_RST = 1
-    // .. ==> 0XF8000240[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. FPGA_DMA3_RST = 1
-    // .. ==> 0XF8000240[11:11] = 0x00000001U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000800U
-    // .. FPGA_DMA2_RST = 1
-    // .. ==> 0XF8000240[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. FPGA_DMA1_RST = 1
-    // .. ==> 0XF8000240[9:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. FPGA_DMA0_RST = 1
-    // .. ==> 0XF8000240[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. reserved = 15
-    // .. ==> 0XF8000240[7:4] = 0x0000000FU
-    // ..     ==> MASK : 0x000000F0U    VAL : 0x000000F0U
-    // .. FPGA3_OUT_RST = 1
-    // .. ==> 0XF8000240[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. FPGA2_OUT_RST = 1
-    // .. ==> 0XF8000240[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. FPGA1_OUT_RST = 1
-    // .. ==> 0XF8000240[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. FPGA0_OUT_RST = 1
-    // .. ==> 0XF8000240[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
-    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0xFFFFFFFFU),
-    // .. FINISH: FPGA RESETS TO 1
-    // .. START: FPGA RESETS TO 0
-    // .. reserved_3 = 0
-    // .. ==> 0XF8000240[31:25] = 0x00000000U
-    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
-    // .. FPGA_ACP_RST = 0
-    // .. ==> 0XF8000240[24:24] = 0x00000000U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. FPGA_AXDS3_RST = 0
-    // .. ==> 0XF8000240[23:23] = 0x00000000U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. FPGA_AXDS2_RST = 0
-    // .. ==> 0XF8000240[22:22] = 0x00000000U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. FPGA_AXDS1_RST = 0
-    // .. ==> 0XF8000240[21:21] = 0x00000000U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. FPGA_AXDS0_RST = 0
-    // .. ==> 0XF8000240[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. reserved_2 = 0
-    // .. ==> 0XF8000240[19:18] = 0x00000000U
-    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. FSSW1_FPGA_RST = 0
-    // .. ==> 0XF8000240[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. FSSW0_FPGA_RST = 0
-    // .. ==> 0XF8000240[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reserved_1 = 0
-    // .. ==> 0XF8000240[15:14] = 0x00000000U
-    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
-    // .. FPGA_FMSW1_RST = 0
-    // .. ==> 0XF8000240[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. FPGA_FMSW0_RST = 0
-    // .. ==> 0XF8000240[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. FPGA_DMA3_RST = 0
-    // .. ==> 0XF8000240[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. FPGA_DMA2_RST = 0
-    // .. ==> 0XF8000240[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. FPGA_DMA1_RST = 0
-    // .. ==> 0XF8000240[9:9] = 0x00000000U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. FPGA_DMA0_RST = 0
-    // .. ==> 0XF8000240[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. reserved = 0
-    // .. ==> 0XF8000240[7:4] = 0x00000000U
-    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. FPGA3_OUT_RST = 0
-    // .. ==> 0XF8000240[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. FPGA2_OUT_RST = 0
-    // .. ==> 0XF8000240[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. FPGA1_OUT_RST = 0
-    // .. ==> 0XF8000240[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. FPGA0_OUT_RST = 0
-    // .. ==> 0XF8000240[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
-    // .. FINISH: FPGA RESETS TO 0
-    // .. START: AFI REGISTERS
-    // .. .. START: AFI0 REGISTERS
-    // .. .. FINISH: AFI0 REGISTERS
-    // .. .. START: AFI1 REGISTERS
-    // .. .. FINISH: AFI1 REGISTERS
-    // .. .. START: AFI2 REGISTERS
-    // .. .. FINISH: AFI2 REGISTERS
-    // .. .. START: AFI3 REGISTERS
-    // .. .. FINISH: AFI3 REGISTERS
-    // .. FINISH: AFI REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // .. 
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_pll_init_data_3_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // .. 
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: PLL SLCR REGISTERS
-    // .. .. START: ARM PLL INIT
-    // .. .. PLL_RES = 0xc
-    // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x177
-    // .. .. ==> 0XF8000110[21:12] = 0x00000177U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00177000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001772C0U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x1a
-    // .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001A000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001A000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. ARM_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. .. 
-    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. SRCSEL = 0x0
-    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. .. .. DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
-    // .. .. .. CPU_6OR4XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. .. .. CPU_3OR2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
-    // .. .. .. CPU_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. .. CPU_1XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. .. CPU_PERI_CLKACT = 0x1
-    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
-    // .. .. FINISH: ARM PLL INIT
-    // .. .. START: DDR PLL INIT
-    // .. .. PLL_RES = 0xc
-    // .. .. ==> 0XF8000114[7:4] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x1db
-    // .. .. ==> 0XF8000114[21:12] = 0x000001DBU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x001DB000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x001DB2C0U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x15
-    // .. .. .. ==> 0XF8000104[18:12] = 0x00000015U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00015000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00015000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. DDR_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. .. 
-    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. .. DDR_3XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. .. DDR_2XCLKACT = 0x1
-    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
-    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
-    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
-    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
-    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
-    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
-    // .. .. FINISH: DDR PLL INIT
-    // .. .. START: IO PLL INIT
-    // .. .. PLL_RES = 0xc
-    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
-    // .. .. PLL_CP = 0x2
-    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x1f4
-    // .. .. ==> 0XF8000118[21:12] = 0x000001F4U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x001F4000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001F42C0U),
-    // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x14
-    // .. .. .. ==> 0XF8000108[18:12] = 0x00000014U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00014000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00014000U),
-    // .. .. .. FINISH: UPDATE FB_DIV
-    // .. .. .. START: BY PASS PLL
-    // .. .. .. PLL_BYPASS_FORCE = 1
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
-    // .. .. .. FINISH: BY PASS PLL
-    // .. .. .. START: ASSERT RESET
-    // .. .. .. PLL_RESET = 1
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
-    // .. .. .. FINISH: ASSERT RESET
-    // .. .. .. START: DEASSERT RESET
-    // .. .. .. PLL_RESET = 0
-    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
-    // .. .. .. FINISH: DEASSERT RESET
-    // .. .. .. START: CHECK PLL STATUS
-    // .. .. .. IO_PLL_LOCK = 1
-    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
-    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. .. .. 
-    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
-    // .. .. .. FINISH: CHECK PLL STATUS
-    // .. .. .. START: REMOVE PLL BY PASS
-    // .. .. .. PLL_BYPASS_FORCE = 0
-    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
-    // .. .. .. FINISH: REMOVE PLL BY PASS
-    // .. .. FINISH: IO PLL INIT
-    // .. FINISH: PLL SLCR REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // .. 
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_clock_init_data_3_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // .. 
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: CLOCK CONTROL SLCR REGISTERS
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000128[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. DIVISOR0 = 0x34
-    // .. ==> 0XF8000128[13:8] = 0x00000034U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00003400U
-    // .. DIVISOR1 = 0x2
-    // .. ==> 0XF8000128[25:20] = 0x00000002U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00203401U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000138[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000138[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000140[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000140[6:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. DIVISOR = 0x8
-    // .. ==> 0XF8000140[13:8] = 0x00000008U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000140[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF800014C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF800014C[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF800014C[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // .. 
-    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
-    // .. CLKACT0 = 0x1
-    // .. ==> 0XF8000150[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. CLKACT1 = 0x0
-    // .. ==> 0XF8000150[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000150[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000150[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. 
-    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
-    // .. CLKACT0 = 0x1
-    // .. ==> 0XF8000154[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. CLKACT1 = 0x1
-    // .. ==> 0XF8000154[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000154[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x14
-    // .. ==> 0XF8000154[13:8] = 0x00000014U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
-    // .. 
-    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U),
-    // .. CLKACT = 0x1
-    // .. ==> 0XF8000168[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000168[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR = 0x5
-    // .. ==> 0XF8000168[13:8] = 0x00000005U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
-    // .. 
-    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000170[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0xa
-    // .. ==> 0XF8000170[13:8] = 0x0000000AU
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000170[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
-    // .. SRCSEL = 0x3
-    // .. ==> 0XF8000180[5:4] = 0x00000003U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000030U
-    // .. DIVISOR0 = 0x6
-    // .. ==> 0XF8000180[13:8] = 0x00000006U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000600U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF8000180[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100630U),
-    // .. SRCSEL = 0x2
-    // .. ==> 0XF8000190[5:4] = 0x00000002U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000020U
-    // .. DIVISOR0 = 0x35
-    // .. ==> 0XF8000190[13:8] = 0x00000035U
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00003500U
-    // .. DIVISOR1 = 0x2
-    // .. ==> 0XF8000190[25:20] = 0x00000002U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00203520U),
-    // .. SRCSEL = 0x0
-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
-    // .. DIVISOR0 = 0xa
-    // .. ==> 0XF80001A0[13:8] = 0x0000000AU
-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
-    // .. DIVISOR1 = 0x1
-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
-    // .. 
-    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100A00U),
-    // .. CLK_621_TRUE = 0x1
-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
-    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
-    // .. DMA_CPU_2XCLKACT = 0x1
-    // .. ==> 0XF800012C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. USB0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USB1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. GEM0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[6:6] = 0x00000001U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
-    // .. GEM1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. SDI0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. SDI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. SPI0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[14:14] = 0x00000000U
-    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. SPI1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[15:15] = 0x00000000U
-    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. CAN0_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. CAN1_CPU_1XCLKACT = 0x0
-    // .. ==> 0XF800012C[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. I2C0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[18:18] = 0x00000001U
-    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
-    // .. I2C1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. UART0_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[20:20] = 0x00000001U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00100000U
-    // .. UART1_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. GPIO_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. LQSPI_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. SMC_CPU_1XCLKACT = 0x1
-    // .. ==> 0XF800012C[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FC044DU),
-    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
-    // .. START: THIS SHOULD BE BLANK
-    // .. FINISH: THIS SHOULD BE BLANK
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // .. 
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_ddr_init_data_3_0[] = {
-    // START: top
-    // .. START: DDR INITIALIZATION
-    // .. .. START: LOCK DDR
-    // .. .. reg_ddrc_soft_rstb = 0
-    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_powerdown_en = 0x0
-    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_data_bus_width = 0x0
-    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. .. reg_ddrc_burst8_refresh = 0x0
-    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
-    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_act_bypass = 0x0
-    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
-    // .. .. FINISH: LOCK DDR
-    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f
-    // .. .. ==> 0XF8006004[11:0] = 0x0000007FU
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x0000007FU
-    // .. .. reserved_reg_ddrc_active_ranks = 0x1
-    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
-    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
-    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x0000107FU),
-    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
-    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
-    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
-    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
-    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
-    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
-    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
-    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
-    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
-    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
-    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
-    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
-    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
-    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
-    // .. .. reg_ddrc_w_xact_run_length = 0x8
-    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
-    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
-    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
-    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
-    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
-    // .. .. reg_ddrc_t_rc = 0x1a
-    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
-    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
-    // .. .. reg_ddrc_t_rfc_min = 0x54
-    // .. .. ==> 0XF8006014[13:6] = 0x00000054U
-    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001500U
-    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
-    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
-    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004151AU),
-    // .. .. reg_ddrc_wr2pre = 0x12
-    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
-    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
-    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
-    // .. .. reg_ddrc_t_faw = 0x15
-    // .. .. ==> 0XF8006018[15:10] = 0x00000015U
-    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005400U
-    // .. .. reg_ddrc_t_ras_max = 0x23
-    // .. .. ==> 0XF8006018[21:16] = 0x00000023U
-    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00230000U
-    // .. .. reg_ddrc_t_ras_min = 0x13
-    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
-    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
-    // .. .. reg_ddrc_t_cke = 0x4
-    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E354D2U),
-    // .. .. reg_ddrc_write_latency = 0x5
-    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
-    // .. .. reg_ddrc_rd2wr = 0x7
-    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
-    // .. .. reg_ddrc_wr2rd = 0xe
-    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
-    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
-    // .. .. reg_ddrc_t_xp = 0x4
-    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
-    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
-    // .. .. reg_ddrc_pad_pd = 0x0
-    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd2pre = 0x4
-    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
-    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
-    // .. .. reg_ddrc_t_rcd = 0x7
-    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
-    // .. .. reg_ddrc_t_ccd = 0x4
-    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
-    // .. .. reg_ddrc_t_rrd = 0x6
-    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
-    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
-    // .. .. reg_ddrc_refresh_margin = 0x2
-    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. reg_ddrc_t_rp = 0x7
-    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
-    // .. .. reg_ddrc_refresh_to_x32 = 0x8
-    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
-    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
-    // .. .. reg_ddrc_mobile = 0x0
-    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
-    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
-    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
-    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_read_latency = 0x7
-    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
-    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
-    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
-    // .. .. reg_ddrc_dis_pad_pd = 0x0
-    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
-    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
-    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
-    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_prefer_write = 0x0
-    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_wr = 0x0
-    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_addr = 0x0
-    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_data = 0x0
-    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
-    // .. .. ddrc_reg_mr_wr_busy = 0x0
-    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_type = 0x0
-    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr_rdata_valid = 0x0
-    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
-    // .. .. reg_ddrc_final_wait_x32 = 0x7
-    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
-    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
-    // .. .. reg_ddrc_t_mrd = 0x4
-    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
-    // .. .. reg_ddrc_emr2 = 0x8
-    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
-    // .. .. reg_ddrc_emr3 = 0x0
-    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
-    // .. .. reg_ddrc_mr = 0x930
-    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
-    // .. .. reg_ddrc_emr = 0x4
-    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
-    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
-    // .. .. reg_ddrc_burst_rdwr = 0x4
-    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
-    // .. .. reg_ddrc_pre_cke_x1024 = 0x101
-    // .. .. ==> 0XF8006034[13:4] = 0x00000101U
-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001010U
-    // .. .. reg_ddrc_post_cke_x1024 = 0x1
-    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
-    // .. .. reg_ddrc_burstchop = 0x0
-    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011014U),
-    // .. .. reg_ddrc_force_low_pri_n = 0x0
-    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_dq = 0x0
-    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
-    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
-    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
-    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
-    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
-    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
-    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
-    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
-    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
-    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
-    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
-    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
-    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
-    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
-    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
-    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
-    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
-    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
-    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
-    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
-    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
-    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
-    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
-    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
-    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
-    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
-    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
-    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
-    // .. .. reg_ddrc_addrmap_row_b14 = 0xf
-    // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
-    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
-    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
-    // .. .. reg_phy_rd_local_odt = 0x0
-    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_local_odt = 0x3
-    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
-    // .. .. reg_phy_idle_local_odt = 0x3
-    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
-    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
-    // .. .. reg_phy_rd_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_phy_wr_cmd_to_data = 0x0
-    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
-    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
-    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
-    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_phy_use_fixed_re = 0x1
-    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
-    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
-    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_phy_clk_stall_level = 0x0
-    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
-    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
-    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
-    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
-    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
-    // .. .. reg_ddrc_dis_dll_calib = 0x0
-    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
-    // .. .. reg_ddrc_rd_odt_delay = 0x3
-    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
-    // .. .. reg_ddrc_wr_odt_delay = 0x0
-    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rd_odt_hold = 0x0
-    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
-    // .. .. reg_ddrc_wr_odt_hold = 0x5
-    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
-    // .. .. reg_ddrc_pageclose = 0x0
-    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_lpr_num_entries = 0x1f
-    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
-    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
-    // .. .. reg_ddrc_auto_pre_en = 0x0
-    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. .. reg_ddrc_refresh_update_level = 0x0
-    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_wc = 0x0
-    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
-    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_ddrc_selfref_en = 0x0
-    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
-    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
-    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
-    // .. .. reg_arb_go2critical_en = 0x1
-    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
-    // .. .. reg_ddrc_wrlvl_ww = 0x41
-    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
-    // .. .. reg_ddrc_rdlvl_rr = 0x41
-    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
-    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
-    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
-    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
-    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
-    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
-    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
-    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
-    // .. .. 
-    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
-    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
-    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
-    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
-    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
-    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
-    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
-    // .. .. reg_ddrc_t_cksre = 0x6
-    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
-    // .. .. reg_ddrc_t_cksrx = 0x6
-    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
-    // .. .. reg_ddrc_t_ckesr = 0x4
-    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
-    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
-    // .. .. reg_ddrc_t_ckpde = 0x2
-    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
-    // .. .. reg_ddrc_t_ckpdx = 0x2
-    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
-    // .. .. reg_ddrc_t_ckdpde = 0x2
-    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
-    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. reg_ddrc_t_ckdpdx = 0x2
-    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
-    // .. .. reg_ddrc_t_ckcsx = 0x3
-    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
-    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
-    // .. .. reg_ddrc_dis_auto_zq = 0x0
-    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_ddr3 = 0x1
-    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. reg_ddrc_t_mod = 0x200
-    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
-    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
-    // .. .. reg_ddrc_t_zq_long_nop = 0x200
-    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
-    // .. .. reg_ddrc_t_zq_short_nop = 0x40
-    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
-    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
-    // .. .. t_zq_short_interval_x1024 = 0xc845
-    // .. .. ==> 0XF80060A8[19:0] = 0x0000C845U
-    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000C845U
-    // .. .. dram_rstn_x1024 = 0x67
-    // .. .. ==> 0XF80060A8[27:20] = 0x00000067U
-    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06700000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0670C845U),
-    // .. .. deeppowerdown_en = 0x0
-    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. deeppowerdown_to_x1024 = 0xff
-    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
-    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
-    // .. .. 
-    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
-    // .. .. dfi_wrlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
-    // .. .. dfi_rdlvl_max_x1024 = 0xfff
-    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
-    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
-    // .. .. ddrc_reg_twrlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
-    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. .. ddrc_reg_trdlvl_max_error = 0x0
-    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
-    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
-    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
-    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
-    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
-    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
-    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
-    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
-    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
-    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
-    // .. .. reg_ddrc_skip_ocd = 0x1
-    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. .. 
-    EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
-    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
-    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
-    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
-    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
-    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
-    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
-    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
-    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
-    // .. .. START: RESET ECC ERROR
-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. Clear_Correctable_DRAM_ECC_error = 1
-    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. 
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
-    // .. .. FINISH: RESET ECC ERROR
-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
-    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
-    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
-    // .. .. CORR_ECC_LOG_VALID = 0x0
-    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
-    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
-    // .. .. UNCORR_ECC_LOG_VALID = 0x0
-    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
-    // .. .. STAT_NUM_CORR_ERR = 0x0
-    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
-    // .. .. STAT_NUM_UNCORR_ERR = 0x0
-    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
-    // .. .. reg_ddrc_ecc_mode = 0x0
-    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_scrub = 0x1
-    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. .. 
-    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
-    // .. .. reg_phy_dif_on = 0x0
-    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
-    // .. .. reg_phy_dif_off = 0x0
-    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
-    // .. .. reg_phy_data_slice_in_use = 0x1
-    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_phy_rdlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_wrlvl_inc_mode = 0x0
-    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_shift_dq = 0x0
-    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_err_clr = 0x0
-    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
-    // .. .. reg_phy_dq_offset = 0x40
-    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
-    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x0
-    // .. .. ==> 0XF800612C[9:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_init_ratio = 0x8f
-    // .. .. ==> 0XF800612C[19:10] = 0x0000008FU
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00023C00U
-    // .. .. 
-    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00023C00U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x0
-    // .. .. ==> 0XF8006130[9:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_init_ratio = 0x8a
-    // .. .. ==> 0XF8006130[19:10] = 0x0000008AU
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00022800U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00022800U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x0
-    // .. .. ==> 0XF8006134[9:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_init_ratio = 0x8b
-    // .. .. ==> 0XF8006134[19:10] = 0x0000008BU
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00022C00U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00022C00U),
-    // .. .. reg_phy_wrlvl_init_ratio = 0x0
-    // .. .. ==> 0XF8006138[9:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
-    // .. .. reg_phy_gatelvl_init_ratio = 0x92
-    // .. .. ==> 0XF8006138[19:10] = 0x00000092U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00024800U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00024800U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
-    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
-    // .. .. reg_phy_rd_dqs_slave_force = 0x0
-    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
-    // .. .. ==> 0XF8006154[9:0] = 0x00000077U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
-    // .. .. ==> 0XF8006158[9:0] = 0x0000007CU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
-    // .. .. ==> 0XF800615C[9:0] = 0x0000007CU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007CU),
-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x75
-    // .. .. ==> 0XF8006160[9:0] = 0x00000075U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000075U
-    // .. .. reg_phy_wr_dqs_slave_force = 0x0
-    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
-    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000075U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0xe4
-    // .. .. ==> 0XF8006168[10:0] = 0x000000E4U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E4U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000E4U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0xdf
-    // .. .. ==> 0XF800616C[10:0] = 0x000000DFU
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000DFU
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000DFU),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0xe0
-    // .. .. ==> 0XF8006170[10:0] = 0x000000E0U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E0U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000E0U),
-    // .. .. reg_phy_fifo_we_slave_ratio = 0xe7
-    // .. .. ==> 0XF8006174[10:0] = 0x000000E7U
-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E7U
-    // .. .. reg_phy_fifo_we_in_force = 0x0
-    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. .. reg_phy_fifo_we_in_delay = 0x0
-    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
-    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000E7U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xb7
-    // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xbc
-    // .. .. ==> 0XF8006180[9:0] = 0x000000BCU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xbc
-    // .. .. ==> 0XF8006184[9:0] = 0x000000BCU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BCU),
-    // .. .. reg_phy_wr_data_slave_ratio = 0xb5
-    // .. .. ==> 0XF8006188[9:0] = 0x000000B5U
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B5U
-    // .. .. reg_phy_wr_data_slave_force = 0x0
-    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. .. reg_phy_wr_data_slave_delay = 0x0
-    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
-    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B5U),
-    // .. .. reg_phy_bl2 = 0x0
-    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_phy_at_spd_atpg = 0x0
-    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_enable = 0x0
-    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_force_err = 0x0
-    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. .. reg_phy_bist_mode = 0x0
-    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. .. reg_phy_invert_clkout = 0x1
-    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. .. reg_phy_sel_logic = 0x0
-    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_ratio = 0x100
-    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
-    // .. .. reg_phy_ctrl_slave_force = 0x0
-    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_delay = 0x0
-    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
-    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
-    // .. .. reg_phy_lpddr = 0x0
-    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
-    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // .. .. reg_phy_cmd_latency = 0x0
-    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
-    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
-    // .. .. reg_phy_wr_rl_delay = 0x2
-    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
-    // .. .. reg_phy_rd_rl_delay = 0x4
-    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
-    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
-    // .. .. reg_phy_dll_lock_diff = 0xf
-    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
-    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
-    // .. .. reg_phy_use_wr_level = 0x1
-    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
-    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
-    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
-    // .. .. reg_phy_use_rd_data_eye_level = 0x1
-    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. .. reg_phy_dis_calib_rst = 0x0
-    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_phy_ctrl_slave_delay = 0x0
-    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
-    // .. .. reg_arb_page_addr_mask = 0x0
-    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_wr_portn = 0x3ff
-    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
-    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_arb_pri_rd_portn = 0x3ff
-    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
-    // .. .. reg_arb_disable_aging_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
-    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
-    // .. .. reg_arb_set_hpr_rd_portn = 0x0
-    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
-    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
-    // .. .. reg_ddrc_lpddr2 = 0x0
-    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. reg_ddrc_derate_enable = 0x0
-    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. .. reg_ddrc_mr4_margin = 0x0
-    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
-    // .. .. reg_ddrc_mr4_read_interval = 0x0
-    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
-    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
-    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
-    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
-    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
-    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
-    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
-    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
-    // .. .. reg_ddrc_t_mrw = 0x5
-    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
-    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa6
-    // .. .. ==> 0XF80062B4[7:0] = 0x000000A6U
-    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A6U
-    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
-    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
-    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
-    // .. .. 
-    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A6U),
-    // .. .. START: POLL ON DCI STATUS
-    // .. .. DONE = 1
-    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
-    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. .. 
-    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
-    // .. .. FINISH: POLL ON DCI STATUS
-    // .. .. START: UNLOCK DDR
-    // .. .. reg_ddrc_soft_rstb = 0x1
-    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. reg_ddrc_powerdown_en = 0x0
-    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. .. reg_ddrc_data_bus_width = 0x0
-    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
-    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
-    // .. .. reg_ddrc_burst8_refresh = 0x0
-    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. .. reg_ddrc_rdwr_idle_gap = 1
-    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
-    // .. .. reg_ddrc_dis_rd_bypass = 0x0
-    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
-    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_act_bypass = 0x0
-    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
-    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
-    // .. .. reg_ddrc_dis_auto_refresh = 0x0
-    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
-    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
-    // .. .. FINISH: UNLOCK DDR
-    // .. .. START: CHECK DDR STATUS
-    // .. .. ddrc_reg_operating_mode = 1
-    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
-    // .. .. 
-    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
-    // .. .. FINISH: CHECK DDR STATUS
-    // .. FINISH: DDR INITIALIZATION
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_mio_init_data_3_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // .. 
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: OCM REMAPPING
-    // .. VREF_EN = 0x1
-    // .. ==> 0XF8000B00[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. VREF_SEL = 0x0
-    // .. ==> 0XF8000B00[6:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B00, 0x00000071U ,0x00000001U),
-    // .. FINISH: OCM REMAPPING
-    // .. START: DDRIOB SETTINGS
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B40[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B40[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B40[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCI_TYPE = 0x0
-    // .. ==> 0XF8000B40[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B40[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B40[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B40[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B40, 0x00000FFEU ,0x00000600U),
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B44[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B44[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B44[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCI_TYPE = 0x0
-    // .. ==> 0XF8000B44[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B44[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B44[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B44[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B44, 0x00000FFEU ,0x00000600U),
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B48[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B48[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B48[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCI_TYPE = 0x3
-    // .. ==> 0XF8000B48[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B48[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B48[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B48[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B48, 0x00000FFEU ,0x00000672U),
-    // .. INP_TYPE = 0x1
-    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCI_TYPE = 0x3
-    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFEU ,0x00000672U),
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B50[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B50[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B50[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCI_TYPE = 0x3
-    // .. ==> 0XF8000B50[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B50[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B50[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B50[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B50, 0x00000FFEU ,0x00000674U),
-    // .. INP_TYPE = 0x2
-    // .. ==> 0XF8000B54[2:1] = 0x00000002U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B54[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x1
-    // .. ==> 0XF8000B54[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. DCI_TYPE = 0x3
-    // .. ==> 0XF8000B54[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. IBUF_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0
-    // .. ==> 0XF8000B54[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B54[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B54[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B54, 0x00000FFEU ,0x00000674U),
-    // .. INP_TYPE = 0x0
-    // .. ==> 0XF8000B58[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. DCI_UPDATE_B = 0x0
-    // .. ==> 0XF8000B58[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. TERM_EN = 0x0
-    // .. ==> 0XF8000B58[4:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
-    // .. DCI_TYPE = 0x0
-    // .. ==> 0XF8000B58[6:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
-    // .. IBUF_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. TERM_DISABLE_MODE = 0x0
-    // .. ==> 0XF8000B58[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. OUTPUT_EN = 0x3
-    // .. ==> 0XF8000B58[10:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
-    // .. PULLUP_EN = 0x0
-    // .. ==> 0XF8000B58[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B58, 0x00000FFEU ,0x00000600U),
-    // .. VREF_INT_EN = 0x0
-    // .. ==> 0XF8000B6C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. VREF_SEL = 0x0
-    // .. ==> 0XF8000B6C[4:1] = 0x00000000U
-    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U
-    // .. VREF_EXT_EN = 0x3
-    // .. ==> 0XF8000B6C[6:5] = 0x00000003U
-    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
-    // .. REFIO_EN = 0x1
-    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B6C, 0x0000027FU ,0x00000260U),
-    // .. .. START: ASSERT RESET
-    // .. .. RESET = 1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
-    // .. .. FINISH: ASSERT RESET
-    // .. .. START: DEASSERT RESET
-    // .. .. RESET = 0
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000000U),
-    // .. .. FINISH: DEASSERT RESET
-    // .. .. RESET = 0x1
-    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. .. ENABLE = 0x1
-    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. .. NREF_OPT1 = 0x0
-    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
-    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. .. NREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
-    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
-    // .. .. NREF_OPT4 = 0x1
-    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
-    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
-    // .. .. PREF_OPT2 = 0x0
-    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
-    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
-    // .. .. UPDATE_CONTROL = 0x0
-    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
-    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. .. 
-    EMIT_MASKWRITE(0XF8000B70, 0x001E3FC3U ,0x00000803U),
-    // .. FINISH: DDRIOB SETTINGS
-    // .. START: MIO PROGRAMMING
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000700[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000700[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000700[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000700[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000700[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000700[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000700[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000700[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000700[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000704[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000704[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000704[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000704[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000704[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000704[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000704[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000704[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000704[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000708[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000708[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000708[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000708[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000708[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000708[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000708[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000708[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000708[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800070C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800070C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800070C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800070C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800070C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800070C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF800070C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800070C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800070C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000710[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000710[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000710[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000710[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000710[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000710[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000710[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000710[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000710[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000714[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000714[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000714[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000714[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000714[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000714[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000714[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000714[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000714[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000718[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000718[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000718[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000718[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000718[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000718[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000718[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000718[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000718[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800071C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800071C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800071C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800071C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800071C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800071C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800071C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800071C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800071C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000720[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000720[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000720[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000720[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000720[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000720[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000720[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000720[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000720[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000702U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000724[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000724[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000724[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000724[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000724[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000724[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000724[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000724[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000724[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000728[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000728[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000728[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000728[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 2
-    // .. ==> 0XF8000728[7:5] = 0x00000002U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
-    // .. Speed = 0
-    // .. ==> 0XF8000728[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000728[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000728[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000728[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001640U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800072C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800072C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800072C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800072C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 2
-    // .. ==> 0XF800072C[7:5] = 0x00000002U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
-    // .. Speed = 0
-    // .. ==> 0XF800072C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800072C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 1
-    // .. ==> 0XF800072C[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800072C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001640U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000730[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000730[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000730[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000730[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 2
-    // .. ==> 0XF8000730[7:5] = 0x00000002U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
-    // .. Speed = 0
-    // .. ==> 0XF8000730[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000730[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000730[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000730[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001640U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000734[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000734[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000734[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000734[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 2
-    // .. ==> 0XF8000734[7:5] = 0x00000002U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
-    // .. Speed = 0
-    // .. ==> 0XF8000734[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000734[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 1
-    // .. ==> 0XF8000734[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000734[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001640U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000738[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000738[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000738[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000738[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000738[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF8000738[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF8000738[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000738[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000738[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800073C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800073C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800073C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800073C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800073C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF800073C[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 3
-    // .. ==> 0XF800073C[11:9] = 0x00000003U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
-    // .. PULLUP = 0
-    // .. ==> 0XF800073C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800073C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000740[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000740[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000740[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000740[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000740[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000740[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000740[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000740[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000740[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002902U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000744[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000744[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000744[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000744[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000744[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000744[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000744[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000744[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000744[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002902U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000748[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000748[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000748[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000748[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000748[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000748[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000748[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000748[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000748[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002902U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800074C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800074C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800074C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800074C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800074C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800074C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF800074C[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF800074C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF800074C[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. 
-    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002902U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000750[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000750[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000750[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000750[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000750[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000750[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000750[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000750[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000750[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002902U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000754[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000754[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000754[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000754[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000754[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000754[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000754[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000754[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 1
-    // .. ==> 0XF8000754[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002902U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000758[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000758[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000758[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000758[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000758[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000758[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000758[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000758[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000758[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000903U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800075C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800075C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800075C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800075C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800075C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800075C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF800075C[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF800075C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800075C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000903U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000760[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000760[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000760[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000760[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000760[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000760[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000760[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000760[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000760[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000903U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000764[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000764[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000764[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000764[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000764[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000764[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000764[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000764[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000764[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000903U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000768[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF8000768[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF8000768[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000768[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000768[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000768[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF8000768[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000768[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000768[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000903U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800076C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 1
-    // .. ==> 0XF800076C[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. L1_SEL = 0
-    // .. ==> 0XF800076C[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800076C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800076C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800076C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 4
-    // .. ==> 0XF800076C[11:9] = 0x00000004U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
-    // .. PULLUP = 0
-    // .. ==> 0XF800076C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800076C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000903U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000770[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000770[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000770[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000770[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000770[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000770[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000770[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000770[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000770[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000774[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000774[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000774[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000774[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000774[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000774[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000774[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000774[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000774[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000778[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000778[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000778[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000778[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000778[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000778[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000778[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000778[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000778[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF800077C[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800077C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800077C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800077C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800077C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800077C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF800077C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800077C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800077C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000780[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000780[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000780[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000780[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000780[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000780[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000780[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000780[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000780[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000784[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000784[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000784[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000784[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000784[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000784[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000784[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000784[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000784[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000788[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000788[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000788[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000788[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000788[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000788[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000788[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000788[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000788[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800078C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800078C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800078C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800078C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800078C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800078C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF800078C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800078C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800078C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF8000790[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000790[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000790[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000790[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000790[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000790[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000790[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000790[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000790[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000794[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000794[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000794[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000794[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000794[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000794[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000794[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000794[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000794[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF8000798[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF8000798[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF8000798[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF8000798[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF8000798[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF8000798[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF8000798[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF8000798[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF8000798[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF800079C[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF800079C[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 1
-    // .. ==> 0XF800079C[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. L2_SEL = 0
-    // .. ==> 0XF800079C[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF800079C[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 1
-    // .. ==> 0XF800079C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF800079C[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF800079C[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF800079C[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007A0[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007A4[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007A8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007A8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007A8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007A8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007A8[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007A8[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007A8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007A8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007A8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007AC[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007AC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007AC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007AC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007AC[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007AC[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007AC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007AC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007AC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007B0[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007B4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007B4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007B4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007B4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 1
-    // .. ==> 0XF80007B4[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007B8[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF80007B8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007B8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007B8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007B8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000200U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007BC[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. Speed = 0
-    // .. ==> 0XF80007BC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007BC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007BC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007BC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007C0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C0[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C4[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 7
-    // .. ==> 0XF80007C4[7:5] = 0x00000007U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
-    // .. Speed = 0
-    // .. ==> 0XF80007C4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007C8[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007C8[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007C8[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007C8[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF80007C8[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF80007C8[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007C8[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007C8[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007C8[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
-    // .. TRI_ENABLE = 1
-    // .. ==> 0XF80007CC[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007CC[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007CC[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007CC[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 0
-    // .. ==> 0XF80007CC[7:5] = 0x00000000U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
-    // .. Speed = 0
-    // .. ==> 0XF80007CC[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007CC[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007CC[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007CC[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D0[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D0[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D0[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D0[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D0[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D0[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D0[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D0[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D0[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
-    // .. TRI_ENABLE = 0
-    // .. ==> 0XF80007D4[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. L0_SEL = 0
-    // .. ==> 0XF80007D4[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. L1_SEL = 0
-    // .. ==> 0XF80007D4[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. L2_SEL = 0
-    // .. ==> 0XF80007D4[4:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
-    // .. L3_SEL = 4
-    // .. ==> 0XF80007D4[7:5] = 0x00000004U
-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
-    // .. Speed = 0
-    // .. ==> 0XF80007D4[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. IO_Type = 1
-    // .. ==> 0XF80007D4[11:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
-    // .. PULLUP = 0
-    // .. ==> 0XF80007D4[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. DisableRcvr = 0
-    // .. ==> 0XF80007D4[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
-    // .. SDIO0_CD_SEL = 47
-    // .. ==> 0XF8000830[21:16] = 0x0000002FU
-    // ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000830, 0x003F0000U ,0x002F0000U),
-    // .. FINISH: MIO PROGRAMMING
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // .. 
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_peripherals_init_data_3_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // .. 
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B48[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B50[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
-    // .. IBUF_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[7:7] = 0x00000001U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
-    // .. TERM_DISABLE_MODE = 0x1
-    // .. ==> 0XF8000B54[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. 
-    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
-    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // .. 
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // .. START: SRAM/NOR SET OPMODE
-    // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // .. 
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // .. 
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
-    // .. BDIV = 0x6
-    // .. ==> 0XE0000034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // .. 
-    EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0000018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // .. 
-    EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0000000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0000000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0000000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0000000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0000000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0000000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0000000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0000000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0000000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
-    EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0000004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0000004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0000004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0000004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0000004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
-    // .. START: QSPI REGISTERS
-    // .. Holdb_dr = 1
-    // .. ==> 0XE000D000[19:19] = 0x00000001U
-    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
-    // .. 
-    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
-    // .. FINISH: QSPI REGISTERS
-    // .. START: PL POWER ON RESET REGISTERS
-    // .. PCFG_POR_CNT_4K = 0
-    // .. ==> 0XF8007000[29:29] = 0x00000000U
-    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
-    // .. FINISH: PL POWER ON RESET REGISTERS
-    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
-    // .. .. START: NAND SET CYCLE
-    // .. .. FINISH: NAND SET CYCLE
-    // .. .. START: OPMODE
-    // .. .. FINISH: OPMODE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: SRAM/NOR CS0 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS0 BASE ADDRESS
-    // .. .. FINISH: NOR CS0 BASE ADDRESS
-    // .. .. START: SRAM/NOR CS1 SET CYCLE
-    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
-    // .. .. START: DIRECT COMMAND
-    // .. .. FINISH: DIRECT COMMAND
-    // .. .. START: NOR CS1 BASE ADDRESS
-    // .. .. FINISH: NOR CS1 BASE ADDRESS
-    // .. .. START: USB RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. DIRECTION_1 = 0x4000
-    // .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. DATA_1_LSW = 0x4000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. OP_ENABLE_1 = 0x4000
-    // .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
-    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. DATA_1_LSW = 0x0
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. MASK_1_LSW = 0xbfff
-    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
-    // .. .. .. DATA_1_LSW = 0x4000
-    // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
-    // .. .. .. 
-    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. FINISH: USB RESET
-    // .. .. START: ENET RESET
-    // .. .. .. START: DIR MODE BANK 0
-    // .. .. .. FINISH: DIR MODE BANK 0
-    // .. .. .. START: DIR MODE BANK 1
-    // .. .. .. FINISH: DIR MODE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE BANK 0
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
-    // .. .. .. START: OUTPUT ENABLE BANK 1
-    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. FINISH: ENET RESET
-    // .. .. START: I2C RESET
-    // .. .. .. START: DIR MODE GPIO BANK0
-    // .. .. .. FINISH: DIR MODE GPIO BANK0
-    // .. .. .. START: DIR MODE GPIO BANK1
-    // .. .. .. FINISH: DIR MODE GPIO BANK1
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: OUTPUT ENABLE
-    // .. .. .. FINISH: OUTPUT ENABLE
-    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
-    // .. .. FINISH: I2C RESET
-    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-unsigned long ps7_post_config_3_0[] = {
-    // START: top
-    // .. START: SLCR SETTINGS
-    // .. UNLOCK_KEY = 0XDF0D
-    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
-    // .. 
-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
-    // .. FINISH: SLCR SETTINGS
-    // .. START: ENABLING LEVEL SHIFTER
-    // .. USER_LVL_INP_EN_0 = 1
-    // .. ==> 0XF8000900[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. USER_LVL_OUT_EN_0 = 1
-    // .. ==> 0XF8000900[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. USER_LVL_INP_EN_1 = 1
-    // .. ==> 0XF8000900[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. USER_LVL_OUT_EN_1 = 1
-    // .. ==> 0XF8000900[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
-    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
-    // .. FINISH: ENABLING LEVEL SHIFTER
-    // .. START: FPGA RESETS TO 1
-    // .. reserved_3 = 127
-    // .. ==> 0XF8000240[31:25] = 0x0000007FU
-    // ..     ==> MASK : 0xFE000000U    VAL : 0xFE000000U
-    // .. reserved_FPGA_ACP_RST = 1
-    // .. ==> 0XF8000240[24:24] = 0x00000001U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
-    // .. reserved_FPGA_AXDS3_RST = 1
-    // .. ==> 0XF8000240[23:23] = 0x00000001U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
-    // .. reserved_FPGA_AXDS2_RST = 1
-    // .. ==> 0XF8000240[22:22] = 0x00000001U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
-    // .. reserved_FPGA_AXDS1_RST = 1
-    // .. ==> 0XF8000240[21:21] = 0x00000001U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
-    // .. reserved_FPGA_AXDS0_RST = 1
-    // .. ==> 0XF8000240[20:20] = 0x00000001U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00100000U
-    // .. reserved_2 = 3
-    // .. ==> 0XF8000240[19:18] = 0x00000003U
-    // ..     ==> MASK : 0x000C0000U    VAL : 0x000C0000U
-    // .. reserved_FSSW1_FPGA_RST = 1
-    // .. ==> 0XF8000240[17:17] = 0x00000001U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
-    // .. reserved_FSSW0_FPGA_RST = 1
-    // .. ==> 0XF8000240[16:16] = 0x00000001U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
-    // .. reserved_1 = 15
-    // .. ==> 0XF8000240[15:14] = 0x0000000FU
-    // ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
-    // .. reserved_FPGA_FMSW1_RST = 1
-    // .. ==> 0XF8000240[13:13] = 0x00000001U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
-    // .. reserved_FPGA_FMSW0_RST = 1
-    // .. ==> 0XF8000240[12:12] = 0x00000001U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
-    // .. reserved_FPGA_DMA3_RST = 1
-    // .. ==> 0XF8000240[11:11] = 0x00000001U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000800U
-    // .. reserved_FPGA_DMA2_RST = 1
-    // .. ==> 0XF8000240[10:10] = 0x00000001U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
-    // .. reserved_FPGA_DMA1_RST = 1
-    // .. ==> 0XF8000240[9:9] = 0x00000001U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
-    // .. reserved_FPGA_DMA0_RST = 1
-    // .. ==> 0XF8000240[8:8] = 0x00000001U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
-    // .. reserved = 15
-    // .. ==> 0XF8000240[7:4] = 0x0000000FU
-    // ..     ==> MASK : 0x000000F0U    VAL : 0x000000F0U
-    // .. FPGA3_OUT_RST = 1
-    // .. ==> 0XF8000240[3:3] = 0x00000001U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
-    // .. FPGA2_OUT_RST = 1
-    // .. ==> 0XF8000240[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. FPGA1_OUT_RST = 1
-    // .. ==> 0XF8000240[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. FPGA0_OUT_RST = 1
-    // .. ==> 0XF8000240[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. 
-    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0xFFFFFFFFU),
-    // .. FINISH: FPGA RESETS TO 1
-    // .. START: FPGA RESETS TO 0
-    // .. reserved_3 = 0
-    // .. ==> 0XF8000240[31:25] = 0x00000000U
-    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
-    // .. reserved_FPGA_ACP_RST = 0
-    // .. ==> 0XF8000240[24:24] = 0x00000000U
-    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
-    // .. reserved_FPGA_AXDS3_RST = 0
-    // .. ==> 0XF8000240[23:23] = 0x00000000U
-    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
-    // .. reserved_FPGA_AXDS2_RST = 0
-    // .. ==> 0XF8000240[22:22] = 0x00000000U
-    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
-    // .. reserved_FPGA_AXDS1_RST = 0
-    // .. ==> 0XF8000240[21:21] = 0x00000000U
-    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
-    // .. reserved_FPGA_AXDS0_RST = 0
-    // .. ==> 0XF8000240[20:20] = 0x00000000U
-    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
-    // .. reserved_2 = 0
-    // .. ==> 0XF8000240[19:18] = 0x00000000U
-    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
-    // .. reserved_FSSW1_FPGA_RST = 0
-    // .. ==> 0XF8000240[17:17] = 0x00000000U
-    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
-    // .. reserved_FSSW0_FPGA_RST = 0
-    // .. ==> 0XF8000240[16:16] = 0x00000000U
-    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
-    // .. reserved_1 = 0
-    // .. ==> 0XF8000240[15:14] = 0x00000000U
-    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
-    // .. reserved_FPGA_FMSW1_RST = 0
-    // .. ==> 0XF8000240[13:13] = 0x00000000U
-    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
-    // .. reserved_FPGA_FMSW0_RST = 0
-    // .. ==> 0XF8000240[12:12] = 0x00000000U
-    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
-    // .. reserved_FPGA_DMA3_RST = 0
-    // .. ==> 0XF8000240[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. reserved_FPGA_DMA2_RST = 0
-    // .. ==> 0XF8000240[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. reserved_FPGA_DMA1_RST = 0
-    // .. ==> 0XF8000240[9:9] = 0x00000000U
-    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
-    // .. reserved_FPGA_DMA0_RST = 0
-    // .. ==> 0XF8000240[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. reserved = 0
-    // .. ==> 0XF8000240[7:4] = 0x00000000U
-    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
-    // .. FPGA3_OUT_RST = 0
-    // .. ==> 0XF8000240[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. FPGA2_OUT_RST = 0
-    // .. ==> 0XF8000240[2:2] = 0x00000000U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
-    // .. FPGA1_OUT_RST = 0
-    // .. ==> 0XF8000240[1:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
-    // .. FPGA0_OUT_RST = 0
-    // .. ==> 0XF8000240[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // .. 
-    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
-    // .. FINISH: FPGA RESETS TO 0
-    // .. START: AFI REGISTERS
-    // .. .. START: AFI0 REGISTERS
-    // .. .. FINISH: AFI0 REGISTERS
-    // .. .. START: AFI1 REGISTERS
-    // .. .. FINISH: AFI1 REGISTERS
-    // .. .. START: AFI2 REGISTERS
-    // .. .. FINISH: AFI2 REGISTERS
-    // .. .. START: AFI3 REGISTERS
-    // .. .. FINISH: AFI3 REGISTERS
-    // .. FINISH: AFI REGISTERS
-    // .. START: LOCK IT BACK
-    // .. LOCK_KEY = 0X767B
-    // .. ==> 0XF8000004[15:0] = 0x0000767BU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
-    // .. 
-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
-    // .. FINISH: LOCK IT BACK
-    // FINISH: top
-    //
-    EMIT_EXIT(),
-
-    //
-};
-
-
-#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
-  char* err_msg = "";
-  switch (key) {
-    case PS7_INIT_SUCCESS:                  err_msg = "PS7 initialization successful"; break;
-    case PS7_INIT_CORRUPT:                  err_msg = "PS7 init Data Corrupted"; break;
-    case PS7_INIT_TIMEOUT:                  err_msg = "PS7 init mask poll timeout"; break;
-    case PS7_POLL_FAILED_DDR_INIT:          err_msg = "Mask Poll failed for DDR Init"; break;
-    case PS7_POLL_FAILED_DMA:               err_msg = "Mask Poll failed for PLL Init"; break;
-    case PS7_POLL_FAILED_PLL:               err_msg = "Mask Poll failed for DMA done bit"; break;
-    default:                                err_msg = "Undefined error status"; break;
-  }
-  
-  return err_msg;  
-}
-
-unsigned long
-ps7GetSiliconVersion () {
-  // Read PS version from MCTRL register [31:28]
-  unsigned long mask = 0xF0000000;
-  unsigned long *addr = (unsigned long*) 0XF8007080;    
-  unsigned long ps_version = (*addr & mask) >> 28;
-  return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
-        unsigned long *addr = (unsigned long*) add;
-        *addr = ( val & mask ) | ( *addr & ~mask);
-        //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
-        unsigned long *addr = (unsigned long*) add;
-        int i = 0;
-        while (!(*addr & mask)) {
-          if (i == PS7_MASK_POLL_TIME) {
-            return -1;
-          }
-          i++;
-        }
-     return 1;   
-        //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
-        unsigned long *addr = (unsigned long*) add;
-        unsigned long val = (*addr & mask);
-        //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
-        return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init) 
-{
-    unsigned long *ptr = ps7_config_init;
-
-    unsigned long  opcode;            // current instruction ..
-    unsigned long  args[16];           // no opcode has so many args ...
-    int  numargs;           // number of arguments of this instruction
-    int  j;                 // general purpose index
-
-    volatile unsigned long *addr;         // some variable to make code readable
-    unsigned long  val,mask;              // some variable to make code readable
-
-    int finish = -1 ;           // loop while this is negative !
-    int i = 0;                  // Timeout variable
-    
-    while( finish < 0 ) {
-        numargs = ptr[0] & 0xF;
-        opcode = ptr[0] >> 4;
-
-        for( j = 0 ; j < numargs ; j ++ ) 
-            args[j] = ptr[j+1];
-        ptr += numargs + 1;
-        
-        
-        switch ( opcode ) {
-            
-        case OPCODE_EXIT:
-            finish = PS7_INIT_SUCCESS;
-            break;
-            
-        case OPCODE_CLEAR:
-            addr = (unsigned long*) args[0];
-            *addr = 0;
-            break;
-
-        case OPCODE_WRITE:
-            addr = (unsigned long*) args[0];
-            val = args[1];
-            *addr = val;
-            break;
-
-        case OPCODE_MASKWRITE:
-            addr = (unsigned long*) args[0];
-            mask = args[1];
-            val = args[2];
-            *addr = ( val & mask ) | ( *addr & ~mask);
-            break;
-
-        case OPCODE_MASKPOLL:
-            addr = (unsigned long*) args[0];
-            mask = args[1];
-            i = 0;
-            while (!(*addr & mask)) {
-                if (i == PS7_MASK_POLL_TIME) {
-                    finish = PS7_INIT_TIMEOUT;
-                    break;
-                }
-                i++;
-            }
-            break;
-        default:
-            finish = PS7_INIT_CORRUPT;
-            break;
-        }
-    }
-    return finish;
-}
-
-unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
-unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
-unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
-unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
-unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
-
-int
-ps7_post_config() 
-{
-  // Get the PS_VERSION on run time
-  unsigned long si_ver = ps7GetSiliconVersion ();
-  int ret = -1;
-  if (si_ver == PCW_SILICON_VERSION_1) {
-      ret = ps7_config (ps7_post_config_1_0);   
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  } else if (si_ver == PCW_SILICON_VERSION_2) {
-      ret = ps7_config (ps7_post_config_2_0);   
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  } else {
-      ret = ps7_config (ps7_post_config_3_0);
-      if (ret != PS7_INIT_SUCCESS) return ret;
-  }
-  return PS7_INIT_SUCCESS;
-}
-
-int
-ps7_init() 
-{
-  // Get the PS_VERSION on run time
-  unsigned long si_ver = ps7GetSiliconVersion ();
-  //int pcw_ver = 0;
-
-  if (si_ver == PCW_SILICON_VERSION_1) {
-    ps7_mio_init_data = ps7_mio_init_data_1_0;
-    ps7_pll_init_data = ps7_pll_init_data_1_0;
-    ps7_clock_init_data = ps7_clock_init_data_1_0;
-    ps7_ddr_init_data = ps7_ddr_init_data_1_0;
-    ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
-    //pcw_ver = 1;
-
-  } else if (si_ver == PCW_SILICON_VERSION_2) {
-    ps7_mio_init_data = ps7_mio_init_data_2_0;
-    ps7_pll_init_data = ps7_pll_init_data_2_0;
-    ps7_clock_init_data = ps7_clock_init_data_2_0;
-    ps7_ddr_init_data = ps7_ddr_init_data_2_0;
-    ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
-    //pcw_ver = 2;
-
-  } else {
-    ps7_mio_init_data = ps7_mio_init_data_3_0;
-    ps7_pll_init_data = ps7_pll_init_data_3_0;
-    ps7_clock_init_data = ps7_clock_init_data_3_0;
-    ps7_ddr_init_data = ps7_ddr_init_data_3_0;
-    ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
-    //pcw_ver = 3;
-  }
-
-  // MIO init
-  int ret = ps7_config (ps7_mio_init_data);  
-  if (ret != PS7_INIT_SUCCESS) return ret;
-
-  // PLL init
-  ret = ps7_config (ps7_pll_init_data); 
-  if (ret != PS7_INIT_SUCCESS) return ret;
-
-  // Clock init
-  ret = ps7_config (ps7_clock_init_data);
-  if (ret != PS7_INIT_SUCCESS) return ret;
-
-  // DDR init
-  ret = ps7_config (ps7_ddr_init_data);
-  if (ret != PS7_INIT_SUCCESS) return ret;
-
-
-  // Peripherals init
-  ret = ps7_config (ps7_peripherals_init_data);
-  if (ret != PS7_INIT_SUCCESS) return ret;
-  //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
-  return PS7_INIT_SUCCESS;
-}
-
diff --git a/quad/xsdk_workspace_vivado/sytem_hw_platform_0/ps7_init.h b/quad/xsdk_workspace_vivado/sytem_hw_platform_0/ps7_init.h
deleted file mode 100644
index d63682e6a8d848399e05e9962eb7473e84e4a954..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/sytem_hw_platform_0/ps7_init.h
+++ /dev/null
@@ -1,139 +0,0 @@
-
-/******************************************************************************
-*
-* (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
-*
-* This file contains confidential and proprietary information of Xilinx, Inc.
-* and is protected under U.S. and international copyright and other
-* intellectual property laws.
-*
-* DISCLAIMER
-* This disclaimer is not a license and does not grant any rights to the
-* materials distributed herewith. Except as otherwise provided in a valid
-* license issued to you by Xilinx, and to the maximum extent permitted by
-* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-* and (2) Xilinx shall not be liable (whether in contract or tort, including
-* negligence, or under any other theory of liability) for any loss or damage
-* of any kind or nature related to, arising under or in connection with these
-* materials, including for any direct, or any indirect, special, incidental,
-* or consequential loss or damage (including loss of data, profits, goodwill,
-* or any type of loss or damage suffered as a result of any action brought by
-* a third party) even if such damage or loss was reasonably foreseeable or
-* Xilinx had been advised of the possibility of the same.
-*
-* CRITICAL APPLICATIONS
-* Xilinx products are not designed or intended to be fail-safe, or for use in
-* any application requiring fail-safe performance, such as life-support or
-* safety devices or systems, Class III medical devices, nuclear facilities,
-* applications related to the deployment of airbags, or any other applications
-* that could lead to death, personal injury, or severe property or
-* environmental damage (individually and collectively, "Critical
-* Applications"). Customer assumes the sole risk and liability of any use of
-* Xilinx products in Critical Applications, subject only to applicable laws
-* and regulations governing limitations on product liability.
-*
-* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-* AT ALL TIMES.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int  u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long  * ps7_ddr_init_data;
-extern unsigned long  * ps7_mio_init_data;
-extern unsigned long  * ps7_pll_init_data;
-extern unsigned long  * ps7_clock_init_data;
-extern unsigned long  * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT       0U
-#define OPCODE_CLEAR      1U
-#define OPCODE_WRITE      2U
-#define OPCODE_MASKWRITE  3U
-#define OPCODE_MASKPOLL   4U
-#define NEW_PS7_ERR_CODE 1
-
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
-#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
-
-
-
-/* Returns codes  of PS7_Init */
-#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
-#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ  650000000
-#define DDR_FREQ  525000000
-#define DCI_FREQ  10159000
-#define QSPI_FREQ  200000000
-#define SMC_FREQ  100000000
-#define ENET0_FREQ  125000000
-#define ENET1_FREQ  125000000
-#define USB0_FREQ  60000000
-#define USB1_FREQ  60000000
-#define SDIO_FREQ  50000000
-#define UART_FREQ  50000000
-#define SPI_FREQ  166666666
-#define I2C_FREQ  108333336
-#define WDT_FREQ  133333333
-#define TTC_FREQ  50000000
-#define CAN_FREQ  100000000
-#define PCAP_FREQ  200000000
-#define TPIU_FREQ  0
-#define FPGA0_FREQ  100000000
-#define FPGA1_FREQ  175000000
-#define FPGA2_FREQ  12288000
-#define FPGA3_FREQ  100000000
-#define C_CPU_REF_CLK_FREQ_HZ  50000000
-
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-char* getPS7MessageInfo(unsigned key);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/quad/xsdk_workspace_vivado/sytem_hw_platform_0/ps7_init.html b/quad/xsdk_workspace_vivado/sytem_hw_platform_0/ps7_init.html
deleted file mode 100644
index 7c6d0beb78efc1194e15518b14e0f72279b7592d..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/sytem_hw_platform_0/ps7_init.html
+++ /dev/null
@@ -1,8860 +0,0 @@
-<!DOCTYPE html>
-<html lang="en">
-<head>
-<meta http-equiv="content-type" content="text/html;charset=UTF-8"/>
-<title>Zynq PS configuration detail</title>
-<style type="text/css">
-.hex {font-family:monospace ; text-align : right}
-td { min-width : 80px ; } 
-</style>
-</head>
-<body>
-<p style="height: 7px">Following peripherals are selected in the design. </p>
-<p><br /></p>
-<h2><a name="Top">Peripheral Selected</a></h2>
-<ul>
-<li>Quad SPI Flash</li>
-<li>Enet 0</li>
-<li>USB 0</li>
-<li>SD 0</li>
-<li>UART 0</li>
-<li>UART 1</li>
-<li>I2C 0</li>
-<li>I2C 1</li>
-<li>GPIO</li>
-</ul>
-<p>To see detailed information please follow below links:</p>
-<ul>
-<li><a href="#MIOConfTab">MIO Configuration Table</a></li>
-<li><a href="#ZynqPerTab">Zynq Peripheral Configuration</a></li>
-<li><a href="#DDRInfoTab">DDR Configuration Information</a></li>
-<li>SLCR settings</li>
-<ul>
-<li><a href="#ps7_pll_init_data">PLL Init Data</a></li>
-<li><a href="#ps7_clock_init_data">Clock Init Data</a></li>
-<li><a href="#ps7_ddr_init_data">DDR Init Data</a></li>
-<li><a href="#ps7_mio_init_data">MIO Init Data</a></li>
-</ul>
-</ul>
-<h2><a name="MIOConfTab">MIO configuration Table</a></h2>
-<ul><table border="1"> 
-<thead><tr>                <th>MIO Pin</th>                <th>Peripheral</th>             <th>Signal</th>               <th>IO type</th>              <th>Speed</th>              <th>Pullup</th>              <th>Direction</th>              </tr></thead>
-<tr bgcolor="#FA4A46"><td><a name="MIO 0">MIO 0</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[0]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 1">MIO 1</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_ss_b</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 2">MIO 2</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_io[0]</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 3">MIO 3</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_io[1]</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 4">MIO 4</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_io[2]</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 5">MIO 5</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_io[3]</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 6">MIO 6</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_sclk</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 7">MIO 7</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[7]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 8">MIO 8</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi_fbclk</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 9">MIO 9</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[9]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="MIO 10">MIO 10</a></td><td><a href="#I2C 0">I2C 0</a></td><td>scl</td><td>LVCMOS 3.3V</td><td>slow</td><td>enabled</td><td>inout</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="MIO 11">MIO 11</a></td><td><a href="#I2C 0">I2C 0</a></td><td>sda</td><td>LVCMOS 3.3V</td><td>slow</td><td>enabled</td><td>inout</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="MIO 12">MIO 12</a></td><td><a href="#I2C 1">I2C 1</a></td><td>scl</td><td>LVCMOS 3.3V</td><td>slow</td><td>enabled</td><td>inout</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="MIO 13">MIO 13</a></td><td><a href="#I2C 1">I2C 1</a></td><td>sda</td><td>LVCMOS 3.3V</td><td>slow</td><td>enabled</td><td>inout</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 14">MIO 14</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[14]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 15">MIO 15</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[15]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 16">MIO 16</a></td><td><a href="#Enet 0">Enet 0</a></td><td>tx_clk</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 17">MIO 17</a></td><td><a href="#Enet 0">Enet 0</a></td><td>txd[0]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 18">MIO 18</a></td><td><a href="#Enet 0">Enet 0</a></td><td>txd[1]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 19">MIO 19</a></td><td><a href="#Enet 0">Enet 0</a></td><td>txd[2]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 20">MIO 20</a></td><td><a href="#Enet 0">Enet 0</a></td><td>txd[3]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 21">MIO 21</a></td><td><a href="#Enet 0">Enet 0</a></td><td>tx_ctl</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 22">MIO 22</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rx_clk</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 23">MIO 23</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rxd[0]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 24">MIO 24</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rxd[1]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 25">MIO 25</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rxd[2]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 26">MIO 26</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rxd[3]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 27">MIO 27</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rx_ctl</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 28">MIO 28</a></td><td><a href="#USB 0">USB 0</a></td><td>data[4]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 29">MIO 29</a></td><td><a href="#USB 0">USB 0</a></td><td>dir</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 30">MIO 30</a></td><td><a href="#USB 0">USB 0</a></td><td>stp</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 31">MIO 31</a></td><td><a href="#USB 0">USB 0</a></td><td>nxt</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 32">MIO 32</a></td><td><a href="#USB 0">USB 0</a></td><td>data[0]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 33">MIO 33</a></td><td><a href="#USB 0">USB 0</a></td><td>data[1]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 34">MIO 34</a></td><td><a href="#USB 0">USB 0</a></td><td>data[2]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 35">MIO 35</a></td><td><a href="#USB 0">USB 0</a></td><td>data[3]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 36">MIO 36</a></td><td><a href="#USB 0">USB 0</a></td><td>clk</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 37">MIO 37</a></td><td><a href="#USB 0">USB 0</a></td><td>data[5]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 38">MIO 38</a></td><td><a href="#USB 0">USB 0</a></td><td>data[6]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 39">MIO 39</a></td><td><a href="#USB 0">USB 0</a></td><td>data[7]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 40">MIO 40</a></td><td><a href="#SD 0">SD 0</a></td><td>clk</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 41">MIO 41</a></td><td><a href="#SD 0">SD 0</a></td><td>cmd</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 42">MIO 42</a></td><td><a href="#SD 0">SD 0</a></td><td>data[0]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 43">MIO 43</a></td><td><a href="#SD 0">SD 0</a></td><td>data[1]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 44">MIO 44</a></td><td><a href="#SD 0">SD 0</a></td><td>data[2]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 45">MIO 45</a></td><td><a href="#SD 0">SD 0</a></td><td>data[3]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 46">MIO 46</a></td><td><a href="#USB 0">USB 0</a></td><td>reset</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 47">MIO 47</a></td><td><a href="#SD 0">SD 0</a></td><td>cd</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#6495ED"><td><a name="MIO 48">MIO 48</a></td><td><a href="#UART 1">UART 1</a></td><td>tx</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#6495ED"><td><a name="MIO 49">MIO 49</a></td><td><a href="#UART 1">UART 1</a></td><td>rx</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 50">MIO 50</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[50]</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 51">MIO 51</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[51]</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 52">MIO 52</a></td><td><a href="#Enet 0">Enet 0</a></td><td>mdc</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 53">MIO 53</a></td><td><a href="#Enet 0">Enet 0</a></td><td>mdio</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-</table></ul>
-<li><a href="#Top">Go To TOP</a></li>
-<h2><a name="ZynqPerTab">Zynq Peripheral Configuration</a></h2>
-<ul><table border="1"> 
-<tr><thead>             <th>Peripheral</th>                <th>Signal Group</th>             <th>Signal</th>               <th>MIO</th>              </thead></tr>
-<tr bgcolor="#FAEBD7"><td><a name="Quad SPI Flash" >Quad SPI Flash</a></td>             <td></td><td></td><td>MIO 1 .. 6</td></tr>
-<tr bgcolor="#FAEBD7"><td></td><td>Dual Quad SPI (4 bit) </td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FAEBD7"><td></td><td>Dual Quad SPI (Parallel 8 bit)</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FAEBD7"><td></td><td>Feedback Clk</td><td></td><td>MIO 8</td></tr>
-<tr bgcolor="#FFFFFF"><td><a name="nor" >SRAM/NOR Flash</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FFE4C4"><td><a name="nand" >NAND Flash</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#DEB887"><td><a name="Enet 0" >Enet 0</a></td>             <td></td><td></td><td>MIO 16 .. 27</td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>tx_clk</td><td><a href="#MIO 16">MIO 16</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>txd[3]</td><td><a href="#MIO 20">MIO 20</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>txd[2]</td><td><a href="#MIO 19">MIO 19</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>txd[1]</td><td><a href="#MIO 18">MIO 18</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>txd[0]</td><td><a href="#MIO 17">MIO 17</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>tx_ctl</td><td><a href="#MIO 21">MIO 21</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rx_clk</td><td><a href="#MIO 22">MIO 22</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rxd[3]</td><td><a href="#MIO 26">MIO 26</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rxd[2]</td><td><a href="#MIO 25">MIO 25</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rxd[1]</td><td><a href="#MIO 24">MIO 24</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rxd[0]</td><td><a href="#MIO 23">MIO 23</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rx_ctl</td><td><a href="#MIO 27">MIO 27</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td>MDIO</td><td></td><td>MIO 52 .. 53</td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>mdc</td><td><a href="#MIO 52">MIO 52</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>mdio</td><td><a href="#MIO 53">MIO 53</a></td></tr>
-<tr bgcolor="#DEB887"><td><a name="enet1" >Enet 1</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="USB 0" >USB 0</a></td>             <td></td><td></td><td>MIO 28 .. 39</td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>clk</td><td><a href="#MIO 36">MIO 36</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>dir</td><td><a href="#MIO 29">MIO 29</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>stp</td><td><a href="#MIO 30">MIO 30</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>nxt</td><td><a href="#MIO 31">MIO 31</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[0]</td><td><a href="#MIO 32">MIO 32</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[1]</td><td><a href="#MIO 33">MIO 33</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[2]</td><td><a href="#MIO 34">MIO 34</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[3]</td><td><a href="#MIO 35">MIO 35</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[4]</td><td><a href="#MIO 28">MIO 28</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[5]</td><td><a href="#MIO 37">MIO 37</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[6]</td><td><a href="#MIO 38">MIO 38</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[7]</td><td><a href="#MIO 39">MIO 39</a></td></tr>
-<tr bgcolor="#7FFF00"><td><a name="usb1" >USB 1</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#D2691E"><td><a name="SD 0" >SD 0</a></td>             <td></td><td></td><td>MIO 40 .. 45</td></tr>
-<tr bgcolor="#D2691E"><td></td><td>CD</td><td></td><td>MIO 47</td></tr>
-<tr bgcolor="#D2691E"><td></td><td>WP</td><td></td><td>EMIO</td></tr>
-<tr bgcolor="#D2691E"><td></td><td>Power</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#D2691E"><td><a name="sd1" >SD 1</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#6495ED"><td><a name="UART 0" >UART 0</a></td>             <td></td><td></td><td>EMIO</td></tr>
-<tr bgcolor="#6495ED"><td></td><td></td><td>rx</td><td>EMIO</td></tr>
-<tr bgcolor="#6495ED"><td></td><td></td><td>tx</td><td>EMIO</td></tr>
-<tr bgcolor="#6495ED"><td></td><td>Modem signals</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#6495ED"><td><a name="UART 1" >UART 1</a></td>             <td></td><td></td><td>MIO 48 .. 49</td></tr>
-<tr bgcolor="#6495ED"><td></td><td></td><td>rx</td><td><a href="#MIO 49">MIO 49</a></td></tr>
-<tr bgcolor="#6495ED"><td></td><td></td><td>tx</td><td><a href="#MIO 48">MIO 48</a></td></tr>
-<tr bgcolor="#6495ED"><td></td><td>Modem Signals</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="I2C 0" >I2C 0</a></td>             <td></td><td></td><td>MIO 10 .. 11</td></tr>
-<tr bgcolor="#BDB76B"><td></td><td></td><td>scl</td><td><a href="#MIO 10">MIO 10</a></td></tr>
-<tr bgcolor="#BDB76B"><td></td><td></td><td>sda</td><td><a href="#MIO 11">MIO 11</a></td></tr>
-<tr bgcolor="#BDB76B"><td></td><td>Interrupt</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="I2C 1" >I2C 1</a></td>             <td></td><td></td><td>MIO 12 .. 13</td></tr>
-<tr bgcolor="#BDB76B"><td></td><td></td><td>scl</td><td><a href="#MIO 12">MIO 12</a></td></tr>
-<tr bgcolor="#BDB76B"><td></td><td></td><td>sda</td><td><a href="#MIO 13">MIO 13</a></td></tr>
-<tr bgcolor="#BDB76B"><td></td><td>Interrupt</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#8DBC8F"><td><a name="spi0" >SPI 0</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#8DBC8F"><td><a name="spi1" >SPI 1</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#DAA520"><td><a name="can0" >CAN 0</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#DAA520"><td><a name="can1" >CAN 1</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#ADD8E6"><td><a name="trace" >Trace</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#BC8F8F"><td><a name="ttc0" >Timer 0</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#BC8F8F"><td><a name="ttc1" >Timer 1</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FF6347"><td><a name="wdt" >Watchdog</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#EE82EE"><td><a name="pjtag" >PJTAG</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="GPIO" >GPIO</a></td>             <td></td><td></td><td>MIO</td></tr>
-<tr bgcolor="#FFFFFF"><td><a name="mode" >Mode</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FFFFFF"><td><a name="vcfg" >VCfg</a></td>             <td></td><td></td><td>Disabled</td></tr>
-</table></ul>
-<li><a href="#Top">Go To TOP</a></li>
-<h2><a name="DDRInfoTab">DDR Memory information</a></h2>
-<h3><a name="DDRInfoTab">DDR Controller Configuration</a></h3>
-<ul><table border="1"> 
-<tr><thead>                 <th>Parameter</th>                    <th>Value</th>                 </thead></tr>
-<tr> <td><a name="Enable DDR">Enable DDR</a></td><td>1</td></tr>
-<tr> <td><a name="Memory Type">Memory Type</a></td><td>DDR 3</td></tr>
-<tr> <td><a name="Memory Part">Memory Part</a></td><td>MT41K128M16 JT-125</td></tr>
-<tr> <td><a name="DRAM bus width">DRAM bus width</a></td><td>32 Bit</td></tr>
-<tr> <td><a name="ECC">ECC</a></td><td>Disabled</td></tr>
-<tr> <td><a name="BURST Length (lppdr only)">BURST Length (lppdr only)</a></td><td>8</td></tr>
-<tr> <td><a name="Internal Vref">Internal Vref</a></td><td>0</td></tr>
-<tr> <td><a name="Operating Frequency (MHz)">Operating Frequency (MHz)</a></td><td>525.000000</td></tr>
-<tr> <td><a name="HIGH temperature">HIGH temperature</a></td><td>Normal (0-85)</td></tr>
-</table></ul>
-<h3><a name="DDRInfoTab">Memory Part Configuration</a></h3>
-<ul><table border="1"> 
-<tr><thead>                 <th>Parameter</th>                    <th>Value</th>                 </thead></tr>
-<tr> <td><a name="DRAM IC bus width">DRAM IC bus width</a></td><td>16 Bits</td></tr>
-<tr> <td><a name="DRAM Device Capacity">DRAM Device Capacity</a></td><td>2048 MBits</td></tr>
-<tr> <td><a name="Speed Bin">Speed Bin</a></td><td>DDR3_1066F</td></tr>
-<tr> <td><a name="BANK Address Count">BANK Address Count</a></td><td>3</td></tr>
-<tr> <td><a name="ROW Address Count">ROW Address Count</a></td><td>14</td></tr>
-<tr> <td><a name="COLUMN Address Count">COLUMN Address Count</a></td><td>10</td></tr>
-<tr> <td><a name="CAS Latency">CAS Latency</a></td><td>7</td></tr>
-<tr> <td><a name="CAS Write Latency">CAS Write Latency</a></td><td>6</td></tr>
-<tr> <td><a name="RAS to CAS Delay">RAS to CAS Delay</a></td><td>7</td></tr>
-<tr> <td><a name="RECHARGE Time">RECHARGE Time</a></td><td>7</td></tr>
-<tr> <td><a name="tRC (ns )">tRC (ns )</a></td><td>48.75</td></tr>
-<tr> <td><a name="tRASmin ( ns )">tRASmin ( ns )</a></td><td>35.0</td></tr>
-<tr> <td><a name="tFAW">tFAW</a></td><td>40.0</td></tr>
-<tr> <td><a name="ADDITIVE Latency">ADDITIVE Latency</a></td><td>0</td></tr>
-</table></ul>
-<h3><a name="DDRInfoTab">Training/Board Details</a></h3>
-<ul><table border="1"> 
-<tr><thead>                 <th>Parameter</th>                    <th>Value</th>                 </thead></tr>
-<tr> <td><a name="Write levelling">Write levelling</a></td><td>1</td></tr>
-<tr> <td><a name="Read gate">Read gate</a></td><td>1</td></tr>
-<tr> <td><a name="Read data eye">Read data eye</a></td><td>1</td></tr>
-<tr> <td><a name="DQS to Clock delay [0] (ns)">DQS to Clock delay [0] (ns)</a></td><td>-0.073</td></tr>
-<tr> <td><a name="DQS to Clock delay [1] (ns)">DQS to Clock delay [1] (ns)</a></td><td>-0.034</td></tr>
-<tr> <td><a name="DQS to Clock delay [2] (ns)">DQS to Clock delay [2] (ns)</a></td><td>-0.03</td></tr>
-<tr> <td><a name="DQS to Clock delay [3] (ns)">DQS to Clock delay [3] (ns)</a></td><td>-0.082</td></tr>
-<tr> <td><a name="Board delay [0] (ns)">Board delay [0] (ns)</a></td><td>0.176</td></tr>
-<tr> <td><a name="Board delay [1] (ns)">Board delay [1] (ns)</a></td><td>0.159</td></tr>
-<tr> <td><a name="Board delay [2] (ns)">Board delay [2] (ns)</a></td><td>0.162</td></tr>
-<tr> <td><a name="Board delay [3] (ns)">Board delay [3] (ns)</a></td><td>0.187</td></tr>
-</table></ul>
-<li><a href="#Top">Go To TOP</a></li>
-<h1><a name="ps7_pll_init_data_1_0">ps7_pll_init_data_1_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>PLL SLCR REGISTERS</h2>
-<ul>
-<p>PLL SLCR REGISTERS</p>
-<h2>ARM PLL INIT</h2>
-<ul>
-<p>ARM PLL INIT</p>
-<li><p>Register : ARM_PLL_CFG @ 0XF8000110</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RES</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">c</td><td class="hex">c0</td></tr>
-<tr><td >PLL_CP</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >LOCK_CNT</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">177</td><td class="hex">177000</td></tr>
-<tr><td><b>ARM_PLL_CFG @ 0XF8000110</td><td></td><td class="hex"><b>3ffff0</b></td><td></td><td class="hex"><b>1772c0</b></td></tr></table>
-</li>
-<h2>UPDATE FB_DIV</h2>
-<ul>
-<p>UPDATE FB_DIV</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_FDIV</td><td class="hex">18:12</td><td class="hex">7f000</td><td class="hex">1a</td><td class="hex">1a000</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>7f000</b></td><td></td><td class="hex"><b>1a000</b></td></tr></table>
-</li>
-</ul>
-<h2>BY PASS PLL</h2>
-<ul>
-<p>BY PASS PLL</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>10</b></td></tr></table>
-</li>
-</ul>
-<h2>ASSERT RESET</h2>
-<ul>
-<p>ASSERT RESET</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>DEASSERT RESET</h2>
-<ul>
-<p>DEASSERT RESET</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>CHECK PLL STATUS</h2>
-<ul>
-<p>CHECK PLL STATUS</p>
-<li><p>Register : PLL_STATUS @ 0XF800010C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >ARM_PLL_LOCK</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>PLL_STATUS @ 0XF800010C</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>REMOVE PLL BY PASS</h2>
-<ul>
-<p>REMOVE PLL BY PASS</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : ARM_CLK_CTRL @ 0XF8000120</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >CPU_6OR4XCLKACT</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">1</td><td class="hex">1000000</td></tr>
-<tr><td >CPU_3OR2XCLKACT</td><td class="hex">25:25</td><td class="hex">2000000</td><td class="hex">1</td><td class="hex">2000000</td></tr>
-<tr><td >CPU_2XCLKACT</td><td class="hex">26:26</td><td class="hex">4000000</td><td class="hex">1</td><td class="hex">4000000</td></tr>
-<tr><td >CPU_1XCLKACT</td><td class="hex">27:27</td><td class="hex">8000000</td><td class="hex">1</td><td class="hex">8000000</td></tr>
-<tr><td >CPU_PERI_CLKACT</td><td class="hex">28:28</td><td class="hex">10000000</td><td class="hex">1</td><td class="hex">10000000</td></tr>
-<tr><td><b>ARM_CLK_CTRL @ 0XF8000120</td><td></td><td class="hex"><b>1f003f30</b></td><td></td><td class="hex"><b>1f000200</b></td></tr></table>
-</li>
-</ul>
-<h2>DDR PLL INIT</h2>
-<ul>
-<p>DDR PLL INIT</p>
-<li><p>Register : DDR_PLL_CFG @ 0XF8000114</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RES</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">c</td><td class="hex">c0</td></tr>
-<tr><td >PLL_CP</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >LOCK_CNT</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">1db</td><td class="hex">1db000</td></tr>
-<tr><td><b>DDR_PLL_CFG @ 0XF8000114</td><td></td><td class="hex"><b>3ffff0</b></td><td></td><td class="hex"><b>1db2c0</b></td></tr></table>
-</li>
-<h2>UPDATE FB_DIV</h2>
-<ul>
-<p>UPDATE FB_DIV</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_FDIV</td><td class="hex">18:12</td><td class="hex">7f000</td><td class="hex">15</td><td class="hex">15000</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>7f000</b></td><td></td><td class="hex"><b>15000</b></td></tr></table>
-</li>
-</ul>
-<h2>BY PASS PLL</h2>
-<ul>
-<p>BY PASS PLL</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>10</b></td></tr></table>
-</li>
-</ul>
-<h2>ASSERT RESET</h2>
-<ul>
-<p>ASSERT RESET</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>DEASSERT RESET</h2>
-<ul>
-<p>DEASSERT RESET</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>CHECK PLL STATUS</h2>
-<ul>
-<p>CHECK PLL STATUS</p>
-<li><p>Register : PLL_STATUS @ 0XF800010C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DDR_PLL_LOCK</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td><b>PLL_STATUS @ 0XF800010C</td><td></td><td class="hex"><b>2</b></td><td></td><td class="hex"><b>2</b></td></tr></table>
-</li>
-</ul>
-<h2>REMOVE PLL BY PASS</h2>
-<ul>
-<p>REMOVE PLL BY PASS</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : DDR_CLK_CTRL @ 0XF8000124</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DDR_3XCLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >DDR_2XCLKACT</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >DDR_3XCLK_DIVISOR</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">2</td><td class="hex">200000</td></tr>
-<tr><td >DDR_2XCLK_DIVISOR</td><td class="hex">31:26</td><td class="hex">fc000000</td><td class="hex">3</td><td class="hex">c000000</td></tr>
-<tr><td><b>DDR_CLK_CTRL @ 0XF8000124</td><td></td><td class="hex"><b>fff00003</b></td><td></td><td class="hex"><b>c200003</b></td></tr></table>
-</li>
-</ul>
-<h2>IO PLL INIT</h2>
-<ul>
-<p>IO PLL INIT</p>
-<li><p>Register : IO_PLL_CFG @ 0XF8000118</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RES</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">c</td><td class="hex">c0</td></tr>
-<tr><td >PLL_CP</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >LOCK_CNT</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">1f4</td><td class="hex">1f4000</td></tr>
-<tr><td><b>IO_PLL_CFG @ 0XF8000118</td><td></td><td class="hex"><b>3ffff0</b></td><td></td><td class="hex"><b>1f42c0</b></td></tr></table>
-</li>
-<h2>UPDATE FB_DIV</h2>
-<ul>
-<p>UPDATE FB_DIV</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_FDIV</td><td class="hex">18:12</td><td class="hex">7f000</td><td class="hex">14</td><td class="hex">14000</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>7f000</b></td><td></td><td class="hex"><b>14000</b></td></tr></table>
-</li>
-</ul>
-<h2>BY PASS PLL</h2>
-<ul>
-<p>BY PASS PLL</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>10</b></td></tr></table>
-</li>
-</ul>
-<h2>ASSERT RESET</h2>
-<ul>
-<p>ASSERT RESET</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>DEASSERT RESET</h2>
-<ul>
-<p>DEASSERT RESET</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>CHECK PLL STATUS</h2>
-<ul>
-<p>CHECK PLL STATUS</p>
-<li><p>Register : PLL_STATUS @ 0XF800010C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IO_PLL_LOCK</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td><b>PLL_STATUS @ 0XF800010C</td><td></td><td class="hex"><b>4</b></td><td></td><td class="hex"><b>4</b></td></tr></table>
-</li>
-</ul>
-<h2>REMOVE PLL BY PASS</h2>
-<ul>
-<p>REMOVE PLL BY PASS</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-</ul>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_clock_init_data_1_0">ps7_clock_init_data_1_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>CLOCK CONTROL SLCR REGISTERS</h2>
-<ul>
-<p>CLOCK CONTROL SLCR REGISTERS</p>
-<li><p>Register : DCI_CLK_CTRL @ 0XF8000128</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">34</td><td class="hex">3400</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">2</td><td class="hex">200000</td></tr>
-<tr><td><b>DCI_CLK_CTRL @ 0XF8000128</td><td></td><td class="hex"><b>3f03f01</b></td><td></td><td class="hex"><b>203401</b></td></tr></table>
-</li>
-<li><p>Register : GEM0_RCLK_CTRL @ 0XF8000138</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >SRCSEL</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>GEM0_RCLK_CTRL @ 0XF8000138</td><td></td><td class="hex"><b>11</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-<li><p>Register : GEM0_CLK_CTRL @ 0XF8000140</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >SRCSEL</td><td class="hex">6:4</td><td class="hex">70</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">8</td><td class="hex">800</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td><b>GEM0_CLK_CTRL @ 0XF8000140</td><td></td><td class="hex"><b>3f03f71</b></td><td></td><td class="hex"><b>100801</b></td></tr></table>
-</li>
-<li><p>Register : LQSPI_CLK_CTRL @ 0XF800014C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">5</td><td class="hex">500</td></tr>
-<tr><td><b>LQSPI_CLK_CTRL @ 0XF800014C</td><td></td><td class="hex"><b>3f31</b></td><td></td><td class="hex"><b>501</b></td></tr></table>
-</li>
-<li><p>Register : SDIO_CLK_CTRL @ 0XF8000150</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT0</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >CLKACT1</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">14</td><td class="hex">1400</td></tr>
-<tr><td><b>SDIO_CLK_CTRL @ 0XF8000150</td><td></td><td class="hex"><b>3f33</b></td><td></td><td class="hex"><b>1401</b></td></tr></table>
-</li>
-<li><p>Register : UART_CLK_CTRL @ 0XF8000154</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT0</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >CLKACT1</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">14</td><td class="hex">1400</td></tr>
-<tr><td><b>UART_CLK_CTRL @ 0XF8000154</td><td></td><td class="hex"><b>3f33</b></td><td></td><td class="hex"><b>1403</b></td></tr></table>
-</li>
-<li><p>Register : PCAP_CLK_CTRL @ 0XF8000168</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">5</td><td class="hex">500</td></tr>
-<tr><td><b>PCAP_CLK_CTRL @ 0XF8000168</td><td></td><td class="hex"><b>3f31</b></td><td></td><td class="hex"><b>501</b></td></tr></table>
-</li>
-<li><p>Register : FPGA0_CLK_CTRL @ 0XF8000170</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">a</td><td class="hex">a00</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td><b>FPGA0_CLK_CTRL @ 0XF8000170</td><td></td><td class="hex"><b>3f03f30</b></td><td></td><td class="hex"><b>100a00</b></td></tr></table>
-</li>
-<li><p>Register : FPGA1_CLK_CTRL @ 0XF8000180</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">3</td><td class="hex">30</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">6</td><td class="hex">600</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td><b>FPGA1_CLK_CTRL @ 0XF8000180</td><td></td><td class="hex"><b>3f03f30</b></td><td></td><td class="hex"><b>100630</b></td></tr></table>
-</li>
-<li><p>Register : FPGA2_CLK_CTRL @ 0XF8000190</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">2</td><td class="hex">20</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">35</td><td class="hex">3500</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">2</td><td class="hex">200000</td></tr>
-<tr><td><b>FPGA2_CLK_CTRL @ 0XF8000190</td><td></td><td class="hex"><b>3f03f30</b></td><td></td><td class="hex"><b>203520</b></td></tr></table>
-</li>
-<li><p>Register : FPGA3_CLK_CTRL @ 0XF80001A0</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">a</td><td class="hex">a00</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td><b>FPGA3_CLK_CTRL @ 0XF80001A0</td><td></td><td class="hex"><b>3f03f30</b></td><td></td><td class="hex"><b>100a00</b></td></tr></table>
-</li>
-<li><p>Register : CLK_621_TRUE @ 0XF80001C4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLK_621_TRUE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>CLK_621_TRUE @ 0XF80001C4</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-<li><p>Register : APER_CLK_CTRL @ 0XF800012C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DMA_CPU_2XCLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >USB0_CPU_1XCLKACT</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >USB1_CPU_1XCLKACT</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">1</td><td class="hex">8</td></tr>
-<tr><td >GEM0_CPU_1XCLKACT</td><td class="hex">6:6</td><td class="hex">40</td><td class="hex">1</td><td class="hex">40</td></tr>
-<tr><td >GEM1_CPU_1XCLKACT</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >SDI0_CPU_1XCLKACT</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">1</td><td class="hex">400</td></tr>
-<tr><td >SDI1_CPU_1XCLKACT</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >SPI0_CPU_1XCLKACT</td><td class="hex">14:14</td><td class="hex">4000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >SPI1_CPU_1XCLKACT</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CAN0_CPU_1XCLKACT</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CAN1_CPU_1XCLKACT</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >I2C0_CPU_1XCLKACT</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">1</td><td class="hex">40000</td></tr>
-<tr><td >I2C1_CPU_1XCLKACT</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td >UART0_CPU_1XCLKACT</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td >UART1_CPU_1XCLKACT</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">1</td><td class="hex">200000</td></tr>
-<tr><td >GPIO_CPU_1XCLKACT</td><td class="hex">22:22</td><td class="hex">400000</td><td class="hex">1</td><td class="hex">400000</td></tr>
-<tr><td >LQSPI_CPU_1XCLKACT</td><td class="hex">23:23</td><td class="hex">800000</td><td class="hex">1</td><td class="hex">800000</td></tr>
-<tr><td >SMC_CPU_1XCLKACT</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">1</td><td class="hex">1000000</td></tr>
-<tr><td><b>APER_CLK_CTRL @ 0XF800012C</td><td></td><td class="hex"><b>1ffcccd</b></td><td></td><td class="hex"><b>1fc044d</b></td></tr></table>
-</li>
-</ul>
-<h2>THIS SHOULD BE BLANK</h2>
-<ul>
-<p>THIS SHOULD BE BLANK</p>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_ddr_init_data_1_0">ps7_ddr_init_data_1_0</a></h1>
-<ul>
-<h2>DDR INITIALIZATION</h2>
-<ul>
-<p>DDR INITIALIZATION</p>
-<h2>LOCK DDR</h2>
-<ul>
-<p>LOCK DDR</p>
-<li><p>Register : ddrc_ctrl @ 0XF8006000</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_soft_rstb</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_powerdown_en</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_data_bus_width</td><td class="hex">3:2</td><td class="hex">c</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_burst8_refresh</td><td class="hex">6:4</td><td class="hex">70</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rdwr_idle_gap</td><td class="hex">13:7</td><td class="hex">3f80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >reg_ddrc_dis_rd_bypass</td><td class="hex">14:14</td><td class="hex">4000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_act_bypass</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_auto_refresh</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ddrc_ctrl @ 0XF8006000</td><td></td><td class="hex"><b>1ffff</b></td><td></td><td class="hex"><b>80</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : Two_rank_cfg @ 0XF8006004</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_t_rfc_nom_x32</td><td class="hex">11:0</td><td class="hex">fff</td><td class="hex">7f</td><td class="hex">7f</td></tr>
-<tr><td >reg_ddrc_active_ranks</td><td class="hex">13:12</td><td class="hex">3000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >reg_ddrc_addrmap_cs_bit0</td><td class="hex">18:14</td><td class="hex">7c000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_wr_odt_block</td><td class="hex">20:19</td><td class="hex">180000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td >reg_ddrc_diff_rank_rd_2cycle_gap</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_cs_bit1</td><td class="hex">26:22</td><td class="hex">7c00000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_open_bank</td><td class="hex">27:27</td><td class="hex">8000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_4bank_ram</td><td class="hex">28:28</td><td class="hex">10000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>Two_rank_cfg @ 0XF8006004</td><td></td><td class="hex"><b>1fffffff</b></td><td></td><td class="hex"><b>8107f</b></td></tr></table>
-</li>
-<li><p>Register : HPR_reg @ 0XF8006008</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_hpr_min_non_critical_x32</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">f</td><td class="hex">f</td></tr>
-<tr><td >reg_ddrc_hpr_max_starve_x32</td><td class="hex">21:11</td><td class="hex">3ff800</td><td class="hex">f</td><td class="hex">7800</td></tr>
-<tr><td >reg_ddrc_hpr_xact_run_length</td><td class="hex">25:22</td><td class="hex">3c00000</td><td class="hex">f</td><td class="hex">3c00000</td></tr>
-<tr><td><b>HPR_reg @ 0XF8006008</td><td></td><td class="hex"><b>3ffffff</b></td><td></td><td class="hex"><b>3c0780f</b></td></tr></table>
-</li>
-<li><p>Register : LPR_reg @ 0XF800600C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_lpr_min_non_critical_x32</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_ddrc_lpr_max_starve_x32</td><td class="hex">21:11</td><td class="hex">3ff800</td><td class="hex">2</td><td class="hex">1000</td></tr>
-<tr><td >reg_ddrc_lpr_xact_run_length</td><td class="hex">25:22</td><td class="hex">3c00000</td><td class="hex">8</td><td class="hex">2000000</td></tr>
-<tr><td><b>LPR_reg @ 0XF800600C</td><td></td><td class="hex"><b>3ffffff</b></td><td></td><td class="hex"><b>2001001</b></td></tr></table>
-</li>
-<li><p>Register : WR_reg @ 0XF8006010</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_w_min_non_critical_x32</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_ddrc_w_xact_run_length</td><td class="hex">14:11</td><td class="hex">7800</td><td class="hex">8</td><td class="hex">4000</td></tr>
-<tr><td >reg_ddrc_w_max_starve_x32</td><td class="hex">25:15</td><td class="hex">3ff8000</td><td class="hex">2</td><td class="hex">10000</td></tr>
-<tr><td><b>WR_reg @ 0XF8006010</td><td></td><td class="hex"><b>3ffffff</b></td><td></td><td class="hex"><b>14001</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg0 @ 0XF8006014</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_t_rc</td><td class="hex">5:0</td><td class="hex">3f</td><td class="hex">1a</td><td class="hex">1a</td></tr>
-<tr><td >reg_ddrc_t_rfc_min</td><td class="hex">13:6</td><td class="hex">3fc0</td><td class="hex">54</td><td class="hex">1500</td></tr>
-<tr><td >reg_ddrc_post_selfref_gap_x32</td><td class="hex">20:14</td><td class="hex">1fc000</td><td class="hex">10</td><td class="hex">40000</td></tr>
-<tr><td><b>DRAM_param_reg0 @ 0XF8006014</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>4151a</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg1 @ 0XF8006018</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_wr2pre</td><td class="hex">4:0</td><td class="hex">1f</td><td class="hex">12</td><td class="hex">12</td></tr>
-<tr><td >reg_ddrc_powerdown_to_x32</td><td class="hex">9:5</td><td class="hex">3e0</td><td class="hex">6</td><td class="hex">c0</td></tr>
-<tr><td >reg_ddrc_t_faw</td><td class="hex">15:10</td><td class="hex">fc00</td><td class="hex">15</td><td class="hex">5400</td></tr>
-<tr><td >reg_ddrc_t_ras_max</td><td class="hex">21:16</td><td class="hex">3f0000</td><td class="hex">23</td><td class="hex">230000</td></tr>
-<tr><td >reg_ddrc_t_ras_min</td><td class="hex">26:22</td><td class="hex">7c00000</td><td class="hex">13</td><td class="hex">4c00000</td></tr>
-<tr><td >reg_ddrc_t_cke</td><td class="hex">31:28</td><td class="hex">f0000000</td><td class="hex">4</td><td class="hex">40000000</td></tr>
-<tr><td><b>DRAM_param_reg1 @ 0XF8006018</td><td></td><td class="hex"><b>f7ffffff</b></td><td></td><td class="hex"><b>44e354d2</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg2 @ 0XF800601C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_write_latency</td><td class="hex">4:0</td><td class="hex">1f</td><td class="hex">5</td><td class="hex">5</td></tr>
-<tr><td >reg_ddrc_rd2wr</td><td class="hex">9:5</td><td class="hex">3e0</td><td class="hex">7</td><td class="hex">e0</td></tr>
-<tr><td >reg_ddrc_wr2rd</td><td class="hex">14:10</td><td class="hex">7c00</td><td class="hex">e</td><td class="hex">3800</td></tr>
-<tr><td >reg_ddrc_t_xp</td><td class="hex">19:15</td><td class="hex">f8000</td><td class="hex">4</td><td class="hex">20000</td></tr>
-<tr><td >reg_ddrc_pad_pd</td><td class="hex">22:20</td><td class="hex">700000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rd2pre</td><td class="hex">27:23</td><td class="hex">f800000</td><td class="hex">4</td><td class="hex">2000000</td></tr>
-<tr><td >reg_ddrc_t_rcd</td><td class="hex">31:28</td><td class="hex">f0000000</td><td class="hex">7</td><td class="hex">70000000</td></tr>
-<tr><td><b>DRAM_param_reg2 @ 0XF800601C</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>720238e5</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg3 @ 0XF8006020</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_t_ccd</td><td class="hex">4:2</td><td class="hex">1c</td><td class="hex">4</td><td class="hex">10</td></tr>
-<tr><td >reg_ddrc_t_rrd</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">6</td><td class="hex">c0</td></tr>
-<tr><td >reg_ddrc_refresh_margin</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >reg_ddrc_t_rp</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">7</td><td class="hex">7000</td></tr>
-<tr><td >reg_ddrc_refresh_to_x32</td><td class="hex">20:16</td><td class="hex">1f0000</td><td class="hex">8</td><td class="hex">80000</td></tr>
-<tr><td >reg_ddrc_sdram</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">1</td><td class="hex">200000</td></tr>
-<tr><td >reg_ddrc_mobile</td><td class="hex">22:22</td><td class="hex">400000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_clock_stop_en</td><td class="hex">23:23</td><td class="hex">800000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_read_latency</td><td class="hex">28:24</td><td class="hex">1f000000</td><td class="hex">7</td><td class="hex">7000000</td></tr>
-<tr><td >reg_phy_mode_ddr1_ddr2</td><td class="hex">29:29</td><td class="hex">20000000</td><td class="hex">1</td><td class="hex">20000000</td></tr>
-<tr><td >reg_ddrc_dis_pad_pd</td><td class="hex">30:30</td><td class="hex">40000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_loopback</td><td class="hex">31:31</td><td class="hex">80000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_param_reg3 @ 0XF8006020</td><td></td><td class="hex"><b>fffffffc</b></td><td></td><td class="hex"><b>272872d0</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg4 @ 0XF8006024</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_en_2t_timing_mode</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_prefer_write</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_max_rank_rd</td><td class="hex">5:2</td><td class="hex">3c</td><td class="hex">f</td><td class="hex">3c</td></tr>
-<tr><td >reg_ddrc_mr_wr</td><td class="hex">6:6</td><td class="hex">40</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr_addr</td><td class="hex">8:7</td><td class="hex">180</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr_data</td><td class="hex">24:9</td><td class="hex">1fffe00</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >ddrc_reg_mr_wr_busy</td><td class="hex">25:25</td><td class="hex">2000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr_type</td><td class="hex">26:26</td><td class="hex">4000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr_rdata_valid</td><td class="hex">27:27</td><td class="hex">8000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_param_reg4 @ 0XF8006024</td><td></td><td class="hex"><b>fffffff</b></td><td></td><td class="hex"><b>3c</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_init_param @ 0XF8006028</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_final_wait_x32</td><td class="hex">6:0</td><td class="hex">7f</td><td class="hex">7</td><td class="hex">7</td></tr>
-<tr><td >reg_ddrc_pre_ocd_x32</td><td class="hex">10:7</td><td class="hex">780</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_t_mrd</td><td class="hex">13:11</td><td class="hex">3800</td><td class="hex">4</td><td class="hex">2000</td></tr>
-<tr><td><b>DRAM_init_param @ 0XF8006028</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2007</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_EMR_reg @ 0XF800602C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_emr2</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">8</td><td class="hex">8</td></tr>
-<tr><td >reg_ddrc_emr3</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_EMR_reg @ 0XF800602C</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>8</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_EMR_MR_reg @ 0XF8006030</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_mr</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">930</td><td class="hex">930</td></tr>
-<tr><td >reg_ddrc_emr</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">4</td><td class="hex">40000</td></tr>
-<tr><td><b>DRAM_EMR_MR_reg @ 0XF8006030</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>40930</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_burst8_rdwr @ 0XF8006034</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_burst_rdwr</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">4</td><td class="hex">4</td></tr>
-<tr><td >reg_ddrc_pre_cke_x1024</td><td class="hex">13:4</td><td class="hex">3ff0</td><td class="hex">101</td><td class="hex">1010</td></tr>
-<tr><td >reg_ddrc_post_cke_x1024</td><td class="hex">25:16</td><td class="hex">3ff0000</td><td class="hex">1</td><td class="hex">10000</td></tr>
-<tr><td >reg_ddrc_burstchop</td><td class="hex">28:28</td><td class="hex">10000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_burst8_rdwr @ 0XF8006034</td><td></td><td class="hex"><b>13ff3fff</b></td><td></td><td class="hex"><b>11014</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_disable_DQ @ 0XF8006038</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_force_low_pri_n</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_dq</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_debug_mode</td><td class="hex">6:6</td><td class="hex">40</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_level_start</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rd_level_start</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq0_wait_t</td><td class="hex">12:9</td><td class="hex">1e00</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_disable_DQ @ 0XF8006038</td><td></td><td class="hex"><b>1fc3</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_addr_map_bank @ 0XF800603C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_addrmap_bank_b0</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">7</td><td class="hex">7</td></tr>
-<tr><td >reg_ddrc_addrmap_bank_b1</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">7</td><td class="hex">70</td></tr>
-<tr><td >reg_ddrc_addrmap_bank_b2</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">7</td><td class="hex">700</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b5</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b6</td><td class="hex">19:16</td><td class="hex">f0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_addr_map_bank @ 0XF800603C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>777</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_addr_map_col @ 0XF8006040</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_addrmap_col_b2</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b3</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b4</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b7</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b8</td><td class="hex">19:16</td><td class="hex">f0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b9</td><td class="hex">23:20</td><td class="hex">f00000</td><td class="hex">f</td><td class="hex">f00000</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b10</td><td class="hex">27:24</td><td class="hex">f000000</td><td class="hex">f</td><td class="hex">f000000</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b11</td><td class="hex">31:28</td><td class="hex">f0000000</td><td class="hex">f</td><td class="hex">f0000000</td></tr>
-<tr><td><b>DRAM_addr_map_col @ 0XF8006040</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>fff00000</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_addr_map_row @ 0XF8006044</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_addrmap_row_b0</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">6</td><td class="hex">6</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b1</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">6</td><td class="hex">60</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b2_11</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">6</td><td class="hex">600</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b12</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">6</td><td class="hex">6000</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b13</td><td class="hex">19:16</td><td class="hex">f0000</td><td class="hex">6</td><td class="hex">60000</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b14</td><td class="hex">23:20</td><td class="hex">f00000</td><td class="hex">f</td><td class="hex">f00000</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b15</td><td class="hex">27:24</td><td class="hex">f000000</td><td class="hex">f</td><td class="hex">f000000</td></tr>
-<tr><td><b>DRAM_addr_map_row @ 0XF8006044</td><td></td><td class="hex"><b>fffffff</b></td><td></td><td class="hex"><b>ff66666</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_ODT_reg @ 0XF8006048</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_rank0_rd_odt</td><td class="hex">2:0</td><td class="hex">7</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rank0_wr_odt</td><td class="hex">5:3</td><td class="hex">38</td><td class="hex">1</td><td class="hex">8</td></tr>
-<tr><td >reg_ddrc_rank1_rd_odt</td><td class="hex">8:6</td><td class="hex">1c0</td><td class="hex">1</td><td class="hex">40</td></tr>
-<tr><td >reg_ddrc_rank1_wr_odt</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >reg_phy_rd_local_odt</td><td class="hex">13:12</td><td class="hex">3000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_local_odt</td><td class="hex">15:14</td><td class="hex">c000</td><td class="hex">3</td><td class="hex">c000</td></tr>
-<tr><td >reg_phy_idle_local_odt</td><td class="hex">17:16</td><td class="hex">30000</td><td class="hex">3</td><td class="hex">30000</td></tr>
-<tr><td >reg_ddrc_rank2_rd_odt</td><td class="hex">20:18</td><td class="hex">1c0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rank2_wr_odt</td><td class="hex">23:21</td><td class="hex">e00000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rank3_rd_odt</td><td class="hex">26:24</td><td class="hex">7000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rank3_wr_odt</td><td class="hex">29:27</td><td class="hex">38000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_ODT_reg @ 0XF8006048</td><td></td><td class="hex"><b>3fffffff</b></td><td></td><td class="hex"><b>3c248</b></td></tr></table>
-</li>
-<li><p>Register : phy_cmd_timeout_rddata_cpt @ 0XF8006050</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_cmd_to_data</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_cmd_to_data</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rdc_we_to_re_delay</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">8</td><td class="hex">800</td></tr>
-<tr><td >reg_phy_rdc_fifo_rst_disable</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_use_fixed_re</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">1</td><td class="hex">10000</td></tr>
-<tr><td >reg_phy_rdc_fifo_rst_err_cnt_clr</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dis_phy_ctrl_rstn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_clk_stall_level</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_num_of_dq0</td><td class="hex">27:24</td><td class="hex">f000000</td><td class="hex">7</td><td class="hex">7000000</td></tr>
-<tr><td >reg_phy_wrlvl_num_of_dq0</td><td class="hex">31:28</td><td class="hex">f0000000</td><td class="hex">7</td><td class="hex">70000000</td></tr>
-<tr><td><b>phy_cmd_timeout_rddata_cpt @ 0XF8006050</td><td></td><td class="hex"><b>ff0f8fff</b></td><td></td><td class="hex"><b>77010800</b></td></tr></table>
-</li>
-<li><p>Register : DLL_calib @ 0XF8006058</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_dll_calib_to_min_x1024</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_ddrc_dll_calib_to_max_x1024</td><td class="hex">15:8</td><td class="hex">ff00</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >reg_ddrc_dis_dll_calib</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DLL_calib @ 0XF8006058</td><td></td><td class="hex"><b>1ffff</b></td><td></td><td class="hex"><b>101</b></td></tr></table>
-</li>
-<li><p>Register : ODT_delay_hold @ 0XF800605C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_rd_odt_delay</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">3</td><td class="hex">3</td></tr>
-<tr><td >reg_ddrc_wr_odt_delay</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rd_odt_hold</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_wr_odt_hold</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">5</td><td class="hex">5000</td></tr>
-<tr><td><b>ODT_delay_hold @ 0XF800605C</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>5003</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg1 @ 0XF8006060</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_pageclose</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_lpr_num_entries</td><td class="hex">6:1</td><td class="hex">7e</td><td class="hex">1f</td><td class="hex">3e</td></tr>
-<tr><td >reg_ddrc_auto_pre_en</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_refresh_update_level</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_wc</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_collision_page_opt</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_selfref_en</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ctrl_reg1 @ 0XF8006060</td><td></td><td class="hex"><b>17ff</b></td><td></td><td class="hex"><b>3e</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg2 @ 0XF8006064</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_go2critical_hysteresis</td><td class="hex">12:5</td><td class="hex">1fe0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_go2critical_en</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">1</td><td class="hex">20000</td></tr>
-<tr><td><b>ctrl_reg2 @ 0XF8006064</td><td></td><td class="hex"><b>21fe0</b></td><td></td><td class="hex"><b>20000</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg3 @ 0XF8006068</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_wrlvl_ww</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">41</td><td class="hex">41</td></tr>
-<tr><td >reg_ddrc_rdlvl_rr</td><td class="hex">15:8</td><td class="hex">ff00</td><td class="hex">41</td><td class="hex">4100</td></tr>
-<tr><td >reg_ddrc_dfi_t_wlmrd</td><td class="hex">25:16</td><td class="hex">3ff0000</td><td class="hex">28</td><td class="hex">280000</td></tr>
-<tr><td><b>ctrl_reg3 @ 0XF8006068</td><td></td><td class="hex"><b>3ffffff</b></td><td></td><td class="hex"><b>284141</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg4 @ 0XF800606C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >dfi_t_ctrlupd_interval_min_x1024</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">10</td><td class="hex">10</td></tr>
-<tr><td >dfi_t_ctrlupd_interval_max_x1024</td><td class="hex">15:8</td><td class="hex">ff00</td><td class="hex">16</td><td class="hex">1600</td></tr>
-<tr><td><b>ctrl_reg4 @ 0XF800606C</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>1610</b></td></tr></table>
-</li>
-<li><p>Register : CHE_REFRESH_TIMER01 @ 0XF80060A0</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >refresh_timer0_start_value_x32</td><td class="hex">11:0</td><td class="hex">fff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >refresh_timer1_start_value_x32</td><td class="hex">23:12</td><td class="hex">fff000</td><td class="hex">8</td><td class="hex">8000</td></tr>
-<tr><td><b>CHE_REFRESH_TIMER01 @ 0XF80060A0</td><td></td><td class="hex"><b>ffffff</b></td><td></td><td class="hex"><b>8000</b></td></tr></table>
-</li>
-<li><p>Register : CHE_T_ZQ @ 0XF80060A4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_dis_auto_zq</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_ddr3</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >reg_ddrc_t_mod</td><td class="hex">11:2</td><td class="hex">ffc</td><td class="hex">200</td><td class="hex">800</td></tr>
-<tr><td >reg_ddrc_t_zq_long_nop</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">200</td><td class="hex">200000</td></tr>
-<tr><td >reg_ddrc_t_zq_short_nop</td><td class="hex">31:22</td><td class="hex">ffc00000</td><td class="hex">40</td><td class="hex">10000000</td></tr>
-<tr><td><b>CHE_T_ZQ @ 0XF80060A4</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>10200802</b></td></tr></table>
-</li>
-<li><p>Register : CHE_T_ZQ_Short_Interval_Reg @ 0XF80060A8</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >t_zq_short_interval_x1024</td><td class="hex">19:0</td><td class="hex">fffff</td><td class="hex">c845</td><td class="hex">c845</td></tr>
-<tr><td >dram_rstn_x1024</td><td class="hex">27:20</td><td class="hex">ff00000</td><td class="hex">67</td><td class="hex">6700000</td></tr>
-<tr><td><b>CHE_T_ZQ_Short_Interval_Reg @ 0XF80060A8</td><td></td><td class="hex"><b>fffffff</b></td><td></td><td class="hex"><b>670c845</b></td></tr></table>
-</li>
-<li><p>Register : deep_pwrdwn_reg @ 0XF80060AC</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >deeppowerdown_en</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >deeppowerdown_to_x1024</td><td class="hex">8:1</td><td class="hex">1fe</td><td class="hex">ff</td><td class="hex">1fe</td></tr>
-<tr><td><b>deep_pwrdwn_reg @ 0XF80060AC</td><td></td><td class="hex"><b>1ff</b></td><td></td><td class="hex"><b>1fe</b></td></tr></table>
-</li>
-<li><p>Register : reg_2c @ 0XF80060B0</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >dfi_wrlvl_max_x1024</td><td class="hex">11:0</td><td class="hex">fff</td><td class="hex">fff</td><td class="hex">fff</td></tr>
-<tr><td >dfi_rdlvl_max_x1024</td><td class="hex">23:12</td><td class="hex">fff000</td><td class="hex">fff</td><td class="hex">fff000</td></tr>
-<tr><td >ddrc_reg_twrlvl_max_error</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >ddrc_reg_trdlvl_max_error</td><td class="hex">25:25</td><td class="hex">2000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dfi_wr_level_en</td><td class="hex">26:26</td><td class="hex">4000000</td><td class="hex">1</td><td class="hex">4000000</td></tr>
-<tr><td >reg_ddrc_dfi_rd_dqs_gate_level</td><td class="hex">27:27</td><td class="hex">8000000</td><td class="hex">1</td><td class="hex">8000000</td></tr>
-<tr><td >reg_ddrc_dfi_rd_data_eye_train</td><td class="hex">28:28</td><td class="hex">10000000</td><td class="hex">1</td><td class="hex">10000000</td></tr>
-<tr><td><b>reg_2c @ 0XF80060B0</td><td></td><td class="hex"><b>1fffffff</b></td><td></td><td class="hex"><b>1cffffff</b></td></tr></table>
-</li>
-<li><p>Register : reg_2d @ 0XF80060B4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_2t_delay</td><td class="hex">8:0</td><td class="hex">1ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_skip_ocd</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >reg_ddrc_dis_pre_bypass</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>reg_2d @ 0XF80060B4</td><td></td><td class="hex"><b>7ff</b></td><td></td><td class="hex"><b>200</b></td></tr></table>
-</li>
-<li><p>Register : dfi_timing @ 0XF80060B8</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_dfi_t_rddata_en</td><td class="hex">4:0</td><td class="hex">1f</td><td class="hex">6</td><td class="hex">6</td></tr>
-<tr><td >reg_ddrc_dfi_t_ctrlup_min</td><td class="hex">14:5</td><td class="hex">7fe0</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >reg_ddrc_dfi_t_ctrlup_max</td><td class="hex">24:15</td><td class="hex">1ff8000</td><td class="hex">40</td><td class="hex">200000</td></tr>
-<tr><td><b>dfi_timing @ 0XF80060B8</td><td></td><td class="hex"><b>1ffffff</b></td><td></td><td class="hex"><b>200066</b></td></tr></table>
-</li>
-<li><p>Register : CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >Clear_Uncorrectable_DRAM_ECC_error</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >Clear_Correctable_DRAM_ECC_error</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td><b>CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4</td><td></td><td class="hex"><b>3</b></td><td></td><td class="hex"><b>3</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >Clear_Uncorrectable_DRAM_ECC_error</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Clear_Correctable_DRAM_ECC_error</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4</td><td></td><td class="hex"><b>3</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : CHE_CORR_ECC_LOG_REG_OFFSET @ 0XF80060C8</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CORR_ECC_LOG_VALID</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >ECC_CORRECTED_BIT_NUM</td><td class="hex">7:1</td><td class="hex">fe</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CHE_CORR_ECC_LOG_REG_OFFSET @ 0XF80060C8</td><td></td><td class="hex"><b>ff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : CHE_UNCORR_ECC_LOG_REG_OFFSET @ 0XF80060DC</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNCORR_ECC_LOG_VALID</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CHE_UNCORR_ECC_LOG_REG_OFFSET @ 0XF80060DC</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : CHE_ECC_STATS_REG_OFFSET @ 0XF80060F0</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >STAT_NUM_CORR_ERR</td><td class="hex">15:8</td><td class="hex">ff00</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >STAT_NUM_UNCORR_ERR</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CHE_ECC_STATS_REG_OFFSET @ 0XF80060F0</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : ECC_scrub @ 0XF80060F4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_ecc_mode</td><td class="hex">2:0</td><td class="hex">7</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_scrub</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">1</td><td class="hex">8</td></tr>
-<tr><td><b>ECC_scrub @ 0XF80060F4</td><td></td><td class="hex"><b>f</b></td><td></td><td class="hex"><b>8</b></td></tr></table>
-</li>
-<li><p>Register : phy_rcvr_enable @ 0XF8006114</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_dif_on</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dif_off</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rcvr_enable @ 0XF8006114</td><td></td><td class="hex"><b>ff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : PHY_Config @ 0XF8006118</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_data_slice_in_use</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_phy_rdlvl_inc_mode</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_inc_mode</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wrlvl_inc_mode</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_tx</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_rx</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_shift_dq</td><td class="hex">14:6</td><td class="hex">7fc0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_err_clr</td><td class="hex">23:15</td><td class="hex">ff8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq_offset</td><td class="hex">30:24</td><td class="hex">7f000000</td><td class="hex">40</td><td class="hex">40000000</td></tr>
-<tr><td><b>PHY_Config @ 0XF8006118</td><td></td><td class="hex"><b>7fffffff</b></td><td></td><td class="hex"><b>40000001</b></td></tr></table>
-</li>
-<li><p>Register : PHY_Config @ 0XF800611C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_data_slice_in_use</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_phy_rdlvl_inc_mode</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_inc_mode</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wrlvl_inc_mode</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_tx</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_rx</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_shift_dq</td><td class="hex">14:6</td><td class="hex">7fc0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_err_clr</td><td class="hex">23:15</td><td class="hex">ff8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq_offset</td><td class="hex">30:24</td><td class="hex">7f000000</td><td class="hex">40</td><td class="hex">40000000</td></tr>
-<tr><td><b>PHY_Config @ 0XF800611C</td><td></td><td class="hex"><b>7fffffff</b></td><td></td><td class="hex"><b>40000001</b></td></tr></table>
-</li>
-<li><p>Register : PHY_Config @ 0XF8006120</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_data_slice_in_use</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_phy_rdlvl_inc_mode</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_inc_mode</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wrlvl_inc_mode</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_tx</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_rx</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_shift_dq</td><td class="hex">14:6</td><td class="hex">7fc0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_err_clr</td><td class="hex">23:15</td><td class="hex">ff8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq_offset</td><td class="hex">30:24</td><td class="hex">7f000000</td><td class="hex">40</td><td class="hex">40000000</td></tr>
-<tr><td><b>PHY_Config @ 0XF8006120</td><td></td><td class="hex"><b>7fffffff</b></td><td></td><td class="hex"><b>40000001</b></td></tr></table>
-</li>
-<li><p>Register : PHY_Config @ 0XF8006124</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_data_slice_in_use</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_phy_rdlvl_inc_mode</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_inc_mode</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wrlvl_inc_mode</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_tx</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_rx</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_shift_dq</td><td class="hex">14:6</td><td class="hex">7fc0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_err_clr</td><td class="hex">23:15</td><td class="hex">ff8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq_offset</td><td class="hex">30:24</td><td class="hex">7f000000</td><td class="hex">40</td><td class="hex">40000000</td></tr>
-<tr><td><b>PHY_Config @ 0XF8006124</td><td></td><td class="hex"><b>7fffffff</b></td><td></td><td class="hex"><b>40000001</b></td></tr></table>
-</li>
-<li><p>Register : phy_init_ratio @ 0XF800612C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wrlvl_init_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_init_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">8f</td><td class="hex">23c00</td></tr>
-<tr><td><b>phy_init_ratio @ 0XF800612C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>23c00</b></td></tr></table>
-</li>
-<li><p>Register : phy_init_ratio @ 0XF8006130</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wrlvl_init_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_init_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">8a</td><td class="hex">22800</td></tr>
-<tr><td><b>phy_init_ratio @ 0XF8006130</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>22800</b></td></tr></table>
-</li>
-<li><p>Register : phy_init_ratio @ 0XF8006134</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wrlvl_init_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_init_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">8b</td><td class="hex">22c00</td></tr>
-<tr><td><b>phy_init_ratio @ 0XF8006134</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>22c00</b></td></tr></table>
-</li>
-<li><p>Register : phy_init_ratio @ 0XF8006138</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wrlvl_init_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_init_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">92</td><td class="hex">24800</td></tr>
-<tr><td><b>phy_init_ratio @ 0XF8006138</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>24800</b></td></tr></table>
-</li>
-<li><p>Register : phy_rd_dqs_cfg @ 0XF8006140</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">35</td><td class="hex">35</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rd_dqs_cfg @ 0XF8006140</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>35</b></td></tr></table>
-</li>
-<li><p>Register : phy_rd_dqs_cfg @ 0XF8006144</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">35</td><td class="hex">35</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rd_dqs_cfg @ 0XF8006144</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>35</b></td></tr></table>
-</li>
-<li><p>Register : phy_rd_dqs_cfg @ 0XF8006148</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">35</td><td class="hex">35</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rd_dqs_cfg @ 0XF8006148</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>35</b></td></tr></table>
-</li>
-<li><p>Register : phy_rd_dqs_cfg @ 0XF800614C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">35</td><td class="hex">35</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rd_dqs_cfg @ 0XF800614C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>35</b></td></tr></table>
-</li>
-<li><p>Register : phy_wr_dqs_cfg @ 0XF8006154</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">77</td><td class="hex">77</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_wr_dqs_cfg @ 0XF8006154</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>77</b></td></tr></table>
-</li>
-<li><p>Register : phy_wr_dqs_cfg @ 0XF8006158</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">7c</td><td class="hex">7c</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_wr_dqs_cfg @ 0XF8006158</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>7c</b></td></tr></table>
-</li>
-<li><p>Register : phy_wr_dqs_cfg @ 0XF800615C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">7c</td><td class="hex">7c</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_wr_dqs_cfg @ 0XF800615C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>7c</b></td></tr></table>
-</li>
-<li><p>Register : phy_wr_dqs_cfg @ 0XF8006160</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">75</td><td class="hex">75</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_wr_dqs_cfg @ 0XF8006160</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>75</b></td></tr></table>
-</li>
-<li><p>Register : phy_we_cfg @ 0XF8006168</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_fifo_we_slave_ratio</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">e4</td><td class="hex">e4</td></tr>
-<tr><td >reg_phy_fifo_we_in_force</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_fifo_we_in_delay</td><td class="hex">20:12</td><td class="hex">1ff000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_we_cfg @ 0XF8006168</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>e4</b></td></tr></table>
-</li>
-<li><p>Register : phy_we_cfg @ 0XF800616C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_fifo_we_slave_ratio</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">df</td><td class="hex">df</td></tr>
-<tr><td >reg_phy_fifo_we_in_force</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_fifo_we_in_delay</td><td class="hex">20:12</td><td class="hex">1ff000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_we_cfg @ 0XF800616C</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>df</b></td></tr></table>
-</li>
-<li><p>Register : phy_we_cfg @ 0XF8006170</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_fifo_we_slave_ratio</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">e0</td><td class="hex">e0</td></tr>
-<tr><td >reg_phy_fifo_we_in_force</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_fifo_we_in_delay</td><td class="hex">20:12</td><td class="hex">1ff000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_we_cfg @ 0XF8006170</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>e0</b></td></tr></table>
-</li>
-<li><p>Register : phy_we_cfg @ 0XF8006174</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_fifo_we_slave_ratio</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">e7</td><td class="hex">e7</td></tr>
-<tr><td >reg_phy_fifo_we_in_force</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_fifo_we_in_delay</td><td class="hex">20:12</td><td class="hex">1ff000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_we_cfg @ 0XF8006174</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>e7</b></td></tr></table>
-</li>
-<li><p>Register : wr_data_slv @ 0XF800617C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_data_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">b7</td><td class="hex">b7</td></tr>
-<tr><td >reg_phy_wr_data_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_data_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>wr_data_slv @ 0XF800617C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>b7</b></td></tr></table>
-</li>
-<li><p>Register : wr_data_slv @ 0XF8006180</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_data_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">bc</td><td class="hex">bc</td></tr>
-<tr><td >reg_phy_wr_data_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_data_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>wr_data_slv @ 0XF8006180</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>bc</b></td></tr></table>
-</li>
-<li><p>Register : wr_data_slv @ 0XF8006184</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_data_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">bc</td><td class="hex">bc</td></tr>
-<tr><td >reg_phy_wr_data_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_data_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>wr_data_slv @ 0XF8006184</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>bc</b></td></tr></table>
-</li>
-<li><p>Register : wr_data_slv @ 0XF8006188</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_data_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">b5</td><td class="hex">b5</td></tr>
-<tr><td >reg_phy_wr_data_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_data_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>wr_data_slv @ 0XF8006188</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>b5</b></td></tr></table>
-</li>
-<li><p>Register : reg_64 @ 0XF8006190</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_loopback</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bl2</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_at_spd_atpg</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_enable</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_force_err</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_mode</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_invert_clkout</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >reg_phy_all_dq_mpr_rd_resp</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_sel_logic</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_ctrl_slave_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">100</td><td class="hex">40000</td></tr>
-<tr><td >reg_phy_ctrl_slave_force</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_ctrl_slave_delay</td><td class="hex">27:21</td><td class="hex">fe00000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_use_rank0_delays</td><td class="hex">28:28</td><td class="hex">10000000</td><td class="hex">1</td><td class="hex">10000000</td></tr>
-<tr><td >reg_phy_lpddr</td><td class="hex">29:29</td><td class="hex">20000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_cmd_latency</td><td class="hex">30:30</td><td class="hex">40000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_int_lpbk</td><td class="hex">31:31</td><td class="hex">80000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>reg_64 @ 0XF8006190</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>10040080</b></td></tr></table>
-</li>
-<li><p>Register : reg_65 @ 0XF8006194</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_rl_delay</td><td class="hex">4:0</td><td class="hex">1f</td><td class="hex">2</td><td class="hex">2</td></tr>
-<tr><td >reg_phy_rd_rl_delay</td><td class="hex">9:5</td><td class="hex">3e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >reg_phy_dll_lock_diff</td><td class="hex">13:10</td><td class="hex">3c00</td><td class="hex">f</td><td class="hex">3c00</td></tr>
-<tr><td >reg_phy_use_wr_level</td><td class="hex">14:14</td><td class="hex">4000</td><td class="hex">1</td><td class="hex">4000</td></tr>
-<tr><td >reg_phy_use_rd_dqs_gate_level</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">1</td><td class="hex">8000</td></tr>
-<tr><td >reg_phy_use_rd_data_eye_level</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">1</td><td class="hex">10000</td></tr>
-<tr><td >reg_phy_dis_calib_rst</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_ctrl_slave_delay</td><td class="hex">19:18</td><td class="hex">c0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>reg_65 @ 0XF8006194</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>1fc82</b></td></tr></table>
-</li>
-<li><p>Register : page_mask @ 0XF8006204</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_page_addr_mask</td><td class="hex">31:0</td><td class="hex">ffffffff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>page_mask @ 0XF8006204</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_wr_port @ 0XF8006208</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_wr_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_wr_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_wr_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_wr_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_rmw_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td><b>axi_priority_wr_port @ 0XF8006208</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>803ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_wr_port @ 0XF800620C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_wr_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_wr_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_wr_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_wr_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_rmw_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td><b>axi_priority_wr_port @ 0XF800620C</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>803ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_wr_port @ 0XF8006210</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_wr_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_wr_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_wr_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_wr_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_rmw_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td><b>axi_priority_wr_port @ 0XF8006210</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>803ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_wr_port @ 0XF8006214</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_wr_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_wr_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_wr_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_wr_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_rmw_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td><b>axi_priority_wr_port @ 0XF8006214</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>803ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_rd_port @ 0XF8006218</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_rd_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_rd_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_rd_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_rd_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_set_hpr_rd_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_rd_port @ 0XF8006218</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_rd_port @ 0XF800621C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_rd_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_rd_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_rd_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_rd_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_set_hpr_rd_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_rd_port @ 0XF800621C</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_rd_port @ 0XF8006220</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_rd_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_rd_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_rd_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_rd_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_set_hpr_rd_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_rd_port @ 0XF8006220</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_rd_port @ 0XF8006224</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_rd_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_rd_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_rd_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_rd_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_set_hpr_rd_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_rd_port @ 0XF8006224</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : lpddr_ctrl0 @ 0XF80062A8</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_lpddr2</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_per_bank_refresh</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_derate_enable</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr4_margin</td><td class="hex">11:4</td><td class="hex">ff0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>lpddr_ctrl0 @ 0XF80062A8</td><td></td><td class="hex"><b>ff7</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : lpddr_ctrl1 @ 0XF80062AC</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_mr4_read_interval</td><td class="hex">31:0</td><td class="hex">ffffffff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>lpddr_ctrl1 @ 0XF80062AC</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : lpddr_ctrl2 @ 0XF80062B0</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_min_stable_clock_x1</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">5</td><td class="hex">5</td></tr>
-<tr><td >reg_ddrc_idle_after_reset_x32</td><td class="hex">11:4</td><td class="hex">ff0</td><td class="hex">12</td><td class="hex">120</td></tr>
-<tr><td >reg_ddrc_t_mrw</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">5</td><td class="hex">5000</td></tr>
-<tr><td><b>lpddr_ctrl2 @ 0XF80062B0</td><td></td><td class="hex"><b>3fffff</b></td><td></td><td class="hex"><b>5125</b></td></tr></table>
-</li>
-<li><p>Register : lpddr_ctrl3 @ 0XF80062B4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_max_auto_init_x1024</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">a6</td><td class="hex">a6</td></tr>
-<tr><td >reg_ddrc_dev_zqinit_x32</td><td class="hex">17:8</td><td class="hex">3ff00</td><td class="hex">12</td><td class="hex">1200</td></tr>
-<tr><td><b>lpddr_ctrl3 @ 0XF80062B4</td><td></td><td class="hex"><b>3ffff</b></td><td></td><td class="hex"><b>12a6</b></td></tr></table>
-</li>
-<h2>POLL ON DCI STATUS</h2>
-<ul>
-<p>POLL ON DCI STATUS</p>
-<li><p>Register : DDRIOB_DCI_STATUS @ 0XF8000B74</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DONE</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>DDRIOB_DCI_STATUS @ 0XF8000B74</td><td></td><td class="hex"><b>2000</b></td><td></td><td class="hex"><b>2000</b></td></tr></table>
-</li>
-</ul>
-<h2>UNLOCK DDR</h2>
-<ul>
-<p>UNLOCK DDR</p>
-<li><p>Register : ddrc_ctrl @ 0XF8006000</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_soft_rstb</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_ddrc_powerdown_en</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_data_bus_width</td><td class="hex">3:2</td><td class="hex">c</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_burst8_refresh</td><td class="hex">6:4</td><td class="hex">70</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rdwr_idle_gap</td><td class="hex">13:7</td><td class="hex">3f80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >reg_ddrc_dis_rd_bypass</td><td class="hex">14:14</td><td class="hex">4000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_act_bypass</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_auto_refresh</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ddrc_ctrl @ 0XF8006000</td><td></td><td class="hex"><b>1ffff</b></td><td></td><td class="hex"><b>81</b></td></tr></table>
-</li>
-</ul>
-<h2>CHECK DDR STATUS</h2>
-<ul>
-<p>CHECK DDR STATUS</p>
-<li><p>Register : mode_sts_reg @ 0XF8006054</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >ddrc_reg_operating_mode</td><td class="hex">2:0</td><td class="hex">7</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>mode_sts_reg @ 0XF8006054</td><td></td><td class="hex"><b>7</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_mio_init_data_1_0">ps7_mio_init_data_1_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>OCM REMAPPING</h2>
-<ul>
-<p>OCM REMAPPING</p>
-<li><p>Register : GPIOB_CTRL @ 0XF8000B00</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >VREF_EN</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >VREF_PULLUP_EN</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CLK_PULLUP_EN</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >SRSTN_PULLUP_EN</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>GPIOB_CTRL @ 0XF8000B00</td><td></td><td class="hex"><b>303</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>DDRIOB SETTINGS</h2>
-<ul>
-<p>DDRIOB SETTINGS</p>
-<li><p>Register : DDRIOB_ADDR0 @ 0XF8000B40</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_POWER</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCI_UPDATE</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCR_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_ADDR0 @ 0XF8000B40</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_ADDR1 @ 0XF8000B44</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_POWER</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCI_UPDATE</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCR_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_ADDR1 @ 0XF8000B44</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DATA0 @ 0XF8000B48</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_POWER</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >DCI_UPDATE</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >DCR_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DATA0 @ 0XF8000B48</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>672</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DATA1 @ 0XF8000B4C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_POWER</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >DCI_UPDATE</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >DCR_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DATA1 @ 0XF8000B4C</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>672</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DIFF0 @ 0XF8000B50</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_POWER</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">2</td><td class="hex">4</td></tr>
-<tr><td >DCI_UPDATE</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >DCR_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DIFF0 @ 0XF8000B50</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>674</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DIFF1 @ 0XF8000B54</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_POWER</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">2</td><td class="hex">4</td></tr>
-<tr><td >DCI_UPDATE</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >DCR_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DIFF1 @ 0XF8000B54</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>674</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_CLOCK @ 0XF8000B58</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_POWER</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCI_UPDATE</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCR_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_CLOCK @ 0XF8000B58</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DRIVE_SLEW_ADDR @ 0XF8000B5C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DRIVE_P</td><td class="hex">6:0</td><td class="hex">7f</td><td class="hex">1c</td><td class="hex">1c</td></tr>
-<tr><td >DRIVE_N</td><td class="hex">13:7</td><td class="hex">3f80</td><td class="hex">c</td><td class="hex">600</td></tr>
-<tr><td >SLEW_P</td><td class="hex">18:14</td><td class="hex">7c000</td><td class="hex">1a</td><td class="hex">68000</td></tr>
-<tr><td >SLEW_N</td><td class="hex">23:19</td><td class="hex">f80000</td><td class="hex">1a</td><td class="hex">d00000</td></tr>
-<tr><td >GTL</td><td class="hex">26:24</td><td class="hex">7000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RTERM</td><td class="hex">31:27</td><td class="hex">f8000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DRIVE_SLEW_ADDR @ 0XF8000B5C</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>d6861c</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DRIVE_SLEW_DATA @ 0XF8000B60</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DRIVE_P</td><td class="hex">6:0</td><td class="hex">7f</td><td class="hex">1c</td><td class="hex">1c</td></tr>
-<tr><td >DRIVE_N</td><td class="hex">13:7</td><td class="hex">3f80</td><td class="hex">c</td><td class="hex">600</td></tr>
-<tr><td >SLEW_P</td><td class="hex">18:14</td><td class="hex">7c000</td><td class="hex">6</td><td class="hex">18000</td></tr>
-<tr><td >SLEW_N</td><td class="hex">23:19</td><td class="hex">f80000</td><td class="hex">1f</td><td class="hex">f80000</td></tr>
-<tr><td >GTL</td><td class="hex">26:24</td><td class="hex">7000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RTERM</td><td class="hex">31:27</td><td class="hex">f8000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DRIVE_SLEW_DATA @ 0XF8000B60</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>f9861c</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DRIVE_SLEW_DIFF @ 0XF8000B64</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DRIVE_P</td><td class="hex">6:0</td><td class="hex">7f</td><td class="hex">1c</td><td class="hex">1c</td></tr>
-<tr><td >DRIVE_N</td><td class="hex">13:7</td><td class="hex">3f80</td><td class="hex">c</td><td class="hex">600</td></tr>
-<tr><td >SLEW_P</td><td class="hex">18:14</td><td class="hex">7c000</td><td class="hex">6</td><td class="hex">18000</td></tr>
-<tr><td >SLEW_N</td><td class="hex">23:19</td><td class="hex">f80000</td><td class="hex">1f</td><td class="hex">f80000</td></tr>
-<tr><td >GTL</td><td class="hex">26:24</td><td class="hex">7000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RTERM</td><td class="hex">31:27</td><td class="hex">f8000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DRIVE_SLEW_DIFF @ 0XF8000B64</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>f9861c</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DRIVE_SLEW_CLOCK @ 0XF8000B68</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DRIVE_P</td><td class="hex">6:0</td><td class="hex">7f</td><td class="hex">1c</td><td class="hex">1c</td></tr>
-<tr><td >DRIVE_N</td><td class="hex">13:7</td><td class="hex">3f80</td><td class="hex">c</td><td class="hex">600</td></tr>
-<tr><td >SLEW_P</td><td class="hex">18:14</td><td class="hex">7c000</td><td class="hex">1a</td><td class="hex">68000</td></tr>
-<tr><td >SLEW_N</td><td class="hex">23:19</td><td class="hex">f80000</td><td class="hex">1a</td><td class="hex">d00000</td></tr>
-<tr><td >GTL</td><td class="hex">26:24</td><td class="hex">7000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RTERM</td><td class="hex">31:27</td><td class="hex">f8000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DRIVE_SLEW_CLOCK @ 0XF8000B68</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>d6861c</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DDR_CTRL @ 0XF8000B6C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >VREF_INT_EN</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >VREF_SEL</td><td class="hex">4:1</td><td class="hex">1e</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >VREF_EXT_EN</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >VREF_PULLUP_EN</td><td class="hex">8:7</td><td class="hex">180</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >REFIO_EN</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >REFIO_PULLUP_EN</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DRST_B_PULLUP_EN</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CKE_PULLUP_EN</td><td class="hex">14:14</td><td class="hex">4000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DDR_CTRL @ 0XF8000B6C</td><td></td><td class="hex"><b>73ff</b></td><td></td><td class="hex"><b>260</b></td></tr></table>
-</li>
-<h2>ASSERT RESET</h2>
-<ul>
-<p>ASSERT RESET</p>
-<li><p>Register : DDRIOB_DCI_CTRL @ 0XF8000B70</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >VRN_OUT</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">1</td><td class="hex">20</td></tr>
-<tr><td><b>DDRIOB_DCI_CTRL @ 0XF8000B70</td><td></td><td class="hex"><b>21</b></td><td></td><td class="hex"><b>21</b></td></tr></table>
-</li>
-</ul>
-<h2>DEASSERT RESET</h2>
-<ul>
-<p>DEASSERT RESET</p>
-<li><p>Register : DDRIOB_DCI_CTRL @ 0XF8000B70</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >VRN_OUT</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">1</td><td class="hex">20</td></tr>
-<tr><td><b>DDRIOB_DCI_CTRL @ 0XF8000B70</td><td></td><td class="hex"><b>21</b></td><td></td><td class="hex"><b>20</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : DDRIOB_DCI_CTRL @ 0XF8000B70</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >ENABLE</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >VRP_TRI</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >VRN_TRI</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >VRP_OUT</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >VRN_OUT</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">1</td><td class="hex">20</td></tr>
-<tr><td >NREF_OPT1</td><td class="hex">7:6</td><td class="hex">c0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >NREF_OPT2</td><td class="hex">10:8</td><td class="hex">700</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >NREF_OPT4</td><td class="hex">13:11</td><td class="hex">3800</td><td class="hex">1</td><td class="hex">800</td></tr>
-<tr><td >PREF_OPT1</td><td class="hex">16:14</td><td class="hex">1c000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >PREF_OPT2</td><td class="hex">19:17</td><td class="hex">e0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >UPDATE_CONTROL</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INIT_COMPLETE</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TST_CLK</td><td class="hex">22:22</td><td class="hex">400000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TST_HLN</td><td class="hex">23:23</td><td class="hex">800000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TST_HLP</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TST_RST</td><td class="hex">25:25</td><td class="hex">2000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INT_DCI_EN</td><td class="hex">26:26</td><td class="hex">4000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DCI_CTRL @ 0XF8000B70</td><td></td><td class="hex"><b>7ffffff</b></td><td></td><td class="hex"><b>823</b></td></tr></table>
-</li>
-</ul>
-<h2>MIO PROGRAMMING</h2>
-<ul>
-<p>MIO PROGRAMMING</p>
-<li><p>Register : MIO_PIN_00 @ 0XF8000700</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_00 @ 0XF8000700</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_01 @ 0XF8000704</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_01 @ 0XF8000704</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_02 @ 0XF8000708</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_02 @ 0XF8000708</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_03 @ 0XF800070C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_03 @ 0XF800070C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_04 @ 0XF8000710</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_04 @ 0XF8000710</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_05 @ 0XF8000714</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_05 @ 0XF8000714</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_06 @ 0XF8000718</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_06 @ 0XF8000718</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_07 @ 0XF800071C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_07 @ 0XF800071C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_08 @ 0XF8000720</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_08 @ 0XF8000720</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_09 @ 0XF8000724</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_09 @ 0XF8000724</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_10 @ 0XF8000728</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">2</td><td class="hex">40</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_10 @ 0XF8000728</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>1640</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_11 @ 0XF800072C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">2</td><td class="hex">40</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_11 @ 0XF800072C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>1640</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_12 @ 0XF8000730</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">2</td><td class="hex">40</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_12 @ 0XF8000730</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>1640</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_13 @ 0XF8000734</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">2</td><td class="hex">40</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_13 @ 0XF8000734</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>1640</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_14 @ 0XF8000738</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_14 @ 0XF8000738</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_15 @ 0XF800073C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_15 @ 0XF800073C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_16 @ 0XF8000740</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_16 @ 0XF8000740</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_17 @ 0XF8000744</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_17 @ 0XF8000744</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_18 @ 0XF8000748</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_18 @ 0XF8000748</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_19 @ 0XF800074C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_19 @ 0XF800074C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_20 @ 0XF8000750</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_20 @ 0XF8000750</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_21 @ 0XF8000754</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_21 @ 0XF8000754</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_22 @ 0XF8000758</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_22 @ 0XF8000758</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_23 @ 0XF800075C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_23 @ 0XF800075C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_24 @ 0XF8000760</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_24 @ 0XF8000760</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_25 @ 0XF8000764</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_25 @ 0XF8000764</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_26 @ 0XF8000768</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_26 @ 0XF8000768</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_27 @ 0XF800076C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_27 @ 0XF800076C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_28 @ 0XF8000770</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_28 @ 0XF8000770</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_29 @ 0XF8000774</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_29 @ 0XF8000774</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>305</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_30 @ 0XF8000778</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_30 @ 0XF8000778</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_31 @ 0XF800077C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_31 @ 0XF800077C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>305</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_32 @ 0XF8000780</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_32 @ 0XF8000780</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_33 @ 0XF8000784</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_33 @ 0XF8000784</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_34 @ 0XF8000788</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_34 @ 0XF8000788</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_35 @ 0XF800078C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_35 @ 0XF800078C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_36 @ 0XF8000790</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_36 @ 0XF8000790</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>305</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_37 @ 0XF8000794</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_37 @ 0XF8000794</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_38 @ 0XF8000798</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_38 @ 0XF8000798</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_39 @ 0XF800079C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_39 @ 0XF800079C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_40 @ 0XF80007A0</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_40 @ 0XF80007A0</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_41 @ 0XF80007A4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_41 @ 0XF80007A4</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_42 @ 0XF80007A8</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_42 @ 0XF80007A8</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_43 @ 0XF80007AC</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_43 @ 0XF80007AC</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_44 @ 0XF80007B0</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_44 @ 0XF80007B0</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_45 @ 0XF80007B4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_45 @ 0XF80007B4</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_46 @ 0XF80007B8</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_46 @ 0XF80007B8</td><td></td><td class="hex"><b>3f01</b></td><td></td><td class="hex"><b>200</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_47 @ 0XF80007BC</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_47 @ 0XF80007BC</td><td></td><td class="hex"><b>3f01</b></td><td></td><td class="hex"><b>201</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_48 @ 0XF80007C0</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">7</td><td class="hex">e0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_48 @ 0XF80007C0</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2e0</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_49 @ 0XF80007C4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">7</td><td class="hex">e0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_49 @ 0XF80007C4</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2e1</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_50 @ 0XF80007C8</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_50 @ 0XF80007C8</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>201</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_51 @ 0XF80007CC</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_51 @ 0XF80007CC</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>201</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_52 @ 0XF80007D0</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_52 @ 0XF80007D0</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>280</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_53 @ 0XF80007D4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_53 @ 0XF80007D4</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>280</b></td></tr></table>
-</li>
-<li><p>Register : SD0_WP_CD_SEL @ 0XF8000830</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SDIO0_CD_SEL</td><td class="hex">21:16</td><td class="hex">3f0000</td><td class="hex">2f</td><td class="hex">2f0000</td></tr>
-<tr><td><b>SD0_WP_CD_SEL @ 0XF8000830</td><td></td><td class="hex"><b>3f0000</b></td><td></td><td class="hex"><b>2f0000</b></td></tr></table>
-</li>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_peripherals_init_data_1_0">ps7_peripherals_init_data_1_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>DDR TERM/IBUF_DISABLE_MODE SETTINGS</h2>
-<ul>
-<p>DDR TERM/IBUF_DISABLE_MODE SETTINGS</p>
-<li><p>Register : DDRIOB_DATA0 @ 0XF8000B48</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td><b>DDRIOB_DATA0 @ 0XF8000B48</td><td></td><td class="hex"><b>180</b></td><td></td><td class="hex"><b>180</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DATA1 @ 0XF8000B4C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td><b>DDRIOB_DATA1 @ 0XF8000B4C</td><td></td><td class="hex"><b>180</b></td><td></td><td class="hex"><b>180</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DIFF0 @ 0XF8000B50</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td><b>DDRIOB_DIFF0 @ 0XF8000B50</td><td></td><td class="hex"><b>180</b></td><td></td><td class="hex"><b>180</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DIFF1 @ 0XF8000B54</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td><b>DDRIOB_DIFF1 @ 0XF8000B54</td><td></td><td class="hex"><b>180</b></td><td></td><td class="hex"><b>180</b></td></tr></table>
-</li>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-<h2>SRAM/NOR SET OPMODE</h2>
-<ul>
-<p>SRAM/NOR SET OPMODE</p>
-</ul>
-<h2>UART REGISTERS</h2>
-<ul>
-<p>UART REGISTERS</p>
-<li><p>Register : Baud_rate_divider_reg0 @ 0XE0001034</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >BDIV</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">6</td><td class="hex">6</td></tr>
-<tr><td><b>Baud_rate_divider_reg0 @ 0XE0001034</td><td></td><td class="hex"><b>ff</b></td><td></td><td class="hex"><b>6</b></td></tr></table>
-</li>
-<li><p>Register : Baud_rate_gen_reg0 @ 0XE0001018</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CD</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">3e</td><td class="hex">3e</td></tr>
-<tr><td><b>Baud_rate_gen_reg0 @ 0XE0001018</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>3e</b></td></tr></table>
-</li>
-<li><p>Register : Control_reg0 @ 0XE0001000</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >STPBRK</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >STTBRK</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RSTTO</td><td class="hex">6:6</td><td class="hex">40</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TXDIS</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TXEN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >RXDIS</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RXEN</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >TXRES</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >RXRES</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>Control_reg0 @ 0XE0001000</td><td></td><td class="hex"><b>1ff</b></td><td></td><td class="hex"><b>17</b></td></tr></table>
-</li>
-<li><p>Register : mode_reg0 @ 0XE0001004</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IRMODE</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >UCLKEN</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CHMODE</td><td class="hex">9:8</td><td class="hex">300</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >NBSTOP</td><td class="hex">7:6</td><td class="hex">c0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >PAR</td><td class="hex">5:3</td><td class="hex">38</td><td class="hex">4</td><td class="hex">20</td></tr>
-<tr><td >CHRL</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CLKS</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>mode_reg0 @ 0XE0001004</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>20</b></td></tr></table>
-</li>
-<li><p>Register : Baud_rate_divider_reg0 @ 0XE0000034</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >BDIV</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">6</td><td class="hex">6</td></tr>
-<tr><td><b>Baud_rate_divider_reg0 @ 0XE0000034</td><td></td><td class="hex"><b>ff</b></td><td></td><td class="hex"><b>6</b></td></tr></table>
-</li>
-<li><p>Register : Baud_rate_gen_reg0 @ 0XE0000018</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CD</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">3e</td><td class="hex">3e</td></tr>
-<tr><td><b>Baud_rate_gen_reg0 @ 0XE0000018</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>3e</b></td></tr></table>
-</li>
-<li><p>Register : Control_reg0 @ 0XE0000000</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >STPBRK</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >STTBRK</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RSTTO</td><td class="hex">6:6</td><td class="hex">40</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TXDIS</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TXEN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >RXDIS</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RXEN</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >TXRES</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >RXRES</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>Control_reg0 @ 0XE0000000</td><td></td><td class="hex"><b>1ff</b></td><td></td><td class="hex"><b>17</b></td></tr></table>
-</li>
-<li><p>Register : mode_reg0 @ 0XE0000004</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IRMODE</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >UCLKEN</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CHMODE</td><td class="hex">9:8</td><td class="hex">300</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >NBSTOP</td><td class="hex">7:6</td><td class="hex">c0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >PAR</td><td class="hex">5:3</td><td class="hex">38</td><td class="hex">4</td><td class="hex">20</td></tr>
-<tr><td >CHRL</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CLKS</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>mode_reg0 @ 0XE0000004</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>20</b></td></tr></table>
-</li>
-</ul>
-<h2>PL POWER ON RESET REGISTERS</h2>
-<ul>
-<p>PL POWER ON RESET REGISTERS</p>
-<li><p>Register : CTRL @ 0XF8007000</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PCFG_POR_CNT_4K</td><td class="hex">29:29</td><td class="hex">20000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CTRL @ 0XF8007000</td><td></td><td class="hex"><b>20000000</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>SMC TIMING CALCULATION REGISTER UPDATE</h2>
-<ul>
-<p>SMC TIMING CALCULATION REGISTER UPDATE</p>
-<h2>NAND SET CYCLE</h2>
-<ul>
-<p>NAND SET CYCLE</p>
-</ul>
-<h2>OPMODE</h2>
-<ul>
-<p>OPMODE</p>
-</ul>
-<h2>DIRECT COMMAND</h2>
-<ul>
-<p>DIRECT COMMAND</p>
-</ul>
-<h2>SRAM/NOR CS0 SET CYCLE</h2>
-<ul>
-<p>SRAM/NOR CS0 SET CYCLE</p>
-</ul>
-<h2>DIRECT COMMAND</h2>
-<ul>
-<p>DIRECT COMMAND</p>
-</ul>
-<h2>NOR CS0 BASE ADDRESS</h2>
-<ul>
-<p>NOR CS0 BASE ADDRESS</p>
-</ul>
-<h2>SRAM/NOR CS1 SET CYCLE</h2>
-<ul>
-<p>SRAM/NOR CS1 SET CYCLE</p>
-</ul>
-<h2>DIRECT COMMAND</h2>
-<ul>
-<p>DIRECT COMMAND</p>
-</ul>
-<h2>NOR CS1 BASE ADDRESS</h2>
-<ul>
-<p>NOR CS1 BASE ADDRESS</p>
-</ul>
-<h2>USB RESET</h2>
-<ul>
-<p>USB RESET</p>
-<h2>DIR MODE BANK 0</h2>
-<ul>
-<p>DIR MODE BANK 0</p>
-</ul>
-<h2>DIR MODE BANK 1</h2>
-<ul>
-<p>DIR MODE BANK 1</p>
-<li><p>Register : DIRM_1 @ 0XE000A244</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DIRECTION_1</td><td class="hex">21:0</td><td class="hex">3fffff</td><td class="hex">4000</td><td class="hex">4000</td></tr>
-<tr><td><b>DIRM_1 @ 0XE000A244</td><td></td><td class="hex"><b>3fffff</b></td><td></td><td class="hex"><b>4000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-<li><p>Register : MASK_DATA_1_LSW @ 0XE000A008</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >MASK_1_LSW</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">bfff</td><td class="hex">bfff0000</td></tr>
-<tr><td >DATA_1_LSW</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">4000</td><td class="hex">4000</td></tr>
-<tr><td><b>MASK_DATA_1_LSW @ 0XE000A008</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>bfff4000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-<h2>OUTPUT ENABLE BANK 0</h2>
-<ul>
-<p>OUTPUT ENABLE BANK 0</p>
-</ul>
-<h2>OUTPUT ENABLE BANK 1</h2>
-<ul>
-<p>OUTPUT ENABLE BANK 1</p>
-<li><p>Register : OEN_1 @ 0XE000A248</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >OP_ENABLE_1</td><td class="hex">21:0</td><td class="hex">3fffff</td><td class="hex">4000</td><td class="hex">4000</td></tr>
-<tr><td><b>OEN_1 @ 0XE000A248</td><td></td><td class="hex"><b>3fffff</b></td><td></td><td class="hex"><b>4000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_0_LSW LOW BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW LOW BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW LOW BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW LOW BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW LOW BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW LOW BANK [47:32]</p>
-<li><p>Register : MASK_DATA_1_LSW @ 0XE000A008</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >MASK_1_LSW</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">bfff</td><td class="hex">bfff0000</td></tr>
-<tr><td >DATA_1_LSW</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MASK_DATA_1_LSW @ 0XE000A008</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>bfff0000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_1_MSW LOW BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW LOW BANK [53:48]</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-<li><p>Register : MASK_DATA_1_LSW @ 0XE000A008</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >MASK_1_LSW</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">bfff</td><td class="hex">bfff0000</td></tr>
-<tr><td >DATA_1_LSW</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">4000</td><td class="hex">4000</td></tr>
-<tr><td><b>MASK_DATA_1_LSW @ 0XE000A008</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>bfff4000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-</ul>
-<h2>ENET RESET</h2>
-<ul>
-<p>ENET RESET</p>
-<h2>DIR MODE BANK 0</h2>
-<ul>
-<p>DIR MODE BANK 0</p>
-</ul>
-<h2>DIR MODE BANK 1</h2>
-<ul>
-<p>DIR MODE BANK 1</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-<h2>OUTPUT ENABLE BANK 0</h2>
-<ul>
-<p>OUTPUT ENABLE BANK 0</p>
-</ul>
-<h2>OUTPUT ENABLE BANK 1</h2>
-<ul>
-<p>OUTPUT ENABLE BANK 1</p>
-</ul>
-<h2>MASK_DATA_0_LSW LOW BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW LOW BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW LOW BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW LOW BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW LOW BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW LOW BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW LOW BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW LOW BANK [53:48]</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-</ul>
-<h2>I2C RESET</h2>
-<ul>
-<p>I2C RESET</p>
-<h2>DIR MODE GPIO BANK0</h2>
-<ul>
-<p>DIR MODE GPIO BANK0</p>
-</ul>
-<h2>DIR MODE GPIO BANK1</h2>
-<ul>
-<p>DIR MODE GPIO BANK1</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-<h2>OUTPUT ENABLE</h2>
-<ul>
-<p>OUTPUT ENABLE</p>
-</ul>
-<h2>OUTPUT ENABLE</h2>
-<ul>
-<p>OUTPUT ENABLE</p>
-</ul>
-<h2>MASK_DATA_0_LSW LOW BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW LOW BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW LOW BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW LOW BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW LOW BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW LOW BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW LOW BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW LOW BANK [53:48]</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-</ul>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_post_config_1_0">ps7_post_config_1_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>ENABLING LEVEL SHIFTER</h2>
-<ul>
-<p>ENABLING LEVEL SHIFTER</p>
-<li><p>Register : LVL_SHFTR_EN @ 0XF8000900</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >USER_INP_ICT_EN_0</td><td class="hex">1:0</td><td class="hex">3</td><td class="hex">3</td><td class="hex">3</td></tr>
-<tr><td >USER_INP_ICT_EN_1</td><td class="hex">3:2</td><td class="hex">c</td><td class="hex">3</td><td class="hex">c</td></tr>
-<tr><td><b>LVL_SHFTR_EN @ 0XF8000900</td><td></td><td class="hex"><b>f</b></td><td></td><td class="hex"><b>f</b></td></tr></table>
-</li>
-</ul>
-<h2>FPGA RESETS TO 1</h2>
-<ul>
-<p>FPGA RESETS TO 1</p>
-<li><p>Register : FPGA_RST_CTRL @ 0XF8000240</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reserved_3</td><td class="hex">31:25</td><td class="hex">fe000000</td><td class="hex">7f</td><td class="hex">fe000000</td></tr>
-<tr><td >FPGA_ACP_RST</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">1</td><td class="hex">1000000</td></tr>
-<tr><td >FPGA_AXDS3_RST</td><td class="hex">23:23</td><td class="hex">800000</td><td class="hex">1</td><td class="hex">800000</td></tr>
-<tr><td >FPGA_AXDS2_RST</td><td class="hex">22:22</td><td class="hex">400000</td><td class="hex">1</td><td class="hex">400000</td></tr>
-<tr><td >FPGA_AXDS1_RST</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">1</td><td class="hex">200000</td></tr>
-<tr><td >FPGA_AXDS0_RST</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td >reserved_2</td><td class="hex">19:18</td><td class="hex">c0000</td><td class="hex">3</td><td class="hex">c0000</td></tr>
-<tr><td >FSSW1_FPGA_RST</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">1</td><td class="hex">20000</td></tr>
-<tr><td >FSSW0_FPGA_RST</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">1</td><td class="hex">10000</td></tr>
-<tr><td >reserved_1</td><td class="hex">15:14</td><td class="hex">c000</td><td class="hex">3</td><td class="hex">c000</td></tr>
-<tr><td >FPGA_FMSW1_RST</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td >FPGA_FMSW0_RST</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >FPGA_DMA3_RST</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">1</td><td class="hex">800</td></tr>
-<tr><td >FPGA_DMA2_RST</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">1</td><td class="hex">400</td></tr>
-<tr><td >FPGA_DMA1_RST</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >FPGA_DMA0_RST</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >reserved</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">f</td><td class="hex">f0</td></tr>
-<tr><td >FPGA3_OUT_RST</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">1</td><td class="hex">8</td></tr>
-<tr><td >FPGA2_OUT_RST</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >FPGA1_OUT_RST</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >FPGA0_OUT_RST</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>FPGA_RST_CTRL @ 0XF8000240</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>ffffffff</b></td></tr></table>
-</li>
-</ul>
-<h2>FPGA RESETS TO 0</h2>
-<ul>
-<p>FPGA RESETS TO 0</p>
-<li><p>Register : FPGA_RST_CTRL @ 0XF8000240</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reserved_3</td><td class="hex">31:25</td><td class="hex">fe000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_ACP_RST</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_AXDS3_RST</td><td class="hex">23:23</td><td class="hex">800000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_AXDS2_RST</td><td class="hex">22:22</td><td class="hex">400000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_AXDS1_RST</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_AXDS0_RST</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_2</td><td class="hex">19:18</td><td class="hex">c0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FSSW1_FPGA_RST</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FSSW0_FPGA_RST</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_1</td><td class="hex">15:14</td><td class="hex">c000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_FMSW1_RST</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_FMSW0_RST</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_DMA3_RST</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_DMA2_RST</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_DMA1_RST</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_DMA0_RST</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA3_OUT_RST</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA2_OUT_RST</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA1_OUT_RST</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA0_OUT_RST</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>FPGA_RST_CTRL @ 0XF8000240</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>AFI REGISTERS</h2>
-<ul>
-<p>AFI REGISTERS</p>
-<h2>AFI0 REGISTERS</h2>
-<ul>
-<p>AFI0 REGISTERS</p>
-</ul>
-<h2>AFI1 REGISTERS</h2>
-<ul>
-<p>AFI1 REGISTERS</p>
-</ul>
-<h2>AFI2 REGISTERS</h2>
-<ul>
-<p>AFI2 REGISTERS</p>
-</ul>
-<h2>AFI3 REGISTERS</h2>
-<ul>
-<p>AFI3 REGISTERS</p>
-</ul>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-</ul>
-<hr/>
-</body>
-</html>
-<!DOCTYPE html>
-<html lang="en">
-<head>
-<meta http-equiv="content-type" content="text/html;charset=UTF-8"/>
-<title>Zynq PS configuration detail</title>
-<style type="text/css">
-.hex {font-family:monospace ; text-align : right}
-td { min-width : 80px ; } 
-</style>
-</head>
-<body>
-<p style="height: 7px">Following peripherals are selected in the design. </p>
-<p><br /></p>
-<h2><a name="Top">Peripheral Selected</a></h2>
-<ul>
-<li>Quad SPI Flash</li>
-<li>Enet 0</li>
-<li>USB 0</li>
-<li>SD 0</li>
-<li>UART 0</li>
-<li>UART 1</li>
-<li>I2C 0</li>
-<li>I2C 1</li>
-<li>GPIO</li>
-</ul>
-<p>To see detailed information please follow below links:</p>
-<ul>
-<li><a href="#MIOConfTab">MIO Configuration Table</a></li>
-<li><a href="#ZynqPerTab">Zynq Peripheral Configuration</a></li>
-<li><a href="#DDRInfoTab">DDR Configuration Information</a></li>
-<li>SLCR settings</li>
-<ul>
-<li><a href="#ps7_pll_init_data">PLL Init Data</a></li>
-<li><a href="#ps7_clock_init_data">Clock Init Data</a></li>
-<li><a href="#ps7_ddr_init_data">DDR Init Data</a></li>
-<li><a href="#ps7_mio_init_data">MIO Init Data</a></li>
-</ul>
-</ul>
-<h2><a name="MIOConfTab">MIO configuration Table</a></h2>
-<ul><table border="1"> 
-<thead><tr>                <th>MIO Pin</th>                <th>Peripheral</th>             <th>Signal</th>               <th>IO type</th>              <th>Speed</th>              <th>Pullup</th>              <th>Direction</th>              </tr></thead>
-<tr bgcolor="#FA4A46"><td><a name="MIO 0">MIO 0</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[0]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 1">MIO 1</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_ss_b</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 2">MIO 2</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_io[0]</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 3">MIO 3</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_io[1]</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 4">MIO 4</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_io[2]</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 5">MIO 5</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_io[3]</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 6">MIO 6</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_sclk</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 7">MIO 7</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[7]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 8">MIO 8</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi_fbclk</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 9">MIO 9</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[9]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="MIO 10">MIO 10</a></td><td><a href="#I2C 0">I2C 0</a></td><td>scl</td><td>LVCMOS 3.3V</td><td>slow</td><td>enabled</td><td>inout</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="MIO 11">MIO 11</a></td><td><a href="#I2C 0">I2C 0</a></td><td>sda</td><td>LVCMOS 3.3V</td><td>slow</td><td>enabled</td><td>inout</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="MIO 12">MIO 12</a></td><td><a href="#I2C 1">I2C 1</a></td><td>scl</td><td>LVCMOS 3.3V</td><td>slow</td><td>enabled</td><td>inout</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="MIO 13">MIO 13</a></td><td><a href="#I2C 1">I2C 1</a></td><td>sda</td><td>LVCMOS 3.3V</td><td>slow</td><td>enabled</td><td>inout</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 14">MIO 14</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[14]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 15">MIO 15</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[15]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 16">MIO 16</a></td><td><a href="#Enet 0">Enet 0</a></td><td>tx_clk</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 17">MIO 17</a></td><td><a href="#Enet 0">Enet 0</a></td><td>txd[0]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 18">MIO 18</a></td><td><a href="#Enet 0">Enet 0</a></td><td>txd[1]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 19">MIO 19</a></td><td><a href="#Enet 0">Enet 0</a></td><td>txd[2]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 20">MIO 20</a></td><td><a href="#Enet 0">Enet 0</a></td><td>txd[3]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 21">MIO 21</a></td><td><a href="#Enet 0">Enet 0</a></td><td>tx_ctl</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 22">MIO 22</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rx_clk</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 23">MIO 23</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rxd[0]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 24">MIO 24</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rxd[1]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 25">MIO 25</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rxd[2]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 26">MIO 26</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rxd[3]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 27">MIO 27</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rx_ctl</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 28">MIO 28</a></td><td><a href="#USB 0">USB 0</a></td><td>data[4]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 29">MIO 29</a></td><td><a href="#USB 0">USB 0</a></td><td>dir</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 30">MIO 30</a></td><td><a href="#USB 0">USB 0</a></td><td>stp</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 31">MIO 31</a></td><td><a href="#USB 0">USB 0</a></td><td>nxt</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 32">MIO 32</a></td><td><a href="#USB 0">USB 0</a></td><td>data[0]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 33">MIO 33</a></td><td><a href="#USB 0">USB 0</a></td><td>data[1]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 34">MIO 34</a></td><td><a href="#USB 0">USB 0</a></td><td>data[2]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 35">MIO 35</a></td><td><a href="#USB 0">USB 0</a></td><td>data[3]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 36">MIO 36</a></td><td><a href="#USB 0">USB 0</a></td><td>clk</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 37">MIO 37</a></td><td><a href="#USB 0">USB 0</a></td><td>data[5]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 38">MIO 38</a></td><td><a href="#USB 0">USB 0</a></td><td>data[6]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 39">MIO 39</a></td><td><a href="#USB 0">USB 0</a></td><td>data[7]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 40">MIO 40</a></td><td><a href="#SD 0">SD 0</a></td><td>clk</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 41">MIO 41</a></td><td><a href="#SD 0">SD 0</a></td><td>cmd</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 42">MIO 42</a></td><td><a href="#SD 0">SD 0</a></td><td>data[0]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 43">MIO 43</a></td><td><a href="#SD 0">SD 0</a></td><td>data[1]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 44">MIO 44</a></td><td><a href="#SD 0">SD 0</a></td><td>data[2]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 45">MIO 45</a></td><td><a href="#SD 0">SD 0</a></td><td>data[3]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 46">MIO 46</a></td><td><a href="#USB 0">USB 0</a></td><td>reset</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 47">MIO 47</a></td><td><a href="#SD 0">SD 0</a></td><td>cd</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#6495ED"><td><a name="MIO 48">MIO 48</a></td><td><a href="#UART 1">UART 1</a></td><td>tx</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#6495ED"><td><a name="MIO 49">MIO 49</a></td><td><a href="#UART 1">UART 1</a></td><td>rx</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 50">MIO 50</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[50]</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 51">MIO 51</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[51]</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 52">MIO 52</a></td><td><a href="#Enet 0">Enet 0</a></td><td>mdc</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 53">MIO 53</a></td><td><a href="#Enet 0">Enet 0</a></td><td>mdio</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-</table></ul>
-<li><a href="#Top">Go To TOP</a></li>
-<h2><a name="ZynqPerTab">Zynq Peripheral Configuration</a></h2>
-<ul><table border="1"> 
-<tr><thead>             <th>Peripheral</th>                <th>Signal Group</th>             <th>Signal</th>               <th>MIO</th>              </thead></tr>
-<tr bgcolor="#FAEBD7"><td><a name="Quad SPI Flash" >Quad SPI Flash</a></td>             <td></td><td></td><td>MIO 1 .. 6</td></tr>
-<tr bgcolor="#FAEBD7"><td></td><td>Dual Quad SPI (4 bit) </td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FAEBD7"><td></td><td>Dual Quad SPI (Parallel 8 bit)</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FAEBD7"><td></td><td>Feedback Clk</td><td></td><td>MIO 8</td></tr>
-<tr bgcolor="#FFFFFF"><td><a name="nor" >SRAM/NOR Flash</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FFE4C4"><td><a name="nand" >NAND Flash</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#DEB887"><td><a name="Enet 0" >Enet 0</a></td>             <td></td><td></td><td>MIO 16 .. 27</td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>tx_clk</td><td><a href="#MIO 16">MIO 16</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>txd[3]</td><td><a href="#MIO 20">MIO 20</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>txd[2]</td><td><a href="#MIO 19">MIO 19</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>txd[1]</td><td><a href="#MIO 18">MIO 18</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>txd[0]</td><td><a href="#MIO 17">MIO 17</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>tx_ctl</td><td><a href="#MIO 21">MIO 21</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rx_clk</td><td><a href="#MIO 22">MIO 22</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rxd[3]</td><td><a href="#MIO 26">MIO 26</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rxd[2]</td><td><a href="#MIO 25">MIO 25</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rxd[1]</td><td><a href="#MIO 24">MIO 24</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rxd[0]</td><td><a href="#MIO 23">MIO 23</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rx_ctl</td><td><a href="#MIO 27">MIO 27</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td>MDIO</td><td></td><td>MIO 52 .. 53</td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>mdc</td><td><a href="#MIO 52">MIO 52</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>mdio</td><td><a href="#MIO 53">MIO 53</a></td></tr>
-<tr bgcolor="#DEB887"><td><a name="enet1" >Enet 1</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="USB 0" >USB 0</a></td>             <td></td><td></td><td>MIO 28 .. 39</td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>clk</td><td><a href="#MIO 36">MIO 36</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>dir</td><td><a href="#MIO 29">MIO 29</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>stp</td><td><a href="#MIO 30">MIO 30</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>nxt</td><td><a href="#MIO 31">MIO 31</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[0]</td><td><a href="#MIO 32">MIO 32</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[1]</td><td><a href="#MIO 33">MIO 33</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[2]</td><td><a href="#MIO 34">MIO 34</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[3]</td><td><a href="#MIO 35">MIO 35</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[4]</td><td><a href="#MIO 28">MIO 28</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[5]</td><td><a href="#MIO 37">MIO 37</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[6]</td><td><a href="#MIO 38">MIO 38</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[7]</td><td><a href="#MIO 39">MIO 39</a></td></tr>
-<tr bgcolor="#7FFF00"><td><a name="usb1" >USB 1</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#D2691E"><td><a name="SD 0" >SD 0</a></td>             <td></td><td></td><td>MIO 40 .. 45</td></tr>
-<tr bgcolor="#D2691E"><td></td><td>CD</td><td></td><td>MIO 47</td></tr>
-<tr bgcolor="#D2691E"><td></td><td>WP</td><td></td><td>EMIO</td></tr>
-<tr bgcolor="#D2691E"><td></td><td>Power</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#D2691E"><td><a name="sd1" >SD 1</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#6495ED"><td><a name="UART 0" >UART 0</a></td>             <td></td><td></td><td>EMIO</td></tr>
-<tr bgcolor="#6495ED"><td></td><td></td><td>rx</td><td>EMIO</td></tr>
-<tr bgcolor="#6495ED"><td></td><td></td><td>tx</td><td>EMIO</td></tr>
-<tr bgcolor="#6495ED"><td></td><td>Modem signals</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#6495ED"><td><a name="UART 1" >UART 1</a></td>             <td></td><td></td><td>MIO 48 .. 49</td></tr>
-<tr bgcolor="#6495ED"><td></td><td></td><td>rx</td><td><a href="#MIO 49">MIO 49</a></td></tr>
-<tr bgcolor="#6495ED"><td></td><td></td><td>tx</td><td><a href="#MIO 48">MIO 48</a></td></tr>
-<tr bgcolor="#6495ED"><td></td><td>Modem Signals</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="I2C 0" >I2C 0</a></td>             <td></td><td></td><td>MIO 10 .. 11</td></tr>
-<tr bgcolor="#BDB76B"><td></td><td></td><td>scl</td><td><a href="#MIO 10">MIO 10</a></td></tr>
-<tr bgcolor="#BDB76B"><td></td><td></td><td>sda</td><td><a href="#MIO 11">MIO 11</a></td></tr>
-<tr bgcolor="#BDB76B"><td></td><td>Interrupt</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="I2C 1" >I2C 1</a></td>             <td></td><td></td><td>MIO 12 .. 13</td></tr>
-<tr bgcolor="#BDB76B"><td></td><td></td><td>scl</td><td><a href="#MIO 12">MIO 12</a></td></tr>
-<tr bgcolor="#BDB76B"><td></td><td></td><td>sda</td><td><a href="#MIO 13">MIO 13</a></td></tr>
-<tr bgcolor="#BDB76B"><td></td><td>Interrupt</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#8DBC8F"><td><a name="spi0" >SPI 0</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#8DBC8F"><td><a name="spi1" >SPI 1</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#DAA520"><td><a name="can0" >CAN 0</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#DAA520"><td><a name="can1" >CAN 1</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#ADD8E6"><td><a name="trace" >Trace</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#BC8F8F"><td><a name="ttc0" >Timer 0</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#BC8F8F"><td><a name="ttc1" >Timer 1</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FF6347"><td><a name="wdt" >Watchdog</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#EE82EE"><td><a name="pjtag" >PJTAG</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="GPIO" >GPIO</a></td>             <td></td><td></td><td>MIO</td></tr>
-<tr bgcolor="#FFFFFF"><td><a name="mode" >Mode</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FFFFFF"><td><a name="vcfg" >VCfg</a></td>             <td></td><td></td><td>Disabled</td></tr>
-</table></ul>
-<li><a href="#Top">Go To TOP</a></li>
-<h2><a name="DDRInfoTab">DDR Memory information</a></h2>
-<h3><a name="DDRInfoTab">DDR Controller Configuration</a></h3>
-<ul><table border="1"> 
-<tr><thead>                 <th>Parameter</th>                    <th>Value</th>                 </thead></tr>
-<tr> <td><a name="Enable DDR">Enable DDR</a></td><td>1</td></tr>
-<tr> <td><a name="Memory Type">Memory Type</a></td><td>DDR 3</td></tr>
-<tr> <td><a name="Memory Part">Memory Part</a></td><td>MT41K128M16 JT-125</td></tr>
-<tr> <td><a name="DRAM bus width">DRAM bus width</a></td><td>32 Bit</td></tr>
-<tr> <td><a name="ECC">ECC</a></td><td>Disabled</td></tr>
-<tr> <td><a name="BURST Length (lppdr only)">BURST Length (lppdr only)</a></td><td>8</td></tr>
-<tr> <td><a name="Internal Vref">Internal Vref</a></td><td>0</td></tr>
-<tr> <td><a name="Operating Frequency (MHz)">Operating Frequency (MHz)</a></td><td>525.000000</td></tr>
-<tr> <td><a name="HIGH temperature">HIGH temperature</a></td><td>Normal (0-85)</td></tr>
-</table></ul>
-<h3><a name="DDRInfoTab">Memory Part Configuration</a></h3>
-<ul><table border="1"> 
-<tr><thead>                 <th>Parameter</th>                    <th>Value</th>                 </thead></tr>
-<tr> <td><a name="DRAM IC bus width">DRAM IC bus width</a></td><td>16 Bits</td></tr>
-<tr> <td><a name="DRAM Device Capacity">DRAM Device Capacity</a></td><td>2048 MBits</td></tr>
-<tr> <td><a name="Speed Bin">Speed Bin</a></td><td>DDR3_1066F</td></tr>
-<tr> <td><a name="BANK Address Count">BANK Address Count</a></td><td>3</td></tr>
-<tr> <td><a name="ROW Address Count">ROW Address Count</a></td><td>14</td></tr>
-<tr> <td><a name="COLUMN Address Count">COLUMN Address Count</a></td><td>10</td></tr>
-<tr> <td><a name="CAS Latency">CAS Latency</a></td><td>7</td></tr>
-<tr> <td><a name="CAS Write Latency">CAS Write Latency</a></td><td>6</td></tr>
-<tr> <td><a name="RAS to CAS Delay">RAS to CAS Delay</a></td><td>7</td></tr>
-<tr> <td><a name="RECHARGE Time">RECHARGE Time</a></td><td>7</td></tr>
-<tr> <td><a name="tRC (ns )">tRC (ns )</a></td><td>48.75</td></tr>
-<tr> <td><a name="tRASmin ( ns )">tRASmin ( ns )</a></td><td>35.0</td></tr>
-<tr> <td><a name="tFAW">tFAW</a></td><td>40.0</td></tr>
-<tr> <td><a name="ADDITIVE Latency">ADDITIVE Latency</a></td><td>0</td></tr>
-</table></ul>
-<h3><a name="DDRInfoTab">Training/Board Details</a></h3>
-<ul><table border="1"> 
-<tr><thead>                 <th>Parameter</th>                    <th>Value</th>                 </thead></tr>
-<tr> <td><a name="Write levelling">Write levelling</a></td><td>1</td></tr>
-<tr> <td><a name="Read gate">Read gate</a></td><td>1</td></tr>
-<tr> <td><a name="Read data eye">Read data eye</a></td><td>1</td></tr>
-<tr> <td><a name="DQS to Clock delay [0] (ns)">DQS to Clock delay [0] (ns)</a></td><td>-0.073</td></tr>
-<tr> <td><a name="DQS to Clock delay [1] (ns)">DQS to Clock delay [1] (ns)</a></td><td>-0.034</td></tr>
-<tr> <td><a name="DQS to Clock delay [2] (ns)">DQS to Clock delay [2] (ns)</a></td><td>-0.03</td></tr>
-<tr> <td><a name="DQS to Clock delay [3] (ns)">DQS to Clock delay [3] (ns)</a></td><td>-0.082</td></tr>
-<tr> <td><a name="Board delay [0] (ns)">Board delay [0] (ns)</a></td><td>0.176</td></tr>
-<tr> <td><a name="Board delay [1] (ns)">Board delay [1] (ns)</a></td><td>0.159</td></tr>
-<tr> <td><a name="Board delay [2] (ns)">Board delay [2] (ns)</a></td><td>0.162</td></tr>
-<tr> <td><a name="Board delay [3] (ns)">Board delay [3] (ns)</a></td><td>0.187</td></tr>
-</table></ul>
-<li><a href="#Top">Go To TOP</a></li>
-<h1><a name="ps7_pll_init_data_2_0">ps7_pll_init_data_2_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>PLL SLCR REGISTERS</h2>
-<ul>
-<p>PLL SLCR REGISTERS</p>
-<h2>ARM PLL INIT</h2>
-<ul>
-<p>ARM PLL INIT</p>
-<li><p>Register : ARM_PLL_CFG @ 0XF8000110</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RES</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">c</td><td class="hex">c0</td></tr>
-<tr><td >PLL_CP</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >LOCK_CNT</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">177</td><td class="hex">177000</td></tr>
-<tr><td><b>ARM_PLL_CFG @ 0XF8000110</td><td></td><td class="hex"><b>3ffff0</b></td><td></td><td class="hex"><b>1772c0</b></td></tr></table>
-</li>
-<h2>UPDATE FB_DIV</h2>
-<ul>
-<p>UPDATE FB_DIV</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_FDIV</td><td class="hex">18:12</td><td class="hex">7f000</td><td class="hex">1a</td><td class="hex">1a000</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>7f000</b></td><td></td><td class="hex"><b>1a000</b></td></tr></table>
-</li>
-</ul>
-<h2>BY PASS PLL</h2>
-<ul>
-<p>BY PASS PLL</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>10</b></td></tr></table>
-</li>
-</ul>
-<h2>ASSERT RESET</h2>
-<ul>
-<p>ASSERT RESET</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>DEASSERT RESET</h2>
-<ul>
-<p>DEASSERT RESET</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>CHECK PLL STATUS</h2>
-<ul>
-<p>CHECK PLL STATUS</p>
-<li><p>Register : PLL_STATUS @ 0XF800010C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >ARM_PLL_LOCK</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>PLL_STATUS @ 0XF800010C</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>REMOVE PLL BY PASS</h2>
-<ul>
-<p>REMOVE PLL BY PASS</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : ARM_CLK_CTRL @ 0XF8000120</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >CPU_6OR4XCLKACT</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">1</td><td class="hex">1000000</td></tr>
-<tr><td >CPU_3OR2XCLKACT</td><td class="hex">25:25</td><td class="hex">2000000</td><td class="hex">1</td><td class="hex">2000000</td></tr>
-<tr><td >CPU_2XCLKACT</td><td class="hex">26:26</td><td class="hex">4000000</td><td class="hex">1</td><td class="hex">4000000</td></tr>
-<tr><td >CPU_1XCLKACT</td><td class="hex">27:27</td><td class="hex">8000000</td><td class="hex">1</td><td class="hex">8000000</td></tr>
-<tr><td >CPU_PERI_CLKACT</td><td class="hex">28:28</td><td class="hex">10000000</td><td class="hex">1</td><td class="hex">10000000</td></tr>
-<tr><td><b>ARM_CLK_CTRL @ 0XF8000120</td><td></td><td class="hex"><b>1f003f30</b></td><td></td><td class="hex"><b>1f000200</b></td></tr></table>
-</li>
-</ul>
-<h2>DDR PLL INIT</h2>
-<ul>
-<p>DDR PLL INIT</p>
-<li><p>Register : DDR_PLL_CFG @ 0XF8000114</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RES</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">c</td><td class="hex">c0</td></tr>
-<tr><td >PLL_CP</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >LOCK_CNT</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">1db</td><td class="hex">1db000</td></tr>
-<tr><td><b>DDR_PLL_CFG @ 0XF8000114</td><td></td><td class="hex"><b>3ffff0</b></td><td></td><td class="hex"><b>1db2c0</b></td></tr></table>
-</li>
-<h2>UPDATE FB_DIV</h2>
-<ul>
-<p>UPDATE FB_DIV</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_FDIV</td><td class="hex">18:12</td><td class="hex">7f000</td><td class="hex">15</td><td class="hex">15000</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>7f000</b></td><td></td><td class="hex"><b>15000</b></td></tr></table>
-</li>
-</ul>
-<h2>BY PASS PLL</h2>
-<ul>
-<p>BY PASS PLL</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>10</b></td></tr></table>
-</li>
-</ul>
-<h2>ASSERT RESET</h2>
-<ul>
-<p>ASSERT RESET</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>DEASSERT RESET</h2>
-<ul>
-<p>DEASSERT RESET</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>CHECK PLL STATUS</h2>
-<ul>
-<p>CHECK PLL STATUS</p>
-<li><p>Register : PLL_STATUS @ 0XF800010C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DDR_PLL_LOCK</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td><b>PLL_STATUS @ 0XF800010C</td><td></td><td class="hex"><b>2</b></td><td></td><td class="hex"><b>2</b></td></tr></table>
-</li>
-</ul>
-<h2>REMOVE PLL BY PASS</h2>
-<ul>
-<p>REMOVE PLL BY PASS</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : DDR_CLK_CTRL @ 0XF8000124</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DDR_3XCLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >DDR_2XCLKACT</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >DDR_3XCLK_DIVISOR</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">2</td><td class="hex">200000</td></tr>
-<tr><td >DDR_2XCLK_DIVISOR</td><td class="hex">31:26</td><td class="hex">fc000000</td><td class="hex">3</td><td class="hex">c000000</td></tr>
-<tr><td><b>DDR_CLK_CTRL @ 0XF8000124</td><td></td><td class="hex"><b>fff00003</b></td><td></td><td class="hex"><b>c200003</b></td></tr></table>
-</li>
-</ul>
-<h2>IO PLL INIT</h2>
-<ul>
-<p>IO PLL INIT</p>
-<li><p>Register : IO_PLL_CFG @ 0XF8000118</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RES</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">c</td><td class="hex">c0</td></tr>
-<tr><td >PLL_CP</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >LOCK_CNT</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">1f4</td><td class="hex">1f4000</td></tr>
-<tr><td><b>IO_PLL_CFG @ 0XF8000118</td><td></td><td class="hex"><b>3ffff0</b></td><td></td><td class="hex"><b>1f42c0</b></td></tr></table>
-</li>
-<h2>UPDATE FB_DIV</h2>
-<ul>
-<p>UPDATE FB_DIV</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_FDIV</td><td class="hex">18:12</td><td class="hex">7f000</td><td class="hex">14</td><td class="hex">14000</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>7f000</b></td><td></td><td class="hex"><b>14000</b></td></tr></table>
-</li>
-</ul>
-<h2>BY PASS PLL</h2>
-<ul>
-<p>BY PASS PLL</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>10</b></td></tr></table>
-</li>
-</ul>
-<h2>ASSERT RESET</h2>
-<ul>
-<p>ASSERT RESET</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>DEASSERT RESET</h2>
-<ul>
-<p>DEASSERT RESET</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>CHECK PLL STATUS</h2>
-<ul>
-<p>CHECK PLL STATUS</p>
-<li><p>Register : PLL_STATUS @ 0XF800010C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IO_PLL_LOCK</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td><b>PLL_STATUS @ 0XF800010C</td><td></td><td class="hex"><b>4</b></td><td></td><td class="hex"><b>4</b></td></tr></table>
-</li>
-</ul>
-<h2>REMOVE PLL BY PASS</h2>
-<ul>
-<p>REMOVE PLL BY PASS</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-</ul>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_clock_init_data_2_0">ps7_clock_init_data_2_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>CLOCK CONTROL SLCR REGISTERS</h2>
-<ul>
-<p>CLOCK CONTROL SLCR REGISTERS</p>
-<li><p>Register : DCI_CLK_CTRL @ 0XF8000128</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">34</td><td class="hex">3400</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">2</td><td class="hex">200000</td></tr>
-<tr><td><b>DCI_CLK_CTRL @ 0XF8000128</td><td></td><td class="hex"><b>3f03f01</b></td><td></td><td class="hex"><b>203401</b></td></tr></table>
-</li>
-<li><p>Register : GEM0_RCLK_CTRL @ 0XF8000138</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >SRCSEL</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>GEM0_RCLK_CTRL @ 0XF8000138</td><td></td><td class="hex"><b>11</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-<li><p>Register : GEM0_CLK_CTRL @ 0XF8000140</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >SRCSEL</td><td class="hex">6:4</td><td class="hex">70</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">8</td><td class="hex">800</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td><b>GEM0_CLK_CTRL @ 0XF8000140</td><td></td><td class="hex"><b>3f03f71</b></td><td></td><td class="hex"><b>100801</b></td></tr></table>
-</li>
-<li><p>Register : LQSPI_CLK_CTRL @ 0XF800014C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">5</td><td class="hex">500</td></tr>
-<tr><td><b>LQSPI_CLK_CTRL @ 0XF800014C</td><td></td><td class="hex"><b>3f31</b></td><td></td><td class="hex"><b>501</b></td></tr></table>
-</li>
-<li><p>Register : SDIO_CLK_CTRL @ 0XF8000150</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT0</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >CLKACT1</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">14</td><td class="hex">1400</td></tr>
-<tr><td><b>SDIO_CLK_CTRL @ 0XF8000150</td><td></td><td class="hex"><b>3f33</b></td><td></td><td class="hex"><b>1401</b></td></tr></table>
-</li>
-<li><p>Register : UART_CLK_CTRL @ 0XF8000154</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT0</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >CLKACT1</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">14</td><td class="hex">1400</td></tr>
-<tr><td><b>UART_CLK_CTRL @ 0XF8000154</td><td></td><td class="hex"><b>3f33</b></td><td></td><td class="hex"><b>1403</b></td></tr></table>
-</li>
-<li><p>Register : PCAP_CLK_CTRL @ 0XF8000168</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">5</td><td class="hex">500</td></tr>
-<tr><td><b>PCAP_CLK_CTRL @ 0XF8000168</td><td></td><td class="hex"><b>3f31</b></td><td></td><td class="hex"><b>501</b></td></tr></table>
-</li>
-<li><p>Register : FPGA0_CLK_CTRL @ 0XF8000170</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">a</td><td class="hex">a00</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td><b>FPGA0_CLK_CTRL @ 0XF8000170</td><td></td><td class="hex"><b>3f03f30</b></td><td></td><td class="hex"><b>100a00</b></td></tr></table>
-</li>
-<li><p>Register : FPGA1_CLK_CTRL @ 0XF8000180</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">3</td><td class="hex">30</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">6</td><td class="hex">600</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td><b>FPGA1_CLK_CTRL @ 0XF8000180</td><td></td><td class="hex"><b>3f03f30</b></td><td></td><td class="hex"><b>100630</b></td></tr></table>
-</li>
-<li><p>Register : FPGA2_CLK_CTRL @ 0XF8000190</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">2</td><td class="hex">20</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">35</td><td class="hex">3500</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">2</td><td class="hex">200000</td></tr>
-<tr><td><b>FPGA2_CLK_CTRL @ 0XF8000190</td><td></td><td class="hex"><b>3f03f30</b></td><td></td><td class="hex"><b>203520</b></td></tr></table>
-</li>
-<li><p>Register : FPGA3_CLK_CTRL @ 0XF80001A0</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">a</td><td class="hex">a00</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td><b>FPGA3_CLK_CTRL @ 0XF80001A0</td><td></td><td class="hex"><b>3f03f30</b></td><td></td><td class="hex"><b>100a00</b></td></tr></table>
-</li>
-<li><p>Register : CLK_621_TRUE @ 0XF80001C4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLK_621_TRUE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>CLK_621_TRUE @ 0XF80001C4</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-<li><p>Register : APER_CLK_CTRL @ 0XF800012C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DMA_CPU_2XCLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >USB0_CPU_1XCLKACT</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >USB1_CPU_1XCLKACT</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">1</td><td class="hex">8</td></tr>
-<tr><td >GEM0_CPU_1XCLKACT</td><td class="hex">6:6</td><td class="hex">40</td><td class="hex">1</td><td class="hex">40</td></tr>
-<tr><td >GEM1_CPU_1XCLKACT</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >SDI0_CPU_1XCLKACT</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">1</td><td class="hex">400</td></tr>
-<tr><td >SDI1_CPU_1XCLKACT</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >SPI0_CPU_1XCLKACT</td><td class="hex">14:14</td><td class="hex">4000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >SPI1_CPU_1XCLKACT</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CAN0_CPU_1XCLKACT</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CAN1_CPU_1XCLKACT</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >I2C0_CPU_1XCLKACT</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">1</td><td class="hex">40000</td></tr>
-<tr><td >I2C1_CPU_1XCLKACT</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td >UART0_CPU_1XCLKACT</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td >UART1_CPU_1XCLKACT</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">1</td><td class="hex">200000</td></tr>
-<tr><td >GPIO_CPU_1XCLKACT</td><td class="hex">22:22</td><td class="hex">400000</td><td class="hex">1</td><td class="hex">400000</td></tr>
-<tr><td >LQSPI_CPU_1XCLKACT</td><td class="hex">23:23</td><td class="hex">800000</td><td class="hex">1</td><td class="hex">800000</td></tr>
-<tr><td >SMC_CPU_1XCLKACT</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">1</td><td class="hex">1000000</td></tr>
-<tr><td><b>APER_CLK_CTRL @ 0XF800012C</td><td></td><td class="hex"><b>1ffcccd</b></td><td></td><td class="hex"><b>1fc044d</b></td></tr></table>
-</li>
-</ul>
-<h2>THIS SHOULD BE BLANK</h2>
-<ul>
-<p>THIS SHOULD BE BLANK</p>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_ddr_init_data_2_0">ps7_ddr_init_data_2_0</a></h1>
-<ul>
-<h2>DDR INITIALIZATION</h2>
-<ul>
-<p>DDR INITIALIZATION</p>
-<h2>LOCK DDR</h2>
-<ul>
-<p>LOCK DDR</p>
-<li><p>Register : ddrc_ctrl @ 0XF8006000</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_soft_rstb</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_powerdown_en</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_data_bus_width</td><td class="hex">3:2</td><td class="hex">c</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_burst8_refresh</td><td class="hex">6:4</td><td class="hex">70</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rdwr_idle_gap</td><td class="hex">13:7</td><td class="hex">3f80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >reg_ddrc_dis_rd_bypass</td><td class="hex">14:14</td><td class="hex">4000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_act_bypass</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_auto_refresh</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ddrc_ctrl @ 0XF8006000</td><td></td><td class="hex"><b>1ffff</b></td><td></td><td class="hex"><b>80</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : Two_rank_cfg @ 0XF8006004</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_t_rfc_nom_x32</td><td class="hex">11:0</td><td class="hex">fff</td><td class="hex">7f</td><td class="hex">7f</td></tr>
-<tr><td >reg_ddrc_active_ranks</td><td class="hex">13:12</td><td class="hex">3000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >reg_ddrc_addrmap_cs_bit0</td><td class="hex">18:14</td><td class="hex">7c000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_wr_odt_block</td><td class="hex">20:19</td><td class="hex">180000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td >reg_ddrc_diff_rank_rd_2cycle_gap</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_cs_bit1</td><td class="hex">26:22</td><td class="hex">7c00000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_open_bank</td><td class="hex">27:27</td><td class="hex">8000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_4bank_ram</td><td class="hex">28:28</td><td class="hex">10000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>Two_rank_cfg @ 0XF8006004</td><td></td><td class="hex"><b>1fffffff</b></td><td></td><td class="hex"><b>8107f</b></td></tr></table>
-</li>
-<li><p>Register : HPR_reg @ 0XF8006008</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_hpr_min_non_critical_x32</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">f</td><td class="hex">f</td></tr>
-<tr><td >reg_ddrc_hpr_max_starve_x32</td><td class="hex">21:11</td><td class="hex">3ff800</td><td class="hex">f</td><td class="hex">7800</td></tr>
-<tr><td >reg_ddrc_hpr_xact_run_length</td><td class="hex">25:22</td><td class="hex">3c00000</td><td class="hex">f</td><td class="hex">3c00000</td></tr>
-<tr><td><b>HPR_reg @ 0XF8006008</td><td></td><td class="hex"><b>3ffffff</b></td><td></td><td class="hex"><b>3c0780f</b></td></tr></table>
-</li>
-<li><p>Register : LPR_reg @ 0XF800600C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_lpr_min_non_critical_x32</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_ddrc_lpr_max_starve_x32</td><td class="hex">21:11</td><td class="hex">3ff800</td><td class="hex">2</td><td class="hex">1000</td></tr>
-<tr><td >reg_ddrc_lpr_xact_run_length</td><td class="hex">25:22</td><td class="hex">3c00000</td><td class="hex">8</td><td class="hex">2000000</td></tr>
-<tr><td><b>LPR_reg @ 0XF800600C</td><td></td><td class="hex"><b>3ffffff</b></td><td></td><td class="hex"><b>2001001</b></td></tr></table>
-</li>
-<li><p>Register : WR_reg @ 0XF8006010</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_w_min_non_critical_x32</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_ddrc_w_xact_run_length</td><td class="hex">14:11</td><td class="hex">7800</td><td class="hex">8</td><td class="hex">4000</td></tr>
-<tr><td >reg_ddrc_w_max_starve_x32</td><td class="hex">25:15</td><td class="hex">3ff8000</td><td class="hex">2</td><td class="hex">10000</td></tr>
-<tr><td><b>WR_reg @ 0XF8006010</td><td></td><td class="hex"><b>3ffffff</b></td><td></td><td class="hex"><b>14001</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg0 @ 0XF8006014</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_t_rc</td><td class="hex">5:0</td><td class="hex">3f</td><td class="hex">1a</td><td class="hex">1a</td></tr>
-<tr><td >reg_ddrc_t_rfc_min</td><td class="hex">13:6</td><td class="hex">3fc0</td><td class="hex">54</td><td class="hex">1500</td></tr>
-<tr><td >reg_ddrc_post_selfref_gap_x32</td><td class="hex">20:14</td><td class="hex">1fc000</td><td class="hex">10</td><td class="hex">40000</td></tr>
-<tr><td><b>DRAM_param_reg0 @ 0XF8006014</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>4151a</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg1 @ 0XF8006018</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_wr2pre</td><td class="hex">4:0</td><td class="hex">1f</td><td class="hex">12</td><td class="hex">12</td></tr>
-<tr><td >reg_ddrc_powerdown_to_x32</td><td class="hex">9:5</td><td class="hex">3e0</td><td class="hex">6</td><td class="hex">c0</td></tr>
-<tr><td >reg_ddrc_t_faw</td><td class="hex">15:10</td><td class="hex">fc00</td><td class="hex">15</td><td class="hex">5400</td></tr>
-<tr><td >reg_ddrc_t_ras_max</td><td class="hex">21:16</td><td class="hex">3f0000</td><td class="hex">23</td><td class="hex">230000</td></tr>
-<tr><td >reg_ddrc_t_ras_min</td><td class="hex">26:22</td><td class="hex">7c00000</td><td class="hex">13</td><td class="hex">4c00000</td></tr>
-<tr><td >reg_ddrc_t_cke</td><td class="hex">31:28</td><td class="hex">f0000000</td><td class="hex">4</td><td class="hex">40000000</td></tr>
-<tr><td><b>DRAM_param_reg1 @ 0XF8006018</td><td></td><td class="hex"><b>f7ffffff</b></td><td></td><td class="hex"><b>44e354d2</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg2 @ 0XF800601C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_write_latency</td><td class="hex">4:0</td><td class="hex">1f</td><td class="hex">5</td><td class="hex">5</td></tr>
-<tr><td >reg_ddrc_rd2wr</td><td class="hex">9:5</td><td class="hex">3e0</td><td class="hex">7</td><td class="hex">e0</td></tr>
-<tr><td >reg_ddrc_wr2rd</td><td class="hex">14:10</td><td class="hex">7c00</td><td class="hex">e</td><td class="hex">3800</td></tr>
-<tr><td >reg_ddrc_t_xp</td><td class="hex">19:15</td><td class="hex">f8000</td><td class="hex">4</td><td class="hex">20000</td></tr>
-<tr><td >reg_ddrc_pad_pd</td><td class="hex">22:20</td><td class="hex">700000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rd2pre</td><td class="hex">27:23</td><td class="hex">f800000</td><td class="hex">4</td><td class="hex">2000000</td></tr>
-<tr><td >reg_ddrc_t_rcd</td><td class="hex">31:28</td><td class="hex">f0000000</td><td class="hex">7</td><td class="hex">70000000</td></tr>
-<tr><td><b>DRAM_param_reg2 @ 0XF800601C</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>720238e5</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg3 @ 0XF8006020</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_t_ccd</td><td class="hex">4:2</td><td class="hex">1c</td><td class="hex">4</td><td class="hex">10</td></tr>
-<tr><td >reg_ddrc_t_rrd</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">6</td><td class="hex">c0</td></tr>
-<tr><td >reg_ddrc_refresh_margin</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >reg_ddrc_t_rp</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">7</td><td class="hex">7000</td></tr>
-<tr><td >reg_ddrc_refresh_to_x32</td><td class="hex">20:16</td><td class="hex">1f0000</td><td class="hex">8</td><td class="hex">80000</td></tr>
-<tr><td >reg_ddrc_sdram</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">1</td><td class="hex">200000</td></tr>
-<tr><td >reg_ddrc_mobile</td><td class="hex">22:22</td><td class="hex">400000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_clock_stop_en</td><td class="hex">23:23</td><td class="hex">800000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_read_latency</td><td class="hex">28:24</td><td class="hex">1f000000</td><td class="hex">7</td><td class="hex">7000000</td></tr>
-<tr><td >reg_phy_mode_ddr1_ddr2</td><td class="hex">29:29</td><td class="hex">20000000</td><td class="hex">1</td><td class="hex">20000000</td></tr>
-<tr><td >reg_ddrc_dis_pad_pd</td><td class="hex">30:30</td><td class="hex">40000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_loopback</td><td class="hex">31:31</td><td class="hex">80000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_param_reg3 @ 0XF8006020</td><td></td><td class="hex"><b>fffffffc</b></td><td></td><td class="hex"><b>272872d0</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg4 @ 0XF8006024</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_en_2t_timing_mode</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_prefer_write</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_max_rank_rd</td><td class="hex">5:2</td><td class="hex">3c</td><td class="hex">f</td><td class="hex">3c</td></tr>
-<tr><td >reg_ddrc_mr_wr</td><td class="hex">6:6</td><td class="hex">40</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr_addr</td><td class="hex">8:7</td><td class="hex">180</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr_data</td><td class="hex">24:9</td><td class="hex">1fffe00</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >ddrc_reg_mr_wr_busy</td><td class="hex">25:25</td><td class="hex">2000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr_type</td><td class="hex">26:26</td><td class="hex">4000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr_rdata_valid</td><td class="hex">27:27</td><td class="hex">8000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_param_reg4 @ 0XF8006024</td><td></td><td class="hex"><b>fffffff</b></td><td></td><td class="hex"><b>3c</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_init_param @ 0XF8006028</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_final_wait_x32</td><td class="hex">6:0</td><td class="hex">7f</td><td class="hex">7</td><td class="hex">7</td></tr>
-<tr><td >reg_ddrc_pre_ocd_x32</td><td class="hex">10:7</td><td class="hex">780</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_t_mrd</td><td class="hex">13:11</td><td class="hex">3800</td><td class="hex">4</td><td class="hex">2000</td></tr>
-<tr><td><b>DRAM_init_param @ 0XF8006028</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2007</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_EMR_reg @ 0XF800602C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_emr2</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">8</td><td class="hex">8</td></tr>
-<tr><td >reg_ddrc_emr3</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_EMR_reg @ 0XF800602C</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>8</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_EMR_MR_reg @ 0XF8006030</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_mr</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">930</td><td class="hex">930</td></tr>
-<tr><td >reg_ddrc_emr</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">4</td><td class="hex">40000</td></tr>
-<tr><td><b>DRAM_EMR_MR_reg @ 0XF8006030</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>40930</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_burst8_rdwr @ 0XF8006034</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_burst_rdwr</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">4</td><td class="hex">4</td></tr>
-<tr><td >reg_ddrc_pre_cke_x1024</td><td class="hex">13:4</td><td class="hex">3ff0</td><td class="hex">101</td><td class="hex">1010</td></tr>
-<tr><td >reg_ddrc_post_cke_x1024</td><td class="hex">25:16</td><td class="hex">3ff0000</td><td class="hex">1</td><td class="hex">10000</td></tr>
-<tr><td >reg_ddrc_burstchop</td><td class="hex">28:28</td><td class="hex">10000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_burst8_rdwr @ 0XF8006034</td><td></td><td class="hex"><b>13ff3fff</b></td><td></td><td class="hex"><b>11014</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_disable_DQ @ 0XF8006038</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_force_low_pri_n</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_dq</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_debug_mode</td><td class="hex">6:6</td><td class="hex">40</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_level_start</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rd_level_start</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq0_wait_t</td><td class="hex">12:9</td><td class="hex">1e00</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_disable_DQ @ 0XF8006038</td><td></td><td class="hex"><b>1fc3</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_addr_map_bank @ 0XF800603C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_addrmap_bank_b0</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">7</td><td class="hex">7</td></tr>
-<tr><td >reg_ddrc_addrmap_bank_b1</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">7</td><td class="hex">70</td></tr>
-<tr><td >reg_ddrc_addrmap_bank_b2</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">7</td><td class="hex">700</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b5</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b6</td><td class="hex">19:16</td><td class="hex">f0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_addr_map_bank @ 0XF800603C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>777</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_addr_map_col @ 0XF8006040</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_addrmap_col_b2</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b3</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b4</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b7</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b8</td><td class="hex">19:16</td><td class="hex">f0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b9</td><td class="hex">23:20</td><td class="hex">f00000</td><td class="hex">f</td><td class="hex">f00000</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b10</td><td class="hex">27:24</td><td class="hex">f000000</td><td class="hex">f</td><td class="hex">f000000</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b11</td><td class="hex">31:28</td><td class="hex">f0000000</td><td class="hex">f</td><td class="hex">f0000000</td></tr>
-<tr><td><b>DRAM_addr_map_col @ 0XF8006040</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>fff00000</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_addr_map_row @ 0XF8006044</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_addrmap_row_b0</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">6</td><td class="hex">6</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b1</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">6</td><td class="hex">60</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b2_11</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">6</td><td class="hex">600</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b12</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">6</td><td class="hex">6000</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b13</td><td class="hex">19:16</td><td class="hex">f0000</td><td class="hex">6</td><td class="hex">60000</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b14</td><td class="hex">23:20</td><td class="hex">f00000</td><td class="hex">f</td><td class="hex">f00000</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b15</td><td class="hex">27:24</td><td class="hex">f000000</td><td class="hex">f</td><td class="hex">f000000</td></tr>
-<tr><td><b>DRAM_addr_map_row @ 0XF8006044</td><td></td><td class="hex"><b>fffffff</b></td><td></td><td class="hex"><b>ff66666</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_ODT_reg @ 0XF8006048</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_rank0_rd_odt</td><td class="hex">2:0</td><td class="hex">7</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rank0_wr_odt</td><td class="hex">5:3</td><td class="hex">38</td><td class="hex">1</td><td class="hex">8</td></tr>
-<tr><td >reg_ddrc_rank1_rd_odt</td><td class="hex">8:6</td><td class="hex">1c0</td><td class="hex">1</td><td class="hex">40</td></tr>
-<tr><td >reg_ddrc_rank1_wr_odt</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >reg_phy_rd_local_odt</td><td class="hex">13:12</td><td class="hex">3000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_local_odt</td><td class="hex">15:14</td><td class="hex">c000</td><td class="hex">3</td><td class="hex">c000</td></tr>
-<tr><td >reg_phy_idle_local_odt</td><td class="hex">17:16</td><td class="hex">30000</td><td class="hex">3</td><td class="hex">30000</td></tr>
-<tr><td >reg_ddrc_rank2_rd_odt</td><td class="hex">20:18</td><td class="hex">1c0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rank2_wr_odt</td><td class="hex">23:21</td><td class="hex">e00000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rank3_rd_odt</td><td class="hex">26:24</td><td class="hex">7000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rank3_wr_odt</td><td class="hex">29:27</td><td class="hex">38000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_ODT_reg @ 0XF8006048</td><td></td><td class="hex"><b>3fffffff</b></td><td></td><td class="hex"><b>3c248</b></td></tr></table>
-</li>
-<li><p>Register : phy_cmd_timeout_rddata_cpt @ 0XF8006050</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_cmd_to_data</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_cmd_to_data</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rdc_we_to_re_delay</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">8</td><td class="hex">800</td></tr>
-<tr><td >reg_phy_rdc_fifo_rst_disable</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_use_fixed_re</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">1</td><td class="hex">10000</td></tr>
-<tr><td >reg_phy_rdc_fifo_rst_err_cnt_clr</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dis_phy_ctrl_rstn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_clk_stall_level</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_num_of_dq0</td><td class="hex">27:24</td><td class="hex">f000000</td><td class="hex">7</td><td class="hex">7000000</td></tr>
-<tr><td >reg_phy_wrlvl_num_of_dq0</td><td class="hex">31:28</td><td class="hex">f0000000</td><td class="hex">7</td><td class="hex">70000000</td></tr>
-<tr><td><b>phy_cmd_timeout_rddata_cpt @ 0XF8006050</td><td></td><td class="hex"><b>ff0f8fff</b></td><td></td><td class="hex"><b>77010800</b></td></tr></table>
-</li>
-<li><p>Register : DLL_calib @ 0XF8006058</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_dll_calib_to_min_x1024</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_ddrc_dll_calib_to_max_x1024</td><td class="hex">15:8</td><td class="hex">ff00</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >reg_ddrc_dis_dll_calib</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DLL_calib @ 0XF8006058</td><td></td><td class="hex"><b>1ffff</b></td><td></td><td class="hex"><b>101</b></td></tr></table>
-</li>
-<li><p>Register : ODT_delay_hold @ 0XF800605C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_rd_odt_delay</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">3</td><td class="hex">3</td></tr>
-<tr><td >reg_ddrc_wr_odt_delay</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rd_odt_hold</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_wr_odt_hold</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">5</td><td class="hex">5000</td></tr>
-<tr><td><b>ODT_delay_hold @ 0XF800605C</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>5003</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg1 @ 0XF8006060</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_pageclose</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_lpr_num_entries</td><td class="hex">6:1</td><td class="hex">7e</td><td class="hex">1f</td><td class="hex">3e</td></tr>
-<tr><td >reg_ddrc_auto_pre_en</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_refresh_update_level</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_wc</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_collision_page_opt</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_selfref_en</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ctrl_reg1 @ 0XF8006060</td><td></td><td class="hex"><b>17ff</b></td><td></td><td class="hex"><b>3e</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg2 @ 0XF8006064</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_go2critical_hysteresis</td><td class="hex">12:5</td><td class="hex">1fe0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_go2critical_en</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">1</td><td class="hex">20000</td></tr>
-<tr><td><b>ctrl_reg2 @ 0XF8006064</td><td></td><td class="hex"><b>21fe0</b></td><td></td><td class="hex"><b>20000</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg3 @ 0XF8006068</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_wrlvl_ww</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">41</td><td class="hex">41</td></tr>
-<tr><td >reg_ddrc_rdlvl_rr</td><td class="hex">15:8</td><td class="hex">ff00</td><td class="hex">41</td><td class="hex">4100</td></tr>
-<tr><td >reg_ddrc_dfi_t_wlmrd</td><td class="hex">25:16</td><td class="hex">3ff0000</td><td class="hex">28</td><td class="hex">280000</td></tr>
-<tr><td><b>ctrl_reg3 @ 0XF8006068</td><td></td><td class="hex"><b>3ffffff</b></td><td></td><td class="hex"><b>284141</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg4 @ 0XF800606C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >dfi_t_ctrlupd_interval_min_x1024</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">10</td><td class="hex">10</td></tr>
-<tr><td >dfi_t_ctrlupd_interval_max_x1024</td><td class="hex">15:8</td><td class="hex">ff00</td><td class="hex">16</td><td class="hex">1600</td></tr>
-<tr><td><b>ctrl_reg4 @ 0XF800606C</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>1610</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg5 @ 0XF8006078</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_dfi_t_ctrl_delay</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_ddrc_dfi_t_dram_clk_disable</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >reg_ddrc_dfi_t_dram_clk_enable</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >reg_ddrc_t_cksre</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">6</td><td class="hex">6000</td></tr>
-<tr><td >reg_ddrc_t_cksrx</td><td class="hex">19:16</td><td class="hex">f0000</td><td class="hex">6</td><td class="hex">60000</td></tr>
-<tr><td >reg_ddrc_t_ckesr</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">4</td><td class="hex">400000</td></tr>
-<tr><td><b>ctrl_reg5 @ 0XF8006078</td><td></td><td class="hex"><b>3ffffff</b></td><td></td><td class="hex"><b>466111</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg6 @ 0XF800607C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_t_ckpde</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">2</td><td class="hex">2</td></tr>
-<tr><td >reg_ddrc_t_ckpdx</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">2</td><td class="hex">20</td></tr>
-<tr><td >reg_ddrc_t_ckdpde</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >reg_ddrc_t_ckdpdx</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">2</td><td class="hex">2000</td></tr>
-<tr><td >reg_ddrc_t_ckcsx</td><td class="hex">19:16</td><td class="hex">f0000</td><td class="hex">3</td><td class="hex">30000</td></tr>
-<tr><td><b>ctrl_reg6 @ 0XF800607C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>32222</b></td></tr></table>
-</li>
-<li><p>Register : CHE_REFRESH_TIMER01 @ 0XF80060A0</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >refresh_timer0_start_value_x32</td><td class="hex">11:0</td><td class="hex">fff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >refresh_timer1_start_value_x32</td><td class="hex">23:12</td><td class="hex">fff000</td><td class="hex">8</td><td class="hex">8000</td></tr>
-<tr><td><b>CHE_REFRESH_TIMER01 @ 0XF80060A0</td><td></td><td class="hex"><b>ffffff</b></td><td></td><td class="hex"><b>8000</b></td></tr></table>
-</li>
-<li><p>Register : CHE_T_ZQ @ 0XF80060A4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_dis_auto_zq</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_ddr3</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >reg_ddrc_t_mod</td><td class="hex">11:2</td><td class="hex">ffc</td><td class="hex">200</td><td class="hex">800</td></tr>
-<tr><td >reg_ddrc_t_zq_long_nop</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">200</td><td class="hex">200000</td></tr>
-<tr><td >reg_ddrc_t_zq_short_nop</td><td class="hex">31:22</td><td class="hex">ffc00000</td><td class="hex">40</td><td class="hex">10000000</td></tr>
-<tr><td><b>CHE_T_ZQ @ 0XF80060A4</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>10200802</b></td></tr></table>
-</li>
-<li><p>Register : CHE_T_ZQ_Short_Interval_Reg @ 0XF80060A8</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >t_zq_short_interval_x1024</td><td class="hex">19:0</td><td class="hex">fffff</td><td class="hex">c845</td><td class="hex">c845</td></tr>
-<tr><td >dram_rstn_x1024</td><td class="hex">27:20</td><td class="hex">ff00000</td><td class="hex">67</td><td class="hex">6700000</td></tr>
-<tr><td><b>CHE_T_ZQ_Short_Interval_Reg @ 0XF80060A8</td><td></td><td class="hex"><b>fffffff</b></td><td></td><td class="hex"><b>670c845</b></td></tr></table>
-</li>
-<li><p>Register : deep_pwrdwn_reg @ 0XF80060AC</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >deeppowerdown_en</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >deeppowerdown_to_x1024</td><td class="hex">8:1</td><td class="hex">1fe</td><td class="hex">ff</td><td class="hex">1fe</td></tr>
-<tr><td><b>deep_pwrdwn_reg @ 0XF80060AC</td><td></td><td class="hex"><b>1ff</b></td><td></td><td class="hex"><b>1fe</b></td></tr></table>
-</li>
-<li><p>Register : reg_2c @ 0XF80060B0</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >dfi_wrlvl_max_x1024</td><td class="hex">11:0</td><td class="hex">fff</td><td class="hex">fff</td><td class="hex">fff</td></tr>
-<tr><td >dfi_rdlvl_max_x1024</td><td class="hex">23:12</td><td class="hex">fff000</td><td class="hex">fff</td><td class="hex">fff000</td></tr>
-<tr><td >ddrc_reg_twrlvl_max_error</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >ddrc_reg_trdlvl_max_error</td><td class="hex">25:25</td><td class="hex">2000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dfi_wr_level_en</td><td class="hex">26:26</td><td class="hex">4000000</td><td class="hex">1</td><td class="hex">4000000</td></tr>
-<tr><td >reg_ddrc_dfi_rd_dqs_gate_level</td><td class="hex">27:27</td><td class="hex">8000000</td><td class="hex">1</td><td class="hex">8000000</td></tr>
-<tr><td >reg_ddrc_dfi_rd_data_eye_train</td><td class="hex">28:28</td><td class="hex">10000000</td><td class="hex">1</td><td class="hex">10000000</td></tr>
-<tr><td><b>reg_2c @ 0XF80060B0</td><td></td><td class="hex"><b>1fffffff</b></td><td></td><td class="hex"><b>1cffffff</b></td></tr></table>
-</li>
-<li><p>Register : reg_2d @ 0XF80060B4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_2t_delay</td><td class="hex">8:0</td><td class="hex">1ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_skip_ocd</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >reg_ddrc_dis_pre_bypass</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>reg_2d @ 0XF80060B4</td><td></td><td class="hex"><b>7ff</b></td><td></td><td class="hex"><b>200</b></td></tr></table>
-</li>
-<li><p>Register : dfi_timing @ 0XF80060B8</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_dfi_t_rddata_en</td><td class="hex">4:0</td><td class="hex">1f</td><td class="hex">6</td><td class="hex">6</td></tr>
-<tr><td >reg_ddrc_dfi_t_ctrlup_min</td><td class="hex">14:5</td><td class="hex">7fe0</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >reg_ddrc_dfi_t_ctrlup_max</td><td class="hex">24:15</td><td class="hex">1ff8000</td><td class="hex">40</td><td class="hex">200000</td></tr>
-<tr><td><b>dfi_timing @ 0XF80060B8</td><td></td><td class="hex"><b>1ffffff</b></td><td></td><td class="hex"><b>200066</b></td></tr></table>
-</li>
-<li><p>Register : CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >Clear_Uncorrectable_DRAM_ECC_error</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >Clear_Correctable_DRAM_ECC_error</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td><b>CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4</td><td></td><td class="hex"><b>3</b></td><td></td><td class="hex"><b>3</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >Clear_Uncorrectable_DRAM_ECC_error</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Clear_Correctable_DRAM_ECC_error</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4</td><td></td><td class="hex"><b>3</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : CHE_CORR_ECC_LOG_REG_OFFSET @ 0XF80060C8</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CORR_ECC_LOG_VALID</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >ECC_CORRECTED_BIT_NUM</td><td class="hex">7:1</td><td class="hex">fe</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CHE_CORR_ECC_LOG_REG_OFFSET @ 0XF80060C8</td><td></td><td class="hex"><b>ff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : CHE_UNCORR_ECC_LOG_REG_OFFSET @ 0XF80060DC</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNCORR_ECC_LOG_VALID</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CHE_UNCORR_ECC_LOG_REG_OFFSET @ 0XF80060DC</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : CHE_ECC_STATS_REG_OFFSET @ 0XF80060F0</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >STAT_NUM_CORR_ERR</td><td class="hex">15:8</td><td class="hex">ff00</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >STAT_NUM_UNCORR_ERR</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CHE_ECC_STATS_REG_OFFSET @ 0XF80060F0</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : ECC_scrub @ 0XF80060F4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_ecc_mode</td><td class="hex">2:0</td><td class="hex">7</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_scrub</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">1</td><td class="hex">8</td></tr>
-<tr><td><b>ECC_scrub @ 0XF80060F4</td><td></td><td class="hex"><b>f</b></td><td></td><td class="hex"><b>8</b></td></tr></table>
-</li>
-<li><p>Register : phy_rcvr_enable @ 0XF8006114</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_dif_on</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dif_off</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rcvr_enable @ 0XF8006114</td><td></td><td class="hex"><b>ff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : PHY_Config0 @ 0XF8006118</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_data_slice_in_use</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_phy_rdlvl_inc_mode</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_inc_mode</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wrlvl_inc_mode</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_tx</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_rx</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_shift_dq</td><td class="hex">14:6</td><td class="hex">7fc0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_err_clr</td><td class="hex">23:15</td><td class="hex">ff8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq_offset</td><td class="hex">30:24</td><td class="hex">7f000000</td><td class="hex">40</td><td class="hex">40000000</td></tr>
-<tr><td><b>PHY_Config0 @ 0XF8006118</td><td></td><td class="hex"><b>7fffffff</b></td><td></td><td class="hex"><b>40000001</b></td></tr></table>
-</li>
-<li><p>Register : PHY_Config1 @ 0XF800611C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_data_slice_in_use</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_phy_rdlvl_inc_mode</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_inc_mode</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wrlvl_inc_mode</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_tx</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_rx</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_shift_dq</td><td class="hex">14:6</td><td class="hex">7fc0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_err_clr</td><td class="hex">23:15</td><td class="hex">ff8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq_offset</td><td class="hex">30:24</td><td class="hex">7f000000</td><td class="hex">40</td><td class="hex">40000000</td></tr>
-<tr><td><b>PHY_Config1 @ 0XF800611C</td><td></td><td class="hex"><b>7fffffff</b></td><td></td><td class="hex"><b>40000001</b></td></tr></table>
-</li>
-<li><p>Register : PHY_Config2 @ 0XF8006120</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_data_slice_in_use</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_phy_rdlvl_inc_mode</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_inc_mode</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wrlvl_inc_mode</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_tx</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_rx</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_shift_dq</td><td class="hex">14:6</td><td class="hex">7fc0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_err_clr</td><td class="hex">23:15</td><td class="hex">ff8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq_offset</td><td class="hex">30:24</td><td class="hex">7f000000</td><td class="hex">40</td><td class="hex">40000000</td></tr>
-<tr><td >reg_phy_data_slice_in_use</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_phy_rdlvl_inc_mode</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_inc_mode</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wrlvl_inc_mode</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_tx</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_rx</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_shift_dq</td><td class="hex">14:6</td><td class="hex">7fc0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_err_clr</td><td class="hex">23:15</td><td class="hex">ff8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq_offset</td><td class="hex">30:24</td><td class="hex">7f000000</td><td class="hex">40</td><td class="hex">40000000</td></tr>
-<tr><td><b>PHY_Config2 @ 0XF8006120</td><td></td><td class="hex"><b>7fffffff</b></td><td></td><td class="hex"><b>40000001</b></td></tr></table>
-</li>
-<li><p>Register : PHY_Config3 @ 0XF8006124</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_data_slice_in_use</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_phy_rdlvl_inc_mode</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_inc_mode</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wrlvl_inc_mode</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_tx</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_board_lpbk_rx</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_shift_dq</td><td class="hex">14:6</td><td class="hex">7fc0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_err_clr</td><td class="hex">23:15</td><td class="hex">ff8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq_offset</td><td class="hex">30:24</td><td class="hex">7f000000</td><td class="hex">40</td><td class="hex">40000000</td></tr>
-<tr><td><b>PHY_Config3 @ 0XF8006124</td><td></td><td class="hex"><b>7fffffff</b></td><td></td><td class="hex"><b>40000001</b></td></tr></table>
-</li>
-<li><p>Register : phy_init_ratio0 @ 0XF800612C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wrlvl_init_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_init_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">8f</td><td class="hex">23c00</td></tr>
-<tr><td><b>phy_init_ratio0 @ 0XF800612C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>23c00</b></td></tr></table>
-</li>
-<li><p>Register : phy_init_ratio1 @ 0XF8006130</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wrlvl_init_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_init_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">8a</td><td class="hex">22800</td></tr>
-<tr><td><b>phy_init_ratio1 @ 0XF8006130</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>22800</b></td></tr></table>
-</li>
-<li><p>Register : phy_init_ratio2 @ 0XF8006134</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wrlvl_init_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_init_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">8b</td><td class="hex">22c00</td></tr>
-<tr><td><b>phy_init_ratio2 @ 0XF8006134</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>22c00</b></td></tr></table>
-</li>
-<li><p>Register : phy_init_ratio3 @ 0XF8006138</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wrlvl_init_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_init_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">92</td><td class="hex">24800</td></tr>
-<tr><td><b>phy_init_ratio3 @ 0XF8006138</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>24800</b></td></tr></table>
-</li>
-<li><p>Register : phy_rd_dqs_cfg0 @ 0XF8006140</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">35</td><td class="hex">35</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rd_dqs_cfg0 @ 0XF8006140</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>35</b></td></tr></table>
-</li>
-<li><p>Register : phy_rd_dqs_cfg1 @ 0XF8006144</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">35</td><td class="hex">35</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rd_dqs_cfg1 @ 0XF8006144</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>35</b></td></tr></table>
-</li>
-<li><p>Register : phy_rd_dqs_cfg2 @ 0XF8006148</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">35</td><td class="hex">35</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rd_dqs_cfg2 @ 0XF8006148</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>35</b></td></tr></table>
-</li>
-<li><p>Register : phy_rd_dqs_cfg3 @ 0XF800614C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">35</td><td class="hex">35</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rd_dqs_cfg3 @ 0XF800614C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>35</b></td></tr></table>
-</li>
-<li><p>Register : phy_wr_dqs_cfg0 @ 0XF8006154</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">77</td><td class="hex">77</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_wr_dqs_cfg0 @ 0XF8006154</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>77</b></td></tr></table>
-</li>
-<li><p>Register : phy_wr_dqs_cfg1 @ 0XF8006158</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">7c</td><td class="hex">7c</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_wr_dqs_cfg1 @ 0XF8006158</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>7c</b></td></tr></table>
-</li>
-<li><p>Register : phy_wr_dqs_cfg2 @ 0XF800615C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">7c</td><td class="hex">7c</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_wr_dqs_cfg2 @ 0XF800615C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>7c</b></td></tr></table>
-</li>
-<li><p>Register : phy_wr_dqs_cfg3 @ 0XF8006160</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">75</td><td class="hex">75</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_wr_dqs_cfg3 @ 0XF8006160</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>75</b></td></tr></table>
-</li>
-<li><p>Register : phy_we_cfg0 @ 0XF8006168</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_fifo_we_slave_ratio</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">e4</td><td class="hex">e4</td></tr>
-<tr><td >reg_phy_fifo_we_in_force</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_fifo_we_in_delay</td><td class="hex">20:12</td><td class="hex">1ff000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_we_cfg0 @ 0XF8006168</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>e4</b></td></tr></table>
-</li>
-<li><p>Register : phy_we_cfg1 @ 0XF800616C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_fifo_we_slave_ratio</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">df</td><td class="hex">df</td></tr>
-<tr><td >reg_phy_fifo_we_in_force</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_fifo_we_in_delay</td><td class="hex">20:12</td><td class="hex">1ff000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_we_cfg1 @ 0XF800616C</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>df</b></td></tr></table>
-</li>
-<li><p>Register : phy_we_cfg2 @ 0XF8006170</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_fifo_we_slave_ratio</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">e0</td><td class="hex">e0</td></tr>
-<tr><td >reg_phy_fifo_we_in_force</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_fifo_we_in_delay</td><td class="hex">20:12</td><td class="hex">1ff000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_we_cfg2 @ 0XF8006170</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>e0</b></td></tr></table>
-</li>
-<li><p>Register : phy_we_cfg3 @ 0XF8006174</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_fifo_we_slave_ratio</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">e7</td><td class="hex">e7</td></tr>
-<tr><td >reg_phy_fifo_we_in_force</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_fifo_we_in_delay</td><td class="hex">20:12</td><td class="hex">1ff000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_we_cfg3 @ 0XF8006174</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>e7</b></td></tr></table>
-</li>
-<li><p>Register : wr_data_slv0 @ 0XF800617C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_data_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">b7</td><td class="hex">b7</td></tr>
-<tr><td >reg_phy_wr_data_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_data_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>wr_data_slv0 @ 0XF800617C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>b7</b></td></tr></table>
-</li>
-<li><p>Register : wr_data_slv1 @ 0XF8006180</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_data_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">bc</td><td class="hex">bc</td></tr>
-<tr><td >reg_phy_wr_data_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_data_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>wr_data_slv1 @ 0XF8006180</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>bc</b></td></tr></table>
-</li>
-<li><p>Register : wr_data_slv2 @ 0XF8006184</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_data_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">bc</td><td class="hex">bc</td></tr>
-<tr><td >reg_phy_wr_data_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_data_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>wr_data_slv2 @ 0XF8006184</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>bc</b></td></tr></table>
-</li>
-<li><p>Register : wr_data_slv3 @ 0XF8006188</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_data_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">b5</td><td class="hex">b5</td></tr>
-<tr><td >reg_phy_wr_data_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_data_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>wr_data_slv3 @ 0XF8006188</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>b5</b></td></tr></table>
-</li>
-<li><p>Register : reg_64 @ 0XF8006190</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_loopback</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bl2</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_at_spd_atpg</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_enable</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_force_err</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_mode</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_invert_clkout</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >reg_phy_all_dq_mpr_rd_resp</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_sel_logic</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_ctrl_slave_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">100</td><td class="hex">40000</td></tr>
-<tr><td >reg_phy_ctrl_slave_force</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_ctrl_slave_delay</td><td class="hex">27:21</td><td class="hex">fe00000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_use_rank0_delays</td><td class="hex">28:28</td><td class="hex">10000000</td><td class="hex">1</td><td class="hex">10000000</td></tr>
-<tr><td >reg_phy_lpddr</td><td class="hex">29:29</td><td class="hex">20000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_cmd_latency</td><td class="hex">30:30</td><td class="hex">40000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_int_lpbk</td><td class="hex">31:31</td><td class="hex">80000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>reg_64 @ 0XF8006190</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>10040080</b></td></tr></table>
-</li>
-<li><p>Register : reg_65 @ 0XF8006194</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_rl_delay</td><td class="hex">4:0</td><td class="hex">1f</td><td class="hex">2</td><td class="hex">2</td></tr>
-<tr><td >reg_phy_rd_rl_delay</td><td class="hex">9:5</td><td class="hex">3e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >reg_phy_dll_lock_diff</td><td class="hex">13:10</td><td class="hex">3c00</td><td class="hex">f</td><td class="hex">3c00</td></tr>
-<tr><td >reg_phy_use_wr_level</td><td class="hex">14:14</td><td class="hex">4000</td><td class="hex">1</td><td class="hex">4000</td></tr>
-<tr><td >reg_phy_use_rd_dqs_gate_level</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">1</td><td class="hex">8000</td></tr>
-<tr><td >reg_phy_use_rd_data_eye_level</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">1</td><td class="hex">10000</td></tr>
-<tr><td >reg_phy_dis_calib_rst</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_ctrl_slave_delay</td><td class="hex">19:18</td><td class="hex">c0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>reg_65 @ 0XF8006194</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>1fc82</b></td></tr></table>
-</li>
-<li><p>Register : page_mask @ 0XF8006204</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_page_addr_mask</td><td class="hex">31:0</td><td class="hex">ffffffff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>page_mask @ 0XF8006204</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_wr_port0 @ 0XF8006208</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_wr_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_wr_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_wr_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_wr_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_rmw_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td><b>axi_priority_wr_port0 @ 0XF8006208</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>803ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_wr_port1 @ 0XF800620C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_wr_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_wr_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_wr_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_wr_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_rmw_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td><b>axi_priority_wr_port1 @ 0XF800620C</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>803ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_wr_port2 @ 0XF8006210</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_wr_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_wr_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_wr_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_wr_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_rmw_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td><b>axi_priority_wr_port2 @ 0XF8006210</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>803ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_wr_port3 @ 0XF8006214</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_wr_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_wr_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_wr_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_wr_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_rmw_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td><b>axi_priority_wr_port3 @ 0XF8006214</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>803ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_rd_port0 @ 0XF8006218</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_rd_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_rd_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_rd_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_rd_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_set_hpr_rd_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_rd_port0 @ 0XF8006218</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_rd_port1 @ 0XF800621C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_rd_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_rd_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_rd_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_rd_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_set_hpr_rd_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_rd_port1 @ 0XF800621C</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_rd_port2 @ 0XF8006220</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_rd_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_rd_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_rd_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_rd_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_set_hpr_rd_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_rd_port2 @ 0XF8006220</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_rd_port3 @ 0XF8006224</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_rd_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_rd_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_rd_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_rd_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_set_hpr_rd_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_rd_port3 @ 0XF8006224</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : lpddr_ctrl0 @ 0XF80062A8</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_lpddr2</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_per_bank_refresh</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_derate_enable</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr4_margin</td><td class="hex">11:4</td><td class="hex">ff0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>lpddr_ctrl0 @ 0XF80062A8</td><td></td><td class="hex"><b>ff7</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : lpddr_ctrl1 @ 0XF80062AC</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_mr4_read_interval</td><td class="hex">31:0</td><td class="hex">ffffffff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>lpddr_ctrl1 @ 0XF80062AC</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : lpddr_ctrl2 @ 0XF80062B0</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_min_stable_clock_x1</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">5</td><td class="hex">5</td></tr>
-<tr><td >reg_ddrc_idle_after_reset_x32</td><td class="hex">11:4</td><td class="hex">ff0</td><td class="hex">12</td><td class="hex">120</td></tr>
-<tr><td >reg_ddrc_t_mrw</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">5</td><td class="hex">5000</td></tr>
-<tr><td><b>lpddr_ctrl2 @ 0XF80062B0</td><td></td><td class="hex"><b>3fffff</b></td><td></td><td class="hex"><b>5125</b></td></tr></table>
-</li>
-<li><p>Register : lpddr_ctrl3 @ 0XF80062B4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_max_auto_init_x1024</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">a6</td><td class="hex">a6</td></tr>
-<tr><td >reg_ddrc_dev_zqinit_x32</td><td class="hex">17:8</td><td class="hex">3ff00</td><td class="hex">12</td><td class="hex">1200</td></tr>
-<tr><td><b>lpddr_ctrl3 @ 0XF80062B4</td><td></td><td class="hex"><b>3ffff</b></td><td></td><td class="hex"><b>12a6</b></td></tr></table>
-</li>
-<h2>POLL ON DCI STATUS</h2>
-<ul>
-<p>POLL ON DCI STATUS</p>
-<li><p>Register : DDRIOB_DCI_STATUS @ 0XF8000B74</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DONE</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>DDRIOB_DCI_STATUS @ 0XF8000B74</td><td></td><td class="hex"><b>2000</b></td><td></td><td class="hex"><b>2000</b></td></tr></table>
-</li>
-</ul>
-<h2>UNLOCK DDR</h2>
-<ul>
-<p>UNLOCK DDR</p>
-<li><p>Register : ddrc_ctrl @ 0XF8006000</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_soft_rstb</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_ddrc_powerdown_en</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_data_bus_width</td><td class="hex">3:2</td><td class="hex">c</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_burst8_refresh</td><td class="hex">6:4</td><td class="hex">70</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rdwr_idle_gap</td><td class="hex">13:7</td><td class="hex">3f80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >reg_ddrc_dis_rd_bypass</td><td class="hex">14:14</td><td class="hex">4000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_act_bypass</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_auto_refresh</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ddrc_ctrl @ 0XF8006000</td><td></td><td class="hex"><b>1ffff</b></td><td></td><td class="hex"><b>81</b></td></tr></table>
-</li>
-</ul>
-<h2>CHECK DDR STATUS</h2>
-<ul>
-<p>CHECK DDR STATUS</p>
-<li><p>Register : mode_sts_reg @ 0XF8006054</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >ddrc_reg_operating_mode</td><td class="hex">2:0</td><td class="hex">7</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>mode_sts_reg @ 0XF8006054</td><td></td><td class="hex"><b>7</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_mio_init_data_2_0">ps7_mio_init_data_2_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>OCM REMAPPING</h2>
-<ul>
-<p>OCM REMAPPING</p>
-<li><p>Register : GPIOB_CTRL @ 0XF8000B00</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >VREF_EN</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >VREF_PULLUP_EN</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CLK_PULLUP_EN</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >SRSTN_PULLUP_EN</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>GPIOB_CTRL @ 0XF8000B00</td><td></td><td class="hex"><b>303</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>DDRIOB SETTINGS</h2>
-<ul>
-<p>DDRIOB SETTINGS</p>
-<li><p>Register : DDRIOB_ADDR0 @ 0XF8000B40</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_POWER</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCI_UPDATE</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCR_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_ADDR0 @ 0XF8000B40</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_ADDR1 @ 0XF8000B44</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_POWER</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCI_UPDATE</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCR_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_ADDR1 @ 0XF8000B44</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DATA0 @ 0XF8000B48</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_POWER</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >DCI_UPDATE</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >DCR_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DATA0 @ 0XF8000B48</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>672</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DATA1 @ 0XF8000B4C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_POWER</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >DCI_UPDATE</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >DCR_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DATA1 @ 0XF8000B4C</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>672</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DIFF0 @ 0XF8000B50</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_POWER</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">2</td><td class="hex">4</td></tr>
-<tr><td >DCI_UPDATE</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >DCR_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DIFF0 @ 0XF8000B50</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>674</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DIFF1 @ 0XF8000B54</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_POWER</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">2</td><td class="hex">4</td></tr>
-<tr><td >DCI_UPDATE</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >DCR_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DIFF1 @ 0XF8000B54</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>674</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_CLOCK @ 0XF8000B58</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_POWER</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCI_UPDATE</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCR_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_CLOCK @ 0XF8000B58</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DRIVE_SLEW_ADDR @ 0XF8000B5C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DRIVE_P</td><td class="hex">6:0</td><td class="hex">7f</td><td class="hex">1c</td><td class="hex">1c</td></tr>
-<tr><td >DRIVE_N</td><td class="hex">13:7</td><td class="hex">3f80</td><td class="hex">c</td><td class="hex">600</td></tr>
-<tr><td >SLEW_P</td><td class="hex">18:14</td><td class="hex">7c000</td><td class="hex">1a</td><td class="hex">68000</td></tr>
-<tr><td >SLEW_N</td><td class="hex">23:19</td><td class="hex">f80000</td><td class="hex">1a</td><td class="hex">d00000</td></tr>
-<tr><td >GTL</td><td class="hex">26:24</td><td class="hex">7000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RTERM</td><td class="hex">31:27</td><td class="hex">f8000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DRIVE_SLEW_ADDR @ 0XF8000B5C</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>d6861c</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DRIVE_SLEW_DATA @ 0XF8000B60</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DRIVE_P</td><td class="hex">6:0</td><td class="hex">7f</td><td class="hex">1c</td><td class="hex">1c</td></tr>
-<tr><td >DRIVE_N</td><td class="hex">13:7</td><td class="hex">3f80</td><td class="hex">c</td><td class="hex">600</td></tr>
-<tr><td >SLEW_P</td><td class="hex">18:14</td><td class="hex">7c000</td><td class="hex">6</td><td class="hex">18000</td></tr>
-<tr><td >SLEW_N</td><td class="hex">23:19</td><td class="hex">f80000</td><td class="hex">1f</td><td class="hex">f80000</td></tr>
-<tr><td >GTL</td><td class="hex">26:24</td><td class="hex">7000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RTERM</td><td class="hex">31:27</td><td class="hex">f8000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DRIVE_SLEW_DATA @ 0XF8000B60</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>f9861c</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DRIVE_SLEW_DIFF @ 0XF8000B64</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DRIVE_P</td><td class="hex">6:0</td><td class="hex">7f</td><td class="hex">1c</td><td class="hex">1c</td></tr>
-<tr><td >DRIVE_N</td><td class="hex">13:7</td><td class="hex">3f80</td><td class="hex">c</td><td class="hex">600</td></tr>
-<tr><td >SLEW_P</td><td class="hex">18:14</td><td class="hex">7c000</td><td class="hex">6</td><td class="hex">18000</td></tr>
-<tr><td >SLEW_N</td><td class="hex">23:19</td><td class="hex">f80000</td><td class="hex">1f</td><td class="hex">f80000</td></tr>
-<tr><td >GTL</td><td class="hex">26:24</td><td class="hex">7000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RTERM</td><td class="hex">31:27</td><td class="hex">f8000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DRIVE_SLEW_DIFF @ 0XF8000B64</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>f9861c</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DRIVE_SLEW_CLOCK @ 0XF8000B68</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DRIVE_P</td><td class="hex">6:0</td><td class="hex">7f</td><td class="hex">1c</td><td class="hex">1c</td></tr>
-<tr><td >DRIVE_N</td><td class="hex">13:7</td><td class="hex">3f80</td><td class="hex">c</td><td class="hex">600</td></tr>
-<tr><td >SLEW_P</td><td class="hex">18:14</td><td class="hex">7c000</td><td class="hex">1a</td><td class="hex">68000</td></tr>
-<tr><td >SLEW_N</td><td class="hex">23:19</td><td class="hex">f80000</td><td class="hex">1a</td><td class="hex">d00000</td></tr>
-<tr><td >GTL</td><td class="hex">26:24</td><td class="hex">7000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RTERM</td><td class="hex">31:27</td><td class="hex">f8000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DRIVE_SLEW_CLOCK @ 0XF8000B68</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>d6861c</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DDR_CTRL @ 0XF8000B6C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >VREF_INT_EN</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >VREF_SEL</td><td class="hex">4:1</td><td class="hex">1e</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >VREF_EXT_EN</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >VREF_PULLUP_EN</td><td class="hex">8:7</td><td class="hex">180</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >REFIO_EN</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >REFIO_TEST</td><td class="hex">11:10</td><td class="hex">c00</td><td class="hex">3</td><td class="hex">c00</td></tr>
-<tr><td >REFIO_PULLUP_EN</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DRST_B_PULLUP_EN</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CKE_PULLUP_EN</td><td class="hex">14:14</td><td class="hex">4000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DDR_CTRL @ 0XF8000B6C</td><td></td><td class="hex"><b>7fff</b></td><td></td><td class="hex"><b>e60</b></td></tr></table>
-</li>
-<h2>ASSERT RESET</h2>
-<ul>
-<p>ASSERT RESET</p>
-<li><p>Register : DDRIOB_DCI_CTRL @ 0XF8000B70</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >VRN_OUT</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">1</td><td class="hex">20</td></tr>
-<tr><td><b>DDRIOB_DCI_CTRL @ 0XF8000B70</td><td></td><td class="hex"><b>21</b></td><td></td><td class="hex"><b>21</b></td></tr></table>
-</li>
-</ul>
-<h2>DEASSERT RESET</h2>
-<ul>
-<p>DEASSERT RESET</p>
-<li><p>Register : DDRIOB_DCI_CTRL @ 0XF8000B70</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >VRN_OUT</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">1</td><td class="hex">20</td></tr>
-<tr><td><b>DDRIOB_DCI_CTRL @ 0XF8000B70</td><td></td><td class="hex"><b>21</b></td><td></td><td class="hex"><b>20</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : DDRIOB_DCI_CTRL @ 0XF8000B70</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >ENABLE</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >VRP_TRI</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >VRN_TRI</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >VRP_OUT</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >VRN_OUT</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">1</td><td class="hex">20</td></tr>
-<tr><td >NREF_OPT1</td><td class="hex">7:6</td><td class="hex">c0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >NREF_OPT2</td><td class="hex">10:8</td><td class="hex">700</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >NREF_OPT4</td><td class="hex">13:11</td><td class="hex">3800</td><td class="hex">1</td><td class="hex">800</td></tr>
-<tr><td >PREF_OPT1</td><td class="hex">16:14</td><td class="hex">1c000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >PREF_OPT2</td><td class="hex">19:17</td><td class="hex">e0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >UPDATE_CONTROL</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INIT_COMPLETE</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TST_CLK</td><td class="hex">22:22</td><td class="hex">400000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TST_HLN</td><td class="hex">23:23</td><td class="hex">800000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TST_HLP</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TST_RST</td><td class="hex">25:25</td><td class="hex">2000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >INT_DCI_EN</td><td class="hex">26:26</td><td class="hex">4000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DCI_CTRL @ 0XF8000B70</td><td></td><td class="hex"><b>7ffffff</b></td><td></td><td class="hex"><b>823</b></td></tr></table>
-</li>
-</ul>
-<h2>MIO PROGRAMMING</h2>
-<ul>
-<p>MIO PROGRAMMING</p>
-<li><p>Register : MIO_PIN_00 @ 0XF8000700</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_00 @ 0XF8000700</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_01 @ 0XF8000704</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_01 @ 0XF8000704</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_02 @ 0XF8000708</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_02 @ 0XF8000708</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_03 @ 0XF800070C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_03 @ 0XF800070C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_04 @ 0XF8000710</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_04 @ 0XF8000710</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_05 @ 0XF8000714</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_05 @ 0XF8000714</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_06 @ 0XF8000718</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_06 @ 0XF8000718</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_07 @ 0XF800071C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_07 @ 0XF800071C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_08 @ 0XF8000720</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_08 @ 0XF8000720</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_09 @ 0XF8000724</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_09 @ 0XF8000724</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_10 @ 0XF8000728</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">2</td><td class="hex">40</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_10 @ 0XF8000728</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>1640</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_11 @ 0XF800072C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">2</td><td class="hex">40</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_11 @ 0XF800072C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>1640</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_12 @ 0XF8000730</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">2</td><td class="hex">40</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_12 @ 0XF8000730</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>1640</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_13 @ 0XF8000734</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">2</td><td class="hex">40</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_13 @ 0XF8000734</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>1640</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_14 @ 0XF8000738</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_14 @ 0XF8000738</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_15 @ 0XF800073C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_15 @ 0XF800073C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_16 @ 0XF8000740</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_16 @ 0XF8000740</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_17 @ 0XF8000744</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_17 @ 0XF8000744</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_18 @ 0XF8000748</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_18 @ 0XF8000748</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_19 @ 0XF800074C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_19 @ 0XF800074C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_20 @ 0XF8000750</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_20 @ 0XF8000750</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_21 @ 0XF8000754</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_21 @ 0XF8000754</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_22 @ 0XF8000758</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_22 @ 0XF8000758</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_23 @ 0XF800075C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_23 @ 0XF800075C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_24 @ 0XF8000760</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_24 @ 0XF8000760</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_25 @ 0XF8000764</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_25 @ 0XF8000764</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_26 @ 0XF8000768</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_26 @ 0XF8000768</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_27 @ 0XF800076C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_27 @ 0XF800076C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_28 @ 0XF8000770</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_28 @ 0XF8000770</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_29 @ 0XF8000774</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_29 @ 0XF8000774</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>305</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_30 @ 0XF8000778</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_30 @ 0XF8000778</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_31 @ 0XF800077C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_31 @ 0XF800077C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>305</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_32 @ 0XF8000780</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_32 @ 0XF8000780</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_33 @ 0XF8000784</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_33 @ 0XF8000784</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_34 @ 0XF8000788</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_34 @ 0XF8000788</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_35 @ 0XF800078C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_35 @ 0XF800078C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_36 @ 0XF8000790</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_36 @ 0XF8000790</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>305</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_37 @ 0XF8000794</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_37 @ 0XF8000794</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_38 @ 0XF8000798</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_38 @ 0XF8000798</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_39 @ 0XF800079C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_39 @ 0XF800079C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_40 @ 0XF80007A0</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_40 @ 0XF80007A0</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_41 @ 0XF80007A4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_41 @ 0XF80007A4</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_42 @ 0XF80007A8</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_42 @ 0XF80007A8</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_43 @ 0XF80007AC</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_43 @ 0XF80007AC</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_44 @ 0XF80007B0</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_44 @ 0XF80007B0</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_45 @ 0XF80007B4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_45 @ 0XF80007B4</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_46 @ 0XF80007B8</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_46 @ 0XF80007B8</td><td></td><td class="hex"><b>3f01</b></td><td></td><td class="hex"><b>200</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_47 @ 0XF80007BC</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_47 @ 0XF80007BC</td><td></td><td class="hex"><b>3f01</b></td><td></td><td class="hex"><b>201</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_48 @ 0XF80007C0</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">7</td><td class="hex">e0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_48 @ 0XF80007C0</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2e0</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_49 @ 0XF80007C4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">7</td><td class="hex">e0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_49 @ 0XF80007C4</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2e1</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_50 @ 0XF80007C8</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_50 @ 0XF80007C8</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>201</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_51 @ 0XF80007CC</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_51 @ 0XF80007CC</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>201</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_52 @ 0XF80007D0</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_52 @ 0XF80007D0</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>280</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_53 @ 0XF80007D4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_53 @ 0XF80007D4</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>280</b></td></tr></table>
-</li>
-<li><p>Register : SD0_WP_CD_SEL @ 0XF8000830</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SDIO0_CD_SEL</td><td class="hex">21:16</td><td class="hex">3f0000</td><td class="hex">2f</td><td class="hex">2f0000</td></tr>
-<tr><td><b>SD0_WP_CD_SEL @ 0XF8000830</td><td></td><td class="hex"><b>3f0000</b></td><td></td><td class="hex"><b>2f0000</b></td></tr></table>
-</li>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_peripherals_init_data_2_0">ps7_peripherals_init_data_2_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>DDR TERM/IBUF_DISABLE_MODE SETTINGS</h2>
-<ul>
-<p>DDR TERM/IBUF_DISABLE_MODE SETTINGS</p>
-<li><p>Register : DDRIOB_DATA0 @ 0XF8000B48</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td><b>DDRIOB_DATA0 @ 0XF8000B48</td><td></td><td class="hex"><b>180</b></td><td></td><td class="hex"><b>180</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DATA1 @ 0XF8000B4C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td><b>DDRIOB_DATA1 @ 0XF8000B4C</td><td></td><td class="hex"><b>180</b></td><td></td><td class="hex"><b>180</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DIFF0 @ 0XF8000B50</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td><b>DDRIOB_DIFF0 @ 0XF8000B50</td><td></td><td class="hex"><b>180</b></td><td></td><td class="hex"><b>180</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DIFF1 @ 0XF8000B54</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td><b>DDRIOB_DIFF1 @ 0XF8000B54</td><td></td><td class="hex"><b>180</b></td><td></td><td class="hex"><b>180</b></td></tr></table>
-</li>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-<h2>SRAM/NOR SET OPMODE</h2>
-<ul>
-<p>SRAM/NOR SET OPMODE</p>
-</ul>
-<h2>UART REGISTERS</h2>
-<ul>
-<p>UART REGISTERS</p>
-<li><p>Register : Baud_rate_divider_reg0 @ 0XE0001034</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >BDIV</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">6</td><td class="hex">6</td></tr>
-<tr><td><b>Baud_rate_divider_reg0 @ 0XE0001034</td><td></td><td class="hex"><b>ff</b></td><td></td><td class="hex"><b>6</b></td></tr></table>
-</li>
-<li><p>Register : Baud_rate_gen_reg0 @ 0XE0001018</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CD</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">3e</td><td class="hex">3e</td></tr>
-<tr><td><b>Baud_rate_gen_reg0 @ 0XE0001018</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>3e</b></td></tr></table>
-</li>
-<li><p>Register : Control_reg0 @ 0XE0001000</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >STPBRK</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >STTBRK</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RSTTO</td><td class="hex">6:6</td><td class="hex">40</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TXDIS</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TXEN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >RXDIS</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RXEN</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >TXRES</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >RXRES</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>Control_reg0 @ 0XE0001000</td><td></td><td class="hex"><b>1ff</b></td><td></td><td class="hex"><b>17</b></td></tr></table>
-</li>
-<li><p>Register : mode_reg0 @ 0XE0001004</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IRMODE</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >UCLKEN</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CHMODE</td><td class="hex">9:8</td><td class="hex">300</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >NBSTOP</td><td class="hex">7:6</td><td class="hex">c0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >PAR</td><td class="hex">5:3</td><td class="hex">38</td><td class="hex">4</td><td class="hex">20</td></tr>
-<tr><td >CHRL</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CLKS</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>mode_reg0 @ 0XE0001004</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>20</b></td></tr></table>
-</li>
-<li><p>Register : Baud_rate_divider_reg0 @ 0XE0000034</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >BDIV</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">6</td><td class="hex">6</td></tr>
-<tr><td><b>Baud_rate_divider_reg0 @ 0XE0000034</td><td></td><td class="hex"><b>ff</b></td><td></td><td class="hex"><b>6</b></td></tr></table>
-</li>
-<li><p>Register : Baud_rate_gen_reg0 @ 0XE0000018</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CD</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">3e</td><td class="hex">3e</td></tr>
-<tr><td><b>Baud_rate_gen_reg0 @ 0XE0000018</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>3e</b></td></tr></table>
-</li>
-<li><p>Register : Control_reg0 @ 0XE0000000</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >STPBRK</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >STTBRK</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RSTTO</td><td class="hex">6:6</td><td class="hex">40</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TXDIS</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TXEN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >RXDIS</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RXEN</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >TXRES</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >RXRES</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>Control_reg0 @ 0XE0000000</td><td></td><td class="hex"><b>1ff</b></td><td></td><td class="hex"><b>17</b></td></tr></table>
-</li>
-<li><p>Register : mode_reg0 @ 0XE0000004</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IRMODE</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >UCLKEN</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CHMODE</td><td class="hex">9:8</td><td class="hex">300</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >NBSTOP</td><td class="hex">7:6</td><td class="hex">c0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >PAR</td><td class="hex">5:3</td><td class="hex">38</td><td class="hex">4</td><td class="hex">20</td></tr>
-<tr><td >CHRL</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CLKS</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>mode_reg0 @ 0XE0000004</td><td></td><td class="hex"><b>fff</b></td><td></td><td class="hex"><b>20</b></td></tr></table>
-</li>
-</ul>
-<h2>QSPI REGISTERS</h2>
-<ul>
-<p>QSPI REGISTERS</p>
-<li><p>Register : Config_reg @ 0XE000D000</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >Holdb_dr</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td><b>Config_reg @ 0XE000D000</td><td></td><td class="hex"><b>80000</b></td><td></td><td class="hex"><b>80000</b></td></tr></table>
-</li>
-</ul>
-<h2>PL POWER ON RESET REGISTERS</h2>
-<ul>
-<p>PL POWER ON RESET REGISTERS</p>
-<li><p>Register : CTRL @ 0XF8007000</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PCFG_POR_CNT_4K</td><td class="hex">29:29</td><td class="hex">20000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CTRL @ 0XF8007000</td><td></td><td class="hex"><b>20000000</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>SMC TIMING CALCULATION REGISTER UPDATE</h2>
-<ul>
-<p>SMC TIMING CALCULATION REGISTER UPDATE</p>
-<h2>NAND SET CYCLE</h2>
-<ul>
-<p>NAND SET CYCLE</p>
-</ul>
-<h2>OPMODE</h2>
-<ul>
-<p>OPMODE</p>
-</ul>
-<h2>DIRECT COMMAND</h2>
-<ul>
-<p>DIRECT COMMAND</p>
-</ul>
-<h2>SRAM/NOR CS0 SET CYCLE</h2>
-<ul>
-<p>SRAM/NOR CS0 SET CYCLE</p>
-</ul>
-<h2>DIRECT COMMAND</h2>
-<ul>
-<p>DIRECT COMMAND</p>
-</ul>
-<h2>NOR CS0 BASE ADDRESS</h2>
-<ul>
-<p>NOR CS0 BASE ADDRESS</p>
-</ul>
-<h2>SRAM/NOR CS1 SET CYCLE</h2>
-<ul>
-<p>SRAM/NOR CS1 SET CYCLE</p>
-</ul>
-<h2>DIRECT COMMAND</h2>
-<ul>
-<p>DIRECT COMMAND</p>
-</ul>
-<h2>NOR CS1 BASE ADDRESS</h2>
-<ul>
-<p>NOR CS1 BASE ADDRESS</p>
-</ul>
-<h2>USB RESET</h2>
-<ul>
-<p>USB RESET</p>
-<h2>DIR MODE BANK 0</h2>
-<ul>
-<p>DIR MODE BANK 0</p>
-</ul>
-<h2>DIR MODE BANK 1</h2>
-<ul>
-<p>DIR MODE BANK 1</p>
-<li><p>Register : DIRM_1 @ 0XE000A244</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DIRECTION_1</td><td class="hex">21:0</td><td class="hex">3fffff</td><td class="hex">4000</td><td class="hex">4000</td></tr>
-<tr><td><b>DIRM_1 @ 0XE000A244</td><td></td><td class="hex"><b>3fffff</b></td><td></td><td class="hex"><b>4000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-<li><p>Register : MASK_DATA_1_LSW @ 0XE000A008</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >MASK_1_LSW</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">bfff</td><td class="hex">bfff0000</td></tr>
-<tr><td >DATA_1_LSW</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">4000</td><td class="hex">4000</td></tr>
-<tr><td><b>MASK_DATA_1_LSW @ 0XE000A008</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>bfff4000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-<h2>OUTPUT ENABLE BANK 0</h2>
-<ul>
-<p>OUTPUT ENABLE BANK 0</p>
-</ul>
-<h2>OUTPUT ENABLE BANK 1</h2>
-<ul>
-<p>OUTPUT ENABLE BANK 1</p>
-<li><p>Register : OEN_1 @ 0XE000A248</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >OP_ENABLE_1</td><td class="hex">21:0</td><td class="hex">3fffff</td><td class="hex">4000</td><td class="hex">4000</td></tr>
-<tr><td><b>OEN_1 @ 0XE000A248</td><td></td><td class="hex"><b>3fffff</b></td><td></td><td class="hex"><b>4000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_0_LSW LOW BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW LOW BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW LOW BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW LOW BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW LOW BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW LOW BANK [47:32]</p>
-<li><p>Register : MASK_DATA_1_LSW @ 0XE000A008</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >MASK_1_LSW</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">bfff</td><td class="hex">bfff0000</td></tr>
-<tr><td >DATA_1_LSW</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MASK_DATA_1_LSW @ 0XE000A008</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>bfff0000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_1_MSW LOW BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW LOW BANK [53:48]</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-<li><p>Register : MASK_DATA_1_LSW @ 0XE000A008</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >MASK_1_LSW</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">bfff</td><td class="hex">bfff0000</td></tr>
-<tr><td >DATA_1_LSW</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">4000</td><td class="hex">4000</td></tr>
-<tr><td><b>MASK_DATA_1_LSW @ 0XE000A008</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>bfff4000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-</ul>
-<h2>ENET RESET</h2>
-<ul>
-<p>ENET RESET</p>
-<h2>DIR MODE BANK 0</h2>
-<ul>
-<p>DIR MODE BANK 0</p>
-</ul>
-<h2>DIR MODE BANK 1</h2>
-<ul>
-<p>DIR MODE BANK 1</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-<h2>OUTPUT ENABLE BANK 0</h2>
-<ul>
-<p>OUTPUT ENABLE BANK 0</p>
-</ul>
-<h2>OUTPUT ENABLE BANK 1</h2>
-<ul>
-<p>OUTPUT ENABLE BANK 1</p>
-</ul>
-<h2>MASK_DATA_0_LSW LOW BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW LOW BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW LOW BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW LOW BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW LOW BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW LOW BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW LOW BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW LOW BANK [53:48]</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-</ul>
-<h2>I2C RESET</h2>
-<ul>
-<p>I2C RESET</p>
-<h2>DIR MODE GPIO BANK0</h2>
-<ul>
-<p>DIR MODE GPIO BANK0</p>
-</ul>
-<h2>DIR MODE GPIO BANK1</h2>
-<ul>
-<p>DIR MODE GPIO BANK1</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-<h2>OUTPUT ENABLE</h2>
-<ul>
-<p>OUTPUT ENABLE</p>
-</ul>
-<h2>OUTPUT ENABLE</h2>
-<ul>
-<p>OUTPUT ENABLE</p>
-</ul>
-<h2>MASK_DATA_0_LSW LOW BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW LOW BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW LOW BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW LOW BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW LOW BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW LOW BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW LOW BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW LOW BANK [53:48]</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-</ul>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_post_config_2_0">ps7_post_config_2_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>ENABLING LEVEL SHIFTER</h2>
-<ul>
-<p>ENABLING LEVEL SHIFTER</p>
-<li><p>Register : LVL_SHFTR_EN @ 0XF8000900</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >USER_INP_ICT_EN_0</td><td class="hex">1:0</td><td class="hex">3</td><td class="hex">3</td><td class="hex">3</td></tr>
-<tr><td >USER_INP_ICT_EN_1</td><td class="hex">3:2</td><td class="hex">c</td><td class="hex">3</td><td class="hex">c</td></tr>
-<tr><td><b>LVL_SHFTR_EN @ 0XF8000900</td><td></td><td class="hex"><b>f</b></td><td></td><td class="hex"><b>f</b></td></tr></table>
-</li>
-</ul>
-<h2>FPGA RESETS TO 1</h2>
-<ul>
-<p>FPGA RESETS TO 1</p>
-<li><p>Register : FPGA_RST_CTRL @ 0XF8000240</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reserved_3</td><td class="hex">31:25</td><td class="hex">fe000000</td><td class="hex">7f</td><td class="hex">fe000000</td></tr>
-<tr><td >FPGA_ACP_RST</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">1</td><td class="hex">1000000</td></tr>
-<tr><td >FPGA_AXDS3_RST</td><td class="hex">23:23</td><td class="hex">800000</td><td class="hex">1</td><td class="hex">800000</td></tr>
-<tr><td >FPGA_AXDS2_RST</td><td class="hex">22:22</td><td class="hex">400000</td><td class="hex">1</td><td class="hex">400000</td></tr>
-<tr><td >FPGA_AXDS1_RST</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">1</td><td class="hex">200000</td></tr>
-<tr><td >FPGA_AXDS0_RST</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td >reserved_2</td><td class="hex">19:18</td><td class="hex">c0000</td><td class="hex">3</td><td class="hex">c0000</td></tr>
-<tr><td >FSSW1_FPGA_RST</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">1</td><td class="hex">20000</td></tr>
-<tr><td >FSSW0_FPGA_RST</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">1</td><td class="hex">10000</td></tr>
-<tr><td >reserved_1</td><td class="hex">15:14</td><td class="hex">c000</td><td class="hex">3</td><td class="hex">c000</td></tr>
-<tr><td >FPGA_FMSW1_RST</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td >FPGA_FMSW0_RST</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >FPGA_DMA3_RST</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">1</td><td class="hex">800</td></tr>
-<tr><td >FPGA_DMA2_RST</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">1</td><td class="hex">400</td></tr>
-<tr><td >FPGA_DMA1_RST</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >FPGA_DMA0_RST</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >reserved</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">f</td><td class="hex">f0</td></tr>
-<tr><td >FPGA3_OUT_RST</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">1</td><td class="hex">8</td></tr>
-<tr><td >FPGA2_OUT_RST</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >FPGA1_OUT_RST</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >FPGA0_OUT_RST</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>FPGA_RST_CTRL @ 0XF8000240</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>ffffffff</b></td></tr></table>
-</li>
-</ul>
-<h2>FPGA RESETS TO 0</h2>
-<ul>
-<p>FPGA RESETS TO 0</p>
-<li><p>Register : FPGA_RST_CTRL @ 0XF8000240</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reserved_3</td><td class="hex">31:25</td><td class="hex">fe000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_ACP_RST</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_AXDS3_RST</td><td class="hex">23:23</td><td class="hex">800000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_AXDS2_RST</td><td class="hex">22:22</td><td class="hex">400000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_AXDS1_RST</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_AXDS0_RST</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_2</td><td class="hex">19:18</td><td class="hex">c0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FSSW1_FPGA_RST</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FSSW0_FPGA_RST</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_1</td><td class="hex">15:14</td><td class="hex">c000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_FMSW1_RST</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_FMSW0_RST</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_DMA3_RST</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_DMA2_RST</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_DMA1_RST</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA_DMA0_RST</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA3_OUT_RST</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA2_OUT_RST</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA1_OUT_RST</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA0_OUT_RST</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>FPGA_RST_CTRL @ 0XF8000240</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>AFI REGISTERS</h2>
-<ul>
-<p>AFI REGISTERS</p>
-<h2>AFI0 REGISTERS</h2>
-<ul>
-<p>AFI0 REGISTERS</p>
-</ul>
-<h2>AFI1 REGISTERS</h2>
-<ul>
-<p>AFI1 REGISTERS</p>
-</ul>
-<h2>AFI2 REGISTERS</h2>
-<ul>
-<p>AFI2 REGISTERS</p>
-</ul>
-<h2>AFI3 REGISTERS</h2>
-<ul>
-<p>AFI3 REGISTERS</p>
-</ul>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-</ul>
-<hr/>
-</body>
-</html>
-<!DOCTYPE html>
-<html lang="en">
-<head>
-<meta http-equiv="content-type" content="text/html;charset=UTF-8"/>
-<title>Zynq PS configuration detail</title>
-<style type="text/css">
-.hex {font-family:monospace ; text-align : right}
-td { min-width : 80px ; } 
-</style>
-</head>
-<body>
-<p style="height: 7px">Following peripherals are selected in the design. </p>
-<p><br /></p>
-<h2><a name="Top">Peripheral Selected</a></h2>
-<ul>
-<li>Quad SPI Flash</li>
-<li>Enet 0</li>
-<li>USB 0</li>
-<li>SD 0</li>
-<li>UART 0</li>
-<li>UART 1</li>
-<li>I2C 0</li>
-<li>I2C 1</li>
-<li>GPIO</li>
-</ul>
-<p>To see detailed information please follow below links:</p>
-<ul>
-<li><a href="#MIOConfTab">MIO Configuration Table</a></li>
-<li><a href="#ZynqPerTab">Zynq Peripheral Configuration</a></li>
-<li><a href="#DDRInfoTab">DDR Configuration Information</a></li>
-<li>SLCR settings</li>
-<ul>
-<li><a href="#ps7_pll_init_data">PLL Init Data</a></li>
-<li><a href="#ps7_clock_init_data">Clock Init Data</a></li>
-<li><a href="#ps7_ddr_init_data">DDR Init Data</a></li>
-<li><a href="#ps7_mio_init_data">MIO Init Data</a></li>
-</ul>
-</ul>
-<h2><a name="MIOConfTab">MIO configuration Table</a></h2>
-<ul><table border="1"> 
-<thead><tr>                <th>MIO Pin</th>                <th>Peripheral</th>             <th>Signal</th>               <th>IO type</th>              <th>Speed</th>              <th>Pullup</th>              <th>Direction</th>              </tr></thead>
-<tr bgcolor="#FA4A46"><td><a name="MIO 0">MIO 0</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[0]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 1">MIO 1</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_ss_b</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 2">MIO 2</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_io[0]</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 3">MIO 3</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_io[1]</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 4">MIO 4</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_io[2]</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 5">MIO 5</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_io[3]</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 6">MIO 6</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi0_sclk</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 7">MIO 7</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[7]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#FAEBD7"><td><a name="MIO 8">MIO 8</a></td><td><a href="#Quad SPI Flash">Quad SPI Flash</a></td><td>qspi_fbclk</td><td>LVCMOS 3.3V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 9">MIO 9</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[9]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="MIO 10">MIO 10</a></td><td><a href="#I2C 0">I2C 0</a></td><td>scl</td><td>LVCMOS 3.3V</td><td>slow</td><td>enabled</td><td>inout</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="MIO 11">MIO 11</a></td><td><a href="#I2C 0">I2C 0</a></td><td>sda</td><td>LVCMOS 3.3V</td><td>slow</td><td>enabled</td><td>inout</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="MIO 12">MIO 12</a></td><td><a href="#I2C 1">I2C 1</a></td><td>scl</td><td>LVCMOS 3.3V</td><td>slow</td><td>enabled</td><td>inout</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="MIO 13">MIO 13</a></td><td><a href="#I2C 1">I2C 1</a></td><td>sda</td><td>LVCMOS 3.3V</td><td>slow</td><td>enabled</td><td>inout</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 14">MIO 14</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[14]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 15">MIO 15</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[15]</td><td>LVCMOS 3.3V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 16">MIO 16</a></td><td><a href="#Enet 0">Enet 0</a></td><td>tx_clk</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 17">MIO 17</a></td><td><a href="#Enet 0">Enet 0</a></td><td>txd[0]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 18">MIO 18</a></td><td><a href="#Enet 0">Enet 0</a></td><td>txd[1]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 19">MIO 19</a></td><td><a href="#Enet 0">Enet 0</a></td><td>txd[2]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 20">MIO 20</a></td><td><a href="#Enet 0">Enet 0</a></td><td>txd[3]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 21">MIO 21</a></td><td><a href="#Enet 0">Enet 0</a></td><td>tx_ctl</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 22">MIO 22</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rx_clk</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 23">MIO 23</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rxd[0]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 24">MIO 24</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rxd[1]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 25">MIO 25</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rxd[2]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 26">MIO 26</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rxd[3]</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 27">MIO 27</a></td><td><a href="#Enet 0">Enet 0</a></td><td>rx_ctl</td><td>HSTL 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 28">MIO 28</a></td><td><a href="#USB 0">USB 0</a></td><td>data[4]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 29">MIO 29</a></td><td><a href="#USB 0">USB 0</a></td><td>dir</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 30">MIO 30</a></td><td><a href="#USB 0">USB 0</a></td><td>stp</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 31">MIO 31</a></td><td><a href="#USB 0">USB 0</a></td><td>nxt</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 32">MIO 32</a></td><td><a href="#USB 0">USB 0</a></td><td>data[0]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 33">MIO 33</a></td><td><a href="#USB 0">USB 0</a></td><td>data[1]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 34">MIO 34</a></td><td><a href="#USB 0">USB 0</a></td><td>data[2]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 35">MIO 35</a></td><td><a href="#USB 0">USB 0</a></td><td>data[3]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 36">MIO 36</a></td><td><a href="#USB 0">USB 0</a></td><td>clk</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 37">MIO 37</a></td><td><a href="#USB 0">USB 0</a></td><td>data[5]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 38">MIO 38</a></td><td><a href="#USB 0">USB 0</a></td><td>data[6]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 39">MIO 39</a></td><td><a href="#USB 0">USB 0</a></td><td>data[7]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 40">MIO 40</a></td><td><a href="#SD 0">SD 0</a></td><td>clk</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 41">MIO 41</a></td><td><a href="#SD 0">SD 0</a></td><td>cmd</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 42">MIO 42</a></td><td><a href="#SD 0">SD 0</a></td><td>data[0]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 43">MIO 43</a></td><td><a href="#SD 0">SD 0</a></td><td>data[1]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 44">MIO 44</a></td><td><a href="#SD 0">SD 0</a></td><td>data[2]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 45">MIO 45</a></td><td><a href="#SD 0">SD 0</a></td><td>data[3]</td><td>LVCMOS 1.8V</td><td>fast</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="MIO 46">MIO 46</a></td><td><a href="#USB 0">USB 0</a></td><td>reset</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-<tr bgcolor="#D2691E"><td><a name="MIO 47">MIO 47</a></td><td><a href="#SD 0">SD 0</a></td><td>cd</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#6495ED"><td><a name="MIO 48">MIO 48</a></td><td><a href="#UART 1">UART 1</a></td><td>tx</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#6495ED"><td><a name="MIO 49">MIO 49</a></td><td><a href="#UART 1">UART 1</a></td><td>rx</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 50">MIO 50</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[50]</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="MIO 51">MIO 51</a></td><td><a href="#GPIO">GPIO</a></td><td>gpio[51]</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>in</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 52">MIO 52</a></td><td><a href="#Enet 0">Enet 0</a></td><td>mdc</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>out</td></tr>
-<tr bgcolor="#DEB887"><td><a name="MIO 53">MIO 53</a></td><td><a href="#Enet 0">Enet 0</a></td><td>mdio</td><td>LVCMOS 1.8V</td><td>slow</td><td>disabled</td><td>inout</td></tr>
-</table></ul>
-<li><a href="#Top">Go To TOP</a></li>
-<h2><a name="ZynqPerTab">Zynq Peripheral Configuration</a></h2>
-<ul><table border="1"> 
-<tr><thead>             <th>Peripheral</th>                <th>Signal Group</th>             <th>Signal</th>               <th>MIO</th>              </thead></tr>
-<tr bgcolor="#FAEBD7"><td><a name="Quad SPI Flash" >Quad SPI Flash</a></td>             <td></td><td></td><td>MIO 1 .. 6</td></tr>
-<tr bgcolor="#FAEBD7"><td></td><td>Dual Quad SPI (4 bit) </td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FAEBD7"><td></td><td>Dual Quad SPI (Parallel 8 bit)</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FAEBD7"><td></td><td>Feedback Clk</td><td></td><td>MIO 8</td></tr>
-<tr bgcolor="#FFFFFF"><td><a name="nor" >SRAM/NOR Flash</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FFE4C4"><td><a name="nand" >NAND Flash</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#DEB887"><td><a name="Enet 0" >Enet 0</a></td>             <td></td><td></td><td>MIO 16 .. 27</td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>tx_clk</td><td><a href="#MIO 16">MIO 16</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>txd[3]</td><td><a href="#MIO 20">MIO 20</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>txd[2]</td><td><a href="#MIO 19">MIO 19</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>txd[1]</td><td><a href="#MIO 18">MIO 18</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>txd[0]</td><td><a href="#MIO 17">MIO 17</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>tx_ctl</td><td><a href="#MIO 21">MIO 21</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rx_clk</td><td><a href="#MIO 22">MIO 22</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rxd[3]</td><td><a href="#MIO 26">MIO 26</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rxd[2]</td><td><a href="#MIO 25">MIO 25</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rxd[1]</td><td><a href="#MIO 24">MIO 24</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rxd[0]</td><td><a href="#MIO 23">MIO 23</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>rx_ctl</td><td><a href="#MIO 27">MIO 27</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td>MDIO</td><td></td><td>MIO 52 .. 53</td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>mdc</td><td><a href="#MIO 52">MIO 52</a></td></tr>
-<tr bgcolor="#DEB887"><td></td><td></td><td>mdio</td><td><a href="#MIO 53">MIO 53</a></td></tr>
-<tr bgcolor="#DEB887"><td><a name="enet1" >Enet 1</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#7FFF00"><td><a name="USB 0" >USB 0</a></td>             <td></td><td></td><td>MIO 28 .. 39</td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>clk</td><td><a href="#MIO 36">MIO 36</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>dir</td><td><a href="#MIO 29">MIO 29</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>stp</td><td><a href="#MIO 30">MIO 30</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>nxt</td><td><a href="#MIO 31">MIO 31</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[0]</td><td><a href="#MIO 32">MIO 32</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[1]</td><td><a href="#MIO 33">MIO 33</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[2]</td><td><a href="#MIO 34">MIO 34</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[3]</td><td><a href="#MIO 35">MIO 35</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[4]</td><td><a href="#MIO 28">MIO 28</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[5]</td><td><a href="#MIO 37">MIO 37</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[6]</td><td><a href="#MIO 38">MIO 38</a></td></tr>
-<tr bgcolor="#7FFF00"><td></td><td></td><td>data[7]</td><td><a href="#MIO 39">MIO 39</a></td></tr>
-<tr bgcolor="#7FFF00"><td><a name="usb1" >USB 1</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#D2691E"><td><a name="SD 0" >SD 0</a></td>             <td></td><td></td><td>MIO 40 .. 45</td></tr>
-<tr bgcolor="#D2691E"><td></td><td>CD</td><td></td><td>MIO 47</td></tr>
-<tr bgcolor="#D2691E"><td></td><td>WP</td><td></td><td>EMIO</td></tr>
-<tr bgcolor="#D2691E"><td></td><td>Power</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#D2691E"><td><a name="sd1" >SD 1</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#6495ED"><td><a name="UART 0" >UART 0</a></td>             <td></td><td></td><td>EMIO</td></tr>
-<tr bgcolor="#6495ED"><td></td><td></td><td>rx</td><td>EMIO</td></tr>
-<tr bgcolor="#6495ED"><td></td><td></td><td>tx</td><td>EMIO</td></tr>
-<tr bgcolor="#6495ED"><td></td><td>Modem signals</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#6495ED"><td><a name="UART 1" >UART 1</a></td>             <td></td><td></td><td>MIO 48 .. 49</td></tr>
-<tr bgcolor="#6495ED"><td></td><td></td><td>rx</td><td><a href="#MIO 49">MIO 49</a></td></tr>
-<tr bgcolor="#6495ED"><td></td><td></td><td>tx</td><td><a href="#MIO 48">MIO 48</a></td></tr>
-<tr bgcolor="#6495ED"><td></td><td>Modem Signals</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="I2C 0" >I2C 0</a></td>             <td></td><td></td><td>MIO 10 .. 11</td></tr>
-<tr bgcolor="#BDB76B"><td></td><td></td><td>scl</td><td><a href="#MIO 10">MIO 10</a></td></tr>
-<tr bgcolor="#BDB76B"><td></td><td></td><td>sda</td><td><a href="#MIO 11">MIO 11</a></td></tr>
-<tr bgcolor="#BDB76B"><td></td><td>Interrupt</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#BDB76B"><td><a name="I2C 1" >I2C 1</a></td>             <td></td><td></td><td>MIO 12 .. 13</td></tr>
-<tr bgcolor="#BDB76B"><td></td><td></td><td>scl</td><td><a href="#MIO 12">MIO 12</a></td></tr>
-<tr bgcolor="#BDB76B"><td></td><td></td><td>sda</td><td><a href="#MIO 13">MIO 13</a></td></tr>
-<tr bgcolor="#BDB76B"><td></td><td>Interrupt</td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#8DBC8F"><td><a name="spi0" >SPI 0</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#8DBC8F"><td><a name="spi1" >SPI 1</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#DAA520"><td><a name="can0" >CAN 0</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#DAA520"><td><a name="can1" >CAN 1</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#ADD8E6"><td><a name="trace" >Trace</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#BC8F8F"><td><a name="ttc0" >Timer 0</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#BC8F8F"><td><a name="ttc1" >Timer 1</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FF6347"><td><a name="wdt" >Watchdog</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#EE82EE"><td><a name="pjtag" >PJTAG</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FA4A46"><td><a name="GPIO" >GPIO</a></td>             <td></td><td></td><td>MIO</td></tr>
-<tr bgcolor="#FFFFFF"><td><a name="mode" >Mode</a></td>             <td></td><td></td><td>Disabled</td></tr>
-<tr bgcolor="#FFFFFF"><td><a name="vcfg" >VCfg</a></td>             <td></td><td></td><td>Disabled</td></tr>
-</table></ul>
-<li><a href="#Top">Go To TOP</a></li>
-<h2><a name="DDRInfoTab">DDR Memory information</a></h2>
-<h3><a name="DDRInfoTab">DDR Controller Configuration</a></h3>
-<ul><table border="1"> 
-<tr><thead>                 <th>Parameter</th>                    <th>Value</th>                 </thead></tr>
-<tr> <td><a name="Enable DDR">Enable DDR</a></td><td>1</td></tr>
-<tr> <td><a name="Memory Type">Memory Type</a></td><td>DDR 3</td></tr>
-<tr> <td><a name="Memory Part">Memory Part</a></td><td>MT41K128M16 JT-125</td></tr>
-<tr> <td><a name="DRAM bus width">DRAM bus width</a></td><td>32 Bit</td></tr>
-<tr> <td><a name="ECC">ECC</a></td><td>Disabled</td></tr>
-<tr> <td><a name="BURST Length (lppdr only)">BURST Length (lppdr only)</a></td><td>8</td></tr>
-<tr> <td><a name="Internal Vref">Internal Vref</a></td><td>0</td></tr>
-<tr> <td><a name="Operating Frequency (MHz)">Operating Frequency (MHz)</a></td><td>525.000000</td></tr>
-<tr> <td><a name="HIGH temperature">HIGH temperature</a></td><td>Normal (0-85)</td></tr>
-</table></ul>
-<h3><a name="DDRInfoTab">Memory Part Configuration</a></h3>
-<ul><table border="1"> 
-<tr><thead>                 <th>Parameter</th>                    <th>Value</th>                 </thead></tr>
-<tr> <td><a name="DRAM IC bus width">DRAM IC bus width</a></td><td>16 Bits</td></tr>
-<tr> <td><a name="DRAM Device Capacity">DRAM Device Capacity</a></td><td>2048 MBits</td></tr>
-<tr> <td><a name="Speed Bin">Speed Bin</a></td><td>DDR3_1066F</td></tr>
-<tr> <td><a name="BANK Address Count">BANK Address Count</a></td><td>3</td></tr>
-<tr> <td><a name="ROW Address Count">ROW Address Count</a></td><td>14</td></tr>
-<tr> <td><a name="COLUMN Address Count">COLUMN Address Count</a></td><td>10</td></tr>
-<tr> <td><a name="CAS Latency">CAS Latency</a></td><td>7</td></tr>
-<tr> <td><a name="CAS Write Latency">CAS Write Latency</a></td><td>6</td></tr>
-<tr> <td><a name="RAS to CAS Delay">RAS to CAS Delay</a></td><td>7</td></tr>
-<tr> <td><a name="RECHARGE Time">RECHARGE Time</a></td><td>7</td></tr>
-<tr> <td><a name="tRC (ns )">tRC (ns )</a></td><td>48.75</td></tr>
-<tr> <td><a name="tRASmin ( ns )">tRASmin ( ns )</a></td><td>35.0</td></tr>
-<tr> <td><a name="tFAW">tFAW</a></td><td>40.0</td></tr>
-<tr> <td><a name="ADDITIVE Latency">ADDITIVE Latency</a></td><td>0</td></tr>
-</table></ul>
-<h3><a name="DDRInfoTab">Training/Board Details</a></h3>
-<ul><table border="1"> 
-<tr><thead>                 <th>Parameter</th>                    <th>Value</th>                 </thead></tr>
-<tr> <td><a name="Write levelling">Write levelling</a></td><td>1</td></tr>
-<tr> <td><a name="Read gate">Read gate</a></td><td>1</td></tr>
-<tr> <td><a name="Read data eye">Read data eye</a></td><td>1</td></tr>
-<tr> <td><a name="DQS to Clock delay [0] (ns)">DQS to Clock delay [0] (ns)</a></td><td>-0.073</td></tr>
-<tr> <td><a name="DQS to Clock delay [1] (ns)">DQS to Clock delay [1] (ns)</a></td><td>-0.034</td></tr>
-<tr> <td><a name="DQS to Clock delay [2] (ns)">DQS to Clock delay [2] (ns)</a></td><td>-0.03</td></tr>
-<tr> <td><a name="DQS to Clock delay [3] (ns)">DQS to Clock delay [3] (ns)</a></td><td>-0.082</td></tr>
-<tr> <td><a name="Board delay [0] (ns)">Board delay [0] (ns)</a></td><td>0.176</td></tr>
-<tr> <td><a name="Board delay [1] (ns)">Board delay [1] (ns)</a></td><td>0.159</td></tr>
-<tr> <td><a name="Board delay [2] (ns)">Board delay [2] (ns)</a></td><td>0.162</td></tr>
-<tr> <td><a name="Board delay [3] (ns)">Board delay [3] (ns)</a></td><td>0.187</td></tr>
-</table></ul>
-<li><a href="#Top">Go To TOP</a></li>
-<h1><a name="ps7_pll_init_data_3_0">ps7_pll_init_data_3_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>PLL SLCR REGISTERS</h2>
-<ul>
-<p>PLL SLCR REGISTERS</p>
-<h2>ARM PLL INIT</h2>
-<ul>
-<p>ARM PLL INIT</p>
-<li><p>Register : ARM_PLL_CFG @ 0XF8000110</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RES</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">c</td><td class="hex">c0</td></tr>
-<tr><td >PLL_CP</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >LOCK_CNT</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">177</td><td class="hex">177000</td></tr>
-<tr><td><b>ARM_PLL_CFG @ 0XF8000110</td><td></td><td class="hex"><b>3ffff0</b></td><td></td><td class="hex"><b>1772c0</b></td></tr></table>
-</li>
-<h2>UPDATE FB_DIV</h2>
-<ul>
-<p>UPDATE FB_DIV</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_FDIV</td><td class="hex">18:12</td><td class="hex">7f000</td><td class="hex">1a</td><td class="hex">1a000</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>7f000</b></td><td></td><td class="hex"><b>1a000</b></td></tr></table>
-</li>
-</ul>
-<h2>BY PASS PLL</h2>
-<ul>
-<p>BY PASS PLL</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>10</b></td></tr></table>
-</li>
-</ul>
-<h2>ASSERT RESET</h2>
-<ul>
-<p>ASSERT RESET</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>DEASSERT RESET</h2>
-<ul>
-<p>DEASSERT RESET</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>CHECK PLL STATUS</h2>
-<ul>
-<p>CHECK PLL STATUS</p>
-<li><p>Register : PLL_STATUS @ 0XF800010C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >ARM_PLL_LOCK</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>PLL_STATUS @ 0XF800010C</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>REMOVE PLL BY PASS</h2>
-<ul>
-<p>REMOVE PLL BY PASS</p>
-<li><p>Register : ARM_PLL_CTRL @ 0XF8000100</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ARM_PLL_CTRL @ 0XF8000100</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : ARM_CLK_CTRL @ 0XF8000120</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >CPU_6OR4XCLKACT</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">1</td><td class="hex">1000000</td></tr>
-<tr><td >CPU_3OR2XCLKACT</td><td class="hex">25:25</td><td class="hex">2000000</td><td class="hex">1</td><td class="hex">2000000</td></tr>
-<tr><td >CPU_2XCLKACT</td><td class="hex">26:26</td><td class="hex">4000000</td><td class="hex">1</td><td class="hex">4000000</td></tr>
-<tr><td >CPU_1XCLKACT</td><td class="hex">27:27</td><td class="hex">8000000</td><td class="hex">1</td><td class="hex">8000000</td></tr>
-<tr><td >CPU_PERI_CLKACT</td><td class="hex">28:28</td><td class="hex">10000000</td><td class="hex">1</td><td class="hex">10000000</td></tr>
-<tr><td><b>ARM_CLK_CTRL @ 0XF8000120</td><td></td><td class="hex"><b>1f003f30</b></td><td></td><td class="hex"><b>1f000200</b></td></tr></table>
-</li>
-</ul>
-<h2>DDR PLL INIT</h2>
-<ul>
-<p>DDR PLL INIT</p>
-<li><p>Register : DDR_PLL_CFG @ 0XF8000114</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RES</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">c</td><td class="hex">c0</td></tr>
-<tr><td >PLL_CP</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >LOCK_CNT</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">1db</td><td class="hex">1db000</td></tr>
-<tr><td><b>DDR_PLL_CFG @ 0XF8000114</td><td></td><td class="hex"><b>3ffff0</b></td><td></td><td class="hex"><b>1db2c0</b></td></tr></table>
-</li>
-<h2>UPDATE FB_DIV</h2>
-<ul>
-<p>UPDATE FB_DIV</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_FDIV</td><td class="hex">18:12</td><td class="hex">7f000</td><td class="hex">15</td><td class="hex">15000</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>7f000</b></td><td></td><td class="hex"><b>15000</b></td></tr></table>
-</li>
-</ul>
-<h2>BY PASS PLL</h2>
-<ul>
-<p>BY PASS PLL</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>10</b></td></tr></table>
-</li>
-</ul>
-<h2>ASSERT RESET</h2>
-<ul>
-<p>ASSERT RESET</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>DEASSERT RESET</h2>
-<ul>
-<p>DEASSERT RESET</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>CHECK PLL STATUS</h2>
-<ul>
-<p>CHECK PLL STATUS</p>
-<li><p>Register : PLL_STATUS @ 0XF800010C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DDR_PLL_LOCK</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td><b>PLL_STATUS @ 0XF800010C</td><td></td><td class="hex"><b>2</b></td><td></td><td class="hex"><b>2</b></td></tr></table>
-</li>
-</ul>
-<h2>REMOVE PLL BY PASS</h2>
-<ul>
-<p>REMOVE PLL BY PASS</p>
-<li><p>Register : DDR_PLL_CTRL @ 0XF8000104</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDR_PLL_CTRL @ 0XF8000104</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : DDR_CLK_CTRL @ 0XF8000124</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DDR_3XCLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >DDR_2XCLKACT</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >DDR_3XCLK_DIVISOR</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">2</td><td class="hex">200000</td></tr>
-<tr><td >DDR_2XCLK_DIVISOR</td><td class="hex">31:26</td><td class="hex">fc000000</td><td class="hex">3</td><td class="hex">c000000</td></tr>
-<tr><td><b>DDR_CLK_CTRL @ 0XF8000124</td><td></td><td class="hex"><b>fff00003</b></td><td></td><td class="hex"><b>c200003</b></td></tr></table>
-</li>
-</ul>
-<h2>IO PLL INIT</h2>
-<ul>
-<p>IO PLL INIT</p>
-<li><p>Register : IO_PLL_CFG @ 0XF8000118</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RES</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">c</td><td class="hex">c0</td></tr>
-<tr><td >PLL_CP</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >LOCK_CNT</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">1f4</td><td class="hex">1f4000</td></tr>
-<tr><td><b>IO_PLL_CFG @ 0XF8000118</td><td></td><td class="hex"><b>3ffff0</b></td><td></td><td class="hex"><b>1f42c0</b></td></tr></table>
-</li>
-<h2>UPDATE FB_DIV</h2>
-<ul>
-<p>UPDATE FB_DIV</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_FDIV</td><td class="hex">18:12</td><td class="hex">7f000</td><td class="hex">14</td><td class="hex">14000</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>7f000</b></td><td></td><td class="hex"><b>14000</b></td></tr></table>
-</li>
-</ul>
-<h2>BY PASS PLL</h2>
-<ul>
-<p>BY PASS PLL</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>10</b></td></tr></table>
-</li>
-</ul>
-<h2>ASSERT RESET</h2>
-<ul>
-<p>ASSERT RESET</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>DEASSERT RESET</h2>
-<ul>
-<p>DEASSERT RESET</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>CHECK PLL STATUS</h2>
-<ul>
-<p>CHECK PLL STATUS</p>
-<li><p>Register : PLL_STATUS @ 0XF800010C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IO_PLL_LOCK</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td><b>PLL_STATUS @ 0XF800010C</td><td></td><td class="hex"><b>4</b></td><td></td><td class="hex"><b>4</b></td></tr></table>
-</li>
-</ul>
-<h2>REMOVE PLL BY PASS</h2>
-<ul>
-<p>REMOVE PLL BY PASS</p>
-<li><p>Register : IO_PLL_CTRL @ 0XF8000108</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PLL_BYPASS_FORCE</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>IO_PLL_CTRL @ 0XF8000108</td><td></td><td class="hex"><b>10</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-</ul>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_clock_init_data_3_0">ps7_clock_init_data_3_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>CLOCK CONTROL SLCR REGISTERS</h2>
-<ul>
-<p>CLOCK CONTROL SLCR REGISTERS</p>
-<li><p>Register : DCI_CLK_CTRL @ 0XF8000128</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">34</td><td class="hex">3400</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">2</td><td class="hex">200000</td></tr>
-<tr><td><b>DCI_CLK_CTRL @ 0XF8000128</td><td></td><td class="hex"><b>3f03f01</b></td><td></td><td class="hex"><b>203401</b></td></tr></table>
-</li>
-<li><p>Register : GEM0_RCLK_CTRL @ 0XF8000138</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >SRCSEL</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>GEM0_RCLK_CTRL @ 0XF8000138</td><td></td><td class="hex"><b>11</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-<li><p>Register : GEM0_CLK_CTRL @ 0XF8000140</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >SRCSEL</td><td class="hex">6:4</td><td class="hex">70</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">8</td><td class="hex">800</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td><b>GEM0_CLK_CTRL @ 0XF8000140</td><td></td><td class="hex"><b>3f03f71</b></td><td></td><td class="hex"><b>100801</b></td></tr></table>
-</li>
-<li><p>Register : LQSPI_CLK_CTRL @ 0XF800014C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">5</td><td class="hex">500</td></tr>
-<tr><td><b>LQSPI_CLK_CTRL @ 0XF800014C</td><td></td><td class="hex"><b>3f31</b></td><td></td><td class="hex"><b>501</b></td></tr></table>
-</li>
-<li><p>Register : SDIO_CLK_CTRL @ 0XF8000150</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT0</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >CLKACT1</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">14</td><td class="hex">1400</td></tr>
-<tr><td><b>SDIO_CLK_CTRL @ 0XF8000150</td><td></td><td class="hex"><b>3f33</b></td><td></td><td class="hex"><b>1401</b></td></tr></table>
-</li>
-<li><p>Register : UART_CLK_CTRL @ 0XF8000154</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT0</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >CLKACT1</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">14</td><td class="hex">1400</td></tr>
-<tr><td><b>UART_CLK_CTRL @ 0XF8000154</td><td></td><td class="hex"><b>3f33</b></td><td></td><td class="hex"><b>1403</b></td></tr></table>
-</li>
-<li><p>Register : PCAP_CLK_CTRL @ 0XF8000168</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">5</td><td class="hex">500</td></tr>
-<tr><td><b>PCAP_CLK_CTRL @ 0XF8000168</td><td></td><td class="hex"><b>3f31</b></td><td></td><td class="hex"><b>501</b></td></tr></table>
-</li>
-<li><p>Register : FPGA0_CLK_CTRL @ 0XF8000170</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">a</td><td class="hex">a00</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td><b>FPGA0_CLK_CTRL @ 0XF8000170</td><td></td><td class="hex"><b>3f03f30</b></td><td></td><td class="hex"><b>100a00</b></td></tr></table>
-</li>
-<li><p>Register : FPGA1_CLK_CTRL @ 0XF8000180</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">3</td><td class="hex">30</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">6</td><td class="hex">600</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td><b>FPGA1_CLK_CTRL @ 0XF8000180</td><td></td><td class="hex"><b>3f03f30</b></td><td></td><td class="hex"><b>100630</b></td></tr></table>
-</li>
-<li><p>Register : FPGA2_CLK_CTRL @ 0XF8000190</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">2</td><td class="hex">20</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">35</td><td class="hex">3500</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">2</td><td class="hex">200000</td></tr>
-<tr><td><b>FPGA2_CLK_CTRL @ 0XF8000190</td><td></td><td class="hex"><b>3f03f30</b></td><td></td><td class="hex"><b>203520</b></td></tr></table>
-</li>
-<li><p>Register : FPGA3_CLK_CTRL @ 0XF80001A0</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SRCSEL</td><td class="hex">5:4</td><td class="hex">30</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DIVISOR0</td><td class="hex">13:8</td><td class="hex">3f00</td><td class="hex">a</td><td class="hex">a00</td></tr>
-<tr><td >DIVISOR1</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td><b>FPGA3_CLK_CTRL @ 0XF80001A0</td><td></td><td class="hex"><b>3f03f30</b></td><td></td><td class="hex"><b>100a00</b></td></tr></table>
-</li>
-<li><p>Register : CLK_621_TRUE @ 0XF80001C4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CLK_621_TRUE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>CLK_621_TRUE @ 0XF80001C4</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-<li><p>Register : APER_CLK_CTRL @ 0XF800012C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DMA_CPU_2XCLKACT</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >USB0_CPU_1XCLKACT</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >USB1_CPU_1XCLKACT</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">1</td><td class="hex">8</td></tr>
-<tr><td >GEM0_CPU_1XCLKACT</td><td class="hex">6:6</td><td class="hex">40</td><td class="hex">1</td><td class="hex">40</td></tr>
-<tr><td >GEM1_CPU_1XCLKACT</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >SDI0_CPU_1XCLKACT</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">1</td><td class="hex">400</td></tr>
-<tr><td >SDI1_CPU_1XCLKACT</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >SPI0_CPU_1XCLKACT</td><td class="hex">14:14</td><td class="hex">4000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >SPI1_CPU_1XCLKACT</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CAN0_CPU_1XCLKACT</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CAN1_CPU_1XCLKACT</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >I2C0_CPU_1XCLKACT</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">1</td><td class="hex">40000</td></tr>
-<tr><td >I2C1_CPU_1XCLKACT</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td >UART0_CPU_1XCLKACT</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td >UART1_CPU_1XCLKACT</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">1</td><td class="hex">200000</td></tr>
-<tr><td >GPIO_CPU_1XCLKACT</td><td class="hex">22:22</td><td class="hex">400000</td><td class="hex">1</td><td class="hex">400000</td></tr>
-<tr><td >LQSPI_CPU_1XCLKACT</td><td class="hex">23:23</td><td class="hex">800000</td><td class="hex">1</td><td class="hex">800000</td></tr>
-<tr><td >SMC_CPU_1XCLKACT</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">1</td><td class="hex">1000000</td></tr>
-<tr><td><b>APER_CLK_CTRL @ 0XF800012C</td><td></td><td class="hex"><b>1ffcccd</b></td><td></td><td class="hex"><b>1fc044d</b></td></tr></table>
-</li>
-</ul>
-<h2>THIS SHOULD BE BLANK</h2>
-<ul>
-<p>THIS SHOULD BE BLANK</p>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_ddr_init_data_3_0">ps7_ddr_init_data_3_0</a></h1>
-<ul>
-<h2>DDR INITIALIZATION</h2>
-<ul>
-<p>DDR INITIALIZATION</p>
-<h2>LOCK DDR</h2>
-<ul>
-<p>LOCK DDR</p>
-<li><p>Register : ddrc_ctrl @ 0XF8006000</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_soft_rstb</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_powerdown_en</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_data_bus_width</td><td class="hex">3:2</td><td class="hex">c</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_burst8_refresh</td><td class="hex">6:4</td><td class="hex">70</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rdwr_idle_gap</td><td class="hex">13:7</td><td class="hex">3f80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >reg_ddrc_dis_rd_bypass</td><td class="hex">14:14</td><td class="hex">4000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_act_bypass</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_auto_refresh</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ddrc_ctrl @ 0XF8006000</td><td></td><td class="hex"><b>1ffff</b></td><td></td><td class="hex"><b>80</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : Two_rank_cfg @ 0XF8006004</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_t_rfc_nom_x32</td><td class="hex">11:0</td><td class="hex">fff</td><td class="hex">7f</td><td class="hex">7f</td></tr>
-<tr><td >reserved_reg_ddrc_active_ranks</td><td class="hex">13:12</td><td class="hex">3000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >reg_ddrc_addrmap_cs_bit0</td><td class="hex">18:14</td><td class="hex">7c000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>Two_rank_cfg @ 0XF8006004</td><td></td><td class="hex"><b>7ffff</b></td><td></td><td class="hex"><b>107f</b></td></tr></table>
-</li>
-<li><p>Register : HPR_reg @ 0XF8006008</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_hpr_min_non_critical_x32</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">f</td><td class="hex">f</td></tr>
-<tr><td >reg_ddrc_hpr_max_starve_x32</td><td class="hex">21:11</td><td class="hex">3ff800</td><td class="hex">f</td><td class="hex">7800</td></tr>
-<tr><td >reg_ddrc_hpr_xact_run_length</td><td class="hex">25:22</td><td class="hex">3c00000</td><td class="hex">f</td><td class="hex">3c00000</td></tr>
-<tr><td><b>HPR_reg @ 0XF8006008</td><td></td><td class="hex"><b>3ffffff</b></td><td></td><td class="hex"><b>3c0780f</b></td></tr></table>
-</li>
-<li><p>Register : LPR_reg @ 0XF800600C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_lpr_min_non_critical_x32</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_ddrc_lpr_max_starve_x32</td><td class="hex">21:11</td><td class="hex">3ff800</td><td class="hex">2</td><td class="hex">1000</td></tr>
-<tr><td >reg_ddrc_lpr_xact_run_length</td><td class="hex">25:22</td><td class="hex">3c00000</td><td class="hex">8</td><td class="hex">2000000</td></tr>
-<tr><td><b>LPR_reg @ 0XF800600C</td><td></td><td class="hex"><b>3ffffff</b></td><td></td><td class="hex"><b>2001001</b></td></tr></table>
-</li>
-<li><p>Register : WR_reg @ 0XF8006010</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_w_min_non_critical_x32</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_ddrc_w_xact_run_length</td><td class="hex">14:11</td><td class="hex">7800</td><td class="hex">8</td><td class="hex">4000</td></tr>
-<tr><td >reg_ddrc_w_max_starve_x32</td><td class="hex">25:15</td><td class="hex">3ff8000</td><td class="hex">2</td><td class="hex">10000</td></tr>
-<tr><td><b>WR_reg @ 0XF8006010</td><td></td><td class="hex"><b>3ffffff</b></td><td></td><td class="hex"><b>14001</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg0 @ 0XF8006014</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_t_rc</td><td class="hex">5:0</td><td class="hex">3f</td><td class="hex">1a</td><td class="hex">1a</td></tr>
-<tr><td >reg_ddrc_t_rfc_min</td><td class="hex">13:6</td><td class="hex">3fc0</td><td class="hex">54</td><td class="hex">1500</td></tr>
-<tr><td >reg_ddrc_post_selfref_gap_x32</td><td class="hex">20:14</td><td class="hex">1fc000</td><td class="hex">10</td><td class="hex">40000</td></tr>
-<tr><td><b>DRAM_param_reg0 @ 0XF8006014</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>4151a</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg1 @ 0XF8006018</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_wr2pre</td><td class="hex">4:0</td><td class="hex">1f</td><td class="hex">12</td><td class="hex">12</td></tr>
-<tr><td >reg_ddrc_powerdown_to_x32</td><td class="hex">9:5</td><td class="hex">3e0</td><td class="hex">6</td><td class="hex">c0</td></tr>
-<tr><td >reg_ddrc_t_faw</td><td class="hex">15:10</td><td class="hex">fc00</td><td class="hex">15</td><td class="hex">5400</td></tr>
-<tr><td >reg_ddrc_t_ras_max</td><td class="hex">21:16</td><td class="hex">3f0000</td><td class="hex">23</td><td class="hex">230000</td></tr>
-<tr><td >reg_ddrc_t_ras_min</td><td class="hex">26:22</td><td class="hex">7c00000</td><td class="hex">13</td><td class="hex">4c00000</td></tr>
-<tr><td >reg_ddrc_t_cke</td><td class="hex">31:28</td><td class="hex">f0000000</td><td class="hex">4</td><td class="hex">40000000</td></tr>
-<tr><td><b>DRAM_param_reg1 @ 0XF8006018</td><td></td><td class="hex"><b>f7ffffff</b></td><td></td><td class="hex"><b>44e354d2</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg2 @ 0XF800601C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_write_latency</td><td class="hex">4:0</td><td class="hex">1f</td><td class="hex">5</td><td class="hex">5</td></tr>
-<tr><td >reg_ddrc_rd2wr</td><td class="hex">9:5</td><td class="hex">3e0</td><td class="hex">7</td><td class="hex">e0</td></tr>
-<tr><td >reg_ddrc_wr2rd</td><td class="hex">14:10</td><td class="hex">7c00</td><td class="hex">e</td><td class="hex">3800</td></tr>
-<tr><td >reg_ddrc_t_xp</td><td class="hex">19:15</td><td class="hex">f8000</td><td class="hex">4</td><td class="hex">20000</td></tr>
-<tr><td >reg_ddrc_pad_pd</td><td class="hex">22:20</td><td class="hex">700000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rd2pre</td><td class="hex">27:23</td><td class="hex">f800000</td><td class="hex">4</td><td class="hex">2000000</td></tr>
-<tr><td >reg_ddrc_t_rcd</td><td class="hex">31:28</td><td class="hex">f0000000</td><td class="hex">7</td><td class="hex">70000000</td></tr>
-<tr><td><b>DRAM_param_reg2 @ 0XF800601C</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>720238e5</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg3 @ 0XF8006020</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_t_ccd</td><td class="hex">4:2</td><td class="hex">1c</td><td class="hex">4</td><td class="hex">10</td></tr>
-<tr><td >reg_ddrc_t_rrd</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">6</td><td class="hex">c0</td></tr>
-<tr><td >reg_ddrc_refresh_margin</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >reg_ddrc_t_rp</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">7</td><td class="hex">7000</td></tr>
-<tr><td >reg_ddrc_refresh_to_x32</td><td class="hex">20:16</td><td class="hex">1f0000</td><td class="hex">8</td><td class="hex">80000</td></tr>
-<tr><td >reg_ddrc_mobile</td><td class="hex">22:22</td><td class="hex">400000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_en_dfi_dram_clk_disable</td><td class="hex">23:23</td><td class="hex">800000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_read_latency</td><td class="hex">28:24</td><td class="hex">1f000000</td><td class="hex">7</td><td class="hex">7000000</td></tr>
-<tr><td >reg_phy_mode_ddr1_ddr2</td><td class="hex">29:29</td><td class="hex">20000000</td><td class="hex">1</td><td class="hex">20000000</td></tr>
-<tr><td >reg_ddrc_dis_pad_pd</td><td class="hex">30:30</td><td class="hex">40000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_param_reg3 @ 0XF8006020</td><td></td><td class="hex"><b>7fdffffc</b></td><td></td><td class="hex"><b>270872d0</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_param_reg4 @ 0XF8006024</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_en_2t_timing_mode</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_prefer_write</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr_wr</td><td class="hex">6:6</td><td class="hex">40</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr_addr</td><td class="hex">8:7</td><td class="hex">180</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr_data</td><td class="hex">24:9</td><td class="hex">1fffe00</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >ddrc_reg_mr_wr_busy</td><td class="hex">25:25</td><td class="hex">2000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr_type</td><td class="hex">26:26</td><td class="hex">4000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr_rdata_valid</td><td class="hex">27:27</td><td class="hex">8000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_param_reg4 @ 0XF8006024</td><td></td><td class="hex"><b>fffffc3</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_init_param @ 0XF8006028</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_final_wait_x32</td><td class="hex">6:0</td><td class="hex">7f</td><td class="hex">7</td><td class="hex">7</td></tr>
-<tr><td >reg_ddrc_pre_ocd_x32</td><td class="hex">10:7</td><td class="hex">780</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_t_mrd</td><td class="hex">13:11</td><td class="hex">3800</td><td class="hex">4</td><td class="hex">2000</td></tr>
-<tr><td><b>DRAM_init_param @ 0XF8006028</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2007</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_EMR_reg @ 0XF800602C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_emr2</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">8</td><td class="hex">8</td></tr>
-<tr><td >reg_ddrc_emr3</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_EMR_reg @ 0XF800602C</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>8</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_EMR_MR_reg @ 0XF8006030</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_mr</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">930</td><td class="hex">930</td></tr>
-<tr><td >reg_ddrc_emr</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">4</td><td class="hex">40000</td></tr>
-<tr><td><b>DRAM_EMR_MR_reg @ 0XF8006030</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>40930</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_burst8_rdwr @ 0XF8006034</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_burst_rdwr</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">4</td><td class="hex">4</td></tr>
-<tr><td >reg_ddrc_pre_cke_x1024</td><td class="hex">13:4</td><td class="hex">3ff0</td><td class="hex">101</td><td class="hex">1010</td></tr>
-<tr><td >reg_ddrc_post_cke_x1024</td><td class="hex">25:16</td><td class="hex">3ff0000</td><td class="hex">1</td><td class="hex">10000</td></tr>
-<tr><td >reg_ddrc_burstchop</td><td class="hex">28:28</td><td class="hex">10000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_burst8_rdwr @ 0XF8006034</td><td></td><td class="hex"><b>13ff3fff</b></td><td></td><td class="hex"><b>11014</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_disable_DQ @ 0XF8006038</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_force_low_pri_n</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_dq</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_disable_DQ @ 0XF8006038</td><td></td><td class="hex"><b>3</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_addr_map_bank @ 0XF800603C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_addrmap_bank_b0</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">7</td><td class="hex">7</td></tr>
-<tr><td >reg_ddrc_addrmap_bank_b1</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">7</td><td class="hex">70</td></tr>
-<tr><td >reg_ddrc_addrmap_bank_b2</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">7</td><td class="hex">700</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b5</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b6</td><td class="hex">19:16</td><td class="hex">f0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DRAM_addr_map_bank @ 0XF800603C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>777</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_addr_map_col @ 0XF8006040</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_addrmap_col_b2</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b3</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b4</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b7</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b8</td><td class="hex">19:16</td><td class="hex">f0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b9</td><td class="hex">23:20</td><td class="hex">f00000</td><td class="hex">f</td><td class="hex">f00000</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b10</td><td class="hex">27:24</td><td class="hex">f000000</td><td class="hex">f</td><td class="hex">f000000</td></tr>
-<tr><td >reg_ddrc_addrmap_col_b11</td><td class="hex">31:28</td><td class="hex">f0000000</td><td class="hex">f</td><td class="hex">f0000000</td></tr>
-<tr><td><b>DRAM_addr_map_col @ 0XF8006040</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>fff00000</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_addr_map_row @ 0XF8006044</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_addrmap_row_b0</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">6</td><td class="hex">6</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b1</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">6</td><td class="hex">60</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b2_11</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">6</td><td class="hex">600</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b12</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">6</td><td class="hex">6000</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b13</td><td class="hex">19:16</td><td class="hex">f0000</td><td class="hex">6</td><td class="hex">60000</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b14</td><td class="hex">23:20</td><td class="hex">f00000</td><td class="hex">f</td><td class="hex">f00000</td></tr>
-<tr><td >reg_ddrc_addrmap_row_b15</td><td class="hex">27:24</td><td class="hex">f000000</td><td class="hex">f</td><td class="hex">f000000</td></tr>
-<tr><td><b>DRAM_addr_map_row @ 0XF8006044</td><td></td><td class="hex"><b>fffffff</b></td><td></td><td class="hex"><b>ff66666</b></td></tr></table>
-</li>
-<li><p>Register : DRAM_ODT_reg @ 0XF8006048</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_local_odt</td><td class="hex">13:12</td><td class="hex">3000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_local_odt</td><td class="hex">15:14</td><td class="hex">c000</td><td class="hex">3</td><td class="hex">c000</td></tr>
-<tr><td >reg_phy_idle_local_odt</td><td class="hex">17:16</td><td class="hex">30000</td><td class="hex">3</td><td class="hex">30000</td></tr>
-<tr><td><b>DRAM_ODT_reg @ 0XF8006048</td><td></td><td class="hex"><b>3f000</b></td><td></td><td class="hex"><b>3c000</b></td></tr></table>
-</li>
-<li><p>Register : phy_cmd_timeout_rddata_cpt @ 0XF8006050</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_cmd_to_data</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_cmd_to_data</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rdc_we_to_re_delay</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">8</td><td class="hex">800</td></tr>
-<tr><td >reg_phy_rdc_fifo_rst_disable</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_use_fixed_re</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">1</td><td class="hex">10000</td></tr>
-<tr><td >reg_phy_rdc_fifo_rst_err_cnt_clr</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dis_phy_ctrl_rstn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_clk_stall_level</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_num_of_dq0</td><td class="hex">27:24</td><td class="hex">f000000</td><td class="hex">7</td><td class="hex">7000000</td></tr>
-<tr><td >reg_phy_wrlvl_num_of_dq0</td><td class="hex">31:28</td><td class="hex">f0000000</td><td class="hex">7</td><td class="hex">70000000</td></tr>
-<tr><td><b>phy_cmd_timeout_rddata_cpt @ 0XF8006050</td><td></td><td class="hex"><b>ff0f8fff</b></td><td></td><td class="hex"><b>77010800</b></td></tr></table>
-</li>
-<li><p>Register : DLL_calib @ 0XF8006058</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_dis_dll_calib</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DLL_calib @ 0XF8006058</td><td></td><td class="hex"><b>10000</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : ODT_delay_hold @ 0XF800605C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_rd_odt_delay</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">3</td><td class="hex">3</td></tr>
-<tr><td >reg_ddrc_wr_odt_delay</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rd_odt_hold</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_wr_odt_hold</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">5</td><td class="hex">5000</td></tr>
-<tr><td><b>ODT_delay_hold @ 0XF800605C</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>5003</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg1 @ 0XF8006060</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_pageclose</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_lpr_num_entries</td><td class="hex">6:1</td><td class="hex">7e</td><td class="hex">1f</td><td class="hex">3e</td></tr>
-<tr><td >reg_ddrc_auto_pre_en</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_refresh_update_level</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_wc</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_collision_page_opt</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_selfref_en</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ctrl_reg1 @ 0XF8006060</td><td></td><td class="hex"><b>17ff</b></td><td></td><td class="hex"><b>3e</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg2 @ 0XF8006064</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_go2critical_hysteresis</td><td class="hex">12:5</td><td class="hex">1fe0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_go2critical_en</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">1</td><td class="hex">20000</td></tr>
-<tr><td><b>ctrl_reg2 @ 0XF8006064</td><td></td><td class="hex"><b>21fe0</b></td><td></td><td class="hex"><b>20000</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg3 @ 0XF8006068</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_wrlvl_ww</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">41</td><td class="hex">41</td></tr>
-<tr><td >reg_ddrc_rdlvl_rr</td><td class="hex">15:8</td><td class="hex">ff00</td><td class="hex">41</td><td class="hex">4100</td></tr>
-<tr><td >reg_ddrc_dfi_t_wlmrd</td><td class="hex">25:16</td><td class="hex">3ff0000</td><td class="hex">28</td><td class="hex">280000</td></tr>
-<tr><td><b>ctrl_reg3 @ 0XF8006068</td><td></td><td class="hex"><b>3ffffff</b></td><td></td><td class="hex"><b>284141</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg4 @ 0XF800606C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >dfi_t_ctrlupd_interval_min_x1024</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">10</td><td class="hex">10</td></tr>
-<tr><td >dfi_t_ctrlupd_interval_max_x1024</td><td class="hex">15:8</td><td class="hex">ff00</td><td class="hex">16</td><td class="hex">1600</td></tr>
-<tr><td><b>ctrl_reg4 @ 0XF800606C</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>1610</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg5 @ 0XF8006078</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_dfi_t_ctrl_delay</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_ddrc_dfi_t_dram_clk_disable</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >reg_ddrc_dfi_t_dram_clk_enable</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >reg_ddrc_t_cksre</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">6</td><td class="hex">6000</td></tr>
-<tr><td >reg_ddrc_t_cksrx</td><td class="hex">19:16</td><td class="hex">f0000</td><td class="hex">6</td><td class="hex">60000</td></tr>
-<tr><td >reg_ddrc_t_ckesr</td><td class="hex">25:20</td><td class="hex">3f00000</td><td class="hex">4</td><td class="hex">400000</td></tr>
-<tr><td><b>ctrl_reg5 @ 0XF8006078</td><td></td><td class="hex"><b>3ffffff</b></td><td></td><td class="hex"><b>466111</b></td></tr></table>
-</li>
-<li><p>Register : ctrl_reg6 @ 0XF800607C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_t_ckpde</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">2</td><td class="hex">2</td></tr>
-<tr><td >reg_ddrc_t_ckpdx</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">2</td><td class="hex">20</td></tr>
-<tr><td >reg_ddrc_t_ckdpde</td><td class="hex">11:8</td><td class="hex">f00</td><td class="hex">2</td><td class="hex">200</td></tr>
-<tr><td >reg_ddrc_t_ckdpdx</td><td class="hex">15:12</td><td class="hex">f000</td><td class="hex">2</td><td class="hex">2000</td></tr>
-<tr><td >reg_ddrc_t_ckcsx</td><td class="hex">19:16</td><td class="hex">f0000</td><td class="hex">3</td><td class="hex">30000</td></tr>
-<tr><td><b>ctrl_reg6 @ 0XF800607C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>32222</b></td></tr></table>
-</li>
-<li><p>Register : CHE_T_ZQ @ 0XF80060A4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_dis_auto_zq</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_ddr3</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >reg_ddrc_t_mod</td><td class="hex">11:2</td><td class="hex">ffc</td><td class="hex">200</td><td class="hex">800</td></tr>
-<tr><td >reg_ddrc_t_zq_long_nop</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">200</td><td class="hex">200000</td></tr>
-<tr><td >reg_ddrc_t_zq_short_nop</td><td class="hex">31:22</td><td class="hex">ffc00000</td><td class="hex">40</td><td class="hex">10000000</td></tr>
-<tr><td><b>CHE_T_ZQ @ 0XF80060A4</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>10200802</b></td></tr></table>
-</li>
-<li><p>Register : CHE_T_ZQ_Short_Interval_Reg @ 0XF80060A8</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >t_zq_short_interval_x1024</td><td class="hex">19:0</td><td class="hex">fffff</td><td class="hex">c845</td><td class="hex">c845</td></tr>
-<tr><td >dram_rstn_x1024</td><td class="hex">27:20</td><td class="hex">ff00000</td><td class="hex">67</td><td class="hex">6700000</td></tr>
-<tr><td><b>CHE_T_ZQ_Short_Interval_Reg @ 0XF80060A8</td><td></td><td class="hex"><b>fffffff</b></td><td></td><td class="hex"><b>670c845</b></td></tr></table>
-</li>
-<li><p>Register : deep_pwrdwn_reg @ 0XF80060AC</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >deeppowerdown_en</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >deeppowerdown_to_x1024</td><td class="hex">8:1</td><td class="hex">1fe</td><td class="hex">ff</td><td class="hex">1fe</td></tr>
-<tr><td><b>deep_pwrdwn_reg @ 0XF80060AC</td><td></td><td class="hex"><b>1ff</b></td><td></td><td class="hex"><b>1fe</b></td></tr></table>
-</li>
-<li><p>Register : reg_2c @ 0XF80060B0</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >dfi_wrlvl_max_x1024</td><td class="hex">11:0</td><td class="hex">fff</td><td class="hex">fff</td><td class="hex">fff</td></tr>
-<tr><td >dfi_rdlvl_max_x1024</td><td class="hex">23:12</td><td class="hex">fff000</td><td class="hex">fff</td><td class="hex">fff000</td></tr>
-<tr><td >ddrc_reg_twrlvl_max_error</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >ddrc_reg_trdlvl_max_error</td><td class="hex">25:25</td><td class="hex">2000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dfi_wr_level_en</td><td class="hex">26:26</td><td class="hex">4000000</td><td class="hex">1</td><td class="hex">4000000</td></tr>
-<tr><td >reg_ddrc_dfi_rd_dqs_gate_level</td><td class="hex">27:27</td><td class="hex">8000000</td><td class="hex">1</td><td class="hex">8000000</td></tr>
-<tr><td >reg_ddrc_dfi_rd_data_eye_train</td><td class="hex">28:28</td><td class="hex">10000000</td><td class="hex">1</td><td class="hex">10000000</td></tr>
-<tr><td><b>reg_2c @ 0XF80060B0</td><td></td><td class="hex"><b>1fffffff</b></td><td></td><td class="hex"><b>1cffffff</b></td></tr></table>
-</li>
-<li><p>Register : reg_2d @ 0XF80060B4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_skip_ocd</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td><b>reg_2d @ 0XF80060B4</td><td></td><td class="hex"><b>200</b></td><td></td><td class="hex"><b>200</b></td></tr></table>
-</li>
-<li><p>Register : dfi_timing @ 0XF80060B8</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_dfi_t_rddata_en</td><td class="hex">4:0</td><td class="hex">1f</td><td class="hex">6</td><td class="hex">6</td></tr>
-<tr><td >reg_ddrc_dfi_t_ctrlup_min</td><td class="hex">14:5</td><td class="hex">7fe0</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >reg_ddrc_dfi_t_ctrlup_max</td><td class="hex">24:15</td><td class="hex">1ff8000</td><td class="hex">40</td><td class="hex">200000</td></tr>
-<tr><td><b>dfi_timing @ 0XF80060B8</td><td></td><td class="hex"><b>1ffffff</b></td><td></td><td class="hex"><b>200066</b></td></tr></table>
-</li>
-<h2>RESET ECC ERROR</h2>
-<ul>
-<p>RESET ECC ERROR</p>
-<li><p>Register : CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >Clear_Uncorrectable_DRAM_ECC_error</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >Clear_Correctable_DRAM_ECC_error</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td><b>CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4</td><td></td><td class="hex"><b>3</b></td><td></td><td class="hex"><b>3</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >Clear_Uncorrectable_DRAM_ECC_error</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Clear_Correctable_DRAM_ECC_error</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CHE_ECC_CONTROL_REG_OFFSET @ 0XF80060C4</td><td></td><td class="hex"><b>3</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : CHE_CORR_ECC_LOG_REG_OFFSET @ 0XF80060C8</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CORR_ECC_LOG_VALID</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >ECC_CORRECTED_BIT_NUM</td><td class="hex">7:1</td><td class="hex">fe</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CHE_CORR_ECC_LOG_REG_OFFSET @ 0XF80060C8</td><td></td><td class="hex"><b>ff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : CHE_UNCORR_ECC_LOG_REG_OFFSET @ 0XF80060DC</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNCORR_ECC_LOG_VALID</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CHE_UNCORR_ECC_LOG_REG_OFFSET @ 0XF80060DC</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : CHE_ECC_STATS_REG_OFFSET @ 0XF80060F0</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >STAT_NUM_CORR_ERR</td><td class="hex">15:8</td><td class="hex">ff00</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >STAT_NUM_UNCORR_ERR</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CHE_ECC_STATS_REG_OFFSET @ 0XF80060F0</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : ECC_scrub @ 0XF80060F4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_ecc_mode</td><td class="hex">2:0</td><td class="hex">7</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_scrub</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">1</td><td class="hex">8</td></tr>
-<tr><td><b>ECC_scrub @ 0XF80060F4</td><td></td><td class="hex"><b>f</b></td><td></td><td class="hex"><b>8</b></td></tr></table>
-</li>
-<li><p>Register : phy_rcvr_enable @ 0XF8006114</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_dif_on</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dif_off</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rcvr_enable @ 0XF8006114</td><td></td><td class="hex"><b>ff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : PHY_Config @ 0XF8006118</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_data_slice_in_use</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_phy_rdlvl_inc_mode</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_inc_mode</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wrlvl_inc_mode</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_shift_dq</td><td class="hex">14:6</td><td class="hex">7fc0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_err_clr</td><td class="hex">23:15</td><td class="hex">ff8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq_offset</td><td class="hex">30:24</td><td class="hex">7f000000</td><td class="hex">40</td><td class="hex">40000000</td></tr>
-<tr><td><b>PHY_Config @ 0XF8006118</td><td></td><td class="hex"><b>7fffffcf</b></td><td></td><td class="hex"><b>40000001</b></td></tr></table>
-</li>
-<li><p>Register : PHY_Config @ 0XF800611C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_data_slice_in_use</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_phy_rdlvl_inc_mode</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_inc_mode</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wrlvl_inc_mode</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_shift_dq</td><td class="hex">14:6</td><td class="hex">7fc0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_err_clr</td><td class="hex">23:15</td><td class="hex">ff8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq_offset</td><td class="hex">30:24</td><td class="hex">7f000000</td><td class="hex">40</td><td class="hex">40000000</td></tr>
-<tr><td><b>PHY_Config @ 0XF800611C</td><td></td><td class="hex"><b>7fffffcf</b></td><td></td><td class="hex"><b>40000001</b></td></tr></table>
-</li>
-<li><p>Register : PHY_Config @ 0XF8006120</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_data_slice_in_use</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_phy_rdlvl_inc_mode</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_inc_mode</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wrlvl_inc_mode</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_shift_dq</td><td class="hex">14:6</td><td class="hex">7fc0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_err_clr</td><td class="hex">23:15</td><td class="hex">ff8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq_offset</td><td class="hex">30:24</td><td class="hex">7f000000</td><td class="hex">40</td><td class="hex">40000000</td></tr>
-<tr><td><b>PHY_Config @ 0XF8006120</td><td></td><td class="hex"><b>7fffffcf</b></td><td></td><td class="hex"><b>40000001</b></td></tr></table>
-</li>
-<li><p>Register : PHY_Config @ 0XF8006124</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_data_slice_in_use</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_phy_rdlvl_inc_mode</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_inc_mode</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wrlvl_inc_mode</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_shift_dq</td><td class="hex">14:6</td><td class="hex">7fc0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_err_clr</td><td class="hex">23:15</td><td class="hex">ff8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_dq_offset</td><td class="hex">30:24</td><td class="hex">7f000000</td><td class="hex">40</td><td class="hex">40000000</td></tr>
-<tr><td><b>PHY_Config @ 0XF8006124</td><td></td><td class="hex"><b>7fffffcf</b></td><td></td><td class="hex"><b>40000001</b></td></tr></table>
-</li>
-<li><p>Register : phy_init_ratio @ 0XF800612C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wrlvl_init_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_init_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">8f</td><td class="hex">23c00</td></tr>
-<tr><td><b>phy_init_ratio @ 0XF800612C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>23c00</b></td></tr></table>
-</li>
-<li><p>Register : phy_init_ratio @ 0XF8006130</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wrlvl_init_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_init_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">8a</td><td class="hex">22800</td></tr>
-<tr><td><b>phy_init_ratio @ 0XF8006130</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>22800</b></td></tr></table>
-</li>
-<li><p>Register : phy_init_ratio @ 0XF8006134</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wrlvl_init_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_init_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">8b</td><td class="hex">22c00</td></tr>
-<tr><td><b>phy_init_ratio @ 0XF8006134</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>22c00</b></td></tr></table>
-</li>
-<li><p>Register : phy_init_ratio @ 0XF8006138</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wrlvl_init_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_gatelvl_init_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">92</td><td class="hex">24800</td></tr>
-<tr><td><b>phy_init_ratio @ 0XF8006138</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>24800</b></td></tr></table>
-</li>
-<li><p>Register : phy_rd_dqs_cfg @ 0XF8006140</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">35</td><td class="hex">35</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rd_dqs_cfg @ 0XF8006140</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>35</b></td></tr></table>
-</li>
-<li><p>Register : phy_rd_dqs_cfg @ 0XF8006144</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">35</td><td class="hex">35</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rd_dqs_cfg @ 0XF8006144</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>35</b></td></tr></table>
-</li>
-<li><p>Register : phy_rd_dqs_cfg @ 0XF8006148</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">35</td><td class="hex">35</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rd_dqs_cfg @ 0XF8006148</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>35</b></td></tr></table>
-</li>
-<li><p>Register : phy_rd_dqs_cfg @ 0XF800614C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_rd_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">35</td><td class="hex">35</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_rd_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_rd_dqs_cfg @ 0XF800614C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>35</b></td></tr></table>
-</li>
-<li><p>Register : phy_wr_dqs_cfg @ 0XF8006154</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">77</td><td class="hex">77</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_wr_dqs_cfg @ 0XF8006154</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>77</b></td></tr></table>
-</li>
-<li><p>Register : phy_wr_dqs_cfg @ 0XF8006158</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">7c</td><td class="hex">7c</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_wr_dqs_cfg @ 0XF8006158</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>7c</b></td></tr></table>
-</li>
-<li><p>Register : phy_wr_dqs_cfg @ 0XF800615C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">7c</td><td class="hex">7c</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_wr_dqs_cfg @ 0XF800615C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>7c</b></td></tr></table>
-</li>
-<li><p>Register : phy_wr_dqs_cfg @ 0XF8006160</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_dqs_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">75</td><td class="hex">75</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_dqs_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_wr_dqs_cfg @ 0XF8006160</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>75</b></td></tr></table>
-</li>
-<li><p>Register : phy_we_cfg @ 0XF8006168</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_fifo_we_slave_ratio</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">e4</td><td class="hex">e4</td></tr>
-<tr><td >reg_phy_fifo_we_in_force</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_fifo_we_in_delay</td><td class="hex">20:12</td><td class="hex">1ff000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_we_cfg @ 0XF8006168</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>e4</b></td></tr></table>
-</li>
-<li><p>Register : phy_we_cfg @ 0XF800616C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_fifo_we_slave_ratio</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">df</td><td class="hex">df</td></tr>
-<tr><td >reg_phy_fifo_we_in_force</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_fifo_we_in_delay</td><td class="hex">20:12</td><td class="hex">1ff000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_we_cfg @ 0XF800616C</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>df</b></td></tr></table>
-</li>
-<li><p>Register : phy_we_cfg @ 0XF8006170</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_fifo_we_slave_ratio</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">e0</td><td class="hex">e0</td></tr>
-<tr><td >reg_phy_fifo_we_in_force</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_fifo_we_in_delay</td><td class="hex">20:12</td><td class="hex">1ff000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_we_cfg @ 0XF8006170</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>e0</b></td></tr></table>
-</li>
-<li><p>Register : phy_we_cfg @ 0XF8006174</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_fifo_we_slave_ratio</td><td class="hex">10:0</td><td class="hex">7ff</td><td class="hex">e7</td><td class="hex">e7</td></tr>
-<tr><td >reg_phy_fifo_we_in_force</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_fifo_we_in_delay</td><td class="hex">20:12</td><td class="hex">1ff000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>phy_we_cfg @ 0XF8006174</td><td></td><td class="hex"><b>1fffff</b></td><td></td><td class="hex"><b>e7</b></td></tr></table>
-</li>
-<li><p>Register : wr_data_slv @ 0XF800617C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_data_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">b7</td><td class="hex">b7</td></tr>
-<tr><td >reg_phy_wr_data_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_data_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>wr_data_slv @ 0XF800617C</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>b7</b></td></tr></table>
-</li>
-<li><p>Register : wr_data_slv @ 0XF8006180</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_data_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">bc</td><td class="hex">bc</td></tr>
-<tr><td >reg_phy_wr_data_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_data_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>wr_data_slv @ 0XF8006180</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>bc</b></td></tr></table>
-</li>
-<li><p>Register : wr_data_slv @ 0XF8006184</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_data_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">bc</td><td class="hex">bc</td></tr>
-<tr><td >reg_phy_wr_data_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_data_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>wr_data_slv @ 0XF8006184</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>bc</b></td></tr></table>
-</li>
-<li><p>Register : wr_data_slv @ 0XF8006188</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_data_slave_ratio</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">b5</td><td class="hex">b5</td></tr>
-<tr><td >reg_phy_wr_data_slave_force</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_wr_data_slave_delay</td><td class="hex">19:11</td><td class="hex">ff800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>wr_data_slv @ 0XF8006188</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>b5</b></td></tr></table>
-</li>
-<li><p>Register : reg_64 @ 0XF8006190</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_bl2</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_at_spd_atpg</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_enable</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_force_err</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_bist_mode</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_invert_clkout</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >reg_phy_sel_logic</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_ctrl_slave_ratio</td><td class="hex">19:10</td><td class="hex">ffc00</td><td class="hex">100</td><td class="hex">40000</td></tr>
-<tr><td >reg_phy_ctrl_slave_force</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_ctrl_slave_delay</td><td class="hex">27:21</td><td class="hex">fe00000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_lpddr</td><td class="hex">29:29</td><td class="hex">20000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_cmd_latency</td><td class="hex">30:30</td><td class="hex">40000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>reg_64 @ 0XF8006190</td><td></td><td class="hex"><b>6ffffefe</b></td><td></td><td class="hex"><b>40080</b></td></tr></table>
-</li>
-<li><p>Register : reg_65 @ 0XF8006194</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_phy_wr_rl_delay</td><td class="hex">4:0</td><td class="hex">1f</td><td class="hex">2</td><td class="hex">2</td></tr>
-<tr><td >reg_phy_rd_rl_delay</td><td class="hex">9:5</td><td class="hex">3e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >reg_phy_dll_lock_diff</td><td class="hex">13:10</td><td class="hex">3c00</td><td class="hex">f</td><td class="hex">3c00</td></tr>
-<tr><td >reg_phy_use_wr_level</td><td class="hex">14:14</td><td class="hex">4000</td><td class="hex">1</td><td class="hex">4000</td></tr>
-<tr><td >reg_phy_use_rd_dqs_gate_level</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">1</td><td class="hex">8000</td></tr>
-<tr><td >reg_phy_use_rd_data_eye_level</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">1</td><td class="hex">10000</td></tr>
-<tr><td >reg_phy_dis_calib_rst</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_phy_ctrl_slave_delay</td><td class="hex">19:18</td><td class="hex">c0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>reg_65 @ 0XF8006194</td><td></td><td class="hex"><b>fffff</b></td><td></td><td class="hex"><b>1fc82</b></td></tr></table>
-</li>
-<li><p>Register : page_mask @ 0XF8006204</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_page_addr_mask</td><td class="hex">31:0</td><td class="hex">ffffffff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>page_mask @ 0XF8006204</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_wr_port @ 0XF8006208</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_wr_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_wr_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_wr_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_wr_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_wr_port @ 0XF8006208</td><td></td><td class="hex"><b>703ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_wr_port @ 0XF800620C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_wr_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_wr_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_wr_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_wr_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_wr_port @ 0XF800620C</td><td></td><td class="hex"><b>703ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_wr_port @ 0XF8006210</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_wr_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_wr_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_wr_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_wr_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_wr_port @ 0XF8006210</td><td></td><td class="hex"><b>703ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_wr_port @ 0XF8006214</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_wr_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_wr_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_wr_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_wr_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_wr_port @ 0XF8006214</td><td></td><td class="hex"><b>703ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_rd_port @ 0XF8006218</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_rd_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_rd_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_rd_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_rd_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_set_hpr_rd_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_rd_port @ 0XF8006218</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_rd_port @ 0XF800621C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_rd_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_rd_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_rd_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_rd_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_set_hpr_rd_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_rd_port @ 0XF800621C</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_rd_port @ 0XF8006220</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_rd_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_rd_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_rd_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_rd_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_set_hpr_rd_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_rd_port @ 0XF8006220</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : axi_priority_rd_port @ 0XF8006224</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_arb_pri_rd_portn</td><td class="hex">9:0</td><td class="hex">3ff</td><td class="hex">3ff</td><td class="hex">3ff</td></tr>
-<tr><td >reg_arb_disable_aging_rd_portn</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_disable_urgent_rd_portn</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_dis_page_match_rd_portn</td><td class="hex">18:18</td><td class="hex">40000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_arb_set_hpr_rd_portn</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>axi_priority_rd_port @ 0XF8006224</td><td></td><td class="hex"><b>f03ff</b></td><td></td><td class="hex"><b>3ff</b></td></tr></table>
-</li>
-<li><p>Register : lpddr_ctrl0 @ 0XF80062A8</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_lpddr2</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_derate_enable</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_mr4_margin</td><td class="hex">11:4</td><td class="hex">ff0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>lpddr_ctrl0 @ 0XF80062A8</td><td></td><td class="hex"><b>ff5</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : lpddr_ctrl1 @ 0XF80062AC</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_mr4_read_interval</td><td class="hex">31:0</td><td class="hex">ffffffff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>lpddr_ctrl1 @ 0XF80062AC</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-<li><p>Register : lpddr_ctrl2 @ 0XF80062B0</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_min_stable_clock_x1</td><td class="hex">3:0</td><td class="hex">f</td><td class="hex">5</td><td class="hex">5</td></tr>
-<tr><td >reg_ddrc_idle_after_reset_x32</td><td class="hex">11:4</td><td class="hex">ff0</td><td class="hex">12</td><td class="hex">120</td></tr>
-<tr><td >reg_ddrc_t_mrw</td><td class="hex">21:12</td><td class="hex">3ff000</td><td class="hex">5</td><td class="hex">5000</td></tr>
-<tr><td><b>lpddr_ctrl2 @ 0XF80062B0</td><td></td><td class="hex"><b>3fffff</b></td><td></td><td class="hex"><b>5125</b></td></tr></table>
-</li>
-<li><p>Register : lpddr_ctrl3 @ 0XF80062B4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_max_auto_init_x1024</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">a6</td><td class="hex">a6</td></tr>
-<tr><td >reg_ddrc_dev_zqinit_x32</td><td class="hex">17:8</td><td class="hex">3ff00</td><td class="hex">12</td><td class="hex">1200</td></tr>
-<tr><td><b>lpddr_ctrl3 @ 0XF80062B4</td><td></td><td class="hex"><b>3ffff</b></td><td></td><td class="hex"><b>12a6</b></td></tr></table>
-</li>
-<h2>POLL ON DCI STATUS</h2>
-<ul>
-<p>POLL ON DCI STATUS</p>
-<li><p>Register : DDRIOB_DCI_STATUS @ 0XF8000B74</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DONE</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>DDRIOB_DCI_STATUS @ 0XF8000B74</td><td></td><td class="hex"><b>2000</b></td><td></td><td class="hex"><b>2000</b></td></tr></table>
-</li>
-</ul>
-<h2>UNLOCK DDR</h2>
-<ul>
-<p>UNLOCK DDR</p>
-<li><p>Register : ddrc_ctrl @ 0XF8006000</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reg_ddrc_soft_rstb</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >reg_ddrc_powerdown_en</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_data_bus_width</td><td class="hex">3:2</td><td class="hex">c</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_burst8_refresh</td><td class="hex">6:4</td><td class="hex">70</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_rdwr_idle_gap</td><td class="hex">13:7</td><td class="hex">3f80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >reg_ddrc_dis_rd_bypass</td><td class="hex">14:14</td><td class="hex">4000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_act_bypass</td><td class="hex">15:15</td><td class="hex">8000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reg_ddrc_dis_auto_refresh</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>ddrc_ctrl @ 0XF8006000</td><td></td><td class="hex"><b>1ffff</b></td><td></td><td class="hex"><b>81</b></td></tr></table>
-</li>
-</ul>
-<h2>CHECK DDR STATUS</h2>
-<ul>
-<p>CHECK DDR STATUS</p>
-<li><p>Register : mode_sts_reg @ 0XF8006054</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >ddrc_reg_operating_mode</td><td class="hex">2:0</td><td class="hex">7</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>mode_sts_reg @ 0XF8006054</td><td></td><td class="hex"><b>7</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_mio_init_data_3_0">ps7_mio_init_data_3_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>OCM REMAPPING</h2>
-<ul>
-<p>OCM REMAPPING</p>
-<li><p>Register : GPIOB_CTRL @ 0XF8000B00</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >VREF_EN</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >VREF_SEL</td><td class="hex">6:4</td><td class="hex">70</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>GPIOB_CTRL @ 0XF8000B00</td><td></td><td class="hex"><b>71</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>DDRIOB SETTINGS</h2>
-<ul>
-<p>DDRIOB SETTINGS</p>
-<li><p>Register : DDRIOB_ADDR0 @ 0XF8000B40</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCI_UPDATE_B</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCI_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_ADDR0 @ 0XF8000B40</td><td></td><td class="hex"><b>ffe</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_ADDR1 @ 0XF8000B44</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCI_UPDATE_B</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCI_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_ADDR1 @ 0XF8000B44</td><td></td><td class="hex"><b>ffe</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DATA0 @ 0XF8000B48</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >DCI_UPDATE_B</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >DCI_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DATA0 @ 0XF8000B48</td><td></td><td class="hex"><b>ffe</b></td><td></td><td class="hex"><b>672</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DATA1 @ 0XF8000B4C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >DCI_UPDATE_B</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >DCI_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DATA1 @ 0XF8000B4C</td><td></td><td class="hex"><b>ffe</b></td><td></td><td class="hex"><b>672</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DIFF0 @ 0XF8000B50</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">2</td><td class="hex">4</td></tr>
-<tr><td >DCI_UPDATE_B</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >DCI_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DIFF0 @ 0XF8000B50</td><td></td><td class="hex"><b>ffe</b></td><td></td><td class="hex"><b>674</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DIFF1 @ 0XF8000B54</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">2</td><td class="hex">4</td></tr>
-<tr><td >DCI_UPDATE_B</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >DCI_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DIFF1 @ 0XF8000B54</td><td></td><td class="hex"><b>ffe</b></td><td></td><td class="hex"><b>674</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_CLOCK @ 0XF8000B58</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >INP_TYPE</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCI_UPDATE_B</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_EN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DCI_TYPE</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >OUTPUT_EN</td><td class="hex">10:9</td><td class="hex">600</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP_EN</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_CLOCK @ 0XF8000B58</td><td></td><td class="hex"><b>ffe</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DDR_CTRL @ 0XF8000B6C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >VREF_INT_EN</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >VREF_SEL</td><td class="hex">4:1</td><td class="hex">1e</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >VREF_EXT_EN</td><td class="hex">6:5</td><td class="hex">60</td><td class="hex">3</td><td class="hex">60</td></tr>
-<tr><td >REFIO_EN</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td><b>DDRIOB_DDR_CTRL @ 0XF8000B6C</td><td></td><td class="hex"><b>27f</b></td><td></td><td class="hex"><b>260</b></td></tr></table>
-</li>
-<h2>ASSERT RESET</h2>
-<ul>
-<p>ASSERT RESET</p>
-<li><p>Register : DDRIOB_DCI_CTRL @ 0XF8000B70</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>DDRIOB_DCI_CTRL @ 0XF8000B70</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>1</b></td></tr></table>
-</li>
-</ul>
-<h2>DEASSERT RESET</h2>
-<ul>
-<p>DEASSERT RESET</p>
-<li><p>Register : DDRIOB_DCI_CTRL @ 0XF8000B70</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DCI_CTRL @ 0XF8000B70</td><td></td><td class="hex"><b>1</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<li><p>Register : DDRIOB_DCI_CTRL @ 0XF8000B70</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >RESET</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >ENABLE</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >NREF_OPT1</td><td class="hex">7:6</td><td class="hex">c0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >NREF_OPT2</td><td class="hex">10:8</td><td class="hex">700</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >NREF_OPT4</td><td class="hex">13:11</td><td class="hex">3800</td><td class="hex">1</td><td class="hex">800</td></tr>
-<tr><td >PREF_OPT2</td><td class="hex">19:17</td><td class="hex">e0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >UPDATE_CONTROL</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>DDRIOB_DCI_CTRL @ 0XF8000B70</td><td></td><td class="hex"><b>1e3fc3</b></td><td></td><td class="hex"><b>803</b></td></tr></table>
-</li>
-</ul>
-<h2>MIO PROGRAMMING</h2>
-<ul>
-<p>MIO PROGRAMMING</p>
-<li><p>Register : MIO_PIN_00 @ 0XF8000700</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_00 @ 0XF8000700</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_01 @ 0XF8000704</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_01 @ 0XF8000704</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_02 @ 0XF8000708</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_02 @ 0XF8000708</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_03 @ 0XF800070C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_03 @ 0XF800070C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_04 @ 0XF8000710</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_04 @ 0XF8000710</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_05 @ 0XF8000714</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_05 @ 0XF8000714</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_06 @ 0XF8000718</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_06 @ 0XF8000718</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_07 @ 0XF800071C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_07 @ 0XF800071C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_08 @ 0XF8000720</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_08 @ 0XF8000720</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>702</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_09 @ 0XF8000724</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_09 @ 0XF8000724</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_10 @ 0XF8000728</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">2</td><td class="hex">40</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_10 @ 0XF8000728</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>1640</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_11 @ 0XF800072C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">2</td><td class="hex">40</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_11 @ 0XF800072C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>1640</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_12 @ 0XF8000730</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">2</td><td class="hex">40</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_12 @ 0XF8000730</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>1640</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_13 @ 0XF8000734</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">2</td><td class="hex">40</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_13 @ 0XF8000734</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>1640</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_14 @ 0XF8000738</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_14 @ 0XF8000738</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_15 @ 0XF800073C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">3</td><td class="hex">600</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_15 @ 0XF800073C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>600</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_16 @ 0XF8000740</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_16 @ 0XF8000740</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_17 @ 0XF8000744</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_17 @ 0XF8000744</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_18 @ 0XF8000748</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_18 @ 0XF8000748</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_19 @ 0XF800074C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_19 @ 0XF800074C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_20 @ 0XF8000750</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_20 @ 0XF8000750</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_21 @ 0XF8000754</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td><b>MIO_PIN_21 @ 0XF8000754</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2902</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_22 @ 0XF8000758</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_22 @ 0XF8000758</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_23 @ 0XF800075C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_23 @ 0XF800075C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_24 @ 0XF8000760</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_24 @ 0XF8000760</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_25 @ 0XF8000764</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_25 @ 0XF8000764</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_26 @ 0XF8000768</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_26 @ 0XF8000768</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_27 @ 0XF800076C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">4</td><td class="hex">800</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_27 @ 0XF800076C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>903</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_28 @ 0XF8000770</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_28 @ 0XF8000770</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_29 @ 0XF8000774</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_29 @ 0XF8000774</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>305</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_30 @ 0XF8000778</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_30 @ 0XF8000778</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_31 @ 0XF800077C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_31 @ 0XF800077C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>305</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_32 @ 0XF8000780</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_32 @ 0XF8000780</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_33 @ 0XF8000784</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_33 @ 0XF8000784</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_34 @ 0XF8000788</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_34 @ 0XF8000788</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_35 @ 0XF800078C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_35 @ 0XF800078C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_36 @ 0XF8000790</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_36 @ 0XF8000790</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>305</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_37 @ 0XF8000794</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_37 @ 0XF8000794</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_38 @ 0XF8000798</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_38 @ 0XF8000798</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_39 @ 0XF800079C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_39 @ 0XF800079C</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>304</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_40 @ 0XF80007A0</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_40 @ 0XF80007A0</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_41 @ 0XF80007A4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_41 @ 0XF80007A4</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_42 @ 0XF80007A8</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_42 @ 0XF80007A8</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_43 @ 0XF80007AC</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_43 @ 0XF80007AC</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_44 @ 0XF80007B0</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_44 @ 0XF80007B0</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_45 @ 0XF80007B4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_45 @ 0XF80007B4</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>380</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_46 @ 0XF80007B8</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_46 @ 0XF80007B8</td><td></td><td class="hex"><b>3f01</b></td><td></td><td class="hex"><b>200</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_47 @ 0XF80007BC</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_47 @ 0XF80007BC</td><td></td><td class="hex"><b>3f01</b></td><td></td><td class="hex"><b>201</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_48 @ 0XF80007C0</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">7</td><td class="hex">e0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_48 @ 0XF80007C0</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2e0</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_49 @ 0XF80007C4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">7</td><td class="hex">e0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_49 @ 0XF80007C4</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>2e1</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_50 @ 0XF80007C8</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_50 @ 0XF80007C8</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>201</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_51 @ 0XF80007CC</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_51 @ 0XF80007CC</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>201</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_52 @ 0XF80007D0</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_52 @ 0XF80007D0</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>280</b></td></tr></table>
-</li>
-<li><p>Register : MIO_PIN_53 @ 0XF80007D4</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >TRI_ENABLE</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L0_SEL</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L1_SEL</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L2_SEL</td><td class="hex">4:3</td><td class="hex">18</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >L3_SEL</td><td class="hex">7:5</td><td class="hex">e0</td><td class="hex">4</td><td class="hex">80</td></tr>
-<tr><td >Speed</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >IO_Type</td><td class="hex">11:9</td><td class="hex">e00</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >PULLUP</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >DisableRcvr</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MIO_PIN_53 @ 0XF80007D4</td><td></td><td class="hex"><b>3fff</b></td><td></td><td class="hex"><b>280</b></td></tr></table>
-</li>
-<li><p>Register : SD0_WP_CD_SEL @ 0XF8000830</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >SDIO0_CD_SEL</td><td class="hex">21:16</td><td class="hex">3f0000</td><td class="hex">2f</td><td class="hex">2f0000</td></tr>
-<tr><td><b>SD0_WP_CD_SEL @ 0XF8000830</td><td></td><td class="hex"><b>3f0000</b></td><td></td><td class="hex"><b>2f0000</b></td></tr></table>
-</li>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_peripherals_init_data_3_0">ps7_peripherals_init_data_3_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>DDR TERM/IBUF_DISABLE_MODE SETTINGS</h2>
-<ul>
-<p>DDR TERM/IBUF_DISABLE_MODE SETTINGS</p>
-<li><p>Register : DDRIOB_DATA0 @ 0XF8000B48</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td><b>DDRIOB_DATA0 @ 0XF8000B48</td><td></td><td class="hex"><b>180</b></td><td></td><td class="hex"><b>180</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DATA1 @ 0XF8000B4C</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td><b>DDRIOB_DATA1 @ 0XF8000B4C</td><td></td><td class="hex"><b>180</b></td><td></td><td class="hex"><b>180</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DIFF0 @ 0XF8000B50</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td><b>DDRIOB_DIFF0 @ 0XF8000B50</td><td></td><td class="hex"><b>180</b></td><td></td><td class="hex"><b>180</b></td></tr></table>
-</li>
-<li><p>Register : DDRIOB_DIFF1 @ 0XF8000B54</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >IBUF_DISABLE_MODE</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">1</td><td class="hex">80</td></tr>
-<tr><td >TERM_DISABLE_MODE</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td><b>DDRIOB_DIFF1 @ 0XF8000B54</td><td></td><td class="hex"><b>180</b></td><td></td><td class="hex"><b>180</b></td></tr></table>
-</li>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-<h2>SRAM/NOR SET OPMODE</h2>
-<ul>
-<p>SRAM/NOR SET OPMODE</p>
-</ul>
-<h2>UART REGISTERS</h2>
-<ul>
-<p>UART REGISTERS</p>
-<li><p>Register : Baud_rate_divider_reg0 @ 0XE0001034</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >BDIV</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">6</td><td class="hex">6</td></tr>
-<tr><td><b>Baud_rate_divider_reg0 @ 0XE0001034</td><td></td><td class="hex"><b>ff</b></td><td></td><td class="hex"><b>6</b></td></tr></table>
-</li>
-<li><p>Register : Baud_rate_gen_reg0 @ 0XE0001018</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CD</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">3e</td><td class="hex">3e</td></tr>
-<tr><td><b>Baud_rate_gen_reg0 @ 0XE0001018</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>3e</b></td></tr></table>
-</li>
-<li><p>Register : Control_reg0 @ 0XE0001000</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >STPBRK</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >STTBRK</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RSTTO</td><td class="hex">6:6</td><td class="hex">40</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TXDIS</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TXEN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >RXDIS</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RXEN</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >TXRES</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >RXRES</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>Control_reg0 @ 0XE0001000</td><td></td><td class="hex"><b>1ff</b></td><td></td><td class="hex"><b>17</b></td></tr></table>
-</li>
-<li><p>Register : mode_reg0 @ 0XE0001004</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CHMODE</td><td class="hex">9:8</td><td class="hex">300</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >NBSTOP</td><td class="hex">7:6</td><td class="hex">c0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >PAR</td><td class="hex">5:3</td><td class="hex">38</td><td class="hex">4</td><td class="hex">20</td></tr>
-<tr><td >CHRL</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CLKS</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>mode_reg0 @ 0XE0001004</td><td></td><td class="hex"><b>3ff</b></td><td></td><td class="hex"><b>20</b></td></tr></table>
-</li>
-<li><p>Register : Baud_rate_divider_reg0 @ 0XE0000034</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >BDIV</td><td class="hex">7:0</td><td class="hex">ff</td><td class="hex">6</td><td class="hex">6</td></tr>
-<tr><td><b>Baud_rate_divider_reg0 @ 0XE0000034</td><td></td><td class="hex"><b>ff</b></td><td></td><td class="hex"><b>6</b></td></tr></table>
-</li>
-<li><p>Register : Baud_rate_gen_reg0 @ 0XE0000018</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CD</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">3e</td><td class="hex">3e</td></tr>
-<tr><td><b>Baud_rate_gen_reg0 @ 0XE0000018</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>3e</b></td></tr></table>
-</li>
-<li><p>Register : Control_reg0 @ 0XE0000000</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >STPBRK</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >STTBRK</td><td class="hex">7:7</td><td class="hex">80</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RSTTO</td><td class="hex">6:6</td><td class="hex">40</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TXDIS</td><td class="hex">5:5</td><td class="hex">20</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >TXEN</td><td class="hex">4:4</td><td class="hex">10</td><td class="hex">1</td><td class="hex">10</td></tr>
-<tr><td >RXDIS</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >RXEN</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >TXRES</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >RXRES</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>Control_reg0 @ 0XE0000000</td><td></td><td class="hex"><b>1ff</b></td><td></td><td class="hex"><b>17</b></td></tr></table>
-</li>
-<li><p>Register : mode_reg0 @ 0XE0000004</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >CHMODE</td><td class="hex">9:8</td><td class="hex">300</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >NBSTOP</td><td class="hex">7:6</td><td class="hex">c0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >PAR</td><td class="hex">5:3</td><td class="hex">38</td><td class="hex">4</td><td class="hex">20</td></tr>
-<tr><td >CHRL</td><td class="hex">2:1</td><td class="hex">6</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >CLKS</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>mode_reg0 @ 0XE0000004</td><td></td><td class="hex"><b>3ff</b></td><td></td><td class="hex"><b>20</b></td></tr></table>
-</li>
-</ul>
-<h2>QSPI REGISTERS</h2>
-<ul>
-<p>QSPI REGISTERS</p>
-<li><p>Register : Config_reg @ 0XE000D000</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >Holdb_dr</td><td class="hex">19:19</td><td class="hex">80000</td><td class="hex">1</td><td class="hex">80000</td></tr>
-<tr><td><b>Config_reg @ 0XE000D000</td><td></td><td class="hex"><b>80000</b></td><td></td><td class="hex"><b>80000</b></td></tr></table>
-</li>
-</ul>
-<h2>PL POWER ON RESET REGISTERS</h2>
-<ul>
-<p>PL POWER ON RESET REGISTERS</p>
-<li><p>Register : CTRL @ 0XF8007000</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >PCFG_POR_CNT_4K</td><td class="hex">29:29</td><td class="hex">20000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>CTRL @ 0XF8007000</td><td></td><td class="hex"><b>20000000</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>SMC TIMING CALCULATION REGISTER UPDATE</h2>
-<ul>
-<p>SMC TIMING CALCULATION REGISTER UPDATE</p>
-<h2>NAND SET CYCLE</h2>
-<ul>
-<p>NAND SET CYCLE</p>
-</ul>
-<h2>OPMODE</h2>
-<ul>
-<p>OPMODE</p>
-</ul>
-<h2>DIRECT COMMAND</h2>
-<ul>
-<p>DIRECT COMMAND</p>
-</ul>
-<h2>SRAM/NOR CS0 SET CYCLE</h2>
-<ul>
-<p>SRAM/NOR CS0 SET CYCLE</p>
-</ul>
-<h2>DIRECT COMMAND</h2>
-<ul>
-<p>DIRECT COMMAND</p>
-</ul>
-<h2>NOR CS0 BASE ADDRESS</h2>
-<ul>
-<p>NOR CS0 BASE ADDRESS</p>
-</ul>
-<h2>SRAM/NOR CS1 SET CYCLE</h2>
-<ul>
-<p>SRAM/NOR CS1 SET CYCLE</p>
-</ul>
-<h2>DIRECT COMMAND</h2>
-<ul>
-<p>DIRECT COMMAND</p>
-</ul>
-<h2>NOR CS1 BASE ADDRESS</h2>
-<ul>
-<p>NOR CS1 BASE ADDRESS</p>
-</ul>
-<h2>USB RESET</h2>
-<ul>
-<p>USB RESET</p>
-<h2>DIR MODE BANK 0</h2>
-<ul>
-<p>DIR MODE BANK 0</p>
-</ul>
-<h2>DIR MODE BANK 1</h2>
-<ul>
-<p>DIR MODE BANK 1</p>
-<li><p>Register : DIRM_1 @ 0XE000A244</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >DIRECTION_1</td><td class="hex">21:0</td><td class="hex">3fffff</td><td class="hex">4000</td><td class="hex">4000</td></tr>
-<tr><td><b>DIRM_1 @ 0XE000A244</td><td></td><td class="hex"><b>3fffff</b></td><td></td><td class="hex"><b>4000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-<li><p>Register : MASK_DATA_1_LSW @ 0XE000A008</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >MASK_1_LSW</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">bfff</td><td class="hex">bfff0000</td></tr>
-<tr><td >DATA_1_LSW</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">4000</td><td class="hex">4000</td></tr>
-<tr><td><b>MASK_DATA_1_LSW @ 0XE000A008</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>bfff4000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-<h2>OUTPUT ENABLE BANK 0</h2>
-<ul>
-<p>OUTPUT ENABLE BANK 0</p>
-</ul>
-<h2>OUTPUT ENABLE BANK 1</h2>
-<ul>
-<p>OUTPUT ENABLE BANK 1</p>
-<li><p>Register : OEN_1 @ 0XE000A248</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >OP_ENABLE_1</td><td class="hex">21:0</td><td class="hex">3fffff</td><td class="hex">4000</td><td class="hex">4000</td></tr>
-<tr><td><b>OEN_1 @ 0XE000A248</td><td></td><td class="hex"><b>3fffff</b></td><td></td><td class="hex"><b>4000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_0_LSW LOW BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW LOW BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW LOW BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW LOW BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW LOW BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW LOW BANK [47:32]</p>
-<li><p>Register : MASK_DATA_1_LSW @ 0XE000A008</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >MASK_1_LSW</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">bfff</td><td class="hex">bfff0000</td></tr>
-<tr><td >DATA_1_LSW</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>MASK_DATA_1_LSW @ 0XE000A008</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>bfff0000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_1_MSW LOW BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW LOW BANK [53:48]</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-<li><p>Register : MASK_DATA_1_LSW @ 0XE000A008</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >MASK_1_LSW</td><td class="hex">31:16</td><td class="hex">ffff0000</td><td class="hex">bfff</td><td class="hex">bfff0000</td></tr>
-<tr><td >DATA_1_LSW</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">4000</td><td class="hex">4000</td></tr>
-<tr><td><b>MASK_DATA_1_LSW @ 0XE000A008</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>bfff4000</b></td></tr></table>
-</li>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-</ul>
-<h2>ENET RESET</h2>
-<ul>
-<p>ENET RESET</p>
-<h2>DIR MODE BANK 0</h2>
-<ul>
-<p>DIR MODE BANK 0</p>
-</ul>
-<h2>DIR MODE BANK 1</h2>
-<ul>
-<p>DIR MODE BANK 1</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-<h2>OUTPUT ENABLE BANK 0</h2>
-<ul>
-<p>OUTPUT ENABLE BANK 0</p>
-</ul>
-<h2>OUTPUT ENABLE BANK 1</h2>
-<ul>
-<p>OUTPUT ENABLE BANK 1</p>
-</ul>
-<h2>MASK_DATA_0_LSW LOW BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW LOW BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW LOW BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW LOW BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW LOW BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW LOW BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW LOW BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW LOW BANK [53:48]</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-</ul>
-<h2>I2C RESET</h2>
-<ul>
-<p>I2C RESET</p>
-<h2>DIR MODE GPIO BANK0</h2>
-<ul>
-<p>DIR MODE GPIO BANK0</p>
-</ul>
-<h2>DIR MODE GPIO BANK1</h2>
-<ul>
-<p>DIR MODE GPIO BANK1</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-<h2>OUTPUT ENABLE</h2>
-<ul>
-<p>OUTPUT ENABLE</p>
-</ul>
-<h2>OUTPUT ENABLE</h2>
-<ul>
-<p>OUTPUT ENABLE</p>
-</ul>
-<h2>MASK_DATA_0_LSW LOW BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW LOW BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW LOW BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW LOW BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW LOW BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW LOW BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW LOW BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW LOW BANK [53:48]</p>
-</ul>
-<h2>MASK_DATA_0_LSW HIGH BANK [15:0]</h2>
-<ul>
-<p>MASK_DATA_0_LSW HIGH BANK [15:0]</p>
-</ul>
-<h2>MASK_DATA_0_MSW HIGH BANK [31:16]</h2>
-<ul>
-<p>MASK_DATA_0_MSW HIGH BANK [31:16]</p>
-</ul>
-<h2>MASK_DATA_1_LSW HIGH BANK [47:32]</h2>
-<ul>
-<p>MASK_DATA_1_LSW HIGH BANK [47:32]</p>
-</ul>
-<h2>MASK_DATA_1_MSW HIGH BANK [53:48]</h2>
-<ul>
-<p>MASK_DATA_1_MSW HIGH BANK [53:48]</p>
-</ul>
-</ul>
-</ul>
-</ul>
-<hr/>
-<h1><a name="ps7_post_config_3_0">ps7_post_config_3_0</a></h1>
-<ul>
-<h2>SLCR SETTINGS</h2>
-<ul>
-<p>SLCR SETTINGS</p>
-<li><p>Register : SLCR_UNLOCK @ 0XF8000008</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >UNLOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">df0d</td><td class="hex">df0d</td></tr>
-<tr><td><b>SLCR_UNLOCK @ 0XF8000008</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>df0d</b></td></tr></table>
-</li>
-</ul>
-<h2>ENABLING LEVEL SHIFTER</h2>
-<ul>
-<p>ENABLING LEVEL SHIFTER</p>
-<li><p>Register : LVL_SHFTR_EN @ 0XF8000900</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >USER_LVL_INP_EN_0</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">1</td><td class="hex">8</td></tr>
-<tr><td >USER_LVL_OUT_EN_0</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >USER_LVL_INP_EN_1</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >USER_LVL_OUT_EN_1</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>LVL_SHFTR_EN @ 0XF8000900</td><td></td><td class="hex"><b>f</b></td><td></td><td class="hex"><b>f</b></td></tr></table>
-</li>
-</ul>
-<h2>FPGA RESETS TO 1</h2>
-<ul>
-<p>FPGA RESETS TO 1</p>
-<li><p>Register : FPGA_RST_CTRL @ 0XF8000240</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reserved_3</td><td class="hex">31:25</td><td class="hex">fe000000</td><td class="hex">7f</td><td class="hex">fe000000</td></tr>
-<tr><td >reserved_FPGA_ACP_RST</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">1</td><td class="hex">1000000</td></tr>
-<tr><td >reserved_FPGA_AXDS3_RST</td><td class="hex">23:23</td><td class="hex">800000</td><td class="hex">1</td><td class="hex">800000</td></tr>
-<tr><td >reserved_FPGA_AXDS2_RST</td><td class="hex">22:22</td><td class="hex">400000</td><td class="hex">1</td><td class="hex">400000</td></tr>
-<tr><td >reserved_FPGA_AXDS1_RST</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">1</td><td class="hex">200000</td></tr>
-<tr><td >reserved_FPGA_AXDS0_RST</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">1</td><td class="hex">100000</td></tr>
-<tr><td >reserved_2</td><td class="hex">19:18</td><td class="hex">c0000</td><td class="hex">3</td><td class="hex">c0000</td></tr>
-<tr><td >reserved_FSSW1_FPGA_RST</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">1</td><td class="hex">20000</td></tr>
-<tr><td >reserved_FSSW0_FPGA_RST</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">1</td><td class="hex">10000</td></tr>
-<tr><td >reserved_1</td><td class="hex">15:14</td><td class="hex">c000</td><td class="hex">3</td><td class="hex">c000</td></tr>
-<tr><td >reserved_FPGA_FMSW1_RST</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">1</td><td class="hex">2000</td></tr>
-<tr><td >reserved_FPGA_FMSW0_RST</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">1</td><td class="hex">1000</td></tr>
-<tr><td >reserved_FPGA_DMA3_RST</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">1</td><td class="hex">800</td></tr>
-<tr><td >reserved_FPGA_DMA2_RST</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">1</td><td class="hex">400</td></tr>
-<tr><td >reserved_FPGA_DMA1_RST</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">1</td><td class="hex">200</td></tr>
-<tr><td >reserved_FPGA_DMA0_RST</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">1</td><td class="hex">100</td></tr>
-<tr><td >reserved</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">f</td><td class="hex">f0</td></tr>
-<tr><td >FPGA3_OUT_RST</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">1</td><td class="hex">8</td></tr>
-<tr><td >FPGA2_OUT_RST</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">1</td><td class="hex">4</td></tr>
-<tr><td >FPGA1_OUT_RST</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">1</td><td class="hex">2</td></tr>
-<tr><td >FPGA0_OUT_RST</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">1</td><td class="hex">1</td></tr>
-<tr><td><b>FPGA_RST_CTRL @ 0XF8000240</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>ffffffff</b></td></tr></table>
-</li>
-</ul>
-<h2>FPGA RESETS TO 0</h2>
-<ul>
-<p>FPGA RESETS TO 0</p>
-<li><p>Register : FPGA_RST_CTRL @ 0XF8000240</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >reserved_3</td><td class="hex">31:25</td><td class="hex">fe000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_FPGA_ACP_RST</td><td class="hex">24:24</td><td class="hex">1000000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_FPGA_AXDS3_RST</td><td class="hex">23:23</td><td class="hex">800000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_FPGA_AXDS2_RST</td><td class="hex">22:22</td><td class="hex">400000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_FPGA_AXDS1_RST</td><td class="hex">21:21</td><td class="hex">200000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_FPGA_AXDS0_RST</td><td class="hex">20:20</td><td class="hex">100000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_2</td><td class="hex">19:18</td><td class="hex">c0000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_FSSW1_FPGA_RST</td><td class="hex">17:17</td><td class="hex">20000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_FSSW0_FPGA_RST</td><td class="hex">16:16</td><td class="hex">10000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_1</td><td class="hex">15:14</td><td class="hex">c000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_FPGA_FMSW1_RST</td><td class="hex">13:13</td><td class="hex">2000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_FPGA_FMSW0_RST</td><td class="hex">12:12</td><td class="hex">1000</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_FPGA_DMA3_RST</td><td class="hex">11:11</td><td class="hex">800</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_FPGA_DMA2_RST</td><td class="hex">10:10</td><td class="hex">400</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_FPGA_DMA1_RST</td><td class="hex">9:9</td><td class="hex">200</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved_FPGA_DMA0_RST</td><td class="hex">8:8</td><td class="hex">100</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >reserved</td><td class="hex">7:4</td><td class="hex">f0</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA3_OUT_RST</td><td class="hex">3:3</td><td class="hex">8</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA2_OUT_RST</td><td class="hex">2:2</td><td class="hex">4</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA1_OUT_RST</td><td class="hex">1:1</td><td class="hex">2</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td >FPGA0_OUT_RST</td><td class="hex">0:0</td><td class="hex">1</td><td class="hex">0</td><td class="hex">0</td></tr>
-<tr><td><b>FPGA_RST_CTRL @ 0XF8000240</td><td></td><td class="hex"><b>ffffffff</b></td><td></td><td class="hex"><b>0</b></td></tr></table>
-</li>
-</ul>
-<h2>AFI REGISTERS</h2>
-<ul>
-<p>AFI REGISTERS</p>
-<h2>AFI0 REGISTERS</h2>
-<ul>
-<p>AFI0 REGISTERS</p>
-</ul>
-<h2>AFI1 REGISTERS</h2>
-<ul>
-<p>AFI1 REGISTERS</p>
-</ul>
-<h2>AFI2 REGISTERS</h2>
-<ul>
-<p>AFI2 REGISTERS</p>
-</ul>
-<h2>AFI3 REGISTERS</h2>
-<ul>
-<p>AFI3 REGISTERS</p>
-</ul>
-</ul>
-<h2>LOCK IT BACK</h2>
-<ul>
-<p>LOCK IT BACK</p>
-<li><p>Register : SLCR_LOCK @ 0XF8000004</p>
-<table border="1"> 
-<tr><thead><th>Bitfield</th><th>Bits</th><th>Mask</th><th>Value</th><th>Shifted Value</th></thead></tr><tbody>
-<tr><td >LOCK_KEY</td><td class="hex">15:0</td><td class="hex">ffff</td><td class="hex">767b</td><td class="hex">767b</td></tr>
-<tr><td><b>SLCR_LOCK @ 0XF8000004</td><td></td><td class="hex"><b>ffff</b></td><td></td><td class="hex"><b>767b</b></td></tr></table>
-</li>
-</ul>
-</ul>
-<hr/>
-</body>
-</html>
diff --git a/quad/xsdk_workspace_vivado/sytem_hw_platform_0/ps7_init.tcl b/quad/xsdk_workspace_vivado/sytem_hw_platform_0/ps7_init.tcl
deleted file mode 100644
index b368b54f4a66fd75be5c9292197f74d8b6d10b12..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/sytem_hw_platform_0/ps7_init.tcl
+++ /dev/null
@@ -1,762 +0,0 @@
-proc ps7_pll_init_data_1_0 {} {
-    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
-    mask_write 0XF8000110 0x003FFFF0 0x001772C0
-    mask_write 0XF8000100 0x0007F000 0x0001A000
-    mask_write 0XF8000100 0x00000010 0x00000010
-    mask_write 0XF8000100 0x00000001 0x00000001
-    mask_write 0XF8000100 0x00000001 0x00000000
-    mask_poll 0XF800010C 0x00000001
-    mask_write 0XF8000100 0x00000010 0x00000000
-    mask_write 0XF8000120 0x1F003F30 0x1F000200
-    mask_write 0XF8000114 0x003FFFF0 0x001DB2C0
-    mask_write 0XF8000104 0x0007F000 0x00015000
-    mask_write 0XF8000104 0x00000010 0x00000010
-    mask_write 0XF8000104 0x00000001 0x00000001
-    mask_write 0XF8000104 0x00000001 0x00000000
-    mask_poll 0XF800010C 0x00000002
-    mask_write 0XF8000104 0x00000010 0x00000000
-    mask_write 0XF8000124 0xFFF00003 0x0C200003
-    mask_write 0XF8000118 0x003FFFF0 0x001F42C0
-    mask_write 0XF8000108 0x0007F000 0x00014000
-    mask_write 0XF8000108 0x00000010 0x00000010
-    mask_write 0XF8000108 0x00000001 0x00000001
-    mask_write 0XF8000108 0x00000001 0x00000000
-    mask_poll 0XF800010C 0x00000004
-    mask_write 0XF8000108 0x00000010 0x00000000
-    mask_write 0XF8000004 0x0000FFFF 0x0000767B
-}
-proc ps7_clock_init_data_1_0 {} {
-    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
-    mask_write 0XF8000128 0x03F03F01 0x00203401
-    mask_write 0XF8000138 0x00000011 0x00000001
-    mask_write 0XF8000140 0x03F03F71 0x00100801
-    mask_write 0XF800014C 0x00003F31 0x00000501
-    mask_write 0XF8000150 0x00003F33 0x00001401
-    mask_write 0XF8000154 0x00003F33 0x00001403
-    mask_write 0XF8000168 0x00003F31 0x00000501
-    mask_write 0XF8000170 0x03F03F30 0x00100A00
-    mask_write 0XF8000180 0x03F03F30 0x00100630
-    mask_write 0XF8000190 0x03F03F30 0x00203520
-    mask_write 0XF80001A0 0x03F03F30 0x00100A00
-    mask_write 0XF80001C4 0x00000001 0x00000001
-    mask_write 0XF800012C 0x01FFCCCD 0x01FC044D
-    mask_write 0XF8000004 0x0000FFFF 0x0000767B
-}
-proc ps7_ddr_init_data_1_0 {} {
-    mask_write 0XF8006000 0x0001FFFF 0x00000080
-    mask_write 0XF8006004 0x1FFFFFFF 0x0008107F
-    mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
-    mask_write 0XF800600C 0x03FFFFFF 0x02001001
-    mask_write 0XF8006010 0x03FFFFFF 0x00014001
-    mask_write 0XF8006014 0x001FFFFF 0x0004151A
-    mask_write 0XF8006018 0xF7FFFFFF 0x44E354D2
-    mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
-    mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
-    mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
-    mask_write 0XF8006028 0x00003FFF 0x00002007
-    mask_write 0XF800602C 0xFFFFFFFF 0x00000008
-    mask_write 0XF8006030 0xFFFFFFFF 0x00040930
-    mask_write 0XF8006034 0x13FF3FFF 0x00011014
-    mask_write 0XF8006038 0x00001FC3 0x00000000
-    mask_write 0XF800603C 0x000FFFFF 0x00000777
-    mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
-    mask_write 0XF8006044 0x0FFFFFFF 0x0FF66666
-    mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
-    mask_write 0XF8006050 0xFF0F8FFF 0x77010800
-    mask_write 0XF8006058 0x0001FFFF 0x00000101
-    mask_write 0XF800605C 0x0000FFFF 0x00005003
-    mask_write 0XF8006060 0x000017FF 0x0000003E
-    mask_write 0XF8006064 0x00021FE0 0x00020000
-    mask_write 0XF8006068 0x03FFFFFF 0x00284141
-    mask_write 0XF800606C 0x0000FFFF 0x00001610
-    mask_write 0XF80060A0 0x00FFFFFF 0x00008000
-    mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
-    mask_write 0XF80060A8 0x0FFFFFFF 0x0670C845
-    mask_write 0XF80060AC 0x000001FF 0x000001FE
-    mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
-    mask_write 0XF80060B4 0x000007FF 0x00000200
-    mask_write 0XF80060B8 0x01FFFFFF 0x00200066
-    mask_write 0XF80060C4 0x00000003 0x00000003
-    mask_write 0XF80060C4 0x00000003 0x00000000
-    mask_write 0XF80060C8 0x000000FF 0x00000000
-    mask_write 0XF80060DC 0x00000001 0x00000000
-    mask_write 0XF80060F0 0x0000FFFF 0x00000000
-    mask_write 0XF80060F4 0x0000000F 0x00000008
-    mask_write 0XF8006114 0x000000FF 0x00000000
-    mask_write 0XF8006118 0x7FFFFFFF 0x40000001
-    mask_write 0XF800611C 0x7FFFFFFF 0x40000001
-    mask_write 0XF8006120 0x7FFFFFFF 0x40000001
-    mask_write 0XF8006124 0x7FFFFFFF 0x40000001
-    mask_write 0XF800612C 0x000FFFFF 0x00023C00
-    mask_write 0XF8006130 0x000FFFFF 0x00022800
-    mask_write 0XF8006134 0x000FFFFF 0x00022C00
-    mask_write 0XF8006138 0x000FFFFF 0x00024800
-    mask_write 0XF8006140 0x000FFFFF 0x00000035
-    mask_write 0XF8006144 0x000FFFFF 0x00000035
-    mask_write 0XF8006148 0x000FFFFF 0x00000035
-    mask_write 0XF800614C 0x000FFFFF 0x00000035
-    mask_write 0XF8006154 0x000FFFFF 0x00000077
-    mask_write 0XF8006158 0x000FFFFF 0x0000007C
-    mask_write 0XF800615C 0x000FFFFF 0x0000007C
-    mask_write 0XF8006160 0x000FFFFF 0x00000075
-    mask_write 0XF8006168 0x001FFFFF 0x000000E4
-    mask_write 0XF800616C 0x001FFFFF 0x000000DF
-    mask_write 0XF8006170 0x001FFFFF 0x000000E0
-    mask_write 0XF8006174 0x001FFFFF 0x000000E7
-    mask_write 0XF800617C 0x000FFFFF 0x000000B7
-    mask_write 0XF8006180 0x000FFFFF 0x000000BC
-    mask_write 0XF8006184 0x000FFFFF 0x000000BC
-    mask_write 0XF8006188 0x000FFFFF 0x000000B5
-    mask_write 0XF8006190 0xFFFFFFFF 0x10040080
-    mask_write 0XF8006194 0x000FFFFF 0x0001FC82
-    mask_write 0XF8006204 0xFFFFFFFF 0x00000000
-    mask_write 0XF8006208 0x000F03FF 0x000803FF
-    mask_write 0XF800620C 0x000F03FF 0x000803FF
-    mask_write 0XF8006210 0x000F03FF 0x000803FF
-    mask_write 0XF8006214 0x000F03FF 0x000803FF
-    mask_write 0XF8006218 0x000F03FF 0x000003FF
-    mask_write 0XF800621C 0x000F03FF 0x000003FF
-    mask_write 0XF8006220 0x000F03FF 0x000003FF
-    mask_write 0XF8006224 0x000F03FF 0x000003FF
-    mask_write 0XF80062A8 0x00000FF7 0x00000000
-    mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
-    mask_write 0XF80062B0 0x003FFFFF 0x00005125
-    mask_write 0XF80062B4 0x0003FFFF 0x000012A6
-    mask_poll 0XF8000B74 0x00002000
-    mask_write 0XF8006000 0x0001FFFF 0x00000081
-    mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_1_0 {} {
-    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
-    mask_write 0XF8000B00 0x00000303 0x00000001
-    mask_write 0XF8000B40 0x00000FFF 0x00000600
-    mask_write 0XF8000B44 0x00000FFF 0x00000600
-    mask_write 0XF8000B48 0x00000FFF 0x00000672
-    mask_write 0XF8000B4C 0x00000FFF 0x00000672
-    mask_write 0XF8000B50 0x00000FFF 0x00000674
-    mask_write 0XF8000B54 0x00000FFF 0x00000674
-    mask_write 0XF8000B58 0x00000FFF 0x00000600
-    mask_write 0XF8000B5C 0xFFFFFFFF 0x00D6861C
-    mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
-    mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
-    mask_write 0XF8000B68 0xFFFFFFFF 0x00D6861C
-    mask_write 0XF8000B6C 0x000073FF 0x00000260
-    mask_write 0XF8000B70 0x00000021 0x00000021
-    mask_write 0XF8000B70 0x00000021 0x00000020
-    mask_write 0XF8000B70 0x07FFFFFF 0x00000823
-    mask_write 0XF8000700 0x00003FFF 0x00000600
-    mask_write 0XF8000704 0x00003FFF 0x00000702
-    mask_write 0XF8000708 0x00003FFF 0x00000702
-    mask_write 0XF800070C 0x00003FFF 0x00000702
-    mask_write 0XF8000710 0x00003FFF 0x00000702
-    mask_write 0XF8000714 0x00003FFF 0x00000702
-    mask_write 0XF8000718 0x00003FFF 0x00000702
-    mask_write 0XF800071C 0x00003FFF 0x00000600
-    mask_write 0XF8000720 0x00003FFF 0x00000702
-    mask_write 0XF8000724 0x00003FFF 0x00000600
-    mask_write 0XF8000728 0x00003FFF 0x00001640
-    mask_write 0XF800072C 0x00003FFF 0x00001640
-    mask_write 0XF8000730 0x00003FFF 0x00001640
-    mask_write 0XF8000734 0x00003FFF 0x00001640
-    mask_write 0XF8000738 0x00003FFF 0x00000600
-    mask_write 0XF800073C 0x00003FFF 0x00000600
-    mask_write 0XF8000740 0x00003FFF 0x00002902
-    mask_write 0XF8000744 0x00003FFF 0x00002902
-    mask_write 0XF8000748 0x00003FFF 0x00002902
-    mask_write 0XF800074C 0x00003FFF 0x00002902
-    mask_write 0XF8000750 0x00003FFF 0x00002902
-    mask_write 0XF8000754 0x00003FFF 0x00002902
-    mask_write 0XF8000758 0x00003FFF 0x00000903
-    mask_write 0XF800075C 0x00003FFF 0x00000903
-    mask_write 0XF8000760 0x00003FFF 0x00000903
-    mask_write 0XF8000764 0x00003FFF 0x00000903
-    mask_write 0XF8000768 0x00003FFF 0x00000903
-    mask_write 0XF800076C 0x00003FFF 0x00000903
-    mask_write 0XF8000770 0x00003FFF 0x00000304
-    mask_write 0XF8000774 0x00003FFF 0x00000305
-    mask_write 0XF8000778 0x00003FFF 0x00000304
-    mask_write 0XF800077C 0x00003FFF 0x00000305
-    mask_write 0XF8000780 0x00003FFF 0x00000304
-    mask_write 0XF8000784 0x00003FFF 0x00000304
-    mask_write 0XF8000788 0x00003FFF 0x00000304
-    mask_write 0XF800078C 0x00003FFF 0x00000304
-    mask_write 0XF8000790 0x00003FFF 0x00000305
-    mask_write 0XF8000794 0x00003FFF 0x00000304
-    mask_write 0XF8000798 0x00003FFF 0x00000304
-    mask_write 0XF800079C 0x00003FFF 0x00000304
-    mask_write 0XF80007A0 0x00003FFF 0x00000380
-    mask_write 0XF80007A4 0x00003FFF 0x00000380
-    mask_write 0XF80007A8 0x00003FFF 0x00000380
-    mask_write 0XF80007AC 0x00003FFF 0x00000380
-    mask_write 0XF80007B0 0x00003FFF 0x00000380
-    mask_write 0XF80007B4 0x00003FFF 0x00000380
-    mask_write 0XF80007B8 0x00003F01 0x00000200
-    mask_write 0XF80007BC 0x00003F01 0x00000201
-    mask_write 0XF80007C0 0x00003FFF 0x000002E0
-    mask_write 0XF80007C4 0x00003FFF 0x000002E1
-    mask_write 0XF80007C8 0x00003FFF 0x00000201
-    mask_write 0XF80007CC 0x00003FFF 0x00000201
-    mask_write 0XF80007D0 0x00003FFF 0x00000280
-    mask_write 0XF80007D4 0x00003FFF 0x00000280
-    mask_write 0XF8000830 0x003F0000 0x002F0000
-    mask_write 0XF8000004 0x0000FFFF 0x0000767B
-}
-proc ps7_peripherals_init_data_1_0 {} {
-    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
-    mask_write 0XF8000B48 0x00000180 0x00000180
-    mask_write 0XF8000B4C 0x00000180 0x00000180
-    mask_write 0XF8000B50 0x00000180 0x00000180
-    mask_write 0XF8000B54 0x00000180 0x00000180
-    mask_write 0XF8000004 0x0000FFFF 0x0000767B
-    mask_write 0XE0001034 0x000000FF 0x00000006
-    mask_write 0XE0001018 0x0000FFFF 0x0000003E
-    mask_write 0XE0001000 0x000001FF 0x00000017
-    mask_write 0XE0001004 0x00000FFF 0x00000020
-    mask_write 0XE0000034 0x000000FF 0x00000006
-    mask_write 0XE0000018 0x0000FFFF 0x0000003E
-    mask_write 0XE0000000 0x000001FF 0x00000017
-    mask_write 0XE0000004 0x00000FFF 0x00000020
-    mask_write 0XF8007000 0x20000000 0x00000000
-    mask_write 0XE000A244 0x003FFFFF 0x00004000
-    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
-    mask_write 0XE000A248 0x003FFFFF 0x00004000
-    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
-    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
-}
-proc ps7_post_config_1_0 {} {
-    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
-    mask_write 0XF8000900 0x0000000F 0x0000000F
-    mask_write 0XF8000240 0xFFFFFFFF 0xFFFFFFFF
-    mask_write 0XF8000240 0xFFFFFFFF 0x00000000
-    mask_write 0XF8000004 0x0000FFFF 0x0000767B
-}
-proc ps7_pll_init_data_2_0 {} {
-    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
-    mask_write 0XF8000110 0x003FFFF0 0x001772C0
-    mask_write 0XF8000100 0x0007F000 0x0001A000
-    mask_write 0XF8000100 0x00000010 0x00000010
-    mask_write 0XF8000100 0x00000001 0x00000001
-    mask_write 0XF8000100 0x00000001 0x00000000
-    mask_poll 0XF800010C 0x00000001
-    mask_write 0XF8000100 0x00000010 0x00000000
-    mask_write 0XF8000120 0x1F003F30 0x1F000200
-    mask_write 0XF8000114 0x003FFFF0 0x001DB2C0
-    mask_write 0XF8000104 0x0007F000 0x00015000
-    mask_write 0XF8000104 0x00000010 0x00000010
-    mask_write 0XF8000104 0x00000001 0x00000001
-    mask_write 0XF8000104 0x00000001 0x00000000
-    mask_poll 0XF800010C 0x00000002
-    mask_write 0XF8000104 0x00000010 0x00000000
-    mask_write 0XF8000124 0xFFF00003 0x0C200003
-    mask_write 0XF8000118 0x003FFFF0 0x001F42C0
-    mask_write 0XF8000108 0x0007F000 0x00014000
-    mask_write 0XF8000108 0x00000010 0x00000010
-    mask_write 0XF8000108 0x00000001 0x00000001
-    mask_write 0XF8000108 0x00000001 0x00000000
-    mask_poll 0XF800010C 0x00000004
-    mask_write 0XF8000108 0x00000010 0x00000000
-    mask_write 0XF8000004 0x0000FFFF 0x0000767B
-}
-proc ps7_clock_init_data_2_0 {} {
-    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
-    mask_write 0XF8000128 0x03F03F01 0x00203401
-    mask_write 0XF8000138 0x00000011 0x00000001
-    mask_write 0XF8000140 0x03F03F71 0x00100801
-    mask_write 0XF800014C 0x00003F31 0x00000501
-    mask_write 0XF8000150 0x00003F33 0x00001401
-    mask_write 0XF8000154 0x00003F33 0x00001403
-    mask_write 0XF8000168 0x00003F31 0x00000501
-    mask_write 0XF8000170 0x03F03F30 0x00100A00
-    mask_write 0XF8000180 0x03F03F30 0x00100630
-    mask_write 0XF8000190 0x03F03F30 0x00203520
-    mask_write 0XF80001A0 0x03F03F30 0x00100A00
-    mask_write 0XF80001C4 0x00000001 0x00000001
-    mask_write 0XF800012C 0x01FFCCCD 0x01FC044D
-    mask_write 0XF8000004 0x0000FFFF 0x0000767B
-}
-proc ps7_ddr_init_data_2_0 {} {
-    mask_write 0XF8006000 0x0001FFFF 0x00000080
-    mask_write 0XF8006004 0x1FFFFFFF 0x0008107F
-    mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
-    mask_write 0XF800600C 0x03FFFFFF 0x02001001
-    mask_write 0XF8006010 0x03FFFFFF 0x00014001
-    mask_write 0XF8006014 0x001FFFFF 0x0004151A
-    mask_write 0XF8006018 0xF7FFFFFF 0x44E354D2
-    mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
-    mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
-    mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
-    mask_write 0XF8006028 0x00003FFF 0x00002007
-    mask_write 0XF800602C 0xFFFFFFFF 0x00000008
-    mask_write 0XF8006030 0xFFFFFFFF 0x00040930
-    mask_write 0XF8006034 0x13FF3FFF 0x00011014
-    mask_write 0XF8006038 0x00001FC3 0x00000000
-    mask_write 0XF800603C 0x000FFFFF 0x00000777
-    mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
-    mask_write 0XF8006044 0x0FFFFFFF 0x0FF66666
-    mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
-    mask_write 0XF8006050 0xFF0F8FFF 0x77010800
-    mask_write 0XF8006058 0x0001FFFF 0x00000101
-    mask_write 0XF800605C 0x0000FFFF 0x00005003
-    mask_write 0XF8006060 0x000017FF 0x0000003E
-    mask_write 0XF8006064 0x00021FE0 0x00020000
-    mask_write 0XF8006068 0x03FFFFFF 0x00284141
-    mask_write 0XF800606C 0x0000FFFF 0x00001610
-    mask_write 0XF8006078 0x03FFFFFF 0x00466111
-    mask_write 0XF800607C 0x000FFFFF 0x00032222
-    mask_write 0XF80060A0 0x00FFFFFF 0x00008000
-    mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
-    mask_write 0XF80060A8 0x0FFFFFFF 0x0670C845
-    mask_write 0XF80060AC 0x000001FF 0x000001FE
-    mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
-    mask_write 0XF80060B4 0x000007FF 0x00000200
-    mask_write 0XF80060B8 0x01FFFFFF 0x00200066
-    mask_write 0XF80060C4 0x00000003 0x00000003
-    mask_write 0XF80060C4 0x00000003 0x00000000
-    mask_write 0XF80060C8 0x000000FF 0x00000000
-    mask_write 0XF80060DC 0x00000001 0x00000000
-    mask_write 0XF80060F0 0x0000FFFF 0x00000000
-    mask_write 0XF80060F4 0x0000000F 0x00000008
-    mask_write 0XF8006114 0x000000FF 0x00000000
-    mask_write 0XF8006118 0x7FFFFFFF 0x40000001
-    mask_write 0XF800611C 0x7FFFFFFF 0x40000001
-    mask_write 0XF8006120 0x7FFFFFFF 0x40000001
-    mask_write 0XF8006124 0x7FFFFFFF 0x40000001
-    mask_write 0XF800612C 0x000FFFFF 0x00023C00
-    mask_write 0XF8006130 0x000FFFFF 0x00022800
-    mask_write 0XF8006134 0x000FFFFF 0x00022C00
-    mask_write 0XF8006138 0x000FFFFF 0x00024800
-    mask_write 0XF8006140 0x000FFFFF 0x00000035
-    mask_write 0XF8006144 0x000FFFFF 0x00000035
-    mask_write 0XF8006148 0x000FFFFF 0x00000035
-    mask_write 0XF800614C 0x000FFFFF 0x00000035
-    mask_write 0XF8006154 0x000FFFFF 0x00000077
-    mask_write 0XF8006158 0x000FFFFF 0x0000007C
-    mask_write 0XF800615C 0x000FFFFF 0x0000007C
-    mask_write 0XF8006160 0x000FFFFF 0x00000075
-    mask_write 0XF8006168 0x001FFFFF 0x000000E4
-    mask_write 0XF800616C 0x001FFFFF 0x000000DF
-    mask_write 0XF8006170 0x001FFFFF 0x000000E0
-    mask_write 0XF8006174 0x001FFFFF 0x000000E7
-    mask_write 0XF800617C 0x000FFFFF 0x000000B7
-    mask_write 0XF8006180 0x000FFFFF 0x000000BC
-    mask_write 0XF8006184 0x000FFFFF 0x000000BC
-    mask_write 0XF8006188 0x000FFFFF 0x000000B5
-    mask_write 0XF8006190 0xFFFFFFFF 0x10040080
-    mask_write 0XF8006194 0x000FFFFF 0x0001FC82
-    mask_write 0XF8006204 0xFFFFFFFF 0x00000000
-    mask_write 0XF8006208 0x000F03FF 0x000803FF
-    mask_write 0XF800620C 0x000F03FF 0x000803FF
-    mask_write 0XF8006210 0x000F03FF 0x000803FF
-    mask_write 0XF8006214 0x000F03FF 0x000803FF
-    mask_write 0XF8006218 0x000F03FF 0x000003FF
-    mask_write 0XF800621C 0x000F03FF 0x000003FF
-    mask_write 0XF8006220 0x000F03FF 0x000003FF
-    mask_write 0XF8006224 0x000F03FF 0x000003FF
-    mask_write 0XF80062A8 0x00000FF7 0x00000000
-    mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
-    mask_write 0XF80062B0 0x003FFFFF 0x00005125
-    mask_write 0XF80062B4 0x0003FFFF 0x000012A6
-    mask_poll 0XF8000B74 0x00002000
-    mask_write 0XF8006000 0x0001FFFF 0x00000081
-    mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_2_0 {} {
-    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
-    mask_write 0XF8000B00 0x00000303 0x00000001
-    mask_write 0XF8000B40 0x00000FFF 0x00000600
-    mask_write 0XF8000B44 0x00000FFF 0x00000600
-    mask_write 0XF8000B48 0x00000FFF 0x00000672
-    mask_write 0XF8000B4C 0x00000FFF 0x00000672
-    mask_write 0XF8000B50 0x00000FFF 0x00000674
-    mask_write 0XF8000B54 0x00000FFF 0x00000674
-    mask_write 0XF8000B58 0x00000FFF 0x00000600
-    mask_write 0XF8000B5C 0xFFFFFFFF 0x00D6861C
-    mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
-    mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
-    mask_write 0XF8000B68 0xFFFFFFFF 0x00D6861C
-    mask_write 0XF8000B6C 0x00007FFF 0x00000E60
-    mask_write 0XF8000B70 0x00000021 0x00000021
-    mask_write 0XF8000B70 0x00000021 0x00000020
-    mask_write 0XF8000B70 0x07FFFFFF 0x00000823
-    mask_write 0XF8000700 0x00003FFF 0x00000600
-    mask_write 0XF8000704 0x00003FFF 0x00000702
-    mask_write 0XF8000708 0x00003FFF 0x00000702
-    mask_write 0XF800070C 0x00003FFF 0x00000702
-    mask_write 0XF8000710 0x00003FFF 0x00000702
-    mask_write 0XF8000714 0x00003FFF 0x00000702
-    mask_write 0XF8000718 0x00003FFF 0x00000702
-    mask_write 0XF800071C 0x00003FFF 0x00000600
-    mask_write 0XF8000720 0x00003FFF 0x00000702
-    mask_write 0XF8000724 0x00003FFF 0x00000600
-    mask_write 0XF8000728 0x00003FFF 0x00001640
-    mask_write 0XF800072C 0x00003FFF 0x00001640
-    mask_write 0XF8000730 0x00003FFF 0x00001640
-    mask_write 0XF8000734 0x00003FFF 0x00001640
-    mask_write 0XF8000738 0x00003FFF 0x00000600
-    mask_write 0XF800073C 0x00003FFF 0x00000600
-    mask_write 0XF8000740 0x00003FFF 0x00002902
-    mask_write 0XF8000744 0x00003FFF 0x00002902
-    mask_write 0XF8000748 0x00003FFF 0x00002902
-    mask_write 0XF800074C 0x00003FFF 0x00002902
-    mask_write 0XF8000750 0x00003FFF 0x00002902
-    mask_write 0XF8000754 0x00003FFF 0x00002902
-    mask_write 0XF8000758 0x00003FFF 0x00000903
-    mask_write 0XF800075C 0x00003FFF 0x00000903
-    mask_write 0XF8000760 0x00003FFF 0x00000903
-    mask_write 0XF8000764 0x00003FFF 0x00000903
-    mask_write 0XF8000768 0x00003FFF 0x00000903
-    mask_write 0XF800076C 0x00003FFF 0x00000903
-    mask_write 0XF8000770 0x00003FFF 0x00000304
-    mask_write 0XF8000774 0x00003FFF 0x00000305
-    mask_write 0XF8000778 0x00003FFF 0x00000304
-    mask_write 0XF800077C 0x00003FFF 0x00000305
-    mask_write 0XF8000780 0x00003FFF 0x00000304
-    mask_write 0XF8000784 0x00003FFF 0x00000304
-    mask_write 0XF8000788 0x00003FFF 0x00000304
-    mask_write 0XF800078C 0x00003FFF 0x00000304
-    mask_write 0XF8000790 0x00003FFF 0x00000305
-    mask_write 0XF8000794 0x00003FFF 0x00000304
-    mask_write 0XF8000798 0x00003FFF 0x00000304
-    mask_write 0XF800079C 0x00003FFF 0x00000304
-    mask_write 0XF80007A0 0x00003FFF 0x00000380
-    mask_write 0XF80007A4 0x00003FFF 0x00000380
-    mask_write 0XF80007A8 0x00003FFF 0x00000380
-    mask_write 0XF80007AC 0x00003FFF 0x00000380
-    mask_write 0XF80007B0 0x00003FFF 0x00000380
-    mask_write 0XF80007B4 0x00003FFF 0x00000380
-    mask_write 0XF80007B8 0x00003F01 0x00000200
-    mask_write 0XF80007BC 0x00003F01 0x00000201
-    mask_write 0XF80007C0 0x00003FFF 0x000002E0
-    mask_write 0XF80007C4 0x00003FFF 0x000002E1
-    mask_write 0XF80007C8 0x00003FFF 0x00000201
-    mask_write 0XF80007CC 0x00003FFF 0x00000201
-    mask_write 0XF80007D0 0x00003FFF 0x00000280
-    mask_write 0XF80007D4 0x00003FFF 0x00000280
-    mask_write 0XF8000830 0x003F0000 0x002F0000
-    mask_write 0XF8000004 0x0000FFFF 0x0000767B
-}
-proc ps7_peripherals_init_data_2_0 {} {
-    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
-    mask_write 0XF8000B48 0x00000180 0x00000180
-    mask_write 0XF8000B4C 0x00000180 0x00000180
-    mask_write 0XF8000B50 0x00000180 0x00000180
-    mask_write 0XF8000B54 0x00000180 0x00000180
-    mask_write 0XF8000004 0x0000FFFF 0x0000767B
-    mask_write 0XE0001034 0x000000FF 0x00000006
-    mask_write 0XE0001018 0x0000FFFF 0x0000003E
-    mask_write 0XE0001000 0x000001FF 0x00000017
-    mask_write 0XE0001004 0x00000FFF 0x00000020
-    mask_write 0XE0000034 0x000000FF 0x00000006
-    mask_write 0XE0000018 0x0000FFFF 0x0000003E
-    mask_write 0XE0000000 0x000001FF 0x00000017
-    mask_write 0XE0000004 0x00000FFF 0x00000020
-    mask_write 0XE000D000 0x00080000 0x00080000
-    mask_write 0XF8007000 0x20000000 0x00000000
-    mask_write 0XE000A244 0x003FFFFF 0x00004000
-    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
-    mask_write 0XE000A248 0x003FFFFF 0x00004000
-    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
-    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
-}
-proc ps7_post_config_2_0 {} {
-    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
-    mask_write 0XF8000900 0x0000000F 0x0000000F
-    mask_write 0XF8000240 0xFFFFFFFF 0xFFFFFFFF
-    mask_write 0XF8000240 0xFFFFFFFF 0x00000000
-    mask_write 0XF8000004 0x0000FFFF 0x0000767B
-}
-proc ps7_pll_init_data_3_0 {} {
-    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
-    mask_write 0XF8000110 0x003FFFF0 0x001772C0
-    mask_write 0XF8000100 0x0007F000 0x0001A000
-    mask_write 0XF8000100 0x00000010 0x00000010
-    mask_write 0XF8000100 0x00000001 0x00000001
-    mask_write 0XF8000100 0x00000001 0x00000000
-    mask_poll 0XF800010C 0x00000001
-    mask_write 0XF8000100 0x00000010 0x00000000
-    mask_write 0XF8000120 0x1F003F30 0x1F000200
-    mask_write 0XF8000114 0x003FFFF0 0x001DB2C0
-    mask_write 0XF8000104 0x0007F000 0x00015000
-    mask_write 0XF8000104 0x00000010 0x00000010
-    mask_write 0XF8000104 0x00000001 0x00000001
-    mask_write 0XF8000104 0x00000001 0x00000000
-    mask_poll 0XF800010C 0x00000002
-    mask_write 0XF8000104 0x00000010 0x00000000
-    mask_write 0XF8000124 0xFFF00003 0x0C200003
-    mask_write 0XF8000118 0x003FFFF0 0x001F42C0
-    mask_write 0XF8000108 0x0007F000 0x00014000
-    mask_write 0XF8000108 0x00000010 0x00000010
-    mask_write 0XF8000108 0x00000001 0x00000001
-    mask_write 0XF8000108 0x00000001 0x00000000
-    mask_poll 0XF800010C 0x00000004
-    mask_write 0XF8000108 0x00000010 0x00000000
-    mask_write 0XF8000004 0x0000FFFF 0x0000767B
-}
-proc ps7_clock_init_data_3_0 {} {
-    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
-    mask_write 0XF8000128 0x03F03F01 0x00203401
-    mask_write 0XF8000138 0x00000011 0x00000001
-    mask_write 0XF8000140 0x03F03F71 0x00100801
-    mask_write 0XF800014C 0x00003F31 0x00000501
-    mask_write 0XF8000150 0x00003F33 0x00001401
-    mask_write 0XF8000154 0x00003F33 0x00001403
-    mask_write 0XF8000168 0x00003F31 0x00000501
-    mask_write 0XF8000170 0x03F03F30 0x00100A00
-    mask_write 0XF8000180 0x03F03F30 0x00100630
-    mask_write 0XF8000190 0x03F03F30 0x00203520
-    mask_write 0XF80001A0 0x03F03F30 0x00100A00
-    mask_write 0XF80001C4 0x00000001 0x00000001
-    mask_write 0XF800012C 0x01FFCCCD 0x01FC044D
-    mask_write 0XF8000004 0x0000FFFF 0x0000767B
-}
-proc ps7_ddr_init_data_3_0 {} {
-    mask_write 0XF8006000 0x0001FFFF 0x00000080
-    mask_write 0XF8006004 0x0007FFFF 0x0000107F
-    mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
-    mask_write 0XF800600C 0x03FFFFFF 0x02001001
-    mask_write 0XF8006010 0x03FFFFFF 0x00014001
-    mask_write 0XF8006014 0x001FFFFF 0x0004151A
-    mask_write 0XF8006018 0xF7FFFFFF 0x44E354D2
-    mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
-    mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
-    mask_write 0XF8006024 0x0FFFFFC3 0x00000000
-    mask_write 0XF8006028 0x00003FFF 0x00002007
-    mask_write 0XF800602C 0xFFFFFFFF 0x00000008
-    mask_write 0XF8006030 0xFFFFFFFF 0x00040930
-    mask_write 0XF8006034 0x13FF3FFF 0x00011014
-    mask_write 0XF8006038 0x00000003 0x00000000
-    mask_write 0XF800603C 0x000FFFFF 0x00000777
-    mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
-    mask_write 0XF8006044 0x0FFFFFFF 0x0FF66666
-    mask_write 0XF8006048 0x0003F000 0x0003C000
-    mask_write 0XF8006050 0xFF0F8FFF 0x77010800
-    mask_write 0XF8006058 0x00010000 0x00000000
-    mask_write 0XF800605C 0x0000FFFF 0x00005003
-    mask_write 0XF8006060 0x000017FF 0x0000003E
-    mask_write 0XF8006064 0x00021FE0 0x00020000
-    mask_write 0XF8006068 0x03FFFFFF 0x00284141
-    mask_write 0XF800606C 0x0000FFFF 0x00001610
-    mask_write 0XF8006078 0x03FFFFFF 0x00466111
-    mask_write 0XF800607C 0x000FFFFF 0x00032222
-    mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
-    mask_write 0XF80060A8 0x0FFFFFFF 0x0670C845
-    mask_write 0XF80060AC 0x000001FF 0x000001FE
-    mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
-    mask_write 0XF80060B4 0x00000200 0x00000200
-    mask_write 0XF80060B8 0x01FFFFFF 0x00200066
-    mask_write 0XF80060C4 0x00000003 0x00000003
-    mask_write 0XF80060C4 0x00000003 0x00000000
-    mask_write 0XF80060C8 0x000000FF 0x00000000
-    mask_write 0XF80060DC 0x00000001 0x00000000
-    mask_write 0XF80060F0 0x0000FFFF 0x00000000
-    mask_write 0XF80060F4 0x0000000F 0x00000008
-    mask_write 0XF8006114 0x000000FF 0x00000000
-    mask_write 0XF8006118 0x7FFFFFCF 0x40000001
-    mask_write 0XF800611C 0x7FFFFFCF 0x40000001
-    mask_write 0XF8006120 0x7FFFFFCF 0x40000001
-    mask_write 0XF8006124 0x7FFFFFCF 0x40000001
-    mask_write 0XF800612C 0x000FFFFF 0x00023C00
-    mask_write 0XF8006130 0x000FFFFF 0x00022800
-    mask_write 0XF8006134 0x000FFFFF 0x00022C00
-    mask_write 0XF8006138 0x000FFFFF 0x00024800
-    mask_write 0XF8006140 0x000FFFFF 0x00000035
-    mask_write 0XF8006144 0x000FFFFF 0x00000035
-    mask_write 0XF8006148 0x000FFFFF 0x00000035
-    mask_write 0XF800614C 0x000FFFFF 0x00000035
-    mask_write 0XF8006154 0x000FFFFF 0x00000077
-    mask_write 0XF8006158 0x000FFFFF 0x0000007C
-    mask_write 0XF800615C 0x000FFFFF 0x0000007C
-    mask_write 0XF8006160 0x000FFFFF 0x00000075
-    mask_write 0XF8006168 0x001FFFFF 0x000000E4
-    mask_write 0XF800616C 0x001FFFFF 0x000000DF
-    mask_write 0XF8006170 0x001FFFFF 0x000000E0
-    mask_write 0XF8006174 0x001FFFFF 0x000000E7
-    mask_write 0XF800617C 0x000FFFFF 0x000000B7
-    mask_write 0XF8006180 0x000FFFFF 0x000000BC
-    mask_write 0XF8006184 0x000FFFFF 0x000000BC
-    mask_write 0XF8006188 0x000FFFFF 0x000000B5
-    mask_write 0XF8006190 0x6FFFFEFE 0x00040080
-    mask_write 0XF8006194 0x000FFFFF 0x0001FC82
-    mask_write 0XF8006204 0xFFFFFFFF 0x00000000
-    mask_write 0XF8006208 0x000703FF 0x000003FF
-    mask_write 0XF800620C 0x000703FF 0x000003FF
-    mask_write 0XF8006210 0x000703FF 0x000003FF
-    mask_write 0XF8006214 0x000703FF 0x000003FF
-    mask_write 0XF8006218 0x000F03FF 0x000003FF
-    mask_write 0XF800621C 0x000F03FF 0x000003FF
-    mask_write 0XF8006220 0x000F03FF 0x000003FF
-    mask_write 0XF8006224 0x000F03FF 0x000003FF
-    mask_write 0XF80062A8 0x00000FF5 0x00000000
-    mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
-    mask_write 0XF80062B0 0x003FFFFF 0x00005125
-    mask_write 0XF80062B4 0x0003FFFF 0x000012A6
-    mask_poll 0XF8000B74 0x00002000
-    mask_write 0XF8006000 0x0001FFFF 0x00000081
-    mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_3_0 {} {
-    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
-    mask_write 0XF8000B00 0x00000071 0x00000001
-    mask_write 0XF8000B40 0x00000FFE 0x00000600
-    mask_write 0XF8000B44 0x00000FFE 0x00000600
-    mask_write 0XF8000B48 0x00000FFE 0x00000672
-    mask_write 0XF8000B4C 0x00000FFE 0x00000672
-    mask_write 0XF8000B50 0x00000FFE 0x00000674
-    mask_write 0XF8000B54 0x00000FFE 0x00000674
-    mask_write 0XF8000B58 0x00000FFE 0x00000600
-    mask_write 0XF8000B6C 0x0000027F 0x00000260
-    mask_write 0XF8000B70 0x00000001 0x00000001
-    mask_write 0XF8000B70 0x00000001 0x00000000
-    mask_write 0XF8000B70 0x001E3FC3 0x00000803
-    mask_write 0XF8000700 0x00003FFF 0x00000600
-    mask_write 0XF8000704 0x00003FFF 0x00000702
-    mask_write 0XF8000708 0x00003FFF 0x00000702
-    mask_write 0XF800070C 0x00003FFF 0x00000702
-    mask_write 0XF8000710 0x00003FFF 0x00000702
-    mask_write 0XF8000714 0x00003FFF 0x00000702
-    mask_write 0XF8000718 0x00003FFF 0x00000702
-    mask_write 0XF800071C 0x00003FFF 0x00000600
-    mask_write 0XF8000720 0x00003FFF 0x00000702
-    mask_write 0XF8000724 0x00003FFF 0x00000600
-    mask_write 0XF8000728 0x00003FFF 0x00001640
-    mask_write 0XF800072C 0x00003FFF 0x00001640
-    mask_write 0XF8000730 0x00003FFF 0x00001640
-    mask_write 0XF8000734 0x00003FFF 0x00001640
-    mask_write 0XF8000738 0x00003FFF 0x00000600
-    mask_write 0XF800073C 0x00003FFF 0x00000600
-    mask_write 0XF8000740 0x00003FFF 0x00002902
-    mask_write 0XF8000744 0x00003FFF 0x00002902
-    mask_write 0XF8000748 0x00003FFF 0x00002902
-    mask_write 0XF800074C 0x00003FFF 0x00002902
-    mask_write 0XF8000750 0x00003FFF 0x00002902
-    mask_write 0XF8000754 0x00003FFF 0x00002902
-    mask_write 0XF8000758 0x00003FFF 0x00000903
-    mask_write 0XF800075C 0x00003FFF 0x00000903
-    mask_write 0XF8000760 0x00003FFF 0x00000903
-    mask_write 0XF8000764 0x00003FFF 0x00000903
-    mask_write 0XF8000768 0x00003FFF 0x00000903
-    mask_write 0XF800076C 0x00003FFF 0x00000903
-    mask_write 0XF8000770 0x00003FFF 0x00000304
-    mask_write 0XF8000774 0x00003FFF 0x00000305
-    mask_write 0XF8000778 0x00003FFF 0x00000304
-    mask_write 0XF800077C 0x00003FFF 0x00000305
-    mask_write 0XF8000780 0x00003FFF 0x00000304
-    mask_write 0XF8000784 0x00003FFF 0x00000304
-    mask_write 0XF8000788 0x00003FFF 0x00000304
-    mask_write 0XF800078C 0x00003FFF 0x00000304
-    mask_write 0XF8000790 0x00003FFF 0x00000305
-    mask_write 0XF8000794 0x00003FFF 0x00000304
-    mask_write 0XF8000798 0x00003FFF 0x00000304
-    mask_write 0XF800079C 0x00003FFF 0x00000304
-    mask_write 0XF80007A0 0x00003FFF 0x00000380
-    mask_write 0XF80007A4 0x00003FFF 0x00000380
-    mask_write 0XF80007A8 0x00003FFF 0x00000380
-    mask_write 0XF80007AC 0x00003FFF 0x00000380
-    mask_write 0XF80007B0 0x00003FFF 0x00000380
-    mask_write 0XF80007B4 0x00003FFF 0x00000380
-    mask_write 0XF80007B8 0x00003F01 0x00000200
-    mask_write 0XF80007BC 0x00003F01 0x00000201
-    mask_write 0XF80007C0 0x00003FFF 0x000002E0
-    mask_write 0XF80007C4 0x00003FFF 0x000002E1
-    mask_write 0XF80007C8 0x00003FFF 0x00000201
-    mask_write 0XF80007CC 0x00003FFF 0x00000201
-    mask_write 0XF80007D0 0x00003FFF 0x00000280
-    mask_write 0XF80007D4 0x00003FFF 0x00000280
-    mask_write 0XF8000830 0x003F0000 0x002F0000
-    mask_write 0XF8000004 0x0000FFFF 0x0000767B
-}
-proc ps7_peripherals_init_data_3_0 {} {
-    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
-    mask_write 0XF8000B48 0x00000180 0x00000180
-    mask_write 0XF8000B4C 0x00000180 0x00000180
-    mask_write 0XF8000B50 0x00000180 0x00000180
-    mask_write 0XF8000B54 0x00000180 0x00000180
-    mask_write 0XF8000004 0x0000FFFF 0x0000767B
-    mask_write 0XE0001034 0x000000FF 0x00000006
-    mask_write 0XE0001018 0x0000FFFF 0x0000003E
-    mask_write 0XE0001000 0x000001FF 0x00000017
-    mask_write 0XE0001004 0x000003FF 0x00000020
-    mask_write 0XE0000034 0x000000FF 0x00000006
-    mask_write 0XE0000018 0x0000FFFF 0x0000003E
-    mask_write 0XE0000000 0x000001FF 0x00000017
-    mask_write 0XE0000004 0x000003FF 0x00000020
-    mask_write 0XE000D000 0x00080000 0x00080000
-    mask_write 0XF8007000 0x20000000 0x00000000
-    mask_write 0XE000A244 0x003FFFFF 0x00004000
-    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
-    mask_write 0XE000A248 0x003FFFFF 0x00004000
-    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
-    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
-}
-proc ps7_post_config_3_0 {} {
-    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
-    mask_write 0XF8000900 0x0000000F 0x0000000F
-    mask_write 0XF8000240 0xFFFFFFFF 0xFFFFFFFF
-    mask_write 0XF8000240 0xFFFFFFFF 0x00000000
-    mask_write 0XF8000004 0x0000FFFF 0x0000767B
-}
-set PCW_SILICON_VER_1_0 "0x0"
-set PCW_SILICON_VER_2_0 "0x1"
-set PCW_SILICON_VER_3_0 "0x2"
-
-
-
-proc mask_poll { addr mask } {
-    set curval "0x[string range [mrd $addr] end-8 end]"
-    set maskedval [expr {$curval & $mask}]
-    while { $maskedval == 0 } {
-        set curval "0x[string range [mrd $addr] end-8 end]"
-        set maskedval [expr {$curval & $mask}]
-    }
-}
-
-proc ps_version { } {
-    set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
-    set mask_sil_ver "0x[expr {$si_ver >> 28}]"
-    return $mask_sil_ver;
-}
-
-proc ps7_post_config {} {
-    variable PCW_SILICON_VER_1_0
-    variable PCW_SILICON_VER_2_0
-    variable PCW_SILICON_VER_3_0
-    set sil_ver [ps_version]
-
-    if { $sil_ver == $PCW_SILICON_VER_1_0} {
-        ps7_post_config_1_0   
-    } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
-        ps7_post_config_2_0   
-    } else {
-        ps7_post_config_3_0   
-    }
-}
-
-proc ps7_init {} {
-    variable PCW_SILICON_VER_1_0
-    variable PCW_SILICON_VER_2_0
-    variable PCW_SILICON_VER_3_0
-    set sil_ver [ps_version]
-
-    if { $sil_ver == $PCW_SILICON_VER_1_0} {
-            ps7_mio_init_data_1_0
-            ps7_pll_init_data_1_0
-            ps7_clock_init_data_1_0
-            ps7_ddr_init_data_1_0
-            ps7_peripherals_init_data_1_0
-            #puts "PCW Silicon Version : 1.0"
-    } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
-            ps7_mio_init_data_2_0
-            ps7_pll_init_data_2_0
-            ps7_clock_init_data_2_0
-            ps7_ddr_init_data_2_0
-            ps7_peripherals_init_data_2_0
-            #puts "PCW Silicon Version : 2.0"
-    } else {
-            ps7_mio_init_data_3_0
-            ps7_pll_init_data_3_0
-            ps7_clock_init_data_3_0
-            ps7_ddr_init_data_3_0
-            ps7_peripherals_init_data_3_0
-            #puts "PCW Silicon Version : 3.0"
-    }
-}
diff --git a/quad/xsdk_workspace_vivado/sytem_hw_platform_0/system.bit b/quad/xsdk_workspace_vivado/sytem_hw_platform_0/system.bit
deleted file mode 100644
index 286b0b3fa151c4f54f8fb01538a1b6d6aec57b13..0000000000000000000000000000000000000000
Binary files a/quad/xsdk_workspace_vivado/sytem_hw_platform_0/system.bit and /dev/null differ
diff --git a/quad/xsdk_workspace_vivado/sytem_hw_platform_0/system.xml b/quad/xsdk_workspace_vivado/sytem_hw_platform_0/system.xml
deleted file mode 100644
index cdf4d9d58d07c230d8e390c8ae8560ba86cc1314..0000000000000000000000000000000000000000
--- a/quad/xsdk_workspace_vivado/sytem_hw_platform_0/system.xml
+++ /dev/null
@@ -1,12677 +0,0 @@
-
-<EDKSYSTEM EDKVERSION="14.7" EDWVERSION="1.2" TIMESTAMP="Fri Apr 21 16:15:41 2017">
-
-  <SYSTEMINFO ARCH="zynq" DEVICE="xc7z010" PACKAGE="clg400" PART="xc7z010clg400-1" SOURCE="/local/ucart/MicroCART_17-18/quad/sytem/system.xmp" SPEEDGRADE="-1"/>
-
-  <EXTERNALPORTS>
-    <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="N" DIR="I" MHS_INDEX="0" NAME="CLK_N" SIGIS="CLK" SIGNAME="CLK">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="clock_generator_0" PORT="CLKIN"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="P" DIR="I" MHS_INDEX="1" NAME="CLK_P" SIGIS="CLK" SIGNAME="CLK">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="clock_generator_0" PORT="CLKIN"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="53" LSB="0" MHS_INDEX="2" MSB="53" NAME="processing_system7_0_MIO" RIGHT="0" SIGNAME="processing_system7_0_MIO">
-      <CONNECTIONS/>
-    </PORT>
-    <PORT DIR="I" MHS_INDEX="3" NAME="processing_system7_0_PS_SRSTB_pin" SIGNAME="processing_system7_0_PS_SRSTB">
-      <CONNECTIONS/>
-    </PORT>
-    <PORT DIR="I" MHS_INDEX="4" NAME="processing_system7_0_PS_CLK_pin" SIGIS="CLK" SIGNAME="processing_system7_0_PS_CLK">
-      <CONNECTIONS/>
-    </PORT>
-    <PORT DIR="I" MHS_INDEX="5" NAME="processing_system7_0_PS_PORB_pin" SIGNAME="processing_system7_0_PS_PORB">
-      <CONNECTIONS/>
-    </PORT>
-    <PORT DIR="IO" MHS_INDEX="6" NAME="processing_system7_0_DDR_Clk" SIGIS="CLK" SIGNAME="processing_system7_0_DDR_Clk">
-      <CONNECTIONS/>
-    </PORT>
-    <PORT DIR="IO" MHS_INDEX="7" NAME="processing_system7_0_DDR_Clk_n" SIGIS="CLK" SIGNAME="processing_system7_0_DDR_Clk_n">
-      <CONNECTIONS/>
-    </PORT>
-    <PORT DIR="IO" MHS_INDEX="8" NAME="processing_system7_0_DDR_CKE" SIGNAME="processing_system7_0_DDR_CKE">
-      <CONNECTIONS/>
-    </PORT>
-    <PORT DIR="IO" MHS_INDEX="9" NAME="processing_system7_0_DDR_CS_n" SIGNAME="processing_system7_0_DDR_CS_n">
-      <CONNECTIONS/>
-    </PORT>
-    <PORT DIR="IO" MHS_INDEX="10" NAME="processing_system7_0_DDR_RAS_n" SIGNAME="processing_system7_0_DDR_RAS_n">
-      <CONNECTIONS/>
-    </PORT>
-    <PORT DIR="IO" MHS_INDEX="11" NAME="processing_system7_0_DDR_CAS_n" SIGNAME="processing_system7_0_DDR_CAS_n">
-      <CONNECTIONS/>
-    </PORT>
-    <PORT DIR="O" MHS_INDEX="12" NAME="processing_system7_0_DDR_WEB_pin" SIGNAME="processing_system7_0_DDR_WEB">
-      <CONNECTIONS/>
-    </PORT>
-    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="2" LSB="0" MHS_INDEX="13" MSB="2" NAME="processing_system7_0_DDR_BankAddr" RIGHT="0" SIGNAME="processing_system7_0_DDR_BankAddr">
-      <CONNECTIONS/>
-    </PORT>
-    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="14" LSB="0" MHS_INDEX="14" MSB="14" NAME="processing_system7_0_DDR_Addr" RIGHT="0" SIGNAME="processing_system7_0_DDR_Addr">
-      <CONNECTIONS/>
-    </PORT>
-    <PORT DIR="IO" MHS_INDEX="15" NAME="processing_system7_0_DDR_ODT" SIGNAME="processing_system7_0_DDR_ODT">
-      <CONNECTIONS/>
-    </PORT>
-    <PORT DIR="IO" MHS_INDEX="16" NAME="processing_system7_0_DDR_DRSTB" SIGIS="RST" SIGNAME="processing_system7_0_DDR_DRSTB">
-      <CONNECTIONS/>
-    </PORT>
-    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="31" LSB="0" MHS_INDEX="17" MSB="31" NAME="processing_system7_0_DDR_DQ" RIGHT="0" SIGNAME="processing_system7_0_DDR_DQ">
-      <CONNECTIONS/>
-    </PORT>
-    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="18" MSB="3" NAME="processing_system7_0_DDR_DM" RIGHT="0" SIGNAME="processing_system7_0_DDR_DM">
-      <CONNECTIONS/>
-    </PORT>
-    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="19" MSB="3" NAME="processing_system7_0_DDR_DQS" RIGHT="0" SIGNAME="processing_system7_0_DDR_DQS">
-      <CONNECTIONS/>
-    </PORT>
-    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="20" MSB="3" NAME="processing_system7_0_DDR_DQS_n" RIGHT="0" SIGNAME="processing_system7_0_DDR_DQS_n">
-      <CONNECTIONS/>
-    </PORT>
-    <PORT DIR="IO" MHS_INDEX="21" NAME="processing_system7_0_DDR_VRN" SIGNAME="processing_system7_0_DDR_VRN">
-      <CONNECTIONS/>
-    </PORT>
-    <PORT DIR="IO" MHS_INDEX="22" NAME="processing_system7_0_DDR_VRP" SIGNAME="processing_system7_0_DDR_VRP">
-      <CONNECTIONS/>
-    </PORT>
-    <PORT DIR="I" MHS_INDEX="23" NAME="pwm_recorder_0_pwm_in_master_pin" SIGNAME="pwm_recorder_0_pwm_in_master">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="pwm_recorder_0" PORT="pwm_in_master"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="I" MHS_INDEX="24" NAME="pwm_recorder_1_pwm_in_master_pin" SIGNAME="pwm_recorder_1_pwm_in_master">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="pwm_recorder_1" PORT="pwm_in_master"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="I" MHS_INDEX="25" NAME="pwm_recorder_2_pwm_in_master_pin" SIGNAME="pwm_recorder_2_pwm_in_master">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="pwm_recorder_2" PORT="pwm_in_master"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="I" MHS_INDEX="26" NAME="pwm_recorder_3_pwm_in_master_pin" SIGNAME="pwm_recorder_3_pwm_in_master">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="pwm_recorder_3" PORT="pwm_in_master"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="I" MHS_INDEX="27" NAME="pwm_recorder_4_pwm_in_master_pin" SIGNAME="pwm_recorder_4_pwm_in_master">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="pwm_recorder_4" PORT="pwm_in_master"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="I" MHS_INDEX="28" NAME="pwm_recorder_5_pwm_in_master_pin" SIGNAME="pwm_recorder_5_pwm_in_master">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="pwm_recorder_5" PORT="pwm_in_master"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="29" MSB="3" NAME="BTNs_4Bits_TRI_IO_GPIO_IO_I_pin" RIGHT="0" SIGNAME="BTNs_4Bits_TRI_IO_GPIO_IO_I">
-      <CONNECTIONS>
-        <CONNECTION BUSINTERFACE="[gpio_0]" INSTANCE="btns_4bits_tri_io" PORT="GPIO_IO_I"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="O" MHS_INDEX="30" NAME="processing_system7_0_UART0_TX_pin" SIGNAME="processing_system7_0_UART0_TX">
-      <CONNECTIONS/>
-    </PORT>
-    <PORT DIR="I" MHS_INDEX="31" NAME="processing_system7_0_UART0_RX_pin" SIGNAME="processing_system7_0_UART0_RX">
-      <CONNECTIONS/>
-    </PORT>
-    <PORT DIR="O" MHS_INDEX="32" NAME="pwm_signal_out_wkillswitch_0_pwm_out_sm_pin" SIGNAME="pwm_signal_out_wkillswitch_0_pwm_out_sm">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="pwm_signal_out_wkillswitch_0" PORT="pwm_out_sm"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="O" MHS_INDEX="33" NAME="pwm_signal_out_wkillswitch_1_pwm_out_sm_pin" SIGNAME="pwm_signal_out_wkillswitch_1_pwm_out_sm">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="pwm_signal_out_wkillswitch_1" PORT="pwm_out_sm"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="O" MHS_INDEX="34" NAME="pwm_signal_out_wkillswitch_2_pwm_out_sm_pin" SIGNAME="pwm_signal_out_wkillswitch_2_pwm_out_sm">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="pwm_signal_out_wkillswitch_2" PORT="pwm_out_sm"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="O" MHS_INDEX="35" NAME="pwm_signal_out_wkillswitch_3_pwm_out_sm_pin" SIGNAME="pwm_signal_out_wkillswitch_3_pwm_out_sm">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="pwm_signal_out_wkillswitch_3" PORT="pwm_out_sm"/>
-      </CONNECTIONS>
-    </PORT>
-  </EXTERNALPORTS>
-
-  <MODULES>
-    <MODULE HWVERSION="4.03.a" INSTANCE="clock_generator_0" IPTYPE="PERIPHERAL" MHS_INDEX="0" MODCLASS="IP" MODTYPE="clock_generator">
-      <DESCRIPTION TYPE="SHORT">Clock Generator</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">Clock generator for processor system.</DESCRIPTION>
-      <DOCUMENTATION>
-        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=clock_generator;v=v4_03_a;d=clock_generator.pdf" TYPE="IP"/>
-      </DOCUMENTATION>
-      <LICENSEINFO ICON_NAME="ps_core_earlyaccess"/>
-      <PARAMETERS>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq">
-          <DESCRIPTION>Family</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_DEVICE" TYPE="STRING" VALUE="7z010">
-          <DESCRIPTION>Device</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_PACKAGE" TYPE="STRING" VALUE="clg400">
-          <DESCRIPTION>Package</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPEEDGRADE" TYPE="STRING" VALUE="-1">
-          <DESCRIPTION>Speed Grade</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_CLKIN_FREQ" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>Input Clock Frequency (Hz) </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="5" NAME="C_CLKOUT0_FREQ" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="6" NAME="C_CLKOUT0_PHASE" TYPE="REAL" VALUE="0">
-          <DESCRIPTION>Required Phase </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="7" NAME="C_CLKOUT0_GROUP" TYPE="STRING" VALUE="NONE">
-          <DESCRIPTION>Required Group</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_CLKOUT0_BUF" TYPE="BOOLEAN" VALUE="TRUE">
-          <DESCRIPTION>Buffered </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_CLKOUT0_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
-          <DESCRIPTION>Variable Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_CLKOUT1_FREQ" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_CLKOUT1_PHASE" TYPE="REAL" VALUE="0">
-          <DESCRIPTION>Required Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="12" NAME="C_CLKOUT1_GROUP" TYPE="STRING" VALUE="NONE">
-          <DESCRIPTION>Required Group </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="13" NAME="C_CLKOUT1_BUF" TYPE="BOOLEAN" VALUE="TRUE">
-          <DESCRIPTION>Buffered</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="14" NAME="C_CLKOUT1_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
-          <DESCRIPTION>Variable Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="15" NAME="C_CLKOUT2_FREQ" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="16" NAME="C_CLKOUT2_PHASE" TYPE="REAL" VALUE="0">
-          <DESCRIPTION>Required Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="17" NAME="C_CLKOUT2_GROUP" TYPE="STRING" VALUE="NONE">
-          <DESCRIPTION>Required Group </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="18" NAME="C_CLKOUT2_BUF" TYPE="BOOLEAN" VALUE="TRUE">
-          <DESCRIPTION>Buffered</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="19" NAME="C_CLKOUT2_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
-          <DESCRIPTION>Varaible Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="20" NAME="C_CLKOUT3_FREQ" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="21" NAME="C_CLKOUT3_PHASE" TYPE="REAL" VALUE="0">
-          <DESCRIPTION>Required Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="22" NAME="C_CLKOUT3_GROUP" TYPE="STRING" VALUE="NONE">
-          <DESCRIPTION>Required Group</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="23" NAME="C_CLKOUT3_BUF" TYPE="BOOLEAN" VALUE="TRUE">
-          <DESCRIPTION>Buffered</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="24" NAME="C_CLKOUT3_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
-          <DESCRIPTION>Variable Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="25" NAME="C_CLKOUT4_FREQ" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="26" NAME="C_CLKOUT4_PHASE" TYPE="REAL" VALUE="0">
-          <DESCRIPTION>Required Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="27" NAME="C_CLKOUT4_GROUP" TYPE="STRING" VALUE="NONE">
-          <DESCRIPTION>Required Group </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="28" NAME="C_CLKOUT4_BUF" TYPE="BOOLEAN" VALUE="TRUE">
-          <DESCRIPTION>Buffered</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="29" NAME="C_CLKOUT4_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
-          <DESCRIPTION>Variable Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="30" NAME="C_CLKOUT5_FREQ" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="31" NAME="C_CLKOUT5_PHASE" TYPE="REAL" VALUE="0">
-          <DESCRIPTION>Required Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="32" NAME="C_CLKOUT5_GROUP" TYPE="STRING" VALUE="NONE">
-          <DESCRIPTION>Required Group</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="33" NAME="C_CLKOUT5_BUF" TYPE="BOOLEAN" VALUE="TRUE">
-          <DESCRIPTION>Buffered</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="34" NAME="C_CLKOUT5_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
-          <DESCRIPTION>Variable Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="35" NAME="C_CLKOUT6_FREQ" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="36" NAME="C_CLKOUT6_PHASE" TYPE="REAL" VALUE="0">
-          <DESCRIPTION>Required Phase </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="37" NAME="C_CLKOUT6_GROUP" TYPE="STRING" VALUE="NONE">
-          <DESCRIPTION>Required Group</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="38" NAME="C_CLKOUT6_BUF" TYPE="BOOLEAN" VALUE="TRUE">
-          <DESCRIPTION>Buffered</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="39" NAME="C_CLKOUT6_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
-          <DESCRIPTION>Variable Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="40" NAME="C_CLKOUT7_FREQ" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="41" NAME="C_CLKOUT7_PHASE" TYPE="REAL" VALUE="0">
-          <DESCRIPTION>Required Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="42" NAME="C_CLKOUT7_GROUP" TYPE="STRING" VALUE="NONE">
-          <DESCRIPTION>Required Group</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="43" NAME="C_CLKOUT7_BUF" TYPE="BOOLEAN" VALUE="TRUE">
-          <DESCRIPTION>Buffered</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="44" NAME="C_CLKOUT7_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
-          <DESCRIPTION>Variable Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="45" NAME="C_CLKOUT8_FREQ" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="46" NAME="C_CLKOUT8_PHASE" TYPE="REAL" VALUE="0">
-          <DESCRIPTION>Required Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="47" NAME="C_CLKOUT8_GROUP" TYPE="STRING" VALUE="NONE">
-          <DESCRIPTION>Required Group</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="48" NAME="C_CLKOUT8_BUF" TYPE="BOOLEAN" VALUE="TRUE">
-          <DESCRIPTION>Buffered</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="49" NAME="C_CLKOUT8_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
-          <DESCRIPTION>Variable Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="50" NAME="C_CLKOUT9_FREQ" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="51" NAME="C_CLKOUT9_PHASE" TYPE="REAL" VALUE="0">
-          <DESCRIPTION>Required Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="52" NAME="C_CLKOUT9_GROUP" TYPE="STRING" VALUE="NONE">
-          <DESCRIPTION>Required Group</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="53" NAME="C_CLKOUT9_BUF" TYPE="BOOLEAN" VALUE="TRUE">
-          <DESCRIPTION>Buffered</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="54" NAME="C_CLKOUT9_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
-          <DESCRIPTION> Varaible Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="55" NAME="C_CLKOUT10_FREQ" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="56" NAME="C_CLKOUT10_PHASE" TYPE="REAL" VALUE="0">
-          <DESCRIPTION>Required Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="57" NAME="C_CLKOUT10_GROUP" TYPE="STRING" VALUE="NONE">
-          <DESCRIPTION>Required Group</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="58" NAME="C_CLKOUT10_BUF" TYPE="BOOLEAN" VALUE="TRUE">
-          <DESCRIPTION>Buffered</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="59" NAME="C_CLKOUT10_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
-          <DESCRIPTION>Variable Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="60" NAME="C_CLKOUT11_FREQ" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="61" NAME="C_CLKOUT11_PHASE" TYPE="REAL" VALUE="0">
-          <DESCRIPTION>Required Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="62" NAME="C_CLKOUT11_GROUP" TYPE="STRING" VALUE="NONE">
-          <DESCRIPTION>Required Group</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="63" NAME="C_CLKOUT11_BUF" TYPE="BOOLEAN" VALUE="TRUE">
-          <DESCRIPTION>Buffered</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="64" NAME="C_CLKOUT11_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
-          <DESCRIPTION>Variable Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="65" NAME="C_CLKOUT12_FREQ" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="66" NAME="C_CLKOUT12_PHASE" TYPE="REAL" VALUE="0">
-          <DESCRIPTION>Required Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="67" NAME="C_CLKOUT12_GROUP" TYPE="STRING" VALUE="NONE">
-          <DESCRIPTION>Required Group</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="68" NAME="C_CLKOUT12_BUF" TYPE="BOOLEAN" VALUE="TRUE">
-          <DESCRIPTION>Buffered</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="69" NAME="C_CLKOUT12_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
-          <DESCRIPTION> Variable Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="70" NAME="C_CLKOUT13_FREQ" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="71" NAME="C_CLKOUT13_PHASE" TYPE="REAL" VALUE="0">
-          <DESCRIPTION>Required Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="72" NAME="C_CLKOUT13_GROUP" TYPE="STRING" VALUE="NONE">
-          <DESCRIPTION>Required Group</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="73" NAME="C_CLKOUT13_BUF" TYPE="BOOLEAN" VALUE="TRUE">
-          <DESCRIPTION>Buffered</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="74" NAME="C_CLKOUT13_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
-          <DESCRIPTION>Variable Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="75" NAME="C_CLKOUT14_FREQ" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="76" NAME="C_CLKOUT14_PHASE" TYPE="REAL" VALUE="0">
-          <DESCRIPTION>Required Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="77" NAME="C_CLKOUT14_GROUP" TYPE="STRING" VALUE="NONE">
-          <DESCRIPTION>Required Group</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="78" NAME="C_CLKOUT14_BUF" TYPE="BOOLEAN" VALUE="TRUE">
-          <DESCRIPTION>Buffered</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="79" NAME="C_CLKOUT14_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
-          <DESCRIPTION>Variable Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="80" NAME="C_CLKOUT15_FREQ" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="81" NAME="C_CLKOUT15_PHASE" TYPE="REAL" VALUE="0">
-          <DESCRIPTION>Required Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="82" NAME="C_CLKOUT15_GROUP" TYPE="STRING" VALUE="NONE">
-          <DESCRIPTION>Required Group</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="83" NAME="C_CLKOUT15_BUF" TYPE="BOOLEAN" VALUE="TRUE">
-          <DESCRIPTION>Buffered</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="84" NAME="C_CLKOUT15_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
-          <DESCRIPTION> Variable Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="85" NAME="C_CLKFBIN_FREQ" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="86" NAME="C_CLKFBIN_DESKEW" TYPE="STRING" VALUE="NONE">
-          <DESCRIPTION>Clock Deskew</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="87" NAME="C_CLKFBOUT_FREQ" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="88" NAME="C_CLKFBOUT_PHASE" TYPE="REAL" VALUE="0">
-          <DESCRIPTION>Required Phase</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="89" NAME="C_CLKFBOUT_GROUP" TYPE="STRING" VALUE="NONE">
-          <DESCRIPTION>Required Group</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="90" NAME="C_CLKFBOUT_BUF" TYPE="BOOLEAN" VALUE="TRUE">
-          <DESCRIPTION>Buffered</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="91" NAME="C_PSDONE_GROUP" TYPE="STRING" VALUE="NONE">
-          <DESCRIPTION>Variable Phase Shift</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="92" NAME="C_EXT_RESET_HIGH" TYPE="INTEGER" VALUE="1">
-          <DESCRIPTION>C_EXT_RESET_HIGH</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="93" NAME="C_CLK_PRIMITIVE_FEEDBACK_BUF" TYPE="BOOLEAN" VALUE="FALSE">
-          <DESCRIPTION>Clock Primitive Feedback Buffer</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="94" NAME="C_CLKOUT0_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="95" NAME="C_CLKOUT1_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="96" NAME="C_CLKOUT2_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="97" NAME="C_CLKOUT3_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="98" NAME="C_CLKOUT4_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="99" NAME="C_CLKOUT5_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="100" NAME="C_CLKOUT6_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="101" NAME="C_CLKOUT7_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="102" NAME="C_CLKOUT8_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="103" NAME="C_CLKOUT9_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="104" NAME="C_CLKOUT10_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="105" NAME="C_CLKOUT11_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="106" NAME="C_CLKOUT12_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="107" NAME="C_CLKOUT13_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="108" NAME="C_CLKOUT14_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="109" NAME="C_CLKOUT15_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="110" NAME="C_CLK_GEN" VALUE="UPDATE"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT CLKFREQUENCY="200000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="CLKIN" SIGIS="CLK" SIGNAME="CLK">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="External Ports" PORT="CLK_N"/>
-            <CONNECTION INSTANCE="External Ports" PORT="CLK_P"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="24" NAME="LOCKED" SIGNAME="clock_generator_0_LOCKED_0">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="reset_0" PORT="Dcm_locked"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="O" MPD_INDEX="1" NAME="CLKOUT0" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="2" NAME="CLKOUT1" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="3" NAME="CLKOUT2" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="CLKOUT3" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="5" NAME="CLKOUT4" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="6" NAME="CLKOUT5" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="7" NAME="CLKOUT6" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="8" NAME="CLKOUT7" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="9" NAME="CLKOUT8" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="10" NAME="CLKOUT9" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="11" NAME="CLKOUT10" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="12" NAME="CLKOUT11" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="13" NAME="CLKOUT12" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="14" NAME="CLKOUT13" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="15" NAME="CLKOUT14" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="16" NAME="CLKOUT15" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="17" NAME="CLKFBIN" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="18" NAME="CLKFBOUT" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="19" NAME="PSCLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="20" NAME="PSEN" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="21" NAME="PSINCDEC" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="22" NAME="PSDONE" SIGNAME="__NOC__"/>
-        <PORT DIR="I" MPD_INDEX="23" NAME="RST" SIGIS="RST" SIGNAME="__NOC__"/>
-      </PORTS>
-      <BUSINTERFACES/>
-    </MODULE>
-    <MODULE HWVERSION="3.00.a" INSTANCE="reset_0" IPTYPE="PERIPHERAL" MHS_INDEX="1" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset">
-      <DESCRIPTION TYPE="SHORT">Processor System Reset Module</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">Reset management module</DESCRIPTION>
-      <DOCUMENTATION>
-        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=proc_sys_reset;v=v3_00_a;d=proc_sys_reset.pdf" TYPE="IP"/>
-      </DOCUMENTATION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="0" NAME="C_SUBFAMILY" TYPE="string" VALUE="lx">
-          <DESCRIPTION>Device Subfamily</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="1" NAME="C_EXT_RST_WIDTH" TYPE="integer" VALUE="4">
-          <DESCRIPTION>Number of Clocks Before Input Change is Recognized On The External Reset Input </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_AUX_RST_WIDTH" TYPE="integer" VALUE="4">
-          <DESCRIPTION>Number of Clocks Before Input Change is Recognized On The Auxiliary Reset Input </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="std_logic" VALUE="1">
-          <DESCRIPTION>External Reset Active High </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_AUX_RESET_HIGH" TYPE="std_logic" VALUE="1">
-          <DESCRIPTION>Auxiliary Reset Active High </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="5" NAME="C_NUM_BUS_RST" TYPE="integer" VALUE="1">
-          <DESCRIPTION>Number of Bus Structure Reset Registered Outputs </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="6" NAME="C_NUM_PERP_RST" TYPE="integer" VALUE="1">
-          <DESCRIPTION>Number of Peripheral Reset Registered Outputs </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="7" NAME="C_NUM_INTERCONNECT_ARESETN" TYPE="integer" VALUE="1">
-          <DESCRIPTION>Number of Active Low Interconnect Reset Registered Outputs </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_NUM_PERP_ARESETN" TYPE="integer" VALUE="1">
-          <DESCRIPTION>Number of Active Low Peripheral Reset Registered Outputs </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_FAMILY" VALUE="zynq">
-          <DESCRIPTION>Device Family</DESCRIPTION>
-        </PARAMETER>
-      </PARAMETERS>
-      <PORTS>
-        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="10" NAME="Dcm_locked" SIGNAME="clock_generator_0_LOCKED_0">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="clock_generator_0" PORT="LOCKED"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" MPD_INDEX="0" NAME="Slowest_sync_clk" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" MPD_INDEX="1" NAME="Ext_Reset_In" SIGIS="RST" SIGNAME="__NOC__"/>
-        <PORT DIR="I" MPD_INDEX="2" NAME="Aux_Reset_In" SIGIS="RST" SIGNAME="__NOC__"/>
-        <PORT DIR="I" MPD_INDEX="3" NAME="MB_Debug_Sys_Rst" SIGIS="RST" SIGNAME="__NOC__"/>
-        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="4" NAME="Core_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
-        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="5" NAME="Chip_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
-        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="6" NAME="System_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
-        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="7" NAME="Core_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
-        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="8" NAME="Chip_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
-        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="9" NAME="System_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
-        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="11" NAME="RstcPPCresetcore_0" SIGIS="RST" SIGNAME="__NOC__"/>
-        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="12" NAME="RstcPPCresetchip_0" SIGIS="RST" SIGNAME="__NOC__"/>
-        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="13" NAME="RstcPPCresetsys_0" SIGIS="RST" SIGNAME="__NOC__"/>
-        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="14" NAME="RstcPPCresetcore_1" SIGIS="RST" SIGNAME="__NOC__"/>
-        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="15" NAME="RstcPPCresetchip_1" SIGIS="RST" SIGNAME="__NOC__"/>
-        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="16" NAME="RstcPPCresetsys_1" SIGIS="RST" SIGNAME="__NOC__"/>
-        <PORT DIR="O" MPD_INDEX="17" NAME="MB_Reset" SIGIS="RST" SIGNAME="__NOC__"/>
-        <PORT DIR="O" MPD_INDEX="18" NAME="Bus_Struct_Reset" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_BUS_RST-1]"/>
-        <PORT DIR="O" MPD_INDEX="19" NAME="Peripheral_Reset" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_RST-1]"/>
-        <PORT DIR="O" MPD_INDEX="20" NAME="Interconnect_aresetn" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_INTERCONNECT_ARESETN-1]"/>
-        <PORT DIR="O" MPD_INDEX="21" NAME="Peripheral_aresetn" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_ARESETN-1]"/>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="0" NAME="RESETPPC0" TYPE="INITIATOR">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_0"/>
-            <PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_0"/>
-            <PORTMAP DIR="I" PHYSICAL="System_Reset_Req_0"/>
-            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_0"/>
-            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_0"/>
-            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_0"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="1" NAME="RESETPPC1" TYPE="INITIATOR">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_1"/>
-            <PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_1"/>
-            <PORTMAP DIR="I" PHYSICAL="System_Reset_Req_1"/>
-            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_1"/>
-            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_1"/>
-            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_1"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <IOINTERFACES>
-        <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
-      </IOINTERFACES>
-    </MODULE>
-    <MODULE HWVERSION="1.04.a" INSTANCE="pwm_recorder_0" IPTYPE="PERIPHERAL" MHS_INDEX="2" MODCLASS="PERIPHERAL" MODTYPE="pwm_recorder">
-      <DESCRIPTION TYPE="SHORT">PWM_RECORDER</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_local"/>
-      <PARAMETERS>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_S_AXI_MIN_SIZE" TYPE="std_logic_vector" VALUE="0x000001ff"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_USE_WSTRB" TYPE="INTEGER" VALUE="0"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_DPHASE_TIMEOUT" TYPE="INTEGER" VALUE="8"/>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x76ea0000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x76eaffff"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_NUM_REG" TYPE="INTEGER" VALUE="1"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_NUM_MEM" TYPE="INTEGER" VALUE="1"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_SLV_AWIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_SLV_DWIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="12" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="pwm_in" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="19" NAME="pwm_in_master" SIGNAME="pwm_recorder_0_pwm_in_master">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="External Ports" PORT="pwm_recorder_0_pwm_in_master_pin"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="5" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="6" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="7" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="8" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="9" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="10" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="1995046912" BASENAME="C_BASEADDR" BASEVALUE="0x76ea0000" HIGHDECIMAL="1995112447" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76eaffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.06.a" INSTANCE="axi_interconnect_1" IPTYPE="BUS" MHS_INDEX="3" MODCLASS="BUS" MODTYPE="axi_interconnect">
-      <DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">AXI4 Memory-Mapped Interconnect</DESCRIPTION>
-      <DOCUMENTATION>
-        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v1_06_a;d=ds768_axi_interconnect.pdf" TYPE="IP"/>
-      </DOCUMENTATION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq">
-          <DESCRIPTION>Family</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="zynq">
-          <DESCRIPTION>Base Family</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="2" NAME="C_NUM_SLAVE_SLOTS" TYPE="INTEGER" VALUE="1">
-          <DESCRIPTION>Number of Slave Slots </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_NUM_MASTER_SLOTS" TYPE="INTEGER" VALUE="12">
-          <DESCRIPTION>Number of Master Slots </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="4" NAME="C_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1">
-          <DESCRIPTION>AXI ID Widgth </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="5" NAME="C_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
-          <DESCRIPTION>AXI Address Widgth </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="6" NAME="C_AXI_DATA_MAX_WIDTH" TYPE="INTEGER" VALUE="32">
-          <DESCRIPTION>AXI Data Maximum Width </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="7" NAME="C_S_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
-          <DESCRIPTION>Slave AXI Data Width</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="8" NAME="C_M_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
-          <DESCRIPTION>Master AXI Data Width </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="9" NAME="C_INTERCONNECT_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
-          <DESCRIPTION>Interconnect Crossbar Data Width </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
-          <DESCRIPTION>AXI Protocol</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="11" NAME="C_M_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002">
-          <DESCRIPTION>Master AXI Protocol</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_M_AXI_BASE_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000042800000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000079400000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000079420000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000079440000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000079460000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041200000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000076e00000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000076e20000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000076e40000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000076e60000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000076e80000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000076ea0000">
-          <DESCRIPTION>Master AXI Base Address</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_M_AXI_HIGH_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004280ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007940ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007942ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007944ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007946ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004120ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000076e0ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000076e2ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000076e4ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000076e6ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000076e8ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000076eaffff">
-          <DESCRIPTION>Master AXI High Address</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="14" NAME="C_S_AXI_BASE_ID" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
-          <DESCRIPTION>Slave AXI Base ID</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="15" NAME="C_S_AXI_THREAD_ID_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
-          <DESCRIPTION>Slave AXI Thread ID Width</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="16" NAME="C_S_AXI_IS_INTERCONNECT" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
-          <DESCRIPTION>Slave AXI Is Interconnect</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="17" NAME="C_S_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
-          <DESCRIPTION>Slave AXI ACLK Ratio</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="18" NAME="C_S_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000001">
-          <DESCRIPTION>Slvave AXI Is ACLK ASYNC</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_M_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000100000001000000010000000105f5e10005f5e10005f5e10005f5e10005f5e10005f5e10005f5e10005f5e10005f5e10005f5e10005f5e10005f5e100">
-          <DESCRIPTION>Master AXI ACLK Ratio</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="20" NAME="C_M_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
-          <DESCRIPTION>Master AXI Is ACLK ASYNC</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="21" NAME="C_INTERCONNECT_ACLK_RATIO" TYPE="INTEGER" VALUE="100000000">
-          <DESCRIPTION>Interconnect Crossbar ACLK Frequency Ratio</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="22" NAME="C_S_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
-          <DESCRIPTION>Slave AXI Supports Write</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="23" NAME="C_S_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
-          <DESCRIPTION>Slave AXI Supports Read</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="24" NAME="C_M_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
-          <DESCRIPTION>Master AXI Supports Write</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="25" NAME="C_M_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
-          <DESCRIPTION>Master AXI Supports Read</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="26" NAME="C_AXI_SUPPORTS_USER_SIGNALS" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>Propagate USER Signals</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="27" NAME="C_AXI_AWUSER_WIDTH" TYPE="INTEGER" VALUE="1">
-          <DESCRIPTION>AWUSER Signal Width </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="28" NAME="C_AXI_ARUSER_WIDTH" TYPE="INTEGER" VALUE="1">
-          <DESCRIPTION>ARUSER Signal Width</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="29" NAME="C_AXI_WUSER_WIDTH" TYPE="INTEGER" VALUE="1">
-          <DESCRIPTION>WUSER Signal Width </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="30" NAME="C_AXI_RUSER_WIDTH" TYPE="INTEGER" VALUE="1">
-          <DESCRIPTION>RUSER Signal Width</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="31" NAME="C_AXI_BUSER_WIDTH" TYPE="INTEGER" VALUE="1">
-          <DESCRIPTION>BUSER Signal Width</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="32" NAME="C_AXI_CONNECTIVITY" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff">
-          <DESCRIPTION>AXI Connectivity</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="33" NAME="C_S_AXI_SINGLE_THREAD" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
-          <DESCRIPTION>Slave AXI Single Thread</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="34" NAME="C_M_AXI_SUPPORTS_REORDERING" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
-          <DESCRIPTION>Master AXI Supports Reordering</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="35" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
-          <DESCRIPTION>Master generates narrow bursts</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="36" NAME="C_M_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
-          <DESCRIPTION>Slave accepts narrow bursts</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="37" NAME="C_S_AXI_WRITE_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
-          <DESCRIPTION>Slave AXI Write Acceptance</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="38" NAME="C_S_AXI_READ_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
-          <DESCRIPTION>Slave AXI Read Acceptance</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="39" NAME="C_M_AXI_WRITE_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
-          <DESCRIPTION>Master AXI Write Issuing</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="40" NAME="C_M_AXI_READ_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
-          <DESCRIPTION>Master AXI Read Issuing</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="41" NAME="C_S_AXI_ARB_PRIORITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
-          <DESCRIPTION>Slave AXI ARB Priority</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="42" NAME="C_M_AXI_SECURE" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
-          <DESCRIPTION>Master AXI Secure</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="43" NAME="C_S_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
-          <DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="44" NAME="C_S_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
-          <DESCRIPTION>Slave AXI Write FIFO Type</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="45" NAME="C_S_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
-          <DESCRIPTION>Slave AXI Write FIFO Delay</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="46" NAME="C_S_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
-          <DESCRIPTION>Slave AXI Read FIFO Depth</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="47" NAME="C_S_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
-          <DESCRIPTION>Slave AXI Read FIFO Type</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="48" NAME="C_S_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
-          <DESCRIPTION>Slave AXI Read FIFO Delay</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="49" NAME="C_M_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
-          <DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="50" NAME="C_M_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
-          <DESCRIPTION>Master AXI Write FIFO Type</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="51" NAME="C_M_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
-          <DESCRIPTION>Master AXI Write FIFO Delay</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="52" NAME="C_M_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
-          <DESCRIPTION>Master AXI Read FIFO Depth</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="53" NAME="C_M_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
-          <DESCRIPTION>Master AXI Read FIFO Type</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="54" NAME="C_M_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
-          <DESCRIPTION>Master AXI Read FIFO Delay</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="55" NAME="C_S_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
-          <DESCRIPTION>Slave AXI AW Register</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="56" NAME="C_S_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
-          <DESCRIPTION>Slave AXI AR Register</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="57" NAME="C_S_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
-          <DESCRIPTION>Slave AXI W Register </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="58" NAME="C_S_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
-          <DESCRIPTION>Slave AXI R Register</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="59" NAME="C_S_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
-          <DESCRIPTION>Slave AXI B Register</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="60" NAME="C_M_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
-          <DESCRIPTION>Master AXI AW Register</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="61" NAME="C_M_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
-          <DESCRIPTION>Master AXI AR Register</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="62" NAME="C_M_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
-          <DESCRIPTION>Master AXI W Register</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="63" NAME="C_M_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
-          <DESCRIPTION>Master AXI R Register</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="64" NAME="C_M_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
-          <DESCRIPTION>Master AXI B Register</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="65" NAME="C_INTERCONNECT_R_REGISTER" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>C_INTERCONNECT_R_REGISTER</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="66" NAME="C_INTERCONNECT_CONNECTIVITY_MODE" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>Interconnect Architecture</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="67" NAME="C_USE_CTRL_PORT" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>Use Diagnostic Slave Port</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="68" NAME="C_USE_INTERRUPT" TYPE="INTEGER" VALUE="1">
-          <DESCRIPTION>Generate Interrupts</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="69" NAME="C_RANGE_CHECK" TYPE="INTEGER" VALUE="2">
-          <DESCRIPTION>Check for transaction errors (DECERR)</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="70" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
-          <DESCRIPTION>Slave AXI CTRL Protocol</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="71" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
-          <DESCRIPTION>Slave AXI CTRL Address Width</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="72" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
-          <DESCRIPTION>Slave AXI CTRL Data Width</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" MPD_INDEX="73" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
-          <DESCRIPTION>Diagnostic Slave Port Base Address</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" MPD_INDEX="74" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
-          <DESCRIPTION>Diagnostic Slave Port High Address</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="75" NAME="C_DEBUG" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>Simulation debug</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="76" NAME="C_S_AXI_DEBUG_SLOT" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>Select SI slot for DEBUG outputs</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="77" NAME="C_M_AXI_DEBUG_SLOT" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>Select MI slot for DEBUG outputs</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="78" NAME="C_MAX_DEBUG_THREADS" TYPE="INTEGER" VALUE="1">
-          <DESCRIPTION>Thread depth of DEBUG signal</DESCRIPTION>
-        </PARAMETER>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI_CTRL" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="INTERCONNECT_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="INTERCONNECT_ARESETN" SIGIS="RST" SIGNAME="processing_system7_0_FCLK_RESET0_N">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_ARESETN" DIR="O" MPD_INDEX="2" NAME="S_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="axi_interconnect_1_S_ARESETN" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="3" MSB="11" NAME="M_AXI_ARESET_OUT_N" RIGHT="0" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_ARESETN"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_ACLK" DIR="I" MPD_INDEX="5" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="axi_interconnect_1_S_ACLK" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_AWID" DIR="I" MPD_INDEX="6" NAME="S_AXI_AWID" SIGNAME="axi_interconnect_1_S_AWID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="7" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="8" MSB="7" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="9" MSB="2" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="11" MSB="1" NAME="S_AXI_AWLOCK" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="12" MSB="3" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="13" MSB="2" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="14" MSB="3" NAME="S_AXI_AWQOS" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_AWUSER" DIR="I" MPD_INDEX="15" NAME="S_AXI_AWUSER" SIGNAME="axi_interconnect_1_S_AWUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_AWVALID" DIR="I" MPD_INDEX="16" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_S_AWVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_AWREADY" DIR="O" MPD_INDEX="17" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_S_AWREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_WID" DIR="I" MPD_INDEX="18" NAME="S_AXI_WID" SIGNAME="axi_interconnect_1_S_WID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_S_WDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="20" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_S_WSTRB" VECFORMULA="[(((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_WLAST" DIR="I" MPD_INDEX="21" NAME="S_AXI_WLAST" SIGNAME="axi_interconnect_1_S_WLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_WUSER" DIR="I" MPD_INDEX="22" NAME="S_AXI_WUSER" SIGNAME="axi_interconnect_1_S_WUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_WVALID" DIR="I" MPD_INDEX="23" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_S_WVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_WREADY" DIR="O" MPD_INDEX="24" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_S_WREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_BID" DIR="O" MPD_INDEX="25" NAME="S_AXI_BID" SIGNAME="axi_interconnect_1_S_BID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="26" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_S_BRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_BUSER" DIR="O" MPD_INDEX="27" NAME="S_AXI_BUSER" SIGNAME="axi_interconnect_1_S_BUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_BVALID" DIR="O" MPD_INDEX="28" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_S_BVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_BREADY" DIR="I" MPD_INDEX="29" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_S_BREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_ARID" DIR="I" MPD_INDEX="30" NAME="S_AXI_ARID" SIGNAME="axi_interconnect_1_S_ARID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="31" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="32" MSB="7" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="33" MSB="2" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="34" MSB="1" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="35" MSB="1" NAME="S_AXI_ARLOCK" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="36" MSB="3" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="37" MSB="2" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="38" MSB="3" NAME="S_AXI_ARQOS" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_ARUSER" DIR="I" MPD_INDEX="39" NAME="S_AXI_ARUSER" SIGNAME="axi_interconnect_1_S_ARUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_ARVALID" DIR="I" MPD_INDEX="40" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_S_ARVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_ARREADY" DIR="O" MPD_INDEX="41" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_S_ARREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_RID" DIR="O" MPD_INDEX="42" NAME="S_AXI_RID" SIGNAME="axi_interconnect_1_S_RID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="43" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_S_RDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="44" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_S_RRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_RLAST" DIR="O" MPD_INDEX="45" NAME="S_AXI_RLAST" SIGNAME="axi_interconnect_1_S_RLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_RUSER" DIR="O" MPD_INDEX="46" NAME="S_AXI_RUSER" SIGNAME="axi_interconnect_1_S_RUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_RVALID" DIR="O" MPD_INDEX="47" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_S_RVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_S_RREADY" DIR="I" MPD_INDEX="48" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_S_RREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_ACLK" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="49" MSB="11" NAME="M_AXI_ACLK" RIGHT="0" SIGIS="CLK" SIGNAME="axi_interconnect_1_M_ACLK" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_AWID" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="50" MSB="11" NAME="M_AXI_AWID" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="383" LSB="0" MPD_INDEX="51" MSB="383" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="95" LSB="0" MPD_INDEX="52" MSB="95" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="35" LSB="0" MPD_INDEX="53" MSB="35" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="54" MSB="23" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_AWLOCK" DIR="O" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="55" MSB="23" NAME="M_AXI_AWLOCK" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="47" LSB="0" MPD_INDEX="56" MSB="47" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="35" LSB="0" MPD_INDEX="57" MSB="35" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_AWREGION" DIR="O" ENDIAN="LITTLE" LEFT="47" LSB="0" MPD_INDEX="58" MSB="47" NAME="M_AXI_AWREGION" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="47" LSB="0" MPD_INDEX="59" MSB="47" NAME="M_AXI_AWQOS" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="60" MSB="11" NAME="M_AXI_AWUSER" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="61" MSB="11" NAME="M_AXI_AWVALID" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="62" MSB="11" NAME="M_AXI_AWREADY" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_WID" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="63" MSB="11" NAME="M_AXI_WID" RIGHT="0" SIGNAME="axi_interconnect_1_M_WID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="383" LSB="0" MPD_INDEX="64" MSB="383" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="47" LSB="0" MPD_INDEX="65" MSB="47" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[(((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_WLAST" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="66" MSB="11" NAME="M_AXI_WLAST" RIGHT="0" SIGNAME="axi_interconnect_1_M_WLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_WUSER" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="67" MSB="11" NAME="M_AXI_WUSER" RIGHT="0" SIGNAME="axi_interconnect_1_M_WUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="68" MSB="11" NAME="M_AXI_WVALID" RIGHT="0" SIGNAME="axi_interconnect_1_M_WVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="69" MSB="11" NAME="M_AXI_WREADY" RIGHT="0" SIGNAME="axi_interconnect_1_M_WREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_BID" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="70" MSB="11" NAME="M_AXI_BID" RIGHT="0" SIGNAME="axi_interconnect_1_M_BID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="71" MSB="23" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_BUSER" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="72" MSB="11" NAME="M_AXI_BUSER" RIGHT="0" SIGNAME="axi_interconnect_1_M_BUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="73" MSB="11" NAME="M_AXI_BVALID" RIGHT="0" SIGNAME="axi_interconnect_1_M_BVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="74" MSB="11" NAME="M_AXI_BREADY" RIGHT="0" SIGNAME="axi_interconnect_1_M_BREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_ARID" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="75" MSB="11" NAME="M_AXI_ARID" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="383" LSB="0" MPD_INDEX="76" MSB="383" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="95" LSB="0" MPD_INDEX="77" MSB="95" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="35" LSB="0" MPD_INDEX="78" MSB="35" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="79" MSB="23" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_ARLOCK" DIR="O" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="80" MSB="23" NAME="M_AXI_ARLOCK" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="47" LSB="0" MPD_INDEX="81" MSB="47" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="35" LSB="0" MPD_INDEX="82" MSB="35" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_ARREGION" DIR="O" ENDIAN="LITTLE" LEFT="47" LSB="0" MPD_INDEX="83" MSB="47" NAME="M_AXI_ARREGION" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="47" LSB="0" MPD_INDEX="84" MSB="47" NAME="M_AXI_ARQOS" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="85" MSB="11" NAME="M_AXI_ARUSER" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="86" MSB="11" NAME="M_AXI_ARVALID" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="87" MSB="11" NAME="M_AXI_ARREADY" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_RID" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="88" MSB="11" NAME="M_AXI_RID" RIGHT="0" SIGNAME="axi_interconnect_1_M_RID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="383" LSB="0" MPD_INDEX="89" MSB="383" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="90" MSB="23" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_RLAST" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="91" MSB="11" NAME="M_AXI_RLAST" RIGHT="0" SIGNAME="axi_interconnect_1_M_RLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_RUSER" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="92" MSB="11" NAME="M_AXI_RUSER" RIGHT="0" SIGNAME="axi_interconnect_1_M_RUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="93" MSB="11" NAME="M_AXI_RVALID" RIGHT="0" SIGNAME="axi_interconnect_1_M_RVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="94" MSB="11" NAME="M_AXI_RREADY" RIGHT="0" SIGNAME="axi_interconnect_1_M_RREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_0" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_1" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_2" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_3" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_4" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_recorder_5" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="btns_4bits_tri_io" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_0" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_1" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_2" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="pwm_signal_out_wkillswitch_3" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_timer_0" PORT="S_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="95" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="96" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="98" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="99" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="100" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="101" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="102" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="103" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="104" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="105" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="106" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="107" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="108" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="109" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="110" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="111" NAME="INTERCONNECT_ARESET_OUT_N" SIGNAME="__NOC__"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="112" MSB="7" NAME="DEBUG_AW_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="113" MSB="7" NAME="DEBUG_AW_ARB_GRANT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="114" MSB="7" NAME="DEBUG_AR_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="115" MSB="7" NAME="DEBUG_AR_ARB_GRANT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="116" NAME="DEBUG_AW_TRANS_QUAL" SIGNAME="__NOC__" VECFORMULA="[(C_MAX_DEBUG_THREADS-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="117" MSB="7" NAME="DEBUG_AW_ACCEPT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="118" MSB="15" NAME="DEBUG_AW_ACTIVE_THREAD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(16-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="119" MSB="7" NAME="DEBUG_AW_ACTIVE_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="120" MSB="7" NAME="DEBUG_AW_ACTIVE_REGION" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="121" MSB="7" NAME="DEBUG_AW_ERROR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="122" MSB="7" NAME="DEBUG_AW_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="123" NAME="DEBUG_AR_TRANS_QUAL" SIGNAME="__NOC__" VECFORMULA="[(C_MAX_DEBUG_THREADS-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="124" MSB="7" NAME="DEBUG_AR_ACCEPT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="125" MSB="15" NAME="DEBUG_AR_ACTIVE_THREAD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(16-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="126" MSB="7" NAME="DEBUG_AR_ACTIVE_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="127" MSB="7" NAME="DEBUG_AR_ACTIVE_REGION" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="128" MSB="7" NAME="DEBUG_AR_ERROR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="129" MSB="7" NAME="DEBUG_AR_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="130" MSB="7" NAME="DEBUG_B_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="131" MSB="7" NAME="DEBUG_R_BEAT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="132" MSB="7" NAME="DEBUG_R_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="133" MSB="7" NAME="DEBUG_AW_ISSUING_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="134" MSB="7" NAME="DEBUG_AR_ISSUING_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="135" MSB="7" NAME="DEBUG_W_BEAT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="136" MSB="7" NAME="DEBUG_W_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="137" MSB="7" NAME="DEBUG_BID_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="138" NAME="DEBUG_BID_ERROR" SIGNAME="__NOC__"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="139" MSB="7" NAME="DEBUG_RID_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="140" NAME="DEBUG_RID_ERROR" SIGNAME="__NOC__"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="141" MSB="31" NAME="DEBUG_SR_SC_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="142" MSB="23" NAME="DEBUG_SR_SC_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="143" MSB="31" NAME="DEBUG_SR_SC_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="144" MSB="23" NAME="DEBUG_SR_SC_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="145" MSB="4" NAME="DEBUG_SR_SC_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="146" MSB="31" NAME="DEBUG_SR_SC_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="147" MSB="5" NAME="DEBUG_SR_SC_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="148" MSB="31" NAME="DEBUG_SR_SC_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="149" MSB="6" NAME="DEBUG_SR_SC_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="150" MSB="31" NAME="DEBUG_SC_SF_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="151" MSB="23" NAME="DEBUG_SC_SF_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="152" MSB="31" NAME="DEBUG_SC_SF_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="153" MSB="23" NAME="DEBUG_SC_SF_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="154" MSB="4" NAME="DEBUG_SC_SF_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="155" MSB="31" NAME="DEBUG_SC_SF_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="156" MSB="5" NAME="DEBUG_SC_SF_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="157" MSB="31" NAME="DEBUG_SC_SF_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="158" MSB="6" NAME="DEBUG_SC_SF_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="159" MSB="31" NAME="DEBUG_SF_CB_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="160" MSB="23" NAME="DEBUG_SF_CB_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="161" MSB="31" NAME="DEBUG_SF_CB_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="162" MSB="23" NAME="DEBUG_SF_CB_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="163" MSB="4" NAME="DEBUG_SF_CB_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="164" MSB="31" NAME="DEBUG_SF_CB_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="165" MSB="5" NAME="DEBUG_SF_CB_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="166" MSB="31" NAME="DEBUG_SF_CB_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="167" MSB="6" NAME="DEBUG_SF_CB_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="168" MSB="31" NAME="DEBUG_CB_MF_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="169" MSB="23" NAME="DEBUG_CB_MF_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="170" MSB="31" NAME="DEBUG_CB_MF_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="171" MSB="23" NAME="DEBUG_CB_MF_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="172" MSB="4" NAME="DEBUG_CB_MF_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="173" MSB="31" NAME="DEBUG_CB_MF_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="174" MSB="5" NAME="DEBUG_CB_MF_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="175" MSB="31" NAME="DEBUG_CB_MF_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="176" MSB="6" NAME="DEBUG_CB_MF_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="177" MSB="31" NAME="DEBUG_MF_MC_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="178" MSB="23" NAME="DEBUG_MF_MC_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="179" MSB="31" NAME="DEBUG_MF_MC_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="180" MSB="23" NAME="DEBUG_MF_MC_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="181" MSB="4" NAME="DEBUG_MF_MC_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="182" MSB="31" NAME="DEBUG_MF_MC_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="183" MSB="5" NAME="DEBUG_MF_MC_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="184" MSB="31" NAME="DEBUG_MF_MC_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="185" MSB="6" NAME="DEBUG_MF_MC_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="186" MSB="31" NAME="DEBUG_MC_MP_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="187" MSB="23" NAME="DEBUG_MC_MP_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="188" MSB="31" NAME="DEBUG_MC_MP_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="189" MSB="23" NAME="DEBUG_MC_MP_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="190" MSB="4" NAME="DEBUG_MC_MP_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="191" MSB="31" NAME="DEBUG_MC_MP_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="192" MSB="5" NAME="DEBUG_MC_MP_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="193" MSB="31" NAME="DEBUG_MC_MP_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="194" MSB="6" NAME="DEBUG_MC_MP_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="195" MSB="31" NAME="DEBUG_MP_MR_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="196" MSB="23" NAME="DEBUG_MP_MR_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="197" MSB="31" NAME="DEBUG_MP_MR_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="198" MSB="23" NAME="DEBUG_MP_MR_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="199" MSB="4" NAME="DEBUG_MP_MR_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="200" MSB="31" NAME="DEBUG_MP_MR_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="201" MSB="5" NAME="DEBUG_MP_MR_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="202" MSB="31" NAME="DEBUG_MP_MR_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="203" MSB="6" NAME="DEBUG_MP_MR_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="INTERCONNECT_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.04.a" INSTANCE="pwm_recorder_1" IPTYPE="PERIPHERAL" MHS_INDEX="4" MODCLASS="PERIPHERAL" MODTYPE="pwm_recorder">
-      <DESCRIPTION TYPE="SHORT">PWM_RECORDER</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_local"/>
-      <PARAMETERS>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_S_AXI_MIN_SIZE" TYPE="std_logic_vector" VALUE="0x000001ff"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_USE_WSTRB" TYPE="INTEGER" VALUE="0"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_DPHASE_TIMEOUT" TYPE="INTEGER" VALUE="8"/>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x76e80000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x76e8ffff"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_NUM_REG" TYPE="INTEGER" VALUE="1"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_NUM_MEM" TYPE="INTEGER" VALUE="1"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_SLV_AWIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_SLV_DWIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="12" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="pwm_in" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="19" NAME="pwm_in_master" SIGNAME="pwm_recorder_1_pwm_in_master">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="External Ports" PORT="pwm_recorder_1_pwm_in_master_pin"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="5" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="6" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="7" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="8" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="9" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="10" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="1994915840" BASENAME="C_BASEADDR" BASEVALUE="0x76e80000" HIGHDECIMAL="1994981375" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e8ffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.04.a" INSTANCE="pwm_recorder_2" IPTYPE="PERIPHERAL" MHS_INDEX="5" MODCLASS="PERIPHERAL" MODTYPE="pwm_recorder">
-      <DESCRIPTION TYPE="SHORT">PWM_RECORDER</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_local"/>
-      <PARAMETERS>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_S_AXI_MIN_SIZE" TYPE="std_logic_vector" VALUE="0x000001ff"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_USE_WSTRB" TYPE="INTEGER" VALUE="0"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_DPHASE_TIMEOUT" TYPE="INTEGER" VALUE="8"/>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x76e60000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x76e6ffff"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_NUM_REG" TYPE="INTEGER" VALUE="1"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_NUM_MEM" TYPE="INTEGER" VALUE="1"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_SLV_AWIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_SLV_DWIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="12" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="pwm_in" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="19" NAME="pwm_in_master" SIGNAME="pwm_recorder_2_pwm_in_master">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="External Ports" PORT="pwm_recorder_2_pwm_in_master_pin"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="5" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="6" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="7" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="8" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="9" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="10" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="1994784768" BASENAME="C_BASEADDR" BASEVALUE="0x76e60000" HIGHDECIMAL="1994850303" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e6ffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.04.a" INSTANCE="pwm_recorder_3" IPTYPE="PERIPHERAL" MHS_INDEX="6" MODCLASS="PERIPHERAL" MODTYPE="pwm_recorder">
-      <DESCRIPTION TYPE="SHORT">PWM_RECORDER</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_local"/>
-      <PARAMETERS>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_S_AXI_MIN_SIZE" TYPE="std_logic_vector" VALUE="0x000001ff"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_USE_WSTRB" TYPE="INTEGER" VALUE="0"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_DPHASE_TIMEOUT" TYPE="INTEGER" VALUE="8"/>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x76e40000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x76e4ffff"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_NUM_REG" TYPE="INTEGER" VALUE="1"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_NUM_MEM" TYPE="INTEGER" VALUE="1"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_SLV_AWIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_SLV_DWIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="12" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="pwm_in" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="19" NAME="pwm_in_master" SIGNAME="pwm_recorder_3_pwm_in_master">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="External Ports" PORT="pwm_recorder_3_pwm_in_master_pin"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="5" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="6" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="7" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="8" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="9" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="10" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="1994653696" BASENAME="C_BASEADDR" BASEVALUE="0x76e40000" HIGHDECIMAL="1994719231" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e4ffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.04.a" INSTANCE="pwm_recorder_4" IPTYPE="PERIPHERAL" MHS_INDEX="7" MODCLASS="PERIPHERAL" MODTYPE="pwm_recorder">
-      <DESCRIPTION TYPE="SHORT">PWM_RECORDER</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_local"/>
-      <PARAMETERS>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_S_AXI_MIN_SIZE" TYPE="std_logic_vector" VALUE="0x000001ff"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_USE_WSTRB" TYPE="INTEGER" VALUE="0"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_DPHASE_TIMEOUT" TYPE="INTEGER" VALUE="8"/>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x76e20000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x76e2ffff"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_NUM_REG" TYPE="INTEGER" VALUE="1"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_NUM_MEM" TYPE="INTEGER" VALUE="1"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_SLV_AWIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_SLV_DWIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="12" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="pwm_in" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="19" NAME="pwm_in_master" SIGNAME="pwm_recorder_4_pwm_in_master">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="External Ports" PORT="pwm_recorder_4_pwm_in_master_pin"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="5" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="6" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="7" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="8" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="9" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="10" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="1994522624" BASENAME="C_BASEADDR" BASEVALUE="0x76e20000" HIGHDECIMAL="1994588159" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e2ffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.04.a" INSTANCE="pwm_recorder_5" IPTYPE="PERIPHERAL" MHS_INDEX="8" MODCLASS="PERIPHERAL" MODTYPE="pwm_recorder">
-      <DESCRIPTION TYPE="SHORT">PWM_RECORDER</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_local"/>
-      <PARAMETERS>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_S_AXI_MIN_SIZE" TYPE="std_logic_vector" VALUE="0x000001ff"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_USE_WSTRB" TYPE="INTEGER" VALUE="0"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_DPHASE_TIMEOUT" TYPE="INTEGER" VALUE="8"/>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x76e00000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x76e0ffff"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_NUM_REG" TYPE="INTEGER" VALUE="1"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_NUM_MEM" TYPE="INTEGER" VALUE="1"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_SLV_AWIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_SLV_DWIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="12" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="pwm_in" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="19" NAME="pwm_in_master" SIGNAME="pwm_recorder_5_pwm_in_master">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="External Ports" PORT="pwm_recorder_5_pwm_in_master_pin"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="5" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="6" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="7" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="8" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="9" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="10" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="1994391552" BASENAME="C_BASEADDR" BASEVALUE="0x76e00000" HIGHDECIMAL="1994457087" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e0ffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.01.b" INSTANCE="btns_4bits_tri_io" IPTYPE="PERIPHERAL" MHS_INDEX="9" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio">
-      <DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the AXI bus.</DESCRIPTION>
-      <DOCUMENTATION>
-        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_gpio;v=v1_01_b;d=ds744_axi_gpio.pdf" TYPE="IP"/>
-      </DOCUMENTATION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq">
-          <DESCRIPTION>Device Family</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_INSTANCE" TYPE="STRING" VALUE="BTNs_4Bits_TRI_IO"/>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="2" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x41200000">
-          <DESCRIPTION>AXI Base Address </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="3" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4120ffff">
-          <DESCRIPTION>AXI High Address</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="4" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="9">
-          <DESCRIPTION>AXI Address Width</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="5" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
-          <DESCRIPTION>AXI Data Width</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="6" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="4">
-          <DESCRIPTION>GPIO Data Channel Width</DESCRIPTION>
-          <DESCRIPTION>GPIO Data Width</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="7" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32">
-          <DESCRIPTION>GPIO2 Data Channel Width</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="8" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="1">
-          <DESCRIPTION>Channel 1 is Input Only </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>Channel 2 is Input Only </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>GPIO Supports Interrupts</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000">
-          <DESCRIPTION>Channel 1 Data Out Default Value </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="12" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff">
-          <DESCRIPTION>Channel 1 3-state Default Value </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="13" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>Enable Channel 2 </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="14" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000">
-          <DESCRIPTION>Channel 2 Data Out Default Value </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="15" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff">
-          <DESCRIPTION>Channel 2 3-state Default Value </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="16" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
-          <DESCRIPTION>AXI Protocol</DESCRIPTION>
-        </PARAMETER>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="1" MPD_INDEX="20" MSB="3" NAME="GPIO_IO_I" RIGHT="0" SIGNAME="BTNs_4Bits_TRI_IO_GPIO_IO_I" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="External Ports" PORT="BTNs_4Bits_TRI_IO_GPIO_IO_I_pin"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="2" MSB="8" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[8:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="12" MSB="8" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[8:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="19" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="21" MSB="3" NAME="GPIO_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="22" MSB="3" NAME="GPIO_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
-        <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="23" MSB="31" NAME="GPIO2_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="24" MSB="31" NAME="GPIO2_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="25" MSB="31" NAME="GPIO2_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
-        <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" LEFT="3" LSB="0" MPD_INDEX="26" MSB="3" NAME="GPIO_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
-          <DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
-        </PORT>
-        <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="27" MSB="31" NAME="GPIO2_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[(C_GPIO2_WIDTH-1):0]">
-          <DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <IOINTERFACES>
-        <IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_AXI_GPIO_V1">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/>
-            <PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/>
-            <PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/>
-            <PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/>
-            <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/>
-            <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/>
-            <PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/>
-            <PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/>
-          </PORTMAPS>
-        </IOINTERFACE>
-      </IOINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="1092616192" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHDECIMAL="1092681727" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="pwm_signal_out_wkillswitch_0" IPTYPE="PERIPHERAL" MHS_INDEX="10" MODCLASS="PERIPHERAL" MODTYPE="pwm_signal_out_wkillswitch">
-      <DESCRIPTION TYPE="SHORT">PWM_SIGNAL_OUT_WKILLSWITCH</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_local"/>
-      <PARAMETERS>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_S_AXI_MIN_SIZE" TYPE="std_logic_vector" VALUE="0x000001ff"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_USE_WSTRB" TYPE="INTEGER" VALUE="0"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_DPHASE_TIMEOUT" TYPE="INTEGER" VALUE="8"/>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x79460000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x7946ffff"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_NUM_REG" TYPE="INTEGER" VALUE="1"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_NUM_MEM" TYPE="INTEGER" VALUE="1"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_SLV_AWIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_SLV_DWIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="12" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="19" NAME="pwm_out_sm" SIGNAME="pwm_signal_out_wkillswitch_0_pwm_out_sm">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="External Ports" PORT="pwm_signal_out_wkillswitch_0_pwm_out_sm_pin"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="5" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="6" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="7" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="8" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="9" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="10" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="2034630656" BASENAME="C_BASEADDR" BASEVALUE="0x79460000" HIGHDECIMAL="2034696191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7946ffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="pwm_signal_out_wkillswitch_1" IPTYPE="PERIPHERAL" MHS_INDEX="11" MODCLASS="PERIPHERAL" MODTYPE="pwm_signal_out_wkillswitch">
-      <DESCRIPTION TYPE="SHORT">PWM_SIGNAL_OUT_WKILLSWITCH</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_local"/>
-      <PARAMETERS>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_S_AXI_MIN_SIZE" TYPE="std_logic_vector" VALUE="0x000001ff"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_USE_WSTRB" TYPE="INTEGER" VALUE="0"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_DPHASE_TIMEOUT" TYPE="INTEGER" VALUE="8"/>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x79440000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x7944ffff"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_NUM_REG" TYPE="INTEGER" VALUE="1"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_NUM_MEM" TYPE="INTEGER" VALUE="1"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_SLV_AWIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_SLV_DWIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="12" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="19" NAME="pwm_out_sm" SIGNAME="pwm_signal_out_wkillswitch_1_pwm_out_sm">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="External Ports" PORT="pwm_signal_out_wkillswitch_1_pwm_out_sm_pin"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="5" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="6" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="7" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="8" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="9" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="10" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="2034499584" BASENAME="C_BASEADDR" BASEVALUE="0x79440000" HIGHDECIMAL="2034565119" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7944ffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="pwm_signal_out_wkillswitch_2" IPTYPE="PERIPHERAL" MHS_INDEX="12" MODCLASS="PERIPHERAL" MODTYPE="pwm_signal_out_wkillswitch">
-      <DESCRIPTION TYPE="SHORT">PWM_SIGNAL_OUT_WKILLSWITCH</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_local"/>
-      <PARAMETERS>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_S_AXI_MIN_SIZE" TYPE="std_logic_vector" VALUE="0x000001ff"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_USE_WSTRB" TYPE="INTEGER" VALUE="0"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_DPHASE_TIMEOUT" TYPE="INTEGER" VALUE="8"/>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x79420000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x7942ffff"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_NUM_REG" TYPE="INTEGER" VALUE="1"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_NUM_MEM" TYPE="INTEGER" VALUE="1"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_SLV_AWIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_SLV_DWIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="12" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="19" NAME="pwm_out_sm" SIGNAME="pwm_signal_out_wkillswitch_2_pwm_out_sm">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="External Ports" PORT="pwm_signal_out_wkillswitch_2_pwm_out_sm_pin"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="5" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="6" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="7" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="8" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="9" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="10" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="2034368512" BASENAME="C_BASEADDR" BASEVALUE="0x79420000" HIGHDECIMAL="2034434047" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7942ffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="pwm_signal_out_wkillswitch_3" IPTYPE="PERIPHERAL" MHS_INDEX="13" MODCLASS="PERIPHERAL" MODTYPE="pwm_signal_out_wkillswitch">
-      <DESCRIPTION TYPE="SHORT">PWM_SIGNAL_OUT_WKILLSWITCH</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_local"/>
-      <PARAMETERS>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_S_AXI_MIN_SIZE" TYPE="std_logic_vector" VALUE="0x000001ff"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_USE_WSTRB" TYPE="INTEGER" VALUE="0"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_DPHASE_TIMEOUT" TYPE="INTEGER" VALUE="8"/>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x79400000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x7940ffff"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_NUM_REG" TYPE="INTEGER" VALUE="1"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_NUM_MEM" TYPE="INTEGER" VALUE="1"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_SLV_AWIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_SLV_DWIDTH" TYPE="INTEGER" VALUE="32"/>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="12" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="19" NAME="pwm_out_sm" SIGNAME="pwm_signal_out_wkillswitch_3_pwm_out_sm">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="External Ports" PORT="pwm_signal_out_wkillswitch_3_pwm_out_sm_pin"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="5" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="6" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="7" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="8" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="9" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="10" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="2034237440" BASENAME="C_BASEADDR" BASEVALUE="0x79400000" HIGHDECIMAL="2034302975" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7940ffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.03.a" INSTANCE="axi_timer_0" IPTYPE="PERIPHERAL" MHS_INDEX="14" MODCLASS="PERIPHERAL" MODTYPE="axi_timer">
-      <DESCRIPTION TYPE="SHORT">AXI Timer/Counter</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">Timer counter with AXI interface</DESCRIPTION>
-      <DOCUMENTATION>
-        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_timer;v=v1_03_a;d=axi_timer_ds764.pdf" TYPE="IP"/>
-      </DOCUMENTATION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
-          <DESCRIPTION>AXI Protocol</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq">
-          <DESCRIPTION>Device Family</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_INSTANCE" TYPE="STRING" VALUE="axi_timer_0">
-          <DESCRIPTION>C_INSTANCE</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_COUNT_WIDTH" TYPE="INTEGER" VALUE="32">
-          <DESCRIPTION>The Width of Counter in Timer</DESCRIPTION>
-          <DESCRIPTION>Count Width</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_ONE_TIMER_ONLY" TYPE="INTEGER" VALUE="0">
-          <DESCRIPTION>Only One Timer is present</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="5" NAME="C_TRIG0_ASSERT" TYPE="std_logic" VALUE="1">
-          <DESCRIPTION>TRIG0 Active Level</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="6" NAME="C_TRIG1_ASSERT" TYPE="std_logic" VALUE="1">
-          <DESCRIPTION>TRIG1 Active Level</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="7" NAME="C_GEN0_ASSERT" TYPE="std_logic" VALUE="1">
-          <DESCRIPTION>GEN0 Active Level</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_GEN1_ASSERT" TYPE="std_logic" VALUE="1">
-          <DESCRIPTION>GEN1 Active Level</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="9" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x42800000">
-          <DESCRIPTION>AXI Base Address </DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="10" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4280ffff">
-          <DESCRIPTION>AXI High Address</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="11" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="5">
-          <DESCRIPTION>AXI Address Width</DESCRIPTION>
-        </PARAMETER>
-        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="12" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
-          <DESCRIPTION>AXI Data Width</DESCRIPTION>
-        </PARAMETER>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="7" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="I" MPD_INDEX="0" NAME="CaptureTrig0" SIGNAME="__NOC__">
-          <DESCRIPTION>Capture Trig 0</DESCRIPTION>
-        </PORT>
-        <PORT DIR="I" MPD_INDEX="1" NAME="CaptureTrig1" SIGNAME="__NOC__">
-          <DESCRIPTION>Capture Trig 1</DESCRIPTION>
-        </PORT>
-        <PORT DIR="O" MPD_INDEX="2" NAME="GenerateOut0" SIGNAME="__NOC__">
-          <DESCRIPTION>Generate Out 0</DESCRIPTION>
-        </PORT>
-        <PORT DIR="O" MPD_INDEX="3" NAME="GenerateOut1" SIGNAME="__NOC__">
-          <DESCRIPTION>Generate Out 1</DESCRIPTION>
-        </PORT>
-        <PORT DIR="O" MPD_INDEX="4" NAME="PWM0" SIGNAME="__NOC__">
-          <DESCRIPTION>Pulse Width Modulation 0</DESCRIPTION>
-        </PORT>
-        <PORT DIR="O" MPD_INDEX="5" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="I" MPD_INDEX="6" NAME="Freeze" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="8" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="9" MSB="4" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[4:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="10" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="13" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="19" MSB="4" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[4:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="20" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="21" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="22" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="23" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="24" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="25" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="1115684864" BASENAME="C_BASEADDR" BASEVALUE="0x42800000" HIGHDECIMAL="1115750399" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4280ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.00.a" INSTANCE="ps7_axi_interconnect_0" IPTYPE="BUS" IS_CROSSBAR="TRUE" MHS_INDEX="15" MODCLASS="BUS" MODTYPE="ps7_axi_interconnect">
-      <DESCRIPTION TYPE="SHORT">PS7 AXI Interconnect</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">PS7 AXI4 Memory-Mapped Interconnect</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS/>
-      <PORTS>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="BREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="114" NAME="M_AXI_GP0_BREADY" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_BREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="ARVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="112" NAME="M_AXI_GP0_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_ARVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="AWVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="113" NAME="M_AXI_GP0_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_AWVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="WVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="117" NAME="M_AXI_GP0_WVALID" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_WVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="AWID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="4" MPD_INDEX="119" MSB="31" NAME="M_AXI_GP0_AWID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_AWID" VECFORMULA="[32-1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="RREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="115" NAME="M_AXI_GP0_RREADY" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_RREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="ARSIZE" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="6" MPD_INDEX="123" MSB="2" NAME="M_AXI_GP0_ARSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_ARSIZE" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="AWREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="141" NAME="M_AXI_GP0_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_AWREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="ARID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="8" MPD_INDEX="118" MSB="31" NAME="M_AXI_GP0_ARID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_ARID" VECFORMULA="[32-1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="WID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="9" MPD_INDEX="120" MSB="31" NAME="M_AXI_GP0_WID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_WID" VECFORMULA="[32-1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="AWBURST" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="10" MPD_INDEX="124" MSB="1" NAME="M_AXI_GP0_AWBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_AWBURST" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="ARBURST" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="11" MPD_INDEX="121" MSB="1" NAME="M_AXI_GP0_ARBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_ARBURST" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="ARLOCK" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="12" MPD_INDEX="122" MSB="1" NAME="M_AXI_GP0_ARLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_ARLOCK" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="AWLOCK" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="13" MPD_INDEX="125" MSB="1" NAME="M_AXI_GP0_AWLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_AWLOCK" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="AWSIZE" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="14" MPD_INDEX="126" MSB="2" NAME="M_AXI_GP0_AWSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_AWSIZE" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="ARPROT" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="15" MPD_INDEX="127" MSB="2" NAME="M_AXI_GP0_ARPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_ARPROT" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="AWPROT" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="16" MPD_INDEX="128" MSB="2" NAME="M_AXI_GP0_AWPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_AWPROT" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="ARADDR" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="17" MPD_INDEX="129" MSB="31" NAME="M_AXI_GP0_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_ARADDR" VECFORMULA="[31:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="BID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="18" MPD_INDEX="146" MSB="31" NAME="M_AXI_GP0_BID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_BID" VECFORMULA="[32-1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="AWADDR" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="19" MPD_INDEX="130" MSB="31" NAME="M_AXI_GP0_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_AWADDR" VECFORMULA="[31:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="WDATA" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="20" MPD_INDEX="131" MSB="31" NAME="M_AXI_GP0_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_WDATA" VECFORMULA="[31:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="ARCACHE" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="21" MPD_INDEX="132" MSB="3" NAME="M_AXI_GP0_ARCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_ARCACHE" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="AWQOS" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="22" MPD_INDEX="137" MSB="3" NAME="M_AXI_GP0_AWQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_AWQOS" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="ARLEN" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="23" MPD_INDEX="133" MSB="3" NAME="M_AXI_GP0_ARLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_ARLEN" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="ARQOS" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="24" MPD_INDEX="134" MSB="3" NAME="M_AXI_GP0_ARQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_ARQOS" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="AWCACHE" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="25" MPD_INDEX="135" MSB="3" NAME="M_AXI_GP0_AWCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_AWCACHE" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="WREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="26" MPD_INDEX="145" NAME="M_AXI_GP0_WREADY" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_WREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="AWLEN" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="27" MPD_INDEX="136" MSB="3" NAME="M_AXI_GP0_AWLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_AWLEN" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="WSTRB" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="28" MPD_INDEX="138" MSB="3" NAME="M_AXI_GP0_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_WSTRB" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="29" MPD_INDEX="139" NAME="M_AXI_GP0_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="ARREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="30" MPD_INDEX="140" NAME="M_AXI_GP0_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_ARREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="BVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="31" MPD_INDEX="142" NAME="M_AXI_GP0_BVALID" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_BVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="RLAST" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="32" MPD_INDEX="143" NAME="M_AXI_GP0_RLAST" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_RLAST">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="RVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="33" MPD_INDEX="144" NAME="M_AXI_GP0_RVALID" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_RVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="RID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="34" MPD_INDEX="147" MSB="31" NAME="M_AXI_GP0_RID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_RID" VECFORMULA="[32-1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="BRESP" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="35" MPD_INDEX="148" MSB="1" NAME="M_AXI_GP0_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="RRESP" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="36" MPD_INDEX="149" MSB="1" NAME="M_AXI_GP0_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="RDATA" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="37" MPD_INDEX="150" MSB="31" NAME="M_AXI_GP0_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_RDATA" VECFORMULA="[31:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="WLAST" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="38" MPD_INDEX="116" NAME="M_AXI_GP0_WLAST" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_WLAST">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="BREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="39" MPD_INDEX="154" NAME="M_AXI_GP1_BREADY" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_BREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="ARQOS" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="40" MPD_INDEX="174" MSB="3" NAME="M_AXI_GP1_ARQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_ARQOS" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="ARID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="41" MPD_INDEX="158" MSB="31" NAME="M_AXI_GP1_ARID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_ARID" VECFORMULA="[32-1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="WID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="42" MPD_INDEX="160" MSB="31" NAME="M_AXI_GP1_WID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_WID" VECFORMULA="[32-1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="AWBURST" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="43" MPD_INDEX="164" MSB="1" NAME="M_AXI_GP1_AWBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_AWBURST" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="ARBURST" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="44" MPD_INDEX="161" MSB="1" NAME="M_AXI_GP1_ARBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_ARBURST" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="ARLOCK" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="45" MPD_INDEX="162" MSB="1" NAME="M_AXI_GP1_ARLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_ARLOCK" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="AWLOCK" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="46" MPD_INDEX="165" MSB="1" NAME="M_AXI_GP1_AWLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_AWLOCK" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="AWSIZE" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="47" MPD_INDEX="166" MSB="2" NAME="M_AXI_GP1_AWSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_AWSIZE" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="ARPROT" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="48" MPD_INDEX="167" MSB="2" NAME="M_AXI_GP1_ARPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_ARPROT" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="AWPROT" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="49" MPD_INDEX="168" MSB="2" NAME="M_AXI_GP1_AWPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_AWPROT" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="ARADDR" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="50" MPD_INDEX="169" MSB="31" NAME="M_AXI_GP1_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_ARADDR" VECFORMULA="[31:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="BID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="51" MPD_INDEX="186" MSB="31" NAME="M_AXI_GP1_BID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_BID" VECFORMULA="[32-1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="AWADDR" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="52" MPD_INDEX="170" MSB="31" NAME="M_AXI_GP1_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_AWADDR" VECFORMULA="[31:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="WDATA" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="53" MPD_INDEX="171" MSB="31" NAME="M_AXI_GP1_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_WDATA" VECFORMULA="[31:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="ARCACHE" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="54" MPD_INDEX="172" MSB="3" NAME="M_AXI_GP1_ARCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_ARCACHE" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="ARLEN" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="55" MPD_INDEX="173" MSB="3" NAME="M_AXI_GP1_ARLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_ARLEN" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="RLAST" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="56" MPD_INDEX="183" NAME="M_AXI_GP1_RLAST" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_RLAST">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="AWQOS" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="57" MPD_INDEX="177" MSB="3" NAME="M_AXI_GP1_AWQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_AWQOS" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="AWREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="58" MPD_INDEX="181" NAME="M_AXI_GP1_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_AWREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="AWCACHE" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="59" MPD_INDEX="175" MSB="3" NAME="M_AXI_GP1_AWCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_AWCACHE" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="AWLEN" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="60" MPD_INDEX="176" MSB="3" NAME="M_AXI_GP1_AWLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_AWLEN" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="WSTRB" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="61" MPD_INDEX="178" MSB="3" NAME="M_AXI_GP1_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_WSTRB" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="WREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="62" MPD_INDEX="185" NAME="M_AXI_GP1_WREADY" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_WREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="63" MPD_INDEX="179" NAME="M_AXI_GP1_ACLK" SIGIS="CLK" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_ACLK">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="ARREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="64" MPD_INDEX="180" NAME="M_AXI_GP1_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_ARREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="BVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="65" MPD_INDEX="182" NAME="M_AXI_GP1_BVALID" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_BVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="RVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="66" MPD_INDEX="184" NAME="M_AXI_GP1_RVALID" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_RVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="RDATA" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="67" MPD_INDEX="190" MSB="31" NAME="M_AXI_GP1_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_RDATA" VECFORMULA="[31:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="RID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="68" MPD_INDEX="187" MSB="31" NAME="M_AXI_GP1_RID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_RID" VECFORMULA="[32-1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="BRESP" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="69" MPD_INDEX="188" MSB="1" NAME="M_AXI_GP1_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="RRESP" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="70" MPD_INDEX="189" MSB="1" NAME="M_AXI_GP1_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="RREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="71" MPD_INDEX="155" NAME="M_AXI_GP1_RREADY" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_RREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="WVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="72" MPD_INDEX="157" NAME="M_AXI_GP1_WVALID" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_WVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="ARVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="73" MPD_INDEX="152" NAME="M_AXI_GP1_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_ARVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="AWID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="74" MPD_INDEX="159" MSB="31" NAME="M_AXI_GP1_AWID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_AWID" VECFORMULA="[32-1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="WLAST" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="75" MPD_INDEX="156" NAME="M_AXI_GP1_WLAST" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_WLAST">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="ARSIZE" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="76" MPD_INDEX="163" MSB="2" NAME="M_AXI_GP1_ARSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_ARSIZE" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="AWVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="77" MPD_INDEX="153" NAME="M_AXI_GP1_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_AWVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="WREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="78" MPD_INDEX="237" NAME="S_AXI_GP1_WREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_WREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="RVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="79" MPD_INDEX="318" NAME="S_AXI_HP0_RVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_RVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="WREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="80" MPD_INDEX="365" NAME="S_AXI_HP1_WREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_WREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="WREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="81" MPD_INDEX="411" NAME="S_AXI_HP2_WREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_WREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="WREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="82" MPD_INDEX="457" NAME="S_AXI_HP3_WREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_WREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="WREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="83" MPD_INDEX="277" NAME="S_AXI_ACP_WREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_WREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="AWID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="84" MPD_INDEX="355" MSB="5" NAME="S_AXI_HP0_AWID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_AWID" VECFORMULA="[(6 - 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="WID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="85" MPD_INDEX="356" MSB="5" NAME="S_AXI_HP0_WID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_WID" VECFORMULA="[(6 - 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="WDATA" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="63" LSB="0" MHS_INDEX="86" MPD_INDEX="357" MSB="63" NAME="S_AXI_HP0_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_WDATA" VECFORMULA="[(64- 1) :0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="WSTRB" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="87" MPD_INDEX="358" MSB="7" NAME="S_AXI_HP0_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_WSTRB" VECFORMULA="[((64/8)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="RLAST" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="88" MPD_INDEX="409" NAME="S_AXI_HP2_RLAST" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_RLAST">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="AWREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="89" MPD_INDEX="407" NAME="S_AXI_HP2_AWREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_AWREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="RVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="90" MPD_INDEX="364" NAME="S_AXI_HP1_RVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_RVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="RRESP" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="91" MPD_INDEX="367" MSB="1" NAME="S_AXI_HP1_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="AWVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="92" MPD_INDEX="377" NAME="S_AXI_HP1_AWVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_AWVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="RREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="93" MPD_INDEX="380" NAME="S_AXI_HP1_RREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_RREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="BID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="94" MPD_INDEX="368" MSB="5" NAME="S_AXI_HP1_BID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_BID" VECFORMULA="[(6 - 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="WLAST" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="95" MPD_INDEX="381" NAME="S_AXI_HP1_WLAST" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_WLAST">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="RID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="96" MPD_INDEX="369" MSB="5" NAME="S_AXI_HP1_RID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_RID" VECFORMULA="[(6 - 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="RDATA" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="63" LSB="0" MHS_INDEX="97" MPD_INDEX="370" MSB="63" NAME="S_AXI_HP1_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_RDATA" VECFORMULA="[(64- 1) :0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="98" MPD_INDEX="375" NAME="S_AXI_HP1_ACLK" SIGIS="CLK" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_ACLK">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="ARVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="99" MPD_INDEX="376" NAME="S_AXI_HP1_ARVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_ARVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="BREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="100" MPD_INDEX="378" NAME="S_AXI_HP1_BREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_BREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="WVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="101" MPD_INDEX="383" NAME="S_AXI_HP1_WVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_WVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="ARSIZE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="102" MPD_INDEX="386" MSB="2" NAME="S_AXI_HP1_ARSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_ARSIZE" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="ARBURST" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="103" MPD_INDEX="384" MSB="1" NAME="S_AXI_HP1_ARBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_ARBURST" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="ARREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="104" MPD_INDEX="406" NAME="S_AXI_HP2_ARREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_ARREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="ARLOCK" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="105" MPD_INDEX="385" MSB="1" NAME="S_AXI_HP1_ARLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_ARLOCK" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="AWBURST" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="106" MPD_INDEX="387" MSB="1" NAME="S_AXI_HP1_AWBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_AWBURST" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="AWLOCK" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="107" MPD_INDEX="388" MSB="1" NAME="S_AXI_HP1_AWLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_AWLOCK" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="AWSIZE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="108" MPD_INDEX="389" MSB="2" NAME="S_AXI_HP1_AWSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_AWSIZE" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="ARPROT" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="109" MPD_INDEX="390" MSB="2" NAME="S_AXI_HP1_ARPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_ARPROT" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="AWPROT" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="110" MPD_INDEX="391" MSB="2" NAME="S_AXI_HP1_AWPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_AWPROT" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="ARADDR" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="111" MPD_INDEX="392" MSB="31" NAME="S_AXI_HP1_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_ARADDR" VECFORMULA="[31:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="AWADDR" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="112" MPD_INDEX="393" MSB="31" NAME="S_AXI_HP1_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_AWADDR" VECFORMULA="[31:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="ARCACHE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="113" MPD_INDEX="394" MSB="3" NAME="S_AXI_HP1_ARCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_ARCACHE" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="ARLEN" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="114" MPD_INDEX="395" MSB="3" NAME="S_AXI_HP1_ARLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_ARLEN" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="ARQOS" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="115" MPD_INDEX="396" MSB="3" NAME="S_AXI_HP1_ARQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_ARQOS" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="RREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="116" MPD_INDEX="287" NAME="S_AXI_ACP_RREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_RREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="RID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="117" MPD_INDEX="281" MSB="2" NAME="S_AXI_ACP_RID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_RID" VECFORMULA="[(3- 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="RDATA" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="63" LSB="0" MHS_INDEX="118" MPD_INDEX="282" MSB="63" NAME="S_AXI_ACP_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_RDATA" VECFORMULA="[63:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="119" MPD_INDEX="283" NAME="S_AXI_ACP_ACLK" SIGIS="CLK" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_ACLK">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="ARVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="120" MPD_INDEX="284" NAME="S_AXI_ACP_ARVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_ARVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="BREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="121" MPD_INDEX="286" NAME="S_AXI_ACP_BREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_BREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="WVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="122" MPD_INDEX="289" NAME="S_AXI_ACP_WVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_WVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="AWQOS" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="123" MPD_INDEX="302" MSB="3" NAME="S_AXI_ACP_AWQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_AWQOS" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="ARID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="124" MPD_INDEX="290" MSB="2" NAME="S_AXI_ACP_ARID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_ARID" VECFORMULA="[(3- 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="ARLEN" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="125" MPD_INDEX="298" MSB="3" NAME="S_AXI_ACP_ARLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_ARLEN" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="ARPROT" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="126" MPD_INDEX="291" MSB="2" NAME="S_AXI_ACP_ARPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_ARPROT" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="AWID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="127" MPD_INDEX="292" MSB="2" NAME="S_AXI_ACP_AWID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_AWID" VECFORMULA="[(3- 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="AWPROT" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="128" MPD_INDEX="293" MSB="2" NAME="S_AXI_ACP_AWPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_AWPROT" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="WID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="129" MPD_INDEX="294" MSB="2" NAME="S_AXI_ACP_WID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_WID" VECFORMULA="[(3- 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="ARADDR" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="130" MPD_INDEX="295" MSB="31" NAME="S_AXI_ACP_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_ARADDR" VECFORMULA="[31:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="AWADDR" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="131" MPD_INDEX="296" MSB="31" NAME="S_AXI_ACP_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_AWADDR" VECFORMULA="[31:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="ARCACHE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="132" MPD_INDEX="297" MSB="3" NAME="S_AXI_ACP_ARCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_ARCACHE" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="ARQOS" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="133" MPD_INDEX="299" MSB="3" NAME="S_AXI_ACP_ARQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_ARQOS" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="ARBURST" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="134" MPD_INDEX="303" MSB="1" NAME="S_AXI_ACP_ARBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_ARBURST" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="AWCACHE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="135" MPD_INDEX="300" MSB="3" NAME="S_AXI_ACP_AWCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_AWCACHE" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="AWBURST" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="136" MPD_INDEX="306" MSB="1" NAME="S_AXI_ACP_AWBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_AWBURST" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="AWLEN" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="137" MPD_INDEX="301" MSB="3" NAME="S_AXI_ACP_AWLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_AWLEN" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="ARSIZE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="138" MPD_INDEX="305" MSB="2" NAME="S_AXI_ACP_ARSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_ARSIZE" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="ARLOCK" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="139" MPD_INDEX="304" MSB="1" NAME="S_AXI_ACP_ARLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_ARLOCK" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="AWLOCK" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="140" MPD_INDEX="307" MSB="1" NAME="S_AXI_ACP_AWLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_AWLOCK" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="AWSIZE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="141" MPD_INDEX="308" MSB="2" NAME="S_AXI_ACP_AWSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_AWSIZE" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="ARUSER" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="4" LSB="0" MHS_INDEX="142" MPD_INDEX="309" MSB="4" NAME="S_AXI_ACP_ARUSER" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_ARUSER" VECFORMULA="[4:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="AWUSER" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="4" LSB="0" MHS_INDEX="143" MPD_INDEX="310" MSB="4" NAME="S_AXI_ACP_AWUSER" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_AWUSER" VECFORMULA="[4:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="WDATA" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="63" LSB="0" MHS_INDEX="144" MPD_INDEX="311" MSB="63" NAME="S_AXI_ACP_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_WDATA" VECFORMULA="[63:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="WSTRB" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="145" MPD_INDEX="312" MSB="7" NAME="S_AXI_ACP_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_WSTRB" VECFORMULA="[7:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="RLAST" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="146" MPD_INDEX="195" NAME="S_AXI_GP0_RLAST" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_RLAST">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="BVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="147" MPD_INDEX="194" NAME="S_AXI_GP0_BVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_BVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="RID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="148" MPD_INDEX="242" MSB="2" NAME="S_AXI_GP1_RID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_RID" VECFORMULA="[(3- 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="149" MPD_INDEX="243" NAME="S_AXI_GP1_ACLK" SIGIS="CLK" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_ACLK">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="ARVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="150" MPD_INDEX="244" NAME="S_AXI_GP1_ARVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_ARVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="BREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="151" MPD_INDEX="246" NAME="S_AXI_GP1_BREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_BREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="WVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="152" MPD_INDEX="249" NAME="S_AXI_GP1_WVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_WVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="ARSIZE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="153" MPD_INDEX="252" MSB="2" NAME="S_AXI_GP1_ARSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_ARSIZE" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="ARBURST" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="154" MPD_INDEX="250" MSB="1" NAME="S_AXI_GP1_ARBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_ARBURST" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="AWREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="155" MPD_INDEX="315" NAME="S_AXI_HP0_AWREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_AWREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="ARLOCK" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="156" MPD_INDEX="251" MSB="1" NAME="S_AXI_GP1_ARLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_ARLOCK" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="AWBURST" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="157" MPD_INDEX="253" MSB="1" NAME="S_AXI_GP1_AWBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_AWBURST" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="AWLOCK" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="158" MPD_INDEX="254" MSB="1" NAME="S_AXI_GP1_AWLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_AWLOCK" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="AWSIZE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="159" MPD_INDEX="255" MSB="2" NAME="S_AXI_GP1_AWSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_AWSIZE" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="ARPROT" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="160" MPD_INDEX="256" MSB="2" NAME="S_AXI_GP1_ARPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_ARPROT" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="AWPROT" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="161" MPD_INDEX="257" MSB="2" NAME="S_AXI_GP1_AWPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_AWPROT" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="ARADDR" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="162" MPD_INDEX="258" MSB="31" NAME="S_AXI_GP1_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_ARADDR" VECFORMULA="[31:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="AWADDR" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="163" MPD_INDEX="259" MSB="31" NAME="S_AXI_GP1_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_AWADDR" VECFORMULA="[31:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="WDATA" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="164" MPD_INDEX="260" MSB="31" NAME="S_AXI_GP1_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_WDATA" VECFORMULA="[31:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="ARCACHE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="165" MPD_INDEX="261" MSB="3" NAME="S_AXI_GP1_ARCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_ARCACHE" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="ARQOS" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="166" MPD_INDEX="263" MSB="3" NAME="S_AXI_GP1_ARQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_ARQOS" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="ARLEN" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="167" MPD_INDEX="262" MSB="3" NAME="S_AXI_GP1_ARLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_ARLEN" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="AWQOS" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="168" MPD_INDEX="266" MSB="3" NAME="S_AXI_GP1_AWQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_AWQOS" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="ARREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="169" MPD_INDEX="314" NAME="S_AXI_HP0_ARREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_ARREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="AWCACHE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="170" MPD_INDEX="264" MSB="3" NAME="S_AXI_GP1_AWCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_AWCACHE" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="AWLEN" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="171" MPD_INDEX="265" MSB="3" NAME="S_AXI_GP1_AWLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_AWLEN" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="WSTRB" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="172" MPD_INDEX="267" MSB="3" NAME="S_AXI_GP1_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_WSTRB" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="ARID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="173" MPD_INDEX="268" MSB="31" NAME="S_AXI_GP1_ARID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_ARID" VECFORMULA="[(32- 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="AWID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="174" MPD_INDEX="269" MSB="31" NAME="S_AXI_GP1_AWID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_AWID" VECFORMULA="[(32- 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="WID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="175" MPD_INDEX="270" MSB="31" NAME="S_AXI_GP1_WID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_WID" VECFORMULA="[(32- 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="RLAST" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="176" MPD_INDEX="363" NAME="S_AXI_HP1_RLAST" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_RLAST">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="AWREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="177" MPD_INDEX="361" NAME="S_AXI_HP1_AWREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_AWREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="RLAST" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="178" MPD_INDEX="317" NAME="S_AXI_HP0_RLAST" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_RLAST">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="BVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="179" MPD_INDEX="316" NAME="S_AXI_HP0_BVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_BVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="ARQOS" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="180" MPD_INDEX="223" MSB="3" NAME="S_AXI_GP0_ARQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_ARQOS" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="AWBURST" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="181" MPD_INDEX="213" MSB="1" NAME="S_AXI_GP0_AWBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_AWBURST" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="AWLOCK" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="182" MPD_INDEX="214" MSB="1" NAME="S_AXI_GP0_AWLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_AWLOCK" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="AWSIZE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="183" MPD_INDEX="215" MSB="2" NAME="S_AXI_GP0_AWSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_AWSIZE" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="ARPROT" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="184" MPD_INDEX="216" MSB="2" NAME="S_AXI_GP0_ARPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_ARPROT" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="AWPROT" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="185" MPD_INDEX="217" MSB="2" NAME="S_AXI_GP0_AWPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_AWPROT" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="ARADDR" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="186" MPD_INDEX="218" MSB="31" NAME="S_AXI_GP0_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_ARADDR" VECFORMULA="[31:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="AWADDR" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="187" MPD_INDEX="219" MSB="31" NAME="S_AXI_GP0_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_AWADDR" VECFORMULA="[31:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="WDATA" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="188" MPD_INDEX="220" MSB="31" NAME="S_AXI_GP0_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_WDATA" VECFORMULA="[31:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="ARCACHE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="189" MPD_INDEX="221" MSB="3" NAME="S_AXI_GP0_ARCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_ARCACHE" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="BVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="190" MPD_INDEX="234" NAME="S_AXI_GP1_BVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_BVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="ARLEN" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="191" MPD_INDEX="222" MSB="3" NAME="S_AXI_GP0_ARLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_ARLEN" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="AWQOS" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="192" MPD_INDEX="226" MSB="3" NAME="S_AXI_GP0_AWQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_AWQOS" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="ARREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="193" MPD_INDEX="232" NAME="S_AXI_GP1_ARREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_ARREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="AWCACHE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="194" MPD_INDEX="224" MSB="3" NAME="S_AXI_GP0_AWCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_AWCACHE" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="WSTRB" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="195" MPD_INDEX="227" MSB="3" NAME="S_AXI_GP0_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_WSTRB" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="ARID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="196" MPD_INDEX="228" MSB="31" NAME="S_AXI_GP0_ARID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_ARID" VECFORMULA="[(32- 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="AWID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="197" MPD_INDEX="229" MSB="31" NAME="S_AXI_GP0_AWID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_AWID" VECFORMULA="[(32- 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="WID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="198" MPD_INDEX="230" MSB="31" NAME="S_AXI_GP0_WID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_WID" VECFORMULA="[(32- 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="BRESP" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="199" MPD_INDEX="320" MSB="1" NAME="S_AXI_HP0_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="WREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="200" MPD_INDEX="319" NAME="S_AXI_HP0_WREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_WREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="RVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="201" MPD_INDEX="236" NAME="S_AXI_GP1_RVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_RVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="RRESP" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="202" MPD_INDEX="239" MSB="1" NAME="S_AXI_GP1_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="AWVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="203" MPD_INDEX="245" NAME="S_AXI_GP1_AWVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_AWVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="RREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="204" MPD_INDEX="247" NAME="S_AXI_GP1_RREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_RREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="RDATA" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="205" MPD_INDEX="240" MSB="31" NAME="S_AXI_GP1_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_RDATA" VECFORMULA="[31:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="WLAST" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="206" MPD_INDEX="248" NAME="S_AXI_GP1_WLAST" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_WLAST">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="BID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="207" MPD_INDEX="241" MSB="2" NAME="S_AXI_GP1_BID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_BID" VECFORMULA="[(3- 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="AWREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="208" MPD_INDEX="193" NAME="S_AXI_GP0_AWREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_AWREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="BRESP" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="209" MPD_INDEX="198" MSB="1" NAME="S_AXI_GP0_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="ARREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="210" MPD_INDEX="192" NAME="S_AXI_GP0_ARREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_ARREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="BRESP" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="211" MPD_INDEX="238" MSB="1" NAME="S_AXI_GP1_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="RLAST" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="212" MPD_INDEX="235" NAME="S_AXI_GP1_RLAST" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_RLAST">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="RVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="213" MPD_INDEX="196" NAME="S_AXI_GP0_RVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_RVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="RRESP" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="214" MPD_INDEX="199" MSB="1" NAME="S_AXI_GP0_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="AWVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="215" MPD_INDEX="205" NAME="S_AXI_GP0_AWVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_AWVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="RREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="216" MPD_INDEX="207" NAME="S_AXI_GP0_RREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_RREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="RDATA" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="217" MPD_INDEX="200" MSB="31" NAME="S_AXI_GP0_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_RDATA" VECFORMULA="[31:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="WLAST" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="218" MPD_INDEX="208" NAME="S_AXI_GP0_WLAST" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_WLAST">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="BID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="219" MPD_INDEX="201" MSB="31" NAME="S_AXI_GP0_BID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_BID" VECFORMULA="[(32- 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="RID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="220" MPD_INDEX="202" MSB="31" NAME="S_AXI_GP0_RID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_RID" VECFORMULA="[(32- 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="221" MPD_INDEX="203" NAME="S_AXI_GP0_ACLK" SIGIS="CLK" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_ACLK">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="ARVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="222" MPD_INDEX="204" NAME="S_AXI_GP0_ARVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_ARVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="BREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="223" MPD_INDEX="206" NAME="S_AXI_GP0_BREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_BREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="WVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="224" MPD_INDEX="209" NAME="S_AXI_GP0_WVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_WVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="ARSIZE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="225" MPD_INDEX="212" MSB="2" NAME="S_AXI_GP0_ARSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_ARSIZE" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="AWLEN" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="226" MPD_INDEX="225" MSB="3" NAME="S_AXI_GP0_AWLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_AWLEN" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP1" DEF_SIGNAME="AWREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="227" MPD_INDEX="233" NAME="S_AXI_GP1_AWREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_AWREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="ARBURST" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="228" MPD_INDEX="210" MSB="1" NAME="S_AXI_GP0_ARBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_ARBURST" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="ARLOCK" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="229" MPD_INDEX="211" MSB="1" NAME="S_AXI_GP0_ARLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_ARLOCK" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="AWSIZE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="230" MPD_INDEX="435" MSB="2" NAME="S_AXI_HP2_AWSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_AWSIZE" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="ARPROT" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="231" MPD_INDEX="436" MSB="2" NAME="S_AXI_HP2_ARPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_ARPROT" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="AWPROT" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="232" MPD_INDEX="437" MSB="2" NAME="S_AXI_HP2_AWPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_AWPROT" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="ARADDR" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="233" MPD_INDEX="438" MSB="31" NAME="S_AXI_HP2_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_ARADDR" VECFORMULA="[31:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="AWADDR" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="234" MPD_INDEX="439" MSB="31" NAME="S_AXI_HP2_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_AWADDR" VECFORMULA="[31:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="ARCACHE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="235" MPD_INDEX="440" MSB="3" NAME="S_AXI_HP2_ARCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_ARCACHE" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="ARLEN" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="236" MPD_INDEX="441" MSB="3" NAME="S_AXI_HP2_ARLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_ARLEN" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="ARQOS" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="237" MPD_INDEX="442" MSB="3" NAME="S_AXI_HP2_ARQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_ARQOS" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="AWCACHE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="238" MPD_INDEX="443" MSB="3" NAME="S_AXI_HP2_AWCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_AWCACHE" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="BRESP" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="239" MPD_INDEX="458" MSB="1" NAME="S_AXI_HP3_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="AWQOS" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="240" MPD_INDEX="445" MSB="3" NAME="S_AXI_HP2_AWQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_AWQOS" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="AWLEN" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="241" MPD_INDEX="444" MSB="3" NAME="S_AXI_HP2_AWLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_AWLEN" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="ARID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="242" MPD_INDEX="446" MSB="5" NAME="S_AXI_HP2_ARID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_ARID" VECFORMULA="[(6- 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="BVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="243" MPD_INDEX="454" NAME="S_AXI_HP3_BVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_BVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="AWID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="244" MPD_INDEX="447" MSB="5" NAME="S_AXI_HP2_AWID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_AWID" VECFORMULA="[(6- 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="WID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="245" MPD_INDEX="448" MSB="5" NAME="S_AXI_HP2_WID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_WID" VECFORMULA="[(6- 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="WDATA" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="63" LSB="0" MHS_INDEX="246" MPD_INDEX="449" MSB="63" NAME="S_AXI_HP2_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_WDATA" VECFORMULA="[(64- 1) :0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="WSTRB" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="247" MPD_INDEX="450" MSB="7" NAME="S_AXI_HP2_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_WSTRB" VECFORMULA="[((64/8)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="RLAST" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="248" MPD_INDEX="275" NAME="S_AXI_ACP_RLAST" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_RLAST">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="ARREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="249" MPD_INDEX="273" NAME="S_AXI_ACP_ARREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_ARREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="RVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="250" MPD_INDEX="456" NAME="S_AXI_HP3_RVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_RVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="RRESP" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="251" MPD_INDEX="459" MSB="1" NAME="S_AXI_HP3_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="AWVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="252" MPD_INDEX="469" NAME="S_AXI_HP3_AWVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_AWVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="RREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="253" MPD_INDEX="472" NAME="S_AXI_HP3_RREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_RREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="BID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="254" MPD_INDEX="460" MSB="5" NAME="S_AXI_HP3_BID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_BID" VECFORMULA="[(6- 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="WLAST" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="255" MPD_INDEX="473" NAME="S_AXI_HP3_WLAST" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_WLAST">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="RID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="256" MPD_INDEX="461" MSB="5" NAME="S_AXI_HP3_RID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_RID" VECFORMULA="[(6- 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="RDATA" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="63" LSB="0" MHS_INDEX="257" MPD_INDEX="462" MSB="63" NAME="S_AXI_HP3_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_RDATA" VECFORMULA="[(64- 1) :0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="258" MPD_INDEX="467" NAME="S_AXI_HP3_ACLK" SIGIS="CLK" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_ACLK">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="ARVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="259" MPD_INDEX="468" NAME="S_AXI_HP3_ARVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_ARVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="BREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="260" MPD_INDEX="470" NAME="S_AXI_HP3_BREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_BREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="WVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="261" MPD_INDEX="475" NAME="S_AXI_HP3_WVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_WVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="ARSIZE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="262" MPD_INDEX="478" MSB="2" NAME="S_AXI_HP3_ARSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_ARSIZE" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="ARBURST" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="263" MPD_INDEX="476" MSB="1" NAME="S_AXI_HP3_ARBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_ARBURST" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="AWREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="264" MPD_INDEX="272" NAME="S_AXI_ACP_AWREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_AWREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="ARLOCK" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="265" MPD_INDEX="477" MSB="1" NAME="S_AXI_HP3_ARLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_ARLOCK" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="AWBURST" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="266" MPD_INDEX="479" MSB="1" NAME="S_AXI_HP3_AWBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_AWBURST" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="AWLOCK" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="267" MPD_INDEX="480" MSB="1" NAME="S_AXI_HP3_AWLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_AWLOCK" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="AWSIZE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="268" MPD_INDEX="481" MSB="2" NAME="S_AXI_HP3_AWSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_AWSIZE" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="ARPROT" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="269" MPD_INDEX="482" MSB="2" NAME="S_AXI_HP3_ARPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_ARPROT" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="AWPROT" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="270" MPD_INDEX="483" MSB="2" NAME="S_AXI_HP3_AWPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_AWPROT" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="ARADDR" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="271" MPD_INDEX="484" MSB="31" NAME="S_AXI_HP3_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_ARADDR" VECFORMULA="[31:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="AWADDR" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="272" MPD_INDEX="485" MSB="31" NAME="S_AXI_HP3_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_AWADDR" VECFORMULA="[31:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="ARCACHE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="273" MPD_INDEX="486" MSB="3" NAME="S_AXI_HP3_ARCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_ARCACHE" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="ARLEN" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="274" MPD_INDEX="487" MSB="3" NAME="S_AXI_HP3_ARLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_ARLEN" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="ARQOS" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="275" MPD_INDEX="488" MSB="3" NAME="S_AXI_HP3_ARQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_ARQOS" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="AWCACHE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="276" MPD_INDEX="489" MSB="3" NAME="S_AXI_HP3_AWCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_AWCACHE" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="BRESP" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="277" MPD_INDEX="278" MSB="1" NAME="S_AXI_ACP_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="AWQOS" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="278" MPD_INDEX="491" MSB="3" NAME="S_AXI_HP3_AWQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_AWQOS" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="AWLEN" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="279" MPD_INDEX="490" MSB="3" NAME="S_AXI_HP3_AWLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_AWLEN" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="ARID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="280" MPD_INDEX="492" MSB="5" NAME="S_AXI_HP3_ARID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_ARID" VECFORMULA="[(6- 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="BVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="281" MPD_INDEX="274" NAME="S_AXI_ACP_BVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_BVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="AWID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="282" MPD_INDEX="493" MSB="5" NAME="S_AXI_HP3_AWID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_AWID" VECFORMULA="[(6- 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="WID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="283" MPD_INDEX="494" MSB="5" NAME="S_AXI_HP3_WID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_WID" VECFORMULA="[(6- 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="WDATA" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="63" LSB="0" MHS_INDEX="284" MPD_INDEX="495" MSB="63" NAME="S_AXI_HP3_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_WDATA" VECFORMULA="[(64- 1) :0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="WSTRB" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="285" MPD_INDEX="496" MSB="7" NAME="S_AXI_HP3_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_WSTRB" VECFORMULA="[((64/8)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="RVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="286" MPD_INDEX="276" NAME="S_AXI_ACP_RVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_RVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="WLAST" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="287" MPD_INDEX="288" NAME="S_AXI_ACP_WLAST" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_WLAST">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="RRESP" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="288" MPD_INDEX="279" MSB="1" NAME="S_AXI_ACP_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="BID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="289" MPD_INDEX="280" MSB="2" NAME="S_AXI_ACP_BID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_BID" VECFORMULA="[(3- 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="AWVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="290" MPD_INDEX="285" NAME="S_AXI_ACP_AWVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_AWVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="AWCACHE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="291" MPD_INDEX="397" MSB="3" NAME="S_AXI_HP1_AWCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_AWCACHE" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="BRESP" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="292" MPD_INDEX="412" MSB="1" NAME="S_AXI_HP2_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="AWQOS" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="293" MPD_INDEX="399" MSB="3" NAME="S_AXI_HP1_AWQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_AWQOS" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="AWLEN" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="294" MPD_INDEX="398" MSB="3" NAME="S_AXI_HP1_AWLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_AWLEN" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="ARID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="295" MPD_INDEX="400" MSB="5" NAME="S_AXI_HP1_ARID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_ARID" VECFORMULA="[(6 - 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="BVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="296" MPD_INDEX="408" NAME="S_AXI_HP2_BVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_BVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="AWID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="297" MPD_INDEX="401" MSB="5" NAME="S_AXI_HP1_AWID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_AWID" VECFORMULA="[(6 - 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="WID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="298" MPD_INDEX="402" MSB="5" NAME="S_AXI_HP1_WID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_WID" VECFORMULA="[(6 - 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="WDATA" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="63" LSB="0" MHS_INDEX="299" MPD_INDEX="403" MSB="63" NAME="S_AXI_HP1_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_WDATA" VECFORMULA="[(64 - 1) :0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="WSTRB" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="300" MPD_INDEX="404" MSB="7" NAME="S_AXI_HP1_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_WSTRB" VECFORMULA="[((64/8)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="RLAST" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="301" MPD_INDEX="455" NAME="S_AXI_HP3_RLAST" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_RLAST">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="AWREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="302" MPD_INDEX="453" NAME="S_AXI_HP3_AWREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_AWREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="RVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="303" MPD_INDEX="410" NAME="S_AXI_HP2_RVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_RVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="RRESP" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="304" MPD_INDEX="413" MSB="1" NAME="S_AXI_HP2_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="AWVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="305" MPD_INDEX="423" NAME="S_AXI_HP2_AWVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_AWVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="RREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="306" MPD_INDEX="426" NAME="S_AXI_HP2_RREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_RREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="BID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="307" MPD_INDEX="414" MSB="5" NAME="S_AXI_HP2_BID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_BID" VECFORMULA="[(6- 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="WLAST" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="308" MPD_INDEX="427" NAME="S_AXI_HP2_WLAST" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_WLAST">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="RID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="309" MPD_INDEX="415" MSB="5" NAME="S_AXI_HP2_RID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_RID" VECFORMULA="[(6- 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="RDATA" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="63" LSB="0" MHS_INDEX="310" MPD_INDEX="416" MSB="63" NAME="S_AXI_HP2_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_RDATA" VECFORMULA="[(64- 1) :0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="311" MPD_INDEX="421" NAME="S_AXI_HP2_ACLK" SIGIS="CLK" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_ACLK">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="ARVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="312" MPD_INDEX="422" NAME="S_AXI_HP2_ARVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_ARVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="BREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="313" MPD_INDEX="424" NAME="S_AXI_HP2_BREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_BREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="WVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="314" MPD_INDEX="429" NAME="S_AXI_HP2_WVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_WVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="ARSIZE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="315" MPD_INDEX="432" MSB="2" NAME="S_AXI_HP2_ARSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_ARSIZE" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="ARBURST" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="316" MPD_INDEX="430" MSB="1" NAME="S_AXI_HP2_ARBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_ARBURST" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP3" DEF_SIGNAME="ARREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="317" MPD_INDEX="452" NAME="S_AXI_HP3_ARREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_ARREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="ARLOCK" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="318" MPD_INDEX="431" MSB="1" NAME="S_AXI_HP2_ARLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_ARLOCK" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="AWBURST" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="319" MPD_INDEX="433" MSB="1" NAME="S_AXI_HP2_AWBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_AWBURST" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="AWLOCK" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="320" MPD_INDEX="434" MSB="1" NAME="S_AXI_HP2_AWLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_AWLOCK" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="RRESP" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="321" MPD_INDEX="321" MSB="1" NAME="S_AXI_HP0_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="AWVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="322" MPD_INDEX="331" NAME="S_AXI_HP0_AWVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_AWVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="RREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="323" MPD_INDEX="334" NAME="S_AXI_HP0_RREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_RREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="BID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="324" MPD_INDEX="322" MSB="5" NAME="S_AXI_HP0_BID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_BID" VECFORMULA="[(6 - 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="WLAST" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="325" MPD_INDEX="335" NAME="S_AXI_HP0_WLAST" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_WLAST">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="RID" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="326" MPD_INDEX="323" MSB="5" NAME="S_AXI_HP0_RID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_RID" VECFORMULA="[(6 - 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="RDATA" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="63" LSB="0" MHS_INDEX="327" MPD_INDEX="324" MSB="63" NAME="S_AXI_HP0_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_RDATA" VECFORMULA="[(64- 1) :0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="328" MPD_INDEX="329" NAME="S_AXI_HP0_ACLK" SIGIS="CLK" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_ACLK">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="ARVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="329" MPD_INDEX="330" NAME="S_AXI_HP0_ARVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_ARVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="BREADY" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="330" MPD_INDEX="332" NAME="S_AXI_HP0_BREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_BREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="WVALID" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="331" MPD_INDEX="337" NAME="S_AXI_HP0_WVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_WVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="ARSIZE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="332" MPD_INDEX="340" MSB="2" NAME="S_AXI_HP0_ARSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_ARSIZE" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="ARBURST" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="333" MPD_INDEX="338" MSB="1" NAME="S_AXI_HP0_ARBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_ARBURST" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="ARREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="334" MPD_INDEX="360" NAME="S_AXI_HP1_ARREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_ARREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="ARLOCK" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="335" MPD_INDEX="339" MSB="1" NAME="S_AXI_HP0_ARLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_ARLOCK" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="AWBURST" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="336" MPD_INDEX="341" MSB="1" NAME="S_AXI_HP0_AWBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_AWBURST" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="AWLOCK" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="337" MPD_INDEX="342" MSB="1" NAME="S_AXI_HP0_AWLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_AWLOCK" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="AWSIZE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="338" MPD_INDEX="343" MSB="2" NAME="S_AXI_HP0_AWSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_AWSIZE" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="ARPROT" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="339" MPD_INDEX="344" MSB="2" NAME="S_AXI_HP0_ARPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_ARPROT" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="AWPROT" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="340" MPD_INDEX="345" MSB="2" NAME="S_AXI_HP0_AWPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_AWPROT" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="ARADDR" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="341" MPD_INDEX="346" MSB="31" NAME="S_AXI_HP0_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_ARADDR" VECFORMULA="[31:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="AWADDR" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="342" MPD_INDEX="347" MSB="31" NAME="S_AXI_HP0_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_AWADDR" VECFORMULA="[31:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="ARCACHE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="343" MPD_INDEX="348" MSB="3" NAME="S_AXI_HP0_ARCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_ARCACHE" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="ARLEN" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="344" MPD_INDEX="349" MSB="3" NAME="S_AXI_HP0_ARLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_ARLEN" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="ARQOS" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="345" MPD_INDEX="350" MSB="3" NAME="S_AXI_HP0_ARQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_ARQOS" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="AWCACHE" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="346" MPD_INDEX="351" MSB="3" NAME="S_AXI_HP0_AWCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_AWCACHE" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="BRESP" DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="347" MPD_INDEX="366" MSB="1" NAME="S_AXI_HP1_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="AWQOS" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="348" MPD_INDEX="353" MSB="3" NAME="S_AXI_HP0_AWQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_AWQOS" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="AWLEN" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="349" MPD_INDEX="352" MSB="3" NAME="S_AXI_HP0_AWLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_AWLEN" VECFORMULA="[3:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="ARID" DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="350" MPD_INDEX="354" MSB="5" NAME="S_AXI_HP0_ARID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_ARID" VECFORMULA="[(6 - 1) : 0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="BVALID" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="351" MPD_INDEX="362" NAME="S_AXI_HP1_BVALID" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_BVALID">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI_GP0" DEF_SIGNAME="WREADY" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="352" MPD_INDEX="197" NAME="S_AXI_GP0_WREADY" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_WREADY">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="353" MPD_INDEX="111" NAME="M_AXI_GP0_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP0_ARESETN">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="354" MPD_INDEX="336" NAME="S_AXI_HP0_WRISSUECAP1_EN" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_WRISSUECAP1_EN">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="355" MPD_INDEX="231" NAME="S_AXI_GP1_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP1_ARESETN">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="356" MPD_INDEX="191" NAME="S_AXI_GP0_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_S_AXI_GP0_ARESETN">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="357" MPD_INDEX="271" NAME="S_AXI_ACP_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_S_AXI_ACP_ARESETN">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="358" MPD_INDEX="313" NAME="S_AXI_HP0_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_ARESETN">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="359" MPD_INDEX="325" MSB="7" NAME="S_AXI_HP0_RCOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_RCOUNT" VECFORMULA="[7:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="360" MPD_INDEX="326" MSB="7" NAME="S_AXI_HP0_WCOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_WCOUNT" VECFORMULA="[7:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="361" MPD_INDEX="327" MSB="2" NAME="S_AXI_HP0_RACOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_RACOUNT" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="362" MPD_INDEX="328" MSB="5" NAME="S_AXI_HP0_WACOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_WACOUNT" VECFORMULA="[5:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="363" MPD_INDEX="333" NAME="S_AXI_HP0_RDISSUECAP1_EN" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP0_RDISSUECAP1_EN">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="364" MPD_INDEX="359" NAME="S_AXI_HP1_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_ARESETN">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="365" MPD_INDEX="382" NAME="S_AXI_HP1_WRISSUECAP1_EN" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_WRISSUECAP1_EN">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="366" MPD_INDEX="371" MSB="7" NAME="S_AXI_HP1_RCOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_RCOUNT" VECFORMULA="[7:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="367" MPD_INDEX="372" MSB="7" NAME="S_AXI_HP1_WCOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_WCOUNT" VECFORMULA="[7:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="368" MPD_INDEX="373" MSB="2" NAME="S_AXI_HP1_RACOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_RACOUNT" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="369" MPD_INDEX="374" MSB="5" NAME="S_AXI_HP1_WACOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_WACOUNT" VECFORMULA="[5:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="370" MPD_INDEX="379" NAME="S_AXI_HP1_RDISSUECAP1_EN" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP1_RDISSUECAP1_EN">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="371" MPD_INDEX="405" NAME="S_AXI_HP2_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_ARESETN">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="372" MPD_INDEX="428" NAME="S_AXI_HP2_WRISSUECAP1_EN" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_WRISSUECAP1_EN">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="373" MPD_INDEX="417" MSB="7" NAME="S_AXI_HP2_RCOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_RCOUNT" VECFORMULA="[7:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="374" MPD_INDEX="418" MSB="7" NAME="S_AXI_HP2_WCOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_WCOUNT" VECFORMULA="[7:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="375" MPD_INDEX="419" MSB="2" NAME="S_AXI_HP2_RACOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_RACOUNT" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="376" MPD_INDEX="420" MSB="5" NAME="S_AXI_HP2_WACOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_WACOUNT" VECFORMULA="[5:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="377" MPD_INDEX="425" NAME="S_AXI_HP2_RDISSUECAP1_EN" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP2_RDISSUECAP1_EN">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="378" MPD_INDEX="451" NAME="S_AXI_HP3_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_ARESETN">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="379" MPD_INDEX="474" NAME="S_AXI_HP3_WRISSUECAP1_EN" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_WRISSUECAP1_EN">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="380" MPD_INDEX="463" MSB="7" NAME="S_AXI_HP3_RCOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_RCOUNT" VECFORMULA="[7:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="381" MPD_INDEX="464" MSB="7" NAME="S_AXI_HP3_WCOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_WCOUNT" VECFORMULA="[7:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="382" MPD_INDEX="465" MSB="2" NAME="S_AXI_HP3_RACOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_RACOUNT" VECFORMULA="[2:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="5" LSB="0" MHS_INDEX="383" MPD_INDEX="466" MSB="5" NAME="S_AXI_HP3_WACOUNT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_WACOUNT" VECFORMULA="[5:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="384" MPD_INDEX="471" NAME="S_AXI_HP3_RDISSUECAP1_EN" SIGNAME="ps7_axi_interconnect_0_S_AXI_HP3_RDISSUECAP1_EN">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="385" MPD_INDEX="151" NAME="M_AXI_GP1_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_AXI_GP1_ARESETN">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="I" MPD_INDEX="0" NAME="INTERCONNECT_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" MPD_INDEX="1" NAME="INTERCONNECT_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_ARESETN" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="2" MSB="1" NAME="S_AXI_ARESET_OUT_N" RIGHT="0" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_S_ARESETN" VECFORMULA="[(2-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="O" MPD_INDEX="3" NAME="M_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN" VECFORMULA="[(1-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="aresetn"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_ARESETN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_ARESETN"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_ACLK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="5" MSB="1" NAME="S_AXI_ACLK" RIGHT="0" SIGIS="CLK" SIGNAME="ps7_axi_interconnect_0_S_ACLK" VECFORMULA="[(2-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_AWID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="6" MSB="1" NAME="S_AXI_AWID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWID" VECFORMULA="[((2*1)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_AWID"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_AWID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="7" MSB="63" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWADDR" VECFORMULA="[((2*32)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="15" LSB="0" MPD_INDEX="8" MSB="15" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWLEN" VECFORMULA="[((2*8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_AWLEN"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_AWLEN"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="9" MSB="5" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWSIZE" VECFORMULA="[((2*3)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_AWSIZE"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_AWSIZE"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="10" MSB="3" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWBURST" VECFORMULA="[((2*2)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_AWBURST"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_AWBURST"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="11" MSB="3" NAME="S_AXI_AWLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWLOCK" VECFORMULA="[((2*2)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_AWLOCK"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_AWLOCK"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="12" MSB="7" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWCACHE" VECFORMULA="[((2*4)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_AWCACHE"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_AWCACHE"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="13" MSB="5" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWPROT" VECFORMULA="[((2*3)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_AWPROT"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_AWPROT"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="14" MSB="7" NAME="S_AXI_AWQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWQOS" VECFORMULA="[((2*4)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_AWQOS"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_AWQOS"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_AWUSER" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="15" MSB="1" NAME="S_AXI_AWUSER" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWUSER" VECFORMULA="[((2*1)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_AWVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_AWVALID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWVALID" VECFORMULA="[(2-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_AWREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_AWREADY" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWREADY" VECFORMULA="[(2-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="18" MSB="63" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_WDATA" VECFORMULA="[((2*32)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_WDATA"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="19" MSB="7" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_WSTRB" VECFORMULA="[(((2*32)/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_WLAST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="20" MSB="1" NAME="S_AXI_WLAST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_WLAST" VECFORMULA="[(2-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_WLAST"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_WLAST"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_WUSER" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="21" MSB="1" NAME="S_AXI_WUSER" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_WUSER" VECFORMULA="[((2*1)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_WVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="22" MSB="1" NAME="S_AXI_WVALID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_WVALID" VECFORMULA="[(2-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_WVALID"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_WREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="23" MSB="1" NAME="S_AXI_WREADY" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_WREADY" VECFORMULA="[(2-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_WREADY"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_BID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="24" MSB="1" NAME="S_AXI_BID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_BID" VECFORMULA="[((2*1)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_BID"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_BID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="25" MSB="3" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_BRESP" VECFORMULA="[((2*2)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_BRESP"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_BUSER" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="26" MSB="1" NAME="S_AXI_BUSER" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_BUSER" VECFORMULA="[((2*1)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_BVALID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="27" MSB="1" NAME="S_AXI_BVALID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_BVALID" VECFORMULA="[(2-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_BVALID"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_BREADY" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="28" MSB="1" NAME="S_AXI_BREADY" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_BREADY" VECFORMULA="[(2-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_BREADY"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_ARID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="29" MSB="1" NAME="S_AXI_ARID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARID" VECFORMULA="[((2*1)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_ARID"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_ARID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="30" MSB="63" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARADDR" VECFORMULA="[((2*32)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="15" LSB="0" MPD_INDEX="31" MSB="15" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARLEN" VECFORMULA="[((2*8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_ARLEN"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_ARLEN"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="32" MSB="5" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARSIZE" VECFORMULA="[((2*3)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_ARSIZE"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_ARSIZE"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="33" MSB="3" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARBURST" VECFORMULA="[((2*2)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_ARBURST"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_ARBURST"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="34" MSB="3" NAME="S_AXI_ARLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARLOCK" VECFORMULA="[((2*2)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_ARLOCK"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_ARLOCK"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="35" MSB="7" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARCACHE" VECFORMULA="[((2*4)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_ARCACHE"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_ARCACHE"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="36" MSB="5" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARPROT" VECFORMULA="[((2*3)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_ARPROT"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_ARPROT"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="37" MSB="7" NAME="S_AXI_ARQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARQOS" VECFORMULA="[((2*4)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_ARQOS"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_ARQOS"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_ARUSER" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="38" MSB="1" NAME="S_AXI_ARUSER" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARUSER" VECFORMULA="[((2*1)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_ARVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="39" MSB="1" NAME="S_AXI_ARVALID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARVALID" VECFORMULA="[(2-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_ARREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="40" MSB="1" NAME="S_AXI_ARREADY" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARREADY" VECFORMULA="[(2-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_RID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="41" MSB="1" NAME="S_AXI_RID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_RID" VECFORMULA="[((2*1)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_RID"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_RID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="42" MSB="63" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_RDATA" VECFORMULA="[((2*32)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_RDATA"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="43" MSB="3" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_RRESP" VECFORMULA="[((2*2)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_RRESP"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_RLAST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="44" MSB="1" NAME="S_AXI_RLAST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_RLAST" VECFORMULA="[(2-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_RLAST"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_RLAST"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_RUSER" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="45" MSB="1" NAME="S_AXI_RUSER" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_RUSER" VECFORMULA="[((2*1)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_RVALID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="46" MSB="1" NAME="S_AXI_RVALID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_RVALID" VECFORMULA="[(2-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_RVALID"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_S_RREADY" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="47" MSB="1" NAME="S_AXI_RREADY" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_RREADY" VECFORMULA="[(2-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_0" PORT="M_AXI_DP_RREADY"/>
-            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="ps7_cortexa9_1" PORT="M_AXI_DP_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ACLK" DIR="I" MPD_INDEX="48" NAME="M_AXI_ACLK" SIGIS="CLK" SIGNAME="ps7_axi_interconnect_0_M_ACLK" VECFORMULA="[(1-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_AWID" DIR="O" MPD_INDEX="49" NAME="M_AXI_AWID" SIGNAME="ps7_axi_interconnect_0_M_AWID" VECFORMULA="[((1*1)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_AWID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_awid"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="50" MSB="31" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[((1*32)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_awaddr"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_awaddr"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_AWADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_awaddr"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="51" MSB="7" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWLEN" VECFORMULA="[((1*8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_AWLEN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_awlen"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="52" MSB="2" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWSIZE" VECFORMULA="[((1*3)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_AWSIZE"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_awsize"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="53" MSB="1" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWBURST" VECFORMULA="[((1*2)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_AWBURST"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_awburst"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_AWLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="54" MSB="1" NAME="M_AXI_AWLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWLOCK" VECFORMULA="[((1*2)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_AWLOCK"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_awlock"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="55" MSB="3" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWCACHE" VECFORMULA="[((1*4)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_AWCACHE"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_awcache"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="56" MSB="2" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWPROT" VECFORMULA="[((1*3)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_AWPROT"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_awprot"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREGION" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="57" MSB="3" NAME="M_AXI_AWREGION" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWREGION" VECFORMULA="[((1*4)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="58" MSB="3" NAME="M_AXI_AWQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWQOS" VECFORMULA="[((1*4)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_awqos"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_AWUSER" DIR="O" MPD_INDEX="59" NAME="M_AXI_AWUSER" SIGNAME="ps7_axi_interconnect_0_M_AWUSER" VECFORMULA="[((1*1)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="O" MPD_INDEX="60" NAME="M_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID" VECFORMULA="[(1-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_awvalid"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_awvalid"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_AWVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_awvalid"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="I" MPD_INDEX="61" NAME="M_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY" VECFORMULA="[(1-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_awready"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_awready"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_AWREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_awready"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_WID" DIR="O" MPD_INDEX="62" NAME="M_AXI_WID" SIGNAME="ps7_axi_interconnect_0_M_WID" VECFORMULA="[((1*1)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[((1*32)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_wdata"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_wdata"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_WDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_wdata"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="64" MSB="3" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[(((1*32)/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_wstrb"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_WSTRB"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_WLAST" DIR="O" MPD_INDEX="65" NAME="M_AXI_WLAST" SIGNAME="ps7_axi_interconnect_0_M_WLAST" VECFORMULA="[(1-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_WLAST"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_wlast"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_WUSER" DIR="O" MPD_INDEX="66" NAME="M_AXI_WUSER" SIGNAME="ps7_axi_interconnect_0_M_WUSER" VECFORMULA="[((1*1)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="O" MPD_INDEX="67" NAME="M_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID" VECFORMULA="[(1-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_wvalid"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_wvalid"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_WVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_wvalid"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="I" MPD_INDEX="68" NAME="M_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY" VECFORMULA="[(1-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_wready"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_wready"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_WREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_wready"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_BID" DIR="I" MPD_INDEX="69" NAME="M_AXI_BID" SIGNAME="ps7_axi_interconnect_0_M_BID" VECFORMULA="[((1*1)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_BID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_bid"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[((1*2)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_bresp"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_bresp"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_BRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_bresp"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_BUSER" DIR="I" MPD_INDEX="71" NAME="M_AXI_BUSER" SIGNAME="ps7_axi_interconnect_0_M_BUSER" VECFORMULA="[((1*1)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="I" MPD_INDEX="72" NAME="M_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID" VECFORMULA="[(1-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_bvalid"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_bvalid"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_BVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_bvalid"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="O" MPD_INDEX="73" NAME="M_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY" VECFORMULA="[(1-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_bready"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_bready"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_BREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_bready"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ARID" DIR="O" MPD_INDEX="74" NAME="M_AXI_ARID" SIGNAME="ps7_axi_interconnect_0_M_ARID" VECFORMULA="[((1*1)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_ARID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_arid"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="75" MSB="31" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[((1*32)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_araddr"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_araddr"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_ARADDR"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_araddr"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="76" MSB="7" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARLEN" VECFORMULA="[((1*8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_ARLEN"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_arlen"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="77" MSB="2" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARSIZE" VECFORMULA="[((1*3)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_ARSIZE"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_arsize"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="78" MSB="1" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARBURST" VECFORMULA="[((1*2)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_ARBURST"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_arburst"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ARLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="79" MSB="1" NAME="M_AXI_ARLOCK" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARLOCK" VECFORMULA="[((1*2)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_ARLOCK"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_arlock"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="80" MSB="3" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARCACHE" VECFORMULA="[((1*4)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_ARCACHE"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_arcache"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="81" MSB="2" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARPROT" VECFORMULA="[((1*3)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_ARPROT"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_arprot"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREGION" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="82" MSB="3" NAME="M_AXI_ARREGION" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARREGION" VECFORMULA="[((1*4)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="83" MSB="3" NAME="M_AXI_ARQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARQOS" VECFORMULA="[((1*4)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_arqos"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ARUSER" DIR="O" MPD_INDEX="84" NAME="M_AXI_ARUSER" SIGNAME="ps7_axi_interconnect_0_M_ARUSER" VECFORMULA="[((1*1)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="O" MPD_INDEX="85" NAME="M_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID" VECFORMULA="[(1-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_arvalid"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_arvalid"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_ARVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_arvalid"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="I" MPD_INDEX="86" NAME="M_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY" VECFORMULA="[(1-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_arready"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_arready"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_ARREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_arready"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_RID" DIR="I" MPD_INDEX="87" NAME="M_AXI_RID" SIGNAME="ps7_axi_interconnect_0_M_RID" VECFORMULA="[((1*1)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_RID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_rid"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="88" MSB="31" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[((1*32)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_rdata"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_rdata"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_RDATA"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_rdata"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="89" MSB="1" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[((1*2)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_rresp"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_rresp"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_RRESP"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_rresp"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_RLAST" DIR="I" MPD_INDEX="90" NAME="M_AXI_RLAST" SIGNAME="ps7_axi_interconnect_0_M_RLAST" VECFORMULA="[(1-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_RLAST"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_rlast"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_RUSER" DIR="I" MPD_INDEX="91" NAME="M_AXI_RUSER" SIGNAME="ps7_axi_interconnect_0_M_RUSER" VECFORMULA="[((1*1)-1):0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="I" MPD_INDEX="92" NAME="M_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID" VECFORMULA="[(1-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_rvalid"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_rvalid"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_RVALID"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_rvalid"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="O" MPD_INDEX="93" NAME="M_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY" VECFORMULA="[(1-1):0]">
-          <CONNECTIONS>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_0" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_uart_1" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_0" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_0" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_1" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_2" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_afi_3" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_i2c_1" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_sd_0" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ethernet_0" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_usb_0" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_0" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_qspi_linear_0" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddr_0" PORT="s_axi_rready"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpio_0" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ddrc_0" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_dev_cfg_0" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_xadc_0" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_coresight_comp_0" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ocmc_0" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_gpv_0" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuc_0" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_intc_dist_0" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_globaltimer_0" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_l2cachec_0" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_s" PORT="s_axi_lite_rready"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_iop_bus_config_0" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_0" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_ram_1" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scugic_0" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scutimer_0" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_scuwdt_0" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="ps7_slcr_0" PORT="S_AXI_RREADY"/>
-            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="ps7_dma_ns" PORT="s_axi_lite_rready"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="94" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(32 - 1) : 0]"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="95" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="97" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(32 - 1) : 0]"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="99" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="100" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="102" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="103" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(32 - 1) : 0]"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="106" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(32 - 1) : 0]"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="107" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="110" NAME="INTERCONNECT_ARESET_OUT_N" SIGNAME="__NOC__"/>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="M_AXI_GP0" TYPE="MASTER">
-          <PORTMAPS>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_BREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWID"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_RREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARSIZE"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_AWREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARID"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_WID"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWBURST"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARBURST"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARLOCK"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWLOCK"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWSIZE"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARPROT"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWPROT"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_BID"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWADDR"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_WDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARCACHE"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWQOS"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARLEN"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARQOS"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWCACHE"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWLEN"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_ARREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_RLAST"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_RID"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_BRESP"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_RRESP"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_WLAST"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="2" NAME="M_AXI_GP1" TYPE="MASTER">
-          <PORTMAPS>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_BREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARQOS"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARID"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_WID"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWBURST"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARBURST"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARLOCK"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWLOCK"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWSIZE"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARPROT"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWPROT"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_BID"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWADDR"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_WDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARCACHE"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARLEN"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_RLAST"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWQOS"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_AWREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWCACHE"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWLEN"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_WREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_ARREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_RDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_RID"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_BRESP"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_RREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWID"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_WLAST"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARSIZE"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWVALID"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="4" NAME="S_AXI_GP1" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_RID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_WVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARSIZE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARBURST"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARLOCK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWBURST"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWLOCK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWSIZE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARPROT"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWPROT"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARCACHE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARQOS"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARLEN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWQOS"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWCACHE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWLEN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_WID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_BVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_RVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_RRESP"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_RREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_RDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_WLAST"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_BID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_RLAST"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_AWREADY"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="5" NAME="S_AXI_HP0" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_WID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_WSTRB"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_AWREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_RLAST"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_BVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_RRESP"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_RREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_BID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_WLAST"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_RID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_RDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_WVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARSIZE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARBURST"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARLOCK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWBURST"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWLOCK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWSIZE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARPROT"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWPROT"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARCACHE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARLEN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARQOS"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWCACHE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWQOS"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWLEN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARID"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="6" NAME="S_AXI_HP1" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_RVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_RRESP"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_RREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_BID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_WLAST"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_RID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_RDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_WVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARSIZE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARBURST"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARLOCK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWBURST"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWLOCK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWSIZE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARPROT"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWPROT"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARCACHE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARLEN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARQOS"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_RLAST"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWCACHE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWQOS"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWLEN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_WID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_WSTRB"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_BVALID"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="7" NAME="S_AXI_HP2" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_RLAST"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_AWREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_ARREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWSIZE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARPROT"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWPROT"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARCACHE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARLEN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARQOS"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWCACHE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWQOS"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWLEN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_WID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_WSTRB"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_BVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_RVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_RRESP"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_RREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_BID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_WLAST"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_RID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_RDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_WVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARSIZE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARBURST"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARLOCK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWBURST"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWLOCK"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="8" NAME="S_AXI_HP3" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_BVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_RVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_RRESP"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_RREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_BID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_WLAST"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_RID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_RDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_WVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARSIZE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARBURST"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARLOCK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWBURST"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWLOCK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWSIZE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARPROT"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWPROT"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARCACHE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARLEN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARQOS"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWCACHE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWQOS"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWLEN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_WID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_WSTRB"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_RLAST"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_AWREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_ARREADY"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="9" NAME="S_AXI_ACP" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_WREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_RREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_RID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_RDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_WVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWQOS"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARLEN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARPROT"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWPROT"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_WID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARCACHE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARQOS"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARBURST"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWCACHE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWBURST"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWLEN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARSIZE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARLOCK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWLOCK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWSIZE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARUSER"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWUSER"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_WSTRB"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_RLAST"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_AWREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_BVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_WLAST"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_BID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWVALID"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="3" NAME="S_AXI_GP0" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_RLAST"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARQOS"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWBURST"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWLOCK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWSIZE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARPROT"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWPROT"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARCACHE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARLEN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWQOS"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWCACHE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_WID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_AWREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_RVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_RRESP"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_RREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_RDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_WLAST"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_BID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_RID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_WVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARSIZE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWLEN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARBURST"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARLOCK"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_WREADY"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI_CTRL" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_uart_0" IPTYPE="PERIPHERAL" MHS_INDEX="16" MODCLASS="PERIPHERAL" MODTYPE="ps7_uart">
-      <DESCRIPTION TYPE="SHORT">PS7 UART</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE0000000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE0000FFF"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="C_UART_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="3" NAME="C_HAS_MODEM" TYPE="STRING" VALUE="0"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="O" MPD_INDEX="2" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="3" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[31:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="4" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="5" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[31:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="7" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[3:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="8" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="9" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="11" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="12" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="13" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[31:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[31:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="18" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="19" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" IOS="uart0_0" MPD_INDEX="20" NAME="RX" SIGNAME="__NOC__">
-          <DESCRIPTION>Serial Data In</DESCRIPTION>
-        </PORT>
-        <PORT DIR="O" IOS="uart0_0" MPD_INDEX="21" NAME="TX" SIGNAME="__NOC__">
-          <DESCRIPTION>Serial Data Out</DESCRIPTION>
-        </PORT>
-        <PORT DIR="I" IOS="uart0_0" MPD_INDEX="22" NAME="CTSN" SIGNAME="__NOC__">
-          <DESCRIPTION>Serial Data In</DESCRIPTION>
-        </PORT>
-        <PORT DIR="O" IOS="uart0_0" MPD_INDEX="23" NAME="RTSN" SIGNAME="__NOC__">
-          <DESCRIPTION>Serial Data Out</DESCRIPTION>
-        </PORT>
-        <PORT DIR="I" IOS="uart0_0" MPD_INDEX="24" NAME="DSRN" SIGNAME="__NOC__">
-          <DESCRIPTION>Serial Data In</DESCRIPTION>
-        </PORT>
-        <PORT DIR="I" IOS="uart0_0" MPD_INDEX="25" NAME="DCDN" SIGNAME="__NOC__">
-          <DESCRIPTION>Serial Data In</DESCRIPTION>
-        </PORT>
-        <PORT DIR="I" IOS="uart0_0" MPD_INDEX="26" NAME="RIN" SIGNAME="__NOC__">
-          <DESCRIPTION>Serial Data In</DESCRIPTION>
-        </PORT>
-        <PORT DIR="O" IOS="uart0_0" MPD_INDEX="27" NAME="DTRN" SIGNAME="__NOC__">
-          <DESCRIPTION>Serial Data Out</DESCRIPTION>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <IOINTERFACES>
-        <IOINTERFACE MPD_INDEX="0" NAME="uart0_0" TYPE="XIL_UART_V1_hide">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="RX"/>
-            <PORTMAP DIR="O" PHYSICAL="TX"/>
-            <PORTMAP DIR="I" PHYSICAL="CTSN"/>
-            <PORTMAP DIR="O" PHYSICAL="RTSN"/>
-            <PORTMAP DIR="I" PHYSICAL="DSRN"/>
-            <PORTMAP DIR="I" PHYSICAL="DCDN"/>
-            <PORTMAP DIR="I" PHYSICAL="RIN"/>
-            <PORTMAP DIR="O" PHYSICAL="DTRN"/>
-          </PORTMAPS>
-        </IOINTERFACE>
-      </IOINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="3758096384" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0000000" HIGHDECIMAL="3758100479" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0000FFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_uart_1" IPTYPE="PERIPHERAL" MHS_INDEX="17" MODCLASS="PERIPHERAL" MODTYPE="ps7_uart">
-      <DESCRIPTION TYPE="SHORT">PS7 UART</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE0001000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE0001FFF"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="C_UART_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="3" NAME="C_HAS_MODEM" TYPE="STRING" VALUE="0"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="O" MPD_INDEX="2" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="3" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[31:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="4" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="5" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[31:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="7" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[3:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="8" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="9" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="11" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="12" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="13" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[31:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[31:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="18" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="19" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" IOS="uart0_0" MPD_INDEX="20" NAME="RX" SIGNAME="__NOC__">
-          <DESCRIPTION>Serial Data In</DESCRIPTION>
-        </PORT>
-        <PORT DIR="O" IOS="uart0_0" MPD_INDEX="21" NAME="TX" SIGNAME="__NOC__">
-          <DESCRIPTION>Serial Data Out</DESCRIPTION>
-        </PORT>
-        <PORT DIR="I" IOS="uart0_0" MPD_INDEX="22" NAME="CTSN" SIGNAME="__NOC__">
-          <DESCRIPTION>Serial Data In</DESCRIPTION>
-        </PORT>
-        <PORT DIR="O" IOS="uart0_0" MPD_INDEX="23" NAME="RTSN" SIGNAME="__NOC__">
-          <DESCRIPTION>Serial Data Out</DESCRIPTION>
-        </PORT>
-        <PORT DIR="I" IOS="uart0_0" MPD_INDEX="24" NAME="DSRN" SIGNAME="__NOC__">
-          <DESCRIPTION>Serial Data In</DESCRIPTION>
-        </PORT>
-        <PORT DIR="I" IOS="uart0_0" MPD_INDEX="25" NAME="DCDN" SIGNAME="__NOC__">
-          <DESCRIPTION>Serial Data In</DESCRIPTION>
-        </PORT>
-        <PORT DIR="I" IOS="uart0_0" MPD_INDEX="26" NAME="RIN" SIGNAME="__NOC__">
-          <DESCRIPTION>Serial Data In</DESCRIPTION>
-        </PORT>
-        <PORT DIR="O" IOS="uart0_0" MPD_INDEX="27" NAME="DTRN" SIGNAME="__NOC__">
-          <DESCRIPTION>Serial Data Out</DESCRIPTION>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <IOINTERFACES>
-        <IOINTERFACE MPD_INDEX="0" NAME="uart0_0" TYPE="XIL_UART_V1_hide">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="RX"/>
-            <PORTMAP DIR="O" PHYSICAL="TX"/>
-            <PORTMAP DIR="I" PHYSICAL="CTSN"/>
-            <PORTMAP DIR="O" PHYSICAL="RTSN"/>
-            <PORTMAP DIR="I" PHYSICAL="DSRN"/>
-            <PORTMAP DIR="I" PHYSICAL="DCDN"/>
-            <PORTMAP DIR="I" PHYSICAL="RIN"/>
-            <PORTMAP DIR="O" PHYSICAL="DTRN"/>
-          </PORTMAPS>
-        </IOINTERFACE>
-      </IOINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="3758100480" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0001000" HIGHDECIMAL="3758104575" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0001FFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_i2c_0" IPTYPE="PERIPHERAL" MHS_INDEX="18" MODCLASS="PERIPHERAL" MODTYPE="ps7_i2c">
-      <DESCRIPTION TYPE="SHORT">PS7 i2c Interface</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">PS7 Interface to Philips I2C bus v2.1</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE0004000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE0004FFF"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="C_I2C_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="108333336"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="3" NAME="C_HAS_INTERRUPT" TYPE="STRING" VALUE="0"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="4" NAME="C_I2C_RESET" VALUE="-1"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" IOS="i2c_0" MPD_INDEX="19" NAME="Sda_I" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="i2c_0" MPD_INDEX="20" NAME="Sda_O" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="i2c_0" MPD_INDEX="21" NAME="Sda_T" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="i2c_0" MPD_INDEX="22" NAME="Scl_I" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="i2c_0" MPD_INDEX="23" NAME="Scl_O" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="i2c_0" MPD_INDEX="24" NAME="Scl_T" SIGNAME="__NOC__"/>
-        <PORT DIR="IO" IOS="i2c_0" IS_THREE_STATE="TRUE" MPD_INDEX="25" NAME="Sda" SIGNAME="__NOC__" TRI_I="Sda_I" TRI_O="Sda_O" TRI_T="Sda_T">
-          <DESCRIPTION></DESCRIPTION>
-        </PORT>
-        <PORT DIR="IO" IOS="i2c_0" IS_THREE_STATE="TRUE" MPD_INDEX="26" NAME="Scl" SIGNAME="__NOC__" TRI_I="Scl_I" TRI_O="Scl_O" TRI_T="Scl_T">
-          <DESCRIPTION></DESCRIPTION>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <IOINTERFACES>
-        <IOINTERFACE MPD_INDEX="0" NAME="i2c_0" TYPE="XIL_AXI_IIC_V1">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="Sda_I"/>
-            <PORTMAP DIR="O" PHYSICAL="Sda_O"/>
-            <PORTMAP DIR="O" PHYSICAL="Sda_T"/>
-            <PORTMAP DIR="I" PHYSICAL="Scl_I"/>
-            <PORTMAP DIR="O" PHYSICAL="Scl_O"/>
-            <PORTMAP DIR="O" PHYSICAL="Scl_T"/>
-            <PORTMAP DIR="IO" PHYSICAL="Sda"/>
-            <PORTMAP DIR="IO" PHYSICAL="Scl"/>
-          </PORTMAPS>
-        </IOINTERFACE>
-      </IOINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="3758112768" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0004000" HIGHDECIMAL="3758116863" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0004FFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_afi_0" IPTYPE="PERIPHERAL" MHS_INDEX="19" MODCLASS="PERIPHERAL" MODTYPE="ps7_afi">
-      <DESCRIPTION TYPE="SHORT">PS7 AFI Engine</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">AXI MemoryMap to/from AXI Stream Direct Memory Access Engine</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8008000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8008FFF"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="4160782336" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8008000" HIGHDECIMAL="4160786431" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8008FFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_afi_1" IPTYPE="PERIPHERAL" MHS_INDEX="20" MODCLASS="PERIPHERAL" MODTYPE="ps7_afi">
-      <DESCRIPTION TYPE="SHORT">PS7 AFI Engine</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">AXI MemoryMap to/from AXI Stream Direct Memory Access Engine</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8009000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8009FFF"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="4160786432" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8009000" HIGHDECIMAL="4160790527" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8009FFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_afi_2" IPTYPE="PERIPHERAL" MHS_INDEX="21" MODCLASS="PERIPHERAL" MODTYPE="ps7_afi">
-      <DESCRIPTION TYPE="SHORT">PS7 AFI Engine</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">AXI MemoryMap to/from AXI Stream Direct Memory Access Engine</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF800A000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF800AFFF"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="4160790528" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF800A000" HIGHDECIMAL="4160794623" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF800AFFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_afi_3" IPTYPE="PERIPHERAL" MHS_INDEX="22" MODCLASS="PERIPHERAL" MODTYPE="ps7_afi">
-      <DESCRIPTION TYPE="SHORT">PS7 AFI Engine</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">AXI MemoryMap to/from AXI Stream Direct Memory Access Engine</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF800B000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF800BFFF"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="4160794624" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF800B000" HIGHDECIMAL="4160798719" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF800BFFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_i2c_1" IPTYPE="PERIPHERAL" MHS_INDEX="23" MODCLASS="PERIPHERAL" MODTYPE="ps7_i2c">
-      <DESCRIPTION TYPE="SHORT">PS7 i2c Interface</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">PS7 Interface to Philips I2C bus v2.1</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE0005000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE0005FFF"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="C_I2C_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="108333336"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="3" NAME="C_HAS_INTERRUPT" TYPE="STRING" VALUE="0"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="4" NAME="C_I2C_RESET" VALUE="-1"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" IOS="i2c_0" MPD_INDEX="19" NAME="Sda_I" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="i2c_0" MPD_INDEX="20" NAME="Sda_O" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="i2c_0" MPD_INDEX="21" NAME="Sda_T" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="i2c_0" MPD_INDEX="22" NAME="Scl_I" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="i2c_0" MPD_INDEX="23" NAME="Scl_O" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="i2c_0" MPD_INDEX="24" NAME="Scl_T" SIGNAME="__NOC__"/>
-        <PORT DIR="IO" IOS="i2c_0" IS_THREE_STATE="TRUE" MPD_INDEX="25" NAME="Sda" SIGNAME="__NOC__" TRI_I="Sda_I" TRI_O="Sda_O" TRI_T="Sda_T">
-          <DESCRIPTION></DESCRIPTION>
-        </PORT>
-        <PORT DIR="IO" IOS="i2c_0" IS_THREE_STATE="TRUE" MPD_INDEX="26" NAME="Scl" SIGNAME="__NOC__" TRI_I="Scl_I" TRI_O="Scl_O" TRI_T="Scl_T">
-          <DESCRIPTION></DESCRIPTION>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <IOINTERFACES>
-        <IOINTERFACE MPD_INDEX="0" NAME="i2c_0" TYPE="XIL_AXI_IIC_V1">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="Sda_I"/>
-            <PORTMAP DIR="O" PHYSICAL="Sda_O"/>
-            <PORTMAP DIR="O" PHYSICAL="Sda_T"/>
-            <PORTMAP DIR="I" PHYSICAL="Scl_I"/>
-            <PORTMAP DIR="O" PHYSICAL="Scl_O"/>
-            <PORTMAP DIR="O" PHYSICAL="Scl_T"/>
-            <PORTMAP DIR="IO" PHYSICAL="Sda"/>
-            <PORTMAP DIR="IO" PHYSICAL="Scl"/>
-          </PORTMAPS>
-        </IOINTERFACE>
-      </IOINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="3758116864" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0005000" HIGHDECIMAL="3758120959" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0005FFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_sd_0" IPTYPE="PERIPHERAL" MHS_INDEX="24" MODCLASS="PERIPHERAL" MODTYPE="ps7_sdio">
-      <DESCRIPTION TYPE="SHORT">PS7 SDIO Controller</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">SD/SDIO/MMC Controller</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE0100000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE0100FFF"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="C_SDIO_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="3" NAME="C_HAS_CD" TYPE="STRING" VALUE="1"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="4" NAME="C_HAS_WP" TYPE="STRING" VALUE="1"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="5" NAME="C_HAS_POWER" TYPE="STRING" VALUE="0"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="3759144960" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0100000" HIGHDECIMAL="3759149055" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0100FFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_ethernet_0" IPTYPE="PERIPHERAL" MHS_INDEX="25" MODCLASS="PERIPHERAL" MODTYPE="ps7_ethernet">
-      <DESCRIPTION TYPE="SHORT">PS7 Ethernet Embedded IP</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">Embedded Ethernet core that implements a Tri-mode (10/100/1000 Mbps) Ethernet MAC or a 10/100 Mbps Ethernet MAC to support MII/GMII/SGMII/RGMII/1000Base-X PHY types</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE000B000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE000BFFF"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="C_ENET_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="125000000"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="3" NAME="C_ENET_SLCR_1000Mbps_DIV0" TYPE="INTEGER" VALUE="8"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="4" NAME="C_ENET_SLCR_1000Mbps_DIV1" TYPE="INTEGER" VALUE="1"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="5" NAME="C_ENET_SLCR_100Mbps_DIV0" TYPE="INTEGER" VALUE="8"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="6" NAME="C_ENET_SLCR_100Mbps_DIV1" TYPE="INTEGER" VALUE="5"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="7" NAME="C_ENET_SLCR_10Mbps_DIV0" TYPE="INTEGER" VALUE="8"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="8" NAME="C_ENET_SLCR_10Mbps_DIV1" TYPE="INTEGER" VALUE="50"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="9" NAME="C_HAS_MDIO" TYPE="STRING" VALUE="1"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="10" NAME="C_ETH_MODE" TYPE="STRING" VALUE="1"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="14" MPD_INDEX="11" NAME="C_ENET_RESET" VALUE="-1"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="O" MPD_INDEX="1" NAME="INTERRUPT" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="3758141440" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE000B000" HIGHDECIMAL="3758145535" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE000BFFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_usb_0" IPTYPE="PERIPHERAL" MHS_INDEX="26" MODCLASS="PERIPHERAL" MODTYPE="ps7_usb">
-      <DESCRIPTION TYPE="SHORT">PS7 USB2 Device</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">PS7 USB 2.0 Device Controller</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE0002000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE0002FFF"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="C_USB_RESET" VALUE="MIO 46"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWID" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="2" MSB="3" NAME="S_AXI_AWID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWID" VECFORMULA="[(4-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="3" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="4" MSB="7" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWLEN" VECFORMULA="[7:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWLEN"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="5" MSB="2" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWSIZE" VECFORMULA="[2:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWSIZE"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="6" MSB="1" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWBURST" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWBURST"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWLOCK" DIR="I" MPD_INDEX="7" NAME="S_AXI_AWLOCK" SIGNAME="ps7_axi_interconnect_0_M_AWLOCK">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWLOCK"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="8" MSB="3" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWCACHE" VECFORMULA="[3:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWCACHE"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="9" MSB="2" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWPROT" VECFORMULA="[2:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWPROT"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="10" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="13" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WLAST" DIR="I" MPD_INDEX="14" NAME="S_AXI_WLAST" SIGNAME="ps7_axi_interconnect_0_M_WLAST">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WLAST"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="15" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="16" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BID" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="17" MSB="3" NAME="S_AXI_BID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BID" VECFORMULA="[(4-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="18" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="19" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="20" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARID" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="21" MSB="3" NAME="S_AXI_ARID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARID" VECFORMULA="[(4-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="22" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="23" MSB="7" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARLEN" VECFORMULA="[7:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARLEN"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="24" MSB="2" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARSIZE" VECFORMULA="[2:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARSIZE"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="25" MSB="1" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARBURST" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARBURST"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="26" MSB="2" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARPROT" VECFORMULA="[2:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARPROT"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARLOCK" DIR="I" MPD_INDEX="27" NAME="S_AXI_ARLOCK" SIGNAME="ps7_axi_interconnect_0_M_ARLOCK">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARLOCK"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="28" MSB="3" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARCACHE" VECFORMULA="[3:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARCACHE"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="29" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="30" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RID" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="31" MSB="3" NAME="S_AXI_RID" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RID" VECFORMULA="[(4-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="32" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="33" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RLAST" DIR="O" MPD_INDEX="34" NAME="S_AXI_RLAST" SIGNAME="ps7_axi_interconnect_0_M_RLAST">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RLAST"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="35" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="36" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="37" NAME="M_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="38" NAME="M_AXI_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="39" NAME="M_AXI_AWID" SIGNAME="__NOC__" VECFORMULA="[1-1:0]"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="40" MSB="31" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[32-1:0]"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="41" MSB="7" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="42" MSB="2" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="43" MSB="1" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="44" MSB="3" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="45" MSB="2" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="46" NAME="M_AXI_AWLOCK" SIGNAME="__NOC__"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="47" NAME="M_AXI_AWVALID" SIGNAME="__NOC__"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="48" NAME="M_AXI_AWREADY" SIGNAME="__NOC__"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="49" MSB="31" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[32-1:0]"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="50" MSB="3" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(32/8)-1:0]"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="51" NAME="M_AXI_WLAST" SIGNAME="__NOC__"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="52" NAME="M_AXI_WVALID" SIGNAME="__NOC__"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="53" NAME="M_AXI_WREADY" SIGNAME="__NOC__"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="54" NAME="M_AXI_BID" SIGNAME="__NOC__" VECFORMULA="[1-1:0]"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="55" MSB="1" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="56" NAME="M_AXI_BVALID" SIGNAME="__NOC__"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="57" NAME="M_AXI_BREADY" SIGNAME="__NOC__"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="58" NAME="M_AXI_ARID" SIGNAME="__NOC__" VECFORMULA="[1-1:0]"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="59" MSB="31" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[32-1:0]"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="60" MSB="7" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="61" MSB="2" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="62" MSB="1" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="63" MSB="3" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="64" MSB="2" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="65" NAME="M_AXI_ARLOCK" SIGNAME="__NOC__"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="66" NAME="M_AXI_ARVALID" SIGNAME="__NOC__"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="67" NAME="M_AXI_ARREADY" SIGNAME="__NOC__"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="68" NAME="M_AXI_RID" SIGNAME="__NOC__" VECFORMULA="[1-1:0]"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="69" MSB="31" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[32-1:0]"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="71" NAME="M_AXI_RLAST" SIGNAME="__NOC__"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="72" NAME="M_AXI_RVALID" SIGNAME="__NOC__"/>
-        <PORT BUS="M_AXI" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="73" NAME="M_AXI_RREADY" SIGNAME="__NOC__"/>
-        <PORT DIR="O" MPD_INDEX="74" NAME="usb_irpt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="usb_0" MPD_INDEX="75" NAME="ULPI_Clock" SIGIS="CLK" SIGNAME="__NOC__">
-          <DESCRIPTION>Ulpi input clock</DESCRIPTION>
-        </PORT>
-        <PORT DIR="O" IOS="usb_0" MPD_INDEX="76" NAME="ULPI_Reset" SIGNAME="__NOC__">
-          <DESCRIPTION>Ulpi reset</DESCRIPTION>
-        </PORT>
-        <PORT DIR="I" ENDIAN="LITTLE" IOS="usb_0" LEFT="7" LSB="0" MPD_INDEX="77" MSB="7" NAME="ULPI_Data_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]">
-          <DESCRIPTION>Ulpi input data</DESCRIPTION>
-        </PORT>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="usb_0" LEFT="7" LSB="0" MPD_INDEX="78" MSB="7" NAME="ULPI_Data_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]">
-          <DESCRIPTION>Ulpi output data</DESCRIPTION>
-        </PORT>
-        <PORT DIR="O" IOS="usb_0" MPD_INDEX="79" NAME="ULPI_Data_T" SIGNAME="__NOC__">
-          <DESCRIPTION>Ulpi data toggle</DESCRIPTION>
-        </PORT>
-        <PORT DIR="O" IOS="usb_0" MPD_INDEX="80" NAME="ULPI_Stop" SIGNAME="__NOC__">
-          <DESCRIPTION>Ulpi stop</DESCRIPTION>
-        </PORT>
-        <PORT DIR="I" IOS="usb_0" MPD_INDEX="81" NAME="ULPI_Next" SIGNAME="__NOC__">
-          <DESCRIPTION>Ulpi next</DESCRIPTION>
-        </PORT>
-        <PORT DIR="I" IOS="usb_0" MPD_INDEX="82" NAME="ULPI_Dir" SIGNAME="__NOC__">
-          <DESCRIPTION>Ulpi direction</DESCRIPTION>
-        </PORT>
-        <PORT DIR="O" IOS="usb_0" MPD_INDEX="83" NAME="vbus_detect" SIGNAME="__NOC__">
-          <DESCRIPTION>vbus detect</DESCRIPTION>
-        </PORT>
-        <PORT DIR="O" IOS="usb_0" MPD_INDEX="84" NAME="show_currentspeed" SIGNAME="__NOC__">
-          <DESCRIPTION>show current speed</DESCRIPTION>
-        </PORT>
-        <PORT DIR="O" IOS="usb_0" MPD_INDEX="85" NAME="running" SIGNAME="__NOC__">
-          <DESCRIPTION>running</DESCRIPTION>
-        </PORT>
-        <PORT DIR="O" IOS="usb_0" MPD_INDEX="86" NAME="suspended" SIGNAME="__NOC__">
-          <DESCRIPTION>suspended</DESCRIPTION>
-        </PORT>
-        <PORT DIR="O" IOS="usb_0" MPD_INDEX="87" NAME="disconnected" SIGNAME="__NOC__">
-          <DESCRIPTION>disconnected</DESCRIPTION>
-        </PORT>
-        <PORT DIR="O" IOS="usb_0" MPD_INDEX="88" NAME="configured" SIGNAME="__NOC__">
-          <DESCRIPTION>test mode 2</DESCRIPTION>
-        </PORT>
-        <PORT DIR="O" IOS="usb_0" MPD_INDEX="89" NAME="spare1" SIGNAME="__NOC__">
-          <DESCRIPTION>test mode 0</DESCRIPTION>
-        </PORT>
-        <PORT DIR="O" IOS="usb_0" MPD_INDEX="90" NAME="spare2" SIGNAME="__NOC__">
-          <DESCRIPTION>test mode 1</DESCRIPTION>
-        </PORT>
-        <PORT DIR="IO" ENDIAN="LITTLE" IOS="usb_0" IS_THREE_STATE="TRUE" LEFT="7" LSB="0" MPD_INDEX="91" MSB="7" NAME="ULPI_Data" RIGHT="0" SIGNAME="__NOC__" TRI_I="ULPI_Data_I" TRI_O="ULPI_Data_O" TRI_T="ULPI_Data_T" VECFORMULA="[7:0]">
-          <DESCRIPTION>Ulpi bi-directional data</DESCRIPTION>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWLEN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWSIZE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWBURST"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWLOCK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWCACHE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWPROT"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WLAST"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARLEN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARSIZE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARBURST"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARPROT"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARLOCK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARCACHE"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RLAST"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="1" NAME="M_AXI" TYPE="MASTER">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_ARESETN"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_AWID"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_AWADDR"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_AWLEN"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_AWSIZE"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_AWBURST"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_AWCACHE"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_AWPROT"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_AWLOCK"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_AWVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_AWREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_WDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_WSTRB"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_WLAST"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_WVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_WREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_BID"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_BRESP"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_BVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_BREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_ARID"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_ARADDR"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_ARLEN"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_ARSIZE"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_ARBURST"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_ARCACHE"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_ARPROT"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_ARLOCK"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_ARVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_ARREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_RID"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_RDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_RRESP"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_RLAST"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_RVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_RREADY"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <IOINTERFACES>
-        <IOINTERFACE MPD_INDEX="0" NAME="usb_0" TYPE="XIL_AXI_USB2DEVICE_V1">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="ULPI_Clock"/>
-            <PORTMAP DIR="O" PHYSICAL="ULPI_Reset"/>
-            <PORTMAP DIR="I" PHYSICAL="ULPI_Data_I"/>
-            <PORTMAP DIR="O" PHYSICAL="ULPI_Data_O"/>
-            <PORTMAP DIR="O" PHYSICAL="ULPI_Data_T"/>
-            <PORTMAP DIR="O" PHYSICAL="ULPI_Stop"/>
-            <PORTMAP DIR="I" PHYSICAL="ULPI_Next"/>
-            <PORTMAP DIR="I" PHYSICAL="ULPI_Dir"/>
-            <PORTMAP DIR="O" PHYSICAL="vbus_detect"/>
-            <PORTMAP DIR="O" PHYSICAL="show_currentspeed"/>
-            <PORTMAP DIR="O" PHYSICAL="running"/>
-            <PORTMAP DIR="O" PHYSICAL="suspended"/>
-            <PORTMAP DIR="O" PHYSICAL="disconnected"/>
-            <PORTMAP DIR="O" PHYSICAL="configured"/>
-            <PORTMAP DIR="O" PHYSICAL="spare1"/>
-            <PORTMAP DIR="O" PHYSICAL="spare2"/>
-            <PORTMAP DIR="IO" PHYSICAL="ULPI_Data"/>
-          </PORTMAPS>
-        </IOINTERFACE>
-      </IOINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="3758104576" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0002000" HIGHDECIMAL="3758108671" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0002FFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_qspi_0" IPTYPE="PERIPHERAL" MHS_INDEX="27" MODCLASS="PERIPHERAL" MODTYPE="ps7_qspi">
-      <DESCRIPTION TYPE="SHORT">PS7 Quad SPI Interface</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">Connects AXI-Lite to the SPI slaves supporting Standard/Dual/Quad interfaces</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE000D000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE000DFFF"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="C_QSPI_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="200000000"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="3" NAME="C_QSPI_MODE" TYPE="STRING" VALUE="0"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="4" NAME="C_FB_CLK" TYPE="STRING" VALUE="1"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" IOS="ps7_qspi_0" IS_VALID="FALSE" MPD_INDEX="19" NAME="SCK_I" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ps7_qspi_0" IS_VALID="FALSE" MPD_INDEX="20" NAME="SCK_O" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ps7_qspi_0" IS_VALID="FALSE" MPD_INDEX="21" NAME="SCK_T" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="ps7_qspi_0" MPD_INDEX="22" NAME="SS_I" SIGNAME="__NOC__" VECFORMULA="[(1-1):0]"/>
-        <PORT DIR="O" IOS="ps7_qspi_0" MPD_INDEX="23" NAME="SS_O" SIGNAME="__NOC__" VECFORMULA="[(1-1):0]"/>
-        <PORT DIR="O" IOS="ps7_qspi_0" MPD_INDEX="24" NAME="SS_T" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="ps7_qspi_0" MPD_INDEX="25" NAME="SPISEL" SIGNAME="__NOC__">
-          <DESCRIPTION>Local QSPI Slave Select Active LOW Input</DESCRIPTION>
-        </PORT>
-        <PORT DIR="I" IOS="ps7_qspi_0" MPD_INDEX="26" NAME="IO0_I" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ps7_qspi_0" MPD_INDEX="27" NAME="IO0_O" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ps7_qspi_0" MPD_INDEX="28" NAME="IO0_T" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="ps7_qspi_0" MPD_INDEX="29" NAME="IO1_I" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ps7_qspi_0" MPD_INDEX="30" NAME="IO1_O" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ps7_qspi_0" MPD_INDEX="31" NAME="IO1_T" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="ps7_qspi_0" IS_VALID="FALSE" MPD_INDEX="32" NAME="IO2_I" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ps7_qspi_0" IS_VALID="FALSE" MPD_INDEX="33" NAME="IO2_O" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ps7_qspi_0" IS_VALID="FALSE" MPD_INDEX="34" NAME="IO2_T" SIGNAME="__NOC__"/>
-        <PORT DIR="I" IOS="ps7_qspi_0" IS_VALID="FALSE" MPD_INDEX="35" NAME="IO3_I" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ps7_qspi_0" IS_VALID="FALSE" MPD_INDEX="36" NAME="IO3_O" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="ps7_qspi_0" IS_VALID="FALSE" MPD_INDEX="37" NAME="IO3_T" SIGNAME="__NOC__"/>
-        <PORT DIR="IO" IOS="ps7_qspi_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="38" NAME="SCK" SIGNAME="__NOC__" TRI_I="SCK_I" TRI_O="SCK_O" TRI_T="SCK_T">
-          <DESCRIPTION>QSPI Bus Clock</DESCRIPTION>
-        </PORT>
-        <PORT DIR="IO" IOS="ps7_qspi_0" IS_THREE_STATE="TRUE" MPD_INDEX="39" NAME="SS" SIGNAME="__NOC__" TRI_I="SS_I" TRI_O="SS_O" TRI_T="SS_T" VECFORMULA="[(1-1):0]">
-          <DESCRIPTION>Slave Select Vector</DESCRIPTION>
-        </PORT>
-        <PORT DIR="IO" IOS="ps7_qspi_0" IS_THREE_STATE="TRUE" MPD_INDEX="40" NAME="IO0" SIGNAME="__NOC__" TRI_I="IO0_I" TRI_O="IO0_O" TRI_T="IO0_T">
-          <DESCRIPTION>Similar to Master Out Slave In</DESCRIPTION>
-        </PORT>
-        <PORT DIR="IO" IOS="ps7_qspi_0" IS_THREE_STATE="TRUE" MPD_INDEX="41" NAME="IO1" SIGNAME="__NOC__" TRI_I="IO1_I" TRI_O="IO1_O" TRI_T="IO1_T">
-          <DESCRIPTION>Similar to Master In Slave Out</DESCRIPTION>
-        </PORT>
-        <PORT DIR="IO" IOS="ps7_qspi_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="42" NAME="IO2" SIGNAME="__NOC__" TRI_I="IO2_I" TRI_O="IO2_O" TRI_T="IO2_T">
-          <DESCRIPTION>3rd Data line in QUAD mode</DESCRIPTION>
-        </PORT>
-        <PORT DIR="IO" IOS="ps7_qspi_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="43" NAME="IO3" SIGNAME="__NOC__" TRI_I="IO3_I" TRI_O="IO3_O" TRI_T="IO3_T">
-          <DESCRIPTION>4th Data line in QUAD mode</DESCRIPTION>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <IOINTERFACES>
-        <IOINTERFACE MPD_INDEX="0" NAME="ps7_qspi_0" TYPE="XIL_QSPI_V1">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="SCK_I"/>
-            <PORTMAP DIR="O" PHYSICAL="SCK_O"/>
-            <PORTMAP DIR="O" PHYSICAL="SCK_T"/>
-            <PORTMAP DIR="I" PHYSICAL="SS_I"/>
-            <PORTMAP DIR="O" PHYSICAL="SS_O"/>
-            <PORTMAP DIR="O" PHYSICAL="SS_T"/>
-            <PORTMAP DIR="I" PHYSICAL="SPISEL"/>
-            <PORTMAP DIR="I" PHYSICAL="IO0_I"/>
-            <PORTMAP DIR="O" PHYSICAL="IO0_O"/>
-            <PORTMAP DIR="O" PHYSICAL="IO0_T"/>
-            <PORTMAP DIR="I" PHYSICAL="IO1_I"/>
-            <PORTMAP DIR="O" PHYSICAL="IO1_O"/>
-            <PORTMAP DIR="O" PHYSICAL="IO1_T"/>
-            <PORTMAP DIR="I" PHYSICAL="IO2_I"/>
-            <PORTMAP DIR="O" PHYSICAL="IO2_O"/>
-            <PORTMAP DIR="O" PHYSICAL="IO2_T"/>
-            <PORTMAP DIR="I" PHYSICAL="IO3_I"/>
-            <PORTMAP DIR="O" PHYSICAL="IO3_O"/>
-            <PORTMAP DIR="O" PHYSICAL="IO3_T"/>
-            <PORTMAP DIR="IO" PHYSICAL="SCK"/>
-            <PORTMAP DIR="IO" PHYSICAL="SS"/>
-            <PORTMAP DIR="IO" PHYSICAL="IO0"/>
-            <PORTMAP DIR="IO" PHYSICAL="IO1"/>
-            <PORTMAP DIR="IO" PHYSICAL="IO2"/>
-            <PORTMAP DIR="IO" PHYSICAL="IO3"/>
-          </PORTMAPS>
-        </IOINTERFACE>
-      </IOINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="3758149632" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE000D000" HIGHDECIMAL="3758153727" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE000DFFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_qspi_linear_0" IPTYPE="PERIPHERAL" MHS_INDEX="28" MODCLASS="MEMORY_CNTLR" MODTYPE="ps7_qspi_linear">
-      <DESCRIPTION TYPE="SHORT">PS7 QSPI LINEAR</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">QSPI LINEAR interface</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFC000000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFCFFFFFF"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_QSPI_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="15000000"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="4227858432" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xFC000000" HIGHDECIMAL="4244635647" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xFCFFFFFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="16777216" SIZEABRV="16M">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_ddr_0" IPTYPE="PERIPHERAL" MHS_INDEX="29" MODCLASS="MEMORY_CNTLR" MODTYPE="ps7_ddr">
-      <DESCRIPTION TYPE="SHORT">PS7 Memory Controller(DDR2/DDR3)</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">7-Series memory controller</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00100000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x1FFFFFFF"/>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="C_S_AXI_HP0_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="3" NAME="C_S_AXI_HP0_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x1FFFFFFF"/>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="4" NAME="C_S_AXI_HP1_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="5" NAME="C_S_AXI_HP1_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x1FFFFFFF"/>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="6" NAME="C_S_AXI_HP2_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="7" NAME="C_S_AXI_HP2_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x1FFFFFFF"/>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="8" NAME="C_S_AXI_HP3_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="9" NAME="C_S_AXI_HP3_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x1FFFFFFF"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="clk" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" MPD_INDEX="1" NAME="clk_ref" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" MPD_INDEX="2" NAME="mem_refclk" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" MPD_INDEX="3" NAME="freq_refclk" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" MPD_INDEX="4" NAME="pll_lock" SIGNAME="__NOC__"/>
-        <PORT DIR="I" MPD_INDEX="5" NAME="sync_pulse" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_aresetn" DIR="I" MPD_INDEX="6" NAME="aresetn" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_aresetn">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" MPD_INDEX="7" NAME="iodelay_ctrl_rdy_i" SIGNAME="__NOC__"/>
-        <PORT DIR="O" MPD_INDEX="8" NAME="iodelay_ctrl_rdy_o" SIGNAME="__NOC__"/>
-        <PORT DIR="O" MPD_INDEX="9" NAME="init_calib_complete" SIGNAME="__NOC__"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" LEFT="13" LSB="0" MPD_INDEX="10" MSB="13" NAME="ddr_addr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[13:0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" LEFT="2" LSB="0" MPD_INDEX="11" MSB="2" NAME="ddr_ba" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3-1:0]"/>
-        <PORT DIR="O" IOS="memory_0" MPD_INDEX="12" NAME="ddr_cas_n" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="memory_0" MPD_INDEX="13" NAME="ddr_ck_p" SIGIS="CLK" SIGNAME="__NOC__" VECFORMULA="[1-1:0]"/>
-        <PORT DIR="O" IOS="memory_0" MPD_INDEX="14" NAME="ddr_ck_n" SIGIS="CLK" SIGNAME="__NOC__" VECFORMULA="[1-1:0]"/>
-        <PORT DIR="O" IOS="memory_0" MPD_INDEX="15" NAME="ddr_cke" SIGNAME="__NOC__" VECFORMULA="[1-1:0]"/>
-        <PORT DIR="O" IOS="memory_0" MPD_INDEX="16" NAME="ddr_cs_n" SIGNAME="__NOC__" VECFORMULA="[1*1-1:0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" LEFT="3" LSB="0" MPD_INDEX="17" MSB="3" NAME="ddr_dm" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[4-1:0]"/>
-        <PORT DIR="O" IOS="memory_0" MPD_INDEX="18" NAME="ddr_odt" SIGNAME="__NOC__" VECFORMULA="[1*1-1:0]"/>
-        <PORT DIR="O" IOS="memory_0" MPD_INDEX="19" NAME="ddr_ras_n" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="memory_0" MPD_INDEX="20" NAME="ddr_reset_n" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="memory_0" MPD_INDEX="21" NAME="ddr_parity" SIGNAME="__NOC__"/>
-        <PORT DIR="O" IOS="memory_0" MPD_INDEX="22" NAME="ddr_we_n" SIGNAME="__NOC__"/>
-        <PORT DIR="IO" ENDIAN="LITTLE" IOS="memory_0" IS_THREE_STATE="FALSE" LEFT="30" LSB="0" MPD_INDEX="23" MSB="30" NAME="ddr_dq" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31-1:0]"/>
-        <PORT DIR="IO" ENDIAN="LITTLE" IOS="memory_0" IS_THREE_STATE="FALSE" LEFT="3" LSB="0" MPD_INDEX="24" MSB="3" NAME="ddr_dqs_p" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[4-1:0]"/>
-        <PORT DIR="IO" ENDIAN="LITTLE" IOS="memory_0" IS_THREE_STATE="FALSE" LEFT="3" LSB="0" MPD_INDEX="25" MSB="3" NAME="ddr_dqs_n" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[4-1:0]"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_awid" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="26" MSB="3" NAME="s_axi_awid" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_awid" VECFORMULA="[(4-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_awaddr" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="27" MSB="31" NAME="s_axi_awaddr" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_awaddr" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_awlen" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="28" MSB="7" NAME="s_axi_awlen" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_awlen" VECFORMULA="[7:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWLEN"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_awsize" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="29" MSB="2" NAME="s_axi_awsize" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_awsize" VECFORMULA="[2:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWSIZE"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_awburst" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="30" MSB="1" NAME="s_axi_awburst" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_awburst" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWBURST"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_awlock" DIR="I" MPD_INDEX="31" NAME="s_axi_awlock" SIGNAME="ps7_axi_interconnect_0_M_awlock" VECFORMULA="[0:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWLOCK"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_awcache" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="32" MSB="3" NAME="s_axi_awcache" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_awcache" VECFORMULA="[3:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWCACHE"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_awprot" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="33" MSB="2" NAME="s_axi_awprot" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_awprot" VECFORMULA="[2:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWPROT"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_awqos" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="34" MSB="3" NAME="s_axi_awqos" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_awqos" VECFORMULA="[3:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWQOS"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_awvalid" DIR="I" MPD_INDEX="35" NAME="s_axi_awvalid" SIGNAME="ps7_axi_interconnect_0_M_awvalid">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_awready" DIR="O" MPD_INDEX="36" NAME="s_axi_awready" SIGNAME="ps7_axi_interconnect_0_M_awready">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_wdata" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="37" MSB="31" NAME="s_axi_wdata" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_wdata" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_wstrb" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="38" MSB="3" NAME="s_axi_wstrb" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_wstrb" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_wlast" DIR="I" MPD_INDEX="39" NAME="s_axi_wlast" SIGNAME="ps7_axi_interconnect_0_M_wlast">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WLAST"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_wvalid" DIR="I" MPD_INDEX="40" NAME="s_axi_wvalid" SIGNAME="ps7_axi_interconnect_0_M_wvalid">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_wready" DIR="O" MPD_INDEX="41" NAME="s_axi_wready" SIGNAME="ps7_axi_interconnect_0_M_wready">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_bid" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="42" MSB="3" NAME="s_axi_bid" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_bid" VECFORMULA="[(4-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_bresp" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="43" MSB="1" NAME="s_axi_bresp" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_bresp" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_bvalid" DIR="O" MPD_INDEX="44" NAME="s_axi_bvalid" SIGNAME="ps7_axi_interconnect_0_M_bvalid">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_bready" DIR="I" MPD_INDEX="45" NAME="s_axi_bready" SIGNAME="ps7_axi_interconnect_0_M_bready">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_arid" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="46" MSB="3" NAME="s_axi_arid" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_arid" VECFORMULA="[(4-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_araddr" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="47" MSB="31" NAME="s_axi_araddr" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_araddr" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_arlen" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="48" MSB="7" NAME="s_axi_arlen" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_arlen" VECFORMULA="[7:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARLEN"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_arsize" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="49" MSB="2" NAME="s_axi_arsize" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_arsize" VECFORMULA="[2:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARSIZE"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_arburst" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="50" MSB="1" NAME="s_axi_arburst" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_arburst" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARBURST"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_arlock" DIR="I" MPD_INDEX="51" NAME="s_axi_arlock" SIGNAME="ps7_axi_interconnect_0_M_arlock" VECFORMULA="[0:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARLOCK"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_arcache" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="52" MSB="3" NAME="s_axi_arcache" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_arcache" VECFORMULA="[3:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARCACHE"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_arprot" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="53" MSB="2" NAME="s_axi_arprot" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_arprot" VECFORMULA="[2:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARPROT"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_arqos" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="54" MSB="3" NAME="s_axi_arqos" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_arqos" VECFORMULA="[3:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARQOS"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_arvalid" DIR="I" MPD_INDEX="55" NAME="s_axi_arvalid" SIGNAME="ps7_axi_interconnect_0_M_arvalid">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_arready" DIR="O" MPD_INDEX="56" NAME="s_axi_arready" SIGNAME="ps7_axi_interconnect_0_M_arready">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_rid" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="57" MSB="3" NAME="s_axi_rid" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_rid" VECFORMULA="[(4-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_rdata" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="58" MSB="31" NAME="s_axi_rdata" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_rdata" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_rresp" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="59" MSB="1" NAME="s_axi_rresp" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_rresp" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_rlast" DIR="O" MPD_INDEX="60" NAME="s_axi_rlast" SIGNAME="ps7_axi_interconnect_0_M_rlast">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RLAST"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_rvalid" DIR="O" MPD_INDEX="61" NAME="s_axi_rvalid" SIGNAME="ps7_axi_interconnect_0_M_rvalid">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_rready" DIR="I" MPD_INDEX="62" NAME="s_axi_rready" SIGNAME="ps7_axi_interconnect_0_M_rready">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="clk"/>
-            <PORTMAP DIR="I" PHYSICAL="aresetn"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_awid"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_awaddr"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_awlen"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_awsize"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_awburst"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_awlock"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_awcache"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_awprot"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_awqos"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_awvalid"/>
-            <PORTMAP DIR="O" PHYSICAL="s_axi_awready"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_wdata"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_wstrb"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_wlast"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_wvalid"/>
-            <PORTMAP DIR="O" PHYSICAL="s_axi_wready"/>
-            <PORTMAP DIR="O" PHYSICAL="s_axi_bid"/>
-            <PORTMAP DIR="O" PHYSICAL="s_axi_bresp"/>
-            <PORTMAP DIR="O" PHYSICAL="s_axi_bvalid"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_bready"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_arid"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_araddr"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_arlen"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_arsize"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_arburst"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_arlock"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_arcache"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_arprot"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_arqos"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_arvalid"/>
-            <PORTMAP DIR="O" PHYSICAL="s_axi_arready"/>
-            <PORTMAP DIR="O" PHYSICAL="s_axi_rid"/>
-            <PORTMAP DIR="O" PHYSICAL="s_axi_rdata"/>
-            <PORTMAP DIR="O" PHYSICAL="s_axi_rresp"/>
-            <PORTMAP DIR="O" PHYSICAL="s_axi_rlast"/>
-            <PORTMAP DIR="O" PHYSICAL="s_axi_rvalid"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_rready"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="1" NAME="S_AXI_HP0" TYPE="SLAVE"/>
-        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="2" NAME="S_AXI_HP1" TYPE="SLAVE"/>
-        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="3" NAME="S_AXI_HP2" TYPE="SLAVE"/>
-        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="4" NAME="S_AXI_HP3" TYPE="SLAVE"/>
-      </BUSINTERFACES>
-      <IOINTERFACES>
-        <IOINTERFACE MPD_INDEX="0" NAME="memory_0" TYPE="hide_122_XIL_MEMORY_V1">
-          <PORTMAPS>
-            <PORTMAP DIR="O" PHYSICAL="ddr_addr"/>
-            <PORTMAP DIR="O" PHYSICAL="ddr_ba"/>
-            <PORTMAP DIR="O" PHYSICAL="ddr_cas_n"/>
-            <PORTMAP DIR="O" PHYSICAL="ddr_ck_p"/>
-            <PORTMAP DIR="O" PHYSICAL="ddr_ck_n"/>
-            <PORTMAP DIR="O" PHYSICAL="ddr_cke"/>
-            <PORTMAP DIR="O" PHYSICAL="ddr_cs_n"/>
-            <PORTMAP DIR="O" PHYSICAL="ddr_dm"/>
-            <PORTMAP DIR="O" PHYSICAL="ddr_odt"/>
-            <PORTMAP DIR="O" PHYSICAL="ddr_ras_n"/>
-            <PORTMAP DIR="O" PHYSICAL="ddr_reset_n"/>
-            <PORTMAP DIR="O" PHYSICAL="ddr_parity"/>
-            <PORTMAP DIR="O" PHYSICAL="ddr_we_n"/>
-            <PORTMAP DIR="IO" PHYSICAL="ddr_dq"/>
-            <PORTMAP DIR="IO" PHYSICAL="ddr_dqs_p"/>
-            <PORTMAP DIR="IO" PHYSICAL="ddr_dqs_n"/>
-          </PORTMAPS>
-        </IOINTERFACE>
-      </IOINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="1048576" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0x00100000" HIGHDECIMAL="536870911" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0x1FFFFFFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="535822336" SIZEABRV="U">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="0" BASENAME="C_S_AXI_HP0_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="536870911" HIGHNAME="C_S_AXI_HP0_HIGHADDR" HIGHVALUE="0x1FFFFFFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="536870912" SIZEABRV="512M">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI_HP0"/>
-          </SLAVES>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="0" BASENAME="C_S_AXI_HP1_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="536870911" HIGHNAME="C_S_AXI_HP1_HIGHADDR" HIGHVALUE="0x1FFFFFFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="536870912" SIZEABRV="512M">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI_HP1"/>
-          </SLAVES>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="0" BASENAME="C_S_AXI_HP2_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="536870911" HIGHNAME="C_S_AXI_HP2_HIGHADDR" HIGHVALUE="0x1FFFFFFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="536870912" SIZEABRV="512M">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI_HP2"/>
-          </SLAVES>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="0" BASENAME="C_S_AXI_HP3_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="536870911" HIGHNAME="C_S_AXI_HP3_HIGHADDR" HIGHVALUE="0x1FFFFFFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="536870912" SIZEABRV="512M">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI_HP3"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_gpio_0" IPTYPE="PERIPHERAL" MHS_INDEX="30" MODCLASS="PERIPHERAL" MODTYPE="ps7_gpio">
-      <DESCRIPTION TYPE="SHORT">PS7 General Purpose IO</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the PS7.</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE000A000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE000AFFF"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="C_MIO_GPIO_MASK" TYPE="STD_LOGIC_VECTOR" VALUE="0xc00000000c281"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="3" NAME="C_EMIO_GPIO_WIDTH" TYPE="INTEGER" VALUE="64"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" LEFT="63" LSB="0" MPD_INDEX="19" MSB="63" NAME="GPIO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[63:0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="63" LSB="0" MPD_INDEX="20" MSB="63" NAME="GPIO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[63:0]"/>
-        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="63" LSB="0" MPD_INDEX="21" MSB="63" NAME="GPIO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[63:0]"/>
-        <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" LEFT="63" LSB="0" MPD_INDEX="22" MSB="63" NAME="GPIO_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[63:0]">
-          <DESCRIPTION>GPIO Data IO</DESCRIPTION>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <IOINTERFACES>
-        <IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_AXI_GPIO_V1">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="GPIO_I"/>
-            <PORTMAP DIR="O" PHYSICAL="GPIO_O"/>
-            <PORTMAP DIR="O" PHYSICAL="GPIO_T"/>
-            <PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/>
-          </PORTMAPS>
-        </IOINTERFACE>
-      </IOINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="3758137344" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE000A000" HIGHDECIMAL="3758141439" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE000AFFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="5.02.a" INSTANCE="ps7_cortexa9_0" IPTYPE="PROCESSOR" MHS_INDEX="31" MODCLASS="PROCESSOR" MODTYPE="ps7_cortexa9">
-      <DESCRIPTION TYPE="SHORT">Processing System</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">ZYNQ Processing System</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="C_CPU_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="650000000"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="1" NAME="C_CPU_1X_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="108333336"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="2" NAME="C_CPU_REF_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" MPD_INDEX="1" NAME="MB_RESET" SIGIS="RST" SIGNAME="__NOC__"/>
-        <PORT DIR="I" MPD_INDEX="2" NAME="INTERRUPT" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DEF_SIGNAME="Ext_BRK" DIR="I" MPD_INDEX="3" NAME="EXT_BRK" SIGNAME="Ext_BRK">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="Ext_NM_BRK" DIR="I" MPD_INDEX="4" NAME="EXT_NM_BRK" SIGNAME="Ext_NM_BRK">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="I" MPD_INDEX="5" NAME="DBG_STOP" SIGNAME="__NOC__"/>
-        <PORT DIR="O" MPD_INDEX="6" NAME="MB_Halted" SIGNAME="__NOC__"/>
-        <PORT DIR="O" MPD_INDEX="7" NAME="MB_Error" SIGNAME="__NOC__"/>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWID" DIR="O" MPD_INDEX="8" NAME="M_AXI_DP_AWID" SIGNAME="ps7_axi_interconnect_0_S_AWID" VECFORMULA="[(1-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="9" MSB="31" NAME="M_AXI_DP_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="10" MSB="7" NAME="M_AXI_DP_AWLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWLEN" VECFORMULA="[7:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWLEN"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="11" MSB="2" NAME="M_AXI_DP_AWSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWSIZE" VECFORMULA="[2:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWSIZE"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="12" MSB="1" NAME="M_AXI_DP_AWBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWBURST" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWBURST"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWLOCK" DIR="O" MPD_INDEX="13" NAME="M_AXI_DP_AWLOCK" SIGNAME="ps7_axi_interconnect_0_S_AWLOCK">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWLOCK"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="14" MSB="3" NAME="M_AXI_DP_AWCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWCACHE" VECFORMULA="[3:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWCACHE"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="15" MSB="2" NAME="M_AXI_DP_AWPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWPROT" VECFORMULA="[2:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWPROT"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="16" MSB="3" NAME="M_AXI_DP_AWQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWQOS" VECFORMULA="[3:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWQOS"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWVALID" DIR="O" MPD_INDEX="17" NAME="M_AXI_DP_AWVALID" SIGNAME="ps7_axi_interconnect_0_S_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWREADY" DIR="I" MPD_INDEX="18" NAME="M_AXI_DP_AWREADY" SIGNAME="ps7_axi_interconnect_0_S_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="M_AXI_DP_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="20" MSB="3" NAME="M_AXI_DP_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_WLAST" DIR="O" MPD_INDEX="21" NAME="M_AXI_DP_WLAST" SIGNAME="ps7_axi_interconnect_0_S_WLAST">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_WLAST"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_WVALID" DIR="O" MPD_INDEX="22" NAME="M_AXI_DP_WVALID" SIGNAME="ps7_axi_interconnect_0_S_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_WREADY" DIR="I" MPD_INDEX="23" NAME="M_AXI_DP_WREADY" SIGNAME="ps7_axi_interconnect_0_S_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_BID" DIR="I" MPD_INDEX="24" NAME="M_AXI_DP_BID" SIGNAME="ps7_axi_interconnect_0_S_BID" VECFORMULA="[(1-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_BID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="25" MSB="1" NAME="M_AXI_DP_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_BVALID" DIR="I" MPD_INDEX="26" NAME="M_AXI_DP_BVALID" SIGNAME="ps7_axi_interconnect_0_S_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_BREADY" DIR="O" MPD_INDEX="27" NAME="M_AXI_DP_BREADY" SIGNAME="ps7_axi_interconnect_0_S_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARID" DIR="O" MPD_INDEX="28" NAME="M_AXI_DP_ARID" SIGNAME="ps7_axi_interconnect_0_S_ARID" VECFORMULA="[(1-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="29" MSB="31" NAME="M_AXI_DP_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="30" MSB="7" NAME="M_AXI_DP_ARLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARLEN" VECFORMULA="[7:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARLEN"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="31" MSB="2" NAME="M_AXI_DP_ARSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARSIZE" VECFORMULA="[2:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARSIZE"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="32" MSB="1" NAME="M_AXI_DP_ARBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARBURST" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARBURST"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARLOCK" DIR="O" MPD_INDEX="33" NAME="M_AXI_DP_ARLOCK" SIGNAME="ps7_axi_interconnect_0_S_ARLOCK">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARLOCK"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="34" MSB="3" NAME="M_AXI_DP_ARCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARCACHE" VECFORMULA="[3:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARCACHE"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="35" MSB="2" NAME="M_AXI_DP_ARPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARPROT" VECFORMULA="[2:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARPROT"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="36" MSB="3" NAME="M_AXI_DP_ARQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARQOS" VECFORMULA="[3:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARQOS"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARVALID" DIR="O" MPD_INDEX="37" NAME="M_AXI_DP_ARVALID" SIGNAME="ps7_axi_interconnect_0_S_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARREADY" DIR="I" MPD_INDEX="38" NAME="M_AXI_DP_ARREADY" SIGNAME="ps7_axi_interconnect_0_S_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_RID" DIR="I" MPD_INDEX="39" NAME="M_AXI_DP_RID" SIGNAME="ps7_axi_interconnect_0_S_RID" VECFORMULA="[(1-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_RID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="40" MSB="31" NAME="M_AXI_DP_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="41" MSB="1" NAME="M_AXI_DP_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_RLAST" DIR="I" MPD_INDEX="42" NAME="M_AXI_DP_RLAST" SIGNAME="ps7_axi_interconnect_0_S_RLAST">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_RLAST"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_RVALID" DIR="I" MPD_INDEX="43" NAME="M_AXI_DP_RVALID" SIGNAME="ps7_axi_interconnect_0_S_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_RREADY" DIR="O" MPD_INDEX="44" NAME="M_AXI_DP_RREADY" SIGNAME="ps7_axi_interconnect_0_S_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="M_AXI_DP" TYPE="MASTER">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="CLK"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWID"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWADDR"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLEN"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWSIZE"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWBURST"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLOCK"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWCACHE"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWPROT"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWQOS"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_AWREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WSTRB"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WLAST"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_WREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BID"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BRESP"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_BREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARID"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARADDR"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLEN"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARSIZE"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARBURST"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLOCK"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARCACHE"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARPROT"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARQOS"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_ARREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RID"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RRESP"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RLAST"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_RREADY"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="3758096384" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0000000" HIGHDECIMAL="3758100479" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0000FFF" INSTANCE="ps7_uart_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="3758100480" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0001000" HIGHDECIMAL="3758104575" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0001FFF" INSTANCE="ps7_uart_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="3758112768" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0004000" HIGHDECIMAL="3758116863" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0004FFF" INSTANCE="ps7_i2c_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4160782336" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8008000" HIGHDECIMAL="4160786431" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8008FFF" INSTANCE="ps7_afi_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4160786432" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8009000" HIGHDECIMAL="4160790527" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8009FFF" INSTANCE="ps7_afi_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4160790528" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF800A000" HIGHDECIMAL="4160794623" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF800AFFF" INSTANCE="ps7_afi_2" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4160794624" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF800B000" HIGHDECIMAL="4160798719" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF800BFFF" INSTANCE="ps7_afi_3" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="3758116864" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0005000" HIGHDECIMAL="3758120959" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0005FFF" INSTANCE="ps7_i2c_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="3759144960" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0100000" HIGHDECIMAL="3759149055" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0100FFF" INSTANCE="ps7_sd_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="3758141440" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE000B000" HIGHDECIMAL="3758145535" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE000BFFF" INSTANCE="ps7_ethernet_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="3758104576" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0002000" HIGHDECIMAL="3758108671" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0002FFF" INSTANCE="ps7_usb_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="3758149632" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE000D000" HIGHDECIMAL="3758153727" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE000DFFF" INSTANCE="ps7_qspi_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4227858432" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xFC000000" HIGHDECIMAL="4244635647" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xFCFFFFFF" INSTANCE="ps7_qspi_linear_0" IS_DATA="FALSE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="16777216" SIZEABRV="16M">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="1048576" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0x00100000" HIGHDECIMAL="536870911" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0x1FFFFFFF" INSTANCE="ps7_ddr_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="535822336" SIZEABRV="U">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="3758137344" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE000A000" HIGHDECIMAL="3758141439" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE000AFFF" INSTANCE="ps7_gpio_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4160774144" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8006000" HIGHDECIMAL="4160778239" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8006FFF" INSTANCE="ps7_ddrc_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4160778240" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8007000" HIGHDECIMAL="4160778495" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF80070FF" INSTANCE="ps7_dev_cfg_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="256" SIZEABRV="256">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4160778496" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8007100" HIGHDECIMAL="4160778528" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8007120" INSTANCE="ps7_xadc_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="33" SIZEABRV="U">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4169138176" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8800000" HIGHDECIMAL="4170186751" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF88FFFFF" INSTANCE="ps7_coresight_comp_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="1048576" SIZEABRV="1M">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4160798720" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF800C000" HIGHDECIMAL="4160802815" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF800CFFF" INSTANCE="ps7_ocmc_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4170186752" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8900000" HIGHDECIMAL="4171235327" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF89FFFFF" INSTANCE="ps7_gpv_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="1048576" SIZEABRV="1M">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4176478208" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F00000" HIGHDECIMAL="4176478460" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F000FC" INSTANCE="ps7_scuc_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="253" SIZEABRV="U">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4176482304" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F01000" HIGHDECIMAL="4176486399" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F01FFF" INSTANCE="ps7_intc_dist_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4176478720" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F00200" HIGHDECIMAL="4176478975" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F002FF" INSTANCE="ps7_globaltimer_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="256" SIZEABRV="256">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4176486400" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F02000" HIGHDECIMAL="4176490495" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F02FFF" INSTANCE="ps7_l2cachec_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4160761856" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8003000" HIGHDECIMAL="4160765951" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8003FFF" INSTANCE="ps7_dma_s" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="3760193536" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0200000" HIGHDECIMAL="3760197631" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0200FFF" INSTANCE="ps7_iop_bus_config_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="0" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="196607" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0x0002FFFF" INSTANCE="ps7_ram_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="196608" SIZEABRV="U">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4294901760" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xFFFF0000" HIGHDECIMAL="4294966783" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xFFFFFDFF" INSTANCE="ps7_ram_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="65024" SIZEABRV="U">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4176478464" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F00100" HIGHDECIMAL="4176478719" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F001FF" INSTANCE="ps7_scugic_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="256" SIZEABRV="256">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4176479744" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F00600" HIGHDECIMAL="4176479775" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F0061F" INSTANCE="ps7_scutimer_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="32" SIZEABRV="32">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4176479776" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F00620" HIGHDECIMAL="4176479999" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F006FF" INSTANCE="ps7_scuwdt_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="224" SIZEABRV="U">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4160749568" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8000000" HIGHDECIMAL="4160753663" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8000FFF" INSTANCE="ps7_slcr_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4160765952" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8004000" HIGHDECIMAL="4160770047" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8004FFF" INSTANCE="ps7_dma_ns" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="1995046912" BASENAME="C_BASEADDR" BASEVALUE="0x76ea0000" HIGHDECIMAL="1995112447" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76eaffff" INSTANCE="pwm_recorder_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-            <ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="1994915840" BASENAME="C_BASEADDR" BASEVALUE="0x76e80000" HIGHDECIMAL="1994981375" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e8ffff" INSTANCE="pwm_recorder_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-            <ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="1994784768" BASENAME="C_BASEADDR" BASEVALUE="0x76e60000" HIGHDECIMAL="1994850303" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e6ffff" INSTANCE="pwm_recorder_2" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-            <ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="1994653696" BASENAME="C_BASEADDR" BASEVALUE="0x76e40000" HIGHDECIMAL="1994719231" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e4ffff" INSTANCE="pwm_recorder_3" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-            <ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="1994522624" BASENAME="C_BASEADDR" BASEVALUE="0x76e20000" HIGHDECIMAL="1994588159" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e2ffff" INSTANCE="pwm_recorder_4" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-            <ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="1994391552" BASENAME="C_BASEADDR" BASEVALUE="0x76e00000" HIGHDECIMAL="1994457087" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e0ffff" INSTANCE="pwm_recorder_5" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-            <ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="1092616192" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHDECIMAL="1092681727" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120ffff" INSTANCE="btns_4bits_tri_io" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-            <ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="2034630656" BASENAME="C_BASEADDR" BASEVALUE="0x79460000" HIGHDECIMAL="2034696191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7946ffff" INSTANCE="pwm_signal_out_wkillswitch_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-            <ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="2034499584" BASENAME="C_BASEADDR" BASEVALUE="0x79440000" HIGHDECIMAL="2034565119" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7944ffff" INSTANCE="pwm_signal_out_wkillswitch_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-            <ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="2034368512" BASENAME="C_BASEADDR" BASEVALUE="0x79420000" HIGHDECIMAL="2034434047" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7942ffff" INSTANCE="pwm_signal_out_wkillswitch_2" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-            <ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="2034237440" BASENAME="C_BASEADDR" BASEVALUE="0x79400000" HIGHDECIMAL="2034302975" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7940ffff" INSTANCE="pwm_signal_out_wkillswitch_3" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-            <ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="1115684864" BASENAME="C_BASEADDR" BASEVALUE="0x42800000" HIGHDECIMAL="1115750399" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4280ffff" INSTANCE="axi_timer_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-            <ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-      </MEMORYMAP>
-      <PERIPHERALS>
-        <PERIPHERAL INSTANCE="ps7_uart_0"/>
-        <PERIPHERAL INSTANCE="ps7_uart_1"/>
-        <PERIPHERAL INSTANCE="ps7_i2c_0"/>
-        <PERIPHERAL INSTANCE="ps7_afi_0"/>
-        <PERIPHERAL INSTANCE="ps7_afi_1"/>
-        <PERIPHERAL INSTANCE="ps7_afi_2"/>
-        <PERIPHERAL INSTANCE="ps7_afi_3"/>
-        <PERIPHERAL INSTANCE="ps7_i2c_1"/>
-        <PERIPHERAL INSTANCE="ps7_sd_0"/>
-        <PERIPHERAL INSTANCE="ps7_ethernet_0"/>
-        <PERIPHERAL INSTANCE="ps7_usb_0"/>
-        <PERIPHERAL INSTANCE="ps7_qspi_0"/>
-        <PERIPHERAL INSTANCE="ps7_qspi_linear_0"/>
-        <PERIPHERAL INSTANCE="ps7_ddr_0"/>
-        <PERIPHERAL INSTANCE="ps7_gpio_0"/>
-        <PERIPHERAL INSTANCE="ps7_ddrc_0"/>
-        <PERIPHERAL INSTANCE="ps7_dev_cfg_0"/>
-        <PERIPHERAL INSTANCE="ps7_xadc_0"/>
-        <PERIPHERAL INSTANCE="ps7_coresight_comp_0"/>
-        <PERIPHERAL INSTANCE="ps7_ocmc_0"/>
-        <PERIPHERAL INSTANCE="ps7_gpv_0"/>
-        <PERIPHERAL INSTANCE="ps7_scuc_0"/>
-        <PERIPHERAL INSTANCE="ps7_intc_dist_0"/>
-        <PERIPHERAL INSTANCE="ps7_globaltimer_0"/>
-        <PERIPHERAL INSTANCE="ps7_l2cachec_0"/>
-        <PERIPHERAL INSTANCE="ps7_dma_s"/>
-        <PERIPHERAL INSTANCE="ps7_iop_bus_config_0"/>
-        <PERIPHERAL INSTANCE="ps7_ram_0"/>
-        <PERIPHERAL INSTANCE="ps7_ram_1"/>
-        <PERIPHERAL INSTANCE="ps7_scugic_0"/>
-        <PERIPHERAL INSTANCE="ps7_scutimer_0"/>
-        <PERIPHERAL INSTANCE="ps7_scuwdt_0"/>
-        <PERIPHERAL INSTANCE="ps7_slcr_0"/>
-        <PERIPHERAL INSTANCE="ps7_dma_ns"/>
-        <PERIPHERAL INSTANCE="pwm_recorder_0"/>
-        <PERIPHERAL INSTANCE="pwm_recorder_1"/>
-        <PERIPHERAL INSTANCE="pwm_recorder_2"/>
-        <PERIPHERAL INSTANCE="pwm_recorder_3"/>
-        <PERIPHERAL INSTANCE="pwm_recorder_4"/>
-        <PERIPHERAL INSTANCE="pwm_recorder_5"/>
-        <PERIPHERAL INSTANCE="btns_4bits_tri_io"/>
-        <PERIPHERAL INSTANCE="pwm_signal_out_wkillswitch_0"/>
-        <PERIPHERAL INSTANCE="pwm_signal_out_wkillswitch_1"/>
-        <PERIPHERAL INSTANCE="pwm_signal_out_wkillswitch_2"/>
-        <PERIPHERAL INSTANCE="pwm_signal_out_wkillswitch_3"/>
-        <PERIPHERAL INSTANCE="axi_timer_0"/>
-      </PERIPHERALS>
-    </MODULE>
-    <MODULE HWVERSION="5.02.a" INSTANCE="ps7_cortexa9_1" IPTYPE="PROCESSOR" MHS_INDEX="32" MODCLASS="PROCESSOR" MODTYPE="ps7_cortexa9">
-      <DESCRIPTION TYPE="SHORT">Processing System</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">ZYNQ Processing System</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="C_CPU_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="650000000"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="1" NAME="C_CPU_1X_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="108333336"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="2" NAME="C_CPU_REF_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT DIR="I" MPD_INDEX="1" NAME="MB_RESET" SIGIS="RST" SIGNAME="__NOC__"/>
-        <PORT DIR="I" MPD_INDEX="2" NAME="INTERRUPT" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DEF_SIGNAME="Ext_BRK" DIR="I" MPD_INDEX="3" NAME="EXT_BRK" SIGNAME="Ext_BRK">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="Ext_NM_BRK" DIR="I" MPD_INDEX="4" NAME="EXT_NM_BRK" SIGNAME="Ext_NM_BRK">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="I" MPD_INDEX="5" NAME="DBG_STOP" SIGNAME="__NOC__"/>
-        <PORT DIR="O" MPD_INDEX="6" NAME="MB_Halted" SIGNAME="__NOC__"/>
-        <PORT DIR="O" MPD_INDEX="7" NAME="MB_Error" SIGNAME="__NOC__"/>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWID" DIR="O" MPD_INDEX="8" NAME="M_AXI_DP_AWID" SIGNAME="ps7_axi_interconnect_0_S_AWID" VECFORMULA="[(1-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="9" MSB="31" NAME="M_AXI_DP_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="10" MSB="7" NAME="M_AXI_DP_AWLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWLEN" VECFORMULA="[7:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWLEN"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="11" MSB="2" NAME="M_AXI_DP_AWSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWSIZE" VECFORMULA="[2:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWSIZE"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="12" MSB="1" NAME="M_AXI_DP_AWBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWBURST" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWBURST"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWLOCK" DIR="O" MPD_INDEX="13" NAME="M_AXI_DP_AWLOCK" SIGNAME="ps7_axi_interconnect_0_S_AWLOCK">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWLOCK"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="14" MSB="3" NAME="M_AXI_DP_AWCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWCACHE" VECFORMULA="[3:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWCACHE"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="15" MSB="2" NAME="M_AXI_DP_AWPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWPROT" VECFORMULA="[2:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWPROT"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="16" MSB="3" NAME="M_AXI_DP_AWQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_AWQOS" VECFORMULA="[3:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWQOS"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWVALID" DIR="O" MPD_INDEX="17" NAME="M_AXI_DP_AWVALID" SIGNAME="ps7_axi_interconnect_0_S_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_AWREADY" DIR="I" MPD_INDEX="18" NAME="M_AXI_DP_AWREADY" SIGNAME="ps7_axi_interconnect_0_S_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="M_AXI_DP_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="20" MSB="3" NAME="M_AXI_DP_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_WLAST" DIR="O" MPD_INDEX="21" NAME="M_AXI_DP_WLAST" SIGNAME="ps7_axi_interconnect_0_S_WLAST">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_WLAST"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_WVALID" DIR="O" MPD_INDEX="22" NAME="M_AXI_DP_WVALID" SIGNAME="ps7_axi_interconnect_0_S_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_WREADY" DIR="I" MPD_INDEX="23" NAME="M_AXI_DP_WREADY" SIGNAME="ps7_axi_interconnect_0_S_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_BID" DIR="I" MPD_INDEX="24" NAME="M_AXI_DP_BID" SIGNAME="ps7_axi_interconnect_0_S_BID" VECFORMULA="[(1-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_BID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="25" MSB="1" NAME="M_AXI_DP_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_BVALID" DIR="I" MPD_INDEX="26" NAME="M_AXI_DP_BVALID" SIGNAME="ps7_axi_interconnect_0_S_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_BREADY" DIR="O" MPD_INDEX="27" NAME="M_AXI_DP_BREADY" SIGNAME="ps7_axi_interconnect_0_S_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARID" DIR="O" MPD_INDEX="28" NAME="M_AXI_DP_ARID" SIGNAME="ps7_axi_interconnect_0_S_ARID" VECFORMULA="[(1-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="29" MSB="31" NAME="M_AXI_DP_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="30" MSB="7" NAME="M_AXI_DP_ARLEN" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARLEN" VECFORMULA="[7:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARLEN"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="31" MSB="2" NAME="M_AXI_DP_ARSIZE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARSIZE" VECFORMULA="[2:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARSIZE"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="32" MSB="1" NAME="M_AXI_DP_ARBURST" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARBURST" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARBURST"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARLOCK" DIR="O" MPD_INDEX="33" NAME="M_AXI_DP_ARLOCK" SIGNAME="ps7_axi_interconnect_0_S_ARLOCK">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARLOCK"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="34" MSB="3" NAME="M_AXI_DP_ARCACHE" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARCACHE" VECFORMULA="[3:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARCACHE"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="35" MSB="2" NAME="M_AXI_DP_ARPROT" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARPROT" VECFORMULA="[2:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARPROT"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="36" MSB="3" NAME="M_AXI_DP_ARQOS" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_ARQOS" VECFORMULA="[3:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARQOS"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARVALID" DIR="O" MPD_INDEX="37" NAME="M_AXI_DP_ARVALID" SIGNAME="ps7_axi_interconnect_0_S_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_ARREADY" DIR="I" MPD_INDEX="38" NAME="M_AXI_DP_ARREADY" SIGNAME="ps7_axi_interconnect_0_S_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_RID" DIR="I" MPD_INDEX="39" NAME="M_AXI_DP_RID" SIGNAME="ps7_axi_interconnect_0_S_RID" VECFORMULA="[(1-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_RID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="40" MSB="31" NAME="M_AXI_DP_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="41" MSB="1" NAME="M_AXI_DP_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_S_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_RLAST" DIR="I" MPD_INDEX="42" NAME="M_AXI_DP_RLAST" SIGNAME="ps7_axi_interconnect_0_S_RLAST">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_RLAST"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_RVALID" DIR="I" MPD_INDEX="43" NAME="M_AXI_DP_RVALID" SIGNAME="ps7_axi_interconnect_0_S_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="M_AXI_DP" DEF_SIGNAME="ps7_axi_interconnect_0_S_RREADY" DIR="O" MPD_INDEX="44" NAME="M_AXI_DP_RREADY" SIGNAME="ps7_axi_interconnect_0_S_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="S_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="M_AXI_DP" TYPE="MASTER">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="CLK"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWID"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWADDR"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLEN"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWSIZE"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWBURST"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLOCK"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWCACHE"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWPROT"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWQOS"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_AWREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WSTRB"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WLAST"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_WREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BID"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BRESP"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_BREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARID"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARADDR"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLEN"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARSIZE"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARBURST"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLOCK"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARCACHE"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARPROT"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARQOS"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_ARREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RID"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RRESP"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RLAST"/>
-            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_RREADY"/>
-          </PORTMAPS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="3758096384" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0000000" HIGHDECIMAL="3758100479" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0000FFF" INSTANCE="ps7_uart_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="3758100480" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0001000" HIGHDECIMAL="3758104575" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0001FFF" INSTANCE="ps7_uart_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="3758112768" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0004000" HIGHDECIMAL="3758116863" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0004FFF" INSTANCE="ps7_i2c_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4160782336" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8008000" HIGHDECIMAL="4160786431" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8008FFF" INSTANCE="ps7_afi_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4160786432" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8009000" HIGHDECIMAL="4160790527" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8009FFF" INSTANCE="ps7_afi_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4160790528" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF800A000" HIGHDECIMAL="4160794623" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF800AFFF" INSTANCE="ps7_afi_2" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4160794624" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF800B000" HIGHDECIMAL="4160798719" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF800BFFF" INSTANCE="ps7_afi_3" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="3758116864" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0005000" HIGHDECIMAL="3758120959" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0005FFF" INSTANCE="ps7_i2c_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="3759144960" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0100000" HIGHDECIMAL="3759149055" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0100FFF" INSTANCE="ps7_sd_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="3758141440" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE000B000" HIGHDECIMAL="3758145535" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE000BFFF" INSTANCE="ps7_ethernet_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="3758104576" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0002000" HIGHDECIMAL="3758108671" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0002FFF" INSTANCE="ps7_usb_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="3758149632" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE000D000" HIGHDECIMAL="3758153727" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE000DFFF" INSTANCE="ps7_qspi_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4227858432" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xFC000000" HIGHDECIMAL="4244635647" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xFCFFFFFF" INSTANCE="ps7_qspi_linear_0" IS_DATA="FALSE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="16777216" SIZEABRV="16M">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="1048576" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0x00100000" HIGHDECIMAL="536870911" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0x1FFFFFFF" INSTANCE="ps7_ddr_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="535822336" SIZEABRV="U">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="3758137344" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE000A000" HIGHDECIMAL="3758141439" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE000AFFF" INSTANCE="ps7_gpio_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4160774144" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8006000" HIGHDECIMAL="4160778239" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8006FFF" INSTANCE="ps7_ddrc_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4160778240" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8007000" HIGHDECIMAL="4160778495" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF80070FF" INSTANCE="ps7_dev_cfg_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="256" SIZEABRV="256">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4160778496" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8007100" HIGHDECIMAL="4160778528" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8007120" INSTANCE="ps7_xadc_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="33" SIZEABRV="U">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4169138176" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8800000" HIGHDECIMAL="4170186751" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF88FFFFF" INSTANCE="ps7_coresight_comp_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="1048576" SIZEABRV="1M">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4160798720" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF800C000" HIGHDECIMAL="4160802815" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF800CFFF" INSTANCE="ps7_ocmc_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4170186752" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8900000" HIGHDECIMAL="4171235327" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF89FFFFF" INSTANCE="ps7_gpv_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="1048576" SIZEABRV="1M">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4176478208" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F00000" HIGHDECIMAL="4176478460" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F000FC" INSTANCE="ps7_scuc_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="253" SIZEABRV="U">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4176482304" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F01000" HIGHDECIMAL="4176486399" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F01FFF" INSTANCE="ps7_intc_dist_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4176478720" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F00200" HIGHDECIMAL="4176478975" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F002FF" INSTANCE="ps7_globaltimer_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="256" SIZEABRV="256">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4176486400" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F02000" HIGHDECIMAL="4176490495" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F02FFF" INSTANCE="ps7_l2cachec_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4160761856" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8003000" HIGHDECIMAL="4160765951" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8003FFF" INSTANCE="ps7_dma_s" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="3760193536" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0200000" HIGHDECIMAL="3760197631" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0200FFF" INSTANCE="ps7_iop_bus_config_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="0" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="196607" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0x0002FFFF" INSTANCE="ps7_ram_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="196608" SIZEABRV="U">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4294901760" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xFFFF0000" HIGHDECIMAL="4294966783" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xFFFFFDFF" INSTANCE="ps7_ram_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="65024" SIZEABRV="U">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4176478464" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F00100" HIGHDECIMAL="4176478719" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F001FF" INSTANCE="ps7_scugic_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="256" SIZEABRV="256">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4176479744" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F00600" HIGHDECIMAL="4176479775" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F0061F" INSTANCE="ps7_scutimer_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="32" SIZEABRV="32">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4176479776" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F00620" HIGHDECIMAL="4176479999" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F006FF" INSTANCE="ps7_scuwdt_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="224" SIZEABRV="U">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4160749568" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8000000" HIGHDECIMAL="4160753663" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8000FFF" INSTANCE="ps7_slcr_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4160765952" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8004000" HIGHDECIMAL="4160770047" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8004FFF" INSTANCE="ps7_dma_ns" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="1995046912" BASENAME="C_BASEADDR" BASEVALUE="0x76ea0000" HIGHDECIMAL="1995112447" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76eaffff" INSTANCE="pwm_recorder_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-            <ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="1994915840" BASENAME="C_BASEADDR" BASEVALUE="0x76e80000" HIGHDECIMAL="1994981375" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e8ffff" INSTANCE="pwm_recorder_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-            <ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="1994784768" BASENAME="C_BASEADDR" BASEVALUE="0x76e60000" HIGHDECIMAL="1994850303" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e6ffff" INSTANCE="pwm_recorder_2" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-            <ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="1994653696" BASENAME="C_BASEADDR" BASEVALUE="0x76e40000" HIGHDECIMAL="1994719231" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e4ffff" INSTANCE="pwm_recorder_3" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-            <ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="1994522624" BASENAME="C_BASEADDR" BASEVALUE="0x76e20000" HIGHDECIMAL="1994588159" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e2ffff" INSTANCE="pwm_recorder_4" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-            <ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="1994391552" BASENAME="C_BASEADDR" BASEVALUE="0x76e00000" HIGHDECIMAL="1994457087" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x76e0ffff" INSTANCE="pwm_recorder_5" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-            <ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="1092616192" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHDECIMAL="1092681727" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120ffff" INSTANCE="btns_4bits_tri_io" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-            <ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="2034630656" BASENAME="C_BASEADDR" BASEVALUE="0x79460000" HIGHDECIMAL="2034696191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7946ffff" INSTANCE="pwm_signal_out_wkillswitch_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-            <ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="2034499584" BASENAME="C_BASEADDR" BASEVALUE="0x79440000" HIGHDECIMAL="2034565119" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7944ffff" INSTANCE="pwm_signal_out_wkillswitch_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-            <ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="2034368512" BASENAME="C_BASEADDR" BASEVALUE="0x79420000" HIGHDECIMAL="2034434047" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7942ffff" INSTANCE="pwm_signal_out_wkillswitch_2" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-            <ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="2034237440" BASENAME="C_BASEADDR" BASEVALUE="0x79400000" HIGHDECIMAL="2034302975" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7940ffff" INSTANCE="pwm_signal_out_wkillswitch_3" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-            <ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="1115684864" BASENAME="C_BASEADDR" BASEVALUE="0x42800000" HIGHDECIMAL="1115750399" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4280ffff" INSTANCE="axi_timer_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
-          <ACCESSROUTE>
-            <ROUTEPNT INDEX="0" INSTANCE="ps7_axi_interconnect_0"/>
-            <ROUTEPNT INDEX="1" INSTANCE="axi_interconnect_1"/>
-          </ACCESSROUTE>
-        </MEMRANGE>
-      </MEMORYMAP>
-      <PERIPHERALS>
-        <PERIPHERAL INSTANCE="ps7_uart_0"/>
-        <PERIPHERAL INSTANCE="ps7_uart_1"/>
-        <PERIPHERAL INSTANCE="ps7_i2c_0"/>
-        <PERIPHERAL INSTANCE="ps7_afi_0"/>
-        <PERIPHERAL INSTANCE="ps7_afi_1"/>
-        <PERIPHERAL INSTANCE="ps7_afi_2"/>
-        <PERIPHERAL INSTANCE="ps7_afi_3"/>
-        <PERIPHERAL INSTANCE="ps7_i2c_1"/>
-        <PERIPHERAL INSTANCE="ps7_sd_0"/>
-        <PERIPHERAL INSTANCE="ps7_ethernet_0"/>
-        <PERIPHERAL INSTANCE="ps7_usb_0"/>
-        <PERIPHERAL INSTANCE="ps7_qspi_0"/>
-        <PERIPHERAL INSTANCE="ps7_qspi_linear_0"/>
-        <PERIPHERAL INSTANCE="ps7_ddr_0"/>
-        <PERIPHERAL INSTANCE="ps7_gpio_0"/>
-        <PERIPHERAL INSTANCE="ps7_ddrc_0"/>
-        <PERIPHERAL INSTANCE="ps7_dev_cfg_0"/>
-        <PERIPHERAL INSTANCE="ps7_xadc_0"/>
-        <PERIPHERAL INSTANCE="ps7_coresight_comp_0"/>
-        <PERIPHERAL INSTANCE="ps7_ocmc_0"/>
-        <PERIPHERAL INSTANCE="ps7_gpv_0"/>
-        <PERIPHERAL INSTANCE="ps7_scuc_0"/>
-        <PERIPHERAL INSTANCE="ps7_intc_dist_0"/>
-        <PERIPHERAL INSTANCE="ps7_globaltimer_0"/>
-        <PERIPHERAL INSTANCE="ps7_l2cachec_0"/>
-        <PERIPHERAL INSTANCE="ps7_dma_s"/>
-        <PERIPHERAL INSTANCE="ps7_iop_bus_config_0"/>
-        <PERIPHERAL INSTANCE="ps7_ram_0"/>
-        <PERIPHERAL INSTANCE="ps7_ram_1"/>
-        <PERIPHERAL INSTANCE="ps7_scugic_0"/>
-        <PERIPHERAL INSTANCE="ps7_scutimer_0"/>
-        <PERIPHERAL INSTANCE="ps7_scuwdt_0"/>
-        <PERIPHERAL INSTANCE="ps7_slcr_0"/>
-        <PERIPHERAL INSTANCE="ps7_dma_ns"/>
-        <PERIPHERAL INSTANCE="pwm_recorder_0"/>
-        <PERIPHERAL INSTANCE="pwm_recorder_1"/>
-        <PERIPHERAL INSTANCE="pwm_recorder_2"/>
-        <PERIPHERAL INSTANCE="pwm_recorder_3"/>
-        <PERIPHERAL INSTANCE="pwm_recorder_4"/>
-        <PERIPHERAL INSTANCE="pwm_recorder_5"/>
-        <PERIPHERAL INSTANCE="btns_4bits_tri_io"/>
-        <PERIPHERAL INSTANCE="pwm_signal_out_wkillswitch_0"/>
-        <PERIPHERAL INSTANCE="pwm_signal_out_wkillswitch_1"/>
-        <PERIPHERAL INSTANCE="pwm_signal_out_wkillswitch_2"/>
-        <PERIPHERAL INSTANCE="pwm_signal_out_wkillswitch_3"/>
-        <PERIPHERAL INSTANCE="axi_timer_0"/>
-      </PERIPHERALS>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_ddrc_0" IPTYPE="PERIPHERAL" MHS_INDEX="33" MODCLASS="PERIPHERAL" MODTYPE="ps7_ddrc">
-      <DESCRIPTION TYPE="SHORT">PS7 DDRC</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">DDRC interface</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8006000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8006FFF"/>
-        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="C_HAS_ECC" TYPE="STRING" VALUE="0"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="4160774144" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8006000" HIGHDECIMAL="4160778239" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8006FFF" IS_CACHEABLE="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_dev_cfg_0" IPTYPE="PERIPHERAL" MHS_INDEX="34" MODCLASS="PERIPHERAL" MODTYPE="ps7_dev_cfg">
-      <DESCRIPTION TYPE="SHORT">PS7 DEV CFG</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">DEV CFG interface</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8007000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF80070FF"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="4160778240" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8007000" HIGHDECIMAL="4160778495" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF80070FF" MEMTYPE="REGISTER" SIZE="256" SIZEABRV="256">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_xadc_0" IPTYPE="PERIPHERAL" MHS_INDEX="35" MODCLASS="PERIPHERAL" MODTYPE="ps7_xadc">
-      <DESCRIPTION TYPE="SHORT">PS7 XADC</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">XADC interface</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8007100"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8007120"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="4160778496" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8007100" HIGHDECIMAL="4160778528" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8007120" MEMTYPE="REGISTER" SIZE="33" SIZEABRV="U">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_coresight_comp_0" IPTYPE="PERIPHERAL" MHS_INDEX="36" MODCLASS="PERIPHERAL" MODTYPE="ps7_coresight_comp">
-      <DESCRIPTION TYPE="SHORT">PS7 coresight component</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">PS7 core sight component</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8800000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF88FFFFF"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="4169138176" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8800000" HIGHDECIMAL="4170186751" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF88FFFFF" MEMTYPE="REGISTER" SIZE="1048576" SIZEABRV="1M">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_ocmc_0" IPTYPE="PERIPHERAL" MHS_INDEX="37" MODCLASS="PERIPHERAL" MODTYPE="ps7_ocmc">
-      <DESCRIPTION TYPE="SHORT">PS7 OCMC</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">On-chip memory (OCM) interface</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF800C000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF800CFFF"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="4160798720" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF800C000" HIGHDECIMAL="4160802815" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF800CFFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_gpv_0" IPTYPE="PERIPHERAL" MHS_INDEX="38" MODCLASS="PERIPHERAL" MODTYPE="ps7_gpv">
-      <DESCRIPTION TYPE="SHORT">PS7 GPV</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">Top-level interconnect configuration and Global Programmers View (GPV) interface</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8900000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF89FFFFF"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="4170186752" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8900000" HIGHDECIMAL="4171235327" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF89FFFFF" MEMTYPE="REGISTER" SIZE="1048576" SIZEABRV="1M">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_scuc_0" IPTYPE="PERIPHERAL" MHS_INDEX="39" MODCLASS="PERIPHERAL" MODTYPE="ps7_scuc">
-      <DESCRIPTION TYPE="SHORT">PS7 SCU controler</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">SCU control and status</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8F00000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8F000FC"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="4176478208" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F00000" HIGHDECIMAL="4176478460" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F000FC" MEMTYPE="REGISTER" SIZE="253" SIZEABRV="U">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_intc_dist_0" IPTYPE="PERIPHERAL" MHS_INDEX="40" MODCLASS="PERIPHERAL" MODTYPE="ps7_intc_dist">
-      <DESCRIPTION TYPE="SHORT">PS7 intc</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">Interrupt controller distributor</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8F01000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8F01FFF"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="4176482304" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F01000" HIGHDECIMAL="4176486399" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F01FFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_globaltimer_0" IPTYPE="PERIPHERAL" MHS_INDEX="41" MODCLASS="PERIPHERAL" MODTYPE="ps7_globaltimer">
-      <DESCRIPTION TYPE="SHORT">PS7 global timer</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">Global timer</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8F00200"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8F002FF"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="4176478720" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F00200" HIGHDECIMAL="4176478975" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F002FF" MEMTYPE="REGISTER" SIZE="256" SIZEABRV="256">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_l2cachec_0" IPTYPE="PERIPHERAL" MHS_INDEX="42" MODCLASS="PERIPHERAL" MODTYPE="ps7_l2cachec">
-      <DESCRIPTION TYPE="SHORT">PS7 l2 chache</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">L2-cache controller</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8F02000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8F02FFF"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="4176486400" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F02000" HIGHDECIMAL="4176490495" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F02FFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_dma_s" IPTYPE="PERIPHERAL" MHS_INDEX="43" MODCLASS="PERIPHERAL" MODTYPE="ps7_dma">
-      <DESCRIPTION TYPE="SHORT">PS7 DMA Engine</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">AXI MemoryMap to/from AXI Stream Direct Memory Access Engine</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8003000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8003FFF"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_LITE_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="s_axi_lite_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="1" NAME="s_axi_lite_awvalid" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="2" NAME="s_axi_lite_awready" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="3" MSB="31" NAME="s_axi_lite_awaddr" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[32-1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="4" NAME="s_axi_lite_wvalid" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="5" NAME="s_axi_lite_wready" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="s_axi_lite_wdata" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[32-1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="7" MSB="1" NAME="s_axi_lite_bresp" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="8" NAME="s_axi_lite_bvalid" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="9" NAME="s_axi_lite_bready" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="10" NAME="s_axi_lite_arvalid" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="11" NAME="s_axi_lite_arready" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="s_axi_lite_araddr" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[32-1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="13" NAME="s_axi_lite_rvalid" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="14" NAME="s_axi_lite_rready" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="s_axi_lite_rdata" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[32-1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="s_axi_lite_rresp" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="RESET_OUT_N" DIR="O" MPD_INDEX="17" NAME="mm2s_prmry_reset_out_n" SIGNAME="RESET_OUT_N">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="RESET_OUT_N" DIR="O" MPD_INDEX="18" NAME="mm2s_cntrl_reset_out_n" SIGNAME="RESET_OUT_N">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="RESET_OUT_N" DIR="O" MPD_INDEX="19" NAME="s2mm_prmry_reset_out_n" SIGNAME="RESET_OUT_N">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="RESET_OUT_N" DIR="O" MPD_INDEX="20" NAME="s2mm_sts_reset_out_n" SIGNAME="RESET_OUT_N">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" MPD_INDEX="21" NAME="mm2s_introut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" MPD_INDEX="22" NAME="s2mm_introut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_LITE" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_aclk"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_awvalid"/>
-            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_awready"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_awaddr"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_wvalid"/>
-            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_wready"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_wdata"/>
-            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_bresp"/>
-            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_bvalid"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_bready"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_arvalid"/>
-            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_arready"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_araddr"/>
-            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_rvalid"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_rready"/>
-            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_rdata"/>
-            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_rresp"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="4160761856" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8003000" HIGHDECIMAL="4160765951" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8003FFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI_LITE"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_iop_bus_config_0" IPTYPE="PERIPHERAL" MHS_INDEX="44" MODCLASS="PERIPHERAL" MODTYPE="ps7_iop_bus_config">
-      <DESCRIPTION TYPE="SHORT">PS7 IOP BUS CONFIG</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">IOP BUS CONFIG interface</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE0200000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xE0200FFF"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="3760193536" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xE0200000" HIGHDECIMAL="3760197631" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xE0200FFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_ram_0" IPTYPE="PERIPHERAL" MHS_INDEX="45" MODCLASS="MEMORY_CNTLR" MODTYPE="ps7_ram">
-      <DESCRIPTION TYPE="SHORT">PS7 RAM</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">RAM interface</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x0002FFFF"/>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_S_AXI_HP0_HIGHOCM_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFC0000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_S_AXI_HP0_HIGHOCM_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFDFF"/>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_S_AXI_HP1_HIGHOCM_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFC0000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="5" NAME="C_S_AXI_HP1_HIGHOCM_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFDFF"/>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="6" NAME="C_S_AXI_HP2_HIGHOCM_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFC0000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="7" NAME="C_S_AXI_HP2_HIGHOCM_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFDFF"/>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_S_AXI_HP3_HIGHOCM_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFC0000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_S_AXI_HP3_HIGHOCM_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFDFF"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="1" NAME="S_AXI_HP0" TYPE="SLAVE"/>
-        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="2" NAME="S_AXI_HP1" TYPE="SLAVE"/>
-        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="3" NAME="S_AXI_HP2" TYPE="SLAVE"/>
-        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="4" NAME="S_AXI_HP3" TYPE="SLAVE"/>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="0" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="196607" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0x0002FFFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="196608" SIZEABRV="U">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4294705152" BASENAME="C_S_AXI_HP0_HIGHOCM_BASEADDR" BASEVALUE="0xFFFC0000" HIGHDECIMAL="4294966783" HIGHNAME="C_S_AXI_HP0_HIGHOCM_HIGHADDR" HIGHVALUE="0xFFFFFDFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="261632" SIZEABRV="U">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI_HP0"/>
-          </SLAVES>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4294705152" BASENAME="C_S_AXI_HP1_HIGHOCM_BASEADDR" BASEVALUE="0xFFFC0000" HIGHDECIMAL="4294966783" HIGHNAME="C_S_AXI_HP1_HIGHOCM_HIGHADDR" HIGHVALUE="0xFFFFFDFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="261632" SIZEABRV="U">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI_HP1"/>
-          </SLAVES>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4294705152" BASENAME="C_S_AXI_HP2_HIGHOCM_BASEADDR" BASEVALUE="0xFFFC0000" HIGHDECIMAL="4294966783" HIGHNAME="C_S_AXI_HP2_HIGHOCM_HIGHADDR" HIGHVALUE="0xFFFFFDFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="261632" SIZEABRV="U">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI_HP2"/>
-          </SLAVES>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4294705152" BASENAME="C_S_AXI_HP3_HIGHOCM_BASEADDR" BASEVALUE="0xFFFC0000" HIGHDECIMAL="4294966783" HIGHNAME="C_S_AXI_HP3_HIGHOCM_HIGHADDR" HIGHVALUE="0xFFFFFDFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="261632" SIZEABRV="U">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI_HP3"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_ram_1" IPTYPE="PERIPHERAL" MHS_INDEX="46" MODCLASS="MEMORY_CNTLR" MODTYPE="ps7_ram">
-      <DESCRIPTION TYPE="SHORT">PS7 RAM</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">RAM interface</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFF0000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFDFF"/>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_S_AXI_HP0_HIGHOCM_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFC0000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_S_AXI_HP0_HIGHOCM_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFDFF"/>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_S_AXI_HP1_HIGHOCM_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFC0000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="5" NAME="C_S_AXI_HP1_HIGHOCM_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFDFF"/>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="6" NAME="C_S_AXI_HP2_HIGHOCM_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFC0000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="7" NAME="C_S_AXI_HP2_HIGHOCM_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFDFF"/>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_S_AXI_HP3_HIGHOCM_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFC0000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_S_AXI_HP3_HIGHOCM_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFDFF"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="1" NAME="S_AXI_HP0" TYPE="SLAVE"/>
-        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="2" NAME="S_AXI_HP1" TYPE="SLAVE"/>
-        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="3" NAME="S_AXI_HP2" TYPE="SLAVE"/>
-        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" MPD_INDEX="4" NAME="S_AXI_HP3" TYPE="SLAVE"/>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="4294901760" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xFFFF0000" HIGHDECIMAL="4294966783" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xFFFFFDFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="65024" SIZEABRV="U">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4294705152" BASENAME="C_S_AXI_HP0_HIGHOCM_BASEADDR" BASEVALUE="0xFFFC0000" HIGHDECIMAL="4294966783" HIGHNAME="C_S_AXI_HP0_HIGHOCM_HIGHADDR" HIGHVALUE="0xFFFFFDFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="261632" SIZEABRV="U">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI_HP0"/>
-          </SLAVES>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4294705152" BASENAME="C_S_AXI_HP1_HIGHOCM_BASEADDR" BASEVALUE="0xFFFC0000" HIGHDECIMAL="4294966783" HIGHNAME="C_S_AXI_HP1_HIGHOCM_HIGHADDR" HIGHVALUE="0xFFFFFDFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="261632" SIZEABRV="U">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI_HP1"/>
-          </SLAVES>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4294705152" BASENAME="C_S_AXI_HP2_HIGHOCM_BASEADDR" BASEVALUE="0xFFFC0000" HIGHDECIMAL="4294966783" HIGHNAME="C_S_AXI_HP2_HIGHOCM_HIGHADDR" HIGHVALUE="0xFFFFFDFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="261632" SIZEABRV="U">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI_HP2"/>
-          </SLAVES>
-        </MEMRANGE>
-        <MEMRANGE BASEDECIMAL="4294705152" BASENAME="C_S_AXI_HP3_HIGHOCM_BASEADDR" BASEVALUE="0xFFFC0000" HIGHDECIMAL="4294966783" HIGHNAME="C_S_AXI_HP3_HIGHOCM_HIGHADDR" HIGHVALUE="0xFFFFFDFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="261632" SIZEABRV="U">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI_HP3"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_scugic_0" IPTYPE="PERIPHERAL" MHS_INDEX="47" MODCLASS="INTERRUPT_CNTLR" MODTYPE="ps7_scugic">
-      <DESCRIPTION TYPE="SHORT">PS7 SCUGIC0</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">SCUGIC0 interface</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8F00100"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8F001FF"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="15" LSB="0" MHS_INDEX="0" MPD_INDEX="19" MSB="15" NAME="IRQ_F2P" RIGHT="0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="ps7_IRQ_F2P" VECFORMULA="[15:0]">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="20" NAME="Core0_nFIQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="ps7_Core0_nFIQ">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="21" NAME="Core0_nIRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="ps7_Core0_nIRQ">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="22" NAME="Core1_nFIQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="ps7_Core1_nFIQ">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="23" NAME="Core1_nIRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="ps7_Core1_nIRQ">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="4176478464" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F00100" HIGHDECIMAL="4176478719" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F001FF" MEMTYPE="REGISTER" SIZE="256" SIZEABRV="256">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_scutimer_0" IPTYPE="PERIPHERAL" MHS_INDEX="48" MODCLASS="PERIPHERAL" MODTYPE="ps7_scutimer">
-      <DESCRIPTION TYPE="SHORT">PS7 SCU Timer/Counter</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">PS7 SCU Timer counter with AXI interface</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8F00600"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8F0061F"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_1.M_AXI_DP &amp; ps7_cortexa9_0.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="4176479744" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F00600" HIGHDECIMAL="4176479775" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F0061F" MEMTYPE="REGISTER" SIZE="32" SIZEABRV="32">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_scuwdt_0" IPTYPE="PERIPHERAL" MHS_INDEX="49" MODCLASS="PERIPHERAL" MODTYPE="ps7_scuwdt">
-      <DESCRIPTION TYPE="SHORT">PS7 SCU Watchdog Timer</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">PS7 SCU Watchdog Timer with AXI interface</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8F00620"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8F006FF"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="4176479776" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8F00620" HIGHDECIMAL="4176479999" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8F006FF" MEMTYPE="REGISTER" SIZE="224" SIZEABRV="U">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_slcr_0" IPTYPE="PERIPHERAL" MHS_INDEX="50" MODCLASS="PERIPHERAL" MODTYPE="ps7_slcr">
-      <DESCRIPTION TYPE="SHORT">PS7 SLCR</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">SLCR interface</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8000000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8000FFF"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="ps7_axi_interconnect_0_M_ARESETN">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARESET_OUT_N"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WSTRB" VECFORMULA="[((32/8)-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WSTRB"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[(32-1):0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
-            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
-            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="4160749568" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8000000" HIGHDECIMAL="4160753663" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8000FFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-    <MODULE HWVERSION="1.00.a" INSTANCE="ps7_dma_ns" IPTYPE="PERIPHERAL" MHS_INDEX="51" MODCLASS="PERIPHERAL" MODTYPE="ps7_dma">
-      <DESCRIPTION TYPE="SHORT">PS7 DMA Engine</DESCRIPTION>
-      <DESCRIPTION TYPE="LONG">AXI MemoryMap to/from AXI Stream Direct Memory Access Engine</DESCRIPTION>
-      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
-      <PARAMETERS>
-        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_S_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8004000"/>
-        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_S_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xF8004FFF"/>
-        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_LITE_MASTERS" VALUE="ps7_cortexa9_0.M_AXI_DP &amp; ps7_cortexa9_1.M_AXI_DP"/>
-      </PARAMETERS>
-      <PORTS>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="s_axi_lite_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWVALID" DIR="I" MPD_INDEX="1" NAME="s_axi_lite_awvalid" SIGNAME="ps7_axi_interconnect_0_M_AWVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWREADY" DIR="O" MPD_INDEX="2" NAME="s_axi_lite_awready" SIGNAME="ps7_axi_interconnect_0_M_AWREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="3" MSB="31" NAME="s_axi_lite_awaddr" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_AWADDR" VECFORMULA="[32-1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_AWADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_WVALID" DIR="I" MPD_INDEX="4" NAME="s_axi_lite_wvalid" SIGNAME="ps7_axi_interconnect_0_M_WVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_WREADY" DIR="O" MPD_INDEX="5" NAME="s_axi_lite_wready" SIGNAME="ps7_axi_interconnect_0_M_WREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="s_axi_lite_wdata" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_WDATA" VECFORMULA="[32-1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_WDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="7" MSB="1" NAME="s_axi_lite_bresp" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_BRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_BVALID" DIR="O" MPD_INDEX="8" NAME="s_axi_lite_bvalid" SIGNAME="ps7_axi_interconnect_0_M_BVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_BREADY" DIR="I" MPD_INDEX="9" NAME="s_axi_lite_bready" SIGNAME="ps7_axi_interconnect_0_M_BREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_BREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARVALID" DIR="I" MPD_INDEX="10" NAME="s_axi_lite_arvalid" SIGNAME="ps7_axi_interconnect_0_M_ARVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARREADY" DIR="O" MPD_INDEX="11" NAME="s_axi_lite_arready" SIGNAME="ps7_axi_interconnect_0_M_ARREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="s_axi_lite_araddr" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_ARADDR" VECFORMULA="[32-1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_ARADDR"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_RVALID" DIR="O" MPD_INDEX="13" NAME="s_axi_lite_rvalid" SIGNAME="ps7_axi_interconnect_0_M_RVALID">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RVALID"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_RREADY" DIR="I" MPD_INDEX="14" NAME="s_axi_lite_rready" SIGNAME="ps7_axi_interconnect_0_M_RREADY">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RREADY"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="s_axi_lite_rdata" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RDATA" VECFORMULA="[32-1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RDATA"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="ps7_axi_interconnect_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="s_axi_lite_rresp" RIGHT="0" SIGNAME="ps7_axi_interconnect_0_M_RRESP" VECFORMULA="[1:0]">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="ps7_axi_interconnect_0" PORT="M_AXI_RRESP"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DEF_SIGNAME="RESET_OUT_N" DIR="O" MPD_INDEX="17" NAME="mm2s_prmry_reset_out_n" SIGNAME="RESET_OUT_N">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="RESET_OUT_N" DIR="O" MPD_INDEX="18" NAME="mm2s_cntrl_reset_out_n" SIGNAME="RESET_OUT_N">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="RESET_OUT_N" DIR="O" MPD_INDEX="19" NAME="s2mm_prmry_reset_out_n" SIGNAME="RESET_OUT_N">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DEF_SIGNAME="RESET_OUT_N" DIR="O" MPD_INDEX="20" NAME="s2mm_sts_reset_out_n" SIGNAME="RESET_OUT_N">
-          <CONNECTIONS/>
-        </PORT>
-        <PORT DIR="O" MPD_INDEX="21" NAME="mm2s_introut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-        <PORT DIR="O" MPD_INDEX="22" NAME="s2mm_introut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
-      </PORTS>
-      <BUSINTERFACES>
-        <BUSINTERFACE BUSNAME="ps7_axi_interconnect_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_LITE" TYPE="SLAVE">
-          <PORTMAPS>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_aclk"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_awvalid"/>
-            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_awready"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_awaddr"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_wvalid"/>
-            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_wready"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_wdata"/>
-            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_bresp"/>
-            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_bvalid"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_bready"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_arvalid"/>
-            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_arready"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_araddr"/>
-            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_rvalid"/>
-            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_rready"/>
-            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_rdata"/>
-            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_rresp"/>
-          </PORTMAPS>
-          <MASTERS>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_0"/>
-            <MASTER BUSINTERFACE="M_AXI_DP" INSTANCE="ps7_cortexa9_1"/>
-          </MASTERS>
-        </BUSINTERFACE>
-      </BUSINTERFACES>
-      <MEMORYMAP>
-        <MEMRANGE BASEDECIMAL="4160765952" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xF8004000" HIGHDECIMAL="4160770047" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xF8004FFF" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K">
-          <SLAVES>
-            <SLAVE BUSINTERFACE="S_AXI_LITE"/>
-          </SLAVES>
-        </MEMRANGE>
-      </MEMORYMAP>
-    </MODULE>
-  </MODULES>
-
-</EDKSYSTEM>
\ No newline at end of file