Project Status (12/10/2017 - 19:00:59)
Project File: system.xmp Implementation State: Programming File Generated
Module Name: system
  • Errors:
 
Product Version:EDK 14.7
  • Warnings:
 
 
XPS Reports [-]
Report NameGenerated ErrorsWarningsInfos
Platgen Log FileSat Dec 9 17:33:28 201703 Warnings (3 new)16 Infos (16 new)
Simgen Log File    
BitInit Log File    
System Log FileSat Dec 9 18:08:44 2017   
 
XPS Synthesis Summary (estimated values) [-]
ReportGeneratedFlip Flops UsedLUTs UsedBRAMS UsedErrors
systemSat Dec 9 17:33:28 201727953056 0
system_axi_interconnect_1_wrapperSat Dec 9 17:33:28 2017272575 0
system_axi_timer_0_wrapperSat Dec 9 17:33:28 2017222322 0
system_btns_4bits_tri_io_wrapperSat Dec 9 17:33:28 20173842 0
system_clock_generator_0_wrapperSat Dec 9 17:33:28 2017   0
system_processing_system7_0_wrapperSat Dec 9 17:33:28 2017 89 0
system_pwm_recorder_0_wrapperSat Dec 9 17:33:28 2017179114 0
system_pwm_recorder_1_wrapperSat Dec 9 17:33:28 2017179114 0
system_pwm_recorder_2_wrapperSat Dec 9 17:33:28 2017179114 0
system_pwm_recorder_3_wrapperSat Dec 9 17:33:28 2017179114 0
system_pwm_recorder_4_wrapperSat Dec 9 17:33:28 2017179114 0
system_pwm_recorder_5_wrapperSat Dec 9 17:33:28 2017179114 0
system_pwm_signal_out_wkillswitch_0_wrapperSat Dec 9 17:33:28 2017280322 0
system_pwm_signal_out_wkillswitch_1_wrapperSat Dec 9 17:33:28 2017280322 0
system_pwm_signal_out_wkillswitch_2_wrapperSat Dec 9 17:33:28 2017280322 0
system_pwm_signal_out_wkillswitch_3_wrapperSat Dec 9 17:33:28 2017280322 0
system_reset_0_wrapperSat Dec 9 17:33:28 20176956 0
 
Device Utilization Summary (actual values) [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 2,592 35,200 7%  
    Number used as Flip Flops 2,336      
    Number used as Latches 256      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 2,463 17,600 13%  
    Number used as logic 2,352 17,600 13%  
        Number using O6 output only 1,360      
        Number using O5 output only 224      
        Number using O5 and O6 768      
        Number used as ROM 0      
    Number used as Memory 4 6,000 1%  
        Number used as Dual Port RAM 0      
        Number used as Single Port RAM 0      
        Number used as Shift Register 4      
            Number using O6 output only 4      
            Number using O5 output only 0      
            Number using O5 and O6 0      
    Number used exclusively as route-thrus 107      
        Number with same-slice register load 97      
        Number with same-slice carry load 5      
        Number with other load 5      
Number of occupied Slices 1,050 4,400 23%  
Number of LUT Flip Flop pairs used 3,371      
    Number with an unused Flip Flop 1,104 3,371 32%  
    Number with an unused LUT 908 3,371 26%  
    Number of fully used LUT-FF pairs 1,359 3,371 40%  
    Number of unique control sets 120      
    Number of slice register sites lost
        to control set restrictions
484 35,200 1%  
Number of bonded IOBs 16 100 16%  
    Number of LOCed IOBs 16 16 100%  
Number of bonded IOPAD 130 130 100%  
    IOB Flip Flops 6      
Number of RAMB36E1/FIFO36E1s 0 60 0%  
Number of RAMB18E1/FIFO18E1s 0 120 0%  
Number of BUFG/BUFGCTRLs 5 32 15%  
    Number used as BUFGs 5      
    Number used as BUFGCTRLs 0      
Number of IDELAYE2/IDELAYE2_FINEDELAYs 0 100 0%  
Number of ILOGICE2/ILOGICE3/ISERDESE2s 6 100 6%  
    Number used as ILOGICE2s 6      
Number used as    ILOGICE3s 0      
    Number used as ISERDESE2s 0      
Number of ODELAYE2/ODELAYE2_FINEDELAYs 0      
Number of OLOGICE2/OLOGICE3/OSERDESE2s 0 100 0%  
Number of PHASER_IN/PHASER_IN_PHYs 0 8 0%  
Number of PHASER_OUT/PHASER_OUT_PHYs 0 8 0%  
Number of BSCANs 0 4 0%  
Number of BUFHCEs 0 48 0%  
Number of BUFRs 0 8 0%  
Number of CAPTUREs 0 1 0%  
Number of DNA_PORTs 0 1 0%  
Number of DSP48E1s 0 80 0%  
Number of EFUSE_USRs 0 1 0%  
Number of FRAME_ECCs 0 1 0%  
Number of ICAPs 0 2 0%  
Number of IDELAYCTRLs 0 2 0%  
Number of IN_FIFOs 0 8 0%  
Number of MMCME2_ADVs 0 2 0%  
Number of OUT_FIFOs 0 8 0%  
Number of PHASER_REFs 0 2 0%  
Number of PHY_CONTROLs 0 2 0%  
Number of PLLE2_ADVs 0 2 0%  
Number of PS7s 1 1 100%  
Number of STARTUPs 0 1 0%  
Number of XADCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.45      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Translation ReportCurrentSat Dec 9 17:33:28 2017   
Map ReportCurrentSat Dec 9 17:33:28 2017   
Place and Route ReportCurrentSat Dec 9 17:33:28 2017   
Post-PAR Static Timing ReportCurrentSat Dec 9 17:33:28 2017   
Bitgen ReportCurrentSat Dec 9 17:33:28 2017   
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk Log FileOut of DateSun Dec 3 18:46:41 2017

Date Generated: 12/10/2017 - 19:00:59