This design is targeted for xc7z010 board (part number: xc7z010clg400-1)
Following peripherals are selected in the design.

Peripheral Selected

• Quad SPI Flash
• Enet 0
• USB 0
• SD 0
• UART 0
• UART 1
• I2C 0
• GPIO

To see detailed information please follow below links:

• MIO Configuration Table
• Zynq Peripheral Configuration
• DDR Configuration Information

MIO configuration Table

MIO Pin	Peripheral	Signal	IO type	Speed	Pullup	Direction
MIO 0	GPIO	gpio[0]	LVCMOS 3.3V	slow	disabled	inout
MIO 1	Quad SPI Flash	qspi0_ss_b	LVCMOS 3.3V	fast	disabled	out
MIO 2	Quad SPI Flash	qspi0_io[0]	LVCMOS 3.3V	fast	disabled	inout
MIO 3	Quad SPI Flash	qspi0_io[1]	LVCMOS 3.3V	fast	disabled	inout
MIO 4	Quad SPI Flash	qspi0_io[2]	LVCMOS 3.3V	fast	disabled	inout
MIO 5	Quad SPI Flash	qspi0_io[3]	LVCMOS 3.3V	fast	disabled	inout
MIO 6	Quad SPI Flash	qspi0_sclk	LVCMOS 3.3V	fast	disabled	out
MIO 7	GPIO	gpio[7]	LVCMOS 3.3V	slow	disabled	out
MIO 8	Quad SPI Flash	qspi_fbclk	LVCMOS 3.3V	fast	disabled	out
MIO 9	GPIO	gpio[9]	LVCMOS 3.3V	slow	disabled	inout
MIO 10	I2C 0	scl	LVCMOS 3.3V	slow	enabled	inout
MIO 11	I2C 0	sda	LVCMOS 3.3V	slow	enabled	inout
MIO 12	GPIO	gpio[12]	LVCMOS 3.3V	slow	disabled	inout
MIO 13	GPIO	gpio[13]	LVCMOS 3.3V	slow	disabled	inout
MIO 14	GPIO	gpio[14]	LVCMOS 3.3V	slow	disabled	inout
MIO 15	GPIO	gpio[15]	LVCMOS 3.3V	slow	disabled	inout
MIO 16	Enet 0	tx_clk	HSTL 1.8V	fast	disabled	out
MIO 17	Enet 0	txd[0]	HSTL 1.8V	fast	disabled	out
MIO 18	Enet 0	txd[1]	HSTL 1.8V	fast	disabled	out
MIO 19	Enet 0	txd[2]	HSTL 1.8V	fast	disabled	out
MIO 20	Enet 0	txd[3]	HSTL 1.8V	fast	disabled	out
MIO 21	Enet 0	tx_ctl	HSTL 1.8V	fast	disabled	out
MIO 22	Enet 0	rx_clk	HSTL 1.8V	fast	disabled	in
MIO 23	Enet 0	rxd[0]	HSTL 1.8V	fast	disabled	in
MIO 24	Enet 0	rxd[1]	HSTL 1.8V	fast	disabled	in
MIO 25	Enet 0	rxd[2]	HSTL 1.8V	fast	disabled	in
MIO 26	Enet 0	rxd[3]	HSTL 1.8V	fast	disabled	in
MIO 27	Enet 0	rx_ctl	HSTL 1.8V	fast	disabled	in
MIO 28	USB 0	data[4]	LVCMOS 1.8V	fast	disabled	inout
MIO 29	USB 0	dir	LVCMOS 1.8V	fast	disabled	in
MIO 30	USB 0	stp	LVCMOS 1.8V	fast	disabled	out
MIO 31	USB 0	nxt	LVCMOS 1.8V	fast	disabled	in
MIO 32	USB 0	data[0]	LVCMOS 1.8V	fast	disabled	inout
MIO 33	USB 0	data[1]	LVCMOS 1.8V	fast	disabled	inout
MIO 34	USB 0	data[2]	LVCMOS 1.8V	fast	disabled	inout
MIO 35	USB 0	data[3]	LVCMOS 1.8V	fast	disabled	inout
MIO 36	USB 0	clk	LVCMOS 1.8V	fast	disabled	in
MIO 37	USB 0	data[5]	LVCMOS 1.8V	fast	disabled	inout
MIO 38	USB 0	data[6]	LVCMOS 1.8V	fast	disabled	inout
MIO 39	USB 0	data[7]	LVCMOS 1.8V	fast	disabled	inout
MIO 40	SD 0	clk	LVCMOS 1.8V	fast	disabled	inout
MIO 41	SD 0	cmd	LVCMOS 1.8V	fast	disabled	inout
MIO 42	SD 0	data[0]	LVCMOS 1.8V	fast	disabled	inout
MIO 43	SD 0	data[1]	LVCMOS 1.8V	fast	disabled	inout
MIO 44	SD 0	data[2]	LVCMOS 1.8V	fast	disabled	inout
MIO 45	SD 0	data[3]	LVCMOS 1.8V	fast	disabled	inout
MIO 46	USB 0	reset	LVCMOS 1.8V	slow	disabled	inout
MIO 47	SD 0	cd	LVCMOS 1.8V	slow	disabled	in
MIO 48	UART 1	tx	LVCMOS 1.8V	slow	disabled	out
MIO 49	UART 1	rx	LVCMOS 1.8V	slow	disabled	in
MIO 50	GPIO	gpio[50]	LVCMOS 1.8V	slow	disabled	in
MIO 51	GPIO	gpio[51]	LVCMOS 1.8V	slow	disabled	in
MIO 52	Enet 0	mdc	LVCMOS 1.8V	slow	disabled	out
MIO 53	Enet 0	mdio	LVCMOS 1.8V	slow	disabled	inout

Zynq Peripheral Configuration

Peripheral	Signal Group	Signal	MIO
Quad SPI Flash			MIO 1 .. 6
	Dual Quad SPI (4 bit)		Disabled
	Dual Quad SPI (Parallel 8 bit)		Disabled
	Feedback Clk		MIO 8
SRAM/NOR Flash			Disabled
NAND Flash			Disabled
Enet 0			MIO 16 .. 27
		tx_clk	MIO 16
		txd[3]	MIO 20
		txd[2]	MIO 19
		txd[1]	MIO 18
		txd[0]	MIO 17
		tx_ctl	MIO 21
		rx_clk	MIO 22
		rxd[3]	MIO 26
		rxd[2]	MIO 25
		rxd[1]	MIO 24
		rxd[0]	MIO 23
		rx_ctl	MIO 27
	MDIO		MIO 52 .. 53
		mdc	MIO 52
		mdio	MIO 53
Enet 1			Disabled
USB 0			MIO 28 .. 39
		clk	MIO 36
		dir	MIO 29
		stp	MIO 30
		nxt	MIO 31
		data[0]	MIO 32
		data[1]	MIO 33
		data[2]	MIO 34
		data[3]	MIO 35
		data[4]	MIO 28
		data[5]	MIO 37
		data[6]	MIO 38
		data[7]	MIO 39
USB 1			Disabled
SD 0			MIO 40 .. 45
	CD		MIO 47
	WP		EMIO
	Power		Disabled
SD 1			Disabled
UART 0			EMIO
		rx	EMIO
		tx	EMIO
	Modem signals		Disabled
UART 1			MIO 48 .. 49
		rx	MIO 49
		tx	MIO 48
	Modem Signals		Disabled
I2C 0			MIO 10 .. 11
		scl	MIO 10
		sda	MIO 11
	Interrupt		Disabled
I2C 1			Disabled
SPI 0			Disabled
SPI 1			Disabled
CAN 0			Disabled
CAN 1			Disabled
Trace			Disabled
Timer 0			Disabled
Timer 1			Disabled
Watchdog			Disabled
PJTAG			Disabled
GPIO			MIO
Mode			Disabled
VCfg			Disabled

DDR Memory information

DDR Controller Configuration

Parameter	Value
Enable DDR	1
Memory Type	DDR 3
Memory Part	MT41K128M16 JT-125
DRAM bus width	32 Bit
ECC	Disabled
BURST Length (lppdr only)	8
Internal Vref	0
Operating Frequency (MHz)	525.000000
HIGH temperature	Normal (0-85)

Memory Part Configuration

Parameter	Value
DRAM IC bus width	16 Bits
DRAM Device Capacity	2048 MBits
Speed Bin	DDR3_1066F
BANK Address Count	3
ROW Address Count	14
COLUMN Address Count	10
CAS Latency	7
CAS Write Latency	6
RAS to CAS Delay	7
RECHARGE Time	7
tRC (ns )	48.75
tRASmin ( ns )	35.0
tFAW	40.0
ADDITIVE Latency	0

Training/Board Details

Parameter	Value
Write levelling	1
Read gate	1
Read data eye	1
DQS to Clock delay [0] (ns)	-0.073
DQS to Clock delay [1] (ns)	-0.034
DQS to Clock delay [2] (ns)	-0.03
DQS to Clock delay [3] (ns)	-0.082
Board delay [0] (ns)	0.176
Board delay [1] (ns)	0.159
Board delay [2] (ns)	0.162
Board delay [3] (ns)	0.187