pwm_signal_out_wkillswitch Project Status (04/17/2015 - 16:39:17) | |||
Project File: | pwm_signal_out_wkillswitch.xise | Parser Errors: | No Errors |
Module Name: | pwm_signal_out_wkillswitch | Implementation State: | Synthesized |
Target Device: | xc7z010-1clg400 |
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No Errors |
Product Version: | ISE 14.7 |
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No Warnings |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slice Registers | 120 | 35200 | 0% | |
Number of Slice LUTs | 174 | 17600 | 0% | |
Number of fully used LUT-FF pairs | 56 | 238 | 23% | |
Number of bonded IOBs | 99 | 100 | 99% | |
Number of BUFG/BUFGCTRLs | 2 | 32 | 6% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Fri Apr 17 17:12:57 2015 | 0 | 0 | 0 | |
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated |