Xilinx Platform Studio (XPS)
Xilinx EDK 14.7 Build EDK_P.20131013
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Assigned Driver generic 1.00.a for instance processing_system7_0
processing_system7_0 has been added to the project
INFO:EDK:3901 - please connect bus interface, set up port and generate address manually
Writing filter settings....
Done writing filter settings to:
/local/ucart/microcart_may16/tasks/Quad/system/etc/system.filters
Done writing Tab View settings to:
/local/ucart/microcart_may16/tasks/Quad/system/etc/system.gui
Writing filter settings....
Done writing filter settings to:
/local/ucart/microcart_may16/tasks/Quad/system/etc/system.filters
Done writing Tab View settings to:
/local/ucart/microcart_may16/tasks/Quad/system/etc/system.gui
Assigned Driver generic 1.00.a for instance pwm_recorder_0
pwm_recorder_0 has been added to the project
WARNING:EDK:2137 - Peripheral pwm_recorder_0 is not accessible from any processor in the system. Check Bus Interface connections and address parameters.
Assigned Driver generic 1.00.a for instance axi_interconnect_1
Address Map for Processor processing_system7_0
Address Map for Processor processing_system7_0
(0x76e00000-0x76e0ffff) pwm_recorder_0 axi_interconnect_1
INFO:EDK - Do connection by refering to bus interface of a processing_system7_0 in design
INFO:EDK - Create new axi_interconnect IP instance axi_interconnect_1
INFO:EDK - Connect clock port M_AXI_GP0_ACLK to processing_system7_0_FCLK_CLK0
INFO:EDK - Connect bus interface S_AXI to axi_interconnect_1
INFO:EDK - Connect clock port S_AXI_ACLK to processing_system7_0_FCLK_CLK0
INFO:EDK - Successfully did connection by refering to M_AXI_GP0 bus interface in processing_system7_0
INFO:EDK - External IO port grouping doneINFO:EDK - Generate address successfully
INFO:EDK - Successfully finished auto bus connection for IP instance: pwm_recorder_0
Assigned Driver generic 1.00.a for instance pwm_signal_out_wkillswitch_0
pwm_signal_out_wkillswitch_0 has been added to the project
WARNING:EDK:2137 - Peripheral pwm_signal_out_wkillswitch_0 is not accessible from any processor in the system. Check Bus Interface connections and address parameters.
Address Map for Processor processing_system7_0
(0x76e00000-0x76e0ffff) pwm_recorder_0 axi_interconnect_1
(0x79400000-0x7940ffff) pwm_signal_out_wkillswitch_0 axi_interconnect_1
INFO:EDK - Do connection by refering to bus interface of a processing_system7_0 in design
INFO:EDK - Connect bus interface S_AXI to axi_interconnect_1
INFO:EDK - Connect clock port S_AXI_ACLK to processing_system7_0_FCLK_CLK0
INFO:EDK - Successfully did connection by refering to M_AXI_GP0 bus interface in processing_system7_0
INFO:EDK - External IO port grouping doneINFO:EDK - Generate address successfully
INFO:EDK - Successfully finished auto bus connection for IP instance: pwm_signal_out_wkillswitch_0
Assigned Driver generic 1.00.a for instance pwm_recorder_1
pwm_recorder_1 has been added to the project
WARNING:EDK:2137 - Peripheral pwm_recorder_1 is not accessible from any processor in the system. Check Bus Interface connections and address parameters.
Address Map for Processor processing_system7_0
(0x76e00000-0x76e0ffff) pwm_recorder_0 axi_interconnect_1
(0x76e20000-0x76e2ffff) pwm_recorder_1 axi_interconnect_1
(0x79400000-0x7940ffff) pwm_signal_out_wkillswitch_0 axi_interconnect_1
INFO:EDK - Do connection by refering to bus interface of a processing_system7_0 in design
INFO:EDK - Connect bus interface S_AXI to axi_interconnect_1
INFO:EDK - Connect clock port S_AXI_ACLK to processing_system7_0_FCLK_CLK0
INFO:EDK - Successfully did connection by refering to M_AXI_GP0 bus interface in processing_system7_0
INFO:EDK - External IO port grouping doneINFO:EDK - Generate address successfully
INFO:EDK - Successfully finished auto bus connection for IP instance: pwm_recorder_1
Assigned Driver generic 1.00.a for instance pwm_recorder_2
pwm_recorder_2 has been added to the project
WARNING:EDK:2137 - Peripheral pwm_recorder_2 is not accessible from any processor in the system. Check Bus Interface connections and address parameters.
Address Map for Processor processing_system7_0
(0x76e00000-0x76e0ffff) pwm_recorder_0 axi_interconnect_1
(0x76e20000-0x76e2ffff) pwm_recorder_1 axi_interconnect_1
(0x76e40000-0x76e4ffff) pwm_recorder_2 axi_interconnect_1
(0x79400000-0x7940ffff) pwm_signal_out_wkillswitch_0 axi_interconnect_1
INFO:EDK - Do connection by refering to bus interface of a processing_system7_0 in design
INFO:EDK - Connect bus interface S_AXI to axi_interconnect_1
INFO:EDK - Connect clock port S_AXI_ACLK to processing_system7_0_FCLK_CLK0
INFO:EDK - Successfully did connection by refering to M_AXI_GP0 bus interface in processing_system7_0
INFO:EDK - External IO port grouping doneINFO:EDK - Generate address successfully
INFO:EDK - Successfully finished auto bus connection for IP instance: pwm_recorder_2
Assigned Driver generic 1.00.a for instance pwm_recorder_3
pwm_recorder_3 has been added to the project
WARNING:EDK:2137 - Peripheral pwm_recorder_3 is not accessible from any processor in the system. Check Bus Interface connections and address parameters.
Address Map for Processor processing_system7_0
(0x76e00000-0x76e0ffff) pwm_recorder_0 axi_interconnect_1
(0x76e20000-0x76e2ffff) pwm_recorder_1 axi_interconnect_1
(0x76e40000-0x76e4ffff) pwm_recorder_2 axi_interconnect_1
(0x76e60000-0x76e6ffff) pwm_recorder_3 axi_interconnect_1
(0x79400000-0x7940ffff) pwm_signal_out_wkillswitch_0 axi_interconnect_1
INFO:EDK - Do connection by refering to bus interface of a processing_system7_0 in design
INFO:EDK - Connect bus interface S_AXI to axi_interconnect_1
INFO:EDK - Connect clock port S_AXI_ACLK to processing_system7_0_FCLK_CLK0
INFO:EDK - Successfully did connection by refering to M_AXI_GP0 bus interface in processing_system7_0
INFO:EDK - External IO port grouping doneINFO:EDK - Generate address successfully
INFO:EDK - Successfully finished auto bus connection for IP instance: pwm_recorder_3
Assigned Driver generic 1.00.a for instance pwm_recorder_4
pwm_recorder_4 has been added to the project
WARNING:EDK:2137 - Peripheral pwm_recorder_4 is not accessible from any processor in the system. Check Bus Interface connections and address parameters.
Address Map for Processor processing_system7_0
(0x76e00000-0x76e0ffff) pwm_recorder_0 axi_interconnect_1
(0x76e20000-0x76e2ffff) pwm_recorder_1 axi_interconnect_1
(0x76e40000-0x76e4ffff) pwm_recorder_2 axi_interconnect_1
(0x76e60000-0x76e6ffff) pwm_recorder_3 axi_interconnect_1
(0x76e80000-0x76e8ffff) pwm_recorder_4 axi_interconnect_1
(0x79400000-0x7940ffff) pwm_signal_out_wkillswitch_0 axi_interconnect_1
INFO:EDK - Do connection by refering to bus interface of a processing_system7_0 in design
INFO:EDK - Connect bus interface S_AXI to axi_interconnect_1
INFO:EDK - Connect clock port S_AXI_ACLK to processing_system7_0_FCLK_CLK0
INFO:EDK - Successfully did connection by refering to M_AXI_GP0 bus interface in processing_system7_0
INFO:EDK - External IO port grouping doneINFO:EDK - Generate address successfully
INFO:EDK - Successfully finished auto bus connection for IP instance: pwm_recorder_4
Assigned Driver generic 1.00.a for instance pwm_recorder_5
pwm_recorder_5 has been added to the project
WARNING:EDK:2137 - Peripheral pwm_recorder_5 is not accessible from any processor in the system. Check Bus Interface connections and address parameters.
Address Map for Processor processing_system7_0
(0x76e00000-0x76e0ffff) pwm_recorder_0 axi_interconnect_1
(0x76e20000-0x76e2ffff) pwm_recorder_1 axi_interconnect_1
(0x76e40000-0x76e4ffff) pwm_recorder_2 axi_interconnect_1
(0x76e60000-0x76e6ffff) pwm_recorder_3 axi_interconnect_1
(0x76e80000-0x76e8ffff) pwm_recorder_4 axi_interconnect_1
(0x76ea0000-0x76eaffff) pwm_recorder_5 axi_interconnect_1
(0x79400000-0x7940ffff) pwm_signal_out_wkillswitch_0 axi_interconnect_1
INFO:EDK - Do connection by refering to bus interface of a processing_system7_0 in design
INFO:EDK - Connect bus interface S_AXI to axi_interconnect_1
INFO:EDK - Connect clock port S_AXI_ACLK to processing_system7_0_FCLK_CLK0
INFO:EDK - Successfully did connection by refering to M_AXI_GP0 bus interface in processing_system7_0
INFO:EDK - External IO port grouping doneINFO:EDK - Generate address successfully
INFO:EDK - Successfully finished auto bus connection for IP instance: pwm_recorder_5
Assigned Driver generic 1.00.a for instance pwm_signal_out_wkillswitch_1
pwm_signal_out_wkillswitch_1 has been added to the project
WARNING:EDK:2137 - Peripheral pwm_signal_out_wkillswitch_1 is not accessible from any processor in the system. Check Bus Interface connections and address parameters.
Address Map for Processor processing_system7_0
(0x76e00000-0x76e0ffff) pwm_recorder_0 axi_interconnect_1
(0x76e20000-0x76e2ffff) pwm_recorder_1 axi_interconnect_1
(0x76e40000-0x76e4ffff) pwm_recorder_2 axi_interconnect_1
(0x76e60000-0x76e6ffff) pwm_recorder_3 axi_interconnect_1
(0x76e80000-0x76e8ffff) pwm_recorder_4 axi_interconnect_1
(0x76ea0000-0x76eaffff) pwm_recorder_5 axi_interconnect_1
(0x79400000-0x7940ffff) pwm_signal_out_wkillswitch_0 axi_interconnect_1
(0x79420000-0x7942ffff) pwm_signal_out_wkillswitch_1 axi_interconnect_1
INFO:EDK - Do connection by refering to bus interface of a processing_system7_0 in design
INFO:EDK - Connect bus interface S_AXI to axi_interconnect_1
INFO:EDK - Connect clock port S_AXI_ACLK to processing_system7_0_FCLK_CLK0
INFO:EDK - Successfully did connection by refering to M_AXI_GP0 bus interface in processing_system7_0
INFO:EDK - External IO port grouping doneINFO:EDK - Generate address successfully
INFO:EDK - Successfully finished auto bus connection for IP instance: pwm_signal_out_wkillswitch_1
Assigned Driver generic 1.00.a for instance pwm_signal_out_wkillswitch_2
pwm_signal_out_wkillswitch_2 has been added to the project
WARNING:EDK:2137 - Peripheral pwm_signal_out_wkillswitch_2 is not accessible from any processor in the system. Check Bus Interface connections and address parameters.
Address Map for Processor processing_system7_0
(0x76e00000-0x76e0ffff) pwm_recorder_0 axi_interconnect_1
(0x76e20000-0x76e2ffff) pwm_recorder_1 axi_interconnect_1
(0x76e40000-0x76e4ffff) pwm_recorder_2 axi_interconnect_1
(0x76e60000-0x76e6ffff) pwm_recorder_3 axi_interconnect_1
(0x76e80000-0x76e8ffff) pwm_recorder_4 axi_interconnect_1
(0x76ea0000-0x76eaffff) pwm_recorder_5 axi_interconnect_1
(0x79400000-0x7940ffff) pwm_signal_out_wkillswitch_0 axi_interconnect_1
(0x79420000-0x7942ffff) pwm_signal_out_wkillswitch_1 axi_interconnect_1
(0x79440000-0x7944ffff) pwm_signal_out_wkillswitch_2 axi_interconnect_1
INFO:EDK - Do connection by refering to bus interface of a processing_system7_0 in design
INFO:EDK - Connect bus interface S_AXI to axi_interconnect_1
INFO:EDK - Connect clock port S_AXI_ACLK to processing_system7_0_FCLK_CLK0
INFO:EDK - Successfully did connection by refering to M_AXI_GP0 bus interface in processing_system7_0
INFO:EDK - External IO port grouping doneINFO:EDK - Generate address successfully
INFO:EDK - Successfully finished auto bus connection for IP instance: pwm_signal_out_wkillswitch_2
Assigned Driver generic 1.00.a for instance pwm_signal_out_wkillswitch_3
pwm_signal_out_wkillswitch_3 has been added to the project
WARNING:EDK:2137 - Peripheral pwm_signal_out_wkillswitch_3 is not accessible from any processor in the system. Check Bus Interface connections and address parameters.
Address Map for Processor processing_system7_0
(0x76e00000-0x76e0ffff) pwm_recorder_0 axi_interconnect_1
(0x76e20000-0x76e2ffff) pwm_recorder_1 axi_interconnect_1
(0x76e40000-0x76e4ffff) pwm_recorder_2 axi_interconnect_1
(0x76e60000-0x76e6ffff) pwm_recorder_3 axi_interconnect_1
(0x76e80000-0x76e8ffff) pwm_recorder_4 axi_interconnect_1
(0x76ea0000-0x76eaffff) pwm_recorder_5 axi_interconnect_1
(0x79400000-0x7940ffff) pwm_signal_out_wkillswitch_0 axi_interconnect_1
(0x79420000-0x7942ffff) pwm_signal_out_wkillswitch_1 axi_interconnect_1
(0x79440000-0x7944ffff) pwm_signal_out_wkillswitch_2 axi_interconnect_1
(0x79460000-0x7946ffff) pwm_signal_out_wkillswitch_3 axi_interconnect_1
INFO:EDK - Do connection by refering to bus interface of a processing_system7_0 in design
INFO:EDK - Connect bus interface S_AXI to axi_interconnect_1
INFO:EDK - Connect clock port S_AXI_ACLK to processing_system7_0_FCLK_CLK0
INFO:EDK - Successfully did connection by refering to M_AXI_GP0 bus interface in processing_system7_0
INFO:EDK - External IO port grouping doneINFO:EDK - Generate address successfully
INFO:EDK - Successfully finished auto bus connection for IP instance: pwm_signal_out_wkillswitch_3
Overriding Xilinx file <TextEditor.cfg> with local file </opt/Xilinx/14.7/ISE_DS/EDK/data/TextEditor.cfg>
Writing filter settings....
Done writing filter settings to:
/local/ucart/microcart_may16/tasks/Quad/system/etc/system.filters
Done writing Tab View settings to:
/local/ucart/microcart_may16/tasks/Quad/system/etc/system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.7 Build EDK_P.20131013
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Overriding Xilinx file <TextEditor.cfg> with local file </opt/Xilinx/14.7/ISE_DS/EDK/data/TextEditor.cfg>
The project's MHS file has changed on disk.
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 30
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 30
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 30
The project's MHS file has changed on disk.
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 31
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 31
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 31
Make instance pwm_signal_out_wkillswitch_0 port pwm_out_sm external with net as port name
Instance pwm_signal_out_wkillswitch_0 port pwm_out_sm connector undefined, using pwm_signal_out_wkillswitch_0_pwm_out_sm
Make instance pwm_signal_out_wkillswitch_1 port pwm_out_sm external with net as port name
Instance pwm_signal_out_wkillswitch_1 port pwm_out_sm connector undefined, using pwm_signal_out_wkillswitch_1_pwm_out_sm
Make instance pwm_signal_out_wkillswitch_2 port pwm_out_sm external with net as port name
Instance pwm_signal_out_wkillswitch_2 port pwm_out_sm connector undefined, using pwm_signal_out_wkillswitch_2_pwm_out_sm
Make instance pwm_signal_out_wkillswitch_3 port pwm_out_sm external with net as port name
Instance pwm_signal_out_wkillswitch_3 port pwm_out_sm connector undefined, using pwm_signal_out_wkillswitch_3_pwm_out_sm
The project's MHS file has changed on disk.
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
The project's MHS file has changed on disk.
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
The project's MHS file has changed on disk.
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
Assigned Driver gpio 3.01.a for instance axi_gpio_0
axi_gpio_0 has been added to the project
ERROR:EDK:4125 - IPNAME: axi_gpio, INSTANCE: axi_gpio_0, PARAMETER: C_BASEADDR - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a value in the MHS.
ERROR:EDK:4125 - IPNAME: axi_gpio, INSTANCE: axi_gpio_0, PARAMETER: C_HIGHADDR - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a value in the MHS.
WARNING:EDK:2137 - Peripheral axi_gpio_0 is not accessible from any processor in the system. Check Bus Interface connections and address parameters.
Address Map for Processor processing_system7_0
(0x41200000-0x4120ffff) BTNs_4Bits_TRI_IO axi_interconnect_1
(0x76e00000-0x76e0ffff) pwm_recorder_0 axi_interconnect_1
(0x76e20000-0x76e2ffff) pwm_recorder_1 axi_interconnect_1
(0x76e40000-0x76e4ffff) pwm_recorder_2 axi_interconnect_1
(0x76e60000-0x76e6ffff) pwm_recorder_3 axi_interconnect_1
(0x76e80000-0x76e8ffff) pwm_recorder_4 axi_interconnect_1
(0x76ea0000-0x76eaffff) pwm_recorder_5 axi_interconnect_1
(0x79400000-0x7940ffff) pwm_signal_out_wkillswitch_0 axi_interconnect_1
(0x79420000-0x7942ffff) pwm_signal_out_wkillswitch_1 axi_interconnect_1
(0x79440000-0x7944ffff) pwm_signal_out_wkillswitch_2 axi_interconnect_1
(0x79460000-0x7946ffff) pwm_signal_out_wkillswitch_3 axi_interconnect_1
INFO:EDK - Do connection by refering to bus interface of a processing_system7_0 in design
INFO:EDK - Connect bus interface S_AXI to axi_interconnect_1
INFO:EDK - Connect clock port S_AXI_ACLK to processing_system7_0_FCLK_CLK0
INFO:EDK - Successfully did connection by refering to M_AXI_GP0 bus interface in processing_system7_0
INFO:EDK - External IO port grouping doneINFO:EDK - Generate address successfully
INFO:EDK - Successfully finished auto bus connection for IP instance: BTNs_4Bits_TRI_IO
The project's MHS file has changed on disk.
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
The project's MHS file has changed on disk.
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 42
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 42
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 42
Make instance BTNs_4Bits_TRI_IO port GPIO_IO_I external with net as port name
Instance BTNs_4Bits_TRI_IO port GPIO_IO_I connector undefined, using BTNs_4Bits_TRI_IO_GPIO_IO_I
The project's MHS file has changed on disk.
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
The project's MHS file has changed on disk.
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
The project's MHS file has changed on disk.
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
The project's MHS file has changed on disk.
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
The project's MHS file has changed on disk.
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
Running DRCs...
Overriding IP level properties ...
Computing clock values...
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Address Map for Processor processing_system7_0
(0x41200000-0x4120ffff) BTNs_4Bits_TRI_IO axi_interconnect_1
(0x76e00000-0x76e0ffff) pwm_recorder_0 axi_interconnect_1
(0x76e20000-0x76e2ffff) pwm_recorder_1 axi_interconnect_1
(0x76e40000-0x76e4ffff) pwm_recorder_2 axi_interconnect_1
(0x76e60000-0x76e6ffff) pwm_recorder_3 axi_interconnect_1
(0x76e80000-0x76e8ffff) pwm_recorder_4 axi_interconnect_1
(0x76ea0000-0x76eaffff) pwm_recorder_5 axi_interconnect_1
(0x79400000-0x7940ffff) pwm_signal_out_wkillswitch_0 axi_interconnect_1
(0x79420000-0x7942ffff) pwm_signal_out_wkillswitch_1 axi_interconnect_1
(0x79440000-0x7944ffff) pwm_signal_out_wkillswitch_2 axi_interconnect_1
(0x79460000-0x7946ffff) pwm_signal_out_wkillswitch_3 axi_interconnect_1
Checking platform address map ...
Checking platform configuration ...
IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - 1 master(s) : 11 slave(s)
Checking port drivers...
Performing Clock DRCs...
Performing Reset DRCs...
Overriding system level properties...
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_FCLK_CLK1_BUF value to FALSE - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 351
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_FCLK_CLK2_BUF value to FALSE - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 352
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_FCLK_CLK3_BUF value to FALSE - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 353
INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi_interconnect_1.
INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is overriding PARAMETER C_RANGE_CHECK value to 1 - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/data/axi_interconnect_v2_1_0.mpd line 149
Running system level update procedures...
Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
Running system level DRCs...
Performing System level DRCs on properties...
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
ERROR:EDK:3900 - issued from TCL procedure "zynqconfig_do" line 34
processing_system7_0 (processing_system7) - MHS file editing for Zynq related parameters is not allowed. Please use Zynq tab in XPS for PS configuration.
Value of parameter C_EN_EMIO_I2C0 (0) in MHS conflicts with the setting in Zynq tab. Value of C_EN_EMIO_I2C0 should be 1
Running DRCs...
Overriding IP level properties ...
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_PACKAGE_NAME value to clg400 - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 185
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_S_AXI_HP0_HIGHADDR value to 0x1FFFFFFF - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 300
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_S_AXI_HP1_HIGHADDR value to 0x1FFFFFFF - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 304
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_S_AXI_HP2_HIGHADDR value to 0x1FFFFFFF - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 308
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_S_AXI_HP3_HIGHADDR value to 0x1FFFFFFF - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 312
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_NUM_F2P_INTR_INPUTS value to 1 - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 319
INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is overriding PARAMETER C_BASEFAMILY value to zynq - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/data/axi_interconnect_v2_1_0.mpd line 81
Computing clock values...
INFO:EDK:1432 - Frequency for Top-Level Input Clock 'processing_system7_0_PS_CLK_pin' is not specified. Clock DRCs will not be performed for IPs connected to that clock port, unless they are connected through the clock generator IP.
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
INFO:EDK - INFO: DDR Base and High address in current configuration is 0x00000000 and 0x1FFFFFFF respectively.
INFO:EDK - INFO: You can modify the DDR address range accessed by Programmable Logic through the processing_system7 AXI slave interfaces. If MicroBlaze is a master on processing_system7 AXI slave interfaces, please use the top half of the address range (Base Address = 0x10000000; High Address = 0x1FFFFFFF). For all other master, any subset of the DDR address can be used. See Xilinx Answer 47167 for more information.
Address Map for Processor processing_system7_0
(0x41200000-0x4120ffff) BTNs_4Bits_TRI_IO axi_interconnect_1
(0x76e00000-0x76e0ffff) pwm_recorder_0 axi_interconnect_1
(0x76e20000-0x76e2ffff) pwm_recorder_1 axi_interconnect_1
(0x76e40000-0x76e4ffff) pwm_recorder_2 axi_interconnect_1
(0x76e60000-0x76e6ffff) pwm_recorder_3 axi_interconnect_1
(0x76e80000-0x76e8ffff) pwm_recorder_4 axi_interconnect_1
(0x76ea0000-0x76eaffff) pwm_recorder_5 axi_interconnect_1
(0x79400000-0x7940ffff) pwm_signal_out_wkillswitch_0 axi_interconnect_1
(0x79420000-0x7942ffff) pwm_signal_out_wkillswitch_1 axi_interconnect_1
(0x79440000-0x7944ffff) pwm_signal_out_wkillswitch_2 axi_interconnect_1
(0x79460000-0x7946ffff) pwm_signal_out_wkillswitch_3 axi_interconnect_1
Checking platform address map ...
Checking platform configuration ...
IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - 1 master(s) : 11 slave(s)
Checking port drivers...
Performing Clock DRCs...
Performing Reset DRCs...
Overriding system level properties...
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_FCLK_CLK1_BUF value to FALSE - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 351
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_FCLK_CLK2_BUF value to FALSE - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 352
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_FCLK_CLK3_BUF value to FALSE - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 353
INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi_interconnect_1.
INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is overriding PARAMETER C_RANGE_CHECK value to 1 - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/data/axi_interconnect_v2_1_0.mpd line 149
Running system level update procedures...
Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
Running system level DRCs...
Performing System level DRCs on properties...
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
Done!
********************************************************************************
At Local date and time: Wed Oct 14 19:55:51 2015
make -f system.make exporttosdk started...
pscgen -mhs system.mhs -expdir SDK/SDK_Export/hw
Generating ps7_init code for Si version 1....
Generating ps7_init code for Si version 2....
Generating ps7_init code for Si version 3....
psf2Edward -inp system.xmp -flat_zynq -dont_run_checkhwsys -dont_add_loginfo -make_inst_lower -edwver 1.2 -xml SDK/SDK_Export/hw/system.xml
Release 14.7 - psf2Edward EDK_P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
/local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
/local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
/local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
/local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
WARNING:EDK -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_i2c_v1_0
0_a/data/ps7_i2c_v2_1_0.mpd line 108 Unknown PORT subproperty IIC Serial Data
WARNING:EDK -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_i2c_v1_0
0_a/data/ps7_i2c_v2_1_0.mpd line 109 Unknown PORT subproperty IIC Serial
Clock
WARNING:EDK:2486 - The bitwidth 52 of new value 0xc00000000f281 is greater than
32
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_BASE_ID -
Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 19
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_IS_ACLK_ASYNC - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 20
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_ACLK_RATIO
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 21
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_ARB_PRIORITY - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 22
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AW_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 23
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AR_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 24
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_W_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 25
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_R_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 26
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_B_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 27
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_WRITE_FIFO_DEPTH - Failure in evaluting ISVALID
expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 28
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_READ_FIFO_DEPTH - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 29
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_WRITE_ISSUING - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 30
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_READ_ISSUING - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 31
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ACLK - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 119
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARESETN - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 120
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 121
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWADDR - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 122
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLEN - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 123
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWSIZE - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 124
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWBURST - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 125
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWCACHE - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 126
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWPROT - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 127
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLOCK - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 128
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 129
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 130
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WDATA - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 131
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WSTRB - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 132
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WLAST - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 133
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 134
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 135
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BID - Failure in evaluting
ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 136
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BRESP - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 137
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 138
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 139
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 140
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARADDR - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 141
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLEN - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 142
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARSIZE - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 143
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARBURST - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 144
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARCACHE - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 145
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARPROT - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 146
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLOCK - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 147
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 148
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 149
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RID - Failure in evaluting
ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 150
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RDATA - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 151
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RRESP - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 152
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RLAST - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 153
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 154
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 155
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI - Failure in evaluting
ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 73
WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_I - Failure in evaluting
ISVALID expresion "(C_USE_STARTUP==0)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_qspi_v1_
00_a/data/ps7_qspi_v2_1_0.mpd line 102
WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_O - Failure in evaluting
ISVALID expresion "(C_USE_STARTUP==0)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_qspi_v1_
00_a/data/ps7_qspi_v2_1_0.mpd line 103
WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_T - Failure in evaluting
ISVALID expresion "(C_USE_STARTUP==0)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_qspi_v1_
00_a/data/ps7_qspi_v2_1_0.mpd line 104
WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK - Failure in evaluting
ISVALID expresion "(C_USE_STARTUP==0)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_qspi_v1_
00_a/data/ps7_qspi_v2_1_0.mpd line 122
Overriding IP level properties ...
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_BASE_ID -
Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 19
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_IS_ACLK_ASYNC - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 20
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_ACLK_RATIO
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 21
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_ARB_PRIORITY - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 22
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AW_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 23
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AR_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 24
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_W_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 25
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_R_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 26
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_B_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 27
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_WRITE_FIFO_DEPTH - Failure in evaluting ISVALID
expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 28
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_READ_FIFO_DEPTH - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 29
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_WRITE_ISSUING - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 30
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_READ_ISSUING - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 31
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ACLK - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 119
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARESETN - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 120
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 121
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWADDR - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 122
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLEN - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 123
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWSIZE - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 124
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWBURST - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 125
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWCACHE - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 126
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWPROT - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 127
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLOCK - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 128
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 129
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 130
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WDATA - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 131
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WSTRB - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 132
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WLAST - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 133
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 134
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 135
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BID - Failure in evaluting
ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 136
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BRESP - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 137
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 138
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 139
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 140
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARADDR - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 141
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLEN - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 142
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARSIZE - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 143
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARBURST - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 144
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARCACHE - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 145
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARPROT - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 146
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLOCK - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 147
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 148
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 149
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RID - Failure in evaluting
ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 150
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RDATA - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 151
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RRESP - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 152
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RLAST - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 153
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 154
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 155
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI - Failure in evaluting
ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 73
WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_I - Failure in evaluting
ISVALID expresion "(C_USE_STARTUP==0)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_qspi_v1_
00_a/data/ps7_qspi_v2_1_0.mpd line 102
WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_O - Failure in evaluting
ISVALID expresion "(C_USE_STARTUP==0)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_qspi_v1_
00_a/data/ps7_qspi_v2_1_0.mpd line 103
WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_T - Failure in evaluting
ISVALID expresion "(C_USE_STARTUP==0)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_qspi_v1_
00_a/data/ps7_qspi_v2_1_0.mpd line 104
WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK - Failure in evaluting
ISVALID expresion "(C_USE_STARTUP==0)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_qspi_v1_
00_a/data/ps7_qspi_v2_1_0.mpd line 122
Computing clock values...
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Address Map for Processor ps7_cortexa9_0
(0000000000-0x0002ffff) ps7_ram_0 ps7_axi_interconnect_0
(0x00100000-0x1fffffff) ps7_ddr_0 ps7_axi_interconnect_0
(0x41200000-0x4120ffff)
BTNs_4Bits_TRI_IO ps7_axi_interconnect_0->axi_interconnect_1
(0x76e00000-0x76e0ffff)
pwm_recorder_0 ps7_axi_interconnect_0->axi_interconnect_1
(0x76e20000-0x76e2ffff)
pwm_recorder_1 ps7_axi_interconnect_0->axi_interconnect_1
(0x76e40000-0x76e4ffff)
pwm_recorder_2 ps7_axi_interconnect_0->axi_interconnect_1
(0x76e60000-0x76e6ffff)
pwm_recorder_3 ps7_axi_interconnect_0->axi_interconnect_1
(0x76e80000-0x76e8ffff)
pwm_recorder_4 ps7_axi_interconnect_0->axi_interconnect_1
(0x76ea0000-0x76eaffff)
pwm_recorder_5 ps7_axi_interconnect_0->axi_interconnect_1
(0x79400000-0x7940ffff)
pwm_signal_out_wkillswitch_0 ps7_axi_interconnect_0->axi_interconnect_1
(0x79420000-0x7942ffff)
pwm_signal_out_wkillswitch_1 ps7_axi_interconnect_0->axi_interconnect_1
(0x79440000-0x7944ffff)
pwm_signal_out_wkillswitch_2 ps7_axi_interconnect_0->axi_interconnect_1
(0x79460000-0x7946ffff)
pwm_signal_out_wkillswitch_3 ps7_axi_interconnect_0->axi_interconnect_1
(0xe0000000-0xe0000fff) ps7_uart_0 ps7_axi_interconnect_0
(0xe0001000-0xe0001fff) ps7_uart_1 ps7_axi_interconnect_0
(0xe0002000-0xe0002fff) ps7_usb_0 ps7_axi_interconnect_0
(0xe0004000-0xe0004fff) ps7_i2c_0 ps7_axi_interconnect_0
(0xe000a000-0xe000afff) ps7_gpio_0 ps7_axi_interconnect_0
(0xe000b000-0xe000bfff) ps7_ethernet_0 ps7_axi_interconnect_0
(0xe000d000-0xe000dfff) ps7_qspi_0 ps7_axi_interconnect_0
(0xe0100000-0xe0100fff) ps7_sd_0 ps7_axi_interconnect_0
(0xe0200000-0xe0200fff) ps7_iop_bus_config_0 ps7_axi_interconnect_0
(0xf8000000-0xf8000fff) ps7_slcr_0 ps7_axi_interconnect_0
(0xf8003000-0xf8003fff) ps7_dma_s ps7_axi_interconnect_0
(0xf8004000-0xf8004fff) ps7_dma_ns ps7_axi_interconnect_0
(0xf8006000-0xf8006fff) ps7_ddrc_0 ps7_axi_interconnect_0
(0xf8007000-0xf80070ff) ps7_dev_cfg_0 ps7_axi_interconnect_0
(0xf8007100-0xf8007120) ps7_xadc_0 ps7_axi_interconnect_0
(0xf8008000-0xf8008fff) ps7_afi_0 ps7_axi_interconnect_0
(0xf8009000-0xf8009fff) ps7_afi_1 ps7_axi_interconnect_0
(0xf800a000-0xf800afff) ps7_afi_2 ps7_axi_interconnect_0
(0xf800b000-0xf800bfff) ps7_afi_3 ps7_axi_interconnect_0
(0xf800c000-0xf800cfff) ps7_ocmc_0 ps7_axi_interconnect_0
(0xf8800000-0xf88fffff) ps7_coresight_comp_0 ps7_axi_interconnect_0
(0xf8900000-0xf89fffff) ps7_gpv_0 ps7_axi_interconnect_0
(0xf8f00000-0xf8f000fc) ps7_scuc_0 ps7_axi_interconnect_0
(0xf8f00100-0xf8f001ff) ps7_scugic_0 ps7_axi_interconnect_0
(0xf8f00200-0xf8f002ff) ps7_globaltimer_0 ps7_axi_interconnect_0
(0xf8f00600-0xf8f0061f) ps7_scutimer_0 ps7_axi_interconnect_0
(0xf8f00620-0xf8f006ff) ps7_scuwdt_0 ps7_axi_interconnect_0
(0xf8f01000-0xf8f01fff) ps7_intc_dist_0 ps7_axi_interconnect_0
(0xf8f02000-0xf8f02fff) ps7_l2cachec_0 ps7_axi_interconnect_0
(0xfc000000-0xfcffffff) ps7_qspi_linear_0 ps7_axi_interconnect_0
(0xffff0000-0xfffffdff) ps7_ram_1 ps7_axi_interconnect_0
Address Map for Processor ps7_cortexa9_1
(0000000000-0x0002ffff) ps7_ram_0 ps7_axi_interconnect_0
(0x00100000-0x1fffffff) ps7_ddr_0 ps7_axi_interconnect_0
(0x41200000-0x4120ffff)
BTNs_4Bits_TRI_IO ps7_axi_interconnect_0->axi_interconnect_1
(0x76e00000-0x76e0ffff)
pwm_recorder_0 ps7_axi_interconnect_0->axi_interconnect_1
(0x76e20000-0x76e2ffff)
pwm_recorder_1 ps7_axi_interconnect_0->axi_interconnect_1
(0x76e40000-0x76e4ffff)
pwm_recorder_2 ps7_axi_interconnect_0->axi_interconnect_1
(0x76e60000-0x76e6ffff)
pwm_recorder_3 ps7_axi_interconnect_0->axi_interconnect_1
(0x76e80000-0x76e8ffff)
pwm_recorder_4 ps7_axi_interconnect_0->axi_interconnect_1
(0x76ea0000-0x76eaffff)
pwm_recorder_5 ps7_axi_interconnect_0->axi_interconnect_1
(0x79400000-0x7940ffff)
pwm_signal_out_wkillswitch_0 ps7_axi_interconnect_0->axi_interconnect_1
(0x79420000-0x7942ffff)
pwm_signal_out_wkillswitch_1 ps7_axi_interconnect_0->axi_interconnect_1
(0x79440000-0x7944ffff)
pwm_signal_out_wkillswitch_2 ps7_axi_interconnect_0->axi_interconnect_1
(0x79460000-0x7946ffff)
pwm_signal_out_wkillswitch_3 ps7_axi_interconnect_0->axi_interconnect_1
(0xe0000000-0xe0000fff) ps7_uart_0 ps7_axi_interconnect_0
(0xe0001000-0xe0001fff) ps7_uart_1 ps7_axi_interconnect_0
(0xe0002000-0xe0002fff) ps7_usb_0 ps7_axi_interconnect_0
(0xe0004000-0xe0004fff) ps7_i2c_0 ps7_axi_interconnect_0
(0xe000a000-0xe000afff) ps7_gpio_0 ps7_axi_interconnect_0
(0xe000b000-0xe000bfff) ps7_ethernet_0 ps7_axi_interconnect_0
(0xe000d000-0xe000dfff) ps7_qspi_0 ps7_axi_interconnect_0
(0xe0100000-0xe0100fff) ps7_sd_0 ps7_axi_interconnect_0
(0xe0200000-0xe0200fff) ps7_iop_bus_config_0 ps7_axi_interconnect_0
(0xf8000000-0xf8000fff) ps7_slcr_0 ps7_axi_interconnect_0
(0xf8003000-0xf8003fff) ps7_dma_s ps7_axi_interconnect_0
(0xf8004000-0xf8004fff) ps7_dma_ns ps7_axi_interconnect_0
(0xf8006000-0xf8006fff) ps7_ddrc_0 ps7_axi_interconnect_0
(0xf8007000-0xf80070ff) ps7_dev_cfg_0 ps7_axi_interconnect_0
(0xf8007100-0xf8007120) ps7_xadc_0 ps7_axi_interconnect_0
(0xf8008000-0xf8008fff) ps7_afi_0 ps7_axi_interconnect_0
(0xf8009000-0xf8009fff) ps7_afi_1 ps7_axi_interconnect_0
(0xf800a000-0xf800afff) ps7_afi_2 ps7_axi_interconnect_0
(0xf800b000-0xf800bfff) ps7_afi_3 ps7_axi_interconnect_0
(0xf800c000-0xf800cfff) ps7_ocmc_0 ps7_axi_interconnect_0
(0xf8800000-0xf88fffff) ps7_coresight_comp_0 ps7_axi_interconnect_0
(0xf8900000-0xf89fffff) ps7_gpv_0 ps7_axi_interconnect_0
(0xf8f00000-0xf8f000fc) ps7_scuc_0 ps7_axi_interconnect_0
(0xf8f00100-0xf8f001ff) ps7_scugic_0 ps7_axi_interconnect_0
(0xf8f00200-0xf8f002ff) ps7_globaltimer_0 ps7_axi_interconnect_0
(0xf8f00600-0xf8f0061f) ps7_scutimer_0 ps7_axi_interconnect_0
(0xf8f00620-0xf8f006ff) ps7_scuwdt_0 ps7_axi_interconnect_0
(0xf8f01000-0xf8f01fff) ps7_intc_dist_0 ps7_axi_interconnect_0
(0xf8f02000-0xf8f02fff) ps7_l2cachec_0 ps7_axi_interconnect_0
(0xfc000000-0xfcffffff) ps7_qspi_linear_0 ps7_axi_interconnect_0
(0xffff0000-0xfffffdff) ps7_ram_1 ps7_axi_interconnect_0
Checking platform address map ...
WARNING:EDK -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_i2c_v1_0
0_a/data/ps7_i2c_v2_1_0.mpd line 108 Unknown PORT subproperty IIC Serial Data
WARNING:EDK -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_i2c_v1_0
0_a/data/ps7_i2c_v2_1_0.mpd line 109 Unknown PORT subproperty IIC Serial
Clock
Conversion to XML complete.
xdsgen -inp system.xmp -report SDK/SDK_Export/hw/system.html -make_docs_local
Release 14.7 - xdsgen EDK_P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
/local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
WARNING:EDK:878 - Could not find IP doc
http://www.xilinx.com/cgi-bin/docs/ipdoc?c=clock_generator;v=v4_03_a;d=clock_
generator.pdf
WARNING:EDK:878 - Could not find IP doc
http://www.xilinx.com/cgi-bin/docs/ipdoc?c=proc_sys_reset;v=v3_00_a;d=proc_sy
s_reset.pdf
WARNING:EDK:878 - Could not find IP doc
http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v1_06_a;d=ds768
_axi_interconnect.pdf
WARNING:EDK:878 - Could not find IP doc
http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_gpio;v=v1_01_b;d=ds744_axi_gpi
o.pdf
Generated Block Diagram.
Rasterizing clock_generator_0.jpg.....
Rasterizing reset_0.jpg.....
Rasterizing processing_system7_0.jpg.....
Rasterizing pwm_recorder_0.jpg.....
Rasterizing axi_interconnect_1.jpg.....
Rasterizing pwm_recorder_1.jpg.....
Rasterizing pwm_recorder_2.jpg.....
Rasterizing pwm_recorder_3.jpg.....
Rasterizing pwm_recorder_4.jpg.....
Rasterizing pwm_recorder_5.jpg.....
Rasterizing BTNs_4Bits_TRI_IO.jpg.....
Rasterizing pwm_signal_out_wkillswitch_0.jpg.....
Rasterizing pwm_signal_out_wkillswitch_1.jpg.....
Rasterizing pwm_signal_out_wkillswitch_2.jpg.....
Rasterizing pwm_signal_out_wkillswitch_3.jpg.....
Rasterizing system_blkd.jpg.....
Report generated.
Report generation completed.
****************************************************
Creating system netlist for hardware specification..
****************************************************
platgen -p xc7z010clg400-1 -lang vhdl -intstyle default -msg __xps/ise/xmsgprops.lst system.mhs
Release 14.7 - platgen Xilinx EDK 14.7 Build EDK_P.20131013
(lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Command Line: platgen -p xc7z010clg400-1 -lang vhdl -intstyle default -msg
__xps/ise/xmsgprops.lst system.mhs
WARNING:EDK - INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable
is not set.
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
'1717@io.ece.iastate.edu:27006@io.ece.iastate.edu'.
INFO:Security:71 - If a license for part 'xc7z010' is available, it will be
possible to use 'XPS_TDP' instead of 'XPS'.
WARNING:Security:43 - No license file was found in the standard Xilinx
license directory.
WARNING:Security:44 - Since no license file was found,
please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
WARNING:Security:42 - Your software subscription period has lapsed. Your
current version of Xilinx tools will continue to function, but you no longer
qualify for Xilinx software updates or new releases.
Parse /local/ucart/microcart_may16/tasks/Quad/system/system.mhs ...
Read MPD definitions ...
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
/local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
/local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43
Overriding IP level properties ...
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_PACKAGE_NAME value to clg400 -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 185
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_S_AXI_HP0_HIGHADDR value to 0x1FFFFFFF -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 300
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_S_AXI_HP1_HIGHADDR value to 0x1FFFFFFF -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 304
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_S_AXI_HP2_HIGHADDR value to 0x1FFFFFFF -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 308
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_S_AXI_HP3_HIGHADDR value to 0x1FFFFFFF -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 312
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_NUM_F2P_INTR_INPUTS value to 1 -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 319
INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is
overriding PARAMETER C_BASEFAMILY value to zynq -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v
1_06_a/data/axi_interconnect_v2_1_0.mpd line 81
Computing clock values...
INFO:EDK:1432 - Frequency for Top-Level Input Clock
'processing_system7_0_PS_CLK_pin' is not specified. Clock DRCs will not be
performed for IPs connected to that clock port, unless they are connected
through the clock generator IP.
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
INFO:EDK - INFO: DDR Base and High address in current configuration is
0x00000000 and 0x1FFFFFFF respectively.
INFO:EDK - INFO: You can modify the DDR address range accessed by Programmable
Logic through the processing_system7 AXI slave interfaces. If MicroBlaze is a
master on processing_system7 AXI slave interfaces, please use the top half of
the address range (Base Address = 0x10000000; High Address = 0x1FFFFFFF). For
all other master, any subset of the DDR address can be used. See Xilinx
Answer 47167 for more information.
Address Map for Processor processing_system7_0
(0x41200000-0x4120ffff) BTNs_4Bits_TRI_IO axi_interconnect_1
(0x76e00000-0x76e0ffff) pwm_recorder_0 axi_interconnect_1
(0x76e20000-0x76e2ffff) pwm_recorder_1 axi_interconnect_1
(0x76e40000-0x76e4ffff) pwm_recorder_2 axi_interconnect_1
(0x76e60000-0x76e6ffff) pwm_recorder_3 axi_interconnect_1
(0x76e80000-0x76e8ffff) pwm_recorder_4 axi_interconnect_1
(0x76ea0000-0x76eaffff) pwm_recorder_5 axi_interconnect_1
(0x79400000-0x7940ffff) pwm_signal_out_wkillswitch_0 axi_interconnect_1
(0x79420000-0x7942ffff) pwm_signal_out_wkillswitch_1 axi_interconnect_1
(0x79440000-0x7944ffff) pwm_signal_out_wkillswitch_2 axi_interconnect_1
(0x79460000-0x7946ffff) pwm_signal_out_wkillswitch_3 axi_interconnect_1
Checking platform address map ...
Checking platform configuration ...
IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - 1 master(s) : 11
slave(s)
Checking port drivers...
Performing Clock DRCs...
Performing Reset DRCs...
Overriding system level properties...
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_FCLK_CLK1_BUF value to FALSE -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 351
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_FCLK_CLK2_BUF value to FALSE -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 352
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_FCLK_CLK3_BUF value to FALSE -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 353
INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi_interconnect_1.
INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is
overriding PARAMETER C_RANGE_CHECK value to 1 -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v
1_06_a/data/axi_interconnect_v2_1_0.mpd line 149
Running system level update procedures...
Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
ZynqConfig: Terminated for tcl mode
Running system level DRCs...
Performing System level DRCs on properties...
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
ZynqConfig: Terminated for tcl mode
Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
ZynqConfig: Terminated for tcl mode
INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_1.
Modify defaults ...
Creating stub ...
Processing licensed instances ...
Completion time: 0.00 seconds
Creating hardware output directories ...
Managing hardware (BBD-specified) netlist files ...
Managing cache ...
Elaborating instances ...
IPNAME:clock_generator INSTANCE:clock_generator_0 -
/local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43 - elaborating
IP
ClkGen elaborate status: PASSED
----------------------------------------
----------------------------------------
Writing HDL for elaborated instances ...
Inserting wrapper level ...
Completion time: 0.00 seconds
Constructing platform-level connectivity ...
Completion time: 1.00 seconds
Writing (top-level) BMM ...
Writing (top-level and wrappers) HDL ...
Generating synthesis project file ...
Running XST synthesis ...
INFO:EDK:4211 - The following instances are synthesized with XST. The MPD option
IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
INSTANCE:clock_generator_0 -
/local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:reset_0 - /local/ucart/microcart_may16/tasks/Quad/system/system.mhs
line 50 - Running XST synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:processing_system7_0 -
/local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 56 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_recorder_0 -
/local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 146 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:axi_interconnect_1 -
/local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 156 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_recorder_1 -
/local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 164 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_recorder_2 -
/local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 174 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_recorder_3 -
/local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 184 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_recorder_4 -
/local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 194 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_recorder_5 -
/local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 204 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:btns_4bits_tri_io -
/local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 214 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_signal_out_wkillswitch_0 -
/local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 226 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_signal_out_wkillswitch_1 -
/local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 236 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_signal_out_wkillswitch_2 -
/local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 246 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_signal_out_wkillswitch_3 -
/local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 256 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
Running NGCBUILD ...
IPNAME:system_clock_generator_0_wrapper INSTANCE:clock_generator_0 -
/local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 43 - Running
NGCBUILD
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
Command Line: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngcbuild -p
xc7z010clg400-1 -intstyle silent -i -sd .. system_clock_generator_0_wrapper.ngc
../system_clock_generator_0_wrapper
Reading NGO file
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/clock_generator_0
_wrapper/system_clock_generator_0_wrapper.ngc" ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../system_clock_generator_0_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 4 sec
Total CPU time to NGCBUILD completion: 4 sec
Writing NGCBUILD log file "../system_clock_generator_0_wrapper.blc"...
NGCBUILD done.
IPNAME:system_axi_interconnect_1_wrapper INSTANCE:axi_interconnect_1 -
/local/ucart/microcart_may16/tasks/Quad/system/system.mhs line 156 - Running
NGCBUILD
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
Command Line: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngcbuild -p
xc7z010clg400-1 -intstyle silent -i -sd .. system_axi_interconnect_1_wrapper.ngc
../system_axi_interconnect_1_wrapper
Reading NGO file
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/axi_interconnect_
1_wrapper/system_axi_interconnect_1_wrapper.ngc" ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../system_axi_interconnect_1_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 4 sec
Total CPU time to NGCBUILD completion: 4 sec
Writing NGCBUILD log file "../system_axi_interconnect_1_wrapper.blc"...
NGCBUILD done.
INFO:EDK:3509 - NCF files should not be modified as they will be regenerated.
If any constraint needs to be overridden, this should be done by modifying
the data/system.ucf file.
Rebuilding cache ...
Total run time: 204.00 seconds
Running synthesis...
bash -c "cd synthesis; ./synthesis.sh"
xst -ifn system_xst.scr -intstyle silent
Running XST synthesis ...
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
XST completed
*********************************************
Running Xilinx Implementation tools..
*********************************************
xflow -wd implementation -p xc7z010clg400-1 -implement xflow.opt system.ngc
Release 14.7 - Xflow P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
xflow -wd implementation -p xc7z010clg400-1 -implement xflow.opt system.ngc
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
.... Copying flowfile /opt/Xilinx/14.7/ISE_DS/ISE/xilinx/data/fpga.flw into
working directory /local/ucart/microcart_may16/tasks/Quad/system/implementation
Using Flow File:
/local/ucart/microcart_may16/tasks/Quad/system/implementation/fpga.flw
Using Option File(s):
/local/ucart/microcart_may16/tasks/Quad/system/implementation/xflow.opt
Creating Script File ...
#----------------------------------------------#
# Starting program ngdbuild
# ngdbuild -p xc7z010clg400-1 -nt timestamp -bm system.bmm
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system.ngc" -uc
system.ucf system.ngd
#----------------------------------------------#
Release 14.7 - ngdbuild P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
Command Line: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -p
xc7z010clg400-1 -nt timestamp -bm system.bmm
/local/ucart/microcart_may16/tasks/Quad/system/implementation/system.ngc -uc
system.ucf system.ngd
Reading NGO file
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system.ngc" ...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_btns_4bits
_tri_io_wrapper.ngc"...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_processing
_system7_0_wrapper.ngc"...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_pwm_record
er_0_wrapper.ngc"...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_pwm_record
er_1_wrapper.ngc"...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_pwm_record
er_2_wrapper.ngc"...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_pwm_record
er_3_wrapper.ngc"...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_pwm_record
er_4_wrapper.ngc"...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_pwm_record
er_5_wrapper.ngc"...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_clock_gene
rator_0_wrapper.ngc"...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_axi_interc
onnect_1_wrapper.ngc"...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_reset_0_wr
apper.ngc"...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_pwm_signal
_out_wkillswitch_0_wrapper.ngc"...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_pwm_signal
_out_wkillswitch_1_wrapper.ngc"...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_pwm_signal
_out_wkillswitch_2_wrapper.ngc"...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_pwm_signal
_out_wkillswitch_3_wrapper.ngc"...
Applying constraints in
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_processing
_system7_0_wrapper.ncf" to module "processing_system7_0"...
Checking Constraint Associations...
Applying constraints in
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_axi_interc
onnect_1_wrapper.ncf" to module "axi_interconnect_1"...
Checking Constraint Associations...
Gathering constraint information from source properties...
Done.
INFO:NgdBuild:649 - Removing redundant 'IBUF' symbol
'processing_system7_0_PS_PORB_pin_IBUF'. All constraints associated with
this symbol will be ignored.
INFO:NgdBuild:649 - Removing redundant 'IBUF' symbol
'processing_system7_0_PS_CLK_pin_IBUF'. All constraints associated with this
symbol will be ignored.
INFO:NgdBuild:649 - Removing redundant 'IBUF' symbol
'processing_system7_0_PS_SRSTB_pin_IBUF'. All constraints associated with
this symbol will be ignored.
Annotating constraints to design from ucf file "system.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
WARNING:ConstraintSystem:135 - Constraint <INST
/system/EXPANDED/system/axi_interconnect_1/axi_interconnect_1\/si_converter_b
ank\/gen_conv_slot[0].clock_conv_inst\/interconnect_aresetn_resync<2>_inv1_IN
V_0 TNM = FFS:axi_interconnect_1_reset...>: No instances of type FFS were
found under block
"axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync<2>_inv1_INV_0" (type=INV).
WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET "processing_system7_0_PS_PORB_pin_IBUF" LOC = C7>' could not be found
and so the Locate constraint will be removed.
WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET "processing_system7_0_PS_CLK_pin_IBUF" LOC = E7>' could not be found
and so the Locate constraint will be removed.
WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET "processing_system7_0_PS_SRSTB_pin_IBUF" LOC = B10>' could not be found
and so the Locate constraint will be removed.
WARNING:ConstraintSystem:58 - Constraint <TIMEGRP
axi_interconnect_1_reset_source = FFS PADS CPUS;>: CPUS "*" does not match
any design objects.
ERROR:ConstraintSystem:59 - Constraint <NET pwm_signal_out_0_pwm_out_sm_pin LOC
= "V13" |> [system.ucf(7)]: NET "pwm_signal_out_0_pwm_out_sm_pin" not found.
Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET pwm_signal_out_0_pwm_out_sm_pin LOC = "V13" |> [system.ucf(7)]' could
not be found and so the Locate constraint will be removed.
ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = "LVCMOS33";>
[system.ucf(7)]: NET "pwm_signal_out_0_pwm_out_sm_pin" not found. Please
verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <NET pwm_signal_out_1_pwm_out_sm_pin LOC
= "U17" |> [system.ucf(8)]: NET "pwm_signal_out_1_pwm_out_sm_pin" not found.
Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET pwm_signal_out_1_pwm_out_sm_pin LOC = "U17" |> [system.ucf(8)]' could
not be found and so the Locate constraint will be removed.
ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = "LVCMOS33";>
[system.ucf(8)]: NET "pwm_signal_out_1_pwm_out_sm_pin" not found. Please
verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <NET pwm_signal_out_2_pwm_out_sm_pin LOC
= "T17" |> [system.ucf(9)]: NET "pwm_signal_out_2_pwm_out_sm_pin" not found.
Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET pwm_signal_out_2_pwm_out_sm_pin LOC = "T17" |> [system.ucf(9)]' could
not be found and so the Locate constraint will be removed.
ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = "LVCMOS33";>
[system.ucf(9)]: NET "pwm_signal_out_2_pwm_out_sm_pin" not found. Please
verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <NET pwm_signal_out_3_pwm_out_sm_pin LOC
= "Y17" |> [system.ucf(10)]: NET "pwm_signal_out_3_pwm_out_sm_pin" not found.
Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET pwm_signal_out_3_pwm_out_sm_pin LOC = "Y17" |> [system.ucf(10)]' could
not be found and so the Locate constraint will be removed.
ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = "LVCMOS33";>
[system.ucf(10)]: NET "pwm_signal_out_3_pwm_out_sm_pin" not found. Please
verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
WARNING:ConstraintSystem:194 - The TNM 'axi_interconnect_1_reset_resync', does
not directly or indirectly drive any flip-flops, latches and/or RAMs and is
not actively used by any referencing constraint.
Done...
Processing BMM file "system.bmm" ...
WARNING::53 - File 'system.bmm' is empty or has no BMM content.
Checking expanded design ...
WARNING:NgdBuild:452 - logical net 'N129' has no driver
WARNING:NgdBuild:452 - logical net 'N130' has no driver
WARNING:NgdBuild:452 - logical net 'N131' has no driver
WARNING:NgdBuild:452 - logical net 'N132' has no driver
WARNING:NgdBuild:452 - logical net 'N133' has no driver
WARNING:NgdBuild:452 - logical net 'N134' has no driver
WARNING:NgdBuild:452 - logical net 'N135' has no driver
WARNING:NgdBuild:452 - logical net 'N136' has no driver
WARNING:NgdBuild:452 - logical net 'N137' has no driver
WARNING:NgdBuild:452 - logical net 'N138' has no driver
WARNING:NgdBuild:452 - logical net 'N139' has no driver
WARNING:NgdBuild:452 - logical net 'N140' has no driver
WARNING:NgdBuild:452 - logical net 'N141' has no driver
WARNING:NgdBuild:452 - logical net 'N142' has no driver
WARNING:NgdBuild:452 - logical net 'N143' has no driver
WARNING:NgdBuild:452 - logical net 'N144' has no driver
WARNING:NgdBuild:452 - logical net 'N145' has no driver
WARNING:NgdBuild:452 - logical net 'N146' has no driver
WARNING:NgdBuild:452 - logical net 'N147' has no driver
WARNING:NgdBuild:452 - logical net 'N148' has no driver
WARNING:NgdBuild:452 - logical net 'N149' has no driver
WARNING:NgdBuild:452 - logical net 'N150' has no driver
WARNING:NgdBuild:452 - logical net 'N151' has no driver
WARNING:NgdBuild:452 - logical net 'N152' has no driver
WARNING:NgdBuild:452 - logical net 'N153' has no driver
WARNING:NgdBuild:452 - logical net 'N154' has no driver
WARNING:NgdBuild:452 - logical net 'N155' has no driver
WARNING:NgdBuild:452 - logical net 'N156' has no driver
WARNING:NgdBuild:452 - logical net 'N157' has no driver
WARNING:NgdBuild:452 - logical net 'N158' has no driver
WARNING:NgdBuild:452 - logical net 'N159' has no driver
WARNING:NgdBuild:452 - logical net 'N160' has no driver
WARNING:NgdBuild:452 - logical net 'N161' has no driver
WARNING:NgdBuild:452 - logical net 'N162' has no driver
WARNING:NgdBuild:452 - logical net 'N163' has no driver
WARNING:NgdBuild:452 - logical net 'N164' has no driver
WARNING:NgdBuild:452 - logical net 'N165' has no driver
WARNING:NgdBuild:452 - logical net 'N166' has no driver
WARNING:NgdBuild:452 - logical net 'N167' has no driver
WARNING:NgdBuild:452 - logical net 'N168' has no driver
WARNING:NgdBuild:452 - logical net 'N169' has no driver
WARNING:NgdBuild:452 - logical net 'N170' has no driver
WARNING:NgdBuild:452 - logical net 'N171' has no driver
WARNING:NgdBuild:452 - logical net 'N172' has no driver
WARNING:NgdBuild:452 - logical net 'N173' has no driver
WARNING:NgdBuild:452 - logical net 'N174' has no driver
WARNING:NgdBuild:452 - logical net 'N175' has no driver
WARNING:NgdBuild:452 - logical net 'N176' has no driver
WARNING:NgdBuild:452 - logical net 'N177' has no driver
WARNING:NgdBuild:452 - logical net 'N178' has no driver
WARNING:NgdBuild:452 - logical net 'N179' has no driver
WARNING:NgdBuild:452 - logical net 'N180' has no driver
WARNING:NgdBuild:452 - logical net 'N181' has no driver
WARNING:NgdBuild:452 - logical net 'N182' has no driver
WARNING:NgdBuild:452 - logical net 'N183' has no driver
WARNING:NgdBuild:452 - logical net 'N184' has no driver
WARNING:NgdBuild:452 - logical net 'N185' has no driver
WARNING:NgdBuild:452 - logical net 'N186' has no driver
WARNING:NgdBuild:452 - logical net 'N187' has no driver
WARNING:NgdBuild:452 - logical net 'N188' has no driver
WARNING:NgdBuild:452 - logical net 'N189' has no driver
WARNING:NgdBuild:452 - logical net 'N190' has no driver
WARNING:NgdBuild:452 - logical net 'N191' has no driver
WARNING:NgdBuild:452 - logical net 'N192' has no driver
WARNING:NgdBuild:452 - logical net 'N193' has no driver
WARNING:NgdBuild:452 - logical net 'N194' has no driver
WARNING:NgdBuild:452 - logical net 'N195' has no driver
WARNING:NgdBuild:452 - logical net 'N196' has no driver
WARNING:NgdBuild:452 - logical net 'N197' has no driver
WARNING:NgdBuild:452 - logical net 'N198' has no driver
WARNING:NgdBuild:452 - logical net 'N199' has no driver
WARNING:NgdBuild:452 - logical net 'N200' has no driver
WARNING:NgdBuild:452 - logical net 'N201' has no driver
WARNING:NgdBuild:452 - logical net 'N202' has no driver
WARNING:NgdBuild:452 - logical net 'N203' has no driver
WARNING:NgdBuild:452 - logical net 'N204' has no driver
WARNING:NgdBuild:452 - logical net 'N205' has no driver
WARNING:NgdBuild:452 - logical net 'N206' has no driver
WARNING:NgdBuild:452 - logical net 'N207' has no driver
WARNING:NgdBuild:452 - logical net 'N208' has no driver
WARNING:NgdBuild:452 - logical net 'N209' has no driver
WARNING:NgdBuild:452 - logical net 'N210' has no driver
WARNING:NgdBuild:452 - logical net 'N211' has no driver
WARNING:NgdBuild:452 - logical net 'N212' has no driver
WARNING:NgdBuild:452 - logical net 'N213' has no driver
WARNING:NgdBuild:452 - logical net 'N214' has no driver
WARNING:NgdBuild:452 - logical net 'N215' has no driver
WARNING:NgdBuild:452 - logical net 'N216' has no driver
WARNING:NgdBuild:452 - logical net 'N217' has no driver
WARNING:NgdBuild:452 - logical net 'N218' has no driver
WARNING:NgdBuild:452 - logical net 'N219' has no driver
WARNING:NgdBuild:452 - logical net 'N220' has no driver
WARNING:NgdBuild:452 - logical net 'N221' has no driver
WARNING:NgdBuild:452 - logical net 'N222' has no driver
WARNING:NgdBuild:452 - logical net 'N223' has no driver
WARNING:NgdBuild:452 - logical net 'N224' has no driver
WARNING:NgdBuild:452 - logical net 'N225' has no driver
WARNING:NgdBuild:452 - logical net 'N226' has no driver
WARNING:NgdBuild:452 - logical net 'N227' has no driver
WARNING:NgdBuild:452 - logical net 'N228' has no driver
WARNING:NgdBuild:452 - logical net 'N229' has no driver
WARNING:NgdBuild:452 - logical net 'N230' has no driver
WARNING:NgdBuild:452 - logical net 'N231' has no driver
WARNING:NgdBuild:452 - logical net 'N232' has no driver
WARNING:NgdBuild:452 - logical net 'N233' has no driver
WARNING:NgdBuild:452 - logical net 'N234' has no driver
WARNING:NgdBuild:452 - logical net 'N235' has no driver
WARNING:NgdBuild:452 - logical net 'N236' has no driver
WARNING:NgdBuild:452 - logical net 'N237' has no driver
WARNING:NgdBuild:452 - logical net 'N238' has no driver
WARNING:NgdBuild:452 - logical net 'N239' has no driver
WARNING:NgdBuild:452 - logical net 'N240' has no driver
WARNING:NgdBuild:452 - logical net 'N241' has no driver
WARNING:NgdBuild:452 - logical net 'N242' has no driver
WARNING:NgdBuild:452 - logical net 'N243' has no driver
WARNING:NgdBuild:452 - logical net 'N244' has no driver
WARNING:NgdBuild:452 - logical net 'N245' has no driver
WARNING:NgdBuild:452 - logical net 'N246' has no driver
WARNING:NgdBuild:452 - logical net 'N247' has no driver
WARNING:NgdBuild:452 - logical net 'N248' has no driver
WARNING:NgdBuild:452 - logical net 'N249' has no driver
WARNING:NgdBuild:452 - logical net 'N250' has no driver
WARNING:NgdBuild:452 - logical net 'N251' has no driver
WARNING:NgdBuild:452 - logical net 'N252' has no driver
WARNING:NgdBuild:452 - logical net 'N253' has no driver
WARNING:NgdBuild:452 - logical net 'N254' has no driver
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 8
Number of warnings: 136
Total REAL time to NGDBUILD completion: 24 sec
Total CPU time to NGDBUILD completion: 24 sec
One or more errors were found during NGDBUILD. No NGD file will be written.
Writing NGDBUILD log file "system.bld"...
ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flow execution...
make: *** [__xps/system_routed] Error 1
Done!
Running DRCs...
Overriding IP level properties ...
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_PACKAGE_NAME value to clg400 - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 185
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_S_AXI_HP0_HIGHADDR value to 0x1FFFFFFF - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 300
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_S_AXI_HP1_HIGHADDR value to 0x1FFFFFFF - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 304
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_S_AXI_HP2_HIGHADDR value to 0x1FFFFFFF - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 308
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_S_AXI_HP3_HIGHADDR value to 0x1FFFFFFF - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 312
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_NUM_F2P_INTR_INPUTS value to 1 - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 319
INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is overriding PARAMETER C_BASEFAMILY value to zynq - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/data/axi_interconnect_v2_1_0.mpd line 81
Computing clock values...
INFO:EDK:1432 - Frequency for Top-Level Input Clock 'processing_system7_0_PS_CLK_pin' is not specified. Clock DRCs will not be performed for IPs connected to that clock port, unless they are connected through the clock generator IP.
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
INFO:EDK - INFO: DDR Base and High address in current configuration is 0x00000000 and 0x1FFFFFFF respectively.
INFO:EDK - INFO: You can modify the DDR address range accessed by Programmable Logic through the processing_system7 AXI slave interfaces. If MicroBlaze is a master on processing_system7 AXI slave interfaces, please use the top half of the address range (Base Address = 0x10000000; High Address = 0x1FFFFFFF). For all other master, any subset of the DDR address can be used. See Xilinx Answer 47167 for more information.
Address Map for Processor processing_system7_0
(0x41200000-0x4120ffff) BTNs_4Bits_TRI_IO axi_interconnect_1
(0x76e00000-0x76e0ffff) pwm_recorder_0 axi_interconnect_1
(0x76e20000-0x76e2ffff) pwm_recorder_1 axi_interconnect_1
(0x76e40000-0x76e4ffff) pwm_recorder_2 axi_interconnect_1
(0x76e60000-0x76e6ffff) pwm_recorder_3 axi_interconnect_1
(0x76e80000-0x76e8ffff) pwm_recorder_4 axi_interconnect_1
(0x76ea0000-0x76eaffff) pwm_recorder_5 axi_interconnect_1
(0x79400000-0x7940ffff) pwm_signal_out_wkillswitch_0 axi_interconnect_1
(0x79420000-0x7942ffff) pwm_signal_out_wkillswitch_1 axi_interconnect_1
(0x79440000-0x7944ffff) pwm_signal_out_wkillswitch_2 axi_interconnect_1
(0x79460000-0x7946ffff) pwm_signal_out_wkillswitch_3 axi_interconnect_1
Checking platform address map ...
Checking platform configuration ...
IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - 1 master(s) : 11 slave(s)
Checking port drivers...
Performing Clock DRCs...
Performing Reset DRCs...
Overriding system level properties...
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_FCLK_CLK1_BUF value to FALSE - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 351
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_FCLK_CLK2_BUF value to FALSE - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 352
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_FCLK_CLK3_BUF value to FALSE - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 353
INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi_interconnect_1.
INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is overriding PARAMETER C_RANGE_CHECK value to 1 - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/data/axi_interconnect_v2_1_0.mpd line 149
Running system level update procedures...
Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
Running system level DRCs...
Performing System level DRCs on properties...
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
Done!
Running DRCs...
Overriding IP level properties ...
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_PACKAGE_NAME value to clg400 - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 185
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_S_AXI_HP0_HIGHADDR value to 0x1FFFFFFF - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 300
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_S_AXI_HP1_HIGHADDR value to 0x1FFFFFFF - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 304
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_S_AXI_HP2_HIGHADDR value to 0x1FFFFFFF - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 308
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_S_AXI_HP3_HIGHADDR value to 0x1FFFFFFF - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 312
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_NUM_F2P_INTR_INPUTS value to 1 - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 319
INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is overriding PARAMETER C_BASEFAMILY value to zynq - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/data/axi_interconnect_v2_1_0.mpd line 81
Computing clock values...
INFO:EDK:1432 - Frequency for Top-Level Input Clock 'processing_system7_0_PS_CLK_pin' is not specified. Clock DRCs will not be performed for IPs connected to that clock port, unless they are connected through the clock generator IP.
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
INFO:EDK - INFO: DDR Base and High address in current configuration is 0x00000000 and 0x1FFFFFFF respectively.
INFO:EDK - INFO: You can modify the DDR address range accessed by Programmable Logic through the processing_system7 AXI slave interfaces. If MicroBlaze is a master on processing_system7 AXI slave interfaces, please use the top half of the address range (Base Address = 0x10000000; High Address = 0x1FFFFFFF). For all other master, any subset of the DDR address can be used. See Xilinx Answer 47167 for more information.
Address Map for Processor processing_system7_0
(0x41200000-0x4120ffff) BTNs_4Bits_TRI_IO axi_interconnect_1
(0x76e00000-0x76e0ffff) pwm_recorder_0 axi_interconnect_1
(0x76e20000-0x76e2ffff) pwm_recorder_1 axi_interconnect_1
(0x76e40000-0x76e4ffff) pwm_recorder_2 axi_interconnect_1
(0x76e60000-0x76e6ffff) pwm_recorder_3 axi_interconnect_1
(0x76e80000-0x76e8ffff) pwm_recorder_4 axi_interconnect_1
(0x76ea0000-0x76eaffff) pwm_recorder_5 axi_interconnect_1
(0x79400000-0x7940ffff) pwm_signal_out_wkillswitch_0 axi_interconnect_1
(0x79420000-0x7942ffff) pwm_signal_out_wkillswitch_1 axi_interconnect_1
(0x79440000-0x7944ffff) pwm_signal_out_wkillswitch_2 axi_interconnect_1
(0x79460000-0x7946ffff) pwm_signal_out_wkillswitch_3 axi_interconnect_1
Checking platform address map ...
Checking platform configuration ...
IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - 1 master(s) : 11 slave(s)
Checking port drivers...
Performing Clock DRCs...
Performing Reset DRCs...
Overriding system level properties...
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_FCLK_CLK1_BUF value to FALSE - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 351
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_FCLK_CLK2_BUF value to FALSE - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 352
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is overriding PARAMETER C_FCLK_CLK3_BUF value to FALSE - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_03_a/data/processing_system7_v2_1_0.mpd line 353
INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi_interconnect_1.
INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is overriding PARAMETER C_RANGE_CHECK value to 1 - /opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/data/axi_interconnect_v2_1_0.mpd line 149
Running system level update procedures...
Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
Running system level DRCs...
Performing System level DRCs on properties...
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
Done!
********************************************************************************
At Local date and time: Wed Oct 14 20:09:40 2015
make -f system.make exporttosdk started...
*********************************************
Running Xilinx Implementation tools..
*********************************************
xflow -wd implementation -p xc7z010clg400-1 -implement xflow.opt system.ngc
Release 14.7 - Xflow P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
xflow -wd implementation -p xc7z010clg400-1 -implement xflow.opt system.ngc
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
Using Flow File:
/local/ucart/microcart_may16/tasks/Quad/system/implementation/fpga.flw
Using Option File(s):
/local/ucart/microcart_may16/tasks/Quad/system/implementation/xflow.opt
Creating Script File ...
#----------------------------------------------#
# Starting program ngdbuild
# ngdbuild -p xc7z010clg400-1 -nt timestamp -bm system.bmm
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system.ngc" -uc
system.ucf system.ngd
#----------------------------------------------#
Release 14.7 - ngdbuild P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
Command Line: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -p
xc7z010clg400-1 -nt timestamp -bm system.bmm
/local/ucart/microcart_may16/tasks/Quad/system/implementation/system.ngc -uc
system.ucf system.ngd
Reading NGO file
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system.ngc" ...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_btns_4bits
_tri_io_wrapper.ngc"...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_processing
_system7_0_wrapper.ngc"...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_pwm_record
er_0_wrapper.ngc"...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_pwm_record
er_1_wrapper.ngc"...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_pwm_record
er_2_wrapper.ngc"...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_pwm_record
er_3_wrapper.ngc"...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_pwm_record
er_4_wrapper.ngc"...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_pwm_record
er_5_wrapper.ngc"...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_clock_gene
rator_0_wrapper.ngc"...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_axi_interc
onnect_1_wrapper.ngc"...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_reset_0_wr
apper.ngc"...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_pwm_signal
_out_wkillswitch_0_wrapper.ngc"...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_pwm_signal
_out_wkillswitch_1_wrapper.ngc"...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_pwm_signal
_out_wkillswitch_2_wrapper.ngc"...
Loading design module
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_pwm_signal
_out_wkillswitch_3_wrapper.ngc"...
Applying constraints in
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_processing
_system7_0_wrapper.ncf" to module "processing_system7_0"...
Checking Constraint Associations...
Applying constraints in
"/local/ucart/microcart_may16/tasks/Quad/system/implementation/system_axi_interc
onnect_1_wrapper.ncf" to module "axi_interconnect_1"...
Checking Constraint Associations...
Gathering constraint information from source properties...
Done.
INFO:NgdBuild:649 - Removing redundant 'IBUF' symbol
'processing_system7_0_PS_PORB_pin_IBUF'. All constraints associated with
this symbol will be ignored.
INFO:NgdBuild:649 - Removing redundant 'IBUF' symbol
'processing_system7_0_PS_CLK_pin_IBUF'. All constraints associated with this
symbol will be ignored.
INFO:NgdBuild:649 - Removing redundant 'IBUF' symbol
'processing_system7_0_PS_SRSTB_pin_IBUF'. All constraints associated with
this symbol will be ignored.
Annotating constraints to design from ucf file "system.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
WARNING:ConstraintSystem:135 - Constraint <INST
/system/EXPANDED/system/axi_interconnect_1/axi_interconnect_1\/si_converter_b
ank\/gen_conv_slot[0].clock_conv_inst\/interconnect_aresetn_resync<2>_inv1_IN
V_0 TNM = FFS:axi_interconnect_1_reset...>: No instances of type FFS were
found under block
"axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync<2>_inv1_INV_0" (type=INV).
WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET "processing_system7_0_PS_PORB_pin_IBUF" LOC = C7>' could not be found
and so the Locate constraint will be removed.
WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET "processing_system7_0_PS_CLK_pin_IBUF" LOC = E7>' could not be found
and so the Locate constraint will be removed.
WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET "processing_system7_0_PS_SRSTB_pin_IBUF" LOC = B10>' could not be found
and so the Locate constraint will be removed.
WARNING:ConstraintSystem:58 - Constraint <TIMEGRP
axi_interconnect_1_reset_source = FFS PADS CPUS;>: CPUS "*" does not match
any design objects.
WARNING:ConstraintSystem:194 - The TNM 'axi_interconnect_1_reset_resync', does
not directly or indirectly drive any flip-flops, latches and/or RAMs and is
not actively used by any referencing constraint.
Done...
Processing BMM file "system.bmm" ...
WARNING::53 - File 'system.bmm' is empty or has no BMM content.
Checking expanded design ...
WARNING:NgdBuild:452 - logical net 'N129' has no driver
WARNING:NgdBuild:452 - logical net 'N130' has no driver
WARNING:NgdBuild:452 - logical net 'N131' has no driver
WARNING:NgdBuild:452 - logical net 'N132' has no driver
WARNING:NgdBuild:452 - logical net 'N133' has no driver
WARNING:NgdBuild:452 - logical net 'N134' has no driver
WARNING:NgdBuild:452 - logical net 'N135' has no driver
WARNING:NgdBuild:452 - logical net 'N136' has no driver
WARNING:NgdBuild:452 - logical net 'N137' has no driver
WARNING:NgdBuild:452 - logical net 'N138' has no driver
WARNING:NgdBuild:452 - logical net 'N139' has no driver
WARNING:NgdBuild:452 - logical net 'N140' has no driver
WARNING:NgdBuild:452 - logical net 'N141' has no driver
WARNING:NgdBuild:452 - logical net 'N142' has no driver
WARNING:NgdBuild:452 - logical net 'N143' has no driver
WARNING:NgdBuild:452 - logical net 'N144' has no driver
WARNING:NgdBuild:452 - logical net 'N145' has no driver
WARNING:NgdBuild:452 - logical net 'N146' has no driver
WARNING:NgdBuild:452 - logical net 'N147' has no driver
WARNING:NgdBuild:452 - logical net 'N148' has no driver
WARNING:NgdBuild:452 - logical net 'N149' has no driver
WARNING:NgdBuild:452 - logical net 'N150' has no driver
WARNING:NgdBuild:452 - logical net 'N151' has no driver
WARNING:NgdBuild:452 - logical net 'N152' has no driver
WARNING:NgdBuild:452 - logical net 'N153' has no driver
WARNING:NgdBuild:452 - logical net 'N154' has no driver
WARNING:NgdBuild:452 - logical net 'N155' has no driver
WARNING:NgdBuild:452 - logical net 'N156' has no driver
WARNING:NgdBuild:452 - logical net 'N157' has no driver
WARNING:NgdBuild:452 - logical net 'N158' has no driver
WARNING:NgdBuild:452 - logical net 'N159' has no driver
WARNING:NgdBuild:452 - logical net 'N160' has no driver
WARNING:NgdBuild:452 - logical net 'N161' has no driver
WARNING:NgdBuild:452 - logical net 'N162' has no driver
WARNING:NgdBuild:452 - logical net 'N163' has no driver
WARNING:NgdBuild:452 - logical net 'N164' has no driver
WARNING:NgdBuild:452 - logical net 'N165' has no driver
WARNING:NgdBuild:452 - logical net 'N166' has no driver
WARNING:NgdBuild:452 - logical net 'N167' has no driver
WARNING:NgdBuild:452 - logical net 'N168' has no driver
WARNING:NgdBuild:452 - logical net 'N169' has no driver
WARNING:NgdBuild:452 - logical net 'N170' has no driver
WARNING:NgdBuild:452 - logical net 'N171' has no driver
WARNING:NgdBuild:452 - logical net 'N172' has no driver
WARNING:NgdBuild:452 - logical net 'N173' has no driver
WARNING:NgdBuild:452 - logical net 'N174' has no driver
WARNING:NgdBuild:452 - logical net 'N175' has no driver
WARNING:NgdBuild:452 - logical net 'N176' has no driver
WARNING:NgdBuild:452 - logical net 'N177' has no driver
WARNING:NgdBuild:452 - logical net 'N178' has no driver
WARNING:NgdBuild:452 - logical net 'N179' has no driver
WARNING:NgdBuild:452 - logical net 'N180' has no driver
WARNING:NgdBuild:452 - logical net 'N181' has no driver
WARNING:NgdBuild:452 - logical net 'N182' has no driver
WARNING:NgdBuild:452 - logical net 'N183' has no driver
WARNING:NgdBuild:452 - logical net 'N184' has no driver
WARNING:NgdBuild:452 - logical net 'N185' has no driver
WARNING:NgdBuild:452 - logical net 'N186' has no driver
WARNING:NgdBuild:452 - logical net 'N187' has no driver
WARNING:NgdBuild:452 - logical net 'N188' has no driver
WARNING:NgdBuild:452 - logical net 'N189' has no driver
WARNING:NgdBuild:452 - logical net 'N190' has no driver
WARNING:NgdBuild:452 - logical net 'N191' has no driver
WARNING:NgdBuild:452 - logical net 'N192' has no driver
WARNING:NgdBuild:452 - logical net 'N193' has no driver
WARNING:NgdBuild:452 - logical net 'N194' has no driver
WARNING:NgdBuild:452 - logical net 'N195' has no driver
WARNING:NgdBuild:452 - logical net 'N196' has no driver
WARNING:NgdBuild:452 - logical net 'N197' has no driver
WARNING:NgdBuild:452 - logical net 'N198' has no driver
WARNING:NgdBuild:452 - logical net 'N199' has no driver
WARNING:NgdBuild:452 - logical net 'N200' has no driver
WARNING:NgdBuild:452 - logical net 'N201' has no driver
WARNING:NgdBuild:452 - logical net 'N202' has no driver
WARNING:NgdBuild:452 - logical net 'N203' has no driver
WARNING:NgdBuild:452 - logical net 'N204' has no driver
WARNING:NgdBuild:452 - logical net 'N205' has no driver
WARNING:NgdBuild:452 - logical net 'N206' has no driver
WARNING:NgdBuild:452 - logical net 'N207' has no driver
WARNING:NgdBuild:452 - logical net 'N208' has no driver
WARNING:NgdBuild:452 - logical net 'N209' has no driver
WARNING:NgdBuild:452 - logical net 'N210' has no driver
WARNING:NgdBuild:452 - logical net 'N211' has no driver
WARNING:NgdBuild:452 - logical net 'N212' has no driver
WARNING:NgdBuild:452 - logical net 'N213' has no driver
WARNING:NgdBuild:452 - logical net 'N214' has no driver
WARNING:NgdBuild:452 - logical net 'N215' has no driver
WARNING:NgdBuild:452 - logical net 'N216' has no driver
WARNING:NgdBuild:452 - logical net 'N217' has no driver
WARNING:NgdBuild:452 - logical net 'N218' has no driver
WARNING:NgdBuild:452 - logical net 'N219' has no driver
WARNING:NgdBuild:452 - logical net 'N220' has no driver
WARNING:NgdBuild:452 - logical net 'N221' has no driver
WARNING:NgdBuild:452 - logical net 'N222' has no driver
WARNING:NgdBuild:452 - logical net 'N223' has no driver
WARNING:NgdBuild:452 - logical net 'N224' has no driver
WARNING:NgdBuild:452 - logical net 'N225' has no driver
WARNING:NgdBuild:452 - logical net 'N226' has no driver
WARNING:NgdBuild:452 - logical net 'N227' has no driver
WARNING:NgdBuild:452 - logical net 'N228' has no driver
WARNING:NgdBuild:452 - logical net 'N229' has no driver
WARNING:NgdBuild:452 - logical net 'N230' has no driver
WARNING:NgdBuild:452 - logical net 'N231' has no driver
WARNING:NgdBuild:452 - logical net 'N232' has no driver
WARNING:NgdBuild:452 - logical net 'N233' has no driver
WARNING:NgdBuild:452 - logical net 'N234' has no driver
WARNING:NgdBuild:452 - logical net 'N235' has no driver
WARNING:NgdBuild:452 - logical net 'N236' has no driver
WARNING:NgdBuild:452 - logical net 'N237' has no driver
WARNING:NgdBuild:452 - logical net 'N238' has no driver
WARNING:NgdBuild:452 - logical net 'N239' has no driver
WARNING:NgdBuild:452 - logical net 'N240' has no driver
WARNING:NgdBuild:452 - logical net 'N241' has no driver
WARNING:NgdBuild:452 - logical net 'N242' has no driver
WARNING:NgdBuild:452 - logical net 'N243' has no driver
WARNING:NgdBuild:452 - logical net 'N244' has no driver
WARNING:NgdBuild:452 - logical net 'N245' has no driver
WARNING:NgdBuild:452 - logical net 'N246' has no driver
WARNING:NgdBuild:452 - logical net 'N247' has no driver
WARNING:NgdBuild:452 - logical net 'N248' has no driver
WARNING:NgdBuild:452 - logical net 'N249' has no driver
WARNING:NgdBuild:452 - logical net 'N250' has no driver
WARNING:NgdBuild:452 - logical net 'N251' has no driver
WARNING:NgdBuild:452 - logical net 'N252' has no driver
WARNING:NgdBuild:452 - logical net 'N253' has no driver
WARNING:NgdBuild:452 - logical net 'N254' has no driver
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 132
Writing NGD file "system.ngd" ...
Total REAL time to NGDBUILD completion: 25 sec
Total CPU time to NGDBUILD completion: 25 sec
Writing NGDBUILD log file "system.bld"...
NGDBUILD done.
#----------------------------------------------#
# Starting program map
# map -o system_map.ncd -w -pr b -ol high -timing -detail system.ngd system.pcf
#----------------------------------------------#
Release 14.7 - Map P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/data/Xdh_PrimTypeLib.xda> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/data/Xdh_PrimTypeLib.xda>
Using target part "7z010clg400-1".
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set.
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
'1717@io.ece.iastate.edu:27006@io.ece.iastate.edu'.
INFO:Security:54 - 'xc7z010' is a WebPack part.
WARNING:Security:43 - No license file was found in the standard Xilinx license
directory.
WARNING:Security:44 - Since no license file was found,
please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
----------------------------------------------------------------------
WARNING:LIT:701 - PAD symbol "CLK_N" has an undefined IOSTANDARD.
WARNING:LIT:702 - PAD symbol "CLK_N" is not constrained (LOC) to a specific
location.
WARNING:LIT:701 - PAD symbol "CLK_P" has an undefined IOSTANDARD.
WARNING:LIT:702 - PAD symbol "CLK_P" is not constrained (LOC) to a specific
location.
WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_SRSTB_pin" has an
undefined IOSTANDARD.
WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_SRSTB_pin" is not
constrained (LOC) to a specific location.
WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_CLK_pin" has an undefined
IOSTANDARD.
WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_CLK_pin" is not
constrained (LOC) to a specific location.
WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_PORB_pin" has an undefined
IOSTANDARD.
WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_PORB_pin" is not
constrained (LOC) to a specific location.
Mapping design into LUTs...
WARNING:MapLib:701 - Signal CLK_P connected to top level port CLK_P has been
removed.
WARNING:MapLib:701 - Signal CLK_N connected to top level port CLK_N has been
removed.
Writing file system_map.ngm...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 27 secs
Total CPU time at the beginning of Placer: 27 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:8310d50b) REAL time: 29 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:8310d50b) REAL time: 30 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:8310d50b) REAL time: 30 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:abb3fc01) REAL time: 34 secs
Phase 5.30 Global Clock Region Assignment
Phase 5.30 Global Clock Region Assignment (Checksum:abb3fc01) REAL time: 34 secs
Phase 6.3 Local Placement Optimization
Phase 6.3 Local Placement Optimization (Checksum:abb3fc01) REAL time: 34 secs
Phase 7.5 Local Placement Optimization
Phase 7.5 Local Placement Optimization (Checksum:abb3fc01) REAL time: 34 secs
Phase 8.8 Global Placement
................................
....................................................................................................................................
.........................................................................................................................................................
Phase 8.8 Global Placement (Checksum:e347f06c) REAL time: 40 secs
Phase 9.5 Local Placement Optimization
Phase 9.5 Local Placement Optimization (Checksum:e347f06c) REAL time: 40 secs
Phase 10.18 Placement Optimization
Phase 10.18 Placement Optimization (Checksum:ab7cf133) REAL time: 43 secs
Phase 11.5 Local Placement Optimization
Phase 11.5 Local Placement Optimization (Checksum:ab7cf133) REAL time: 43 secs
Phase 12.34 Placement Validation
Phase 12.34 Placement Validation (Checksum:ab7cf133) REAL time: 44 secs
Total REAL time to Placer completion: 44 secs
Total CPU time to Placer completion: 44 secs
Running post-placement packing...
Writing output files...
Design Summary:
Number of errors: 0
Number of warnings: 12
Slice Logic Utilization:
Number of Slice Registers: 2,373 out of 35,200 6%
Number used as Flip Flops: 2,116
Number used as Latches: 256
Number used as Latch-thrus: 0
Number used as AND/OR logics: 1
Number of Slice LUTs: 2,146 out of 17,600 12%
Number used as logic: 2,042 out of 17,600 11%
Number using O6 output only: 1,096
Number using O5 output only: 224
Number using O5 and O6: 722
Number used as ROM: 0
Number used as Memory: 4 out of 6,000 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 4
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 100
Number with same-slice register load: 96
Number with same-slice carry load: 4
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 938 out of 4,400 21%
Number of LUT Flip Flop pairs used: 3,038
Number with an unused Flip Flop: 983 out of 3,038 32%
Number with an unused LUT: 892 out of 3,038 29%
Number of fully used LUT-FF pairs: 1,163 out of 3,038 38%
Number of unique control sets: 106
Number of slice register sites lost
to control set restrictions: 432 out of 35,200 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
OVERMAPPING of BRAM resources should be ignored if the design is
over-mapped for a non-BRAM resource or if placement fails.
IO Utilization:
Number of bonded IOBs: 16 out of 100 16%
Number of LOCed IOBs: 16 out of 16 100%
Number of bonded IOPAD: 130 out of 130 100%
IOB Flip Flops: 6
Specific Feature Utilization:
Number of RAMB36E1/FIFO36E1s: 0 out of 60 0%
Number of RAMB18E1/FIFO18E1s: 0 out of 120 0%
Number of BUFG/BUFGCTRLs: 5 out of 32 15%
Number used as BUFGs: 5
Number used as BUFGCTRLs: 0
Number of IDELAYE2/IDELAYE2_FINEDELAYs: 0 out of 100 0%
Number of ILOGICE2/ILOGICE3/ISERDESE2s: 6 out of 100 6%
Number used as ILOGICE2s: 6
Number used as ILOGICE3s: 0
Number used as ISERDESE2s: 0
Number of ODELAYE2/ODELAYE2_FINEDELAYs: 0
Number of OLOGICE2/OLOGICE3/OSERDESE2s: 0 out of 100 0%
Number of PHASER_IN/PHASER_IN_PHYs: 0 out of 8 0%
Number of PHASER_OUT/PHASER_OUT_PHYs: 0 out of 8 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHCEs: 0 out of 48 0%
Number of BUFRs: 0 out of 8 0%
Number of CAPTUREs: 0 out of 1 0%
Number of DNA_PORTs: 0 out of 1 0%
Number of DSP48E1s: 0 out of 80 0%
Number of EFUSE_USRs: 0 out of 1 0%
Number of FRAME_ECCs: 0 out of 1 0%
Number of ICAPs: 0 out of 2 0%
Number of IDELAYCTRLs: 0 out of 2 0%
Number of IN_FIFOs: 0 out of 8 0%
Number of MMCME2_ADVs: 0 out of 2 0%
Number of OUT_FIFOs: 0 out of 8 0%
Number of PHASER_REFs: 0 out of 2 0%
Number of PHY_CONTROLs: 0 out of 2 0%
Number of PLLE2_ADVs: 0 out of 2 0%
Number of PS7s: 1 out of 1 100%
Number of STARTUPs: 0 out of 1 0%
Number of XADCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.25
Peak Memory Usage: 1270 MB
Total REAL time to MAP completion: 46 secs
Total CPU time to MAP completion: 46 secs
Mapping completed.
See MAP report file "system_map.mrp" for details.
#----------------------------------------------#
# Starting program par
# par -w -ol high system_map.ncd system.ncd system.pcf
#----------------------------------------------#
Release 14.7 - par P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file </opt/Xilinx/14.7/ISE_DS/EDK/data/parBmgr.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/data/parBmgr.acd>
Constraints file: system.pcf.
Loading device for application Rf_Device from file '7z010.nph' in environment
/opt/Xilinx/14.7/ISE_DS/ISE/:/opt/Xilinx/14.7/ISE_DS/EDK.
"system" is an NCD, version 3.2, device xc7z010, package clg400, speed -1
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set.
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
'1717@io.ece.iastate.edu:27006@io.ece.iastate.edu'.
INFO:Security:54 - 'xc7z010' is a WebPack part.
WARNING:Security:43 - No license file was found in the standard Xilinx license directory.
WARNING:Security:44 - Since no license file was found,
please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)
Device speed data version: "PRODUCTION 1.08 2013-10-13".
Device Utilization Summary:
Number of BUFGs 5 out of 32 15%
Number of ILOGICE2s 6 out of 100 6%
Number of External IOB33s 16 out of 100 16%
Number of LOCed IOB33s 16 out of 16 100%
Number of External IOPADs 130 out of 130 100%
Number of LOCed IOPADs 127 out of 130 97%
Number of PS7s 1 out of 1 100%
Number of Slices 938 out of 4400 21%
Number of Slice Registers 2373 out of 35200 6%
Number used as Flip Flops 2117
Number used as Latches 256
Number used as LatchThrus 0
Number of Slice LUTS 2146 out of 17600 12%
Number of Slice LUT-Flip Flop pairs 2994 out of 17600 17%
Overall effort level (-ol): High
Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 15 secs
Finished initial Timing Analysis. REAL time: 15 secs
Starting Router
Phase 1 : 13725 unrouted; REAL time: 16 secs
Phase 2 : 10227 unrouted; REAL time: 16 secs
Phase 3 : 3457 unrouted; REAL time: 20 secs
Phase 4 : 3457 unrouted; (Setup:0, Hold:13564, Component Switching Limit:0) REAL time: 21 secs
Updating file: system.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:12100, Component Switching Limit:0) REAL time: 25 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:12100, Component Switching Limit:0) REAL time: 25 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:12100, Component Switching Limit:0) REAL time: 25 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:12100, Component Switching Limit:0) REAL time: 25 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 26 secs
Total REAL time to Router completion: 26 secs
Total CPU time to Router completion: 26 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|processing_system7_0 | | | | | |
| _FCLK_CLK0 | BUFGCTRL_X0Y0| No | 611 | 0.133 | 1.774 |
+---------------------+--------------+------+------+------------+-------------+
|pwm_signal_out_wkill | | | | | |
|switch_0/pwm_signal_ | | | | | |
|out_wkillswitch_0/US | | | | | |
|ER_LOGIC_I/PWM_Hello | | | | | |
|/counter[31]_pwm_per | | | | | |
|_t[31]_equal_9_o_BUF | | | | | |
| G |BUFGCTRL_X0Y31| No | 16 | 0.022 | 1.657 |
+---------------------+--------------+------+------+------------+-------------+
|pwm_signal_out_wkill | | | | | |
|switch_1/pwm_signal_ | | | | | |
|out_wkillswitch_1/US | | | | | |
|ER_LOGIC_I/PWM_Hello | | | | | |
|/counter[31]_pwm_per | | | | | |
|_t[31]_equal_9_o_BUF | | | | | |
| G |BUFGCTRL_X0Y30| No | 16 | 0.018 | 1.667 |
+---------------------+--------------+------+------+------------+-------------+
|pwm_signal_out_wkill | | | | | |
|switch_3/pwm_signal_ | | | | | |
|out_wkillswitch_3/US | | | | | |
|ER_LOGIC_I/PWM_Hello | | | | | |
|/counter[31]_pwm_per | | | | | |
|_t[31]_equal_9_o_BUF | | | | | |
| G | BUFGCTRL_X0Y1| No | 16 | 0.018 | 1.665 |
+---------------------+--------------+------+------+------------+-------------+
|pwm_signal_out_wkill | | | | | |
|switch_2/pwm_signal_ | | | | | |
|out_wkillswitch_2/US | | | | | |
|ER_LOGIC_I/PWM_Hello | | | | | |
|/counter[31]_pwm_per | | | | | |
|_t[31]_equal_9_o_BUF | | | | | |
| G | BUFGCTRL_X0Y2| No | 16 | 0.012 | 1.670 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_clk_fpga_0 = PERIOD TIMEGRP "clk_fpga_ | SETUP | 0.453ns| 9.547ns| 0| 0
0" 100 MHz HIGH 50% | HOLD | 0.018ns| | 0| 0
----------------------------------------------------------------------------------------------------------
PATH "TS_axi_interconnect_1_reset_resync_ | SETUP | N/A| 1.100ns| N/A| 0
path" TIG | | | | |
----------------------------------------------------------------------------------------------------------
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 27 secs
Total CPU time to PAR completion: 27 secs
Peak Memory Usage: 961 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1
Writing design to file system.ncd
PAR done!
#----------------------------------------------#
# Starting program post_par_trce
# trce -e 3 -xml system.twx system.ncd system.pcf
#----------------------------------------------#
Release 14.7 - Trace (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
Loading device for application Rf_Device from file '7z010.nph' in environment
/opt/Xilinx/14.7/ISE_DS/ISE/:/opt/Xilinx/14.7/ISE_DS/EDK.
"system" is an NCD, version 3.2, device xc7z010, package clg400, speed -1
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more
information, see the TSI report. Please consult the Xilinx Command Line
Tools User Guide for information on generating a TSI report.
--------------------------------------------------------------------------------
Release 14.7 Trace (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -e 3 -xml system.twx
system.ncd system.pcf
Design file: system.ncd
Physical constraint file: system.pcf
Device,speed: xc7z010,-1 (PRODUCTION 1.08 2013-10-13)
Report level: error report
--------------------------------------------------------------------------------
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in
the unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of
this model, and for more information on accounting for different loading conditions, please see the device datasheet.
Timing summary:
---------------
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
Constraints cover 71514 paths, 0 nets, and 9934 connections
Design statistics:
Minimum period: 9.547ns (Maximum frequency: 104.745MHz)
Analysis completed Wed Oct 14 20:11:43 2015
--------------------------------------------------------------------------------
Generating Report ...
Number of warnings: 0
Number of info messages: 4
Total time: 15 secs
xflow done!
touch __xps/system_routed
xilperl /opt/Xilinx/14.7/ISE_DS/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par
Analyzing implementation/system.par
*********************************************
Running Bitgen..
*********************************************
cd implementation ; bitgen -w -f bitgen.ut system ; cd ..
Release 14.7 - Bitgen P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
Loading device for application Rf_Device from file '7z010.nph' in environment
/opt/Xilinx/14.7/ISE_DS/ISE/:/opt/Xilinx/14.7/ISE_DS/EDK.
"system" is an NCD, version 3.2, device xc7z010, package clg400, speed -1
Opened constraints file system.pcf.
Wed Oct 14 20:11:55 2015
Running DRC.
DRC detected 0 errors and 0 warnings.
INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set.
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
'1717@io.ece.iastate.edu:27006@io.ece.iastate.edu'.
INFO:Security:54 - 'xc7z010' is a WebPack part.
WARNING:Security:43 - No license file was found in the standard Xilinx license
directory.
WARNING:Security:44 - Since no license file was found,
please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
Creating bit map...
Saving bit stream in "system.bit".
Bitstream generation is complete.
Done!
Writing filter settings....
Done writing filter settings to:
/local/ucart/microcart_may16/tasks/Quad/system/etc/system.filters
Done writing Tab View settings to:
/local/ucart/microcart_may16/tasks/Quad/system/etc/system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.7 Build EDK_P.20131013
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Writing filter settings....
Done writing filter settings to:
/local/ucart/microcart_may16/tasks/Quad/system/etc/system.filters
Done writing Tab View settings to:
/local/ucart/microcart_may16/tasks/Quad/system/etc/system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.7 Build EDK_P.20131013
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Overriding Xilinx file <TextEditor.cfg> with local file </opt/Xilinx/14.7/ISE_DS/EDK/data/TextEditor.cfg>
Writing filter settings....
Done writing filter settings to:
/local/ucart/microcart1630/tasks/Quad/system/etc/system.filters
Done writing Tab View settings to:
/local/ucart/microcart1630/tasks/Quad/system/etc/system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.7 Build EDK_P.20131013
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Overriding Xilinx file <TextEditor.cfg> with local file </opt/Xilinx/14.7/ISE_DS/EDK/data/TextEditor.cfg>
Xilinx Platform Studio (XPS)
Xilinx EDK 14.7 Build EDK_P.20131013
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Overriding Xilinx file <TextEditor.cfg> with local file </opt/Xilinx/14.7/ISE_DS/EDK/data/TextEditor.cfg>
Writing filter settings....
Done writing filter settings to:
/local/ucart/microcart1630/tasks/Quad/system/etc/system.filters
Done writing Tab View settings to:
/local/ucart/microcart1630/tasks/Quad/system/etc/system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.7 Build EDK_P.20131013
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Writing filter settings....
Done writing filter settings to:
/local/ucart/microcart1630/tasks/Quad/system/etc/system.filters
Done writing Tab View settings to:
/local/ucart/microcart1630/tasks/Quad/system/etc/system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.7 Build EDK_P.20131013
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Overriding Xilinx file <TextEditor.cfg> with local file </opt/Xilinx/14.7/ISE_DS/EDK/data/TextEditor.cfg>
Writing filter settings....
Done writing filter settings to:
/local/ucart/microcart1630/tasks/Quad/system/etc/system.filters
Done writing Tab View settings to:
/local/ucart/microcart1630/tasks/Quad/system/etc/system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.7 Build EDK_P.20131013
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Assigned Driver tmrctr 2.05.a for instance axi_timer_0
axi_timer_0 has been added to the project
ERROR:EDK:4125 - IPNAME: axi_timer, INSTANCE: axi_timer_0, PARAMETER: C_BASEADDR - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a value in the MHS.
ERROR:EDK:4125 - IPNAME: axi_timer, INSTANCE: axi_timer_0, PARAMETER: C_HIGHADDR - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a value in the MHS.
WARNING:EDK:2137 - Peripheral axi_timer_0 is not accessible from any processor in the system. Check Bus Interface connections and address parameters.
Address Map for Processor processing_system7_0
(0x41200000-0x4120ffff) BTNs_4Bits_TRI_IO axi_interconnect_1
(0x42800000-0x4280ffff) axi_timer_0 axi_interconnect_1
(0x76e00000-0x76e0ffff) pwm_recorder_0 axi_interconnect_1
(0x76e20000-0x76e2ffff) pwm_recorder_1 axi_interconnect_1
(0x76e40000-0x76e4ffff) pwm_recorder_2 axi_interconnect_1
(0x76e60000-0x76e6ffff) pwm_recorder_3 axi_interconnect_1
(0x76e80000-0x76e8ffff) pwm_recorder_4 axi_interconnect_1
(0x76ea0000-0x76eaffff) pwm_recorder_5 axi_interconnect_1
(0x79400000-0x7940ffff) pwm_signal_out_wkillswitch_0 axi_interconnect_1
(0x79420000-0x7942ffff) pwm_signal_out_wkillswitch_1 axi_interconnect_1
(0x79440000-0x7944ffff) pwm_signal_out_wkillswitch_2 axi_interconnect_1
(0x79460000-0x7946ffff) pwm_signal_out_wkillswitch_3 axi_interconnect_1
INFO:EDK - Do connection by refering to bus interface of a processing_system7_0 in design
INFO:EDK - Connect bus interface S_AXI to axi_interconnect_1
INFO:EDK - Connect clock port S_AXI_ACLK to processing_system7_0_FCLK_CLK0
INFO:EDK - Successfully did connection by refering to M_AXI_GP0 bus interface in processing_system7_0
INFO:EDK - External IO port grouping doneINFO:EDK - Generate address successfully
INFO:EDK - Successfully finished auto bus connection for IP instance: axi_timer_0
********************************************************************************
At Local date and time: Wed Dec 30 20:33:54 2015
make -f system.make hwclean started...
rm -f implementation/system.ngc
rm -f implementation/system_clock_generator_0_wrapper.ngc implementation/system_reset_0_wrapper.ngc implementation/system_processing_system7_0_wrapper.ngc implementation/system_pwm_recorder_0_wrapper.ngc implementation/system_axi_interconnect_1_wrapper.ngc implementation/system_pwm_recorder_1_wrapper.ngc implementation/system_pwm_recorder_2_wrapper.ngc implementation/system_pwm_recorder_3_wrapper.ngc implementation/system_pwm_recorder_4_wrapper.ngc implementation/system_pwm_recorder_5_wrapper.ngc implementation/system_btns_4bits_tri_io_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_0_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_1_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_2_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_3_wrapper.ngc implementation/system_axi_timer_0_wrapper.ngc
rm -f platgen.log
rm -f __xps/ise/_xmsgs/platgen.xmsgs
rm -f implementation/system.bmm
rm -rf implementation/cache
rm -f implementation/system.bit
rm -f implementation/system.ncd
rm -f implementation/system_bd.bmm
rm -f implementation/system_map.ncd
rm -f implementation/download.bit
rm -f __xps/system_bits
rm -rf implementation synthesis xst hdl
rm -rf xst.srp system.srp
rm -f __xps/ise/_xmsgs/bitinit.xmsgs
rm -rf __xps/ps7_instance.mhs
Done!
********************************************************************************
At Local date and time: Wed Dec 30 20:33:59 2015
make -f system.make netlistclean started...
rm -f implementation/system.ngc
rm -f implementation/system_clock_generator_0_wrapper.ngc implementation/system_reset_0_wrapper.ngc implementation/system_processing_system7_0_wrapper.ngc implementation/system_pwm_recorder_0_wrapper.ngc implementation/system_axi_interconnect_1_wrapper.ngc implementation/system_pwm_recorder_1_wrapper.ngc implementation/system_pwm_recorder_2_wrapper.ngc implementation/system_pwm_recorder_3_wrapper.ngc implementation/system_pwm_recorder_4_wrapper.ngc implementation/system_pwm_recorder_5_wrapper.ngc implementation/system_btns_4bits_tri_io_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_0_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_1_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_2_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_3_wrapper.ngc implementation/system_axi_timer_0_wrapper.ngc
rm -f platgen.log
rm -f __xps/ise/_xmsgs/platgen.xmsgs
rm -f implementation/system.bmm
rm -rf implementation/cache
Done!
********************************************************************************
At Local date and time: Wed Dec 30 20:34:03 2015
make -f system.make bitsclean started...
rm -f implementation/system.bit
rm -f implementation/system.ncd
rm -f implementation/system_bd.bmm
rm -f implementation/system_map.ncd
rm -f implementation/download.bit
rm -f __xps/system_bits
Done!
********************************************************************************
At Local date and time: Wed Dec 30 20:34:29 2015
make -f system.make exporttosdk started...
pscgen -mhs system.mhs -expdir SDK/SDK_Export/hw
Generating ps7_init code for Si version 1....
Generating ps7_init code for Si version 2....
Generating ps7_init code for Si version 3....
psf2Edward -inp system.xmp -flat_zynq -dont_run_checkhwsys -dont_add_loginfo -make_inst_lower -edwver 1.2 -xml SDK/SDK_Export/hw/system.xml
Release 14.7 - psf2Edward EDK_P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 43
WARNING:EDK -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_i2c_v1_0
0_a/data/ps7_i2c_v2_1_0.mpd line 108 Unknown PORT subproperty IIC Serial Data
WARNING:EDK -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_i2c_v1_0
0_a/data/ps7_i2c_v2_1_0.mpd line 109 Unknown PORT subproperty IIC Serial
Clock
WARNING:EDK:2486 - The bitwidth 52 of new value 0xc00000000f281 is greater than
32
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_BASE_ID -
Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 19
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_IS_ACLK_ASYNC - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 20
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_ACLK_RATIO
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 21
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_ARB_PRIORITY - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 22
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AW_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 23
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AR_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 24
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_W_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 25
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_R_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 26
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_B_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 27
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_WRITE_FIFO_DEPTH - Failure in evaluting ISVALID
expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 28
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_READ_FIFO_DEPTH - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 29
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_WRITE_ISSUING - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 30
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_READ_ISSUING - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 31
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ACLK - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 119
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARESETN - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 120
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 121
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWADDR - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 122
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLEN - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 123
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWSIZE - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 124
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWBURST - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 125
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWCACHE - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 126
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWPROT - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 127
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLOCK - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 128
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 129
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 130
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WDATA - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 131
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WSTRB - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 132
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WLAST - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 133
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 134
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 135
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BID - Failure in evaluting
ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 136
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BRESP - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 137
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 138
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 139
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 140
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARADDR - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 141
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLEN - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 142
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARSIZE - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 143
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARBURST - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 144
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARCACHE - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 145
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARPROT - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 146
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLOCK - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 147
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 148
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 149
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RID - Failure in evaluting
ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 150
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RDATA - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 151
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RRESP - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 152
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RLAST - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 153
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 154
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 155
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI - Failure in evaluting
ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 73
WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_I - Failure in evaluting
ISVALID expresion "(C_USE_STARTUP==0)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_qspi_v1_
00_a/data/ps7_qspi_v2_1_0.mpd line 102
WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_O - Failure in evaluting
ISVALID expresion "(C_USE_STARTUP==0)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_qspi_v1_
00_a/data/ps7_qspi_v2_1_0.mpd line 103
WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_T - Failure in evaluting
ISVALID expresion "(C_USE_STARTUP==0)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_qspi_v1_
00_a/data/ps7_qspi_v2_1_0.mpd line 104
WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK - Failure in evaluting
ISVALID expresion "(C_USE_STARTUP==0)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_qspi_v1_
00_a/data/ps7_qspi_v2_1_0.mpd line 122
Overriding IP level properties ...
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_BASE_ID -
Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 19
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_IS_ACLK_ASYNC - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 20
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_ACLK_RATIO
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 21
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_ARB_PRIORITY - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 22
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AW_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 23
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AR_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 24
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_W_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 25
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_R_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 26
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_B_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 27
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_WRITE_FIFO_DEPTH - Failure in evaluting ISVALID
expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 28
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_READ_FIFO_DEPTH - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 29
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_WRITE_ISSUING - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 30
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_READ_ISSUING - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 31
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ACLK - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 119
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARESETN - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 120
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 121
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWADDR - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 122
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLEN - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 123
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWSIZE - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 124
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWBURST - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 125
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWCACHE - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 126
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWPROT - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 127
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLOCK - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 128
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 129
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 130
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WDATA - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 131
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WSTRB - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 132
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WLAST - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 133
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 134
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 135
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BID - Failure in evaluting
ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 136
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BRESP - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 137
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 138
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 139
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 140
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARADDR - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 141
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLEN - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 142
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARSIZE - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 143
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARBURST - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 144
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARCACHE - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 145
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARPROT - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 146
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLOCK - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 147
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 148
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 149
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RID - Failure in evaluting
ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 150
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RDATA - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 151
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RRESP - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 152
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RLAST - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 153
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 154
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 155
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI - Failure in evaluting
ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 73
WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_I - Failure in evaluting
ISVALID expresion "(C_USE_STARTUP==0)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_qspi_v1_
00_a/data/ps7_qspi_v2_1_0.mpd line 102
WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_O - Failure in evaluting
ISVALID expresion "(C_USE_STARTUP==0)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_qspi_v1_
00_a/data/ps7_qspi_v2_1_0.mpd line 103
WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_T - Failure in evaluting
ISVALID expresion "(C_USE_STARTUP==0)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_qspi_v1_
00_a/data/ps7_qspi_v2_1_0.mpd line 104
WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK - Failure in evaluting
ISVALID expresion "(C_USE_STARTUP==0)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_qspi_v1_
00_a/data/ps7_qspi_v2_1_0.mpd line 122
Computing clock values...
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Address Map for Processor ps7_cortexa9_0
(0000000000-0x0002ffff) ps7_ram_0 ps7_axi_interconnect_0
(0x00100000-0x1fffffff) ps7_ddr_0 ps7_axi_interconnect_0
(0x41200000-0x4120ffff)
BTNs_4Bits_TRI_IO ps7_axi_interconnect_0->axi_interconnect_1
(0x42800000-0x4280ffff) axi_timer_0 ps7_axi_interconnect_0->axi_interconnect_1
(0x76e00000-0x76e0ffff)
pwm_recorder_0 ps7_axi_interconnect_0->axi_interconnect_1
(0x76e20000-0x76e2ffff)
pwm_recorder_1 ps7_axi_interconnect_0->axi_interconnect_1
(0x76e40000-0x76e4ffff)
pwm_recorder_2 ps7_axi_interconnect_0->axi_interconnect_1
(0x76e60000-0x76e6ffff)
pwm_recorder_3 ps7_axi_interconnect_0->axi_interconnect_1
(0x76e80000-0x76e8ffff)
pwm_recorder_4 ps7_axi_interconnect_0->axi_interconnect_1
(0x76ea0000-0x76eaffff)
pwm_recorder_5 ps7_axi_interconnect_0->axi_interconnect_1
(0x79400000-0x7940ffff)
pwm_signal_out_wkillswitch_0 ps7_axi_interconnect_0->axi_interconnect_1
(0x79420000-0x7942ffff)
pwm_signal_out_wkillswitch_1 ps7_axi_interconnect_0->axi_interconnect_1
(0x79440000-0x7944ffff)
pwm_signal_out_wkillswitch_2 ps7_axi_interconnect_0->axi_interconnect_1
(0x79460000-0x7946ffff)
pwm_signal_out_wkillswitch_3 ps7_axi_interconnect_0->axi_interconnect_1
(0xe0000000-0xe0000fff) ps7_uart_0 ps7_axi_interconnect_0
(0xe0001000-0xe0001fff) ps7_uart_1 ps7_axi_interconnect_0
(0xe0002000-0xe0002fff) ps7_usb_0 ps7_axi_interconnect_0
(0xe0004000-0xe0004fff) ps7_i2c_0 ps7_axi_interconnect_0
(0xe000a000-0xe000afff) ps7_gpio_0 ps7_axi_interconnect_0
(0xe000b000-0xe000bfff) ps7_ethernet_0 ps7_axi_interconnect_0
(0xe000d000-0xe000dfff) ps7_qspi_0 ps7_axi_interconnect_0
(0xe0100000-0xe0100fff) ps7_sd_0 ps7_axi_interconnect_0
(0xe0200000-0xe0200fff) ps7_iop_bus_config_0 ps7_axi_interconnect_0
(0xf8000000-0xf8000fff) ps7_slcr_0 ps7_axi_interconnect_0
(0xf8003000-0xf8003fff) ps7_dma_s ps7_axi_interconnect_0
(0xf8004000-0xf8004fff) ps7_dma_ns ps7_axi_interconnect_0
(0xf8006000-0xf8006fff) ps7_ddrc_0 ps7_axi_interconnect_0
(0xf8007000-0xf80070ff) ps7_dev_cfg_0 ps7_axi_interconnect_0
(0xf8007100-0xf8007120) ps7_xadc_0 ps7_axi_interconnect_0
(0xf8008000-0xf8008fff) ps7_afi_0 ps7_axi_interconnect_0
(0xf8009000-0xf8009fff) ps7_afi_1 ps7_axi_interconnect_0
(0xf800a000-0xf800afff) ps7_afi_2 ps7_axi_interconnect_0
(0xf800b000-0xf800bfff) ps7_afi_3 ps7_axi_interconnect_0
(0xf800c000-0xf800cfff) ps7_ocmc_0 ps7_axi_interconnect_0
(0xf8800000-0xf88fffff) ps7_coresight_comp_0 ps7_axi_interconnect_0
(0xf8900000-0xf89fffff) ps7_gpv_0 ps7_axi_interconnect_0
(0xf8f00000-0xf8f000fc) ps7_scuc_0 ps7_axi_interconnect_0
(0xf8f00100-0xf8f001ff) ps7_scugic_0 ps7_axi_interconnect_0
(0xf8f00200-0xf8f002ff) ps7_globaltimer_0 ps7_axi_interconnect_0
(0xf8f00600-0xf8f0061f) ps7_scutimer_0 ps7_axi_interconnect_0
(0xf8f00620-0xf8f006ff) ps7_scuwdt_0 ps7_axi_interconnect_0
(0xf8f01000-0xf8f01fff) ps7_intc_dist_0 ps7_axi_interconnect_0
(0xf8f02000-0xf8f02fff) ps7_l2cachec_0 ps7_axi_interconnect_0
(0xfc000000-0xfcffffff) ps7_qspi_linear_0 ps7_axi_interconnect_0
(0xffff0000-0xfffffdff) ps7_ram_1 ps7_axi_interconnect_0
Address Map for Processor ps7_cortexa9_1
(0000000000-0x0002ffff) ps7_ram_0 ps7_axi_interconnect_0
(0x00100000-0x1fffffff) ps7_ddr_0 ps7_axi_interconnect_0
(0x41200000-0x4120ffff)
BTNs_4Bits_TRI_IO ps7_axi_interconnect_0->axi_interconnect_1
(0x42800000-0x4280ffff) axi_timer_0 ps7_axi_interconnect_0->axi_interconnect_1
(0x76e00000-0x76e0ffff)
pwm_recorder_0 ps7_axi_interconnect_0->axi_interconnect_1
(0x76e20000-0x76e2ffff)
pwm_recorder_1 ps7_axi_interconnect_0->axi_interconnect_1
(0x76e40000-0x76e4ffff)
pwm_recorder_2 ps7_axi_interconnect_0->axi_interconnect_1
(0x76e60000-0x76e6ffff)
pwm_recorder_3 ps7_axi_interconnect_0->axi_interconnect_1
(0x76e80000-0x76e8ffff)
pwm_recorder_4 ps7_axi_interconnect_0->axi_interconnect_1
(0x76ea0000-0x76eaffff)
pwm_recorder_5 ps7_axi_interconnect_0->axi_interconnect_1
(0x79400000-0x7940ffff)
pwm_signal_out_wkillswitch_0 ps7_axi_interconnect_0->axi_interconnect_1
(0x79420000-0x7942ffff)
pwm_signal_out_wkillswitch_1 ps7_axi_interconnect_0->axi_interconnect_1
(0x79440000-0x7944ffff)
pwm_signal_out_wkillswitch_2 ps7_axi_interconnect_0->axi_interconnect_1
(0x79460000-0x7946ffff)
pwm_signal_out_wkillswitch_3 ps7_axi_interconnect_0->axi_interconnect_1
(0xe0000000-0xe0000fff) ps7_uart_0 ps7_axi_interconnect_0
(0xe0001000-0xe0001fff) ps7_uart_1 ps7_axi_interconnect_0
(0xe0002000-0xe0002fff) ps7_usb_0 ps7_axi_interconnect_0
(0xe0004000-0xe0004fff) ps7_i2c_0 ps7_axi_interconnect_0
(0xe000a000-0xe000afff) ps7_gpio_0 ps7_axi_interconnect_0
(0xe000b000-0xe000bfff) ps7_ethernet_0 ps7_axi_interconnect_0
(0xe000d000-0xe000dfff) ps7_qspi_0 ps7_axi_interconnect_0
(0xe0100000-0xe0100fff) ps7_sd_0 ps7_axi_interconnect_0
(0xe0200000-0xe0200fff) ps7_iop_bus_config_0 ps7_axi_interconnect_0
(0xf8000000-0xf8000fff) ps7_slcr_0 ps7_axi_interconnect_0
(0xf8003000-0xf8003fff) ps7_dma_s ps7_axi_interconnect_0
(0xf8004000-0xf8004fff) ps7_dma_ns ps7_axi_interconnect_0
(0xf8006000-0xf8006fff) ps7_ddrc_0 ps7_axi_interconnect_0
(0xf8007000-0xf80070ff) ps7_dev_cfg_0 ps7_axi_interconnect_0
(0xf8007100-0xf8007120) ps7_xadc_0 ps7_axi_interconnect_0
(0xf8008000-0xf8008fff) ps7_afi_0 ps7_axi_interconnect_0
(0xf8009000-0xf8009fff) ps7_afi_1 ps7_axi_interconnect_0
(0xf800a000-0xf800afff) ps7_afi_2 ps7_axi_interconnect_0
(0xf800b000-0xf800bfff) ps7_afi_3 ps7_axi_interconnect_0
(0xf800c000-0xf800cfff) ps7_ocmc_0 ps7_axi_interconnect_0
(0xf8800000-0xf88fffff) ps7_coresight_comp_0 ps7_axi_interconnect_0
(0xf8900000-0xf89fffff) ps7_gpv_0 ps7_axi_interconnect_0
(0xf8f00000-0xf8f000fc) ps7_scuc_0 ps7_axi_interconnect_0
(0xf8f00100-0xf8f001ff) ps7_scugic_0 ps7_axi_interconnect_0
(0xf8f00200-0xf8f002ff) ps7_globaltimer_0 ps7_axi_interconnect_0
(0xf8f00600-0xf8f0061f) ps7_scutimer_0 ps7_axi_interconnect_0
(0xf8f00620-0xf8f006ff) ps7_scuwdt_0 ps7_axi_interconnect_0
(0xf8f01000-0xf8f01fff) ps7_intc_dist_0 ps7_axi_interconnect_0
(0xf8f02000-0xf8f02fff) ps7_l2cachec_0 ps7_axi_interconnect_0
(0xfc000000-0xfcffffff) ps7_qspi_linear_0 ps7_axi_interconnect_0
(0xffff0000-0xfffffdff) ps7_ram_1 ps7_axi_interconnect_0
Checking platform address map ...
WARNING:EDK -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_i2c_v1_0
0_a/data/ps7_i2c_v2_1_0.mpd line 108 Unknown PORT subproperty IIC Serial Data
WARNING:EDK -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_i2c_v1_0
0_a/data/ps7_i2c_v2_1_0.mpd line 109 Unknown PORT subproperty IIC Serial
Clock
Conversion to XML complete.
xdsgen -inp system.xmp -report SDK/SDK_Export/hw/system.html -make_docs_local
Release 14.7 - xdsgen EDK_P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 43
WARNING:EDK:878 - Could not find IP doc
http://www.xilinx.com/cgi-bin/docs/ipdoc?c=clock_generator;v=v4_03_a;d=clock_
generator.pdf
WARNING:EDK:878 - Could not find IP doc
http://www.xilinx.com/cgi-bin/docs/ipdoc?c=proc_sys_reset;v=v3_00_a;d=proc_sy
s_reset.pdf
WARNING:EDK:878 - Could not find IP doc
http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v1_06_a;d=ds768
_axi_interconnect.pdf
WARNING:EDK:878 - Could not find IP doc
http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_gpio;v=v1_01_b;d=ds744_axi_gpi
o.pdf
WARNING:EDK:878 - Could not find IP doc
http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_timer;v=v1_03_a;d=axi_timer_ds
764.pdf
Generated Block Diagram.
Rasterizing clock_generator_0.jpg.....
Rasterizing reset_0.jpg.....
Rasterizing processing_system7_0.jpg.....
Rasterizing pwm_recorder_0.jpg.....
Rasterizing axi_interconnect_1.jpg.....
Rasterizing pwm_recorder_1.jpg.....
Rasterizing pwm_recorder_2.jpg.....
Rasterizing pwm_recorder_3.jpg.....
Rasterizing pwm_recorder_4.jpg.....
Rasterizing pwm_recorder_5.jpg.....
Rasterizing BTNs_4Bits_TRI_IO.jpg.....
Rasterizing pwm_signal_out_wkillswitch_0.jpg.....
Rasterizing pwm_signal_out_wkillswitch_1.jpg.....
Rasterizing pwm_signal_out_wkillswitch_2.jpg.....
Rasterizing pwm_signal_out_wkillswitch_3.jpg.....
Rasterizing axi_timer_0.jpg.....
Rasterizing system_blkd.jpg.....
Report generated.
Report generation completed.
****************************************************
Creating system netlist for hardware specification..
****************************************************
platgen -p xc7z010clg400-1 -lang vhdl -intstyle default -msg __xps/ise/xmsgprops.lst system.mhs
Release 14.7 - platgen Xilinx EDK 14.7 Build EDK_P.20131013
(lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Command Line: platgen -p xc7z010clg400-1 -lang vhdl -intstyle default -msg
__xps/ise/xmsgprops.lst system.mhs
WARNING:EDK - INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable
is not set.
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
'1717@io.ece.iastate.edu:27006@io.ece.iastate.edu'.
INFO:Security:71 - If a license for part 'xc7z010' is available, it will be
possible to use 'XPS_TDP' instead of 'XPS'.
WARNING:Security:43 - No license file was found in the standard Xilinx
license directory.
WARNING:Security:44 - Since no license file was found,
please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
WARNING:Security:42 - Your software subscription period has lapsed. Your
current version of Xilinx tools will continue to function, but you no longer
qualify for Xilinx software updates or new releases.
Parse /local/ucart/microcart1630/tasks/Quad/system/system.mhs ...
Read MPD definitions ...
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 43
Overriding IP level properties ...
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_PACKAGE_NAME value to clg400 -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 185
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_S_AXI_HP0_HIGHADDR value to 0x1FFFFFFF -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 300
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_S_AXI_HP1_HIGHADDR value to 0x1FFFFFFF -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 304
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_S_AXI_HP2_HIGHADDR value to 0x1FFFFFFF -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 308
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_S_AXI_HP3_HIGHADDR value to 0x1FFFFFFF -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 312
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_NUM_F2P_INTR_INPUTS value to 1 -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 319
INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is
overriding PARAMETER C_BASEFAMILY value to zynq -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v
1_06_a/data/axi_interconnect_v2_1_0.mpd line 81
Computing clock values...
INFO:EDK:1432 - Frequency for Top-Level Input Clock
'processing_system7_0_PS_CLK_pin' is not specified. Clock DRCs will not be
performed for IPs connected to that clock port, unless they are connected
through the clock generator IP.
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
INFO:EDK - INFO: DDR Base and High address in current configuration is
0x00000000 and 0x1FFFFFFF respectively.
INFO:EDK - INFO: You can modify the DDR address range accessed by Programmable
Logic through the processing_system7 AXI slave interfaces. If MicroBlaze is a
master on processing_system7 AXI slave interfaces, please use the top half of
the address range (Base Address = 0x10000000; High Address = 0x1FFFFFFF). For
all other master, any subset of the DDR address can be used. See Xilinx
Answer 47167 for more information.
Address Map for Processor processing_system7_0
(0x41200000-0x4120ffff) BTNs_4Bits_TRI_IO axi_interconnect_1
(0x42800000-0x4280ffff) axi_timer_0 axi_interconnect_1
(0x76e00000-0x76e0ffff) pwm_recorder_0 axi_interconnect_1
(0x76e20000-0x76e2ffff) pwm_recorder_1 axi_interconnect_1
(0x76e40000-0x76e4ffff) pwm_recorder_2 axi_interconnect_1
(0x76e60000-0x76e6ffff) pwm_recorder_3 axi_interconnect_1
(0x76e80000-0x76e8ffff) pwm_recorder_4 axi_interconnect_1
(0x76ea0000-0x76eaffff) pwm_recorder_5 axi_interconnect_1
(0x79400000-0x7940ffff) pwm_signal_out_wkillswitch_0 axi_interconnect_1
(0x79420000-0x7942ffff) pwm_signal_out_wkillswitch_1 axi_interconnect_1
(0x79440000-0x7944ffff) pwm_signal_out_wkillswitch_2 axi_interconnect_1
(0x79460000-0x7946ffff) pwm_signal_out_wkillswitch_3 axi_interconnect_1
Checking platform address map ...
Checking platform configuration ...
IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - 1 master(s) : 12
slave(s)
Checking port drivers...
Performing Clock DRCs...
Performing Reset DRCs...
Overriding system level properties...
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_FCLK_CLK1_BUF value to FALSE -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 351
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_FCLK_CLK2_BUF value to FALSE -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 352
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_FCLK_CLK3_BUF value to FALSE -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 353
INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi_interconnect_1.
INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is
overriding PARAMETER C_RANGE_CHECK value to 1 -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v
1_06_a/data/axi_interconnect_v2_1_0.mpd line 149
Running system level update procedures...
Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
ZynqConfig: Terminated for tcl mode
Running system level DRCs...
Performing System level DRCs on properties...
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
ZynqConfig: Terminated for tcl mode
Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
ZynqConfig: Terminated for tcl mode
INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_1.
Modify defaults ...
Creating stub ...
Processing licensed instances ...
Completion time: 0.00 seconds
Creating hardware output directories ...
Managing hardware (BBD-specified) netlist files ...
Managing cache ...
Elaborating instances ...
IPNAME:clock_generator INSTANCE:clock_generator_0 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 43 - elaborating IP
ClkGen elaborate status: PASSED
----------------------------------------
----------------------------------------
Writing HDL for elaborated instances ...
Inserting wrapper level ...
Completion time: 0.00 seconds
Constructing platform-level connectivity ...
Completion time: 0.00 seconds
Writing (top-level) BMM ...
Writing (top-level and wrappers) HDL ...
Generating synthesis project file ...
Running XST synthesis ...
INFO:EDK:4211 - The following instances are synthesized with XST. The MPD option
IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
INSTANCE:clock_generator_0 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 43 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:reset_0 - /local/ucart/microcart1630/tasks/Quad/system/system.mhs line
50 - Running XST synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:processing_system7_0 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 56 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_recorder_0 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 146 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:axi_interconnect_1 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 156 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_recorder_1 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 164 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_recorder_2 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 174 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_recorder_3 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 184 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_recorder_4 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 194 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_recorder_5 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 204 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:btns_4bits_tri_io -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 214 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_signal_out_wkillswitch_0 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 226 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_signal_out_wkillswitch_1 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 236 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_signal_out_wkillswitch_2 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 246 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_signal_out_wkillswitch_3 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 256 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:axi_timer_0 - /local/ucart/microcart1630/tasks/Quad/system/system.mhs
line 266 - Running XST synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
Running NGCBUILD ...
IPNAME:system_clock_generator_0_wrapper INSTANCE:clock_generator_0 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 43 - Running
NGCBUILD
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
Command Line: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngcbuild -p
xc7z010clg400-1 -intstyle silent -i -sd .. system_clock_generator_0_wrapper.ngc
../system_clock_generator_0_wrapper
Reading NGO file
"/local/ucart/microcart1630/tasks/Quad/system/implementation/clock_generator_0_w
rapper/system_clock_generator_0_wrapper.ngc" ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../system_clock_generator_0_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 5 sec
Total CPU time to NGCBUILD completion: 4 sec
Writing NGCBUILD log file "../system_clock_generator_0_wrapper.blc"...
NGCBUILD done.
IPNAME:system_axi_interconnect_1_wrapper INSTANCE:axi_interconnect_1 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 156 - Running
NGCBUILD
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
Command Line: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngcbuild -p
xc7z010clg400-1 -intstyle silent -i -sd .. system_axi_interconnect_1_wrapper.ngc
../system_axi_interconnect_1_wrapper
Reading NGO file
"/local/ucart/microcart1630/tasks/Quad/system/implementation/axi_interconnect_1_
wrapper/system_axi_interconnect_1_wrapper.ngc" ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../system_axi_interconnect_1_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 4 sec
Total CPU time to NGCBUILD completion: 4 sec
Writing NGCBUILD log file "../system_axi_interconnect_1_wrapper.blc"...
NGCBUILD done.
INFO:EDK:3509 - NCF files should not be modified as they will be regenerated.
If any constraint needs to be overridden, this should be done by modifying
the data/system.ucf file.
Rebuilding cache ...
Total run time: 224.00 seconds
Running synthesis...
bash -c "cd synthesis; ./synthesis.sh"
xst -ifn system_xst.scr -intstyle silent
Running XST synthesis ...
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
XST completed
*********************************************
Running Xilinx Implementation tools..
*********************************************
xflow -wd implementation -p xc7z010clg400-1 -implement xflow.opt system.ngc
Release 14.7 - Xflow P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
xflow -wd implementation -p xc7z010clg400-1 -implement xflow.opt system.ngc
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
.... Copying flowfile /opt/Xilinx/14.7/ISE_DS/ISE/xilinx/data/fpga.flw into
working directory /local/ucart/microcart1630/tasks/Quad/system/implementation
Using Flow File:
/local/ucart/microcart1630/tasks/Quad/system/implementation/fpga.flw
Using Option File(s):
/local/ucart/microcart1630/tasks/Quad/system/implementation/xflow.opt
Creating Script File ...
#----------------------------------------------#
# Starting program ngdbuild
# ngdbuild -p xc7z010clg400-1 -nt timestamp -bm system.bmm
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system.ngc" -uc
system.ucf system.ngd
#----------------------------------------------#
Release 14.7 - ngdbuild P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
Command Line: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -p
xc7z010clg400-1 -nt timestamp -bm system.bmm
/local/ucart/microcart1630/tasks/Quad/system/implementation/system.ngc -uc
system.ucf system.ngd
Reading NGO file
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system.ngc" ...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_btns_4bits_t
ri_io_wrapper.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_processing_s
ystem7_0_wrapper.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_pwm_recorder
_0_wrapper.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_pwm_recorder
_1_wrapper.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_pwm_recorder
_2_wrapper.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_pwm_recorder
_3_wrapper.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_pwm_recorder
_4_wrapper.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_pwm_recorder
_5_wrapper.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_clock_genera
tor_0_wrapper.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_axi_intercon
nect_1_wrapper.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_reset_0_wrap
per.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_pwm_signal_o
ut_wkillswitch_0_wrapper.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_pwm_signal_o
ut_wkillswitch_1_wrapper.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_pwm_signal_o
ut_wkillswitch_2_wrapper.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_pwm_signal_o
ut_wkillswitch_3_wrapper.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_axi_timer_0_
wrapper.ngc"...
Applying constraints in
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_processing_s
ystem7_0_wrapper.ncf" to module "processing_system7_0"...
Checking Constraint Associations...
Applying constraints in
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_axi_intercon
nect_1_wrapper.ncf" to module "axi_interconnect_1"...
Checking Constraint Associations...
Gathering constraint information from source properties...
Done.
INFO:NgdBuild:649 - Removing redundant 'IBUF' symbol
'processing_system7_0_PS_PORB_pin_IBUF'. All constraints associated with
this symbol will be ignored.
INFO:NgdBuild:649 - Removing redundant 'IBUF' symbol
'processing_system7_0_PS_CLK_pin_IBUF'. All constraints associated with this
symbol will be ignored.
INFO:NgdBuild:649 - Removing redundant 'IBUF' symbol
'processing_system7_0_PS_SRSTB_pin_IBUF'. All constraints associated with
this symbol will be ignored.
Annotating constraints to design from ucf file "system.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
WARNING:ConstraintSystem:135 - Constraint <INST
/system/EXPANDED/system/axi_interconnect_1/axi_interconnect_1\/si_converter_b
ank\/gen_conv_slot[0].clock_conv_inst\/interconnect_aresetn_resync<2>_inv1_IN
V_0 TNM = FFS:axi_interconnect_1_reset...>: No instances of type FFS were
found under block
"axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync<2>_inv1_INV_0" (type=INV).
WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET "processing_system7_0_PS_PORB_pin_IBUF" LOC = C7>' could not be found
and so the Locate constraint will be removed.
WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET "processing_system7_0_PS_CLK_pin_IBUF" LOC = E7>' could not be found
and so the Locate constraint will be removed.
WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET "processing_system7_0_PS_SRSTB_pin_IBUF" LOC = B10>' could not be found
and so the Locate constraint will be removed.
WARNING:ConstraintSystem:58 - Constraint <TIMEGRP
axi_interconnect_1_reset_source = FFS PADS CPUS;>: CPUS "*" does not match
any design objects.
WARNING:ConstraintSystem:194 - The TNM 'axi_interconnect_1_reset_resync', does
not directly or indirectly drive any flip-flops, latches and/or RAMs and is
not actively used by any referencing constraint.
Done...
Processing BMM file "system.bmm" ...
WARNING::53 - File 'system.bmm' is empty or has no BMM content.
Checking expanded design ...
WARNING:NgdBuild:452 - logical net 'N129' has no driver
WARNING:NgdBuild:452 - logical net 'N130' has no driver
WARNING:NgdBuild:452 - logical net 'N131' has no driver
WARNING:NgdBuild:452 - logical net 'N132' has no driver
WARNING:NgdBuild:452 - logical net 'N133' has no driver
WARNING:NgdBuild:452 - logical net 'N134' has no driver
WARNING:NgdBuild:452 - logical net 'N135' has no driver
WARNING:NgdBuild:452 - logical net 'N136' has no driver
WARNING:NgdBuild:452 - logical net 'N137' has no driver
WARNING:NgdBuild:452 - logical net 'N138' has no driver
WARNING:NgdBuild:452 - logical net 'N139' has no driver
WARNING:NgdBuild:452 - logical net 'N140' has no driver
WARNING:NgdBuild:452 - logical net 'N141' has no driver
WARNING:NgdBuild:452 - logical net 'N142' has no driver
WARNING:NgdBuild:452 - logical net 'N143' has no driver
WARNING:NgdBuild:452 - logical net 'N144' has no driver
WARNING:NgdBuild:452 - logical net 'N145' has no driver
WARNING:NgdBuild:452 - logical net 'N146' has no driver
WARNING:NgdBuild:452 - logical net 'N147' has no driver
WARNING:NgdBuild:452 - logical net 'N148' has no driver
WARNING:NgdBuild:452 - logical net 'N149' has no driver
WARNING:NgdBuild:452 - logical net 'N150' has no driver
WARNING:NgdBuild:452 - logical net 'N151' has no driver
WARNING:NgdBuild:452 - logical net 'N152' has no driver
WARNING:NgdBuild:452 - logical net 'N153' has no driver
WARNING:NgdBuild:452 - logical net 'N154' has no driver
WARNING:NgdBuild:452 - logical net 'N155' has no driver
WARNING:NgdBuild:452 - logical net 'N156' has no driver
WARNING:NgdBuild:452 - logical net 'N157' has no driver
WARNING:NgdBuild:452 - logical net 'N158' has no driver
WARNING:NgdBuild:452 - logical net 'N159' has no driver
WARNING:NgdBuild:452 - logical net 'N160' has no driver
WARNING:NgdBuild:452 - logical net 'N161' has no driver
WARNING:NgdBuild:452 - logical net 'N162' has no driver
WARNING:NgdBuild:452 - logical net 'N163' has no driver
WARNING:NgdBuild:452 - logical net 'N164' has no driver
WARNING:NgdBuild:452 - logical net 'N165' has no driver
WARNING:NgdBuild:452 - logical net 'N166' has no driver
WARNING:NgdBuild:452 - logical net 'N167' has no driver
WARNING:NgdBuild:452 - logical net 'N168' has no driver
WARNING:NgdBuild:452 - logical net 'N169' has no driver
WARNING:NgdBuild:452 - logical net 'N170' has no driver
WARNING:NgdBuild:452 - logical net 'N171' has no driver
WARNING:NgdBuild:452 - logical net 'N172' has no driver
WARNING:NgdBuild:452 - logical net 'N173' has no driver
WARNING:NgdBuild:452 - logical net 'N174' has no driver
WARNING:NgdBuild:452 - logical net 'N175' has no driver
WARNING:NgdBuild:452 - logical net 'N176' has no driver
WARNING:NgdBuild:452 - logical net 'N177' has no driver
WARNING:NgdBuild:452 - logical net 'N178' has no driver
WARNING:NgdBuild:452 - logical net 'N179' has no driver
WARNING:NgdBuild:452 - logical net 'N180' has no driver
WARNING:NgdBuild:452 - logical net 'N181' has no driver
WARNING:NgdBuild:452 - logical net 'N182' has no driver
WARNING:NgdBuild:452 - logical net 'N183' has no driver
WARNING:NgdBuild:452 - logical net 'N184' has no driver
WARNING:NgdBuild:452 - logical net 'N185' has no driver
WARNING:NgdBuild:452 - logical net 'N186' has no driver
WARNING:NgdBuild:452 - logical net 'N187' has no driver
WARNING:NgdBuild:452 - logical net 'N188' has no driver
WARNING:NgdBuild:452 - logical net 'N189' has no driver
WARNING:NgdBuild:452 - logical net 'N190' has no driver
WARNING:NgdBuild:452 - logical net 'N191' has no driver
WARNING:NgdBuild:452 - logical net 'N192' has no driver
WARNING:NgdBuild:452 - logical net 'N193' has no driver
WARNING:NgdBuild:452 - logical net 'N194' has no driver
WARNING:NgdBuild:452 - logical net 'N195' has no driver
WARNING:NgdBuild:452 - logical net 'N196' has no driver
WARNING:NgdBuild:452 - logical net 'N197' has no driver
WARNING:NgdBuild:452 - logical net 'N198' has no driver
WARNING:NgdBuild:452 - logical net 'N199' has no driver
WARNING:NgdBuild:452 - logical net 'N200' has no driver
WARNING:NgdBuild:452 - logical net 'N201' has no driver
WARNING:NgdBuild:452 - logical net 'N202' has no driver
WARNING:NgdBuild:452 - logical net 'N203' has no driver
WARNING:NgdBuild:452 - logical net 'N204' has no driver
WARNING:NgdBuild:452 - logical net 'N205' has no driver
WARNING:NgdBuild:452 - logical net 'N206' has no driver
WARNING:NgdBuild:452 - logical net 'N207' has no driver
WARNING:NgdBuild:452 - logical net 'N208' has no driver
WARNING:NgdBuild:452 - logical net 'N209' has no driver
WARNING:NgdBuild:452 - logical net 'N210' has no driver
WARNING:NgdBuild:452 - logical net 'N211' has no driver
WARNING:NgdBuild:452 - logical net 'N212' has no driver
WARNING:NgdBuild:452 - logical net 'N213' has no driver
WARNING:NgdBuild:452 - logical net 'N214' has no driver
WARNING:NgdBuild:452 - logical net 'N215' has no driver
WARNING:NgdBuild:452 - logical net 'N216' has no driver
WARNING:NgdBuild:452 - logical net 'N217' has no driver
WARNING:NgdBuild:452 - logical net 'N218' has no driver
WARNING:NgdBuild:452 - logical net 'N219' has no driver
WARNING:NgdBuild:452 - logical net 'N220' has no driver
WARNING:NgdBuild:452 - logical net 'N221' has no driver
WARNING:NgdBuild:452 - logical net 'N222' has no driver
WARNING:NgdBuild:452 - logical net 'N223' has no driver
WARNING:NgdBuild:452 - logical net 'N224' has no driver
WARNING:NgdBuild:452 - logical net 'N225' has no driver
WARNING:NgdBuild:452 - logical net 'N226' has no driver
WARNING:NgdBuild:452 - logical net 'N227' has no driver
WARNING:NgdBuild:452 - logical net 'N228' has no driver
WARNING:NgdBuild:452 - logical net 'N229' has no driver
WARNING:NgdBuild:452 - logical net 'N230' has no driver
WARNING:NgdBuild:452 - logical net 'N231' has no driver
WARNING:NgdBuild:452 - logical net 'N232' has no driver
WARNING:NgdBuild:452 - logical net 'N233' has no driver
WARNING:NgdBuild:452 - logical net 'N234' has no driver
WARNING:NgdBuild:452 - logical net 'N235' has no driver
WARNING:NgdBuild:452 - logical net 'N236' has no driver
WARNING:NgdBuild:452 - logical net 'N237' has no driver
WARNING:NgdBuild:452 - logical net 'N238' has no driver
WARNING:NgdBuild:452 - logical net 'N239' has no driver
WARNING:NgdBuild:452 - logical net 'N240' has no driver
WARNING:NgdBuild:452 - logical net 'N241' has no driver
WARNING:NgdBuild:452 - logical net 'N242' has no driver
WARNING:NgdBuild:452 - logical net 'N243' has no driver
WARNING:NgdBuild:452 - logical net 'N244' has no driver
WARNING:NgdBuild:452 - logical net 'N245' has no driver
WARNING:NgdBuild:452 - logical net 'N246' has no driver
WARNING:NgdBuild:452 - logical net 'N247' has no driver
WARNING:NgdBuild:452 - logical net 'N248' has no driver
WARNING:NgdBuild:452 - logical net 'N249' has no driver
WARNING:NgdBuild:452 - logical net 'N250' has no driver
WARNING:NgdBuild:452 - logical net 'N251' has no driver
WARNING:NgdBuild:452 - logical net 'N252' has no driver
WARNING:NgdBuild:452 - logical net 'N253' has no driver
WARNING:NgdBuild:452 - logical net 'N254' has no driver
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 132
Writing NGD file "system.ngd" ...
Total REAL time to NGDBUILD completion: 26 sec
Total CPU time to NGDBUILD completion: 26 sec
Writing NGDBUILD log file "system.bld"...
NGDBUILD done.
#----------------------------------------------#
# Starting program map
# map -o system_map.ncd -w -pr b -ol high -timing -detail system.ngd system.pcf
#----------------------------------------------#
Release 14.7 - Map P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/data/Xdh_PrimTypeLib.xda> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/data/Xdh_PrimTypeLib.xda>
Using target part "7z010clg400-1".
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set.
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
'1717@io.ece.iastate.edu:27006@io.ece.iastate.edu'.
INFO:Security:54 - 'xc7z010' is a WebPack part.
WARNING:Security:43 - No license file was found in the standard Xilinx license
directory.
WARNING:Security:44 - Since no license file was found,
please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
----------------------------------------------------------------------
WARNING:LIT:701 - PAD symbol "CLK_N" has an undefined IOSTANDARD.
WARNING:LIT:702 - PAD symbol "CLK_N" is not constrained (LOC) to a specific
location.
WARNING:LIT:701 - PAD symbol "CLK_P" has an undefined IOSTANDARD.
WARNING:LIT:702 - PAD symbol "CLK_P" is not constrained (LOC) to a specific
location.
WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_SRSTB_pin" has an
undefined IOSTANDARD.
WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_SRSTB_pin" is not
constrained (LOC) to a specific location.
WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_CLK_pin" has an undefined
IOSTANDARD.
WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_CLK_pin" is not
constrained (LOC) to a specific location.
WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_PORB_pin" has an undefined
IOSTANDARD.
WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_PORB_pin" is not
constrained (LOC) to a specific location.
Mapping design into LUTs...
WARNING:MapLib:701 - Signal CLK_P connected to top level port CLK_P has been
removed.
WARNING:MapLib:701 - Signal CLK_N connected to top level port CLK_N has been
removed.
Writing file system_map.ngm...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 31 secs
Total CPU time at the beginning of Placer: 28 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:6266348b) REAL time: 33 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:6266348b) REAL time: 33 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:6266348b) REAL time: 33 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:8ad877f8) REAL time: 38 secs
Phase 5.30 Global Clock Region Assignment
Phase 5.30 Global Clock Region Assignment (Checksum:8ad877f8) REAL time: 38 secs
Phase 6.3 Local Placement Optimization
Phase 6.3 Local Placement Optimization (Checksum:8ad877f8) REAL time: 38 secs
Phase 7.5 Local Placement Optimization
Phase 7.5 Local Placement Optimization (Checksum:8ad877f8) REAL time: 38 secs
Phase 8.8 Global Placement
...............................
.................................................................................................................................................................
..........................................................................................................................................
Phase 8.8 Global Placement (Checksum:c2ef263) REAL time: 46 secs
Phase 9.5 Local Placement Optimization
Phase 9.5 Local Placement Optimization (Checksum:c2ef263) REAL time: 46 secs
Phase 10.18 Placement Optimization
Phase 10.18 Placement Optimization (Checksum:69f76ad6) REAL time: 49 secs
Phase 11.5 Local Placement Optimization
Phase 11.5 Local Placement Optimization (Checksum:69f76ad6) REAL time: 50 secs
Phase 12.34 Placement Validation
Phase 12.34 Placement Validation (Checksum:69f76ad6) REAL time: 50 secs
Total REAL time to Placer completion: 50 secs
Total CPU time to Placer completion: 47 secs
Running post-placement packing...
Writing output files...
Design Summary:
Number of errors: 0
Number of warnings: 12
Slice Logic Utilization:
Number of Slice Registers: 2,592 out of 35,200 7%
Number used as Flip Flops: 2,336
Number used as Latches: 256
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 2,463 out of 17,600 13%
Number used as logic: 2,352 out of 17,600 13%
Number using O6 output only: 1,360
Number using O5 output only: 224
Number using O5 and O6: 768
Number used as ROM: 0
Number used as Memory: 4 out of 6,000 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 4
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 107
Number with same-slice register load: 97
Number with same-slice carry load: 5
Number with other load: 5
Slice Logic Distribution:
Number of occupied Slices: 1,050 out of 4,400 23%
Number of LUT Flip Flop pairs used: 3,371
Number with an unused Flip Flop: 1,104 out of 3,371 32%
Number with an unused LUT: 908 out of 3,371 26%
Number of fully used LUT-FF pairs: 1,359 out of 3,371 40%
Number of unique control sets: 120
Number of slice register sites lost
to control set restrictions: 484 out of 35,200 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
OVERMAPPING of BRAM resources should be ignored if the design is
over-mapped for a non-BRAM resource or if placement fails.
IO Utilization:
Number of bonded IOBs: 16 out of 100 16%
Number of LOCed IOBs: 16 out of 16 100%
Number of bonded IOPAD: 130 out of 130 100%
IOB Flip Flops: 6
Specific Feature Utilization:
Number of RAMB36E1/FIFO36E1s: 0 out of 60 0%
Number of RAMB18E1/FIFO18E1s: 0 out of 120 0%
Number of BUFG/BUFGCTRLs: 5 out of 32 15%
Number used as BUFGs: 5
Number used as BUFGCTRLs: 0
Number of IDELAYE2/IDELAYE2_FINEDELAYs: 0 out of 100 0%
Number of ILOGICE2/ILOGICE3/ISERDESE2s: 6 out of 100 6%
Number used as ILOGICE2s: 6
Number used as ILOGICE3s: 0
Number used as ISERDESE2s: 0
Number of ODELAYE2/ODELAYE2_FINEDELAYs: 0
Number of OLOGICE2/OLOGICE3/OSERDESE2s: 0 out of 100 0%
Number of PHASER_IN/PHASER_IN_PHYs: 0 out of 8 0%
Number of PHASER_OUT/PHASER_OUT_PHYs: 0 out of 8 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHCEs: 0 out of 48 0%
Number of BUFRs: 0 out of 8 0%
Number of CAPTUREs: 0 out of 1 0%
Number of DNA_PORTs: 0 out of 1 0%
Number of DSP48E1s: 0 out of 80 0%
Number of EFUSE_USRs: 0 out of 1 0%
Number of FRAME_ECCs: 0 out of 1 0%
Number of ICAPs: 0 out of 2 0%
Number of IDELAYCTRLs: 0 out of 2 0%
Number of IN_FIFOs: 0 out of 8 0%
Number of MMCME2_ADVs: 0 out of 2 0%
Number of OUT_FIFOs: 0 out of 8 0%
Number of PHASER_REFs: 0 out of 2 0%
Number of PHY_CONTROLs: 0 out of 2 0%
Number of PLLE2_ADVs: 0 out of 2 0%
Number of PS7s: 1 out of 1 100%
Number of STARTUPs: 0 out of 1 0%
Number of XADCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.45
Peak Memory Usage: 1276 MB
Total REAL time to MAP completion: 53 secs
Total CPU time to MAP completion: 50 secs
Mapping completed.
See MAP report file "system_map.mrp" for details.
#----------------------------------------------#
# Starting program par
# par -w -ol high system_map.ncd system.ncd system.pcf
#----------------------------------------------#
Release 14.7 - par P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file </opt/Xilinx/14.7/ISE_DS/EDK/data/parBmgr.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/data/parBmgr.acd>
Constraints file: system.pcf.
Loading device for application Rf_Device from file '7z010.nph' in environment
/opt/Xilinx/14.7/ISE_DS/ISE/:/opt/Xilinx/14.7/ISE_DS/EDK.
"system" is an NCD, version 3.2, device xc7z010, package clg400, speed -1
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set.
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
'1717@io.ece.iastate.edu:27006@io.ece.iastate.edu'.
INFO:Security:54 - 'xc7z010' is a WebPack part.
WARNING:Security:43 - No license file was found in the standard Xilinx license directory.
WARNING:Security:44 - Since no license file was found,
please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)
Device speed data version: "PRODUCTION 1.08 2013-10-13".
Device Utilization Summary:
Number of BUFGs 5 out of 32 15%
Number of ILOGICE2s 6 out of 100 6%
Number of External IOB33s 16 out of 100 16%
Number of LOCed IOB33s 16 out of 16 100%
Number of External IOPADs 130 out of 130 100%
Number of LOCed IOPADs 127 out of 130 97%
Number of PS7s 1 out of 1 100%
Number of Slices 1050 out of 4400 23%
Number of Slice Registers 2592 out of 35200 6%
Number used as Flip Flops 2336
Number used as Latches 256
Number used as LatchThrus 0
Number of Slice LUTS 2463 out of 17600 13%
Number of Slice LUT-Flip Flop pairs 3337 out of 17600 18%
Overall effort level (-ol): High
Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 15 secs
Finished initial Timing Analysis. REAL time: 15 secs
Starting Router
Phase 1 : 15492 unrouted; REAL time: 16 secs
Phase 2 : 11844 unrouted; REAL time: 17 secs
Phase 3 : 4168 unrouted; REAL time: 21 secs
Phase 4 : 4168 unrouted; (Setup:0, Hold:12522, Component Switching Limit:0) REAL time: 22 secs
Updating file: system.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:10927, Component Switching Limit:0) REAL time: 26 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:10927, Component Switching Limit:0) REAL time: 26 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:10927, Component Switching Limit:0) REAL time: 26 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:10927, Component Switching Limit:0) REAL time: 26 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 28 secs
Total REAL time to Router completion: 28 secs
Total CPU time to Router completion: 28 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|processing_system7_0 | | | | | |
| _FCLK_CLK0 | BUFGCTRL_X0Y0| No | 709 | 0.132 | 1.774 |
+---------------------+--------------+------+------+------------+-------------+
|pwm_signal_out_wkill | | | | | |
|switch_0/pwm_signal_ | | | | | |
|out_wkillswitch_0/US | | | | | |
|ER_LOGIC_I/PWM_Hello | | | | | |
|/counter[31]_pwm_per | | | | | |
|_t[31]_equal_9_o_BUF | | | | | |
| G |BUFGCTRL_X0Y31| No | 16 | 0.011 | 1.651 |
+---------------------+--------------+------+------+------------+-------------+
|pwm_signal_out_wkill | | | | | |
|switch_2/pwm_signal_ | | | | | |
|out_wkillswitch_2/US | | | | | |
|ER_LOGIC_I/PWM_Hello | | | | | |
|/counter[31]_pwm_per | | | | | |
|_t[31]_equal_9_o_BUF | | | | | |
| G | BUFGCTRL_X0Y2| No | 16 | 0.007 | 1.663 |
+---------------------+--------------+------+------+------------+-------------+
|pwm_signal_out_wkill | | | | | |
|switch_3/pwm_signal_ | | | | | |
|out_wkillswitch_3/US | | | | | |
|ER_LOGIC_I/PWM_Hello | | | | | |
|/counter[31]_pwm_per | | | | | |
|_t[31]_equal_9_o_BUF | | | | | |
| G | BUFGCTRL_X0Y1| No | 16 | 0.015 | 1.660 |
+---------------------+--------------+------+------+------------+-------------+
|pwm_signal_out_wkill | | | | | |
|switch_1/pwm_signal_ | | | | | |
|out_wkillswitch_1/US | | | | | |
|ER_LOGIC_I/PWM_Hello | | | | | |
|/counter[31]_pwm_per | | | | | |
|_t[31]_equal_9_o_BUF | | | | | |
| G |BUFGCTRL_X0Y30| No | 16 | 0.059 | 1.706 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_clk_fpga_0 = PERIOD TIMEGRP "clk_fpga_ | SETUP | 0.721ns| 9.279ns| 0| 0
0" 100 MHz HIGH 50% | HOLD | 0.004ns| | 0| 0
----------------------------------------------------------------------------------------------------------
PATH "TS_axi_interconnect_1_reset_resync_ | SETUP | N/A| 1.100ns| N/A| 0
path" TIG | | | | |
----------------------------------------------------------------------------------------------------------
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 29 secs
Total CPU time to PAR completion: 30 secs
Peak Memory Usage: 966 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1
Writing design to file system.ncd
PAR done!
#----------------------------------------------#
# Starting program post_par_trce
# trce -e 3 -xml system.twx system.ncd system.pcf
#----------------------------------------------#
Release 14.7 - Trace (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
Loading device for application Rf_Device from file '7z010.nph' in environment
/opt/Xilinx/14.7/ISE_DS/ISE/:/opt/Xilinx/14.7/ISE_DS/EDK.
"system" is an NCD, version 3.2, device xc7z010, package clg400, speed -1
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more
information, see the TSI report. Please consult the Xilinx Command Line
Tools User Guide for information on generating a TSI report.
--------------------------------------------------------------------------------
Release 14.7 Trace (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -e 3 -xml system.twx
system.ncd system.pcf
Design file: system.ncd
Physical constraint file: system.pcf
Device,speed: xc7z010,-1 (PRODUCTION 1.08 2013-10-13)
Report level: error report
--------------------------------------------------------------------------------
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in
the unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of
this model, and for more information on accounting for different loading conditions, please see the device datasheet.
Timing summary:
---------------
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
Constraints cover 98919 paths, 0 nets, and 11664 connections
Design statistics:
Minimum period: 9.279ns (Maximum frequency: 107.770MHz)
Analysis completed Wed Dec 30 20:41:07 2015
--------------------------------------------------------------------------------
Generating Report ...
Number of warnings: 0
Number of info messages: 4
Total time: 15 secs
xflow done!
touch __xps/system_routed
xilperl /opt/Xilinx/14.7/ISE_DS/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par
Analyzing implementation/system.par
*********************************************
Running Bitgen..
*********************************************
cd implementation ; bitgen -w -f bitgen.ut system ; cd ..
Release 14.7 - Bitgen P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
Loading device for application Rf_Device from file '7z010.nph' in environment
/opt/Xilinx/14.7/ISE_DS/ISE/:/opt/Xilinx/14.7/ISE_DS/EDK.
"system" is an NCD, version 3.2, device xc7z010, package clg400, speed -1
Opened constraints file system.pcf.
Wed Dec 30 20:41:18 2015
Running DRC.
DRC detected 0 errors and 0 warnings.
INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set.
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
'1717@io.ece.iastate.edu:27006@io.ece.iastate.edu'.
INFO:Security:54 - 'xc7z010' is a WebPack part.
WARNING:Security:43 - No license file was found in the standard Xilinx license
directory.
WARNING:Security:44 - Since no license file was found,
please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
Creating bit map...
Saving bit stream in "system.bit".
Bitstream generation is complete.
Done!
********************************************************************************
At Local date and time: Wed Dec 30 21:27:19 2015
make -f system.make netlistclean started...
rm -f implementation/system.ngc
rm -f implementation/system_clock_generator_0_wrapper.ngc implementation/system_reset_0_wrapper.ngc implementation/system_processing_system7_0_wrapper.ngc implementation/system_pwm_recorder_0_wrapper.ngc implementation/system_axi_interconnect_1_wrapper.ngc implementation/system_pwm_recorder_1_wrapper.ngc implementation/system_pwm_recorder_2_wrapper.ngc implementation/system_pwm_recorder_3_wrapper.ngc implementation/system_pwm_recorder_4_wrapper.ngc implementation/system_pwm_recorder_5_wrapper.ngc implementation/system_btns_4bits_tri_io_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_0_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_1_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_2_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_3_wrapper.ngc implementation/system_axi_timer_0_wrapper.ngc
rm -f platgen.log
rm -f __xps/ise/_xmsgs/platgen.xmsgs
rm -f implementation/system.bmm
rm -rf implementation/cache
Done!
********************************************************************************
At Local date and time: Wed Dec 30 21:27:23 2015
make -f system.make bitsclean started...
rm -f implementation/system.bit
rm -f implementation/system.ncd
rm -f implementation/system_bd.bmm
rm -f implementation/system_map.ncd
rm -f implementation/download.bit
rm -f __xps/system_bits
Done!
********************************************************************************
At Local date and time: Wed Dec 30 21:27:27 2015
make -f system.make hwclean started...
rm -f implementation/system.ngc
rm -f implementation/system_clock_generator_0_wrapper.ngc implementation/system_reset_0_wrapper.ngc implementation/system_processing_system7_0_wrapper.ngc implementation/system_pwm_recorder_0_wrapper.ngc implementation/system_axi_interconnect_1_wrapper.ngc implementation/system_pwm_recorder_1_wrapper.ngc implementation/system_pwm_recorder_2_wrapper.ngc implementation/system_pwm_recorder_3_wrapper.ngc implementation/system_pwm_recorder_4_wrapper.ngc implementation/system_pwm_recorder_5_wrapper.ngc implementation/system_btns_4bits_tri_io_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_0_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_1_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_2_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_3_wrapper.ngc implementation/system_axi_timer_0_wrapper.ngc
rm -f platgen.log
rm -f __xps/ise/_xmsgs/platgen.xmsgs
rm -f implementation/system.bmm
rm -rf implementation/cache
rm -f implementation/system.bit
rm -f implementation/system.ncd
rm -f implementation/system_bd.bmm
rm -f implementation/system_map.ncd
rm -f implementation/download.bit
rm -f __xps/system_bits
rm -rf implementation synthesis xst hdl
rm -rf xst.srp system.srp
rm -f __xps/ise/_xmsgs/bitinit.xmsgs
rm -rf __xps/ps7_instance.mhs
Done!
********************************************************************************
At Local date and time: Wed Dec 30 21:27:37 2015
make -f system.make exporttosdk started...
****************************************************
Creating system netlist for hardware specification..
****************************************************
platgen -p xc7z010clg400-1 -lang vhdl -intstyle default -msg __xps/ise/xmsgprops.lst system.mhs
Release 14.7 - platgen Xilinx EDK 14.7 Build EDK_P.20131013
(lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Command Line: platgen -p xc7z010clg400-1 -lang vhdl -intstyle default -msg
__xps/ise/xmsgprops.lst system.mhs
WARNING:EDK - INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable
is not set.
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
'1717@io.ece.iastate.edu:27006@io.ece.iastate.edu'.
INFO:Security:71 - If a license for part 'xc7z010' is available, it will be
possible to use 'XPS_TDP' instead of 'XPS'.
WARNING:Security:43 - No license file was found in the standard Xilinx
license directory.
WARNING:Security:44 - Since no license file was found,
please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
WARNING:Security:42 - Your software subscription period has lapsed. Your
current version of Xilinx tools will continue to function, but you no longer
qualify for Xilinx software updates or new releases.
Parse /local/ucart/microcart1630/tasks/Quad/system/system.mhs ...
Read MPD definitions ...
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 43
Overriding IP level properties ...
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_PACKAGE_NAME value to clg400 -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 185
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_S_AXI_HP0_HIGHADDR value to 0x1FFFFFFF -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 300
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_S_AXI_HP1_HIGHADDR value to 0x1FFFFFFF -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 304
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_S_AXI_HP2_HIGHADDR value to 0x1FFFFFFF -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 308
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_S_AXI_HP3_HIGHADDR value to 0x1FFFFFFF -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 312
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_NUM_F2P_INTR_INPUTS value to 1 -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 319
INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is
overriding PARAMETER C_BASEFAMILY value to zynq -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v
1_06_a/data/axi_interconnect_v2_1_0.mpd line 81
Computing clock values...
INFO:EDK:1432 - Frequency for Top-Level Input Clock
'processing_system7_0_PS_CLK_pin' is not specified. Clock DRCs will not be
performed for IPs connected to that clock port, unless they are connected
through the clock generator IP.
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
INFO:EDK - INFO: DDR Base and High address in current configuration is
0x00000000 and 0x1FFFFFFF respectively.
INFO:EDK - INFO: You can modify the DDR address range accessed by Programmable
Logic through the processing_system7 AXI slave interfaces. If MicroBlaze is a
master on processing_system7 AXI slave interfaces, please use the top half of
the address range (Base Address = 0x10000000; High Address = 0x1FFFFFFF). For
all other master, any subset of the DDR address can be used. See Xilinx
Answer 47167 for more information.
Address Map for Processor processing_system7_0
(0x41200000-0x4120ffff) BTNs_4Bits_TRI_IO axi_interconnect_1
(0x42800000-0x4280ffff) axi_timer_0 axi_interconnect_1
(0x76e00000-0x76e0ffff) pwm_recorder_0 axi_interconnect_1
(0x76e20000-0x76e2ffff) pwm_recorder_1 axi_interconnect_1
(0x76e40000-0x76e4ffff) pwm_recorder_2 axi_interconnect_1
(0x76e60000-0x76e6ffff) pwm_recorder_3 axi_interconnect_1
(0x76e80000-0x76e8ffff) pwm_recorder_4 axi_interconnect_1
(0x76ea0000-0x76eaffff) pwm_recorder_5 axi_interconnect_1
(0x79400000-0x7940ffff) pwm_signal_out_wkillswitch_0 axi_interconnect_1
(0x79420000-0x7942ffff) pwm_signal_out_wkillswitch_1 axi_interconnect_1
(0x79440000-0x7944ffff) pwm_signal_out_wkillswitch_2 axi_interconnect_1
(0x79460000-0x7946ffff) pwm_signal_out_wkillswitch_3 axi_interconnect_1
Checking platform address map ...
Checking platform configuration ...
IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - 1 master(s) : 12
slave(s)
Checking port drivers...
Performing Clock DRCs...
Performing Reset DRCs...
Overriding system level properties...
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_FCLK_CLK1_BUF value to FALSE -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 351
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_FCLK_CLK2_BUF value to FALSE -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 352
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_FCLK_CLK3_BUF value to FALSE -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 353
INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi_interconnect_1.
INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is
overriding PARAMETER C_RANGE_CHECK value to 1 -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v
1_06_a/data/axi_interconnect_v2_1_0.mpd line 149
Running system level update procedures...
Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
ZynqConfig: Terminated for tcl mode
Running system level DRCs...
Performing System level DRCs on properties...
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
ZynqConfig: Terminated for tcl mode
Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
ZynqConfig: Terminated for tcl mode
INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_1.
Modify defaults ...
Creating stub ...
Processing licensed instances ...
Completion time: 0.00 seconds
Creating hardware output directories ...
Managing hardware (BBD-specified) netlist files ...
Managing cache ...
Elaborating instances ...
IPNAME:clock_generator INSTANCE:clock_generator_0 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 43 - elaborating IP
ClkGen elaborate status: PASSED
----------------------------------------
----------------------------------------
Writing HDL for elaborated instances ...
Inserting wrapper level ...
Completion time: 0.00 seconds
Constructing platform-level connectivity ...
Completion time: 0.00 seconds
Writing (top-level) BMM ...
Writing (top-level and wrappers) HDL ...
Generating synthesis project file ...
Running XST synthesis ...
INFO:EDK:4211 - The following instances are synthesized with XST. The MPD option
IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
INSTANCE:clock_generator_0 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 43 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
Trying to terminate Process...
make: *** Deleting file `implementation/system.bmm'
make: *** [implementation/system.bmm] Terminated
Done!
Overriding Xilinx file <TextEditor.cfg> with local file </opt/Xilinx/14.7/ISE_DS/EDK/data/TextEditor.cfg>
Address Map for Processor processing_system7_0
(0x41200000-0x4120ffff) BTNs_4Bits_TRI_IO axi_interconnect_1
(0x42800000-0x4280ffff) axi_timer_0 axi_interconnect_1
(0x76e00000-0x76e0ffff) pwm_recorder_5 axi_interconnect_1
(0x76e20000-0x76e2ffff) pwm_recorder_4 axi_interconnect_1
(0x76e40000-0x76e4ffff) pwm_recorder_3 axi_interconnect_1
(0x76e60000-0x76e6ffff) pwm_recorder_2 axi_interconnect_1
(0x76e80000-0x76e8ffff) pwm_recorder_1 axi_interconnect_1
(0x76ea0000-0x76eaffff) pwm_recorder_0 axi_interconnect_1
(0x79400000-0x7940ffff) pwm_signal_out_wkillswitch_3 axi_interconnect_1
(0x79420000-0x7942ffff) pwm_signal_out_wkillswitch_2 axi_interconnect_1
(0x79440000-0x7944ffff) pwm_signal_out_wkillswitch_1 axi_interconnect_1
(0x79460000-0x7946ffff) pwm_signal_out_wkillswitch_0 axi_interconnect_1
Generated Addresses Successfully
********************************************************************************
At Local date and time: Wed Dec 30 21:28:45 2015
make -f system.make netlistclean started...
rm -f implementation/system.ngc
rm -f implementation/system_clock_generator_0_wrapper.ngc implementation/system_reset_0_wrapper.ngc implementation/system_processing_system7_0_wrapper.ngc implementation/system_pwm_recorder_0_wrapper.ngc implementation/system_axi_interconnect_1_wrapper.ngc implementation/system_pwm_recorder_1_wrapper.ngc implementation/system_pwm_recorder_2_wrapper.ngc implementation/system_pwm_recorder_3_wrapper.ngc implementation/system_pwm_recorder_4_wrapper.ngc implementation/system_pwm_recorder_5_wrapper.ngc implementation/system_btns_4bits_tri_io_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_0_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_1_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_2_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_3_wrapper.ngc implementation/system_axi_timer_0_wrapper.ngc
rm -f platgen.log
rm -f __xps/ise/_xmsgs/platgen.xmsgs
rm -f implementation/system.bmm
rm -rf implementation/cache
Done!
********************************************************************************
At Local date and time: Wed Dec 30 21:28:53 2015
make -f system.make clean started...
rm -f implementation/system.ngc
rm -f implementation/system_clock_generator_0_wrapper.ngc implementation/system_reset_0_wrapper.ngc implementation/system_processing_system7_0_wrapper.ngc implementation/system_pwm_recorder_0_wrapper.ngc implementation/system_axi_interconnect_1_wrapper.ngc implementation/system_pwm_recorder_1_wrapper.ngc implementation/system_pwm_recorder_2_wrapper.ngc implementation/system_pwm_recorder_3_wrapper.ngc implementation/system_pwm_recorder_4_wrapper.ngc implementation/system_pwm_recorder_5_wrapper.ngc implementation/system_btns_4bits_tri_io_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_0_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_1_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_2_wrapper.ngc implementation/system_pwm_signal_out_wkillswitch_3_wrapper.ngc implementation/system_axi_timer_0_wrapper.ngc
rm -f platgen.log
rm -f __xps/ise/_xmsgs/platgen.xmsgs
rm -f implementation/system.bmm
rm -rf implementation/cache
rm -f implementation/system.bit
rm -f implementation/system.ncd
rm -f implementation/system_bd.bmm
rm -f implementation/system_map.ncd
rm -f implementation/download.bit
rm -f __xps/system_bits
rm -rf implementation synthesis xst hdl
rm -rf xst.srp system.srp
rm -f __xps/ise/_xmsgs/bitinit.xmsgs
rm -rf __xps/ps7_instance.mhs
rm -rf simulation/behavioral
rm -f simgen.log
rm -f __xps/ise/_xmsgs/simgen.xmsgs
rm -f _impact.cmd
Done!
********************************************************************************
At Local date and time: Wed Dec 30 21:29:01 2015
make -f system.make exporttosdk started...
pscgen -mhs system.mhs -expdir SDK/SDK_Export/hw
Generating ps7_init code for Si version 1....
Generating ps7_init code for Si version 2....
Generating ps7_init code for Si version 3....
psf2Edward -inp system.xmp -flat_zynq -dont_run_checkhwsys -dont_add_loginfo -make_inst_lower -edwver 1.2 -xml SDK/SDK_Export/hw/system.xml
Release 14.7 - psf2Edward EDK_P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 43
WARNING:EDK -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_i2c_v1_0
0_a/data/ps7_i2c_v2_1_0.mpd line 108 Unknown PORT subproperty IIC Serial Data
WARNING:EDK -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_i2c_v1_0
0_a/data/ps7_i2c_v2_1_0.mpd line 109 Unknown PORT subproperty IIC Serial
Clock
WARNING:EDK:2486 - The bitwidth 52 of new value 0xc00000000f281 is greater than
32
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_BASE_ID -
Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 19
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_IS_ACLK_ASYNC - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 20
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_ACLK_RATIO
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 21
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_ARB_PRIORITY - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 22
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AW_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 23
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AR_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 24
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_W_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 25
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_R_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 26
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_B_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 27
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_WRITE_FIFO_DEPTH - Failure in evaluting ISVALID
expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 28
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_READ_FIFO_DEPTH - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 29
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_WRITE_ISSUING - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 30
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_READ_ISSUING - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 31
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ACLK - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 119
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARESETN - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 120
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 121
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWADDR - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 122
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLEN - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 123
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWSIZE - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 124
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWBURST - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 125
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWCACHE - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 126
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWPROT - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 127
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLOCK - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 128
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 129
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 130
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WDATA - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 131
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WSTRB - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 132
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WLAST - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 133
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 134
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 135
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BID - Failure in evaluting
ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 136
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BRESP - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 137
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 138
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 139
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 140
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARADDR - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 141
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLEN - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 142
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARSIZE - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 143
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARBURST - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 144
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARCACHE - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 145
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARPROT - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 146
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLOCK - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 147
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 148
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 149
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RID - Failure in evaluting
ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 150
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RDATA - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 151
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RRESP - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 152
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RLAST - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 153
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 154
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 155
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI - Failure in evaluting
ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 73
WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_I - Failure in evaluting
ISVALID expresion "(C_USE_STARTUP==0)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_qspi_v1_
00_a/data/ps7_qspi_v2_1_0.mpd line 102
WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_O - Failure in evaluting
ISVALID expresion "(C_USE_STARTUP==0)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_qspi_v1_
00_a/data/ps7_qspi_v2_1_0.mpd line 103
WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_T - Failure in evaluting
ISVALID expresion "(C_USE_STARTUP==0)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_qspi_v1_
00_a/data/ps7_qspi_v2_1_0.mpd line 104
WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK - Failure in evaluting
ISVALID expresion "(C_USE_STARTUP==0)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_qspi_v1_
00_a/data/ps7_qspi_v2_1_0.mpd line 122
Overriding IP level properties ...
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_BASE_ID -
Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 19
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_IS_ACLK_ASYNC - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 20
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_ACLK_RATIO
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 21
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_ARB_PRIORITY - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 22
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AW_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 23
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AR_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 24
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_W_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 25
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_R_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 26
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_B_REGISTER
- Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 27
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_WRITE_FIFO_DEPTH - Failure in evaluting ISVALID
expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 28
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_READ_FIFO_DEPTH - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 29
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_WRITE_ISSUING - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 30
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:
C_INTERCONNECT_M_AXI_READ_ISSUING - Failure in evaluting ISVALID expresion
"(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/EDK/data/coremodel/axi/data/tools_axi_v1_01_a.txt
line 31
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ACLK - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 119
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARESETN - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 120
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 121
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWADDR - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 122
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLEN - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 123
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWSIZE - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 124
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWBURST - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 125
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWCACHE - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 126
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWPROT - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 127
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLOCK - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 128
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 129
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 130
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WDATA - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 131
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WSTRB - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 132
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WLAST - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 133
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 134
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 135
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BID - Failure in evaluting
ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 136
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BRESP - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 137
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 138
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 139
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 140
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARADDR - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 141
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLEN - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 142
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARSIZE - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 143
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARBURST - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 144
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARCACHE - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 145
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARPROT - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 146
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLOCK - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 147
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 148
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 149
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RID - Failure in evaluting
ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 150
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RDATA - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 151
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RRESP - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 152
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RLAST - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 153
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RVALID - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 154
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RREADY - Failure in
evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 155
WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI - Failure in evaluting
ISVALID expresion "(C_INCLUDE_DMA == 1)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_usb_v1_0
0_a/data/ps7_usb_v2_1_0.mpd line 73
WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_I - Failure in evaluting
ISVALID expresion "(C_USE_STARTUP==0)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_qspi_v1_
00_a/data/ps7_qspi_v2_1_0.mpd line 102
WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_O - Failure in evaluting
ISVALID expresion "(C_USE_STARTUP==0)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_qspi_v1_
00_a/data/ps7_qspi_v2_1_0.mpd line 103
WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_T - Failure in evaluting
ISVALID expresion "(C_USE_STARTUP==0)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_qspi_v1_
00_a/data/ps7_qspi_v2_1_0.mpd line 104
WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK - Failure in evaluting
ISVALID expresion "(C_USE_STARTUP==0)" -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_qspi_v1_
00_a/data/ps7_qspi_v2_1_0.mpd line 122
Computing clock values...
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Address Map for Processor ps7_cortexa9_0
(0000000000-0x0002ffff) ps7_ram_0 ps7_axi_interconnect_0
(0x00100000-0x1fffffff) ps7_ddr_0 ps7_axi_interconnect_0
(0x41200000-0x4120ffff)
BTNs_4Bits_TRI_IO ps7_axi_interconnect_0->axi_interconnect_1
(0x42800000-0x4280ffff) axi_timer_0 ps7_axi_interconnect_0->axi_interconnect_1
(0x76e00000-0x76e0ffff)
pwm_recorder_5 ps7_axi_interconnect_0->axi_interconnect_1
(0x76e20000-0x76e2ffff)
pwm_recorder_4 ps7_axi_interconnect_0->axi_interconnect_1
(0x76e40000-0x76e4ffff)
pwm_recorder_3 ps7_axi_interconnect_0->axi_interconnect_1
(0x76e60000-0x76e6ffff)
pwm_recorder_2 ps7_axi_interconnect_0->axi_interconnect_1
(0x76e80000-0x76e8ffff)
pwm_recorder_1 ps7_axi_interconnect_0->axi_interconnect_1
(0x76ea0000-0x76eaffff)
pwm_recorder_0 ps7_axi_interconnect_0->axi_interconnect_1
(0x79400000-0x7940ffff)
pwm_signal_out_wkillswitch_3 ps7_axi_interconnect_0->axi_interconnect_1
(0x79420000-0x7942ffff)
pwm_signal_out_wkillswitch_2 ps7_axi_interconnect_0->axi_interconnect_1
(0x79440000-0x7944ffff)
pwm_signal_out_wkillswitch_1 ps7_axi_interconnect_0->axi_interconnect_1
(0x79460000-0x7946ffff)
pwm_signal_out_wkillswitch_0 ps7_axi_interconnect_0->axi_interconnect_1
(0xe0000000-0xe0000fff) ps7_uart_0 ps7_axi_interconnect_0
(0xe0001000-0xe0001fff) ps7_uart_1 ps7_axi_interconnect_0
(0xe0002000-0xe0002fff) ps7_usb_0 ps7_axi_interconnect_0
(0xe0004000-0xe0004fff) ps7_i2c_0 ps7_axi_interconnect_0
(0xe000a000-0xe000afff) ps7_gpio_0 ps7_axi_interconnect_0
(0xe000b000-0xe000bfff) ps7_ethernet_0 ps7_axi_interconnect_0
(0xe000d000-0xe000dfff) ps7_qspi_0 ps7_axi_interconnect_0
(0xe0100000-0xe0100fff) ps7_sd_0 ps7_axi_interconnect_0
(0xe0200000-0xe0200fff) ps7_iop_bus_config_0 ps7_axi_interconnect_0
(0xf8000000-0xf8000fff) ps7_slcr_0 ps7_axi_interconnect_0
(0xf8003000-0xf8003fff) ps7_dma_s ps7_axi_interconnect_0
(0xf8004000-0xf8004fff) ps7_dma_ns ps7_axi_interconnect_0
(0xf8006000-0xf8006fff) ps7_ddrc_0 ps7_axi_interconnect_0
(0xf8007000-0xf80070ff) ps7_dev_cfg_0 ps7_axi_interconnect_0
(0xf8007100-0xf8007120) ps7_xadc_0 ps7_axi_interconnect_0
(0xf8008000-0xf8008fff) ps7_afi_0 ps7_axi_interconnect_0
(0xf8009000-0xf8009fff) ps7_afi_1 ps7_axi_interconnect_0
(0xf800a000-0xf800afff) ps7_afi_2 ps7_axi_interconnect_0
(0xf800b000-0xf800bfff) ps7_afi_3 ps7_axi_interconnect_0
(0xf800c000-0xf800cfff) ps7_ocmc_0 ps7_axi_interconnect_0
(0xf8800000-0xf88fffff) ps7_coresight_comp_0 ps7_axi_interconnect_0
(0xf8900000-0xf89fffff) ps7_gpv_0 ps7_axi_interconnect_0
(0xf8f00000-0xf8f000fc) ps7_scuc_0 ps7_axi_interconnect_0
(0xf8f00100-0xf8f001ff) ps7_scugic_0 ps7_axi_interconnect_0
(0xf8f00200-0xf8f002ff) ps7_globaltimer_0 ps7_axi_interconnect_0
(0xf8f00600-0xf8f0061f) ps7_scutimer_0 ps7_axi_interconnect_0
(0xf8f00620-0xf8f006ff) ps7_scuwdt_0 ps7_axi_interconnect_0
(0xf8f01000-0xf8f01fff) ps7_intc_dist_0 ps7_axi_interconnect_0
(0xf8f02000-0xf8f02fff) ps7_l2cachec_0 ps7_axi_interconnect_0
(0xfc000000-0xfcffffff) ps7_qspi_linear_0 ps7_axi_interconnect_0
(0xffff0000-0xfffffdff) ps7_ram_1 ps7_axi_interconnect_0
Address Map for Processor ps7_cortexa9_1
(0000000000-0x0002ffff) ps7_ram_0 ps7_axi_interconnect_0
(0x00100000-0x1fffffff) ps7_ddr_0 ps7_axi_interconnect_0
(0x41200000-0x4120ffff)
BTNs_4Bits_TRI_IO ps7_axi_interconnect_0->axi_interconnect_1
(0x42800000-0x4280ffff) axi_timer_0 ps7_axi_interconnect_0->axi_interconnect_1
(0x76e00000-0x76e0ffff)
pwm_recorder_5 ps7_axi_interconnect_0->axi_interconnect_1
(0x76e20000-0x76e2ffff)
pwm_recorder_4 ps7_axi_interconnect_0->axi_interconnect_1
(0x76e40000-0x76e4ffff)
pwm_recorder_3 ps7_axi_interconnect_0->axi_interconnect_1
(0x76e60000-0x76e6ffff)
pwm_recorder_2 ps7_axi_interconnect_0->axi_interconnect_1
(0x76e80000-0x76e8ffff)
pwm_recorder_1 ps7_axi_interconnect_0->axi_interconnect_1
(0x76ea0000-0x76eaffff)
pwm_recorder_0 ps7_axi_interconnect_0->axi_interconnect_1
(0x79400000-0x7940ffff)
pwm_signal_out_wkillswitch_3 ps7_axi_interconnect_0->axi_interconnect_1
(0x79420000-0x7942ffff)
pwm_signal_out_wkillswitch_2 ps7_axi_interconnect_0->axi_interconnect_1
(0x79440000-0x7944ffff)
pwm_signal_out_wkillswitch_1 ps7_axi_interconnect_0->axi_interconnect_1
(0x79460000-0x7946ffff)
pwm_signal_out_wkillswitch_0 ps7_axi_interconnect_0->axi_interconnect_1
(0xe0000000-0xe0000fff) ps7_uart_0 ps7_axi_interconnect_0
(0xe0001000-0xe0001fff) ps7_uart_1 ps7_axi_interconnect_0
(0xe0002000-0xe0002fff) ps7_usb_0 ps7_axi_interconnect_0
(0xe0004000-0xe0004fff) ps7_i2c_0 ps7_axi_interconnect_0
(0xe000a000-0xe000afff) ps7_gpio_0 ps7_axi_interconnect_0
(0xe000b000-0xe000bfff) ps7_ethernet_0 ps7_axi_interconnect_0
(0xe000d000-0xe000dfff) ps7_qspi_0 ps7_axi_interconnect_0
(0xe0100000-0xe0100fff) ps7_sd_0 ps7_axi_interconnect_0
(0xe0200000-0xe0200fff) ps7_iop_bus_config_0 ps7_axi_interconnect_0
(0xf8000000-0xf8000fff) ps7_slcr_0 ps7_axi_interconnect_0
(0xf8003000-0xf8003fff) ps7_dma_s ps7_axi_interconnect_0
(0xf8004000-0xf8004fff) ps7_dma_ns ps7_axi_interconnect_0
(0xf8006000-0xf8006fff) ps7_ddrc_0 ps7_axi_interconnect_0
(0xf8007000-0xf80070ff) ps7_dev_cfg_0 ps7_axi_interconnect_0
(0xf8007100-0xf8007120) ps7_xadc_0 ps7_axi_interconnect_0
(0xf8008000-0xf8008fff) ps7_afi_0 ps7_axi_interconnect_0
(0xf8009000-0xf8009fff) ps7_afi_1 ps7_axi_interconnect_0
(0xf800a000-0xf800afff) ps7_afi_2 ps7_axi_interconnect_0
(0xf800b000-0xf800bfff) ps7_afi_3 ps7_axi_interconnect_0
(0xf800c000-0xf800cfff) ps7_ocmc_0 ps7_axi_interconnect_0
(0xf8800000-0xf88fffff) ps7_coresight_comp_0 ps7_axi_interconnect_0
(0xf8900000-0xf89fffff) ps7_gpv_0 ps7_axi_interconnect_0
(0xf8f00000-0xf8f000fc) ps7_scuc_0 ps7_axi_interconnect_0
(0xf8f00100-0xf8f001ff) ps7_scugic_0 ps7_axi_interconnect_0
(0xf8f00200-0xf8f002ff) ps7_globaltimer_0 ps7_axi_interconnect_0
(0xf8f00600-0xf8f0061f) ps7_scutimer_0 ps7_axi_interconnect_0
(0xf8f00620-0xf8f006ff) ps7_scuwdt_0 ps7_axi_interconnect_0
(0xf8f01000-0xf8f01fff) ps7_intc_dist_0 ps7_axi_interconnect_0
(0xf8f02000-0xf8f02fff) ps7_l2cachec_0 ps7_axi_interconnect_0
(0xfc000000-0xfcffffff) ps7_qspi_linear_0 ps7_axi_interconnect_0
(0xffff0000-0xfffffdff) ps7_ram_1 ps7_axi_interconnect_0
Checking platform address map ...
WARNING:EDK -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_i2c_v1_0
0_a/data/ps7_i2c_v2_1_0.mpd line 108 Unknown PORT subproperty IIC Serial Data
WARNING:EDK -
/opt/Xilinx/14.7/ISE_DS/ISE/data/zynqconfig/ps7_internals/pcores/ps7_i2c_v1_0
0_a/data/ps7_i2c_v2_1_0.mpd line 109 Unknown PORT subproperty IIC Serial
Clock
Conversion to XML complete.
xdsgen -inp system.xmp -report SDK/SDK_Export/hw/system.html -make_docs_local
Release 14.7 - xdsgen EDK_P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 43
WARNING:EDK:878 - Could not find IP doc
http://www.xilinx.com/cgi-bin/docs/ipdoc?c=clock_generator;v=v4_03_a;d=clock_
generator.pdf
WARNING:EDK:878 - Could not find IP doc
http://www.xilinx.com/cgi-bin/docs/ipdoc?c=proc_sys_reset;v=v3_00_a;d=proc_sy
s_reset.pdf
WARNING:EDK:878 - Could not find IP doc
http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v1_06_a;d=ds768
_axi_interconnect.pdf
WARNING:EDK:878 - Could not find IP doc
http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_gpio;v=v1_01_b;d=ds744_axi_gpi
o.pdf
WARNING:EDK:878 - Could not find IP doc
http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_timer;v=v1_03_a;d=axi_timer_ds
764.pdf
Generated Block Diagram.
Rasterizing clock_generator_0.jpg.....
Rasterizing reset_0.jpg.....
Rasterizing processing_system7_0.jpg.....
Rasterizing pwm_recorder_0.jpg.....
Rasterizing axi_interconnect_1.jpg.....
Rasterizing pwm_recorder_1.jpg.....
Rasterizing pwm_recorder_2.jpg.....
Rasterizing pwm_recorder_3.jpg.....
Rasterizing pwm_recorder_4.jpg.....
Rasterizing pwm_recorder_5.jpg.....
Rasterizing BTNs_4Bits_TRI_IO.jpg.....
Rasterizing pwm_signal_out_wkillswitch_0.jpg.....
Rasterizing pwm_signal_out_wkillswitch_1.jpg.....
Rasterizing pwm_signal_out_wkillswitch_2.jpg.....
Rasterizing pwm_signal_out_wkillswitch_3.jpg.....
Rasterizing axi_timer_0.jpg.....
Rasterizing system_blkd.jpg.....
Report generated.
Report generation completed.
****************************************************
Creating system netlist for hardware specification..
****************************************************
platgen -p xc7z010clg400-1 -lang vhdl -intstyle default -msg __xps/ise/xmsgprops.lst system.mhs
Release 14.7 - platgen Xilinx EDK 14.7 Build EDK_P.20131013
(lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Command Line: platgen -p xc7z010clg400-1 -lang vhdl -intstyle default -msg
__xps/ise/xmsgprops.lst system.mhs
WARNING:EDK - INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable
is not set.
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
'1717@io.ece.iastate.edu:27006@io.ece.iastate.edu'.
INFO:Security:71 - If a license for part 'xc7z010' is available, it will be
possible to use 'XPS_TDP' instead of 'XPS'.
WARNING:Security:43 - No license file was found in the standard Xilinx
license directory.
WARNING:Security:44 - Since no license file was found,
please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
WARNING:Security:42 - Your software subscription period has lapsed. Your
current version of Xilinx tools will continue to function, but you no longer
qualify for Xilinx software updates or new releases.
Parse /local/ucart/microcart1630/tasks/Quad/system/system.mhs ...
Read MPD definitions ...
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 43
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 43
Overriding IP level properties ...
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_PACKAGE_NAME value to clg400 -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 185
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_S_AXI_HP0_HIGHADDR value to 0x1FFFFFFF -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 300
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_S_AXI_HP1_HIGHADDR value to 0x1FFFFFFF -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 304
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_S_AXI_HP2_HIGHADDR value to 0x1FFFFFFF -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 308
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_S_AXI_HP3_HIGHADDR value to 0x1FFFFFFF -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 312
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_NUM_F2P_INTR_INPUTS value to 1 -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 319
INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is
overriding PARAMETER C_BASEFAMILY value to zynq -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v
1_06_a/data/axi_interconnect_v2_1_0.mpd line 81
Computing clock values...
INFO:EDK:1432 - Frequency for Top-Level Input Clock
'processing_system7_0_PS_CLK_pin' is not specified. Clock DRCs will not be
performed for IPs connected to that clock port, unless they are connected
through the clock generator IP.
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
INFO:EDK - INFO: DDR Base and High address in current configuration is
0x00000000 and 0x1FFFFFFF respectively.
INFO:EDK - INFO: You can modify the DDR address range accessed by Programmable
Logic through the processing_system7 AXI slave interfaces. If MicroBlaze is a
master on processing_system7 AXI slave interfaces, please use the top half of
the address range (Base Address = 0x10000000; High Address = 0x1FFFFFFF). For
all other master, any subset of the DDR address can be used. See Xilinx
Answer 47167 for more information.
Address Map for Processor processing_system7_0
(0x41200000-0x4120ffff) BTNs_4Bits_TRI_IO axi_interconnect_1
(0x42800000-0x4280ffff) axi_timer_0 axi_interconnect_1
(0x76e00000-0x76e0ffff) pwm_recorder_5 axi_interconnect_1
(0x76e20000-0x76e2ffff) pwm_recorder_4 axi_interconnect_1
(0x76e40000-0x76e4ffff) pwm_recorder_3 axi_interconnect_1
(0x76e60000-0x76e6ffff) pwm_recorder_2 axi_interconnect_1
(0x76e80000-0x76e8ffff) pwm_recorder_1 axi_interconnect_1
(0x76ea0000-0x76eaffff) pwm_recorder_0 axi_interconnect_1
(0x79400000-0x7940ffff) pwm_signal_out_wkillswitch_3 axi_interconnect_1
(0x79420000-0x7942ffff) pwm_signal_out_wkillswitch_2 axi_interconnect_1
(0x79440000-0x7944ffff) pwm_signal_out_wkillswitch_1 axi_interconnect_1
(0x79460000-0x7946ffff) pwm_signal_out_wkillswitch_0 axi_interconnect_1
Checking platform address map ...
Checking platform configuration ...
IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - 1 master(s) : 12
slave(s)
Checking port drivers...
Performing Clock DRCs...
Performing Reset DRCs...
Overriding system level properties...
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_FCLK_CLK1_BUF value to FALSE -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 351
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_FCLK_CLK2_BUF value to FALSE -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 352
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_FCLK_CLK3_BUF value to FALSE -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7
_v4_03_a/data/processing_system7_v2_1_0.mpd line 353
INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi_interconnect_1.
INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is
overriding PARAMETER C_RANGE_CHECK value to 1 -
/opt/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v
1_06_a/data/axi_interconnect_v2_1_0.mpd line 149
Running system level update procedures...
Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
ZynqConfig: Terminated for tcl mode
Running system level DRCs...
Performing System level DRCs on properties...
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
ZynqConfig: Terminated for tcl mode
Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
ZynqConfig: Terminated for tcl mode
INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_1.
Modify defaults ...
Creating stub ...
Processing licensed instances ...
Completion time: 0.00 seconds
Creating hardware output directories ...
Managing hardware (BBD-specified) netlist files ...
Managing cache ...
Elaborating instances ...
IPNAME:clock_generator INSTANCE:clock_generator_0 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 43 - elaborating IP
ClkGen elaborate status: PASSED
----------------------------------------
----------------------------------------
Writing HDL for elaborated instances ...
Inserting wrapper level ...
Completion time: 0.00 seconds
Constructing platform-level connectivity ...
Completion time: 0.00 seconds
Writing (top-level) BMM ...
Writing (top-level and wrappers) HDL ...
Generating synthesis project file ...
Running XST synthesis ...
INFO:EDK:4211 - The following instances are synthesized with XST. The MPD option
IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
INSTANCE:clock_generator_0 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 43 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:reset_0 - /local/ucart/microcart1630/tasks/Quad/system/system.mhs line
50 - Running XST synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:processing_system7_0 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 56 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_recorder_0 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 146 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:axi_interconnect_1 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 156 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_recorder_1 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 164 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_recorder_2 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 174 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_recorder_3 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 184 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_recorder_4 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 194 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_recorder_5 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 204 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:btns_4bits_tri_io -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 214 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_signal_out_wkillswitch_0 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 226 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_signal_out_wkillswitch_1 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 236 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_signal_out_wkillswitch_2 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 246 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:pwm_signal_out_wkillswitch_3 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 256 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
INSTANCE:axi_timer_0 - /local/ucart/microcart1630/tasks/Quad/system/system.mhs
line 266 - Running XST synthesis
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
Running NGCBUILD ...
IPNAME:system_clock_generator_0_wrapper INSTANCE:clock_generator_0 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 43 - Running
NGCBUILD
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
Command Line: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngcbuild -p
xc7z010clg400-1 -intstyle silent -i -sd .. system_clock_generator_0_wrapper.ngc
../system_clock_generator_0_wrapper
Reading NGO file
"/local/ucart/microcart1630/tasks/Quad/system/implementation/clock_generator_0_w
rapper/system_clock_generator_0_wrapper.ngc" ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../system_clock_generator_0_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 4 sec
Total CPU time to NGCBUILD completion: 4 sec
Writing NGCBUILD log file "../system_clock_generator_0_wrapper.blc"...
NGCBUILD done.
IPNAME:system_axi_interconnect_1_wrapper INSTANCE:axi_interconnect_1 -
/local/ucart/microcart1630/tasks/Quad/system/system.mhs line 156 - Running
NGCBUILD
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
Command Line: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngcbuild -p
xc7z010clg400-1 -intstyle silent -i -sd .. system_axi_interconnect_1_wrapper.ngc
../system_axi_interconnect_1_wrapper
Reading NGO file
"/local/ucart/microcart1630/tasks/Quad/system/implementation/axi_interconnect_1_
wrapper/system_axi_interconnect_1_wrapper.ngc" ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../system_axi_interconnect_1_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 4 sec
Total CPU time to NGCBUILD completion: 4 sec
Writing NGCBUILD log file "../system_axi_interconnect_1_wrapper.blc"...
NGCBUILD done.
INFO:EDK:3509 - NCF files should not be modified as they will be regenerated.
If any constraint needs to be overridden, this should be done by modifying
the data/system.ucf file.
Rebuilding cache ...
Total run time: 218.00 seconds
Running synthesis...
bash -c "cd synthesis; ./synthesis.sh"
xst -ifn system_xst.scr -intstyle silent
Running XST synthesis ...
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
XST completed
*********************************************
Running Xilinx Implementation tools..
*********************************************
xflow -wd implementation -p xc7z010clg400-1 -implement xflow.opt system.ngc
Release 14.7 - Xflow P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
xflow -wd implementation -p xc7z010clg400-1 -implement xflow.opt system.ngc
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
.... Copying flowfile /opt/Xilinx/14.7/ISE_DS/ISE/xilinx/data/fpga.flw into
working directory /local/ucart/microcart1630/tasks/Quad/system/implementation
Using Flow File:
/local/ucart/microcart1630/tasks/Quad/system/implementation/fpga.flw
Using Option File(s):
/local/ucart/microcart1630/tasks/Quad/system/implementation/xflow.opt
Creating Script File ...
#----------------------------------------------#
# Starting program ngdbuild
# ngdbuild -p xc7z010clg400-1 -nt timestamp -bm system.bmm
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system.ngc" -uc
system.ucf system.ngd
#----------------------------------------------#
Release 14.7 - ngdbuild P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
Command Line: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -p
xc7z010clg400-1 -nt timestamp -bm system.bmm
/local/ucart/microcart1630/tasks/Quad/system/implementation/system.ngc -uc
system.ucf system.ngd
Reading NGO file
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system.ngc" ...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_btns_4bits_t
ri_io_wrapper.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_processing_s
ystem7_0_wrapper.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_pwm_recorder
_0_wrapper.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_pwm_recorder
_1_wrapper.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_pwm_recorder
_2_wrapper.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_pwm_recorder
_3_wrapper.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_pwm_recorder
_4_wrapper.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_pwm_recorder
_5_wrapper.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_clock_genera
tor_0_wrapper.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_axi_intercon
nect_1_wrapper.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_reset_0_wrap
per.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_pwm_signal_o
ut_wkillswitch_0_wrapper.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_pwm_signal_o
ut_wkillswitch_1_wrapper.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_pwm_signal_o
ut_wkillswitch_2_wrapper.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_pwm_signal_o
ut_wkillswitch_3_wrapper.ngc"...
Loading design module
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_axi_timer_0_
wrapper.ngc"...
Applying constraints in
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_processing_s
ystem7_0_wrapper.ncf" to module "processing_system7_0"...
Checking Constraint Associations...
Applying constraints in
"/local/ucart/microcart1630/tasks/Quad/system/implementation/system_axi_intercon
nect_1_wrapper.ncf" to module "axi_interconnect_1"...
Checking Constraint Associations...
Gathering constraint information from source properties...
Done.
INFO:NgdBuild:649 - Removing redundant 'IBUF' symbol
'processing_system7_0_PS_PORB_pin_IBUF'. All constraints associated with
this symbol will be ignored.
INFO:NgdBuild:649 - Removing redundant 'IBUF' symbol
'processing_system7_0_PS_CLK_pin_IBUF'. All constraints associated with this
symbol will be ignored.
INFO:NgdBuild:649 - Removing redundant 'IBUF' symbol
'processing_system7_0_PS_SRSTB_pin_IBUF'. All constraints associated with
this symbol will be ignored.
Annotating constraints to design from ucf file "system.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
WARNING:ConstraintSystem:135 - Constraint <INST
/system/EXPANDED/system/axi_interconnect_1/axi_interconnect_1\/si_converter_b
ank\/gen_conv_slot[0].clock_conv_inst\/interconnect_aresetn_resync<2>_inv1_IN
V_0 TNM = FFS:axi_interconnect_1_reset...>: No instances of type FFS were
found under block
"axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync<2>_inv1_INV_0" (type=INV).
WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET "processing_system7_0_PS_PORB_pin_IBUF" LOC = C7>' could not be found
and so the Locate constraint will be removed.
WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET "processing_system7_0_PS_CLK_pin_IBUF" LOC = E7>' could not be found
and so the Locate constraint will be removed.
WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET "processing_system7_0_PS_SRSTB_pin_IBUF" LOC = B10>' could not be found
and so the Locate constraint will be removed.
WARNING:ConstraintSystem:58 - Constraint <TIMEGRP
axi_interconnect_1_reset_source = FFS PADS CPUS;>: CPUS "*" does not match
any design objects.
WARNING:ConstraintSystem:194 - The TNM 'axi_interconnect_1_reset_resync', does
not directly or indirectly drive any flip-flops, latches and/or RAMs and is
not actively used by any referencing constraint.
Done...
Processing BMM file "system.bmm" ...
WARNING::53 - File 'system.bmm' is empty or has no BMM content.
Checking expanded design ...
WARNING:NgdBuild:452 - logical net 'N129' has no driver
WARNING:NgdBuild:452 - logical net 'N130' has no driver
WARNING:NgdBuild:452 - logical net 'N131' has no driver
WARNING:NgdBuild:452 - logical net 'N132' has no driver
WARNING:NgdBuild:452 - logical net 'N133' has no driver
WARNING:NgdBuild:452 - logical net 'N134' has no driver
WARNING:NgdBuild:452 - logical net 'N135' has no driver
WARNING:NgdBuild:452 - logical net 'N136' has no driver
WARNING:NgdBuild:452 - logical net 'N137' has no driver
WARNING:NgdBuild:452 - logical net 'N138' has no driver
WARNING:NgdBuild:452 - logical net 'N139' has no driver
WARNING:NgdBuild:452 - logical net 'N140' has no driver
WARNING:NgdBuild:452 - logical net 'N141' has no driver
WARNING:NgdBuild:452 - logical net 'N142' has no driver
WARNING:NgdBuild:452 - logical net 'N143' has no driver
WARNING:NgdBuild:452 - logical net 'N144' has no driver
WARNING:NgdBuild:452 - logical net 'N145' has no driver
WARNING:NgdBuild:452 - logical net 'N146' has no driver
WARNING:NgdBuild:452 - logical net 'N147' has no driver
WARNING:NgdBuild:452 - logical net 'N148' has no driver
WARNING:NgdBuild:452 - logical net 'N149' has no driver
WARNING:NgdBuild:452 - logical net 'N150' has no driver
WARNING:NgdBuild:452 - logical net 'N151' has no driver
WARNING:NgdBuild:452 - logical net 'N152' has no driver
WARNING:NgdBuild:452 - logical net 'N153' has no driver
WARNING:NgdBuild:452 - logical net 'N154' has no driver
WARNING:NgdBuild:452 - logical net 'N155' has no driver
WARNING:NgdBuild:452 - logical net 'N156' has no driver
WARNING:NgdBuild:452 - logical net 'N157' has no driver
WARNING:NgdBuild:452 - logical net 'N158' has no driver
WARNING:NgdBuild:452 - logical net 'N159' has no driver
WARNING:NgdBuild:452 - logical net 'N160' has no driver
WARNING:NgdBuild:452 - logical net 'N161' has no driver
WARNING:NgdBuild:452 - logical net 'N162' has no driver
WARNING:NgdBuild:452 - logical net 'N163' has no driver
WARNING:NgdBuild:452 - logical net 'N164' has no driver
WARNING:NgdBuild:452 - logical net 'N165' has no driver
WARNING:NgdBuild:452 - logical net 'N166' has no driver
WARNING:NgdBuild:452 - logical net 'N167' has no driver
WARNING:NgdBuild:452 - logical net 'N168' has no driver
WARNING:NgdBuild:452 - logical net 'N169' has no driver
WARNING:NgdBuild:452 - logical net 'N170' has no driver
WARNING:NgdBuild:452 - logical net 'N171' has no driver
WARNING:NgdBuild:452 - logical net 'N172' has no driver
WARNING:NgdBuild:452 - logical net 'N173' has no driver
WARNING:NgdBuild:452 - logical net 'N174' has no driver
WARNING:NgdBuild:452 - logical net 'N175' has no driver
WARNING:NgdBuild:452 - logical net 'N176' has no driver
WARNING:NgdBuild:452 - logical net 'N177' has no driver
WARNING:NgdBuild:452 - logical net 'N178' has no driver
WARNING:NgdBuild:452 - logical net 'N179' has no driver
WARNING:NgdBuild:452 - logical net 'N180' has no driver
WARNING:NgdBuild:452 - logical net 'N181' has no driver
WARNING:NgdBuild:452 - logical net 'N182' has no driver
WARNING:NgdBuild:452 - logical net 'N183' has no driver
WARNING:NgdBuild:452 - logical net 'N184' has no driver
WARNING:NgdBuild:452 - logical net 'N185' has no driver
WARNING:NgdBuild:452 - logical net 'N186' has no driver
WARNING:NgdBuild:452 - logical net 'N187' has no driver
WARNING:NgdBuild:452 - logical net 'N188' has no driver
WARNING:NgdBuild:452 - logical net 'N189' has no driver
WARNING:NgdBuild:452 - logical net 'N190' has no driver
WARNING:NgdBuild:452 - logical net 'N191' has no driver
WARNING:NgdBuild:452 - logical net 'N192' has no driver
WARNING:NgdBuild:452 - logical net 'N193' has no driver
WARNING:NgdBuild:452 - logical net 'N194' has no driver
WARNING:NgdBuild:452 - logical net 'N195' has no driver
WARNING:NgdBuild:452 - logical net 'N196' has no driver
WARNING:NgdBuild:452 - logical net 'N197' has no driver
WARNING:NgdBuild:452 - logical net 'N198' has no driver
WARNING:NgdBuild:452 - logical net 'N199' has no driver
WARNING:NgdBuild:452 - logical net 'N200' has no driver
WARNING:NgdBuild:452 - logical net 'N201' has no driver
WARNING:NgdBuild:452 - logical net 'N202' has no driver
WARNING:NgdBuild:452 - logical net 'N203' has no driver
WARNING:NgdBuild:452 - logical net 'N204' has no driver
WARNING:NgdBuild:452 - logical net 'N205' has no driver
WARNING:NgdBuild:452 - logical net 'N206' has no driver
WARNING:NgdBuild:452 - logical net 'N207' has no driver
WARNING:NgdBuild:452 - logical net 'N208' has no driver
WARNING:NgdBuild:452 - logical net 'N209' has no driver
WARNING:NgdBuild:452 - logical net 'N210' has no driver
WARNING:NgdBuild:452 - logical net 'N211' has no driver
WARNING:NgdBuild:452 - logical net 'N212' has no driver
WARNING:NgdBuild:452 - logical net 'N213' has no driver
WARNING:NgdBuild:452 - logical net 'N214' has no driver
WARNING:NgdBuild:452 - logical net 'N215' has no driver
WARNING:NgdBuild:452 - logical net 'N216' has no driver
WARNING:NgdBuild:452 - logical net 'N217' has no driver
WARNING:NgdBuild:452 - logical net 'N218' has no driver
WARNING:NgdBuild:452 - logical net 'N219' has no driver
WARNING:NgdBuild:452 - logical net 'N220' has no driver
WARNING:NgdBuild:452 - logical net 'N221' has no driver
WARNING:NgdBuild:452 - logical net 'N222' has no driver
WARNING:NgdBuild:452 - logical net 'N223' has no driver
WARNING:NgdBuild:452 - logical net 'N224' has no driver
WARNING:NgdBuild:452 - logical net 'N225' has no driver
WARNING:NgdBuild:452 - logical net 'N226' has no driver
WARNING:NgdBuild:452 - logical net 'N227' has no driver
WARNING:NgdBuild:452 - logical net 'N228' has no driver
WARNING:NgdBuild:452 - logical net 'N229' has no driver
WARNING:NgdBuild:452 - logical net 'N230' has no driver
WARNING:NgdBuild:452 - logical net 'N231' has no driver
WARNING:NgdBuild:452 - logical net 'N232' has no driver
WARNING:NgdBuild:452 - logical net 'N233' has no driver
WARNING:NgdBuild:452 - logical net 'N234' has no driver
WARNING:NgdBuild:452 - logical net 'N235' has no driver
WARNING:NgdBuild:452 - logical net 'N236' has no driver
WARNING:NgdBuild:452 - logical net 'N237' has no driver
WARNING:NgdBuild:452 - logical net 'N238' has no driver
WARNING:NgdBuild:452 - logical net 'N239' has no driver
WARNING:NgdBuild:452 - logical net 'N240' has no driver
WARNING:NgdBuild:452 - logical net 'N241' has no driver
WARNING:NgdBuild:452 - logical net 'N242' has no driver
WARNING:NgdBuild:452 - logical net 'N243' has no driver
WARNING:NgdBuild:452 - logical net 'N244' has no driver
WARNING:NgdBuild:452 - logical net 'N245' has no driver
WARNING:NgdBuild:452 - logical net 'N246' has no driver
WARNING:NgdBuild:452 - logical net 'N247' has no driver
WARNING:NgdBuild:452 - logical net 'N248' has no driver
WARNING:NgdBuild:452 - logical net 'N249' has no driver
WARNING:NgdBuild:452 - logical net 'N250' has no driver
WARNING:NgdBuild:452 - logical net 'N251' has no driver
WARNING:NgdBuild:452 - logical net 'N252' has no driver
WARNING:NgdBuild:452 - logical net 'N253' has no driver
WARNING:NgdBuild:452 - logical net 'N254' has no driver
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 132
Writing NGD file "system.ngd" ...
Total REAL time to NGDBUILD completion: 26 sec
Total CPU time to NGDBUILD completion: 26 sec
Writing NGDBUILD log file "system.bld"...
NGDBUILD done.
#----------------------------------------------#
# Starting program map
# map -o system_map.ncd -w -pr b -ol high -timing -detail system.ngd system.pcf
#----------------------------------------------#
Release 14.7 - Map P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/data/Xdh_PrimTypeLib.xda> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/data/Xdh_PrimTypeLib.xda>
Using target part "7z010clg400-1".
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set.
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
'1717@io.ece.iastate.edu:27006@io.ece.iastate.edu'.
INFO:Security:54 - 'xc7z010' is a WebPack part.
WARNING:Security:43 - No license file was found in the standard Xilinx license
directory.
WARNING:Security:44 - Since no license file was found,
please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
----------------------------------------------------------------------
WARNING:LIT:701 - PAD symbol "CLK_N" has an undefined IOSTANDARD.
WARNING:LIT:702 - PAD symbol "CLK_N" is not constrained (LOC) to a specific
location.
WARNING:LIT:701 - PAD symbol "CLK_P" has an undefined IOSTANDARD.
WARNING:LIT:702 - PAD symbol "CLK_P" is not constrained (LOC) to a specific
location.
WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_SRSTB_pin" has an
undefined IOSTANDARD.
WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_SRSTB_pin" is not
constrained (LOC) to a specific location.
WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_CLK_pin" has an undefined
IOSTANDARD.
WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_CLK_pin" is not
constrained (LOC) to a specific location.
WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_PORB_pin" has an undefined
IOSTANDARD.
WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_PORB_pin" is not
constrained (LOC) to a specific location.
Mapping design into LUTs...
WARNING:MapLib:701 - Signal CLK_P connected to top level port CLK_P has been
removed.
WARNING:MapLib:701 - Signal CLK_N connected to top level port CLK_N has been
removed.
Writing file system_map.ngm...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 28 secs
Total CPU time at the beginning of Placer: 28 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:6266348b) REAL time: 30 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:6266348b) REAL time: 31 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:6266348b) REAL time: 31 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:8ad877f8) REAL time: 35 secs
Phase 5.30 Global Clock Region Assignment
Phase 5.30 Global Clock Region Assignment (Checksum:8ad877f8) REAL time: 35 secs
Phase 6.3 Local Placement Optimization
Phase 6.3 Local Placement Optimization (Checksum:8ad877f8) REAL time: 35 secs
Phase 7.5 Local Placement Optimization
Phase 7.5 Local Placement Optimization (Checksum:8ad877f8) REAL time: 35 secs
Phase 8.8 Global Placement
...............................
.................................................................................................................................................................
..........................................................................................................................................
Phase 8.8 Global Placement (Checksum:c2ef263) REAL time: 43 secs
Phase 9.5 Local Placement Optimization
Phase 9.5 Local Placement Optimization (Checksum:c2ef263) REAL time: 43 secs
Phase 10.18 Placement Optimization
Phase 10.18 Placement Optimization (Checksum:69f76ad6) REAL time: 47 secs
Phase 11.5 Local Placement Optimization
Phase 11.5 Local Placement Optimization (Checksum:69f76ad6) REAL time: 47 secs
Phase 12.34 Placement Validation
Phase 12.34 Placement Validation (Checksum:69f76ad6) REAL time: 47 secs
Total REAL time to Placer completion: 47 secs
Total CPU time to Placer completion: 47 secs
Running post-placement packing...
Writing output files...
Design Summary:
Number of errors: 0
Number of warnings: 12
Slice Logic Utilization:
Number of Slice Registers: 2,592 out of 35,200 7%
Number used as Flip Flops: 2,336
Number used as Latches: 256
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 2,463 out of 17,600 13%
Number used as logic: 2,352 out of 17,600 13%
Number using O6 output only: 1,360
Number using O5 output only: 224
Number using O5 and O6: 768
Number used as ROM: 0
Number used as Memory: 4 out of 6,000 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 4
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 107
Number with same-slice register load: 97
Number with same-slice carry load: 5
Number with other load: 5
Slice Logic Distribution:
Number of occupied Slices: 1,050 out of 4,400 23%
Number of LUT Flip Flop pairs used: 3,371
Number with an unused Flip Flop: 1,104 out of 3,371 32%
Number with an unused LUT: 908 out of 3,371 26%
Number of fully used LUT-FF pairs: 1,359 out of 3,371 40%
Number of unique control sets: 120
Number of slice register sites lost
to control set restrictions: 484 out of 35,200 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
OVERMAPPING of BRAM resources should be ignored if the design is
over-mapped for a non-BRAM resource or if placement fails.
IO Utilization:
Number of bonded IOBs: 16 out of 100 16%
Number of LOCed IOBs: 16 out of 16 100%
Number of bonded IOPAD: 130 out of 130 100%
IOB Flip Flops: 6
Specific Feature Utilization:
Number of RAMB36E1/FIFO36E1s: 0 out of 60 0%
Number of RAMB18E1/FIFO18E1s: 0 out of 120 0%
Number of BUFG/BUFGCTRLs: 5 out of 32 15%
Number used as BUFGs: 5
Number used as BUFGCTRLs: 0
Number of IDELAYE2/IDELAYE2_FINEDELAYs: 0 out of 100 0%
Number of ILOGICE2/ILOGICE3/ISERDESE2s: 6 out of 100 6%
Number used as ILOGICE2s: 6
Number used as ILOGICE3s: 0
Number used as ISERDESE2s: 0
Number of ODELAYE2/ODELAYE2_FINEDELAYs: 0
Number of OLOGICE2/OLOGICE3/OSERDESE2s: 0 out of 100 0%
Number of PHASER_IN/PHASER_IN_PHYs: 0 out of 8 0%
Number of PHASER_OUT/PHASER_OUT_PHYs: 0 out of 8 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHCEs: 0 out of 48 0%
Number of BUFRs: 0 out of 8 0%
Number of CAPTUREs: 0 out of 1 0%
Number of DNA_PORTs: 0 out of 1 0%
Number of DSP48E1s: 0 out of 80 0%
Number of EFUSE_USRs: 0 out of 1 0%
Number of FRAME_ECCs: 0 out of 1 0%
Number of ICAPs: 0 out of 2 0%
Number of IDELAYCTRLs: 0 out of 2 0%
Number of IN_FIFOs: 0 out of 8 0%
Number of MMCME2_ADVs: 0 out of 2 0%
Number of OUT_FIFOs: 0 out of 8 0%
Number of PHASER_REFs: 0 out of 2 0%
Number of PHY_CONTROLs: 0 out of 2 0%
Number of PLLE2_ADVs: 0 out of 2 0%
Number of PS7s: 1 out of 1 100%
Number of STARTUPs: 0 out of 1 0%
Number of XADCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.45
Peak Memory Usage: 1276 MB
Total REAL time to MAP completion: 50 secs
Total CPU time to MAP completion: 50 secs
Mapping completed.
See MAP report file "system_map.mrp" for details.
#----------------------------------------------#
# Starting program par
# par -w -ol high system_map.ncd system.ncd system.pcf
#----------------------------------------------#
Release 14.7 - par P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file </opt/Xilinx/14.7/ISE_DS/EDK/data/parBmgr.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/data/parBmgr.acd>
Constraints file: system.pcf.
Loading device for application Rf_Device from file '7z010.nph' in environment
/opt/Xilinx/14.7/ISE_DS/ISE/:/opt/Xilinx/14.7/ISE_DS/EDK.
"system" is an NCD, version 3.2, device xc7z010, package clg400, speed -1
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set.
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
'1717@io.ece.iastate.edu:27006@io.ece.iastate.edu'.
INFO:Security:54 - 'xc7z010' is a WebPack part.
WARNING:Security:43 - No license file was found in the standard Xilinx license directory.
WARNING:Security:44 - Since no license file was found,
please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)
Device speed data version: "PRODUCTION 1.08 2013-10-13".
Device Utilization Summary:
Number of BUFGs 5 out of 32 15%
Number of ILOGICE2s 6 out of 100 6%
Number of External IOB33s 16 out of 100 16%
Number of LOCed IOB33s 16 out of 16 100%
Number of External IOPADs 130 out of 130 100%
Number of LOCed IOPADs 127 out of 130 97%
Number of PS7s 1 out of 1 100%
Number of Slices 1050 out of 4400 23%
Number of Slice Registers 2592 out of 35200 6%
Number used as Flip Flops 2336
Number used as Latches 256
Number used as LatchThrus 0
Number of Slice LUTS 2463 out of 17600 13%
Number of Slice LUT-Flip Flop pairs 3337 out of 17600 18%
Overall effort level (-ol): High
Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 15 secs
Finished initial Timing Analysis. REAL time: 15 secs
Starting Router
Phase 1 : 15492 unrouted; REAL time: 16 secs
Phase 2 : 11844 unrouted; REAL time: 17 secs
Phase 3 : 4171 unrouted; REAL time: 21 secs
Phase 4 : 4171 unrouted; (Setup:0, Hold:12522, Component Switching Limit:0) REAL time: 22 secs
Updating file: system.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:10929, Component Switching Limit:0) REAL time: 26 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:10929, Component Switching Limit:0) REAL time: 26 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:10929, Component Switching Limit:0) REAL time: 26 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:10929, Component Switching Limit:0) REAL time: 26 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 28 secs
Total REAL time to Router completion: 28 secs
Total CPU time to Router completion: 28 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|processing_system7_0 | | | | | |
| _FCLK_CLK0 | BUFGCTRL_X0Y0| No | 709 | 0.132 | 1.774 |
+---------------------+--------------+------+------+------------+-------------+
|pwm_signal_out_wkill | | | | | |
|switch_0/pwm_signal_ | | | | | |
|out_wkillswitch_0/US | | | | | |
|ER_LOGIC_I/PWM_Hello | | | | | |
|/counter[31]_pwm_per | | | | | |
|_t[31]_equal_9_o_BUF | | | | | |
| G |BUFGCTRL_X0Y31| No | 16 | 0.011 | 1.651 |
+---------------------+--------------+------+------+------------+-------------+
|pwm_signal_out_wkill | | | | | |
|switch_2/pwm_signal_ | | | | | |
|out_wkillswitch_2/US | | | | | |
|ER_LOGIC_I/PWM_Hello | | | | | |
|/counter[31]_pwm_per | | | | | |
|_t[31]_equal_9_o_BUF | | | | | |
| G | BUFGCTRL_X0Y2| No | 16 | 0.007 | 1.663 |
+---------------------+--------------+------+------+------------+-------------+
|pwm_signal_out_wkill | | | | | |
|switch_3/pwm_signal_ | | | | | |
|out_wkillswitch_3/US | | | | | |
|ER_LOGIC_I/PWM_Hello | | | | | |
|/counter[31]_pwm_per | | | | | |
|_t[31]_equal_9_o_BUF | | | | | |
| G | BUFGCTRL_X0Y1| No | 16 | 0.015 | 1.660 |
+---------------------+--------------+------+------+------------+-------------+
|pwm_signal_out_wkill | | | | | |
|switch_1/pwm_signal_ | | | | | |
|out_wkillswitch_1/US | | | | | |
|ER_LOGIC_I/PWM_Hello | | | | | |
|/counter[31]_pwm_per | | | | | |
|_t[31]_equal_9_o_BUF | | | | | |
| G |BUFGCTRL_X0Y30| No | 16 | 0.059 | 1.706 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_clk_fpga_0 = PERIOD TIMEGRP "clk_fpga_ | SETUP | 0.708ns| 9.292ns| 0| 0
0" 100 MHz HIGH 50% | HOLD | 0.004ns| | 0| 0
----------------------------------------------------------------------------------------------------------
PATH "TS_axi_interconnect_1_reset_resync_ | SETUP | N/A| 1.100ns| N/A| 0
path" TIG | | | | |
----------------------------------------------------------------------------------------------------------
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 29 secs
Total CPU time to PAR completion: 30 secs
Peak Memory Usage: 966 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1
Writing design to file system.ncd
PAR done!
#----------------------------------------------#
# Starting program post_par_trce
# trce -e 3 -xml system.twx system.ncd system.pcf
#----------------------------------------------#
Release 14.7 - Trace (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
Loading device for application Rf_Device from file '7z010.nph' in environment
/opt/Xilinx/14.7/ISE_DS/ISE/:/opt/Xilinx/14.7/ISE_DS/EDK.
"system" is an NCD, version 3.2, device xc7z010, package clg400, speed -1
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more
information, see the TSI report. Please consult the Xilinx Command Line
Tools User Guide for information on generating a TSI report.
--------------------------------------------------------------------------------
Release 14.7 Trace (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -e 3 -xml system.twx
system.ncd system.pcf
Design file: system.ncd
Physical constraint file: system.pcf
Device,speed: xc7z010,-1 (PRODUCTION 1.08 2013-10-13)
Report level: error report
--------------------------------------------------------------------------------
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in
the unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of
this model, and for more information on accounting for different loading conditions, please see the device datasheet.
Timing summary:
---------------
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
Constraints cover 98919 paths, 0 nets, and 11664 connections
Design statistics:
Minimum period: 9.292ns (Maximum frequency: 107.619MHz)
Analysis completed Wed Dec 30 21:35:27 2015
--------------------------------------------------------------------------------
Generating Report ...
Number of warnings: 0
Number of info messages: 4
Total time: 16 secs
xflow done!
touch __xps/system_routed
xilperl /opt/Xilinx/14.7/ISE_DS/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par
Analyzing implementation/system.par
*********************************************
Running Bitgen..
*********************************************
cd implementation ; bitgen -w -f bitgen.ut system ; cd ..
Release 14.7 - Bitgen P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/14.7/ISE_DS/EDK/zynq/data/zynq.acd> with local file
</opt/Xilinx/14.7/ISE_DS/ISE/zynq/data/zynq.acd>
Loading device for application Rf_Device from file '7z010.nph' in environment
/opt/Xilinx/14.7/ISE_DS/ISE/:/opt/Xilinx/14.7/ISE_DS/EDK.
"system" is an NCD, version 3.2, device xc7z010, package clg400, speed -1
Opened constraints file system.pcf.
Wed Dec 30 21:35:38 2015
Running DRC.
DRC detected 0 errors and 0 warnings.
INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set.
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
'1717@io.ece.iastate.edu:27006@io.ece.iastate.edu'.
INFO:Security:54 - 'xc7z010' is a WebPack part.
WARNING:Security:43 - No license file was found in the standard Xilinx license
directory.
WARNING:Security:44 - Since no license file was found,
please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
Creating bit map...
Saving bit stream in "system.bit".
Bitstream generation is complete.
Done!
Xilinx Platform Studio (XPS)
Xilinx EDK 14.7 Build EDK_P.20131013
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Overriding Xilinx file <TextEditor.cfg> with local file </opt/Xilinx/14.7/ISE_DS/EDK/data/TextEditor.cfg>
Writing filter settings....
Done writing filter settings to:
/local/ucart/microcart1630/tasks/Quad/system/etc/system.filters
Done writing Tab View settings to:
/local/ucart/microcart1630/tasks/Quad/system/etc/system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.7 Build EDK_P.20131013
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Overriding Xilinx file <TextEditor.cfg> with local file </opt/Xilinx/14.7/ISE_DS/EDK/data/TextEditor.cfg>
Writing filter settings....
Done writing filter settings to:
/local/ucart/microcart1630/tasks/Quad/system/etc/system.filters
Done writing Tab View settings to:
/local/ucart/microcart1630/tasks/Quad/system/etc/system.gui