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quad/sw/system_bsp/ps7_cortexa9_0/include/xgpiops.h 0 → 100644
View file @ fb5bce18
/******************************************************************************
*
* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xgpiops.h
*
* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
* Controller.
*
* The GPIO Controller supports the following features:
* - 4 banks
* - Masked writes (There are no masked reads)
* - Bypass mode
* - Configurable Interrupts (Level/Edge)
*
* This driver is intended to be RTOS and processor independent. Any needs for
* dynamic memory management, threads or thread mutual exclusion, virtual
* memory, or cache control must be satisfied by the layer above this driver.
* This driver supports all the features listed above, if applicable.
*
* <b>Driver Description</b>
*
* The device driver enables higher layer software (e.g., an application) to
* communicate to the GPIO.
*
* <b>Interrupts</b>
*
* The driver provides interrupt management functions and an interrupt handler.
* Users of this driver need to provide callback functions. An interrupt handler
* example is available with the driver.
*
* <b>Threads</b>
*
* This driver is not thread safe. Any needs for threads or thread mutual
* exclusion must be satisfied by the layer above this driver.
*
* <b>Asserts</b>
*
* Asserts are used within all Xilinx drivers to enforce constraints on argument
* values. Asserts can be turned off on a system-wide basis by defining, at
* compile time, the NDEBUG identifier. By default, asserts are turned on and it
* is recommended that users leave asserts on during development.
*
* <b>Building the driver</b>
*
* The XGpioPs driver is composed of several source files. This allows the user
* to build and link only those parts of the driver that are necessary.
* <br><br>
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a sv 01/15/10 First Release
* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
* relevant to Zynq device.The interrupts are disabled
* for output pins on all banks during initialization.
* 1.02a hk 08/22/13 Added low level reset API
* </pre>
*
******************************************************************************/
#ifndef XGPIOPS_H /* prevent circular inclusions */
#define XGPIOPS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xstatus.h"
#include "xgpiops_hw.h"
/************************** Constant Definitions *****************************/
/** @name Interrupt types
* @{
* The following constants define the interrupt types that can be set for each
* GPIO pin.
*/
#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0 /**< Interrupt on Rising edge */
#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 1 /**< Interrupt Falling edge */
#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 2 /**< Interrupt on both edges */
#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 3 /**< Interrupt on high level */
#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 4 /**< Interrupt on low level */
/*@}*/
#define XGPIOPS_BANK0 0 /**< GPIO Bank 0 */
#define XGPIOPS_BANK1 1 /**< GPIO Bank 1 */
#define XGPIOPS_BANK2 2 /**< GPIO Bank 2 */
#define XGPIOPS_BANK3 3 /**< GPIO Bank 3 */
#define XGPIOPS_MAX_BANKS 4 /**< Max banks in a GPIO device */
#define XGPIOPS_BANK_MAX_PINS 32 /**< Max pins in a GPIO bank */
#define XGPIOPS_DEVICE_MAX_PIN_NUM 118 /*< Max pins in the GPIO device
* 0 - 31, Bank 0
* 32 - 53, Bank 1
* 54 - 85, Bank 2
* 86 - 117, Bank 3
*/
/**************************** Type Definitions *******************************/
/****************************************************************************/
/**
* This handler data type allows the user to define a callback function to
* handle the interrupts for the GPIO device. The application using this
* driver is expected to define a handler of this type, to support interrupt
* driven mode. The handler executes in an interrupt context such that minimal
* processing should be performed.
*
* @param CallBackRef is a callback reference passed in by the upper layer
* when setting the callback functions for a GPIO bank. It is
* passed back to the upper layer when the callback is invoked. Its
* type is not important to the driver component, so it is a void
* pointer.
* @param Bank is the bank for which the interrupt status has changed.
* @param Status is the Interrupt status of the GPIO bank.
*
*****************************************************************************/
typedef void (*XGpioPs_Handler) (void *CallBackRef, int Bank, u32 Status);
/**
* This typedef contains configuration information for a device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddr; /**< Register base address */
} XGpioPs_Config;
/**
* The XGpioPs driver instance data. The user is required to allocate a
* variable of this type for the GPIO device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
XGpioPs_Config GpioConfig; /**< Device configuration */
u32 IsReady; /**< Device is initialized and ready */
XGpioPs_Handler Handler; /**< Status handlers for all banks */
void *CallBackRef; /**< Callback ref for bank handlers */
} XGpioPs;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*
* Functions in xgpiops.c
*/
int XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
u32 EffectiveAddr);
/*
* Bank APIs in xgpiops.c
*/
u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank);
void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data);
void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction);
u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank);
void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 Enable);
u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank);
void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank);
/*
* Pin APIs in xgpiops.c
*/
int XGpioPs_ReadPin(XGpioPs *InstancePtr, int Pin);
void XGpioPs_WritePin(XGpioPs *InstancePtr, int Pin, int Data);
void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, int Pin, int Direction);
int XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, int Pin);
void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, int Pin, int Enable);
int XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, int Pin);
/*
* Diagnostic functions in xgpiops_selftest.c
*/
int XGpioPs_SelfTest(XGpioPs *InstancePtr);
/*
* Functions in xgpiops_intr.c
*/
/*
* Bank APIs in xgpiops_intr.c
*/
void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank);
u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank);
void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
u32 IntrPolarity, u32 IntrOnAny);
void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
u32 *IntrPolarity, u32 *IntrOnAny);
void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
XGpioPs_Handler FuncPtr);
void XGpioPs_IntrHandler(XGpioPs *InstancePtr);
/*
* Pin APIs in xgpiops_intr.c
*/
void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, int Pin, u8 IrqType);
u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, int Pin);
void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, int Pin);
void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, int Pin);
int XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, int Pin);
int XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, int Pin);
void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, int Pin);
/*
* Functions in xgpiops_sinit.c
*/
XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
quad/sw/system_bsp/ps7_cortexa9_0/include/xgpiops_hw.h 0 → 100644
View file @ fb5bce18
/******************************************************************************
*
* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xgpiops_hw.h
*
* This header file contains the identifiers and basic driver functions (or
* macros) that can be used to access the device. Other driver functions
* are defined in xgpiops.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------
* 1.00a sv 01/15/10 First Release
* 1.02a hk 08/22/13 Added low level reset API function prototype and
* related constant definitions
* </pre>
*
******************************************************************************/
#ifndef XGPIOPS_HW_H /* prevent circular inclusions */
#define XGPIOPS_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name Register offsets for the GPIO. Each register is 32 bits.
* @{
*/
#define XGPIOPS_DATA_LSW_OFFSET 0x000 /* Mask and Data Register LSW, WO */
#define XGPIOPS_DATA_MSW_OFFSET 0x004 /* Mask and Data Register MSW, WO */
#define XGPIOPS_DATA_OFFSET 0x040 /* Data Register, RW */
#define XGPIOPS_DIRM_OFFSET 0x204 /* Direction Mode Register, RW */
#define XGPIOPS_OUTEN_OFFSET 0x208 /* Output Enable Register, RW */
#define XGPIOPS_INTMASK_OFFSET 0x20C /* Interrupt Mask Register, RO */
#define XGPIOPS_INTEN_OFFSET 0x210 /* Interrupt Enable Register, WO */
#define XGPIOPS_INTDIS_OFFSET 0x214 /* Interrupt Disable Register, WO*/
#define XGPIOPS_INTSTS_OFFSET 0x218 /* Interrupt Status Register, RO */
#define XGPIOPS_INTTYPE_OFFSET 0x21C /* Interrupt Type Register, RW */
#define XGPIOPS_INTPOL_OFFSET 0x220 /* Interrupt Polarity Register, RW */
#define XGPIOPS_INTANY_OFFSET 0x224 /* Interrupt On Any Register, RW */
/* @} */
/** @name Register offsets for each Bank.
* @{
*/
#define XGPIOPS_DATA_MASK_OFFSET 0x8 /* Data/Mask Registers offset */
#define XGPIOPS_DATA_BANK_OFFSET 0x4 /* Data Registers offset */
#define XGPIOPS_REG_MASK_OFFSET 0x40 /* Registers offset */
/* @} */
/* For backwards compatibility */
#define XGPIOPS_BYPM_MASK_OFFSET XGPIOPS_REG_MASK_OFFSET
/** @name Interrupt type reset values for each bank
* @{
*/
#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFF
#define XGPIOPS_INTTYPE_BANK1_RESET 0x3FFFFFFF
#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFF
#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFF
/* @} */
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
*
* This macro reads the given register.
*
* @param BaseAddr is the base address of the device.
* @param RegOffset is the register offset to be read.
*
* @return The 32-bit value of the register
*
* @note None.
*
*****************************************************************************/
#define XGpioPs_ReadReg(BaseAddr, RegOffset) \
Xil_In32((BaseAddr) + (RegOffset))
/****************************************************************************/
/**
*
* This macro writes to the given register.
*
* @param BaseAddr is the base address of the device.
* @param RegOffset is the offset of the register to be written.
* @param Data is the 32-bit value to write to the register.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
Xil_Out32((BaseAddr) + (RegOffset), (Data))
/************************** Function Prototypes ******************************/
void XGpioPs_ResetHw(u32 BaseAddress);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XGPIOPS_HW_H */
quad/sw/system_bsp/ps7_cortexa9_0/include/xiicps.h 0 → 100644
View file @ fb5bce18
/******************************************************************************
*
* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiicps.h
*
* This is an implementation of IIC driver in the PS block. The device can
* be either a master or a slave on the IIC bus. This implementation supports
* both interrupt mode transfer and polled mode transfer. Only 7-bit address
* is used in the driver, although the hardware also supports 10-bit address.
*
* IIC is a 2-wire serial interface. The master controls the clock, so it can
* regulate when it wants to send or receive data. The slave is under control of
* the master, it must respond quickly since it has no control of the clock and
* must send/receive data as fast or as slow as the master does.
*
* The higher level software must implement a higher layer protocol to inform
* the slave what to send to the master.
*
* <b>Initialization & Configuration</b>
*
* The XIicPs_Config structure is used by the driver to configure itself. This
* configuration structure is typically created by the tool-chain based on HW
* build properties.
*
* To support multiple runtime loading and initialization strategies employed by
* various operating systems, the driver instance can be initialized in the
* following way:
*
* - XIicPs_LookupConfig(DeviceId) - Use the device identifier to find
* the static configuration structure defined in xiicps_g.c. This is
* setup by the tools. For some operating systems the config structure
* will be initialized by the software and this call is not needed.
*
* - XIicPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
* configuration structure provided by the caller. If running in a
* system with address translation, the provided virtual memory base
* address replaces the physical address in the configuration
* structure.
*
* <b>Multiple Masters</b>
*
* More than one master can exist, bus arbitration is defined in the IIC
* standard. Lost of arbitration causes arbitration loss interrupt on the device.
*
* <b>Multiple Slaves</b>
*
* Multiple slaves are supported by selecting them with unique addresses. It is
* up to the system designer to be sure all devices on the IIC bus have
* unique addresses.
*
* <b>Addressing</b>
*
* The IIC hardware can use 7 or 10 bit addresses. The driver provides the
* ability to control which address size is sent in messages as a master to a
* slave device.
*
* <b>FIFO Size </b>
* The hardware FIFO is 32 bytes deep. The user must know the limitations of
* other IIC devices on the bus. Some are only able to receive a limited number
* of bytes in a single transfer.
*
* <b>Data Rates</b>
*
* The data rate is set by values in the control register. The formula for
* determining the correct register values is:
* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
*
* When the device is configured as a slave, the slck setting controls the
* sample rate and so must be set to be at least as fast as the fastest scl
* expected to be seen in the system.
*
* <b>Polled Mode Operation</b>
*
* This driver supports polled mode transfers.
*
* <b>Interrupts</b>
*
* The user must connect the interrupt handler of the driver,
* XIicPs_InterruptHandler to an interrupt system such that it will be called
* when an interrupt occurs. This function does not save and restore the
* processor context such that the user must provide this processing.
*
* The driver handles the following interrupts:
* - Transfer complete
* - More Data
* - Transfer not Acknowledged
* - Transfer Time out
* - Monitored slave ready - master mode only
* - Receive Overflow
* - Transmit FIFO overflow
* - Receive FIFO underflow
* - Arbitration lost
*
* <b>Bus Busy</b>
*
* Bus busy is checked before the setup of a master mode device, to avoid
* unnecessary arbitration loss interrupt.
*
* <b>RTOS Independence</b>
*
* This driver is intended to be RTOS and processor independent. It works with
* physical addresses only. Any needs for dynamic memory management, threads or
* thread mutual exclusion, virtual memory, or cache control must be satisfied by
* the layer above this driver.
*
* @note
* . Less than FIFO size transfers work for both 100 KHz and 400 KHz.
* . Larger than FIFO size interrupt-driven transfers are not reliable on
* busy systems where interrupt latency is high.
* . Larger than FIFO size interrupt-driven transfers are not reliable for
* data rate of 400 KHz.
* . Larger than FIFO size polled mode transfers work reliably.
*
* <pre> MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- -----------------------------------------------
* 1.00a drg/jz 01/30/08 First release
* 1.00a sdm 09/21/11 Fixed an issue in the XIicPs_SetOptions and
* XIicPs_ClearOptions where the InstancePtr->Options
* was not updated correctly.
* Updated the InstancePtr->Options in the
* XIicPs_CfgInitialize by calling XIicPs_GetOptions.
* Updated the XIicPs_SetupMaster to not check for
* Bus Busy condition when the Hold Bit is set.
* Removed some unused variables.
* 1.01a sg 03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
* check for transfer completion is added, which indicates
* the completion of current transfer.
* 1.02a sg 08/29/12 Updated the logic to arrive at the best divisors
* to achieve I2C clock with minimum error for
* CR #674195
* 1.03a hk 05/04/13 Initialized BestDivA and BestDivB to 0.
* This is fix for CR#704398 to remove warning.
*
* </pre>
*
******************************************************************************/
#ifndef XIICPS_H /* prevent circular inclusions */
#define XIICPS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xiicps_hw.h"
/************************** Constant Definitions *****************************/
/** @name Configuration options
*
* The following options may be specified or retrieved for the device and
* enable/disable additional features of the IIC. Each of the options
* are bit fields, so more than one may be specified.
*
* @{
*/
#define XIICPS_7_BIT_ADDR_OPTION 0x01 /**< 7-bit address mode */
#define XIICPS_10_BIT_ADDR_OPTION 0x02 /**< 10-bit address mode */
#define XIICPS_SLAVE_MON_OPTION 0x04 /**< Slave monitor mode */
#define XIICPS_REP_START_OPTION 0x08 /**< Repeated Start */
/*@}*/
/** @name Callback events
*
* These constants specify the handler events that are passed to an application
* event handler from the driver. These constants are bit masks such that
* more than one event can be passed to the handler.
*
* @{
*/
#define XIICPS_EVENT_COMPLETE_SEND 0x0001 /**< Transmit Complete Event*/
#define XIICPS_EVENT_COMPLETE_RECV 0x0002 /**< Receive Complete Event*/
#define XIICPS_EVENT_TIME_OUT 0x0004 /**< Transfer timed out */
#define XIICPS_EVENT_ERROR 0x0008 /**< Receive error */
#define XIICPS_EVENT_ARB_LOST 0x0010 /**< Arbitration lost */
#define XIICPS_EVENT_NACK 0x0020 /**< NACK Received */
#define XIICPS_EVENT_SLAVE_RDY 0x0040 /**< Slave ready */
#define XIICPS_EVENT_RX_OVR 0x0080 /**< RX overflow */
#define XIICPS_EVENT_TX_OVR 0x0100 /**< TX overflow */
#define XIICPS_EVENT_RX_UNF 0x0200 /**< RX underflow */
/*@}*/
/** @name Role constants
*
* These constants are used to pass into the device setup routines to
* set up the device according to transfer direction.
*/
#define SENDING_ROLE 1 /**< Transfer direction is sending */
#define RECVING_ROLE 0 /**< Transfer direction is receiving */
/**************************** Type Definitions *******************************/
/**
* The handler data type allows the user to define a callback function to
* respond to interrupt events in the system. This function is executed
* in interrupt context, so amount of processing should be minimized.
*
* @param CallBackRef is the callback reference passed in by the upper
* layer when setting the callback functions, and passed back to
* the upper layer when the callback is invoked. Its type is
* not important to the driver, so it is a void pointer.
* @param StatusEvent indicates one or more status events that occurred.
*/
typedef void (*XIicPs_IntrHandler) (void *CallBackRef, u32 StatusEvent);
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddress; /**< Base address of the device */
u32 InputClockHz; /**< Input clock frequency */
} XIicPs_Config;
/**
* The XIicPs driver instance data. The user is required to allocate a
* variable of this type for each IIC device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
XIicPs_Config Config; /* Configuration structure */
u32 IsReady; /* Device is initialized and ready */
u32 Options; /* Options set in the device */
u8 *SendBufferPtr; /* Pointer to send buffer */
u8 *RecvBufferPtr; /* Pointer to recv buffer */
int SendByteCount; /* Number of bytes still expected to send */
int RecvByteCount; /* Number of bytes still expected to receive */
XIicPs_IntrHandler StatusHandler; /* Event handler function */
void *CallBackRef; /* Callback reference for event handler */
} XIicPs;
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/*
*
* Place one byte into the transmit FIFO.
*
* @param InstancePtr is the instance of IIC
*
* @return None.
*
* @note C-Style signature:
* void XIicPs_SendByte(XIicPs *InstancePtr)
*
*****************************************************************************/
#define XIicPs_SendByte(InstancePtr) \
{ \
XIicPs_Out32((InstancePtr)->Config.BaseAddress \
+ XIICPS_DATA_OFFSET, \
*(InstancePtr)->SendBufferPtr ++); \
(InstancePtr)->SendByteCount --; \
}
/****************************************************************************/
/*
*
* Receive one byte from FIFO.
*
* @param InstancePtr is the instance of IIC
*
* @return None.
*
* @note C-Style signature:
* u8 XIicPs_RecvByte(XIicPs *InstancePtr)
*
*****************************************************************************/
#define XIicPs_RecvByte(InstancePtr) \
{ \
*(InstancePtr)->RecvBufferPtr ++ = \
(u8)XIicPs_In32((InstancePtr)->Config.BaseAddress \
+ XIICPS_DATA_OFFSET); \
(InstancePtr)->RecvByteCount --; \
}
/************************** Function Prototypes ******************************/
/*
* Function for configuration lookup, in xiicps_sinit.c
*/
XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId);
/*
* Functions for general setup, in xiicps.c
*/
int XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config * Config,
u32 EffectiveAddr);
void XIicPs_Abort(XIicPs *InstancePtr);
void XIicPs_Reset(XIicPs *InstancePtr);
int XIicPs_BusIsBusy(XIicPs *InstancePtr);
/*
* Functions for interrupts, in xiicps_intr.c
*/
void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef,
XIicPs_IntrHandler FuncPtr);
/*
* Functions for device as master, in xiicps_master.c
*/
void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount,
u16 SlaveAddr);
void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount,
u16 SlaveAddr);
int XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount,
u16 SlaveAddr);
int XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount,
u16 SlaveAddr);
void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr);
void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr);
void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr);
/*
* Functions for device as slave, in xiicps_slave.c
*/
void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr);
void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount);
void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount);
int XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount);
int XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount);
void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr);
/*
* Functions for selftest, in xiicps_selftest.c
*/
int XIicPs_SelfTest(XIicPs *InstancePtr);
/*
* Functions for setting and getting data rate, in xiicps_options.c
*/
int XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options);
int XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options);
u32 XIicPs_GetOptions(XIicPs *InstancePtr);
int XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz);
u32 XIicPs_GetSClk(XIicPs *InstancePtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
quad/sw/system_bsp/ps7_cortexa9_0/include/xiicps_hw.h 0 → 100644
View file @ fb5bce18
/******************************************************************************
*
* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xiicps_hw.h
*
* This header file contains the hardware definition for an IIC device.
* It includes register definitions and interface functions to read/write
* the registers.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- -----------------------------------------------
* 1.00a drg/jz 01/30/10 First release
* 1.04a kpc 11/07/13 Added function prototype.
* </pre>
*
******************************************************************************/
#ifndef XIICPS_HW_H /* prevent circular inclusions */
#define XIICPS_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name Register Map
*
* Register offsets for the IIC.
* @{
*/
#define XIICPS_CR_OFFSET 0x00 /**< 32-bit Control */
#define XIICPS_SR_OFFSET 0x04 /**< Status */
#define XIICPS_ADDR_OFFSET 0x08 /**< IIC Address */
#define XIICPS_DATA_OFFSET 0x0C /**< IIC FIFO Data */
#define XIICPS_ISR_OFFSET 0x10 /**< Interrupt Status */
#define XIICPS_TRANS_SIZE_OFFSET 0x14 /**< Transfer Size */
#define XIICPS_SLV_PAUSE_OFFSET 0x18 /**< Slave monitor pause */
#define XIICPS_TIME_OUT_OFFSET 0x1C /**< Time Out */
#define XIICPS_IMR_OFFSET 0x20 /**< Interrupt Enabled Mask */
#define XIICPS_IER_OFFSET 0x24 /**< Interrupt Enable */
#define XIICPS_IDR_OFFSET 0x28 /**< Interrupt Disable */
/* @} */
/** @name Control Register
*
* This register contains various control bits that
* affects the operation of the IIC controller. Read/Write.
* @{
*/
#define XIICPS_CR_DIV_A_MASK 0x0000C000 /**< Clock Divisor A */
#define XIICPS_CR_DIV_A_SHIFT 14 /**< Clock Divisor A shift */
#define XIICPS_DIV_A_MAX 4 /**< Maximum value of Divisor A */
#define XIICPS_CR_DIV_B_MASK 0x00003F00 /**< Clock Divisor B */
#define XIICPS_CR_DIV_B_SHIFT 8 /**< Clock Divisor B shift */
#define XIICPS_CR_CLR_FIFO_MASK 0x00000040 /**< Clear FIFO, auto clears*/
#define XIICPS_CR_SLVMON_MASK 0x00000020 /**< Slave monitor mode */
#define XIICPS_CR_HOLD_MASK 0x00000010 /**< Hold bus 1=Hold scl,
0=terminate transfer */
#define XIICPS_CR_ACKEN_MASK 0x00000008 /**< Enable TX of ACK when
Master receiver*/
#define XIICPS_CR_NEA_MASK 0x00000004 /**< Addressing Mode 1=7 bit,
0=10 bit */
#define XIICPS_CR_MS_MASK 0x00000002 /**< Master mode bit 1=Master,
0=Slave */
#define XIICPS_CR_RD_WR_MASK 0x00000001 /**< Read or Write Master
transfer 0=Transmitter,
1=Receiver*/
#define XIICPS_CR_RESET_VALUE 0 /**< Reset value of the Control
register */
/* @} */
/** @name IIC Status Register
*
* This register is used to indicate status of the IIC controller. Read only
* @{
*/
#define XIICPS_SR_BA_MASK 0x00000100 /**< Bus Active Mask */
#define XIICPS_SR_RXOVF_MASK 0x00000080 /**< Receiver Overflow Mask */
#define XIICPS_SR_TXDV_MASK 0x00000040 /**< Transmit Data Valid Mask */
#define XIICPS_SR_RXDV_MASK 0x00000020 /**< Receiver Data Valid Mask */
#define XIICPS_SR_RXRW_MASK 0x00000008 /**< Receive read/write Mask */
/* @} */
/** @name IIC Address Register
*
* Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0].
* A write access to this register always initiates a transfer if the IIC is in
* master mode. Read/Write
* @{
*/
#define XIICPS_ADDR_MASK 0x000003FF /**< IIC Address Mask */
/* @} */
/** @name IIC Data Register
*
* When written to, the data register sets data to transmit. When read from, the
* data register reads the last received byte of data. Read/Write
* @{
*/
#define XIICPS_DATA_MASK 0x000000FF /**< IIC Data Mask */
/* @} */
/** @name IIC Interrupt Registers
*
* <b>IIC Interrupt Status Register</b>
*
* This register holds the interrupt status flags for the IIC controller. Some
* of the flags are level triggered
* - i.e. are set as long as the interrupt condition exists. Other flags are
* edge triggered, which means they are set one the interrupt condition occurs
* then remain set until they are cleared by software.
* The interrupts are cleared by writing a one to the interrupt bit position
* in the Interrupt Status Register. Read/Write.
*
* <b>IIC Interrupt Enable Register</b>
*
* This register is used to enable interrupt sources for the IIC controller.
* Writing a '1' to a bit in this register clears the corresponding bit in the
* IIC Interrupt Mask register. Write only.
*
* <b>IIC Interrupt Disable Register </b>
*
* This register is used to disable interrupt sources for the IIC controller.
* Writing a '1' to a bit in this register sets the corresponding bit in the
* IIC Interrupt Mask register. Write only.
*
* <b>IIC Interrupt Mask Register</b>
*
* This register shows the enabled/disabled status of each IIC controller
* interrupt source. A bit set to 1 will ignore the corresponding interrupt in
* the status register. A bit set to 0 means the interrupt is enabled.
* All mask bits are set and all interrupts are disabled after reset. Read only.
*
* All four registers have the same bit definitions. They are only defined once
* for each of the Interrupt Enable Register, Interrupt Disable Register,
* Interrupt Mask Register, and Interrupt Status Register
* @{
*/
#define XIICPS_IXR_ARB_LOST_MASK 0x00000200 /**< Arbitration Lost Interrupt
mask */
#define XIICPS_IXR_RX_UNF_MASK 0x00000080 /**< FIFO Recieve Underflow
Interrupt mask */
#define XIICPS_IXR_TX_OVR_MASK 0x00000040 /**< Transmit Overflow
Interrupt mask */
#define XIICPS_IXR_RX_OVR_MASK 0x00000020 /**< Receive Overflow Interrupt
mask */
#define XIICPS_IXR_SLV_RDY_MASK 0x00000010 /**< Monitored Slave Ready
Interrupt mask */
#define XIICPS_IXR_TO_MASK 0x00000008 /**< Transfer Time Out
Interrupt mask */
#define XIICPS_IXR_NACK_MASK 0x00000004 /**< NACK Interrupt mask */
#define XIICPS_IXR_DATA_MASK 0x00000002 /**< Data Interrupt mask */
#define XIICPS_IXR_COMP_MASK 0x00000001 /**< Transfer Complete
Interrupt mask */
#define XIICPS_IXR_DEFAULT_MASK 0x000002FF /**< Default ISR Mask */
#define XIICPS_IXR_ALL_INTR_MASK 0x000002FF /**< All ISR Mask */
/* @} */
/** @name IIC Transfer Size Register
*
* The register's meaning varies according to the operating mode as follows:
* - Master transmitter mode: number of data bytes still not transmitted minus
* one
* - Master receiver mode: number of data bytes that are still expected to be
* received
* - Slave transmitter mode: number of bytes remaining in the FIFO after the
* master terminates the transfer
* - Slave receiver mode: number of valid data bytes in the FIFO
*
* This register is cleared if CLR_FIFO bit in the control register is set.
* Read/Write
* @{
*/
#define XIICPS_TRANS_SIZE_MASK 0x0000003F /**< IIC Transfer Size Mask */
#define XIICPS_FIFO_DEPTH 16 /**< Number of bytes in the FIFO */
#define XIICPS_DATA_INTR_DEPTH 14 /**< Number of bytes at DATA intr */
/* @} */
/** @name IIC Slave Monitor Pause Register
*
* This register is associated with the slave monitor mode of the I2C interface.
* It is meaningful only when the module is in master mode and bit SLVMON in the
* control register is set.
*
* This register defines the pause interval between consecutive attempts to
* address the slave once a write to an I2C address register is done by the
* host. It represents the number of sclk cycles minus one between two attempts.
*
* The reset value of the register is 0, which results in the master repeatedly
* trying to access the slave immediately after unsuccessful attempt.
* Read/Write
* @{
*/
#define XIICPS_SLV_PAUSE_MASK 0x0000000F /**< Slave monitor pause mask */
/* @} */
/** @name IIC Time Out Register
*
* The value of time out register represents the time out interval in number of
* sclk cycles minus one.
*
* When the accessed slave holds the sclk line low for longer than the time out
* period, thus prohibiting the I2C interface in master mode to complete the
* current transfer, an interrupt is generated and TO interrupt flag is set.
*
* The reset value of the register is 0x1f.
* Read/Write
* @{
*/
#define XIICPS_TIME_OUT_MASK 0x000000FF /**< IIC Time Out mask */
#define XIICPS_TO_RESET_VALUE 0x0000001F /**< IIC Time Out reset value */
/* @} */
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define XIicPs_In32 Xil_In32
#define XIicPs_Out32 Xil_Out32
/****************************************************************************/
/**
* Read an IIC register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to select the specific register.
*
* @return The value read from the register.
*
* @note C-Style signature:
* u32 XIicPs_ReadReg(u32 BaseAddress. int RegOffset)
*
******************************************************************************/
#define XIicPs_ReadReg(BaseAddress, RegOffset) \
XIicPs_In32((BaseAddress) + (RegOffset))
/***************************************************************************/
/**
* Write an IIC register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to select the specific register.
* @param RegisterValue is the value to be written to the register.
*
* @return None.
*
* @note C-Style signature:
* void XIicPs_WriteReg(u32 BaseAddress, int RegOffset, u32 RegisterValue)
*
******************************************************************************/
#define XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
XIicPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
/***************************************************************************/
/**
* Read the interrupt enable register.
*
* @param BaseAddress contains the base address of the device.
*
* @return Current bit mask that represents currently enabled interrupts.
*
* @note C-Style signature:
* u32 XIicPs_ReadIER(u32 BaseAddress)
*
******************************************************************************/
#define XIicPs_ReadIER(BaseAddress) \
XIicPs_ReadReg((BaseAddress), XIICPS_IER_OFFSET)
/***************************************************************************/
/**
* Write to the interrupt enable register.
*
* @param BaseAddress contains the base address of the device.
*
* @param IntrMask is the interrupts to be enabled.
*
* @return None.
*
* @note C-Style signature:
* void XIicPs_EnabledInterrupts(u32 BaseAddress, u32 IntrMask)
*
******************************************************************************/
#define XIicPs_EnableInterrupts(BaseAddress, IntrMask) \
XIicPs_WriteReg((BaseAddress), XIICPS_IER_OFFSET, (IntrMask))
/***************************************************************************/
/**
* Disable all interrupts.
*
* @param BaseAddress contains the base address of the device.
*
* @return None.
*
* @note C-Style signature:
* void XIicPs_DisableAllInterrupts(u32 BaseAddress)
*
******************************************************************************/
#define XIicPs_DisableAllInterrupts(BaseAddress) \
XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
XIICPS_IXR_ALL_INTR_MASK)
/***************************************************************************/
/**
* Disable selected interrupts.
*
* @param BaseAddress contains the base address of the device.
*
* @param IntrMask is the interrupts to be disabled.
*
* @return None.
*
* @note C-Style signature:
* void XIicPs_DisableInterrupts(u32 BaseAddress, u32 IntrMask)
*
******************************************************************************/
#define XIicPs_DisableInterrupts(BaseAddress, IntrMask) \
XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
(IntrMask))
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
/*
* Perform reset operation to the I2c interface
*/
void XIicPs_ResetHw(u32 BaseAddr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
quad/sw/system_bsp/ps7_cortexa9_0/include/xil_assert.h 0 → 100644
View file @ fb5bce18
/******************************************************************************
*
* (c) Copyright 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_assert.h
*
* This file contains assert related functions.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/14/09 First release
* </pre>
*
******************************************************************************/
#ifndef XIL_ASSERT_H /* prevent circular inclusions */
#define XIL_ASSERT_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
#define XIL_ASSERT_NONE 0
#define XIL_ASSERT_OCCURRED 1
extern unsigned int Xil_AssertStatus;
extern void Xil_Assert(const char *, int);
/**
* This data type defines a callback to be invoked when an
* assert occurs. The callback is invoked only when asserts are enabled
*/
typedef void (*Xil_AssertCallback) (const char *File, int Line);
/***************** Macros (Inline Functions) Definitions *********************/
#ifndef NDEBUG
/*****************************************************************************/
/**
* This assert macro is to be used for functions that do not return anything
* (void). This in conjunction with the Xil_AssertWait boolean can be used to
* accomodate tests so that asserts which fail allow execution to continue.
*
* @param expression is the expression to evaluate. If it evaluates to
* false, the assert occurs.
*
* @return Returns void unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
* @note None.
*
******************************************************************************/
#define Xil_AssertVoid(Expression) \
{ \
if (Expression) { \
Xil_AssertStatus = XIL_ASSERT_NONE; \
} else { \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return; \
} \
}
/*****************************************************************************/
/**
* This assert macro is to be used for functions that do return a value. This in
* conjunction with the Xil_AssertWait boolean can be used to accomodate tests
* so that asserts which fail allow execution to continue.
*
* @param expression is the expression to evaluate. If it evaluates to false,
* the assert occurs.
*
* @return Returns 0 unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
* @note None.
*
******************************************************************************/
#define Xil_AssertNonvoid(Expression) \
{ \
if (Expression) { \
Xil_AssertStatus = XIL_ASSERT_NONE; \
} else { \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return 0; \
} \
}
/*****************************************************************************/
/**
* Always assert. This assert macro is to be used for functions that do not
* return anything (void). Use for instances where an assert should always
* occur.
*
* @return Returns void unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
* @note None.
*
******************************************************************************/
#define Xil_AssertVoidAlways() \
{ \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return; \
}
/*****************************************************************************/
/**
* Always assert. This assert macro is to be used for functions that do return
* a value. Use for instances where an assert should always occur.
*
* @return Returns void unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
* @note None.
*
******************************************************************************/
#define Xil_AssertNonvoidAlways() \
{ \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return 0; \
}
#else
#define Xil_AssertVoid(Expression)
#define Xil_AssertVoidAlways()
#define Xil_AssertNonvoid(Expression)
#define Xil_AssertNonvoidAlways()
#endif
/************************** Function Prototypes ******************************/
void Xil_AssertSetCallback(Xil_AssertCallback Routine);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
quad/sw/system_bsp/ps7_cortexa9_0/include/xil_cache.h 0 → 100644
View file @ fb5bce18
/******************************************************************************
*
* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_cache.h
*
* Contains required functions for the ARM cache functionality
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a ecm 01/29/10 First release
* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
* APIs.
* </pre>
*
******************************************************************************/
#ifndef XIL_CACHE_H
#define XIL_CACHE_H
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
void Xil_DCacheEnable(void);
void Xil_DCacheDisable(void);
void Xil_DCacheInvalidate(void);
void Xil_DCacheInvalidateRange(unsigned int adr, unsigned len);
void Xil_DCacheFlush(void);
void Xil_DCacheFlushRange(unsigned int adr, unsigned len);
void Xil_ICacheEnable(void);
void Xil_ICacheDisable(void);
void Xil_ICacheInvalidate(void);
void Xil_ICacheInvalidateRange(unsigned int adr, unsigned len);
#ifdef __cplusplus
}
#endif
#endif
quad/sw/system_bsp/ps7_cortexa9_0/include/xil_cache_l.h 0 → 100644
View file @ fb5bce18
/******************************************************************************
*
* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_cache_l.h
*
* Contains L1 and L2 specific functions for the ARM cache functionality
* used by xcache.c. This functionality is being made available here for
* more sophisticated users.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a ecm 01/24/10 First release
* </pre>
*
******************************************************************************/
#ifndef XIL_CACHE_MACH_H
#define XIL_CACHE_MACH_H
#ifdef __cplusplus
extern "C" {
#endif
/************************** Function Prototypes ******************************/
void Xil_DCacheInvalidateLine(unsigned int adr);
void Xil_DCacheFlushLine(unsigned int adr);
void Xil_DCacheStoreLine(unsigned int adr);
void Xil_ICacheInvalidateLine(unsigned int adr);
void Xil_L1DCacheEnable(void);
void Xil_L1DCacheDisable(void);
void Xil_L1DCacheInvalidate(void);
void Xil_L1DCacheInvalidateLine(unsigned int adr);
void Xil_L1DCacheInvalidateRange(unsigned int adr, unsigned len);
void Xil_L1DCacheFlush(void);
void Xil_L1DCacheFlushLine(unsigned int adr);
void Xil_L1DCacheFlushRange(unsigned int adr, unsigned len);
void Xil_L1DCacheStoreLine(unsigned int adr);
void Xil_L1ICacheEnable(void);
void Xil_L1ICacheDisable(void);
void Xil_L1ICacheInvalidate(void);
void Xil_L1ICacheInvalidateLine(unsigned int adr);
void Xil_L1ICacheInvalidateRange(unsigned int adr, unsigned len);
void Xil_L2CacheEnable(void);
void Xil_L2CacheDisable(void);
void Xil_L2CacheInvalidate(void);
void Xil_L2CacheInvalidateLine(unsigned int adr);
void Xil_L2CacheInvalidateRange(unsigned int adr, unsigned len);
void Xil_L2CacheFlush(void);
void Xil_L2CacheFlushLine(unsigned int adr);
void Xil_L2CacheFlushRange(unsigned int adr, unsigned len);
void Xil_L2CacheStoreLine(unsigned int adr);
#ifdef __cplusplus
}
#endif
#endif
quad/sw/system_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h 0 → 100644
View file @ fb5bce18
/******************************************************************************
*
* (c) Copyright 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_cache_vxworks.h
*
* Contains the cache related functions for VxWorks that is wrapped by
* xil_cache.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 12/11/09 Initial release
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef XIL_CACHE_VXWORKS_H
#define XIL_CACHE_VXWORKS_H
#ifdef __cplusplus
extern "C" {
#endif
#include "vxWorks.h"
#include "vxLib.h"
#include "sysLibExtra.h"
#include "cacheLib.h"
#if (CPU_FAMILY==PPC)
#define Xil_DCacheEnable() cacheEnable(DATA_CACHE)
#define Xil_DCacheDisable() cacheDisable(DATA_CACHE)
#define Xil_DCacheInvalidateRange(Addr, Len) \
cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
#define Xil_DCacheFlushRange(Addr, Len) \
cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE)
#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE)
#define Xil_ICacheInvalidateRange(Addr, Len) \
cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
#else
#error "Unknown processor / architecture. Must be PPC for VxWorks."
#endif
#ifdef __cplusplus
}
#endif
#endif
quad/sw/system_bsp/ps7_cortexa9_0/include/xil_errata.h 0 → 100644
View file @ fb5bce18
/*******************************************************************************
*
* (c) Copyright 2013 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_errata.h
*
* This header file contains Cortex A9 and PL310 Errata definitions.
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a srt 04/18/13 First release
* </pre>
*
******************************************************************************/
#ifndef XIL_ERRATA_H
#define XIL_ERRATA_H
#define ENABLE_ARM_ERRATA 1
#ifdef ENABLE_ARM_ERRATA
/* Cortex A9 ARM Errata */
/*
* Errata No: 742230
* Description: DMB operation may be faulty
*/
#define CONFIG_ARM_ERRATA_742230 1
/*
* Errata No: 743622
* Description: Faulty hazard checking in the Store Buffer may lead
* to data corruption.
*/
#define CONFIG_ARM_ERRATA_743622 1
/*
* Errata No: 775420
* Description: A data cache maintenance operation which aborts,
* might lead to deadlock
*/
#define CONFIG_ARM_ERRATA_775420 1
/*
* Errata No: 794073
* Description: Speculative instruction fetches with MMU disabled
* might not comply with architectural requirements
*/
#define CONFIG_ARM_ERRATA_794073 1
/* PL310 L2 Cache Errata */
/*
* Errata No: 588369
* Description: Clean & Invalidate maintenance operations do not
* invalidate clean lines
*/
#define CONFIG_PL310_ERRATA_588369 1
/*
* Errata No: 727915
* Description: Background Clean and Invalidate by Way operation
* can cause data corruption
*/
#define CONFIG_PL310_ERRATA_727915 1
/*
* Errata No: 753970
* Description: Cache sync operation may be faulty
*/
#define CONFIG_PL310_ERRATA_753970 1
#endif /* ENABLE_ARM_ERRATA */
#endif /* XIL_ERRATA_H */
quad/sw/system_bsp/ps7_cortexa9_0/include/xil_exception.h 0 → 100644
View file @ fb5bce18
/******************************************************************************
*
* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_exception.h
*
* This header file contains ARM Cortex A9 specific exception related APIs.
* For exception related functions that can be used across all Xilinx supported
* processors, please use xil_exception.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 1.00a ecm/sdm 11/04/09 First release
* </pre>
*
******************************************************************************/
#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
#define XIL_EXCEPTION_H /* by using protection macros */
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xpseudo_asm.h"
#ifdef __cplusplus
extern "C" {
#endif
/************************** Constant Definitions ****************************/
#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE
#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE
#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
#define XIL_EXCEPTION_ID_FIRST 0
#define XIL_EXCEPTION_ID_RESET 0
#define XIL_EXCEPTION_ID_UNDEFINED_INT 1
#define XIL_EXCEPTION_ID_SWI_INT 2
#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3
#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4
#define XIL_EXCEPTION_ID_IRQ_INT 5
#define XIL_EXCEPTION_ID_FIQ_INT 6
#define XIL_EXCEPTION_ID_LAST 6
/*
* XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
*/
#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
/**************************** Type Definitions ******************************/
/**
* This typedef is the exception handler function.
*/
typedef void (*Xil_ExceptionHandler)(void *data);
typedef void (*Xil_InterruptHandler)(void *data);
/***************** Macros (Inline Functions) Definitions ********************/
/****************************************************************************/
/**
* Enable Exceptions.
*
* @param Mask for exceptions to be enabled.
*
* @return None.
*
* @note If bit is 0, exception is enabled.
* C-Style signature: void Xil_ExceptionEnableMask(Mask);
*
******************************************************************************/
#ifdef __GNUC__
#define Xil_ExceptionEnableMask(Mask) \
mtcpsr(mfcpsr() & ~ (Mask & XIL_EXCEPTION_ALL))
#elif defined (__ICCARM__)
#define Xil_ExceptionEnableMask(Mask) \
{ register unsigned int rval; \
mfcpsr(rval); \
mtcpsr(rval & ~ (Mask & XIL_EXCEPTION_ALL)) ;}
#else
#define Xil_ExceptionEnableMask(Mask) \
{ register unsigned int Reg __asm("cpsr"); \
mtcpsr(Reg & ~ (Mask & XIL_EXCEPTION_ALL)) }
#endif
/****************************************************************************/
/**
* Enable the IRQ exception.
*
* @return None.
*
* @note None.
*
******************************************************************************/
#define Xil_ExceptionEnable() \
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
/****************************************************************************/
/**
* Disable Exceptions.
*
* @param Mask for exceptions to be enabled.
*
* @return None.
*
* @note If bit is 1, exception is disabled.
* C-Style signature: Xil_ExceptionDisableMask(Mask);
*
******************************************************************************/
#ifdef __GNUC__
#define Xil_ExceptionDisableMask(Mask) \
mtcpsr(mfcpsr() | (Mask & XIL_EXCEPTION_ALL))
#elif defined (__ICCARM__)
#define Xil_ExceptionDisableMask(Mask) \
{ register unsigned int rval; \
mfcpsr(rval); \
mtcpsr(rval | (Mask & XIL_EXCEPTION_ALL)) ;}
#else
#define Xil_ExceptionDisableMask(Mask) \
{ register unsigned int Reg __asm("cpsr"); \
mtcpsr(Reg | (Mask & XIL_EXCEPTION_ALL)) }
#endif
/****************************************************************************/
/**
* Disable the IRQ exception.
*
* @return None.
*
* @note None.
*
******************************************************************************/
#define Xil_ExceptionDisable() \
Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
/****************************************************************************/
/**
* Enable nested interrupts by clearing the I and F bits it CPSR
*
* @return None.
*
* @note This macro is supposed to be used from interrupt handlers. In the
* interrupt handler the interrupts are disabled by default (I and F
* are 1). To allow nesting of interrupts, this macro should be
* used. It clears the I and F bits by changing the ARM mode to
* system mode. Once these bits are cleared and provided the
* preemption of interrupt conditions are met in the GIC, nesting of
* interrupts will start happening.
* Caution: This macro must be used with caution. Before calling this
* macro, the user must ensure that the source of the current IRQ
* is appropriately cleared. Otherwise, as soon as we clear the I and
* F bits, there can be an infinite loop of interrupts with an
* eventual crash (all the stack space getting consumed).
******************************************************************************/
#define Xil_EnableNestedInterrupts() \
__asm__ __volatile__ ("mrs lr, spsr"); \
__asm__ __volatile__ ("stmfd sp!, {lr}"); \
__asm__ __volatile__ ("msr cpsr_c, #0x1F"); \
__asm__ __volatile__ ("stmfd sp!, {lr}");
/****************************************************************************/
/**
* Disable the nested interrupts by setting the I and F bits.
*
* @return None.
*
* @note This macro is meant to be called in the interrupt service routines.
* This macro cannot be used independently. It can only be used when
* nesting of interrupts have been enabled by using the macro
* Xil_EnableNestedInterrupts(). In a typical flow, the user first
* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
* point. The user then must call this macro before exiting the interrupt
* service routine. This macro puts the ARM back in IRQ/FIQ mode and
* hence sets back the I and F bits.
******************************************************************************/
#define Xil_DisableNestedInterrupts() \
__asm__ __volatile__ ("ldmfd sp!, {lr}"); \
__asm__ __volatile__ ("msr cpsr_c, #0x92"); \
__asm__ __volatile__ ("ldmfd sp!, {lr}"); \
__asm__ __volatile__ ("msr spsr_cxsf, lr");
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
extern void Xil_ExceptionRegisterHandler(u32 id,
Xil_ExceptionHandler handler,
void *data);
extern void Xil_ExceptionRemoveHandler(u32 id);
extern void Xil_ExceptionInit(void);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XIL_EXCEPTION_H */
quad/sw/system_bsp/ps7_cortexa9_0/include/xil_hal.h 0 → 100644
View file @ fb5bce18
/******************************************************************************
*
* (c) Copyright 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_hal.h
*
* Contains all the HAL header files.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/28/09 Initial release
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef XIL_HAL_H
#define XIL_HAL_H
#include "xil_cache.h"
#include "xil_io.h"
#include "xil_assert.h"
#include "xil_exception.h"
#include "xil_types.h"
#endif
quad/sw/system_bsp/ps7_cortexa9_0/include/xil_io.h 0 → 100644
View file @ fb5bce18
/******************************************************************************
*
* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_io.h
*
* This file contains the interface for the general IO component, which
* encapsulates the Input/Output functions for processors that do not
* require any special I/O handling.
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 1.00a ecm/sdm 10/24/09 First release
* 1.00a sdm 07/21/10 Added Xil_Htonl/s, Xil_Ntohl/s
* 3.07a asa 08/31/12 Added xil_printf.h include
* 3.08a sgd 11/05/12 Reverted SYNC macros definitions
* </pre>
******************************************************************************/
#ifndef XIL_IO_H /* prevent circular inclusions */
#define XIL_IO_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xpseudo_asm.h"
#include "xil_printf.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#if defined __GNUC__
# define SYNCHRONIZE_IO dmb()
# define INST_SYNC isb()
# define DATA_SYNC dsb()
#else
# define SYNCHRONIZE_IO
# define INST_SYNC
# define DATA_SYNC
#endif /* __GNUC__ */
/*****************************************************************************/
/**
*
* Perform an big-endian input operation for a 16-bit memory location
* by reading from the specified address and returning the Value read from
* that address.
*
* @param Addr contains the address to perform the input operation at.
*
* @return The Value read from the specified input address with the
* proper endianness. The return Value has the same endianness
* as that of the processor, i.e. if the processor is
* little-engian, the return Value is the byte-swapped Value read
* from the address.
*
* @note None.
*
******************************************************************************/
#define Xil_In16LE(Addr) Xil_In16(Addr)
/*****************************************************************************/
/**
*
* Perform a big-endian input operation for a 32-bit memory location
* by reading from the specified address and returning the Value read from
* that address.
*
* @param Addr contains the address to perform the input operation at.
*
* @return The Value read from the specified input address with the
* proper endianness. The return Value has the same endianness
* as that of the processor, i.e. if the processor is
* little-engian, the return Value is the byte-swapped Value read
* from the address.
*
*
* @note None.
*
******************************************************************************/
#define Xil_In32LE(Addr) Xil_In32(Addr)
/*****************************************************************************/
/**
*
* Perform a big-endian output operation for a 16-bit memory location
* by writing the specified Value to the specified address.
*
* @param Addr contains the address to perform the output operation at.
* @param Value contains the Value to be output at the specified address.
* The Value has the same endianness as that of the processor.
* If the processor is little-endian, the byte-swapped Value is
* written to the address.
*
*
* @return None
*
* @note None.
*
******************************************************************************/
#define Xil_Out16LE(Addr, Value) Xil_Out16(Addr, Value)
/*****************************************************************************/
/**
*
* Perform a big-endian output operation for a 32-bit memory location
* by writing the specified Value to the specified address.
*
* @param Addr contains the address to perform the output operation at.
* @param Value contains the Value to be output at the specified address.
* The Value has the same endianness as that of the processor.
* If the processor is little-endian, the byte-swapped Value is
* written to the address.
*
* @return None
*
* @note None.
*
******************************************************************************/
#define Xil_Out32LE(Addr, Value) Xil_Out32(Addr, Value)
/*****************************************************************************/
/**
*
* Convert a 32-bit number from host byte order to network byte order.
*
* @param Data the 32-bit number to be converted.
*
* @return The converted 32-bit number in network byte order.
*
* @note None.
*
******************************************************************************/
#define Xil_Htonl(Data) Xil_EndianSwap32(Data)
/*****************************************************************************/
/**
*
* Convert a 16-bit number from host byte order to network byte order.
*
* @param Data the 16-bit number to be converted.
*
* @return The converted 16-bit number in network byte order.
*
* @note None.
*
******************************************************************************/
#define Xil_Htons(Data) Xil_EndianSwap16(Data)
/*****************************************************************************/
/**
*
* Convert a 32-bit number from network byte order to host byte order.
*
* @param Data the 32-bit number to be converted.
*
* @return The converted 32-bit number in host byte order.
*
* @note None.
*
******************************************************************************/
#define Xil_Ntohl(Data) Xil_EndianSwap32(Data)
/*****************************************************************************/
/**
*
* Convert a 16-bit number from network byte order to host byte order.
*
* @param Data the 16-bit number to be converted.
*
* @return The converted 16-bit number in host byte order.
*
* @note None.
*
******************************************************************************/
#define Xil_Ntohs(Data) Xil_EndianSwap16(Data)
/************************** Function Prototypes ******************************/
/* The following functions allow the software to be transportable across
* processors which may use memory mapped I/O or I/O which is mapped into a
* seperate address space.
*/
u8 Xil_In8(u32 Addr);
u16 Xil_In16(u32 Addr);
u32 Xil_In32(u32 Addr);
void Xil_Out8(u32 Addr, u8 Value);
void Xil_Out16(u32 Addr, u16 Value);
void Xil_Out32(u32 Addr, u32 Value);
u16 Xil_In16BE(u32 Addr);
u32 Xil_In32BE(u32 Addr);
void Xil_Out16BE(u32 Addr, u16 Value);
void Xil_Out32BE(u32 Addr, u32 Value);
u16 Xil_EndianSwap16(u16 Data);
u32 Xil_EndianSwap32(u32 Data);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
quad/sw/system_bsp/ps7_cortexa9_0/include/xil_macroback.h 0 → 100644
View file @ fb5bce18
/*********************************************************************/
/**
* (c) Copyright 2010 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information
* of Xilinx, Inc. and is protected under U.S. and
* international copyright and other intellectual property
* laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any
* rights to the materials distributed herewith. Except as
* otherwise provided in a valid license issued to you by
* Xilinx, and to the maximum extent permitted by applicable
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
* (2) Xilinx shall not be liable (whether in contract or tort,
* including negligence, or under any other theory of
* liability) for any loss or damage of any kind or nature
* related to, arising under or in connection with these
* materials, including for any direct, or any indirect,
* special, incidental, or consequential loss or damage
* (including loss of data, profits, goodwill, or any type of
* loss or damage suffered as a result of any action brought
* by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the
* possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-
* safe, or for use in any application requiring fail-safe
* performance, such as life-support or safety devices or
* systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any
* other applications that could lead to death, personal
* injury, or severe property or environmental damage
* (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and
* liability of any use of Xilinx products in Critical
* Applications, subject only to applicable laws and
* regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
* PART OF THIS FILE AT ALL TIMES.
*********************************************************************/
/*********************************************************************/
/**
* @file xil_macroback.h
*
* This header file is meant to bring back the removed _m macros.
* This header file must be included last.
* The following macros are not defined here due to the driver change:
* XGpio_mSetDataDirection
* XGpio_mGetDataReg
* XGpio_mSetDataReg
* XIIC_RESET
* XIIC_CLEAR_STATS
* XSpi_mReset
* XSysAce_mSetCfgAddr
* XSysAce_mIsCfgDone
* XTft_mSetPixel
* XTft_mGetPixel
* XWdtTb_mEnableWdt
* XWdtTb_mDisbleWdt
* XWdtTb_mRestartWdt
* XWdtTb_mGetTimebaseReg
* XWdtTb_mHasReset
*
* Please refer the corresonding driver document for replacement.
*
*********************************************************************/
#ifndef XIL_MACROBACK_H
#define XIL_MACROBACK_H
/*********************************************************************/
/**
* Macros for Driver XCan
*
*********************************************************************/
#ifndef XCan_mReadReg
#define XCan_mReadReg XCan_ReadReg
#endif
#ifndef XCan_mWriteReg
#define XCan_mWriteReg XCan_WriteReg
#endif
#ifndef XCan_mIsTxDone
#define XCan_mIsTxDone XCan_IsTxDone
#endif
#ifndef XCan_mIsTxFifoFull
#define XCan_mIsTxFifoFull XCan_IsTxFifoFull
#endif
#ifndef XCan_mIsHighPriorityBufFull
#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull
#endif
#ifndef XCan_mIsRxEmpty
#define XCan_mIsRxEmpty XCan_IsRxEmpty
#endif
#ifndef XCan_mIsAcceptFilterBusy
#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy
#endif
#ifndef XCan_mCreateIdValue
#define XCan_mCreateIdValue XCan_CreateIdValue
#endif
#ifndef XCan_mCreateDlcValue
#define XCan_mCreateDlcValue XCan_CreateDlcValue
#endif
/*********************************************************************/
/**
* Macros for Driver XDmaCentral
*
*********************************************************************/
#ifndef XDmaCentral_mWriteReg
#define XDmaCentral_mWriteReg XDmaCentral_WriteReg
#endif
#ifndef XDmaCentral_mReadReg
#define XDmaCentral_mReadReg XDmaCentral_ReadReg
#endif
/*********************************************************************/
/**
* Macros for Driver XDsAdc
*
*********************************************************************/
#ifndef XDsAdc_mWriteReg
#define XDsAdc_mWriteReg XDsAdc_WriteReg
#endif
#ifndef XDsAdc_mReadReg
#define XDsAdc_mReadReg XDsAdc_ReadReg
#endif
#ifndef XDsAdc_mIsEmpty
#define XDsAdc_mIsEmpty XDsAdc_IsEmpty
#endif
#ifndef XDsAdc_mSetFstmReg
#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg
#endif
#ifndef XDsAdc_mGetFstmReg
#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg
#endif
#ifndef XDsAdc_mEnableConversion
#define XDsAdc_mEnableConversion XDsAdc_EnableConversion
#endif
#ifndef XDsAdc_mDisableConversion
#define XDsAdc_mDisableConversion XDsAdc_DisableConversion
#endif
#ifndef XDsAdc_mGetFifoOccyReg
#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg
#endif
/*********************************************************************/
/**
* Macros for Driver XDsDac
*
*********************************************************************/
#ifndef XDsDac_mWriteReg
#define XDsDac_mWriteReg XDsDac_WriteReg
#endif
#ifndef XDsDac_mReadReg
#define XDsDac_mReadReg XDsDac_ReadReg
#endif
#ifndef XDsDac_mIsEmpty
#define XDsDac_mIsEmpty XDsDac_IsEmpty
#endif
#ifndef XDsDac_mFifoIsFull
#define XDsDac_mFifoIsFull XDsDac_FifoIsFull
#endif
#ifndef XDsDac_mGetVacancy
#define XDsDac_mGetVacancy XDsDac_GetVacancy
#endif
/*********************************************************************/
/**
* Macros for Driver XEmacLite
*
*********************************************************************/
#ifndef XEmacLite_mReadReg
#define XEmacLite_mReadReg XEmacLite_ReadReg
#endif
#ifndef XEmacLite_mWriteReg
#define XEmacLite_mWriteReg XEmacLite_WriteReg
#endif
#ifndef XEmacLite_mGetTxStatus
#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus
#endif
#ifndef XEmacLite_mSetTxStatus
#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus
#endif
#ifndef XEmacLite_mGetRxStatus
#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus
#endif
#ifndef XEmacLite_mSetRxStatus
#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus
#endif
#ifndef XEmacLite_mIsTxDone
#define XEmacLite_mIsTxDone XEmacLite_IsTxDone
#endif
#ifndef XEmacLite_mIsRxEmpty
#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty
#endif
#ifndef XEmacLite_mNextTransmitAddr
#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr
#endif
#ifndef XEmacLite_mNextReceiveAddr
#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr
#endif
#ifndef XEmacLite_mIsMdioConfigured
#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured
#endif
#ifndef XEmacLite_mIsLoopbackConfigured
#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured
#endif
#ifndef XEmacLite_mGetReceiveDataLength
#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength
#endif
#ifndef XEmacLite_mGetTxActive
#define XEmacLite_mGetTxActive XEmacLite_GetTxActive
#endif
#ifndef XEmacLite_mSetTxActive
#define XEmacLite_mSetTxActive XEmacLite_SetTxActive
#endif
/*********************************************************************/
/**
* Macros for Driver XGpio
*
*********************************************************************/
#ifndef XGpio_mWriteReg
#define XGpio_mWriteReg XGpio_WriteReg
#endif
#ifndef XGpio_mReadReg
#define XGpio_mReadReg XGpio_ReadReg
#endif
/*********************************************************************/
/**
* Macros for Driver XHwIcap
*
*********************************************************************/
#ifndef XHwIcap_mFifoWrite
#define XHwIcap_mFifoWrite XHwIcap_FifoWrite
#endif
#ifndef XHwIcap_mFifoRead
#define XHwIcap_mFifoRead XHwIcap_FifoRead
#endif
#ifndef XHwIcap_mSetSizeReg
#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg
#endif
#ifndef XHwIcap_mGetControlReg
#define XHwIcap_mGetControlReg XHwIcap_GetControlReg
#endif
#ifndef XHwIcap_mStartConfig
#define XHwIcap_mStartConfig XHwIcap_StartConfig
#endif
#ifndef XHwIcap_mStartReadBack
#define XHwIcap_mStartReadBack XHwIcap_StartReadBack
#endif
#ifndef XHwIcap_mGetStatusReg
#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg
#endif
#ifndef XHwIcap_mIsTransferDone
#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone
#endif
#ifndef XHwIcap_mIsDeviceBusy
#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy
#endif
#ifndef XHwIcap_mIntrGlobalEnable
#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable
#endif
#ifndef XHwIcap_mIntrGlobalDisable
#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable
#endif
#ifndef XHwIcap_mIntrGetStatus
#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus
#endif
#ifndef XHwIcap_mIntrDisable
#define XHwIcap_mIntrDisable XHwIcap_IntrDisable
#endif
#ifndef XHwIcap_mIntrEnable
#define XHwIcap_mIntrEnable XHwIcap_IntrEnable
#endif
#ifndef XHwIcap_mIntrGetEnabled
#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled
#endif
#ifndef XHwIcap_mIntrClear
#define XHwIcap_mIntrClear XHwIcap_IntrClear
#endif
#ifndef XHwIcap_mGetWrFifoVacancy
#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy
#endif
#ifndef XHwIcap_mGetRdFifoOccupancy
#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy
#endif
#ifndef XHwIcap_mSliceX2Col
#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col
#endif
#ifndef XHwIcap_mSliceY2Row
#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row
#endif
#ifndef XHwIcap_mSliceXY2Slice
#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice
#endif
#ifndef XHwIcap_mReadReg
#define XHwIcap_mReadReg XHwIcap_ReadReg
#endif
#ifndef XHwIcap_mWriteReg
#define XHwIcap_mWriteReg XHwIcap_WriteReg
#endif
/*********************************************************************/
/**
* Macros for Driver XIic
*
*********************************************************************/
#ifndef XIic_mReadReg
#define XIic_mReadReg XIic_ReadReg
#endif
#ifndef XIic_mWriteReg
#define XIic_mWriteReg XIic_WriteReg
#endif
#ifndef XIic_mEnterCriticalRegion
#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable
#endif
#ifndef XIic_mExitCriticalRegion
#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable
#endif
#ifndef XIIC_GINTR_DISABLE
#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable
#endif
#ifndef XIIC_GINTR_ENABLE
#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable
#endif
#ifndef XIIC_IS_GINTR_ENABLED
#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled
#endif
#ifndef XIIC_WRITE_IISR
#define XIIC_WRITE_IISR XIic_WriteIisr
#endif
#ifndef XIIC_READ_IISR
#define XIIC_READ_IISR XIic_ReadIisr
#endif
#ifndef XIIC_WRITE_IIER
#define XIIC_WRITE_IIER XIic_WriteIier
#endif
#ifndef XIic_mClearIisr
#define XIic_mClearIisr XIic_ClearIisr
#endif
#ifndef XIic_mSend7BitAddress
#define XIic_mSend7BitAddress XIic_Send7BitAddress
#endif
#ifndef XIic_mDynSend7BitAddress
#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress
#endif
#ifndef XIic_mDynSendStartStopAddress
#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress
#endif
#ifndef XIic_mDynSendStop
#define XIic_mDynSendStop XIic_DynSendStop
#endif
#ifndef XIic_mSend10BitAddrByte1
#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1
#endif
#ifndef XIic_mSend10BitAddrByte2
#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2
#endif
#ifndef XIic_mSend7BitAddr
#define XIic_mSend7BitAddr XIic_Send7BitAddr
#endif
#ifndef XIic_mDisableIntr
#define XIic_mDisableIntr XIic_DisableIntr
#endif
#ifndef XIic_mEnableIntr
#define XIic_mEnableIntr XIic_EnableIntr
#endif
#ifndef XIic_mClearIntr
#define XIic_mClearIntr XIic_ClearIntr
#endif
#ifndef XIic_mClearEnableIntr
#define XIic_mClearEnableIntr XIic_ClearEnableIntr
#endif
#ifndef XIic_mFlushRxFifo
#define XIic_mFlushRxFifo XIic_FlushRxFifo
#endif
#ifndef XIic_mFlushTxFifo
#define XIic_mFlushTxFifo XIic_FlushTxFifo
#endif
#ifndef XIic_mReadRecvByte
#define XIic_mReadRecvByte XIic_ReadRecvByte
#endif
#ifndef XIic_mWriteSendByte
#define XIic_mWriteSendByte XIic_WriteSendByte
#endif
#ifndef XIic_mSetControlRegister
#define XIic_mSetControlRegister XIic_SetControlRegister
#endif
/*********************************************************************/
/**
* Macros for Driver XIntc
*
*********************************************************************/
#ifndef XIntc_mMasterEnable
#define XIntc_mMasterEnable XIntc_MasterEnable
#endif
#ifndef XIntc_mMasterDisable
#define XIntc_mMasterDisable XIntc_MasterDisable
#endif
#ifndef XIntc_mEnableIntr
#define XIntc_mEnableIntr XIntc_EnableIntr
#endif
#ifndef XIntc_mDisableIntr
#define XIntc_mDisableIntr XIntc_DisableIntr
#endif
#ifndef XIntc_mAckIntr
#define XIntc_mAckIntr XIntc_AckIntr
#endif
#ifndef XIntc_mGetIntrStatus
#define XIntc_mGetIntrStatus XIntc_GetIntrStatus
#endif
/*********************************************************************/
/**
* Macros for Driver XLlDma
*
*********************************************************************/
#ifndef XLlDma_mBdRead
#define XLlDma_mBdRead XLlDma_BdRead
#endif
#ifndef XLlDma_mBdWrite
#define XLlDma_mBdWrite XLlDma_BdWrite
#endif
#ifndef XLlDma_mWriteReg
#define XLlDma_mWriteReg XLlDma_WriteReg
#endif
#ifndef XLlDma_mReadReg
#define XLlDma_mReadReg XLlDma_ReadReg
#endif
#ifndef XLlDma_mBdClear
#define XLlDma_mBdClear XLlDma_BdClear
#endif
#ifndef XLlDma_mBdSetStsCtrl
#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl
#endif
#ifndef XLlDma_mBdGetStsCtrl
#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl
#endif
#ifndef XLlDma_mBdSetLength
#define XLlDma_mBdSetLength XLlDma_BdSetLength
#endif
#ifndef XLlDma_mBdGetLength
#define XLlDma_mBdGetLength XLlDma_BdGetLength
#endif
#ifndef XLlDma_mBdSetId
#define XLlDma_mBdSetId XLlDma_BdSetId
#endif
#ifndef XLlDma_mBdGetId
#define XLlDma_mBdGetId XLlDma_BdGetId
#endif
#ifndef XLlDma_mBdSetBufAddr
#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr
#endif
#ifndef XLlDma_mBdGetBufAddr
#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr
#endif
#ifndef XLlDma_mBdGetLength
#define XLlDma_mBdGetLength XLlDma_BdGetLength
#endif
#ifndef XLlDma_mGetTxRing
#define XLlDma_mGetTxRing XLlDma_GetTxRing
#endif
#ifndef XLlDma_mGetRxRing
#define XLlDma_mGetRxRing XLlDma_GetRxRing
#endif
#ifndef XLlDma_mGetCr
#define XLlDma_mGetCr XLlDma_GetCr
#endif
#ifndef XLlDma_mSetCr
#define XLlDma_mSetCr XLlDma_SetCr
#endif
#ifndef XLlDma_mBdRingCntCalc
#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc
#endif
#ifndef XLlDma_mBdRingMemCalc
#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc
#endif
#ifndef XLlDma_mBdRingGetCnt
#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt
#endif
#ifndef XLlDma_mBdRingGetFreeCnt
#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt
#endif
#ifndef XLlDma_mBdRingSnapShotCurrBd
#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd
#endif
#ifndef XLlDma_mBdRingNext
#define XLlDma_mBdRingNext XLlDma_BdRingNext
#endif
#ifndef XLlDma_mBdRingPrev
#define XLlDma_mBdRingPrev XLlDma_BdRingPrev
#endif
#ifndef XLlDma_mBdRingGetSr
#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr
#endif
#ifndef XLlDma_mBdRingSetSr
#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr
#endif
#ifndef XLlDma_mBdRingGetCr
#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr
#endif
#ifndef XLlDma_mBdRingSetCr
#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr
#endif
#ifndef XLlDma_mBdRingBusy
#define XLlDma_mBdRingBusy XLlDma_BdRingBusy
#endif
#ifndef XLlDma_mBdRingIntEnable
#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable
#endif
#ifndef XLlDma_mBdRingIntDisable
#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable
#endif
#ifndef XLlDma_mBdRingIntGetEnabled
#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled
#endif
#ifndef XLlDma_mBdRingGetIrq
#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq
#endif
#ifndef XLlDma_mBdRingAckIrq
#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq
#endif
/*********************************************************************/
/**
* Macros for Driver XMbox
*
*********************************************************************/
#ifndef XMbox_mWriteReg
#define XMbox_mWriteReg XMbox_WriteReg
#endif
#ifndef XMbox_mReadReg
#define XMbox_mReadReg XMbox_ReadReg
#endif
#ifndef XMbox_mWriteMBox
#define XMbox_mWriteMBox XMbox_WriteMBox
#endif
#ifndef XMbox_mReadMBox
#define XMbox_mReadMBox XMbox_ReadMBox
#endif
#ifndef XMbox_mFSLReadMBox
#define XMbox_mFSLReadMBox XMbox_FSLReadMBox
#endif
#ifndef XMbox_mFSLWriteMBox
#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox
#endif
#ifndef XMbox_mFSLIsEmpty
#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty
#endif
#ifndef XMbox_mFSLIsFull
#define XMbox_mFSLIsFull XMbox_FSLIsFull
#endif
#ifndef XMbox_mIsEmpty
#define XMbox_mIsEmpty XMbox_IsEmptyHw
#endif
#ifndef XMbox_mIsFull
#define XMbox_mIsFull XMbox_IsFullHw
#endif
/*********************************************************************/
/**
* Macros for Driver XMpmc
*
*********************************************************************/
#ifndef XMpmc_mReadReg
#define XMpmc_mReadReg XMpmc_ReadReg
#endif
#ifndef XMpmc_mWriteReg
#define XMpmc_mWriteReg XMpmc_WriteReg
#endif
/*********************************************************************/
/**
* Macros for Driver XMutex
*
*********************************************************************/
#ifndef XMutex_mWriteReg
#define XMutex_mWriteReg XMutex_WriteReg
#endif
#ifndef XMutex_mReadReg
#define XMutex_mReadReg XMutex_ReadReg
#endif
/*********************************************************************/
/**
* Macros for Driver XPcie
*
*********************************************************************/
#ifndef XPcie_mReadReg
#define XPcie_mReadReg XPcie_ReadReg
#endif
#ifndef XPcie_mWriteReg
#define XPcie_mWriteReg XPcie_WriteReg
#endif
/*********************************************************************/
/**
* Macros for Driver XSpi
*
*********************************************************************/
#ifndef XSpi_mIntrGlobalEnable
#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable
#endif
#ifndef XSpi_mIntrGlobalDisable
#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable
#endif
#ifndef XSpi_mIsIntrGlobalEnabled
#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled
#endif
#ifndef XSpi_mIntrGetStatus
#define XSpi_mIntrGetStatus XSpi_IntrGetStatus
#endif
#ifndef XSpi_mIntrClear
#define XSpi_mIntrClear XSpi_IntrClear
#endif
#ifndef XSpi_mIntrEnable
#define XSpi_mIntrEnable XSpi_IntrEnable
#endif
#ifndef XSpi_mIntrDisable
#define XSpi_mIntrDisable XSpi_IntrDisable
#endif
#ifndef XSpi_mIntrGetEnabled
#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled
#endif
#ifndef XSpi_mSetControlReg
#define XSpi_mSetControlReg XSpi_SetControlReg
#endif
#ifndef XSpi_mGetControlReg
#define XSpi_mGetControlReg XSpi_GetControlReg
#endif
#ifndef XSpi_mGetStatusReg
#define XSpi_mGetStatusReg XSpi_GetStatusReg
#endif
#ifndef XSpi_mSetSlaveSelectReg
#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg
#endif
#ifndef XSpi_mGetSlaveSelectReg
#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg
#endif
#ifndef XSpi_mEnable
#define XSpi_mEnable XSpi_Enable
#endif
#ifndef XSpi_mDisable
#define XSpi_mDisable XSpi_Disable
#endif
/*********************************************************************/
/**
* Macros for Driver XSysAce
*
*********************************************************************/
#ifndef XSysAce_mGetControlReg
#define XSysAce_mGetControlReg XSysAce_GetControlReg
#endif
#ifndef XSysAce_mSetControlReg
#define XSysAce_mSetControlReg XSysAce_SetControlReg
#endif
#ifndef XSysAce_mOrControlReg
#define XSysAce_mOrControlReg XSysAce_OrControlReg
#endif
#ifndef XSysAce_mAndControlReg
#define XSysAce_mAndControlReg XSysAce_AndControlReg
#endif
#ifndef XSysAce_mGetErrorReg
#define XSysAce_mGetErrorReg XSysAce_GetErrorReg
#endif
#ifndef XSysAce_mGetStatusReg
#define XSysAce_mGetStatusReg XSysAce_GetStatusReg
#endif
#ifndef XSysAce_mWaitForLock
#define XSysAce_mWaitForLock XSysAce_WaitForLock
#endif
#ifndef XSysAce_mEnableIntr
#define XSysAce_mEnableIntr XSysAce_EnableIntr
#endif
#ifndef XSysAce_mDisableIntr
#define XSysAce_mDisableIntr XSysAce_DisableIntr
#endif
#ifndef XSysAce_mIsReadyForCmd
#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd
#endif
#ifndef XSysAce_mIsMpuLocked
#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked
#endif
#ifndef XSysAce_mIsIntrEnabled
#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled
#endif
/*********************************************************************/
/**
* Macros for Driver XSysMon
*
*********************************************************************/
#ifndef XSysMon_mIsEventSamplingModeSet
#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet
#endif
#ifndef XSysMon_mIsDrpBusy
#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy
#endif
#ifndef XSysMon_mIsDrpLocked
#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked
#endif
#ifndef XSysMon_mRawToTemperature
#define XSysMon_mRawToTemperature XSysMon_RawToTemperature
#endif
#ifndef XSysMon_mRawToVoltage
#define XSysMon_mRawToVoltage XSysMon_RawToVoltage
#endif
#ifndef XSysMon_mTemperatureToRaw
#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw
#endif
#ifndef XSysMon_mVoltageToRaw
#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw
#endif
#ifndef XSysMon_mReadReg
#define XSysMon_mReadReg XSysMon_ReadReg
#endif
#ifndef XSysMon_mWriteReg
#define XSysMon_mWriteReg XSysMon_WriteReg
#endif
/*********************************************************************/
/**
* Macros for Driver XTmrCtr
*
*********************************************************************/
#ifndef XTimerCtr_mReadReg
#define XTimerCtr_mReadReg XTimerCtr_ReadReg
#endif
#ifndef XTmrCtr_mWriteReg
#define XTmrCtr_mWriteReg XTmrCtr_WriteReg
#endif
#ifndef XTmrCtr_mSetControlStatusReg
#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg
#endif
#ifndef XTmrCtr_mGetControlStatusReg
#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg
#endif
#ifndef XTmrCtr_mGetTimerCounterReg
#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg
#endif
#ifndef XTmrCtr_mSetLoadReg
#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg
#endif
#ifndef XTmrCtr_mGetLoadReg
#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg
#endif
#ifndef XTmrCtr_mEnable
#define XTmrCtr_mEnable XTmrCtr_Enable
#endif
#ifndef XTmrCtr_mDisable
#define XTmrCtr_mDisable XTmrCtr_Disable
#endif
#ifndef XTmrCtr_mEnableIntr
#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr
#endif
#ifndef XTmrCtr_mDisableIntr
#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr
#endif
#ifndef XTmrCtr_mLoadTimerCounterReg
#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg
#endif
#ifndef XTmrCtr_mHasEventOccurred
#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred
#endif
/*********************************************************************/
/**
* Macros for Driver XUartLite
*
*********************************************************************/
#ifndef XUartLite_mUpdateStats
#define XUartLite_mUpdateStats XUartLite_UpdateStats
#endif
#ifndef XUartLite_mWriteReg
#define XUartLite_mWriteReg XUartLite_WriteReg
#endif
#ifndef XUartLite_mReadReg
#define XUartLite_mReadReg XUartLite_ReadReg
#endif
#ifndef XUartLite_mClearStats
#define XUartLite_mClearStats XUartLite_ClearStats
#endif
#ifndef XUartLite_mSetControlReg
#define XUartLite_mSetControlReg XUartLite_SetControlReg
#endif
#ifndef XUartLite_mGetStatusReg
#define XUartLite_mGetStatusReg XUartLite_GetStatusReg
#endif
#ifndef XUartLite_mIsReceiveEmpty
#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty
#endif
#ifndef XUartLite_mIsTransmitFull
#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull
#endif
#ifndef XUartLite_mIsIntrEnabled
#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled
#endif
#ifndef XUartLite_mEnableIntr
#define XUartLite_mEnableIntr XUartLite_EnableIntr
#endif
#ifndef XUartLite_mDisableIntr
#define XUartLite_mDisableIntr XUartLite_DisableIntr
#endif
/*********************************************************************/
/**
* Macros for Driver XUartNs550
*
*********************************************************************/
#ifndef XUartNs550_mUpdateStats
#define XUartNs550_mUpdateStats XUartNs550_UpdateStats
#endif
#ifndef XUartNs550_mReadReg
#define XUartNs550_mReadReg XUartNs550_ReadReg
#endif
#ifndef XUartNs550_mWriteReg
#define XUartNs550_mWriteReg XUartNs550_WriteReg
#endif
#ifndef XUartNs550_mClearStats
#define XUartNs550_mClearStats XUartNs550_ClearStats
#endif
#ifndef XUartNs550_mGetLineStatusReg
#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg
#endif
#ifndef XUartNs550_mGetLineControlReg
#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg
#endif
#ifndef XUartNs550_mSetLineControlReg
#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg
#endif
#ifndef XUartNs550_mEnableIntr
#define XUartNs550_mEnableIntr XUartNs550_EnableIntr
#endif
#ifndef XUartNs550_mDisableIntr
#define XUartNs550_mDisableIntr XUartNs550_DisableIntr
#endif
#ifndef XUartNs550_mIsReceiveData
#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData
#endif
#ifndef XUartNs550_mIsTransmitEmpty
#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty
#endif
/*********************************************************************/
/**
* Macros for Driver XUsb
*
*********************************************************************/
#ifndef XUsb_mReadReg
#define XUsb_mReadReg XUsb_ReadReg
#endif
#ifndef XUsb_mWriteReg
#define XUsb_mWriteReg XUsb_WriteReg
#endif
#endif
quad/sw/system_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h 0 → 100644
View file @ fb5bce18
/******************************************************************************
*
* (c) Copyright 2013 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xil_misc_psreset_api.h
*
* This file contains the various register defintions and function prototypes for
* implementing the reset functionality of zynq ps devices
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00b kpc 03/07/13 First release.
* </pre>
*
******************************************************************************/
#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */
#define XIL_MISC_RESET_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
#define XDDRC_CTRL_BASEADDR 0xF8006000
#define XSLCR_BASEADDR 0xF8000000
/**< OCM configuration register */
#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x910)
/**< SLCR unlock register */
#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x8)
/**< SLCR GEM0 rx clock control register */
#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x138)
/**< SLCR GEM1 rx clock control register */
#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x13C)
/**< SLCR GEM0 clock control register */
#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x140)
/**< SLCR GEM1 clock control register */
#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x144)
/**< SLCR SMC clock control register */
#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x148)
/**< SLCR GEM reset control register */
#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x214)
/**< SLCR USB0 clock control register */
#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x130)
/**< SLCR USB1 clock control register */
#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x134)
/**< SLCR USB1 reset control register */
#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x210)
/**< SLCR SMC reset control register */
#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x234)
/**< SLCR Level shifter enable register */
#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x900)
/**< SLCR ARM pll control register */
#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x100)
/**< SLCR DDR pll control register */
#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x104)
/**< SLCR IO pll control register */
#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x108)
/**< SLCR ARM pll configuration register */
#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x110)
/**< SLCR DDR pll configuration register */
#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x114)
/**< SLCR IO pll configuration register */
#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x118)
/**< SLCR ARM clock control register */
#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x120)
/**< SLCR DDR clock control register */
#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x124)
/**< SLCR MIO pin address register */
#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x700)
/**< SLCR DMAC reset control address register */
#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x20C)
/**< SLCR USB reset control address register */
#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x210)
/**< SLCR GEM reset control address register */
#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x214)
/**< SLCR SDIO reset control address register */
#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x218)
/**< SLCR SPI reset control address register */
#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x21C)
/**< SLCR CAN reset control address register */
#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x220)
/**< SLCR I2C reset control address register */
#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x224)
/**< SLCR UART reset control address register */
#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x228)
/**< SLCR GPIO reset control address register */
#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x22C)
/**< SLCR LQSPI reset control address register */
#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x230)
/**< SLCR SMC reset control address register */
#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x234)
/**< SLCR OCM reset control address register */
#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x238)
/**< SMC mem controller clear config register */
#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0C
/**< SMC idlecount configuration register */
#define XSMC_REFRESH_PERIOD_0_OFFSET 0x20
#define XSMC_REFRESH_PERIOD_1_OFFSET 0x24
/**< SMC ECC configuration register */
#define XSMC_ECC_MEMCFG1_OFFSET 0x404
/**< SMC ECC command 1 register */
#define XSMC_ECC_MEMCMD1_OFFSET 0x404
/**< SMC ECC command 2 register */
#define XSMC_ECC_MEMCMD2_OFFSET 0x404
/**< SLCR unlock code */
#define XSLCR_UNLOCK_CODE 0x0000DF0D
/**< SMC mem clear configuration mask */
#define XSMC_MEMC_CLR_CONFIG_MASK 0x5F
/**< SMC ECC memconfig 1 reset value */
#define XSMC_ECC_MEMCFG1_RESET_VAL 0x43
/**< SMC ECC memcommand 1 reset value */
#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080
/**< SMC ECC memcommand 2 reset value */
#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585
/**< DDR controller reset bit mask */
#define XDDRPS_CTRL_RESET_MASK 0x1
/**< SLCR OCM configuration reset value*/
#define XSLCR_OCM_CFG_RESETVAL 0x8
/**< SLCR OCM bank selection mask*/
#define XSLCR_OCM_CFG_HIADDR_MASK 0xF
/**< SLCR level shifter enable mask*/
#define XSLCR_LVL_SHFTR_EN_MASK 0xF
/**< SLCR PLL register reset values */
#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008
#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008
#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008
#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0
#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0
#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0
#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400
#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003
/**< SLCR MIO register default values */
#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601
#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601
/**< SLCR Reset control registers default values */
#define XSLCR_DMAC_RST_CTRL_VAL 0x1
#define XSLCR_GEM_RST_CTRL_VAL 0xF3
#define XSLCR_USB_RST_CTRL_VAL 0x3
#define XSLCR_I2C_RST_CTRL_VAL 0x3
#define XSLCR_SPI_RST_CTRL_VAL 0xF
#define XSLCR_UART_RST_CTRL_VAL 0xF
#define XSLCR_QSPI_RST_CTRL_VAL 0x3
#define XSLCR_GPIO_RST_CTRL_VAL 0x1
#define XSLCR_SMC_RST_CTRL_VAL 0x3
#define XSLCR_OCM_RST_CTRL_VAL 0x1
#define XSLCR_SDIO_RST_CTRL_VAL 0x33
#define XSLCR_CAN_RST_CTRL_VAL 0x3
/**************************** Type Definitions *******************************/
/* the following data type is used to hold a null terminated version string
* consisting of the following format, "X.YYX"
*/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*
* Performs reset operation to the ddr interface
*/
void XDdr_ResetHw();
/*
* Map the ocm region to post bootrom state
*/
void XOcm_Remap();
/*
* Performs the smc interface reset
*/
void XSmc_ResetHw(u32 BaseAddress);
/*
* updates the MIO registers with reset values
*/
void XSlcr_MioWriteResetValues();
/*
* updates the PLL and clock registers with reset values
*/
void XSlcr_PllWriteResetValues();
/*
* Disables the level shifters
*/
void XSlcr_DisableLevelShifters();
/*
* provides softreset to the GPIO interface
*/
void XSlcr_GpioPsReset(void);
/*
* provides softreset to the DMA interface
*/
void XSlcr_DmaPsReset(void);
/*
* provides softreset to the SMC interface
*/
void XSlcr_SmcPsReset(void);
/*
* provides softreset to the CAN interface
*/
void XSlcr_CanPsReset(void);
/*
* provides softreset to the Uart interface
*/
void XSlcr_UartPsReset(void);
/*
* provides softreset to the I2C interface
*/
void XSlcr_I2cPsReset(void);
/*
* provides softreset to the SPI interface
*/
void XSlcr_SpiPsReset(void);
/*
* provides softreset to the QSPI interface
*/
void XSlcr_QspiPsReset(void);
/*
* provides softreset to the USB interface
*/
void XSlcr_UsbPsReset(void);
/*
* provides softreset to the GEM interface
*/
void XSlcr_EmacPsReset(void);
/*
* provides softreset to the OCM interface
*/
void XSlcr_OcmReset(void);
#ifdef __cplusplus
}
#endif
#endif /* XIL_MISC_RESET_H */
quad/sw/system_bsp/ps7_cortexa9_0/include/xil_mmu.h 0 → 100644
View file @ fb5bce18
/******************************************************************************
*
* (c) Copyright 2012 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
******************************************************************************/
/*****************************************************************************/
/**
* @file xil_mmu.h
*
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 1.00a sdm 01/12/12 Initial version
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#ifndef XIL_MMU_H
#define XIL_MMU_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/***************************** Include Files *********************************/
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Constant Definitions *****************************/
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
void Xil_SetTlbAttributes(u32 addr, u32 attrib);
void Xil_EnableMMU(void);
void Xil_DisableMMU(void);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XIL_MMU_H */
quad/sw/system_bsp/ps7_cortexa9_0/include/xil_printf.h 0 → 100644
View file @ fb5bce18
#ifndef XIL_PRINTF_H
#define XIL_PRINTF_H
#ifdef __cplusplus
extern "C" {
#endif
#include <ctype.h>
#include <string.h>
#include <stdarg.h>
#include "xparameters.h"
#include "xil_types.h"
/*----------------------------------------------------*/
/* Use the following parameter passing structure to */
/* make xil_printf re-entrant. */
/*----------------------------------------------------*/
struct params_s;
/*---------------------------------------------------*/
/* The purpose of this routine is to output data the */
/* same as the standard printf function without the */
/* overhead most run-time libraries involve. Usually */
/* the printf brings in many kilobytes of code and */
/* that is unacceptable in most embedded systems. */
/*---------------------------------------------------*/
typedef char* charptr;
typedef int (*func_ptr)(int c);
/* */
void padding( const int l_flag, struct params_s *par);
void outs( charptr lp, struct params_s *par);
void outnum( const long n, const long base, struct params_s *par);
int getnum( charptr* linep);
void xil_printf( const char *ctrl1, ...);
void print( const char *ptr);
void outbyte (char);
char inbyte(void);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
quad/sw/system_bsp/ps7_cortexa9_0/include/xil_testcache.h 0 → 100644
View file @ fb5bce18
/******************************************************************************
*
*
* (c) Copyright 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_testcache.h
*
* This file contains utility functions to test cache.
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a hbm 07/29/09 First release
*
******************************************************************************/
#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */
#define XIL_TESTCACHE_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
extern int Xil_TestDCacheRange(void);
extern int Xil_TestDCacheAll(void);
extern int Xil_TestICacheRange(void);
extern int Xil_TestICacheAll(void);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
quad/sw/system_bsp/ps7_cortexa9_0/include/xil_testio.h 0 → 100644
View file @ fb5bce18
/******************************************************************************
*
* (c) Copyright 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_testmemend.h
*
* This file contains utility functions to teach endian related memory
* IO functions.
*
* <b>Memory test description</b>
*
* A subset of the memory tests can be selected or all of the tests can be run
* in order. If there is an error detected by a subtest, the test stops and the
* failure code is returned. Further tests are not run even if all of the tests
* are selected.
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00 hbm 08/05/09 First release
* </pre>
*
******************************************************************************/
#ifndef XIL_TESTIO_H /* prevent circular inclusions */
#define XIL_TESTIO_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
/************************** Constant Definitions *****************************/
#define XIL_TESTIO_DEFAULT 0
#define XIL_TESTIO_LE 1
#define XIL_TESTIO_BE 2
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
extern int Xil_TestIO8(u8 *Addr, int Len, u8 Value);
extern int Xil_TestIO16(u16 *Addr, int Len, u16 Value, int Kind, int Swap);
extern int Xil_TestIO32(u32 *Addr, int Len, u32 Value, int Kind, int Swap);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
quad/sw/system_bsp/ps7_cortexa9_0/include/xil_testmem.h 0 → 100644
View file @ fb5bce18
/******************************************************************************
*
*
* (c) Copyright 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_testmem.h
*
* This file contains utility functions to test memory.
*
* <b>Memory test description</b>
*
* A subset of the memory tests can be selected or all of the tests can be run
* in order. If there is an error detected by a subtest, the test stops and the
* failure code is returned. Further tests are not run even if all of the tests
* are selected.
*
* Subtest descriptions:
* <pre>
* XIL_TESTMEM_ALLMEMTESTS:
* Runs all of the following tests
*
* XIL_TESTMEM_INCREMENT:
* Incrementing Value Test.
* This test starts at 'XIL_TESTMEM_INIT_VALUE' and uses the
* incrementing value as the test value for memory.
*
* XIL_TESTMEM_WALKONES:
* Walking Ones Test.
* This test uses a walking '1' as the test value for memory.
* location 1 = 0x00000001
* location 2 = 0x00000002
* ...
*
* XIL_TESTMEM_WALKZEROS:
* Walking Zero's Test.
* This test uses the inverse value of the walking ones test
* as the test value for memory.
* location 1 = 0xFFFFFFFE
* location 2 = 0xFFFFFFFD
* ...
*
* XIL_TESTMEM_INVERSEADDR:
* Inverse Address Test.
* This test uses the inverse of the address of the location under test
* as the test value for memory.
*
* XIL_TESTMEM_FIXEDPATTERN:
* Fixed Pattern Test.
* This test uses the provided patters as the test value for memory.
* If zero is provided as the pattern the test uses '0xDEADBEEF".
* </pre>
*
* <i>WARNING</i>
*
* The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces
* have been set up.
*
* The address provided to the memory tests is not checked for
* validity except for the NULL case. It is possible to provide a code-space
* pointer for this test to start with and ultimately destroy executable code
* causing random failures.
*
* @note
*
* Used for spaces where the address range of the region is smaller than
* the data width. If the memory range is greater than 2 ** width,
* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
* repeat on a boundry of a power of two making it more difficult to detect
* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
* tests suffer the same problem. Ideally, if large blocks of memory are to be
* tested, break them up into smaller regions of memory to allow the test
* patterns used not to repeat over the region tested.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a hbm 08/25/09 First release
* </pre>
*
******************************************************************************/
#ifndef XIL_TESTMEM_H /* prevent circular inclusions */
#define XIL_TESTMEM_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/* xutil_memtest defines */
#define XIL_TESTMEM_INIT_VALUE 1
/** @name Memory subtests
* @{
*/
/**
* See the detailed description of the subtests in the file description.
*/
#define XIL_TESTMEM_ALLMEMTESTS 0
#define XIL_TESTMEM_INCREMENT 1
#define XIL_TESTMEM_WALKONES 2
#define XIL_TESTMEM_WALKZEROS 3
#define XIL_TESTMEM_INVERSEADDR 4
#define XIL_TESTMEM_FIXEDPATTERN 5
#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN
/* @} */
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/* xutil_testmem prototypes */
extern int Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
extern int Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
extern int Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
quad/sw/system_bsp/ps7_cortexa9_0/include/xil_types.h 0 → 100644
View file @ fb5bce18
/******************************************************************************
*
* (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_types.h
*
* This file contains basic types for Xilinx software IP.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/14/09 First release
* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
* </pre>
*
******************************************************************************/
#ifndef XIL_TYPES_H /* prevent circular inclusions */
#define XIL_TYPES_H /* by using protection macros */
/************************** Constant Definitions *****************************/
#ifndef TRUE
# define TRUE 1
#endif
#ifndef FALSE
# define FALSE 0
#endif
#ifndef NULL
#define NULL 0
#endif
#define XIL_COMPONENT_IS_READY 0x11111111 /**< component has been initialized */
#define XIL_COMPONENT_IS_STARTED 0x22222222 /**< component has been started */
/** @name New types
* New simple types.
* @{
*/
#ifndef __KERNEL__
#ifndef XBASIC_TYPES_H
/**
* guarded against xbasic_types.h.
*/
typedef unsigned char u8;
typedef unsigned short u16;
typedef unsigned long u32;
#define __XUINT64__
typedef struct
{
u32 Upper;
u32 Lower;
} Xuint64;
/*****************************************************************************/
/**
* Return the most significant half of the 64 bit data type.
*
* @param x is the 64 bit word.
*
* @return The upper 32 bits of the 64 bit word.
*
* @note None.
*
******************************************************************************/
#define XUINT64_MSW(x) ((x).Upper)
/*****************************************************************************/
/**
* Return the least significant half of the 64 bit data type.
*
* @param x is the 64 bit word.
*
* @return The lower 32 bits of the 64 bit word.
*
* @note None.
*
******************************************************************************/
#define XUINT64_LSW(x) ((x).Lower)
#endif /* XBASIC_TYPES_H */
/**
* xbasic_types.h does not typedef s* or u64
*/
typedef unsigned long long u64;
typedef char s8;
typedef short s16;
typedef long s32;
typedef long long s64;
#else
#include <linux/types.h>
#endif
/*@}*/
/************************** Constant Definitions *****************************/
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
#ifndef NULL
#define NULL 0
#endif
#endif /* end of protection macro */