quad/sw/modular_quad_pid/src/uart.c

+/*
+ * uart.c
+ *
+ *  Created on: Nov 10, 2014
+ *      Author: ucart
+ */
+
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include "uart.h"
+#include <xuartps.h>
+#include <xstatus.h>
+
+// Global PS's
+XUartPs* _Uart0PS;
+XUartPs* _Uart1PS;
+
+//This is copied from xuart driver
+/***************************************************/
+
+#define XUARTPS_MAX_BAUD_ERROR_RATE		 3	/* max % error allowed */
+int XUartPs_SetBaudRate_ours(XUartPs *InstancePtr, u32 BaudRate)
+{
+	u8 IterBAUDDIV;		/* Iterator for available baud divisor values */
+	u32 BRGR_Value;		/* Calculated value for baud rate generator */
+	u32 CalcBaudRate;	/* Calculated baud rate */
+	u32 BaudError;		/* Diff between calculated and requested baud rate */
+	u32 Best_BRGR = 0;	/* Best value for baud rate generator */
+	u8 Best_BAUDDIV = 0;	/* Best value for baud divisor */
+	u32 Best_Error = 0xFFFFFFFF;
+	u32 PercentError;
+	u32 ModeReg;
+	u32 InputClk;
+
+	/*
+	 * Asserts validate the input arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	//Xil_AssertNonvoid(BaudRate <= XUARTPS_MAX_RATE);
+	Xil_AssertNonvoid(BaudRate >= XUARTPS_MIN_RATE);
+
+	/*
+	 * Make sure the baud rate is not impossilby large.
+	 * Fastest possible baud rate is Input Clock / 2.
+	 */
+	if ((BaudRate * 2) > InstancePtr->Config.InputClockHz) {
+		return XST_UART_BAUD_ERROR;
+	}
+	/*
+	 * Check whether the input clock is divided by 8
+	 */
+	ModeReg = XUartPs_ReadReg( InstancePtr->Config.BaseAddress,
+				 XUARTPS_MR_OFFSET);
+
+	InputClk = InstancePtr->Config.InputClockHz;
+	if(ModeReg & XUARTPS_MR_CLKSEL) {
+		InputClk = InstancePtr->Config.InputClockHz / 8;
+	}
+
+	/*
+	 * Determine the Baud divider. It can be 4to 254.
+	 * Loop through all possible combinations
+	 */
+	for (IterBAUDDIV = 4; IterBAUDDIV < 255; IterBAUDDIV++) {
+
+		/*
+		 * Calculate the value for BRGR register
+		 */
+		BRGR_Value = InputClk / (BaudRate * (IterBAUDDIV + 1));
+
+		/*
+		 * Calculate the baud rate from the BRGR value
+		 */
+		CalcBaudRate = InputClk/ (BRGR_Value * (IterBAUDDIV + 1));
+
+		/*
+		 * Avoid unsigned integer underflow
+		 */
+		if (BaudRate > CalcBaudRate) {
+			BaudError = BaudRate - CalcBaudRate;
+		}
+		else {
+			BaudError = CalcBaudRate - BaudRate;
+		}
+
+		/*
+		 * Find the calculated baud rate closest to requested baud rate.
+		 */
+		if (Best_Error > BaudError) {
+
+			Best_BRGR = BRGR_Value;
+			Best_BAUDDIV = IterBAUDDIV;
+			Best_Error = BaudError;
+		}
+	}
+
+	/*
+	 * Make sure the best error is not too large.
+	 */
+	PercentError = (Best_Error * 100) / BaudRate;
+	if (XUARTPS_MAX_BAUD_ERROR_RATE < PercentError) {
+		return XST_UART_BAUD_ERROR;
+	}
+
+	/*
+	 * Disable TX and RX to avoid glitches when setting the baud rate.
+	 */
+	XUartPs_DisableUart(InstancePtr);
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_BAUDGEN_OFFSET, Best_BRGR);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_BAUDDIV_OFFSET, Best_BAUDDIV);
+
+	/*
+	 * Enable device
+	 */
+	XUartPs_EnableUart(InstancePtr);
+
+	InstancePtr->BaudRate = BaudRate;
+
+	return XST_SUCCESS;
+
+}
+
+/***************************************************/
+
+/************************************************/
+/************** Main UART Interface *************/
+
+XUartPs* uart_init(XUartPs* uartps_ptr, u16 deviceID, int baudRate) {
+	XUartPs_Config* config = XUartPs_LookupConfig(deviceID);
+
+	//Configure XUartPs instance
+	int Status = XUartPs_CfgInitialize(uartps_ptr, config, config->BaseAddress);
+	if (Status != XST_SUCCESS){
+		return NULL;
+	}
+
+	//Set Baudrate for BT
+	//XUartPs_SetBaudRate(uartps_ptr, baudRate);
+	XUartPs_SetBaudRate_ours(uartps_ptr, baudRate);
+
+	return uartps_ptr;
+}
+
+void uart_clearFIFOs(XUartPs* uartps_ptr) {
+	//Get UART0 Control Register and clear the TX and RX Fifos
+	int* uart_ctrl_reg = (int*) uartps_ptr->Config.BaseAddress;
+	*uart_ctrl_reg |= 0x00000003; // clear TX & RX
+}
+
+void uart_sendByte(XUartPs* uartps_ptr, char data) {
+	XUartPs_SendByte(uartps_ptr->Config.BaseAddress, data);
+}
+
+void uart_sendStr(XUartPs* uartps_ptr, char* str) {
+	uart_sendBytes(uartps_ptr, str, strlen(str));
+}
+
+void uart_sendBytes(XUartPs* uartps_ptr, char* data, int numBytes) {
+	while (uart_isSending(uartps_ptr))
+		;
+
+	int done = 0;
+	while (done < numBytes) {
+		done += XUartPs_Send(uartps_ptr, (unsigned char*) (&data[done]), numBytes - done);
+	}
+}
+
+int uart_isSending(XUartPs* uartps_ptr) {
+	return XUartPs_IsSending(uartps_ptr);
+}
+
+int uart_hasData(XUartPs* uartps_ptr) {
+	return XUartPs_IsReceiveData(uartps_ptr->Config.BaseAddress);
+}
+
+void uart_recvBytes(XUartPs* uartps_ptr, char* buffer, int numBytes) {
+	int received = 0;
+	while (received < numBytes) {
+		received += XUartPs_Recv(uartps_ptr, (unsigned char*) &buffer[received], (numBytes - received));
+	}
+}
+
+char uart_recvByte(XUartPs* uartps_ptr) {
+	return XUartPs_RecvByte(uartps_ptr->Config.BaseAddress);
+	//char buffer[1];
+	//XUartPs_Recv(uartps_ptr, (unsigned char*) &buffer[0], 1);
+
+//	return buffer[0];
+}
+
+/************************************************/
+/************************************************/
+
+
+
+
+
+/************************************************/
+/********** UART 0 convenience methods **********/
+
+XUartPs* uart0_init(u16 deviceID, int baudRate){
+	if (_Uart0PS) {
+		free(_Uart0PS);
+	}
+	_Uart0PS = malloc(sizeof(XUartPs));
+	return uart_init(_Uart0PS, deviceID, baudRate);
+}
+
+void uart0_clearFIFOs(){
+	uart_clearFIFOs(_Uart0PS);
+}
+
+void uart0_sendByte(u8 data){
+	uart_sendByte(_Uart0PS, data);
+}
+
+void uart0_sendStr(char* str) {
+	uart_sendStr(_Uart0PS, str);
+}
+
+void uart0_sendMetaData(metadata_t md)
+{
+	uart0_sendByte(md.begin_char);
+	uart0_sendByte(md.msg_type);
+	uart0_sendByte(md.msg_subtype);
+	uart0_sendByte(md.msg_id & 0x00ff);
+	uart0_sendByte((md.msg_id >> 8) & 0x00ff);
+	uart0_sendByte(md.data_len & 0x00ff);
+	uart0_sendByte((md.data_len >> 8) & 0x00ff);
+}
+
+void uart0_sendBytes(char* data, int numBytes){
+	uart_sendBytes(_Uart0PS, data, numBytes);
+}
+
+int uart0_isSending(){
+	return uart_isSending(_Uart0PS);
+}
+
+int uart0_hasData(){
+	return uart_hasData(_Uart0PS);
+}
+
+void uart0_recvBytes(char* buffer, int numBytes) {
+	uart_recvBytes(_Uart0PS, buffer, numBytes);
+}
+
+char uart0_recvByte() {
+	return uart_recvByte(_Uart0PS);
+}
+
+/************************************************/
+/************************************************/
+
+
+
+
+
+
+/************************************************/
+/********** UART 1 convenience methods **********/
+
+XUartPs* uart1_init(u16 deviceID, int baudRate){
+	if (_Uart1PS) {
+		free(_Uart1PS);
+	}
+	_Uart1PS = malloc(sizeof(XUartPs));
+	return uart_init(_Uart1PS, deviceID, baudRate);
+}
+
+void uart1_clearFIFOs(){
+	uart_clearFIFOs(_Uart1PS);
+}
+
+void uart1_sendByte(char data){
+	uart_sendByte(_Uart1PS, data);
+}
+
+void uart1_sendStr(char* str) {
+	uart_sendStr(_Uart1PS, str);
+}
+
+void uart1_sendBytes(char* data, int numBytes){
+	uart_sendBytes(_Uart1PS, data, numBytes);
+}
+
+int uart1_isSending(){
+	return uart_isSending(_Uart1PS);
+}
+
+int uart1_hasData(){
+	return uart_hasData(_Uart1PS);
+}
+
+void uart1_recvBytes(char* buffer, int numBytes) {
+	uart_recvBytes(_Uart1PS, buffer, numBytes);
+}
+
+char uart1_recvByte() {
+	return uart_recvByte(_Uart1PS);
+}
+
+/************************************************/
+/************************************************/
+
+int tryReceivePacket(stringBuilder_t* sb, int echo) {
+	while(uart0_hasData()) {
+		char c = uart0_recvByte(); // begin char
+		if(c == 0xBE) {
+//			printf("Beginning to read packet from UART.\n");
+
+			sb->addChar(sb, 0xBE);
+			char type = uart0_recvByte();
+			sb->addChar(sb, type); // type
+			sb->addChar(sb, uart0_recvByte()); // subtype
+			sb->addChar(sb, uart0_recvByte()); // id
+			sb->addChar(sb, uart0_recvByte()); // id
+
+			unsigned char byte5 = uart0_recvByte(); // data length
+			unsigned char byte6 = uart0_recvByte(); // data length
+
+			int datalen = (byte6 << 8) | byte5;
+//			printf("Received packet with data length: %d", datalen);
+
+			sb->addChar(sb, byte5);
+			sb->addChar(sb, byte6);
+
+			// Read all the data and the checksum byte
+			int i;
+			for(i=0; i < datalen + 1; i++)
+			{
+				sb->addChar(sb, uart0_recvByte());
+			}
+
+//			printf("Done reading packet from UART.\n");
+			return type;
+		} else {
+//			printf("The first byte was not the begin char: %x\n", c);
+			return -1;
+		}
+	}
+	return -1;
+/*
+
+	while (uart0_hasData()) {
+		char c = uart0_recvByte();
+		if (c == PACKET_START_CHAR) {
+#if DEBUG
+			uart0_sendStr("Start ");
+#endif
+			c = uart0_recvByte();
+			char type = c;
+//			sb->addChar(sb, type);
+			int count = 0;
+
+			//uart0_sendByte(c);
+
+			// if it's a 'C' packet (a command for the quad), then
+			// wait for the packet end char. Else, if it's a 'U' packet
+			// which is an update from the camera system, then we read
+			// a fixed number of bytes (UPDATE_SIZE # of bytes)
+			if(type == 'C')
+			{
+				while (c != PACKET_END_CHAR)
+				{
+					c = uart0_recvByte();
+					count++;
+					if(c == PACKET_END_CHAR)
+						break;
+					if ((c != 0 && c != '\r' && c != '\n'))
+					{
+						sb->addChar(sb, c);
+						if (echo) {
+							uart0_sendByte(c);
+						}
+					}
+				}
+				return type;
+			}
+
+			else if(type == 'U')
+			{
+				while(count < UPDATE_SIZE)
+				{
+					c = uart0_recvByte();
+					count++;
+
+					sb->addChar(sb, c);
+					if (echo) {
+						uart0_sendByte(c);
+					}
+				}
+				return type;
+			}
+#if DEBUG
+			uart0_sendStr("End:[");
+			uart0_sendStr(sb->buf);
+			uart0_sendStr("] ");
+#endif
+			return 0;
+		}
+	}
+
+	return 0;
+	*/
+}
+

quad/sw/modular_quad_pid/src/uart.h

+/*
+ * uart.h
+ *
+ *  Created on: Nov 10, 2014
+ *      Author: ucart
+ */
+
+#ifndef UART_H_
+#define UART_H_
+
+#include "xparameters.h"
+#include "xuartps.h"
+#include "stringBuilder.h"
+
+#define PACKET_START_CHAR 2
+#define PACKET_END_CHAR 3
+#define UPDATE_SIZE 28
+
+extern XUartPs* _Uart0PS;
+extern XUartPs* _Uart1PS;
+
+
+/************************************************/
+/************** Main UART Interface *************/
+XUartPs* uart_init(XUartPs* uartps_ptr, u16 deviceID, int baudRate);
+void uart_clearFIFOs(XUartPs* uartps_ptr);
+void uart_sendByte(XUartPs* uartps_ptr, char data);
+void uart_sendStr(XUartPs* uartps_ptr, char* str);
+void uart_sendBytes(XUartPs* uartps_ptr, char* data, int numBytes);
+int uart_isSending(XUartPs* uartps_ptr);
+int uart_hasData(XUartPs* uartps_ptr);
+
+//char uart_recvByte(); // block until char received
+
+//int uart_recvBytes(char* buffer, int numBytes, int timeoutMicros); // block until all received
+
+//void uart_recvCallback(void (*func)(char data));
+
+void uart_recvBytes(XUartPs* uartps_ptr, char* buffer, int numBytes);
+
+char uart_recvByte(XUartPs* uartps_ptr);
+/************************************************/
+/************************************************/
+
+
+
+/************************************************/
+/********** UART 0 convenience methods **********/
+XUartPs* uart0_init(u16 deviceID, int baudRate);
+void uart0_clearFIFOs();
+void uart0_sendByte(u8 data);
+void uart0_sendStr(char* data);
+void uart0_sendBytes(char* data, int numBytes);
+int uart0_isSending();
+int uart0_hasData();
+void uart0_recvBytes(char* buffer, int numBytes);
+char uart0_recvByte();
+void uart0_sendMetaData(metadata_t md);
+/************************************************/
+/************************************************/
+
+
+
+/************************************************/
+/********** UART 1 convenience methods **********/
+XUartPs* uart1_init(u16 deviceID, int baudRate);
+void uart1_clearFIFOs();
+void uart1_sendByte(char data);
+void uart1_sendStr(char* data);
+void uart1_sendBytes(char* data, int numBytes);
+int uart1_isSending();
+int uart1_hasData();
+void uart1_recvBytes(char* buffer, int numBytes);
+char uart1_recvByte();
+/************************************************/
+/************************************************/
+
+int tryReceivePacket(stringBuilder_t* sb, int echo);
+
+#endif /* UART_H_ */

quad/sw/modular_quad_pid/src/update_gui.c

+/*
+ * update_gui.c
+ *
+ *  Created on: Feb 20, 2016
+ *      Author: ucart
+ */
+ 
+#include "update_gui.h"
+
+int update_GUI(log_t* log_struct)
+{
+    return 0;
+}
+ 

quad/sw/modular_quad_pid/src/update_gui.h

+/*
+ * update_gui.h
+ *
+ *  Created on: Feb 20, 2016
+ *      Author: ucart
+ */
+
+#ifndef UPDATE_GUI_H_
+#define UPDATE_GUI_H_
+ 
+#include <stdio.h>
+
+#include "log_data.h"
+
+/**
+ * @brief 
+ *      Updates the user interface.
+ *
+ * @param log_struct
+ *      structure of the data to be logged
+ *
+ * @return 
+ *      error message
+ *
+ */
+int update_GUI(log_t* log_struct);
+
+#endif /* UPDATE_GUI_H_ */

quad/sw/modular_quad_pid/src/user_input.c

+/*
+ * user_input.c
+ *
+ *  Created on: Feb 20, 2016
+ *      Author: ucart
+ */
+ 
+#include "user_input.h"
+#include "uart.h"
+ 
+int get_user_input(log_t* log_struct, user_input_t* user_input_struct)
+{
+	// Read in values from RC Receiver
+	read_rec_all(user_input_struct->rc_commands);
+
+	log_struct->commands.pitch    = user_input_struct->rc_commands[PITCH];
+	log_struct->commands.roll     = user_input_struct->rc_commands[ROLL];
+	log_struct->commands.throttle = user_input_struct->rc_commands[THROTTLE];
+	log_struct->commands.yaw      = user_input_struct->rc_commands[YAW];
+
+	//create setpoints for manual flight
+	// currently in units of radians
+	user_input_struct->yaw_manual_setpoint = convert_from_receiver_cmd(user_input_struct->rc_commands[YAW], YAW_MAX, YAW_CENTER, YAW_MIN, YAW_RAD_TARGET, -(YAW_RAD_TARGET));
+	user_input_struct->roll_angle_manual_setpoint = convert_from_receiver_cmd(user_input_struct->rc_commands[ROLL], ROLL_MAX, ROLL_CENTER, ROLL_MIN, ROLL_RAD_TARGET, -(ROLL_RAD_TARGET));
+	user_input_struct->pitch_angle_manual_setpoint = convert_from_receiver_cmd(user_input_struct->rc_commands[PITCH], PITCH_MAX, PITCH_CENTER, PITCH_MIN, PITCH_RAD_TARGET, -(PITCH_RAD_TARGET));
+
+	// Listen on bluetooth and if there's a packet,
+	// then receive the packet and set hasPacket for later processing
+	// "update packet" type processing is done in sensor.c
+	// "command packet" type processing is done in control_algorithm.c
+	user_input_struct->hasPacket = tryReceivePacket(user_input_struct->sb, 0);
+
+    return 0;
+}
+
+int kill_condition(user_input_t* user_input_struct)
+{
+	return read_kill(user_input_struct->rc_commands[GEAR]);
+}
+
+/*
+ * Converts an RC receiver command to whatever units that max_target and min_target are in. This function first centers the receiver command at 0.
+ * It creates a windowed linear function, based on the sign of the centered receiver command.
+ *
+ * 										       -
+ * 									          / (x - center_receiver_cmd) * (min_target / (min_receiver_cmd - center_receiver_cmd)) when x <=  0
+ * convert_receiver_cmd(x = receiver_cmd) =  <
+ * 										      \ (x - center_receiver_cmd) * (max_target / (max_receiver_cmd - center_receiver_cmd) when x > 0
+ * 										       -
+ *
+ */
+float convert_from_receiver_cmd(int receiver_cmd, int max_receiver_cmd, int center_receiver_cmd, int min_receiver_cmd, float max_target, float min_target)
+{
+	// centers the receiver command by subtracting the given center value. This means that if receiver_cmd == center then receiver_cmd_centered should be 0.
+	int receiver_cmd_centered = receiver_cmd - center_receiver_cmd;
+
+	if(receiver_cmd_centered <= 0) {
+		float ret = ((float)(receiver_cmd_centered * min_target)) / ((float) (min_receiver_cmd - center_receiver_cmd));
+
+		if(ret < min_target)
+			ret = min_target;
+
+		return ret;
+	}
+
+	else {
+		float ret = ((float)(receiver_cmd_centered * max_target)) / ((float) (max_receiver_cmd - center_receiver_cmd));
+
+		if(ret > max_target)
+			ret = max_target;
+
+		return ret;
+	}
+
+	return 0.0;
+}
+ 

quad/sw/modular_quad_pid/src/user_input.h

+/*
+ * user_input.h
+ *
+ *  Created on: Feb 20, 2016
+ *      Author: ucart
+ */
+
+#ifndef USER_INPUT_H_
+#define USER_INPUT_H_
+ 
+#include <stdio.h>
+#include "type_def.h"
+#include "log_data.h"
+#include "util.h"
+#include "stringBuilder.h"
+
+/*
+ * Aero channel declaration
+ */
+
+#define THROTTLE 0
+#define ROLL     1
+#define PITCH    2
+#define YAW      3
+#define GEAR 	 4
+#define FLAP 	 5
+
+//////TARGETS
+
+#define YAW_DEG_TARGET 60.0f
+#define YAW_RAD_TARGET ((float) ((YAW_DEG_TARGET * 3.141592) / ((float) 180)))
+
+#define ROLL_DEG_TARGET 10.0f
+#define ROLL_RAD_TARGET ((float) ((ROLL_DEG_TARGET * 3.141592) / ((float) 180)))
+
+#define PITCH_DEG_TARGET 12.0f
+#define PITCH_RAD_TARGET ((float) ((PITCH_DEG_TARGET * 3.141592) / ((float) 180)))
+
+/////// Signals from the Rx mins, maxes and ranges
+
+//#define THROTTLE_MAX  191900
+//#define THROTTLE_MIN  110200
+//#define THROTTLE_RANGE THROTTLE_MAX - THROTTLE_MIN
+//
+//#define ROLL_MAX      170200
+//#define ROLL_MIN      129400
+//#define ROLL_CENTER   149800
+//#define ROLL_RANGE    ROLL_MAX - ROLL_MIN
+//
+//#define PITCH_MAX     169900
+//#define PITCH_MIN     129500
+//#define PITCH_CENTER  149700
+//#define PITCH_RANGE   PITCH_MAX - PITCH_MIN
+//
+//#define YAW_MAX       169400
+//#define YAW_MIN       129300
+//#define YAW_CENTER   (YAW_MIN + YAW_MAX)/2 //149800
+//#define YAW_RANGE     YAW_MAX - YAW_MIN
+//
+//#define GEAR_1	170800
+//#define GEAR_0	118300
+//
+//#define FLAP_1		192000
+//#define FLAP_0		107600
+//
+//#define GEAR_KILL     GEAR_0 // The kill point for the program
+//#define BASE          150000
+
+/**
+ * @brief 
+ *      Receives user input to the system.
+ *
+ * @param log_struct
+ *      structure of the data to be logged
+ *
+ * @param user_input_struct
+ *      structure of the data inputed by the user
+ *
+ * @return 
+ *      error message
+ *
+ */
+int get_user_input(log_t* log_struct,  user_input_t* user_input_struct);
+int kill_condition(user_input_t* user_input_struct);
+float convert_from_receiver_cmd(int receiver_cmd, int max_receiver_cmd, int center_receiver_cmd, int min_receiver_cmd, float max_target, float min_target);
+
+
+#endif /* USER_INPUT_H_ */

quad/sw/modular_quad_pid/src/util.c

+/*
+ * util.c
+ *
+ *  Created on: Oct 11, 2014
+ *      Author: ucart
+ */
+
+#include "util.h"
+
+extern int motor0_bias, motor1_bias, motor2_bias, motor3_bias;
+//Global variable representing the current pulseW
+int pulseW = pulse_throttle_low;
+
+/**
+ * Initializes the PWM output components.
+ * Default pulse length  = 1 ms
+ * Default period length = 2.33 ms
+ */
+void pwm_init() {
+	printf("Period initialization starting\r\n");
+
+	int* pwm_0 = (int*) PWM_0_ADDR + PWM_PERIOD;
+	int* pwm_1 = (int*) PWM_1_ADDR + PWM_PERIOD;
+	int* pwm_2 = (int*) PWM_2_ADDR + PWM_PERIOD;
+	int* pwm_3 = (int*) PWM_3_ADDR + PWM_PERIOD;
+
+	// Initializes all the PWM address to have the correct period width at 450 hz
+	*pwm_0 = period_width;
+	*pwm_1 = period_width;
+	*pwm_2 = period_width;
+	*pwm_3 = period_width;
+	printf("Period initialization successful %d\n", period_width);
+	// Initializes the PWM pulse lengths to be 1 ms
+	*(int*) (PWM_0_ADDR + PWM_PULSE) = pulse_throttle_low;
+	*(int*) (PWM_1_ADDR + PWM_PULSE) = pulse_throttle_low;
+	*(int*) (PWM_2_ADDR + PWM_PULSE) = pulse_throttle_low;
+	*(int*) (PWM_3_ADDR + PWM_PULSE) = pulse_throttle_low;
+	printf("Pulse initialization successful %d\n", pulse_throttle_low);
+
+#ifdef X_CONFIG
+	printf("In x config mode\n");
+#else
+	printf("In + config mode\n");
+#endif
+	usleep(1000000);
+}
+
+/**
+ * Writes all PWM components to be the same given pulsewidth
+ */
+void pwm_write_all(int pulseWidth) {
+	// Check lower and upper bounds
+	if (pulseWidth > pulse_throttle_high)
+		pulseWidth = pulse_throttle_high;
+	if (pulseWidth < pulse_throttle_low)
+		pulseWidth = pulse_throttle_low;
+	// Set all the pulse widths
+	*(int*) (PWM_0_ADDR + PWM_PULSE) = pulseWidth;
+	*(int*) (PWM_1_ADDR + PWM_PULSE) = pulseWidth;
+	*(int*) (PWM_2_ADDR + PWM_PULSE) = pulseWidth;
+	*(int*) (PWM_3_ADDR + PWM_PULSE) = pulseWidth;
+}
+/**
+ * Write a given pulseWidth to a channel
+ */
+void pwm_write_channel(int pulseWidth, int channel){
+	// Check lower and upper bounds
+		if (pulseWidth > pulse_throttle_high)
+			pulseWidth = pulse_throttle_high;
+		if (pulseWidth < pulse_throttle_low)
+			pulseWidth = pulse_throttle_low;
+
+		switch(channel){
+		case 0:
+			*(int*) (PWM_0_ADDR + PWM_PULSE) = pulseWidth;
+			break;
+		case 1:
+			*(int*) (PWM_1_ADDR + PWM_PULSE) = pulseWidth;
+			break;
+		case 2:
+			*(int*) (PWM_2_ADDR + PWM_PULSE) = pulseWidth;
+			break;
+		case 3:
+			*(int*) (PWM_3_ADDR + PWM_PULSE) = pulseWidth;
+			break;
+		default:
+			break;
+		}
+}
+/**
+ * Reads the registers from the PWM_Recorders, and returns the pulse width
+ * of the last PWM signal to come in
+ */
+int read_rec(int channel) {
+	switch (channel) {
+	case 0:
+		return *((int*) PWM_REC_0_ADDR);
+	case 1:
+		return *((int*) PWM_REC_1_ADDR);
+	case 2:
+		return *((int*) PWM_REC_2_ADDR);
+	case 3:
+		return *((int*) PWM_REC_3_ADDR);
+	case 4:
+		return *((int*) PWM_REC_4_ADDR);
+	case 5:
+		return *((int*) PWM_REC_5_ADDR);
+	default:
+		return 0;
+	}
+}
+/**
+ * Reads all 4 receiver channels at once
+ */
+void read_rec_all(int* mixer){
+	int i;
+	for(i = 0; i < 6; i++){
+		mixer[i] = read_rec(i);
+	}
+}
+
+int hexStrToInt(char *buf, int startIdx, int endIdx) {
+	int result = 0;
+	int i;
+	int power = 0;
+	for (i=endIdx; i >= startIdx; i--) {
+		int value = buf[i];
+		if ('0' <= value && value <= '9') {
+			value -= '0';
+		} else if ('a' <= value && value <= 'f') {
+			value -= 'a';
+			value += 10;
+		} else if ('A' <= value && value <= 'F') {
+			value -= 'A';
+			value += 10;
+		}
+
+		result += (2 << (4 * power)) * value;
+		power++;
+	}
+
+	return result;
+}
+
+void read_bluetooth_all(int* mixer) {
+	char buffer[32];
+
+	int done = 0;
+	int gotS = 0;
+	char c  = 0;
+	while (!done) {
+		int counter = 0;
+		if (!gotS) {
+			c = uart0_recvByte();
+		}
+		if (c == 'S') {
+
+			while (1) {
+				char cc = uart0_recvByte();
+				if (cc == 'S') {
+									counter = 0;
+									gotS = 1;
+									break;
+								}
+				printf("C=%c,\r\n",cc);
+				buffer[counter++] = cc;
+
+
+				if (counter == 12) {
+					buffer[12] = 0;
+					done = 1;
+					gotS = 0;
+				}
+			}
+			//uart0_recvBytes(buffer, 12);
+			//buffer[12] = 0;
+
+
+		}
+	}
+
+//	// data := "XX XX XX XX XX"
+//	uart0_recvBytes(buffer, 12);
+//	buffer[12] = 0;
+//
+//
+	int i;
+	for(i=0; i < 5; i++) {
+		mixer[i] = 0;
+	}
+
+	for (i=0; i < 4; i++) {
+		//mixer[i] = hexStrToInt(buffer, 3*i, 3*i + 1);
+		mixer[i] = (buffer[i*3] << 8) | buffer[i*3 + 1];
+	}
+
+	printf("mixer: \"%s\" -> %d %d %d %d %d\r\n", buffer, mixer[0], mixer[1], mixer[2], mixer[3], mixer[4]);
+
+}
+
+/**
+ * Use the buttons to drive the pulse length of the channels
+ */
+void b_drive_pulse() {
+	int* btns = (int *) XPAR_BTNS_BASEADDR;
+
+	// Increment the pulse width by 5% throttle
+	if (*btns & 0x1) {
+		pulseW += 1000;
+		if (pulseW > 200000)
+			pulseW = 200000;
+		pwm_write_all(pulseW);
+		while (*btns & 0x1)
+			;
+	} //Decrease the pulse width by 5% throttle
+	else if (*btns & 0x2) {
+		pulseW -= 1000;
+		if (pulseW < 100000) {
+			pulseW = 100000;
+		}
+		pwm_write_all(pulseW);
+		while (*btns & 0x2)
+			;
+	}
+	// Set the pulses back to default
+	else if (*btns & 0x4) {
+		pulseW = MOTOR_0_PERCENT;
+		pwm_write_all(pulseW);
+	}
+	// Read the pulse width of pwm_recorder 0
+	else if (*btns & 0x8) {
+		int i;
+		for(i = 0; i < 4; i++){
+			xil_printf("Channel %d:  %d\n", i, read_rec(i));
+		}
+		//xil_printf("%d\n",pulseW);
+		while (*btns & 0x8)
+			;
+	}
+}
+
+/**
+ * Creates a sine wave driving the motors from 0 to 100% throttle
+ */
+void sine_example(){
+
+	int* btns = (int *) XPAR_BTNS_BASEADDR;
+	/*        Sine Wave        */
+	static double time = 0;
+
+	time += .0001;
+	pulseW = (int)fabs(sin(time)*(100000)) + 100000;
+	//pulseW = (int) (sin(time) + 1)*50000 + 100000;
+	if (*btns & 0x1){
+		printf("%d", pulseW);
+		printf("   %d\n", *(int*) (PWM_0_ADDR + PWM_PULSE));
+	}
+	pwm_write_all(pulseW);
+	usleep(300);
+}
+
+void print_mixer(int * mixer){
+	int i;
+	for(i = 0; i < 4; i++){
+		xil_printf("%d : %d			", i, mixer[i]);
+	}
+	xil_printf("\n");
+}
+
+/**
+ * Argument is the reading from the pwm_recorder4 which is connected to the gear pwm
+ * If the message from the receiver is 0 - gear, kill the system by sending a 1
+ * Otherwise, do nothing
+ */
+int read_kill(int gear){
+	if(gear > 115000 && gear < 125000)
+		return 1;
+	return 0;
+}
+
+int read_flap(int flap)
+{
+	// flap '0' is 108,000 CC (Up)
+	// flap '1' is 192,000 CC (Down)
+	// here we say if the reading is greater than 150,000 than its '1'; '0' otherwise
+	if(flap > 150000)
+		return 1;
+	return 0;
+}
+
+/**
+ * Turns off the motors
+ */
+void pwm_kill(){
+	// Initializes the PWM pulse lengths to be 1 ms
+	*(int*) (PWM_0_ADDR + PWM_PULSE) = pulse_throttle_low;
+	*(int*) (PWM_1_ADDR + PWM_PULSE) = pulse_throttle_low;
+	*(int*) (PWM_2_ADDR + PWM_PULSE) = pulse_throttle_low;
+	*(int*) (PWM_3_ADDR + PWM_PULSE) = pulse_throttle_low;
+	xil_printf("Kill switch was touched, shutting off the motors and ending the program\n");
+}
+
+/**
+ * Useful stuff in here in regards to PID tuning, and motor tuning
+ * TODO : Scanf string stuff
+ * TODO : Make adam do it :DDDDDDDD
+ */
+void bluetoothTunePID(char instr, gam_t* gam, PID_t* CFpid, PID_t* Gpid){
+	int wasX = 0;
+	int wasPid = 0;
+	int wasSetpoint = 0;
+	int wasLog = 0;
+	char buf[100];
+
+	switch (instr) {
+	case 'P':
+		// Change this if tuning other PIDs
+		CFpid->Kp += .5;
+		wasPid = 1;
+		break;
+	case 'p':
+		CFpid->Kp -= .5;
+		wasPid = 1;
+		break;
+	case 'O':
+		CFpid->Kp += .2;
+		wasPid = 1;
+		break;
+	case 'o':
+		CFpid->Kp -= .2;
+		wasPid = 1;
+		break;
+
+	case 'I':
+		CFpid->Kp += 0.1;
+		wasPid = 1;
+		break;
+	case 'i':
+		CFpid->Kp -= 0.1;
+		wasPid = 1;
+		break;
+	case 'W':
+		Gpid->Kp += 1;
+		wasPid = 1;
+		break;
+	case 'w':
+		Gpid->Kp -= 1;
+		wasPid = 1;
+		break;
+	case 'E':
+		Gpid->Kp += 2;
+		wasPid = 1;
+		break;
+	case 'e':
+		Gpid->Kp -= 2;
+		wasPid = 1;
+		break;
+	case 'R':
+		Gpid->Kp += 5;
+		wasPid = 1;
+		break;
+	case 'r':
+		Gpid->Kp -= 5;
+		wasPid = 1;
+		break;
+	case 'D':
+		CFpid->Kd += .1;
+		wasPid = 1;
+		break;
+	case 'd':
+			CFpid->Kd -= .1;
+			wasPid = 1;
+			break;
+	case 'S':
+			CFpid->setpoint += 1;
+			wasSetpoint = 1;
+			break;
+	case 's':
+			CFpid->setpoint -= 1;
+			wasSetpoint = 1;
+			break;
+	case '0':
+		motor0_bias += 100;
+		wasPid = 0;
+		break;
+	case '1':
+		motor1_bias += 100;
+		wasPid = 0;
+		break;
+	case '2':
+		motor2_bias += 100;
+		wasPid = 0;
+		break;
+	case '3':
+		motor3_bias += 100;
+		wasPid = 0;
+		break;
+	case ')':
+		motor0_bias -= 100;
+		wasPid = 0;
+		break;
+	case '!':
+		motor1_bias -= 100;
+		wasPid = 0;
+		break;
+	case '@':
+		motor2_bias -= 100;
+		wasPid = 0;
+		break;
+	case '#':
+		motor3_bias -= 100;
+		wasPid = 0;
+		break;
+	case 'x':
+		wasX = 1;
+		break;
+	case ' ':
+		wasLog = 1;
+		break;
+/*	case 'm':
+		pid->setpoint = -45.0;
+		// Change set point
+		break;
+	case 'n':
+		pid->setpoint = 45.0;
+	*/	// Change set point
+	default:
+		wasPid = 0;
+		break;
+	}
+
+	if(wasX){
+		return;
+	}
+	else if(wasSetpoint){
+		sprintf(buf, "Setpoint: %4.1f\n\r", CFpid->setpoint);
+		uart0_sendBytes(buf, strlen(buf));
+		usleep(5000);
+	}
+	else if (wasPid) {
+		/*sprintf(buf,
+				"PAngle: %8.3f RAngle: %8.3f PID p: %8.3f  d: %8.3f\r\n",
+				compY, compX, pitchPID.Kp, pitchPID.Kd);*/
+
+		sprintf(buf, "CFP Coeff: %4.1f D %4.1f GP Coeff: %4.1f\n\r", CFpid->Kp, CFpid->Kd, Gpid->Kp);
+		uart0_sendBytes(buf, strlen(buf));
+		usleep(5000);
+	}
+	else if (wasLog){
+		sprintf(buf, "CX %5.2f GP GX: %5.2f\n\r", 0.0, gam->gyro_xVel_p);
+		uart0_sendBytes(buf, strlen(buf));
+		usleep(5000);
+	}
+	else {
+		sprintf(buf, "Motor bias's \t\t0: %d 1: %d 2: %d 3: %d \r\n", motor0_bias,
+				motor1_bias, motor2_bias, motor3_bias);
+		uart0_sendBytes(buf, strlen(buf));
+
+//		sprintf(buf, "P: %3.2f I: %3.2f D: %3.2f\r\n", log_struct.ang_vel_pitch_PID_values.P, log_struct.ang_vel_pitch_PID_values.I, log_struct.ang_vel_pitch_PID_values.D);
+		uart0_sendBytes(buf, strlen(buf));
+		usleep(1e4);
+	}
+}
+/*
+void flash_MIO_7_led(int how_many_times, int ms_between_flashes)
+{
+	if(how_many_times <= 0)
+		return;
+
+	while(how_many_times)
+	{
+		MIO7_led_on();
+
+		usleep(ms_between_flashes * 500);
+
+		MIO7_led_off();
+
+		usleep(ms_between_flashes * 500);
+
+		how_many_times--;
+	}
+}
+
+void MIO7_led_off()
+{
+	XGpioPs Gpio;
+
+	XGpioPs_Config * ConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
+	XGpioPs_CfgInitialize(&Gpio, ConfigPtr, ConfigPtr->BaseAddr);
+
+	XGpioPs_SetDirectionPin(&Gpio, 7, 1);
+
+	// Disable LED
+	XGpioPs_WritePin(&Gpio, 7, 0x00);
+}
+
+void MIO7_led_on()
+{
+	XGpioPs Gpio;
+
+	XGpioPs_Config * ConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
+	XGpioPs_CfgInitialize(&Gpio, ConfigPtr, ConfigPtr->BaseAddr);
+
+	XGpioPs_SetDirectionPin(&Gpio, 7, 1);
+
+	// Enable LED
+	XGpioPs_WritePin(&Gpio, 7, 0x01);
+}
+*/
+void msleep(int msecs)
+{
+	usleep(msecs * 1000);
+}
+

quad/sw/modular_quad_pid/src/util.h

+/*
+ * util.h
+ *
+ *  Created on: Oct 11, 2014
+ *      Author: ucart
+ */
+#ifndef _UTIL_H
+#define _UTIL_H
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <math.h>
+#include <xgpiops.h>
+#include "PID.h"
+#include "log_data.h"
+#include <sleep.h>
+#include "controllers.h"
+#include "xparameters.h"
+#include "uart.h"
+
+
+#define clock_rate          100000000
+#define frequency           450
+#define period_width        clock_rate/frequency
+#define pulse_throttle_low  clock_rate / 1000
+#define pulse_throttle_high clock_rate / 500
+#define MOTOR_0_PERCENT     115000
+
+
+#define XPAR_BTNS_BASEADDR 0x41200000
+
+/**
+ * Various Addresses of custom IP components
+ */
+#define PWM_0_ADDR     XPAR_PWM_SIGNAL_OUT_WKILLSWITCH_0_BASEADDR
+#define PWM_1_ADDR     XPAR_PWM_SIGNAL_OUT_WKILLSWITCH_1_BASEADDR
+#define PWM_2_ADDR     XPAR_PWM_SIGNAL_OUT_WKILLSWITCH_2_BASEADDR
+#define PWM_3_ADDR     XPAR_PWM_SIGNAL_OUT_WKILLSWITCH_3_BASEADDR
+#define PWM_REC_0_ADDR XPAR_PWM_RECORDER_0_BASEADDR
+#define PWM_REC_1_ADDR XPAR_PWM_RECORDER_1_BASEADDR
+#define PWM_REC_2_ADDR XPAR_PWM_RECORDER_2_BASEADDR
+#define PWM_REC_3_ADDR XPAR_PWM_RECORDER_3_BASEADDR
+#define PWM_REC_4_ADDR XPAR_PWM_RECORDER_4_BASEADDR
+#define PWM_REC_5_ADDR XPAR_PWM_RECORDER_5_BASEADDR
+
+/**
+ * Register offsets within the custom IP
+ */
+#define PWM_PERIOD     0
+#define PWM_PULSE      4
+
+void pwm_init();
+void pwm_write_all(int pulseWidth);
+void pwm_write_channel(int pulseWidth, int channel);
+
+int read_rec(int channel);
+void read_rec_all(int* mixer);
+
+void read_bluetooth_all(int* mixer);
+
+void b_drive_pulse();
+
+void sine_example();
+
+void print_mixer(int* mixer);
+int read_kill(int gear);
+int read_flap(int flap);
+void pwm_kill();
+
+void printLogging();
+void bluetoothTunePID(char instr, gam_t* gam, PID_t* CFpid, PID_t* Gpid);
+void msleep(int msecs);
+
+/**
+ * @brief
+ *      Flashes the MIO7 LED how_many_times times and with ms_between_flashes between the flashes.
+ *
+ * @param how_many_times
+ *      times the LED should be flashed
+ *
+ * @param ms_between_flashes
+ *      time between flashes in milliseconds
+ *
+ */
+void flash_MIO_7_led(int how_many_times, int ms_between_flashes);
+
+/**
+ * @brief
+ *      Turns off MIO7 LED.
+ *
+ */
+void MIO7_led_off();
+
+/**
+ * @brief
+ *      Turns on MIO7 LED.
+ *
+ */
+void MIO7_led_on();
+
+#endif //_UTIL_H

quad/sw/system_bsp/.cproject

+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="org.eclipse.cdt.core.default.config.1372124342">
+			<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1372124342" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
+				<externalSettings/>
+				<extensions/>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+</cproject>

quad/sw/system_bsp/.project

+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>system_bsp</name>
+	<comment></comment>
+	<projects>
+		<project>system_hw_platform</project>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.make.core.makeBuilder</name>
+			<arguments>
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+					<value>org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser;</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
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+					<value></value>
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+					<key>org.eclipse.cdt.make.core.build.command</key>
+					<value>make</value>
+				</dictionary>
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+					<key>org.eclipse.cdt.make.core.build.target.auto</key>
+					<value>all</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.build.target.clean</key>
+					<value>clean</value>
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+				<dictionary>
+					<key>org.eclipse.cdt.make.core.build.target.inc</key>
+					<value>all</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
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+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enabledIncrementalBuild</key>
+					<value>true</value>
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+				<dictionary>
+					<key>org.eclipse.cdt.make.core.environment</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>com.xilinx.sdk.sw.SwProjectNature</nature>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.make.core.makeNature</nature>
+	</natures>
+</projectDescription>

quad/sw/system_bsp/.sdkproject

+THIRPARTY=false
+PROCESSOR=ps7_cortexa9_0
+MSS_FILE=system.mss

quad/sw/system_bsp/Makefile

+# Makefile generated by Xilinx SDK.
+
+-include libgen.options
+
+LIBRARIES = ${PROCESSOR}/lib/libxil.a
+MSS = system.mss
+
+all: libs
+	@echo 'Finished building libraries'
+
+libs: $(LIBRARIES)
+
+$(LIBRARIES): $(MSS)
+	libgen -hw ${HWSPEC}\
+	       ${REPOSITORIES}\
+	       -pe ${PROCESSOR} \
+	       -log libgen.log \
+	       $(MSS)
+
+clean:
+	rm -rf ${PROCESSOR}

quad/sw/system_bsp/libgen.log

+Release 14.7 - libgen Xilinx EDK 14.7 Build EDK_P.20131013
+ (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+Command Line: libgen -hw ../system_hw_platform/system.xml -pe ps7_cortexa9_0
+-log libgen.log system.mss 
+
+
+Staging source files.
+Running DRCs.
+Running generate.
+Running post_generate.
+Running include - 'gmake -s include "COMPILER=arm-xilinx-eabi-gcc"
+"ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g
+-O0"'.
+
+Running libs - 'gmake -s libs "COMPILER=arm-xilinx-eabi-gcc"
+"ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g
+-O0"'.
+Running execs_generate.

quad/sw/system_bsp/libgen.options

+PROCESSOR=ps7_cortexa9_0
+REPOSITORIES=
+HWSPEC=../system_hw_platform/system.xml

quad/sw/system_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h

+//////////////////////////////////////////////////////////////////////
+//
+// Copyright (c) 2004-11 Xilinx, Inc.  All rights reserved.
+// Xilinx, Inc.
+//
+// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+// COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
+// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
+// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
+// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
+// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
+// AND FITNESS FOR A PARTICULAR PURPOSE.
+//
+// $Id: _profile_timer_hw.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $
+//
+// _program_timer_hw.h:
+//	Timer related functions
+//
+//////////////////////////////////////////////////////////////////////
+
+#ifndef _PROFILE_TIMER_HW_H
+#define _PROFILE_TIMER_HW_H
+
+#include "profile.h"
+
+#ifdef PROC_PPC
+#if defined __GNUC__
+#  define SYNCHRONIZE_IO __asm__ volatile ("eieio")
+#elif defined __DCC__
+#  define SYNCHRONIZE_IO __asm volatile(" eieio")
+#else
+#  define SYNCHRONIZE_IO
+#endif
+#endif
+
+#ifdef PROC_PPC
+#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO;
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
+#else
+#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); }
+#endif
+
+#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
+	ProfIo_Out32(((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] +	\
+			   (RegOffset)), (ValueToWrite))
+
+#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset)	\
+	ProfIo_In32((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + (RegOffset))
+
+#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
+	ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET,     \
+					   (RegisterValue))
+
+#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber)		\
+	ProfTimerCtr_mReadReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef PROC_PPC
+#include "xexception_l.h"
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#endif
+
+#ifdef TIMER_CONNECT_INTC
+#include "xintc_l.h"
+#include "xintc.h"
+#endif	// TIMER_CONNECT_INTC
+
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+#include "xtmrctr_l.h"
+#endif
+
+#ifdef PROC_CORTEXA9
+#include "xscutimer_hw.h"
+#include "xscugic.h"
+#endif
+
+extern unsigned int timer_clk_ticks ;
+
+//--------------------------------------------------------------------
+// PowerPC Target - Timer related functions
+//--------------------------------------------------------------------
+#ifdef PROC_PPC
+
+#ifdef PPC_PIT_INTERRUPT
+unsigned long timer_lo_clk_ticks ;	// Clk ticks when Timer is disabled in CG
+#endif
+
+#ifdef PROC_PPC440
+#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
+#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
+#define XREG_SPR_PIT XREG_SPR_DEC
+#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
+#endif
+
+//--------------------------------------------------------------------
+// Disable the Timer - During Profiling
+//
+// For PIT Timer -
+//	1. XTime_PITDisableInterrupt() ;
+//	2. Store the remaining timer clk tick
+//	3. Stop the PIT Timer
+//--------------------------------------------------------------------
+
+#ifdef PPC_PIT_INTERRUPT
+#define disable_timer() 		\
+	{				\
+		unsigned long val;	\
+		val=mfspr(XREG_SPR_TCR);	\
+		mtspr(XREG_SPR_TCR, val & ~XREG_TCR_PIT_INTERRUPT_ENABLE);	\
+		timer_lo_clk_ticks = mfspr(XREG_SPR_PIT);			\
+		mtspr(XREG_SPR_PIT, 0);	\
+	}
+#else
+#define disable_timer() 	\
+   { \
+      u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+      u32 tmp_v = ProfIo_In32(addr); \
+      tmp_v = tmp_v & ~XTC_CSR_ENABLE_TMR_MASK; \
+      ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+   }
+#endif
+
+
+
+//--------------------------------------------------------------------
+// Enable the Timer
+//
+// For PIT Timer -
+//	1. Load the remaining timer clk ticks
+//	2. XTime_PITEnableInterrupt() ;
+//--------------------------------------------------------------------
+#ifdef PPC_PIT_INTERRUPT
+#define enable_timer()				\
+	{					\
+		unsigned long val;		\
+		val=mfspr(XREG_SPR_TCR);	\
+		mtspr(XREG_SPR_PIT, timer_lo_clk_ticks);	\
+		mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
+	}
+#else
+#define enable_timer()						\
+	{							\
+      u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+      u32 tmp_v = ProfIo_In32(addr); \
+      tmp_v = tmp_v |  XTC_CSR_ENABLE_TMR_MASK; \
+      ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+	}
+#endif
+
+
+
+//--------------------------------------------------------------------
+// Send Ack to Timer Interrupt
+//
+// For PIT Timer -
+// 	1. Load the timer clk ticks
+//	2. Enable AutoReload and Interrupt
+//	3. Clear PIT Timer Status bits
+//--------------------------------------------------------------------
+#ifdef PPC_PIT_INTERRUPT
+#define timer_ack()							\
+	{								\
+		unsigned long val;					\
+		mtspr(XREG_SPR_PIT, timer_clk_ticks);			\
+		mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS);	\
+		val=mfspr(XREG_SPR_TCR);				\
+		mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
+	}
+#else
+#define timer_ack()				\
+	{						\
+		unsigned int csr;			\
+		csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0);	\
+		ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr);	\
+	}
+#endif
+
+//--------------------------------------------------------------------
+#endif	// PROC_PPC
+//--------------------------------------------------------------------
+
+
+
+
+//--------------------------------------------------------------------
+// MicroBlaze Target - Timer related functions
+//--------------------------------------------------------------------
+#ifdef PROC_MICROBLAZE
+
+//--------------------------------------------------------------------
+// Disable the Timer during Call-Graph Data collection
+//
+//--------------------------------------------------------------------
+#define disable_timer()					\
+	{						\
+      u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+      u32 tmp_v = ProfIo_In32(addr); \
+      tmp_v = tmp_v & ~XTC_CSR_ENABLE_TMR_MASK; \
+      ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+    }
+
+
+//--------------------------------------------------------------------
+// Enable the Timer after Call-Graph Data collection
+//
+//--------------------------------------------------------------------
+#define enable_timer()					\
+	{						\
+      u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+      u32 tmp_v = ProfIo_In32(addr); \
+      tmp_v = tmp_v |  XTC_CSR_ENABLE_TMR_MASK; \
+      ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+	}
+
+
+//--------------------------------------------------------------------
+// Send Ack to Timer Interrupt
+//
+//--------------------------------------------------------------------
+#define timer_ack()				\
+	{						\
+		unsigned int csr;			\
+		csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0);	\
+		ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr);	\
+	}
+
+//--------------------------------------------------------------------
+#endif	// PROC_MICROBLAZE
+//--------------------------------------------------------------------
+
+//--------------------------------------------------------------------
+// Cortex A9 Target - Timer related functions
+//--------------------------------------------------------------------
+#ifdef PROC_CORTEXA9
+
+//--------------------------------------------------------------------
+// Disable the Timer during Call-Graph Data collection
+//
+//--------------------------------------------------------------------
+#define disable_timer()							\
+{								\
+	u32 Reg;							\
+	Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+	Reg &= ~XSCUTIMER_CONTROL_ENABLE_MASK;\
+	Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}								\
+
+
+//--------------------------------------------------------------------
+// Enable the Timer after Call-Graph Data collection
+//
+//--------------------------------------------------------------------
+#define enable_timer()							\
+{								\
+	u32 Reg;							\
+	Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+	Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
+	Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}								\
+
+
+//--------------------------------------------------------------------
+// Send Ack to Timer Interrupt
+//
+//--------------------------------------------------------------------
+#define timer_ack()						\
+{							\
+	Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_ISR_OFFSET, \
+		XSCUTIMER_ISR_EVENT_FLAG_MASK);\
+}
+
+//--------------------------------------------------------------------
+#endif	// PROC_CORTEXA9
+//--------------------------------------------------------------------
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

quad/sw/system_bsp/ps7_cortexa9_0/include/bspconfig.h

+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by libgen.
+* Version: Xilinx EDK 14.7 EDK_P.20131013
+* DO NOT EDIT.
+*
+* Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
+
+* 
+* Description: Configurations for Standalone BSP
+*
+*******************************************************************/
+
+#define MICROBLAZE_PVR_NONE

quad/sw/system_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h

+//////////////////////////////////////////////////////////////////////
+//
+// Copyright (c) 2002-11 Xilinx, Inc.  All rights reserved.
+// Xilinx, Inc.
+//
+// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+// COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
+// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
+// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
+// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
+// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
+// AND FITNESS FOR A PARTICULAR PURPOSE.
+//
+// $Id: mblaze_nt_types.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $
+//
+//////////////////////////////////////////////////////////////////////
+
+#ifndef _MBLAZE_NT_TYPES_H
+#define _MBLAZE_NT_TYPES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef char            byte;
+typedef short           half;
+typedef int             word;
+typedef unsigned char   ubyte;
+typedef unsigned short  uhalf;
+typedef unsigned int    uword;
+typedef ubyte           boolean;
+
+//typedef unsigned char   u_char;
+//typedef unsigned short  u_short;
+//typedef unsigned int    u_int;
+//typedef unsigned long   u_long;
+
+typedef short           int16_t;
+typedef unsigned short  uint16_t;
+typedef int             int32_t;
+typedef unsigned int    uint32_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

quad/sw/system_bsp/ps7_cortexa9_0/include/profile.h

+//////////////////////////////////////////////////////////////////////
+//
+// Copyright (c) 2002-11 Xilinx, Inc.  All rights reserved.
+// Xilinx, Inc.
+//
+// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+// COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
+// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
+// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
+// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
+// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
+// AND FITNESS FOR A PARTICULAR PURPOSE.
+//
+// $Id: profile.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $
+//
+//////////////////////////////////////////////////////////////////////
+
+#ifndef	_PROFILE_H
+#define	_PROFILE_H	1
+
+#include <stdio.h>
+#include "mblaze_nt_types.h"
+#include "profile_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void _system_init( void ) ;
+void _system_clean( void ) ;
+void mcount(unsigned long frompc, unsigned long selfpc);
+void profile_intr_handler( void ) ;
+
+
+
+/****************************************************************************
+ * Profiling on hardware - Hash table maintained on hardware and data sent
+ * to xmd for gmon.out generation.
+ ****************************************************************************/
+/*
+ * histogram counters are unsigned shorts (according to the kernel).
+ */
+#define	HISTCOUNTER	unsigned short
+
+struct tostruct {
+	unsigned long  selfpc;
+	long	       count;
+	short 	       link;
+	unsigned short pad;
+};
+
+struct fromstruct {
+	unsigned long frompc ;
+	short link ;
+	unsigned short pad ;
+} ;
+
+/*
+ * general rounding functions.
+ */
+#define ROUNDDOWN(x,y)	(((x)/(y))*(y))
+#define ROUNDUP(x,y)	((((x)+(y)-1)/(y))*(y))
+
+/*
+ * The profiling data structures are housed in this structure.
+ */
+struct gmonparam {
+	long int		state;
+
+	// Histogram Information
+	unsigned short		*kcount;	/* No. of bins in histogram */
+	unsigned long		kcountsize;	/* Histogram samples */
+
+	// Call-graph Information
+	struct fromstruct	*froms;
+	unsigned long		fromssize;
+	struct tostruct		*tos;
+	unsigned long		tossize;
+
+	// Initialization I/Ps
+	unsigned long    	lowpc;
+	unsigned long		highpc;
+	unsigned long		textsize;
+	//unsigned long 		cg_froms;
+	//unsigned long 		cg_tos;
+};
+extern struct gmonparam *_gmonparam;
+extern int n_gmon_sections;
+
+/*
+ * Possible states of profiling.
+ */
+#define	GMON_PROF_ON	0
+#define	GMON_PROF_BUSY	1
+#define	GMON_PROF_ERROR	2
+#define	GMON_PROF_OFF	3
+
+/*
+ * Sysctl definitions for extracting profiling information from the kernel.
+ */
+#define	GPROF_STATE	0	/* int: profiling enabling variable */
+#define	GPROF_COUNT	1	/* struct: profile tick count buffer */
+#define	GPROF_FROMS	2	/* struct: from location hash bucket */
+#define	GPROF_TOS	3	/* struct: destination/count structure */
+#define	GPROF_GMONPARAM	4	/* struct: profiling parameters (see above) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 		/* _PROFILE_H */
+
+
+
+
+
+
+
+
+
+
+
+

quad/sw/system_bsp/ps7_cortexa9_0/include/sleep.h

+/******************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+#ifndef SLEEP_H
+#define SLEEP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void nanosleep(unsigned int nanoseconds);
+int usleep(unsigned int useconds);
+int sleep(unsigned int seconds);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

quad/sw/system_bsp/ps7_cortexa9_0/include/smc.h

+/******************************************************************************
+*
+* (c) Copyright 2010-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file smc.h
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  11/03/09 Initial release.
+* </pre>
+*
+* @note		None.
+*
+******************************************************************************/
+
+#ifndef SMC_H /* prevent circular inclusions */
+#define SMC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xil_io.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Memory controller configuration register offset */
+#define XSMCPSS_MC_STATUS		0x000	/* Controller status reg, RO */
+#define XSMCPSS_MC_INTERFACE_CONFIG	0x004	/* Interface config reg, RO */
+#define XSMCPSS_MC_SET_CONFIG		0x008	/* Set configuration reg, WO */
+#define XSMCPSS_MC_CLR_CONFIG		0x00C	/* Clear config reg, WO */
+#define XSMCPSS_MC_DIRECT_CMD		0x010	/* Direct command reg, WO */
+#define XSMCPSS_MC_SET_CYCLES		0x014	/* Set cycles register, WO */
+#define XSMCPSS_MC_SET_OPMODE		0x018	/* Set opmode register, WO */
+#define XSMCPSS_MC_REFRESH_PERIOD_0	0x020	/* Refresh period_0 reg, RW */
+#define XSMCPSS_MC_REFRESH_PERIOD_1	0x024	/* Refresh period_1 reg, RW */
+
+/* Chip select configuration register offset */
+#define XSMCPSS_CS_IF0_CHIP_0_OFFSET	0x100	/* Interface 0 chip 0 config */
+#define XSMCPSS_CS_IF0_CHIP_1_OFFSET	0x120	/* Interface 0 chip 1 config */
+#define XSMCPSS_CS_IF0_CHIP_2_OFFSET	0x140	/* Interface 0 chip 2 config */
+#define XSMCPSS_CS_IF0_CHIP_3_OFFSET	0x160	/* Interface 0 chip 3 config */
+#define XSMCPSS_CS_IF1_CHIP_0_OFFSET	0x180	/* Interface 1 chip 0 config */
+#define XSMCPSS_CS_IF1_CHIP_1_OFFSET	0x1A0	/* Interface 1 chip 1 config */
+#define XSMCPSS_CS_IF1_CHIP_2_OFFSET	0x1C0	/* Interface 1 chip 2 config */
+#define XSMCPSS_CS_IF1_CHIP_3_OFFSET	0x1E0	/* Interface 1 chip 3 config */
+
+/* User configuration register offset */
+#define XSMCPSS_UC_STATUS_OFFSET	0x200	/* User status reg, RO */
+#define XSMCPSS_UC_CONFIG_OFFSET	0x204	/* User config reg, WO */
+
+/* Integration test register offset */
+#define XSMCPSS_IT_OFFSET		0xE00
+
+/* ID configuration register offset */
+#define XSMCPSS_ID_PERIP_0_OFFSET	0xFE0
+#define XSMCPSS_ID_PERIP_1_OFFSET	0xFE4
+#define XSMCPSS_ID_PERIP_2_OFFSET	0xFE8
+#define XSMCPSS_ID_PERIP_3_OFFSET	0xFEC
+#define XSMCPSS_ID_PCELL_0_OFFSET	0xFF0
+#define XSMCPSS_ID_PCELL_1_OFFSET	0xFF4
+#define XSMCPSS_ID_PCELL_2_OFFSET	0xFF8
+#define XSMCPSS_ID_PCELL_3_OFFSET	0xFFC
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void XSmc_SramInit (void);
+void XSmc_NorInit(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* SMC_H */