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quad/sytem/__xps/platgen.opt 0 → 100644
View file @ f6378157
-p xc7z010clg400-1 -lang vhdl$(PROJECT_SEARCHPATHOPT) $(GLOBAL_SEARCHPATHOPT) -msg __xps/ise/xmsgprops.lst
quad/sytem/__xps/ps7_instance.mhs 0 → 100644
View file @ f6378157
# ##############################################################################
# This is complete Pele System mhs file with tags on it
# Manually created PS7 Internal peripherals for ps7 instance mhs generation
# Tue Aug 9 17:37:48 2011
# Target Board: xilinx.com ml605 Rev D
# Family: zynq
# Speed Grade: -1
# ##############################################################################
PARAMETER VERSION = 2.1.0
PORT IRQ_F2P = ps7_IRQ_F2P , VEC=[15:0], DIR = I
PORT Core0_nFIQ = ps7_Core0_nFIQ , DIR = I
PORT Core0_nIRQ = ps7_Core0_nIRQ , DIR = I
PORT Core1_nFIQ = ps7_Core1_nFIQ , DIR = I
PORT Core1_nIRQ = ps7_Core1_nIRQ , DIR = I
# TAG_NO__START PCW::MPD::PS7::C_USE_CAN0
PORT ps7_can_0_CAN_PHY_RX_pin = ps7_can_0_CAN_PHY_RX, DIR = I
PORT ps7_can_0_CAN_PHY_TX_pin = ps7_can_0_CAN_PHY_TX, DIR = O
# TAG_NO__END
# TAG_NO__START PCW::MPD::PS7::C_USE_M_AXI_GP0
PORT M_AXI_GP0_BREADY = ps7_axi_interconnect_0_M_AXI_GP0_BREADY, DIR = O
PORT M_AXI_GP0_ARVALID = ps7_axi_interconnect_0_M_AXI_GP0_ARVALID, DIR = O
PORT M_AXI_GP0_AWVALID = ps7_axi_interconnect_0_M_AXI_GP0_AWVALID, DIR = O
PORT M_AXI_GP0_WVALID = ps7_axi_interconnect_0_M_AXI_GP0_WVALID, DIR = O
PORT M_AXI_GP0_AWID = ps7_axi_interconnect_0_M_AXI_GP0_AWID, DIR = O, VEC = [31:0]
PORT M_AXI_GP0_RREADY = ps7_axi_interconnect_0_M_AXI_GP0_RREADY, DIR = O
PORT M_AXI_GP0_ARSIZE = ps7_axi_interconnect_0_M_AXI_GP0_ARSIZE, DIR = O, VEC = [2:0]
PORT M_AXI_GP0_AWREADY = ps7_axi_interconnect_0_M_AXI_GP0_AWREADY, DIR = I
PORT M_AXI_GP0_ARID = ps7_axi_interconnect_0_M_AXI_GP0_ARID, DIR = O, VEC = [31:0]
PORT M_AXI_GP0_WID = ps7_axi_interconnect_0_M_AXI_GP0_WID, DIR = O, VEC = [31:0]
PORT M_AXI_GP0_AWBURST = ps7_axi_interconnect_0_M_AXI_GP0_AWBURST, DIR = O, VEC = [1:0]
PORT M_AXI_GP0_ARBURST = ps7_axi_interconnect_0_M_AXI_GP0_ARBURST, DIR = O, VEC = [1:0]
PORT M_AXI_GP0_ARLOCK = ps7_axi_interconnect_0_M_AXI_GP0_ARLOCK, DIR = O, VEC = [1:0]
PORT M_AXI_GP0_AWLOCK = ps7_axi_interconnect_0_M_AXI_GP0_AWLOCK, DIR = O, VEC = [1:0]
PORT M_AXI_GP0_AWSIZE = ps7_axi_interconnect_0_M_AXI_GP0_AWSIZE, DIR = O, VEC = [2:0]
PORT M_AXI_GP0_ARPROT = ps7_axi_interconnect_0_M_AXI_GP0_ARPROT, DIR = O, VEC = [2:0]
PORT M_AXI_GP0_AWPROT = ps7_axi_interconnect_0_M_AXI_GP0_AWPROT, DIR = O, VEC = [2:0]
PORT M_AXI_GP0_ARADDR = ps7_axi_interconnect_0_M_AXI_GP0_ARADDR, DIR = O, VEC = [31:0]
PORT M_AXI_GP0_BID = ps7_axi_interconnect_0_M_AXI_GP0_BID, DIR = I, VEC = [31:0]
PORT M_AXI_GP0_AWADDR = ps7_axi_interconnect_0_M_AXI_GP0_AWADDR, DIR = O, VEC = [31:0]
PORT M_AXI_GP0_WDATA = ps7_axi_interconnect_0_M_AXI_GP0_WDATA, DIR = O, VEC = [31:0]
PORT M_AXI_GP0_ARCACHE = ps7_axi_interconnect_0_M_AXI_GP0_ARCACHE, DIR = O, VEC = [3:0]
PORT M_AXI_GP0_AWQOS = ps7_axi_interconnect_0_M_AXI_GP0_AWQOS, DIR = O, VEC = [3:0]
PORT M_AXI_GP0_ARLEN = ps7_axi_interconnect_0_M_AXI_GP0_ARLEN, DIR = O, VEC = [3:0]
PORT M_AXI_GP0_ARQOS = ps7_axi_interconnect_0_M_AXI_GP0_ARQOS, DIR = O, VEC = [3:0]
PORT M_AXI_GP0_AWCACHE = ps7_axi_interconnect_0_M_AXI_GP0_AWCACHE, DIR = O, VEC = [3:0]
PORT M_AXI_GP0_WREADY = ps7_axi_interconnect_0_M_AXI_GP0_WREADY, DIR = I
PORT M_AXI_GP0_AWLEN = ps7_axi_interconnect_0_M_AXI_GP0_AWLEN, DIR = O, VEC = [3:0]
PORT M_AXI_GP0_WSTRB = ps7_axi_interconnect_0_M_AXI_GP0_WSTRB, DIR = O, VEC = [3:0]
PORT M_AXI_GP0_ACLK = ps7_axi_interconnect_0_M_AXI_GP0_ACLK, DIR = I, SIGIS = CLK
PORT M_AXI_GP0_ARREADY = ps7_axi_interconnect_0_M_AXI_GP0_ARREADY, DIR = I
PORT M_AXI_GP0_BVALID = ps7_axi_interconnect_0_M_AXI_GP0_BVALID, DIR = I
PORT M_AXI_GP0_RLAST = ps7_axi_interconnect_0_M_AXI_GP0_RLAST, DIR = I
PORT M_AXI_GP0_RVALID = ps7_axi_interconnect_0_M_AXI_GP0_RVALID, DIR = I
PORT M_AXI_GP0_RID = ps7_axi_interconnect_0_M_AXI_GP0_RID, DIR = I, VEC = [31:0]
PORT M_AXI_GP0_BRESP = ps7_axi_interconnect_0_M_AXI_GP0_BRESP, DIR = I, VEC = [1:0]
PORT M_AXI_GP0_RRESP = ps7_axi_interconnect_0_M_AXI_GP0_RRESP, DIR = I, VEC = [1:0]
PORT M_AXI_GP0_RDATA = ps7_axi_interconnect_0_M_AXI_GP0_RDATA, DIR = I, VEC = [31:0]
# TAG_NO__END
# TAG_NO__START PCW::MPD::PS7::C_USE_M_AXI_GP1
PORT M_AXI_GP0_WLAST = ps7_axi_interconnect_0_M_AXI_GP0_WLAST, DIR = O
PORT M_AXI_GP1_BREADY = ps7_axi_interconnect_0_M_AXI_GP1_BREADY, DIR = O
PORT M_AXI_GP1_ARQOS = ps7_axi_interconnect_0_M_AXI_GP1_ARQOS, DIR = O, VEC = [3:0]
PORT M_AXI_GP1_ARID = ps7_axi_interconnect_0_M_AXI_GP1_ARID, DIR = O, VEC = [31:0]
PORT M_AXI_GP1_WID = ps7_axi_interconnect_0_M_AXI_GP1_WID, DIR = O, VEC = [31:0]
PORT M_AXI_GP1_AWBURST = ps7_axi_interconnect_0_M_AXI_GP1_AWBURST, DIR = O, VEC = [1:0]
PORT M_AXI_GP1_ARBURST = ps7_axi_interconnect_0_M_AXI_GP1_ARBURST, DIR = O, VEC = [1:0]
PORT M_AXI_GP1_ARLOCK = ps7_axi_interconnect_0_M_AXI_GP1_ARLOCK, DIR = O, VEC = [1:0]
PORT M_AXI_GP1_AWLOCK = ps7_axi_interconnect_0_M_AXI_GP1_AWLOCK, DIR = O, VEC = [1:0]
PORT M_AXI_GP1_AWSIZE = ps7_axi_interconnect_0_M_AXI_GP1_AWSIZE, DIR = O, VEC = [2:0]
PORT M_AXI_GP1_ARPROT = ps7_axi_interconnect_0_M_AXI_GP1_ARPROT, DIR = O, VEC = [2:0]
PORT M_AXI_GP1_AWPROT = ps7_axi_interconnect_0_M_AXI_GP1_AWPROT, DIR = O, VEC = [2:0]
PORT M_AXI_GP1_ARADDR = ps7_axi_interconnect_0_M_AXI_GP1_ARADDR, DIR = O, VEC = [31:0]
PORT M_AXI_GP1_BID = ps7_axi_interconnect_0_M_AXI_GP1_BID, DIR = I, VEC = [31:0]
PORT M_AXI_GP1_AWADDR = ps7_axi_interconnect_0_M_AXI_GP1_AWADDR, DIR = O, VEC = [31:0]
PORT M_AXI_GP1_WDATA = ps7_axi_interconnect_0_M_AXI_GP1_WDATA, DIR = O, VEC = [31:0]
PORT M_AXI_GP1_ARCACHE = ps7_axi_interconnect_0_M_AXI_GP1_ARCACHE, DIR = O, VEC = [3:0]
PORT M_AXI_GP1_ARLEN = ps7_axi_interconnect_0_M_AXI_GP1_ARLEN, DIR = O, VEC = [3:0]
PORT M_AXI_GP1_RLAST = ps7_axi_interconnect_0_M_AXI_GP1_RLAST, DIR = I
PORT M_AXI_GP1_AWQOS = ps7_axi_interconnect_0_M_AXI_GP1_AWQOS, DIR = O, VEC = [3:0]
PORT M_AXI_GP1_AWREADY = ps7_axi_interconnect_0_M_AXI_GP1_AWREADY, DIR = I
PORT M_AXI_GP1_AWCACHE = ps7_axi_interconnect_0_M_AXI_GP1_AWCACHE, DIR = O, VEC = [3:0]
PORT M_AXI_GP1_AWLEN = ps7_axi_interconnect_0_M_AXI_GP1_AWLEN, DIR = O, VEC = [3:0]
PORT M_AXI_GP1_WSTRB = ps7_axi_interconnect_0_M_AXI_GP1_WSTRB, DIR = O, VEC = [3:0]
PORT M_AXI_GP1_WREADY = ps7_axi_interconnect_0_M_AXI_GP1_WREADY, DIR = I
PORT M_AXI_GP1_ACLK = ps7_axi_interconnect_0_M_AXI_GP1_ACLK, DIR = I, SIGIS = CLK
PORT M_AXI_GP1_ARREADY = ps7_axi_interconnect_0_M_AXI_GP1_ARREADY, DIR = I
PORT M_AXI_GP1_BVALID = ps7_axi_interconnect_0_M_AXI_GP1_BVALID, DIR = I
PORT M_AXI_GP1_RVALID = ps7_axi_interconnect_0_M_AXI_GP1_RVALID, DIR = I
PORT M_AXI_GP1_RDATA = ps7_axi_interconnect_0_M_AXI_GP1_RDATA, DIR = I, VEC = [31:0]
PORT M_AXI_GP1_RID = ps7_axi_interconnect_0_M_AXI_GP1_RID, DIR = I, VEC = [31:0]
PORT M_AXI_GP1_BRESP = ps7_axi_interconnect_0_M_AXI_GP1_BRESP, DIR = I, VEC = [1:0]
PORT M_AXI_GP1_RRESP = ps7_axi_interconnect_0_M_AXI_GP1_RRESP, DIR = I, VEC = [1:0]
PORT M_AXI_GP1_RREADY = ps7_axi_interconnect_0_M_AXI_GP1_RREADY, DIR = O
PORT M_AXI_GP1_WVALID = ps7_axi_interconnect_0_M_AXI_GP1_WVALID, DIR = O
PORT M_AXI_GP1_ARVALID = ps7_axi_interconnect_0_M_AXI_GP1_ARVALID, DIR = O
PORT M_AXI_GP1_AWID = ps7_axi_interconnect_0_M_AXI_GP1_AWID, DIR = O, VEC = [31:0]
PORT M_AXI_GP1_WLAST = ps7_axi_interconnect_0_M_AXI_GP1_WLAST, DIR = O
PORT M_AXI_GP1_ARSIZE = ps7_axi_interconnect_0_M_AXI_GP1_ARSIZE, DIR = O, VEC = [2:0]
PORT M_AXI_GP1_AWVALID = ps7_axi_interconnect_0_M_AXI_GP1_AWVALID, DIR = O
# TAG_NO__END
# TAG_NO__START PCW::MPD::PS7::C_USE_S_AXI_GP0
PORT S_AXI_GP0_RLAST = ps7_axi_interconnect_0_S_AXI_GP0_RLAST, DIR = O
PORT S_AXI_GP0_BVALID = ps7_axi_interconnect_0_S_AXI_GP0_BVALID, DIR = O
PORT S_AXI_GP0_ARQOS = ps7_axi_interconnect_0_S_AXI_GP0_ARQOS, DIR = I, VEC = [3:0]
PORT S_AXI_GP0_AWBURST = ps7_axi_interconnect_0_S_AXI_GP0_AWBURST, DIR = I, VEC = [1:0]
PORT S_AXI_GP0_AWLOCK = ps7_axi_interconnect_0_S_AXI_GP0_AWLOCK, DIR = I, VEC = [1:0]
PORT S_AXI_GP0_AWSIZE = ps7_axi_interconnect_0_S_AXI_GP0_AWSIZE, DIR = I, VEC = [2:0]
PORT S_AXI_GP0_ARPROT = ps7_axi_interconnect_0_S_AXI_GP0_ARPROT, DIR = I, VEC = [2:0]
PORT S_AXI_GP0_AWPROT = ps7_axi_interconnect_0_S_AXI_GP0_AWPROT, DIR = I, VEC = [2:0]
PORT S_AXI_GP0_ARADDR = ps7_axi_interconnect_0_S_AXI_GP0_ARADDR, DIR = I, VEC = [31:0]
PORT S_AXI_GP0_AWADDR = ps7_axi_interconnect_0_S_AXI_GP0_AWADDR, DIR = I, VEC = [31:0]
PORT S_AXI_GP0_WDATA = ps7_axi_interconnect_0_S_AXI_GP0_WDATA, DIR = I, VEC = [31:0]
PORT S_AXI_GP0_ARCACHE = ps7_axi_interconnect_0_S_AXI_GP0_ARCACHE, DIR = I, VEC = [3:0]
PORT S_AXI_GP0_ARLEN = ps7_axi_interconnect_0_S_AXI_GP0_ARLEN, DIR = I, VEC = [3:0]
PORT S_AXI_GP0_AWQOS = ps7_axi_interconnect_0_S_AXI_GP0_AWQOS, DIR = I, VEC = [3:0]
PORT S_AXI_GP0_AWCACHE = ps7_axi_interconnect_0_S_AXI_GP0_AWCACHE, DIR = I, VEC = [3:0]
PORT S_AXI_GP0_WSTRB = ps7_axi_interconnect_0_S_AXI_GP0_WSTRB, DIR = I, VEC = [3:0]
PORT S_AXI_GP0_ARID = ps7_axi_interconnect_0_S_AXI_GP0_ARID, DIR = I, VEC = [31:0]
PORT S_AXI_GP0_AWID = ps7_axi_interconnect_0_S_AXI_GP0_AWID, DIR = I, VEC = [31:0]
PORT S_AXI_GP0_WID = ps7_axi_interconnect_0_S_AXI_GP0_WID, DIR = I, VEC = [31:0]
PORT S_AXI_GP0_AWREADY = ps7_axi_interconnect_0_S_AXI_GP0_AWREADY, DIR = O
PORT S_AXI_GP0_BRESP = ps7_axi_interconnect_0_S_AXI_GP0_BRESP, DIR = O, VEC = [1:0]
PORT S_AXI_GP0_ARREADY = ps7_axi_interconnect_0_S_AXI_GP0_ARREADY, DIR = O
PORT S_AXI_GP0_RVALID = ps7_axi_interconnect_0_S_AXI_GP0_RVALID, DIR = O
PORT S_AXI_GP0_RRESP = ps7_axi_interconnect_0_S_AXI_GP0_RRESP, DIR = O, VEC = [1:0]
PORT S_AXI_GP0_AWVALID = ps7_axi_interconnect_0_S_AXI_GP0_AWVALID, DIR = I
PORT S_AXI_GP0_RREADY = ps7_axi_interconnect_0_S_AXI_GP0_RREADY, DIR = I
PORT S_AXI_GP0_RDATA = ps7_axi_interconnect_0_S_AXI_GP0_RDATA, DIR = O, VEC = [31:0]
PORT S_AXI_GP0_WLAST = ps7_axi_interconnect_0_S_AXI_GP0_WLAST, DIR = I
PORT S_AXI_GP0_BID = ps7_axi_interconnect_0_S_AXI_GP0_BID, DIR = O, VEC = [31:0]
PORT S_AXI_GP0_RID = ps7_axi_interconnect_0_S_AXI_GP0_RID, DIR = O, VEC = [31:0]
PORT S_AXI_GP0_ACLK = ps7_axi_interconnect_0_S_AXI_GP0_ACLK, DIR = I, SIGIS = CLK
PORT S_AXI_GP0_ARVALID = ps7_axi_interconnect_0_S_AXI_GP0_ARVALID, DIR = I
PORT S_AXI_GP0_BREADY = ps7_axi_interconnect_0_S_AXI_GP0_BREADY, DIR = I
PORT S_AXI_GP0_WVALID = ps7_axi_interconnect_0_S_AXI_GP0_WVALID, DIR = I
PORT S_AXI_GP0_ARSIZE = ps7_axi_interconnect_0_S_AXI_GP0_ARSIZE, DIR = I, VEC = [2:0]
PORT S_AXI_GP0_AWLEN = ps7_axi_interconnect_0_S_AXI_GP0_AWLEN, DIR = I, VEC = [3:0]
PORT S_AXI_GP0_ARBURST = ps7_axi_interconnect_0_S_AXI_GP0_ARBURST, DIR = I, VEC = [1:0]
PORT S_AXI_GP0_ARLOCK = ps7_axi_interconnect_0_S_AXI_GP0_ARLOCK, DIR = I, VEC = [1:0]
PORT S_AXI_GP0_WREADY = ps7_axi_interconnect_0_S_AXI_GP0_WREADY, DIR = O
# TAG_NO__END
# TAG_NO__START PCW::MPD::PS7::C_USE_S_AXI_GP1
PORT S_AXI_GP1_WREADY = ps7_axi_interconnect_0_S_AXI_GP1_WREADY, DIR = O
PORT S_AXI_GP1_RID = ps7_axi_interconnect_0_S_AXI_GP1_RID, DIR = O, VEC = [2:0]
PORT S_AXI_GP1_ACLK = ps7_axi_interconnect_0_S_AXI_GP1_ACLK, DIR = I, SIGIS = CLK
PORT S_AXI_GP1_ARVALID = ps7_axi_interconnect_0_S_AXI_GP1_ARVALID, DIR = I
PORT S_AXI_GP1_BREADY = ps7_axi_interconnect_0_S_AXI_GP1_BREADY, DIR = I
PORT S_AXI_GP1_WVALID = ps7_axi_interconnect_0_S_AXI_GP1_WVALID, DIR = I
PORT S_AXI_GP1_ARSIZE = ps7_axi_interconnect_0_S_AXI_GP1_ARSIZE, DIR = I, VEC = [2:0]
PORT S_AXI_GP1_ARBURST = ps7_axi_interconnect_0_S_AXI_GP1_ARBURST, DIR = I, VEC = [1:0]
PORT S_AXI_GP1_ARLOCK = ps7_axi_interconnect_0_S_AXI_GP1_ARLOCK, DIR = I, VEC = [1:0]
PORT S_AXI_GP1_AWBURST = ps7_axi_interconnect_0_S_AXI_GP1_AWBURST, DIR = I, VEC = [1:0]
PORT S_AXI_GP1_AWLOCK = ps7_axi_interconnect_0_S_AXI_GP1_AWLOCK, DIR = I, VEC = [1:0]
PORT S_AXI_GP1_AWSIZE = ps7_axi_interconnect_0_S_AXI_GP1_AWSIZE, DIR = I, VEC = [2:0]
PORT S_AXI_GP1_ARPROT = ps7_axi_interconnect_0_S_AXI_GP1_ARPROT, DIR = I, VEC = [2:0]
PORT S_AXI_GP1_AWPROT = ps7_axi_interconnect_0_S_AXI_GP1_AWPROT, DIR = I, VEC = [2:0]
PORT S_AXI_GP1_ARADDR = ps7_axi_interconnect_0_S_AXI_GP1_ARADDR, DIR = I, VEC = [31:0]
PORT S_AXI_GP1_AWADDR = ps7_axi_interconnect_0_S_AXI_GP1_AWADDR, DIR = I, VEC = [31:0]
PORT S_AXI_GP1_WDATA = ps7_axi_interconnect_0_S_AXI_GP1_WDATA, DIR = I, VEC = [31:0]
PORT S_AXI_GP1_ARCACHE = ps7_axi_interconnect_0_S_AXI_GP1_ARCACHE, DIR = I, VEC = [3:0]
PORT S_AXI_GP1_ARQOS = ps7_axi_interconnect_0_S_AXI_GP1_ARQOS, DIR = I, VEC = [3:0]
PORT S_AXI_GP1_ARLEN = ps7_axi_interconnect_0_S_AXI_GP1_ARLEN, DIR = I, VEC = [3:0]
PORT S_AXI_GP1_AWQOS = ps7_axi_interconnect_0_S_AXI_GP1_AWQOS, DIR = I, VEC = [3:0]
PORT S_AXI_GP1_AWCACHE = ps7_axi_interconnect_0_S_AXI_GP1_AWCACHE, DIR = I, VEC = [3:0]
PORT S_AXI_GP1_AWLEN = ps7_axi_interconnect_0_S_AXI_GP1_AWLEN, DIR = I, VEC = [3:0]
PORT S_AXI_GP1_WSTRB = ps7_axi_interconnect_0_S_AXI_GP1_WSTRB, DIR = I, VEC = [3:0]
PORT S_AXI_GP1_ARID = ps7_axi_interconnect_0_S_AXI_GP1_ARID, DIR = I, VEC = [31:0]
PORT S_AXI_GP1_AWID = ps7_axi_interconnect_0_S_AXI_GP1_AWID, DIR = I, VEC = [31:0]
PORT S_AXI_GP1_WID = ps7_axi_interconnect_0_S_AXI_GP1_WID, DIR = I, VEC = [31:0]
PORT S_AXI_GP1_BVALID = ps7_axi_interconnect_0_S_AXI_GP1_BVALID, DIR = O
PORT S_AXI_GP1_ARREADY = ps7_axi_interconnect_0_S_AXI_GP1_ARREADY, DIR = O
PORT S_AXI_GP1_RVALID = ps7_axi_interconnect_0_S_AXI_GP1_RVALID, DIR = O
PORT S_AXI_GP1_RRESP = ps7_axi_interconnect_0_S_AXI_GP1_RRESP, DIR = O, VEC = [1:0]
PORT S_AXI_GP1_AWVALID = ps7_axi_interconnect_0_S_AXI_GP1_AWVALID, DIR = I
PORT S_AXI_GP1_RREADY = ps7_axi_interconnect_0_S_AXI_GP1_RREADY, DIR = I
PORT S_AXI_GP1_RDATA = ps7_axi_interconnect_0_S_AXI_GP1_RDATA, DIR = O, VEC = [31:0]
PORT S_AXI_GP1_WLAST = ps7_axi_interconnect_0_S_AXI_GP1_WLAST, DIR = I
PORT S_AXI_GP1_BID = ps7_axi_interconnect_0_S_AXI_GP1_BID, DIR = O, VEC = [2:0]
PORT S_AXI_GP1_BRESP = ps7_axi_interconnect_0_S_AXI_GP1_BRESP, DIR = O, VEC = [1:0]
PORT S_AXI_GP1_RLAST = ps7_axi_interconnect_0_S_AXI_GP1_RLAST, DIR = O
PORT S_AXI_GP1_AWREADY = ps7_axi_interconnect_0_S_AXI_GP1_AWREADY, DIR = O
# TAG_NO__END
# TAG_NO__START PCW::MPD::PS7::C_USE_S_AXI_HP0
PORT S_AXI_HP0_BRESP = ps7_axi_interconnect_0_S_AXI_HP0_BRESP, DIR = O, VEC = [1:0]
PORT S_AXI_HP0_WREADY = ps7_axi_interconnect_0_S_AXI_HP0_WREADY, DIR = O
PORT S_AXI_HP0_RLAST = ps7_axi_interconnect_0_S_AXI_HP0_RLAST, DIR = O
PORT S_AXI_HP0_BVALID = ps7_axi_interconnect_0_S_AXI_HP0_BVALID, DIR = O
PORT S_AXI_HP0_AWREADY = ps7_axi_interconnect_0_S_AXI_HP0_AWREADY, DIR = O
PORT S_AXI_HP0_ARREADY = ps7_axi_interconnect_0_S_AXI_HP0_ARREADY, DIR = O
PORT S_AXI_HP0_RVALID = ps7_axi_interconnect_0_S_AXI_HP0_RVALID, DIR = O
PORT S_AXI_HP0_AWID = ps7_axi_interconnect_0_S_AXI_HP0_AWID, DIR = I, VEC = [5:0]
PORT S_AXI_HP0_WID = ps7_axi_interconnect_0_S_AXI_HP0_WID, DIR = I, VEC = [5:0]
PORT S_AXI_HP0_WDATA = ps7_axi_interconnect_0_S_AXI_HP0_WDATA, DIR = I, VEC = [63:0]
PORT S_AXI_HP0_WSTRB = ps7_axi_interconnect_0_S_AXI_HP0_WSTRB, DIR = I, VEC = [7:0]
PORT S_AXI_HP0_RRESP = ps7_axi_interconnect_0_S_AXI_HP0_RRESP, DIR = O, VEC = [1:0]
PORT S_AXI_HP0_AWVALID = ps7_axi_interconnect_0_S_AXI_HP0_AWVALID, DIR = I
PORT S_AXI_HP0_RREADY = ps7_axi_interconnect_0_S_AXI_HP0_RREADY, DIR = I
PORT S_AXI_HP0_BID = ps7_axi_interconnect_0_S_AXI_HP0_BID, DIR = O, VEC = [5:0]
PORT S_AXI_HP0_WLAST = ps7_axi_interconnect_0_S_AXI_HP0_WLAST, DIR = I
PORT S_AXI_HP0_RID = ps7_axi_interconnect_0_S_AXI_HP0_RID, DIR = O, VEC = [5:0]
PORT S_AXI_HP0_RDATA = ps7_axi_interconnect_0_S_AXI_HP0_RDATA, DIR = O, VEC = [63:0]
PORT S_AXI_HP0_ACLK = ps7_axi_interconnect_0_S_AXI_HP0_ACLK, DIR = I, SIGIS = CLK
PORT S_AXI_HP0_ARVALID = ps7_axi_interconnect_0_S_AXI_HP0_ARVALID, DIR = I
PORT S_AXI_HP0_BREADY = ps7_axi_interconnect_0_S_AXI_HP0_BREADY, DIR = I
PORT S_AXI_HP0_WVALID = ps7_axi_interconnect_0_S_AXI_HP0_WVALID, DIR = I
PORT S_AXI_HP0_ARSIZE = ps7_axi_interconnect_0_S_AXI_HP0_ARSIZE, DIR = I, VEC = [2:0]
PORT S_AXI_HP0_ARBURST = ps7_axi_interconnect_0_S_AXI_HP0_ARBURST, DIR = I, VEC = [1:0]
PORT S_AXI_HP0_ARLOCK = ps7_axi_interconnect_0_S_AXI_HP0_ARLOCK, DIR = I, VEC = [1:0]
PORT S_AXI_HP0_AWBURST = ps7_axi_interconnect_0_S_AXI_HP0_AWBURST, DIR = I, VEC = [1:0]
PORT S_AXI_HP0_AWLOCK = ps7_axi_interconnect_0_S_AXI_HP0_AWLOCK, DIR = I, VEC = [1:0]
PORT S_AXI_HP0_AWSIZE = ps7_axi_interconnect_0_S_AXI_HP0_AWSIZE, DIR = I, VEC = [2:0]
PORT S_AXI_HP0_ARPROT = ps7_axi_interconnect_0_S_AXI_HP0_ARPROT, DIR = I, VEC = [2:0]
PORT S_AXI_HP0_AWPROT = ps7_axi_interconnect_0_S_AXI_HP0_AWPROT, DIR = I, VEC = [2:0]
PORT S_AXI_HP0_ARADDR = ps7_axi_interconnect_0_S_AXI_HP0_ARADDR, DIR = I, VEC = [31:0]
PORT S_AXI_HP0_AWADDR = ps7_axi_interconnect_0_S_AXI_HP0_AWADDR, DIR = I, VEC = [31:0]
PORT S_AXI_HP0_ARCACHE = ps7_axi_interconnect_0_S_AXI_HP0_ARCACHE, DIR = I, VEC = [3:0]
PORT S_AXI_HP0_ARLEN = ps7_axi_interconnect_0_S_AXI_HP0_ARLEN, DIR = I, VEC = [3:0]
PORT S_AXI_HP0_ARQOS = ps7_axi_interconnect_0_S_AXI_HP0_ARQOS, DIR = I, VEC = [3:0]
PORT S_AXI_HP0_AWCACHE = ps7_axi_interconnect_0_S_AXI_HP0_AWCACHE, DIR = I, VEC = [3:0]
PORT S_AXI_HP0_AWQOS = ps7_axi_interconnect_0_S_AXI_HP0_AWQOS, DIR = I, VEC = [3:0]
PORT S_AXI_HP0_AWLEN = ps7_axi_interconnect_0_S_AXI_HP0_AWLEN, DIR = I, VEC = [3:0]
PORT S_AXI_HP0_ARID = ps7_axi_interconnect_0_S_AXI_HP0_ARID, DIR = I, VEC = [5:0]
# TAG_NO__END
# TAG_NO__START PCW::MPD::PS7::C_USE_S_AXI_HP1
PORT S_AXI_HP1_RLAST = ps7_axi_interconnect_0_S_AXI_HP1_RLAST, DIR = O
PORT S_AXI_HP1_BRESP = ps7_axi_interconnect_0_S_AXI_HP1_BRESP, DIR = O, VEC = [1:0]
PORT S_AXI_HP1_ARREADY = ps7_axi_interconnect_0_S_AXI_HP1_ARREADY, DIR = O
PORT S_AXI_HP1_AWREADY = ps7_axi_interconnect_0_S_AXI_HP1_AWREADY, DIR = O
PORT S_AXI_HP1_WREADY = ps7_axi_interconnect_0_S_AXI_HP1_WREADY, DIR = O
PORT S_AXI_HP1_RVALID = ps7_axi_interconnect_0_S_AXI_HP1_RVALID, DIR = O
PORT S_AXI_HP1_RRESP = ps7_axi_interconnect_0_S_AXI_HP1_RRESP, DIR = O, VEC = [1:0]
PORT S_AXI_HP1_AWVALID = ps7_axi_interconnect_0_S_AXI_HP1_AWVALID, DIR = I
PORT S_AXI_HP1_RREADY = ps7_axi_interconnect_0_S_AXI_HP1_RREADY, DIR = I
PORT S_AXI_HP1_BID = ps7_axi_interconnect_0_S_AXI_HP1_BID, DIR = O, VEC = [5:0]
PORT S_AXI_HP1_WLAST = ps7_axi_interconnect_0_S_AXI_HP1_WLAST, DIR = I
PORT S_AXI_HP1_RID = ps7_axi_interconnect_0_S_AXI_HP1_RID, DIR = O, VEC = [5:0]
PORT S_AXI_HP1_RDATA = ps7_axi_interconnect_0_S_AXI_HP1_RDATA, DIR = O, VEC = [63:0]
PORT S_AXI_HP1_ACLK = ps7_axi_interconnect_0_S_AXI_HP1_ACLK, DIR = I, SIGIS = CLK
PORT S_AXI_HP1_ARVALID = ps7_axi_interconnect_0_S_AXI_HP1_ARVALID, DIR = I
PORT S_AXI_HP1_BREADY = ps7_axi_interconnect_0_S_AXI_HP1_BREADY, DIR = I
PORT S_AXI_HP1_WVALID = ps7_axi_interconnect_0_S_AXI_HP1_WVALID, DIR = I
PORT S_AXI_HP1_ARSIZE = ps7_axi_interconnect_0_S_AXI_HP1_ARSIZE, DIR = I, VEC = [2:0]
PORT S_AXI_HP1_ARBURST = ps7_axi_interconnect_0_S_AXI_HP1_ARBURST, DIR = I, VEC = [1:0]
PORT S_AXI_HP1_ARLOCK = ps7_axi_interconnect_0_S_AXI_HP1_ARLOCK, DIR = I, VEC = [1:0]
PORT S_AXI_HP1_AWBURST = ps7_axi_interconnect_0_S_AXI_HP1_AWBURST, DIR = I, VEC = [1:0]
PORT S_AXI_HP1_AWLOCK = ps7_axi_interconnect_0_S_AXI_HP1_AWLOCK, DIR = I, VEC = [1:0]
PORT S_AXI_HP1_AWSIZE = ps7_axi_interconnect_0_S_AXI_HP1_AWSIZE, DIR = I, VEC = [2:0]
PORT S_AXI_HP1_ARPROT = ps7_axi_interconnect_0_S_AXI_HP1_ARPROT, DIR = I, VEC = [2:0]
PORT S_AXI_HP1_AWPROT = ps7_axi_interconnect_0_S_AXI_HP1_AWPROT, DIR = I, VEC = [2:0]
PORT S_AXI_HP1_ARADDR = ps7_axi_interconnect_0_S_AXI_HP1_ARADDR, DIR = I, VEC = [31:0]
PORT S_AXI_HP1_AWADDR = ps7_axi_interconnect_0_S_AXI_HP1_AWADDR, DIR = I, VEC = [31:0]
PORT S_AXI_HP1_ARCACHE = ps7_axi_interconnect_0_S_AXI_HP1_ARCACHE, DIR = I, VEC = [3:0]
PORT S_AXI_HP1_ARLEN = ps7_axi_interconnect_0_S_AXI_HP1_ARLEN, DIR = I, VEC = [3:0]
PORT S_AXI_HP1_ARQOS = ps7_axi_interconnect_0_S_AXI_HP1_ARQOS, DIR = I, VEC = [3:0]
PORT S_AXI_HP1_AWCACHE = ps7_axi_interconnect_0_S_AXI_HP1_AWCACHE, DIR = I, VEC = [3:0]
PORT S_AXI_HP1_AWQOS = ps7_axi_interconnect_0_S_AXI_HP1_AWQOS, DIR = I, VEC = [3:0]
PORT S_AXI_HP1_AWLEN = ps7_axi_interconnect_0_S_AXI_HP1_AWLEN, DIR = I, VEC = [3:0]
PORT S_AXI_HP1_ARID = ps7_axi_interconnect_0_S_AXI_HP1_ARID, DIR = I, VEC = [5:0]
PORT S_AXI_HP1_AWID = ps7_axi_interconnect_0_S_AXI_HP1_AWID, DIR = I, VEC = [5:0]
PORT S_AXI_HP1_WID = ps7_axi_interconnect_0_S_AXI_HP1_WID, DIR = I, VEC = [5:0]
PORT S_AXI_HP1_WDATA = ps7_axi_interconnect_0_S_AXI_HP1_WDATA, DIR = I, VEC = [63:0]
PORT S_AXI_HP1_WSTRB = ps7_axi_interconnect_0_S_AXI_HP1_WSTRB, DIR = I, VEC = [7:0]
PORT S_AXI_HP1_BVALID = ps7_axi_interconnect_0_S_AXI_HP1_BVALID, DIR = O
# TAG_NO__END
# TAG_NO__START PCW::MPD::PS7::C_USE_S_AXI_HP2
PORT S_AXI_HP2_ARREADY = ps7_axi_interconnect_0_S_AXI_HP2_ARREADY, DIR = O
PORT S_AXI_HP2_BVALID = ps7_axi_interconnect_0_S_AXI_HP2_BVALID, DIR = O
PORT S_AXI_HP2_BRESP = ps7_axi_interconnect_0_S_AXI_HP2_BRESP, DIR = O, VEC = [1:0]
PORT S_AXI_HP2_WREADY = ps7_axi_interconnect_0_S_AXI_HP2_WREADY, DIR = O
PORT S_AXI_HP2_RLAST = ps7_axi_interconnect_0_S_AXI_HP2_RLAST, DIR = O
PORT S_AXI_HP2_AWREADY = ps7_axi_interconnect_0_S_AXI_HP2_AWREADY, DIR = O
PORT S_AXI_HP2_AWSIZE = ps7_axi_interconnect_0_S_AXI_HP2_AWSIZE, DIR = I, VEC = [2:0]
PORT S_AXI_HP2_ARPROT = ps7_axi_interconnect_0_S_AXI_HP2_ARPROT, DIR = I, VEC = [2:0]
PORT S_AXI_HP2_AWPROT = ps7_axi_interconnect_0_S_AXI_HP2_AWPROT, DIR = I, VEC = [2:0]
PORT S_AXI_HP2_ARADDR = ps7_axi_interconnect_0_S_AXI_HP2_ARADDR, DIR = I, VEC = [31:0]
PORT S_AXI_HP2_AWADDR = ps7_axi_interconnect_0_S_AXI_HP2_AWADDR, DIR = I, VEC = [31:0]
PORT S_AXI_HP2_ARCACHE = ps7_axi_interconnect_0_S_AXI_HP2_ARCACHE, DIR = I, VEC = [3:0]
PORT S_AXI_HP2_ARLEN = ps7_axi_interconnect_0_S_AXI_HP2_ARLEN, DIR = I, VEC = [3:0]
PORT S_AXI_HP2_ARQOS = ps7_axi_interconnect_0_S_AXI_HP2_ARQOS, DIR = I, VEC = [3:0]
PORT S_AXI_HP2_AWCACHE = ps7_axi_interconnect_0_S_AXI_HP2_AWCACHE, DIR = I, VEC = [3:0]
PORT S_AXI_HP2_AWQOS = ps7_axi_interconnect_0_S_AXI_HP2_AWQOS, DIR = I, VEC = [3:0]
PORT S_AXI_HP2_AWLEN = ps7_axi_interconnect_0_S_AXI_HP2_AWLEN, DIR = I, VEC = [3:0]
PORT S_AXI_HP2_ARID = ps7_axi_interconnect_0_S_AXI_HP2_ARID, DIR = I, VEC = [5:0]
PORT S_AXI_HP2_AWID = ps7_axi_interconnect_0_S_AXI_HP2_AWID, DIR = I, VEC = [5:0]
PORT S_AXI_HP2_WID = ps7_axi_interconnect_0_S_AXI_HP2_WID, DIR = I, VEC = [5:0]
PORT S_AXI_HP2_WDATA = ps7_axi_interconnect_0_S_AXI_HP2_WDATA, DIR = I, VEC = [63:0]
PORT S_AXI_HP2_WSTRB = ps7_axi_interconnect_0_S_AXI_HP2_WSTRB, DIR = I, VEC = [7:0]
PORT S_AXI_HP2_RVALID = ps7_axi_interconnect_0_S_AXI_HP2_RVALID, DIR = O
PORT S_AXI_HP2_RRESP = ps7_axi_interconnect_0_S_AXI_HP2_RRESP, DIR = O, VEC = [1:0]
PORT S_AXI_HP2_AWVALID = ps7_axi_interconnect_0_S_AXI_HP2_AWVALID, DIR = I
PORT S_AXI_HP2_RREADY = ps7_axi_interconnect_0_S_AXI_HP2_RREADY, DIR = I
PORT S_AXI_HP2_BID = ps7_axi_interconnect_0_S_AXI_HP2_BID, DIR = O, VEC = [5:0]
PORT S_AXI_HP2_WLAST = ps7_axi_interconnect_0_S_AXI_HP2_WLAST, DIR = I
PORT S_AXI_HP2_RID = ps7_axi_interconnect_0_S_AXI_HP2_RID, DIR = O, VEC = [5:0]
PORT S_AXI_HP2_RDATA = ps7_axi_interconnect_0_S_AXI_HP2_RDATA, DIR = O, VEC = [63:0]
PORT S_AXI_HP2_ACLK = ps7_axi_interconnect_0_S_AXI_HP2_ACLK, DIR = I, SIGIS = CLK
PORT S_AXI_HP2_ARVALID = ps7_axi_interconnect_0_S_AXI_HP2_ARVALID, DIR = I
PORT S_AXI_HP2_BREADY = ps7_axi_interconnect_0_S_AXI_HP2_BREADY, DIR = I
PORT S_AXI_HP2_WVALID = ps7_axi_interconnect_0_S_AXI_HP2_WVALID, DIR = I
PORT S_AXI_HP2_ARSIZE = ps7_axi_interconnect_0_S_AXI_HP2_ARSIZE, DIR = I, VEC = [2:0]
PORT S_AXI_HP2_ARBURST = ps7_axi_interconnect_0_S_AXI_HP2_ARBURST, DIR = I, VEC = [1:0]
PORT S_AXI_HP2_ARLOCK = ps7_axi_interconnect_0_S_AXI_HP2_ARLOCK, DIR = I, VEC = [1:0]
PORT S_AXI_HP2_AWBURST = ps7_axi_interconnect_0_S_AXI_HP2_AWBURST, DIR = I, VEC = [1:0]
PORT S_AXI_HP2_AWLOCK = ps7_axi_interconnect_0_S_AXI_HP2_AWLOCK, DIR = I, VEC = [1:0]
# TAG_NO__END
# TAG_NO__START PCW::MPD::PS7::C_USE_S_AXI_HP3
PORT S_AXI_HP3_ARREADY = ps7_axi_interconnect_0_S_AXI_HP3_ARREADY, DIR = O
PORT S_AXI_HP3_WREADY = ps7_axi_interconnect_0_S_AXI_HP3_WREADY, DIR = O
PORT S_AXI_HP3_BVALID = ps7_axi_interconnect_0_S_AXI_HP3_BVALID, DIR = O
PORT S_AXI_HP3_BRESP = ps7_axi_interconnect_0_S_AXI_HP3_BRESP, DIR = O, VEC = [1:0]
PORT S_AXI_HP3_RVALID = ps7_axi_interconnect_0_S_AXI_HP3_RVALID, DIR = O
PORT S_AXI_HP3_RRESP = ps7_axi_interconnect_0_S_AXI_HP3_RRESP, DIR = O, VEC = [1:0]
PORT S_AXI_HP3_AWVALID = ps7_axi_interconnect_0_S_AXI_HP3_AWVALID, DIR = I
PORT S_AXI_HP3_RREADY = ps7_axi_interconnect_0_S_AXI_HP3_RREADY, DIR = I
PORT S_AXI_HP3_BID = ps7_axi_interconnect_0_S_AXI_HP3_BID, DIR = O, VEC = [5:0]
PORT S_AXI_HP3_WLAST = ps7_axi_interconnect_0_S_AXI_HP3_WLAST, DIR = I
PORT S_AXI_HP3_RID = ps7_axi_interconnect_0_S_AXI_HP3_RID, DIR = O, VEC = [5:0]
PORT S_AXI_HP3_RDATA = ps7_axi_interconnect_0_S_AXI_HP3_RDATA, DIR = O, VEC = [63:0]
PORT S_AXI_HP3_ACLK = ps7_axi_interconnect_0_S_AXI_HP3_ACLK, DIR = I, SIGIS = CLK
PORT S_AXI_HP3_ARVALID = ps7_axi_interconnect_0_S_AXI_HP3_ARVALID, DIR = I
PORT S_AXI_HP3_BREADY = ps7_axi_interconnect_0_S_AXI_HP3_BREADY, DIR = I
PORT S_AXI_HP3_WVALID = ps7_axi_interconnect_0_S_AXI_HP3_WVALID, DIR = I
PORT S_AXI_HP3_ARSIZE = ps7_axi_interconnect_0_S_AXI_HP3_ARSIZE, DIR = I, VEC = [2:0]
PORT S_AXI_HP3_ARBURST = ps7_axi_interconnect_0_S_AXI_HP3_ARBURST, DIR = I, VEC = [1:0]
PORT S_AXI_HP3_ARLOCK = ps7_axi_interconnect_0_S_AXI_HP3_ARLOCK, DIR = I, VEC = [1:0]
PORT S_AXI_HP3_AWBURST = ps7_axi_interconnect_0_S_AXI_HP3_AWBURST, DIR = I, VEC = [1:0]
PORT S_AXI_HP3_AWLOCK = ps7_axi_interconnect_0_S_AXI_HP3_AWLOCK, DIR = I, VEC = [1:0]
PORT S_AXI_HP3_AWSIZE = ps7_axi_interconnect_0_S_AXI_HP3_AWSIZE, DIR = I, VEC = [2:0]
PORT S_AXI_HP3_ARPROT = ps7_axi_interconnect_0_S_AXI_HP3_ARPROT, DIR = I, VEC = [2:0]
PORT S_AXI_HP3_AWPROT = ps7_axi_interconnect_0_S_AXI_HP3_AWPROT, DIR = I, VEC = [2:0]
PORT S_AXI_HP3_ARADDR = ps7_axi_interconnect_0_S_AXI_HP3_ARADDR, DIR = I, VEC = [31:0]
PORT S_AXI_HP3_AWADDR = ps7_axi_interconnect_0_S_AXI_HP3_AWADDR, DIR = I, VEC = [31:0]
PORT S_AXI_HP3_ARCACHE = ps7_axi_interconnect_0_S_AXI_HP3_ARCACHE, DIR = I, VEC = [3:0]
PORT S_AXI_HP3_ARLEN = ps7_axi_interconnect_0_S_AXI_HP3_ARLEN, DIR = I, VEC = [3:0]
PORT S_AXI_HP3_ARQOS = ps7_axi_interconnect_0_S_AXI_HP3_ARQOS, DIR = I, VEC = [3:0]
PORT S_AXI_HP3_AWCACHE = ps7_axi_interconnect_0_S_AXI_HP3_AWCACHE, DIR = I, VEC = [3:0]
PORT S_AXI_HP3_AWQOS = ps7_axi_interconnect_0_S_AXI_HP3_AWQOS, DIR = I, VEC = [3:0]
PORT S_AXI_HP3_AWLEN = ps7_axi_interconnect_0_S_AXI_HP3_AWLEN, DIR = I, VEC = [3:0]
PORT S_AXI_HP3_ARID = ps7_axi_interconnect_0_S_AXI_HP3_ARID, DIR = I, VEC = [5:0]
PORT S_AXI_HP3_AWID = ps7_axi_interconnect_0_S_AXI_HP3_AWID, DIR = I, VEC = [5:0]
PORT S_AXI_HP3_WID = ps7_axi_interconnect_0_S_AXI_HP3_WID, DIR = I, VEC = [5:0]
PORT S_AXI_HP3_WDATA = ps7_axi_interconnect_0_S_AXI_HP3_WDATA, DIR = I, VEC = [63:0]
PORT S_AXI_HP3_WSTRB = ps7_axi_interconnect_0_S_AXI_HP3_WSTRB, DIR = I, VEC = [7:0]
PORT S_AXI_HP3_RLAST = ps7_axi_interconnect_0_S_AXI_HP3_RLAST, DIR = O
PORT S_AXI_HP3_AWREADY = ps7_axi_interconnect_0_S_AXI_HP3_AWREADY, DIR = O
# TAG_NO__END
# TAG_NO__START PCW::MPD::PS7::C_USE_S_AXI_ACP
PORT S_AXI_ACP_BVALID = ps7_axi_interconnect_0_S_AXI_ACP_BVALID, DIR = O
PORT S_AXI_ACP_BRESP = ps7_axi_interconnect_0_S_AXI_ACP_BRESP, DIR = O, VEC = [1:0]
PORT S_AXI_ACP_AWREADY = ps7_axi_interconnect_0_S_AXI_ACP_AWREADY, DIR = O
PORT S_AXI_ACP_RVALID = ps7_axi_interconnect_0_S_AXI_ACP_RVALID, DIR = O
PORT S_AXI_ACP_WLAST = ps7_axi_interconnect_0_S_AXI_ACP_WLAST, DIR = I
PORT S_AXI_ACP_RRESP = ps7_axi_interconnect_0_S_AXI_ACP_RRESP, DIR = O, VEC = [1:0]
PORT S_AXI_ACP_BID = ps7_axi_interconnect_0_S_AXI_ACP_BID, DIR = O, VEC = [2:0]
PORT S_AXI_ACP_AWVALID = ps7_axi_interconnect_0_S_AXI_ACP_AWVALID, DIR = I
PORT S_AXI_ACP_WREADY = ps7_axi_interconnect_0_S_AXI_ACP_WREADY, DIR = O
PORT S_AXI_ACP_RREADY = ps7_axi_interconnect_0_S_AXI_ACP_RREADY, DIR = I
PORT S_AXI_ACP_RID = ps7_axi_interconnect_0_S_AXI_ACP_RID, DIR = O, VEC = [2:0]
PORT S_AXI_ACP_RDATA = ps7_axi_interconnect_0_S_AXI_ACP_RDATA, DIR = O, VEC = [63:0]
PORT S_AXI_ACP_ACLK = ps7_axi_interconnect_0_S_AXI_ACP_ACLK, DIR = I, SIGIS = CLK
PORT S_AXI_ACP_ARVALID = ps7_axi_interconnect_0_S_AXI_ACP_ARVALID, DIR = I
PORT S_AXI_ACP_BREADY = ps7_axi_interconnect_0_S_AXI_ACP_BREADY, DIR = I
PORT S_AXI_ACP_WVALID = ps7_axi_interconnect_0_S_AXI_ACP_WVALID, DIR = I
PORT S_AXI_ACP_AWQOS = ps7_axi_interconnect_0_S_AXI_ACP_AWQOS, DIR = I, VEC = [3:0]
PORT S_AXI_ACP_ARID = ps7_axi_interconnect_0_S_AXI_ACP_ARID, DIR = I, VEC = [2:0]
PORT S_AXI_ACP_ARLEN = ps7_axi_interconnect_0_S_AXI_ACP_ARLEN, DIR = I, VEC = [3:0]
PORT S_AXI_ACP_ARPROT = ps7_axi_interconnect_0_S_AXI_ACP_ARPROT, DIR = I, VEC = [2:0]
PORT S_AXI_ACP_AWID = ps7_axi_interconnect_0_S_AXI_ACP_AWID, DIR = I, VEC = [2:0]
PORT S_AXI_ACP_AWPROT = ps7_axi_interconnect_0_S_AXI_ACP_AWPROT, DIR = I, VEC = [2:0]
PORT S_AXI_ACP_WID = ps7_axi_interconnect_0_S_AXI_ACP_WID, DIR = I, VEC = [2:0]
PORT S_AXI_ACP_ARADDR = ps7_axi_interconnect_0_S_AXI_ACP_ARADDR, DIR = I, VEC = [31:0]
PORT S_AXI_ACP_AWADDR = ps7_axi_interconnect_0_S_AXI_ACP_AWADDR, DIR = I, VEC = [31:0]
PORT S_AXI_ACP_ARCACHE = ps7_axi_interconnect_0_S_AXI_ACP_ARCACHE, DIR = I, VEC = [3:0]
PORT S_AXI_ACP_ARQOS = ps7_axi_interconnect_0_S_AXI_ACP_ARQOS, DIR = I, VEC = [3:0]
PORT S_AXI_ACP_ARBURST = ps7_axi_interconnect_0_S_AXI_ACP_ARBURST, DIR = I, VEC = [1:0]
PORT S_AXI_ACP_AWCACHE = ps7_axi_interconnect_0_S_AXI_ACP_AWCACHE, DIR = I, VEC = [3:0]
PORT S_AXI_ACP_AWBURST = ps7_axi_interconnect_0_S_AXI_ACP_AWBURST, DIR = I, VEC = [1:0]
PORT S_AXI_ACP_AWLEN = ps7_axi_interconnect_0_S_AXI_ACP_AWLEN, DIR = I, VEC = [3:0]
PORT S_AXI_ACP_ARSIZE = ps7_axi_interconnect_0_S_AXI_ACP_ARSIZE, DIR = I, VEC = [2:0]
PORT S_AXI_ACP_ARLOCK = ps7_axi_interconnect_0_S_AXI_ACP_ARLOCK, DIR = I, VEC = [1:0]
PORT S_AXI_ACP_AWLOCK = ps7_axi_interconnect_0_S_AXI_ACP_AWLOCK, DIR = I, VEC = [1:0]
PORT S_AXI_ACP_AWSIZE = ps7_axi_interconnect_0_S_AXI_ACP_AWSIZE, DIR = I, VEC = [2:0]
PORT S_AXI_ACP_ARUSER = ps7_axi_interconnect_0_S_AXI_ACP_ARUSER, DIR = I, VEC = [4:0]
PORT S_AXI_ACP_AWUSER = ps7_axi_interconnect_0_S_AXI_ACP_AWUSER, DIR = I, VEC = [4:0]
PORT S_AXI_ACP_WDATA = ps7_axi_interconnect_0_S_AXI_ACP_WDATA, DIR = I, VEC = [63:0]
PORT S_AXI_ACP_WSTRB = ps7_axi_interconnect_0_S_AXI_ACP_WSTRB, DIR = I, VEC = [7:0]
PORT S_AXI_ACP_RLAST = ps7_axi_interconnect_0_S_AXI_ACP_RLAST, DIR = O
PORT S_AXI_ACP_ARREADY = ps7_axi_interconnect_0_S_AXI_ACP_ARREADY, DIR = O
# RESTET Pins
PORT M_AXI_GP0_ARESETN = ps7_axi_interconnect_0_M_AXI_GP0_ARESETN, DIR = O, SIGIS = RST
PORT S_AXI_HP0_WRISSUECAP1_EN = ps7_axi_interconnect_0_S_AXI_HP0_WRISSUECAP1_EN, DIR = I
PORT S_AXI_GP1_ARESETN = ps7_axi_interconnect_0_S_AXI_GP1_ARESETN, DIR = O, SIGIS = RST
PORT S_AXI_GP0_ARESETN = ps7_axi_interconnect_0_S_AXI_GP0_ARESETN, DIR = O, SIGIS = RST
PORT S_AXI_ACP_ARESETN = ps7_axi_interconnect_0_S_AXI_ACP_ARESETN, DIR = O, SIGIS = RST
PORT S_AXI_HP0_ARESETN = ps7_axi_interconnect_0_S_AXI_HP0_ARESETN, DIR = O, SIGIS = RST
PORT S_AXI_HP0_RCOUNT = ps7_axi_interconnect_0_S_AXI_HP0_RCOUNT, DIR = O, VEC = [7:0]
PORT S_AXI_HP0_WCOUNT = ps7_axi_interconnect_0_S_AXI_HP0_WCOUNT, DIR = O, VEC = [7:0]
PORT S_AXI_HP0_RACOUNT = ps7_axi_interconnect_0_S_AXI_HP0_RACOUNT, DIR = O, VEC = [2:0]
PORT S_AXI_HP0_WACOUNT = ps7_axi_interconnect_0_S_AXI_HP0_WACOUNT, DIR = O, VEC = [5:0]
PORT S_AXI_HP0_RDISSUECAP1_EN = ps7_axi_interconnect_0_S_AXI_HP0_RDISSUECAP1_EN, DIR = I
PORT S_AXI_HP1_ARESETN = ps7_axi_interconnect_0_S_AXI_HP1_ARESETN, DIR = O, SIGIS = RST
PORT S_AXI_HP1_WRISSUECAP1_EN = ps7_axi_interconnect_0_S_AXI_HP1_WRISSUECAP1_EN, DIR = I
PORT S_AXI_HP1_RCOUNT = ps7_axi_interconnect_0_S_AXI_HP1_RCOUNT, DIR = O, VEC = [7:0]
PORT S_AXI_HP1_WCOUNT = ps7_axi_interconnect_0_S_AXI_HP1_WCOUNT, DIR = O, VEC = [7:0]
PORT S_AXI_HP1_RACOUNT = ps7_axi_interconnect_0_S_AXI_HP1_RACOUNT, DIR = O, VEC = [2:0]
PORT S_AXI_HP1_WACOUNT = ps7_axi_interconnect_0_S_AXI_HP1_WACOUNT, DIR = O, VEC = [5:0]
PORT S_AXI_HP1_RDISSUECAP1_EN = ps7_axi_interconnect_0_S_AXI_HP1_RDISSUECAP1_EN, DIR = I
PORT S_AXI_HP2_ARESETN = ps7_axi_interconnect_0_S_AXI_HP2_ARESETN, DIR = O, SIGIS = RST
PORT S_AXI_HP2_WRISSUECAP1_EN = ps7_axi_interconnect_0_S_AXI_HP2_WRISSUECAP1_EN, DIR = I
PORT S_AXI_HP2_RCOUNT = ps7_axi_interconnect_0_S_AXI_HP2_RCOUNT, DIR = O, VEC = [7:0]
PORT S_AXI_HP2_WCOUNT = ps7_axi_interconnect_0_S_AXI_HP2_WCOUNT, DIR = O, VEC = [7:0]
PORT S_AXI_HP2_RACOUNT = ps7_axi_interconnect_0_S_AXI_HP2_RACOUNT, DIR = O, VEC = [2:0]
PORT S_AXI_HP2_WACOUNT = ps7_axi_interconnect_0_S_AXI_HP2_WACOUNT, DIR = O, VEC = [5:0]
PORT S_AXI_HP2_RDISSUECAP1_EN = ps7_axi_interconnect_0_S_AXI_HP2_RDISSUECAP1_EN, DIR = I
PORT S_AXI_HP3_ARESETN = ps7_axi_interconnect_0_S_AXI_HP3_ARESETN, DIR = O, SIGIS = RST
PORT S_AXI_HP3_WRISSUECAP1_EN = ps7_axi_interconnect_0_S_AXI_HP3_WRISSUECAP1_EN, DIR = I
PORT S_AXI_HP3_RCOUNT = ps7_axi_interconnect_0_S_AXI_HP3_RCOUNT, DIR = O, VEC = [7:0]
PORT S_AXI_HP3_WCOUNT = ps7_axi_interconnect_0_S_AXI_HP3_WCOUNT, DIR = O, VEC = [7:0]
PORT S_AXI_HP3_RACOUNT = ps7_axi_interconnect_0_S_AXI_HP3_RACOUNT, DIR = O, VEC = [2:0]
PORT S_AXI_HP3_WACOUNT = ps7_axi_interconnect_0_S_AXI_HP3_WACOUNT, DIR = O, VEC = [5:0]
PORT S_AXI_HP3_RDISSUECAP1_EN = ps7_axi_interconnect_0_S_AXI_HP3_RDISSUECAP1_EN, DIR = I
PORT M_AXI_GP1_ARESETN = ps7_axi_interconnect_0_M_AXI_GP1_ARESETN, DIR = O, SIGIS = RST
BEGIN ps7_axi_interconnect
PARAMETER INSTANCE = ps7_axi_interconnect_0
PARAMETER HW_VER = 1.00.a
#BUS_INTERFACE M_AXI_GP0 = ps7_axi_interconnect_0
PORT M_AXI_GP0_BREADY = ps7_axi_interconnect_0_M_AXI_GP0_BREADY
PORT M_AXI_GP0_ARVALID = ps7_axi_interconnect_0_M_AXI_GP0_ARVALID
PORT M_AXI_GP0_AWVALID = ps7_axi_interconnect_0_M_AXI_GP0_AWVALID
PORT M_AXI_GP0_WVALID = ps7_axi_interconnect_0_M_AXI_GP0_WVALID
PORT M_AXI_GP0_AWID = ps7_axi_interconnect_0_M_AXI_GP0_AWID
PORT M_AXI_GP0_RREADY = ps7_axi_interconnect_0_M_AXI_GP0_RREADY
PORT M_AXI_GP0_ARSIZE = ps7_axi_interconnect_0_M_AXI_GP0_ARSIZE
PORT M_AXI_GP0_AWREADY = ps7_axi_interconnect_0_M_AXI_GP0_AWREADY
PORT M_AXI_GP0_ARID = ps7_axi_interconnect_0_M_AXI_GP0_ARID
PORT M_AXI_GP0_WID = ps7_axi_interconnect_0_M_AXI_GP0_WID
PORT M_AXI_GP0_AWBURST = ps7_axi_interconnect_0_M_AXI_GP0_AWBURST
PORT M_AXI_GP0_ARBURST = ps7_axi_interconnect_0_M_AXI_GP0_ARBURST
PORT M_AXI_GP0_ARLOCK = ps7_axi_interconnect_0_M_AXI_GP0_ARLOCK
PORT M_AXI_GP0_AWLOCK = ps7_axi_interconnect_0_M_AXI_GP0_AWLOCK
PORT M_AXI_GP0_AWSIZE = ps7_axi_interconnect_0_M_AXI_GP0_AWSIZE
PORT M_AXI_GP0_ARPROT = ps7_axi_interconnect_0_M_AXI_GP0_ARPROT
PORT M_AXI_GP0_AWPROT = ps7_axi_interconnect_0_M_AXI_GP0_AWPROT
PORT M_AXI_GP0_ARADDR = ps7_axi_interconnect_0_M_AXI_GP0_ARADDR
PORT M_AXI_GP0_BID = ps7_axi_interconnect_0_M_AXI_GP0_BID
PORT M_AXI_GP0_AWADDR = ps7_axi_interconnect_0_M_AXI_GP0_AWADDR
PORT M_AXI_GP0_WDATA = ps7_axi_interconnect_0_M_AXI_GP0_WDATA
PORT M_AXI_GP0_ARCACHE = ps7_axi_interconnect_0_M_AXI_GP0_ARCACHE
PORT M_AXI_GP0_AWQOS = ps7_axi_interconnect_0_M_AXI_GP0_AWQOS
PORT M_AXI_GP0_ARLEN = ps7_axi_interconnect_0_M_AXI_GP0_ARLEN
PORT M_AXI_GP0_ARQOS = ps7_axi_interconnect_0_M_AXI_GP0_ARQOS
PORT M_AXI_GP0_AWCACHE = ps7_axi_interconnect_0_M_AXI_GP0_AWCACHE
PORT M_AXI_GP0_WREADY = ps7_axi_interconnect_0_M_AXI_GP0_WREADY
PORT M_AXI_GP0_AWLEN = ps7_axi_interconnect_0_M_AXI_GP0_AWLEN
PORT M_AXI_GP0_WSTRB = ps7_axi_interconnect_0_M_AXI_GP0_WSTRB
PORT M_AXI_GP0_ACLK = ps7_axi_interconnect_0_M_AXI_GP0_ACLK
PORT M_AXI_GP0_ARREADY = ps7_axi_interconnect_0_M_AXI_GP0_ARREADY
PORT M_AXI_GP0_BVALID = ps7_axi_interconnect_0_M_AXI_GP0_BVALID
PORT M_AXI_GP0_RLAST = ps7_axi_interconnect_0_M_AXI_GP0_RLAST
PORT M_AXI_GP0_RVALID = ps7_axi_interconnect_0_M_AXI_GP0_RVALID
PORT M_AXI_GP0_RID = ps7_axi_interconnect_0_M_AXI_GP0_RID
PORT M_AXI_GP0_BRESP = ps7_axi_interconnect_0_M_AXI_GP0_BRESP
PORT M_AXI_GP0_RRESP = ps7_axi_interconnect_0_M_AXI_GP0_RRESP
PORT M_AXI_GP0_RDATA = ps7_axi_interconnect_0_M_AXI_GP0_RDATA
PORT M_AXI_GP0_WLAST = ps7_axi_interconnect_0_M_AXI_GP0_WLAST
PORT M_AXI_GP1_BREADY = ps7_axi_interconnect_0_M_AXI_GP1_BREADY
PORT M_AXI_GP1_ARQOS = ps7_axi_interconnect_0_M_AXI_GP1_ARQOS
PORT M_AXI_GP1_ARID = ps7_axi_interconnect_0_M_AXI_GP1_ARID
PORT M_AXI_GP1_WID = ps7_axi_interconnect_0_M_AXI_GP1_WID
PORT M_AXI_GP1_AWBURST = ps7_axi_interconnect_0_M_AXI_GP1_AWBURST
PORT M_AXI_GP1_ARBURST = ps7_axi_interconnect_0_M_AXI_GP1_ARBURST
PORT M_AXI_GP1_ARLOCK = ps7_axi_interconnect_0_M_AXI_GP1_ARLOCK
PORT M_AXI_GP1_AWLOCK = ps7_axi_interconnect_0_M_AXI_GP1_AWLOCK
PORT M_AXI_GP1_AWSIZE = ps7_axi_interconnect_0_M_AXI_GP1_AWSIZE
PORT M_AXI_GP1_ARPROT = ps7_axi_interconnect_0_M_AXI_GP1_ARPROT
PORT M_AXI_GP1_AWPROT = ps7_axi_interconnect_0_M_AXI_GP1_AWPROT
PORT M_AXI_GP1_ARADDR = ps7_axi_interconnect_0_M_AXI_GP1_ARADDR
PORT M_AXI_GP1_BID = ps7_axi_interconnect_0_M_AXI_GP1_BID
PORT M_AXI_GP1_AWADDR = ps7_axi_interconnect_0_M_AXI_GP1_AWADDR
PORT M_AXI_GP1_WDATA = ps7_axi_interconnect_0_M_AXI_GP1_WDATA
PORT M_AXI_GP1_ARCACHE = ps7_axi_interconnect_0_M_AXI_GP1_ARCACHE
PORT M_AXI_GP1_ARLEN = ps7_axi_interconnect_0_M_AXI_GP1_ARLEN
PORT M_AXI_GP1_RLAST = ps7_axi_interconnect_0_M_AXI_GP1_RLAST
PORT M_AXI_GP1_AWQOS = ps7_axi_interconnect_0_M_AXI_GP1_AWQOS
PORT M_AXI_GP1_AWREADY = ps7_axi_interconnect_0_M_AXI_GP1_AWREADY
PORT M_AXI_GP1_AWCACHE = ps7_axi_interconnect_0_M_AXI_GP1_AWCACHE
PORT M_AXI_GP1_AWLEN = ps7_axi_interconnect_0_M_AXI_GP1_AWLEN
PORT M_AXI_GP1_WSTRB = ps7_axi_interconnect_0_M_AXI_GP1_WSTRB
PORT M_AXI_GP1_WREADY = ps7_axi_interconnect_0_M_AXI_GP1_WREADY
PORT M_AXI_GP1_ACLK = ps7_axi_interconnect_0_M_AXI_GP1_ACLK
PORT M_AXI_GP1_ARREADY = ps7_axi_interconnect_0_M_AXI_GP1_ARREADY
PORT M_AXI_GP1_BVALID = ps7_axi_interconnect_0_M_AXI_GP1_BVALID
PORT M_AXI_GP1_RVALID = ps7_axi_interconnect_0_M_AXI_GP1_RVALID
PORT M_AXI_GP1_RDATA = ps7_axi_interconnect_0_M_AXI_GP1_RDATA
PORT M_AXI_GP1_RID = ps7_axi_interconnect_0_M_AXI_GP1_RID
PORT M_AXI_GP1_BRESP = ps7_axi_interconnect_0_M_AXI_GP1_BRESP
PORT M_AXI_GP1_RRESP = ps7_axi_interconnect_0_M_AXI_GP1_RRESP
PORT M_AXI_GP1_RREADY = ps7_axi_interconnect_0_M_AXI_GP1_RREADY
PORT M_AXI_GP1_WVALID = ps7_axi_interconnect_0_M_AXI_GP1_WVALID
PORT M_AXI_GP1_ARVALID = ps7_axi_interconnect_0_M_AXI_GP1_ARVALID
PORT M_AXI_GP1_AWID = ps7_axi_interconnect_0_M_AXI_GP1_AWID
PORT M_AXI_GP1_WLAST = ps7_axi_interconnect_0_M_AXI_GP1_WLAST
PORT M_AXI_GP1_ARSIZE = ps7_axi_interconnect_0_M_AXI_GP1_ARSIZE
PORT M_AXI_GP1_AWVALID = ps7_axi_interconnect_0_M_AXI_GP1_AWVALID
PORT S_AXI_GP1_WREADY = ps7_axi_interconnect_0_S_AXI_GP1_WREADY
PORT S_AXI_HP0_RVALID = ps7_axi_interconnect_0_S_AXI_HP0_RVALID
PORT S_AXI_HP1_WREADY = ps7_axi_interconnect_0_S_AXI_HP1_WREADY
PORT S_AXI_HP2_WREADY = ps7_axi_interconnect_0_S_AXI_HP2_WREADY
PORT S_AXI_HP3_WREADY = ps7_axi_interconnect_0_S_AXI_HP3_WREADY
PORT S_AXI_ACP_WREADY = ps7_axi_interconnect_0_S_AXI_ACP_WREADY
PORT S_AXI_HP0_AWID = ps7_axi_interconnect_0_S_AXI_HP0_AWID
PORT S_AXI_HP0_WID = ps7_axi_interconnect_0_S_AXI_HP0_WID
PORT S_AXI_HP0_WDATA = ps7_axi_interconnect_0_S_AXI_HP0_WDATA
PORT S_AXI_HP0_WSTRB = ps7_axi_interconnect_0_S_AXI_HP0_WSTRB
PORT S_AXI_HP2_RLAST = ps7_axi_interconnect_0_S_AXI_HP2_RLAST
PORT S_AXI_HP2_AWREADY = ps7_axi_interconnect_0_S_AXI_HP2_AWREADY
PORT S_AXI_HP1_RVALID = ps7_axi_interconnect_0_S_AXI_HP1_RVALID
PORT S_AXI_HP1_RRESP = ps7_axi_interconnect_0_S_AXI_HP1_RRESP
PORT S_AXI_HP1_AWVALID = ps7_axi_interconnect_0_S_AXI_HP1_AWVALID
PORT S_AXI_HP1_RREADY = ps7_axi_interconnect_0_S_AXI_HP1_RREADY
PORT S_AXI_HP1_BID = ps7_axi_interconnect_0_S_AXI_HP1_BID
PORT S_AXI_HP1_WLAST = ps7_axi_interconnect_0_S_AXI_HP1_WLAST
PORT S_AXI_HP1_RID = ps7_axi_interconnect_0_S_AXI_HP1_RID
PORT S_AXI_HP1_RDATA = ps7_axi_interconnect_0_S_AXI_HP1_RDATA
PORT S_AXI_HP1_ACLK = ps7_axi_interconnect_0_S_AXI_HP1_ACLK
PORT S_AXI_HP1_ARVALID = ps7_axi_interconnect_0_S_AXI_HP1_ARVALID
PORT S_AXI_HP1_BREADY = ps7_axi_interconnect_0_S_AXI_HP1_BREADY
PORT S_AXI_HP1_WVALID = ps7_axi_interconnect_0_S_AXI_HP1_WVALID
PORT S_AXI_HP1_ARSIZE = ps7_axi_interconnect_0_S_AXI_HP1_ARSIZE
PORT S_AXI_HP1_ARBURST = ps7_axi_interconnect_0_S_AXI_HP1_ARBURST
PORT S_AXI_HP2_ARREADY = ps7_axi_interconnect_0_S_AXI_HP2_ARREADY
PORT S_AXI_HP1_ARLOCK = ps7_axi_interconnect_0_S_AXI_HP1_ARLOCK
PORT S_AXI_HP1_AWBURST = ps7_axi_interconnect_0_S_AXI_HP1_AWBURST
PORT S_AXI_HP1_AWLOCK = ps7_axi_interconnect_0_S_AXI_HP1_AWLOCK
PORT S_AXI_HP1_AWSIZE = ps7_axi_interconnect_0_S_AXI_HP1_AWSIZE
PORT S_AXI_HP1_ARPROT = ps7_axi_interconnect_0_S_AXI_HP1_ARPROT
PORT S_AXI_HP1_AWPROT = ps7_axi_interconnect_0_S_AXI_HP1_AWPROT
PORT S_AXI_HP1_ARADDR = ps7_axi_interconnect_0_S_AXI_HP1_ARADDR
PORT S_AXI_HP1_AWADDR = ps7_axi_interconnect_0_S_AXI_HP1_AWADDR
PORT S_AXI_HP1_ARCACHE = ps7_axi_interconnect_0_S_AXI_HP1_ARCACHE
PORT S_AXI_HP1_ARLEN = ps7_axi_interconnect_0_S_AXI_HP1_ARLEN
PORT S_AXI_HP1_ARQOS = ps7_axi_interconnect_0_S_AXI_HP1_ARQOS
PORT S_AXI_ACP_RREADY = ps7_axi_interconnect_0_S_AXI_ACP_RREADY
PORT S_AXI_ACP_RID = ps7_axi_interconnect_0_S_AXI_ACP_RID
PORT S_AXI_ACP_RDATA = ps7_axi_interconnect_0_S_AXI_ACP_RDATA
PORT S_AXI_ACP_ACLK = ps7_axi_interconnect_0_S_AXI_ACP_ACLK
PORT S_AXI_ACP_ARVALID = ps7_axi_interconnect_0_S_AXI_ACP_ARVALID
PORT S_AXI_ACP_BREADY = ps7_axi_interconnect_0_S_AXI_ACP_BREADY
PORT S_AXI_ACP_WVALID = ps7_axi_interconnect_0_S_AXI_ACP_WVALID
PORT S_AXI_ACP_AWQOS = ps7_axi_interconnect_0_S_AXI_ACP_AWQOS
PORT S_AXI_ACP_ARID = ps7_axi_interconnect_0_S_AXI_ACP_ARID
PORT S_AXI_ACP_ARLEN = ps7_axi_interconnect_0_S_AXI_ACP_ARLEN
PORT S_AXI_ACP_ARPROT = ps7_axi_interconnect_0_S_AXI_ACP_ARPROT
PORT S_AXI_ACP_AWID = ps7_axi_interconnect_0_S_AXI_ACP_AWID
PORT S_AXI_ACP_AWPROT = ps7_axi_interconnect_0_S_AXI_ACP_AWPROT
PORT S_AXI_ACP_WID = ps7_axi_interconnect_0_S_AXI_ACP_WID
PORT S_AXI_ACP_ARADDR = ps7_axi_interconnect_0_S_AXI_ACP_ARADDR
PORT S_AXI_ACP_AWADDR = ps7_axi_interconnect_0_S_AXI_ACP_AWADDR
PORT S_AXI_ACP_ARCACHE = ps7_axi_interconnect_0_S_AXI_ACP_ARCACHE
PORT S_AXI_ACP_ARQOS = ps7_axi_interconnect_0_S_AXI_ACP_ARQOS
PORT S_AXI_ACP_ARBURST = ps7_axi_interconnect_0_S_AXI_ACP_ARBURST
PORT S_AXI_ACP_AWCACHE = ps7_axi_interconnect_0_S_AXI_ACP_AWCACHE
PORT S_AXI_ACP_AWBURST = ps7_axi_interconnect_0_S_AXI_ACP_AWBURST
PORT S_AXI_ACP_AWLEN = ps7_axi_interconnect_0_S_AXI_ACP_AWLEN
PORT S_AXI_ACP_ARSIZE = ps7_axi_interconnect_0_S_AXI_ACP_ARSIZE
PORT S_AXI_ACP_ARLOCK = ps7_axi_interconnect_0_S_AXI_ACP_ARLOCK
PORT S_AXI_ACP_AWLOCK = ps7_axi_interconnect_0_S_AXI_ACP_AWLOCK
PORT S_AXI_ACP_AWSIZE = ps7_axi_interconnect_0_S_AXI_ACP_AWSIZE
PORT S_AXI_ACP_ARUSER = ps7_axi_interconnect_0_S_AXI_ACP_ARUSER
PORT S_AXI_ACP_AWUSER = ps7_axi_interconnect_0_S_AXI_ACP_AWUSER
PORT S_AXI_ACP_WDATA = ps7_axi_interconnect_0_S_AXI_ACP_WDATA
PORT S_AXI_ACP_WSTRB = ps7_axi_interconnect_0_S_AXI_ACP_WSTRB
PORT S_AXI_GP0_RLAST = ps7_axi_interconnect_0_S_AXI_GP0_RLAST
PORT S_AXI_GP0_BVALID = ps7_axi_interconnect_0_S_AXI_GP0_BVALID
PORT S_AXI_GP1_RID = ps7_axi_interconnect_0_S_AXI_GP1_RID
PORT S_AXI_GP1_ACLK = ps7_axi_interconnect_0_S_AXI_GP1_ACLK
PORT S_AXI_GP1_ARVALID = ps7_axi_interconnect_0_S_AXI_GP1_ARVALID
PORT S_AXI_GP1_BREADY = ps7_axi_interconnect_0_S_AXI_GP1_BREADY
PORT S_AXI_GP1_WVALID = ps7_axi_interconnect_0_S_AXI_GP1_WVALID
PORT S_AXI_GP1_ARSIZE = ps7_axi_interconnect_0_S_AXI_GP1_ARSIZE
PORT S_AXI_GP1_ARBURST = ps7_axi_interconnect_0_S_AXI_GP1_ARBURST
PORT S_AXI_HP0_AWREADY = ps7_axi_interconnect_0_S_AXI_HP0_AWREADY
PORT S_AXI_GP1_ARLOCK = ps7_axi_interconnect_0_S_AXI_GP1_ARLOCK
PORT S_AXI_GP1_AWBURST = ps7_axi_interconnect_0_S_AXI_GP1_AWBURST
PORT S_AXI_GP1_AWLOCK = ps7_axi_interconnect_0_S_AXI_GP1_AWLOCK
PORT S_AXI_GP1_AWSIZE = ps7_axi_interconnect_0_S_AXI_GP1_AWSIZE
PORT S_AXI_GP1_ARPROT = ps7_axi_interconnect_0_S_AXI_GP1_ARPROT
PORT S_AXI_GP1_AWPROT = ps7_axi_interconnect_0_S_AXI_GP1_AWPROT
PORT S_AXI_GP1_ARADDR = ps7_axi_interconnect_0_S_AXI_GP1_ARADDR
PORT S_AXI_GP1_AWADDR = ps7_axi_interconnect_0_S_AXI_GP1_AWADDR
PORT S_AXI_GP1_WDATA = ps7_axi_interconnect_0_S_AXI_GP1_WDATA
PORT S_AXI_GP1_ARCACHE = ps7_axi_interconnect_0_S_AXI_GP1_ARCACHE
PORT S_AXI_GP1_ARQOS = ps7_axi_interconnect_0_S_AXI_GP1_ARQOS
PORT S_AXI_GP1_ARLEN = ps7_axi_interconnect_0_S_AXI_GP1_ARLEN
PORT S_AXI_GP1_AWQOS = ps7_axi_interconnect_0_S_AXI_GP1_AWQOS
PORT S_AXI_HP0_ARREADY = ps7_axi_interconnect_0_S_AXI_HP0_ARREADY
PORT S_AXI_GP1_AWCACHE = ps7_axi_interconnect_0_S_AXI_GP1_AWCACHE
PORT S_AXI_GP1_AWLEN = ps7_axi_interconnect_0_S_AXI_GP1_AWLEN
PORT S_AXI_GP1_WSTRB = ps7_axi_interconnect_0_S_AXI_GP1_WSTRB
PORT S_AXI_GP1_ARID = ps7_axi_interconnect_0_S_AXI_GP1_ARID
PORT S_AXI_GP1_AWID = ps7_axi_interconnect_0_S_AXI_GP1_AWID
PORT S_AXI_GP1_WID = ps7_axi_interconnect_0_S_AXI_GP1_WID
PORT S_AXI_HP1_RLAST = ps7_axi_interconnect_0_S_AXI_HP1_RLAST
PORT S_AXI_HP1_AWREADY = ps7_axi_interconnect_0_S_AXI_HP1_AWREADY
PORT S_AXI_HP0_RLAST = ps7_axi_interconnect_0_S_AXI_HP0_RLAST
PORT S_AXI_HP0_BVALID = ps7_axi_interconnect_0_S_AXI_HP0_BVALID
PORT S_AXI_GP0_ARQOS = ps7_axi_interconnect_0_S_AXI_GP0_ARQOS
PORT S_AXI_GP0_AWBURST = ps7_axi_interconnect_0_S_AXI_GP0_AWBURST
PORT S_AXI_GP0_AWLOCK = ps7_axi_interconnect_0_S_AXI_GP0_AWLOCK
PORT S_AXI_GP0_AWSIZE = ps7_axi_interconnect_0_S_AXI_GP0_AWSIZE
PORT S_AXI_GP0_ARPROT = ps7_axi_interconnect_0_S_AXI_GP0_ARPROT
PORT S_AXI_GP0_AWPROT = ps7_axi_interconnect_0_S_AXI_GP0_AWPROT
PORT S_AXI_GP0_ARADDR = ps7_axi_interconnect_0_S_AXI_GP0_ARADDR
PORT S_AXI_GP0_AWADDR = ps7_axi_interconnect_0_S_AXI_GP0_AWADDR
PORT S_AXI_GP0_WDATA = ps7_axi_interconnect_0_S_AXI_GP0_WDATA
PORT S_AXI_GP0_ARCACHE = ps7_axi_interconnect_0_S_AXI_GP0_ARCACHE
PORT S_AXI_GP1_BVALID = ps7_axi_interconnect_0_S_AXI_GP1_BVALID
PORT S_AXI_GP0_ARLEN = ps7_axi_interconnect_0_S_AXI_GP0_ARLEN
PORT S_AXI_GP0_AWQOS = ps7_axi_interconnect_0_S_AXI_GP0_AWQOS
PORT S_AXI_GP1_ARREADY = ps7_axi_interconnect_0_S_AXI_GP1_ARREADY
PORT S_AXI_GP0_AWCACHE = ps7_axi_interconnect_0_S_AXI_GP0_AWCACHE
PORT S_AXI_GP0_WSTRB = ps7_axi_interconnect_0_S_AXI_GP0_WSTRB
PORT S_AXI_GP0_ARID = ps7_axi_interconnect_0_S_AXI_GP0_ARID
PORT S_AXI_GP0_AWID = ps7_axi_interconnect_0_S_AXI_GP0_AWID
PORT S_AXI_GP0_WID = ps7_axi_interconnect_0_S_AXI_GP0_WID
PORT S_AXI_HP0_BRESP = ps7_axi_interconnect_0_S_AXI_HP0_BRESP
PORT S_AXI_HP0_WREADY = ps7_axi_interconnect_0_S_AXI_HP0_WREADY
PORT S_AXI_GP1_RVALID = ps7_axi_interconnect_0_S_AXI_GP1_RVALID
PORT S_AXI_GP1_RRESP = ps7_axi_interconnect_0_S_AXI_GP1_RRESP
PORT S_AXI_GP1_AWVALID = ps7_axi_interconnect_0_S_AXI_GP1_AWVALID
PORT S_AXI_GP1_RREADY = ps7_axi_interconnect_0_S_AXI_GP1_RREADY
PORT S_AXI_GP1_RDATA = ps7_axi_interconnect_0_S_AXI_GP1_RDATA
PORT S_AXI_GP1_WLAST = ps7_axi_interconnect_0_S_AXI_GP1_WLAST
PORT S_AXI_GP1_BID = ps7_axi_interconnect_0_S_AXI_GP1_BID
PORT S_AXI_GP0_AWREADY = ps7_axi_interconnect_0_S_AXI_GP0_AWREADY
PORT S_AXI_GP0_BRESP = ps7_axi_interconnect_0_S_AXI_GP0_BRESP
PORT S_AXI_GP0_ARREADY = ps7_axi_interconnect_0_S_AXI_GP0_ARREADY
PORT S_AXI_GP1_BRESP = ps7_axi_interconnect_0_S_AXI_GP1_BRESP
PORT S_AXI_GP1_RLAST = ps7_axi_interconnect_0_S_AXI_GP1_RLAST
PORT S_AXI_GP0_RVALID = ps7_axi_interconnect_0_S_AXI_GP0_RVALID
PORT S_AXI_GP0_RRESP = ps7_axi_interconnect_0_S_AXI_GP0_RRESP
PORT S_AXI_GP0_AWVALID = ps7_axi_interconnect_0_S_AXI_GP0_AWVALID
PORT S_AXI_GP0_RREADY = ps7_axi_interconnect_0_S_AXI_GP0_RREADY
PORT S_AXI_GP0_RDATA = ps7_axi_interconnect_0_S_AXI_GP0_RDATA
PORT S_AXI_GP0_WLAST = ps7_axi_interconnect_0_S_AXI_GP0_WLAST
PORT S_AXI_GP0_BID = ps7_axi_interconnect_0_S_AXI_GP0_BID
PORT S_AXI_GP0_RID = ps7_axi_interconnect_0_S_AXI_GP0_RID
PORT S_AXI_GP0_ACLK = ps7_axi_interconnect_0_S_AXI_GP0_ACLK
PORT S_AXI_GP0_ARVALID = ps7_axi_interconnect_0_S_AXI_GP0_ARVALID
PORT S_AXI_GP0_BREADY = ps7_axi_interconnect_0_S_AXI_GP0_BREADY
PORT S_AXI_GP0_WVALID = ps7_axi_interconnect_0_S_AXI_GP0_WVALID
PORT S_AXI_GP0_ARSIZE = ps7_axi_interconnect_0_S_AXI_GP0_ARSIZE
PORT S_AXI_GP0_AWLEN = ps7_axi_interconnect_0_S_AXI_GP0_AWLEN
PORT S_AXI_GP1_AWREADY = ps7_axi_interconnect_0_S_AXI_GP1_AWREADY
PORT S_AXI_GP0_ARBURST = ps7_axi_interconnect_0_S_AXI_GP0_ARBURST
PORT S_AXI_GP0_ARLOCK = ps7_axi_interconnect_0_S_AXI_GP0_ARLOCK
PORT S_AXI_HP2_AWSIZE = ps7_axi_interconnect_0_S_AXI_HP2_AWSIZE
PORT S_AXI_HP2_ARPROT = ps7_axi_interconnect_0_S_AXI_HP2_ARPROT
PORT S_AXI_HP2_AWPROT = ps7_axi_interconnect_0_S_AXI_HP2_AWPROT
PORT S_AXI_HP2_ARADDR = ps7_axi_interconnect_0_S_AXI_HP2_ARADDR
PORT S_AXI_HP2_AWADDR = ps7_axi_interconnect_0_S_AXI_HP2_AWADDR
PORT S_AXI_HP2_ARCACHE = ps7_axi_interconnect_0_S_AXI_HP2_ARCACHE
PORT S_AXI_HP2_ARLEN = ps7_axi_interconnect_0_S_AXI_HP2_ARLEN
PORT S_AXI_HP2_ARQOS = ps7_axi_interconnect_0_S_AXI_HP2_ARQOS
PORT S_AXI_HP2_AWCACHE = ps7_axi_interconnect_0_S_AXI_HP2_AWCACHE
PORT S_AXI_HP3_BRESP = ps7_axi_interconnect_0_S_AXI_HP3_BRESP
PORT S_AXI_HP2_AWQOS = ps7_axi_interconnect_0_S_AXI_HP2_AWQOS
PORT S_AXI_HP2_AWLEN = ps7_axi_interconnect_0_S_AXI_HP2_AWLEN
PORT S_AXI_HP2_ARID = ps7_axi_interconnect_0_S_AXI_HP2_ARID
PORT S_AXI_HP3_BVALID = ps7_axi_interconnect_0_S_AXI_HP3_BVALID
PORT S_AXI_HP2_AWID = ps7_axi_interconnect_0_S_AXI_HP2_AWID
PORT S_AXI_HP2_WID = ps7_axi_interconnect_0_S_AXI_HP2_WID
PORT S_AXI_HP2_WDATA = ps7_axi_interconnect_0_S_AXI_HP2_WDATA
PORT S_AXI_HP2_WSTRB = ps7_axi_interconnect_0_S_AXI_HP2_WSTRB
PORT S_AXI_ACP_RLAST = ps7_axi_interconnect_0_S_AXI_ACP_RLAST
PORT S_AXI_ACP_ARREADY = ps7_axi_interconnect_0_S_AXI_ACP_ARREADY
PORT S_AXI_HP3_RVALID = ps7_axi_interconnect_0_S_AXI_HP3_RVALID
PORT S_AXI_HP3_RRESP = ps7_axi_interconnect_0_S_AXI_HP3_RRESP
PORT S_AXI_HP3_AWVALID = ps7_axi_interconnect_0_S_AXI_HP3_AWVALID
PORT S_AXI_HP3_RREADY = ps7_axi_interconnect_0_S_AXI_HP3_RREADY
PORT S_AXI_HP3_BID = ps7_axi_interconnect_0_S_AXI_HP3_BID
PORT S_AXI_HP3_WLAST = ps7_axi_interconnect_0_S_AXI_HP3_WLAST
PORT S_AXI_HP3_RID = ps7_axi_interconnect_0_S_AXI_HP3_RID
PORT S_AXI_HP3_RDATA = ps7_axi_interconnect_0_S_AXI_HP3_RDATA
PORT S_AXI_HP3_ACLK = ps7_axi_interconnect_0_S_AXI_HP3_ACLK
PORT S_AXI_HP3_ARVALID = ps7_axi_interconnect_0_S_AXI_HP3_ARVALID
PORT S_AXI_HP3_BREADY = ps7_axi_interconnect_0_S_AXI_HP3_BREADY
PORT S_AXI_HP3_WVALID = ps7_axi_interconnect_0_S_AXI_HP3_WVALID
PORT S_AXI_HP3_ARSIZE = ps7_axi_interconnect_0_S_AXI_HP3_ARSIZE
PORT S_AXI_HP3_ARBURST = ps7_axi_interconnect_0_S_AXI_HP3_ARBURST
PORT S_AXI_ACP_AWREADY = ps7_axi_interconnect_0_S_AXI_ACP_AWREADY
PORT S_AXI_HP3_ARLOCK = ps7_axi_interconnect_0_S_AXI_HP3_ARLOCK
PORT S_AXI_HP3_AWBURST = ps7_axi_interconnect_0_S_AXI_HP3_AWBURST
PORT S_AXI_HP3_AWLOCK = ps7_axi_interconnect_0_S_AXI_HP3_AWLOCK
PORT S_AXI_HP3_AWSIZE = ps7_axi_interconnect_0_S_AXI_HP3_AWSIZE
PORT S_AXI_HP3_ARPROT = ps7_axi_interconnect_0_S_AXI_HP3_ARPROT
PORT S_AXI_HP3_AWPROT = ps7_axi_interconnect_0_S_AXI_HP3_AWPROT
PORT S_AXI_HP3_ARADDR = ps7_axi_interconnect_0_S_AXI_HP3_ARADDR
PORT S_AXI_HP3_AWADDR = ps7_axi_interconnect_0_S_AXI_HP3_AWADDR
PORT S_AXI_HP3_ARCACHE = ps7_axi_interconnect_0_S_AXI_HP3_ARCACHE
PORT S_AXI_HP3_ARLEN = ps7_axi_interconnect_0_S_AXI_HP3_ARLEN
PORT S_AXI_HP3_ARQOS = ps7_axi_interconnect_0_S_AXI_HP3_ARQOS
PORT S_AXI_HP3_AWCACHE = ps7_axi_interconnect_0_S_AXI_HP3_AWCACHE
PORT S_AXI_ACP_BRESP = ps7_axi_interconnect_0_S_AXI_ACP_BRESP
PORT S_AXI_HP3_AWQOS = ps7_axi_interconnect_0_S_AXI_HP3_AWQOS
PORT S_AXI_HP3_AWLEN = ps7_axi_interconnect_0_S_AXI_HP3_AWLEN
PORT S_AXI_HP3_ARID = ps7_axi_interconnect_0_S_AXI_HP3_ARID
PORT S_AXI_ACP_BVALID = ps7_axi_interconnect_0_S_AXI_ACP_BVALID
PORT S_AXI_HP3_AWID = ps7_axi_interconnect_0_S_AXI_HP3_AWID
PORT S_AXI_HP3_WID = ps7_axi_interconnect_0_S_AXI_HP3_WID
PORT S_AXI_HP3_WDATA = ps7_axi_interconnect_0_S_AXI_HP3_WDATA
PORT S_AXI_HP3_WSTRB = ps7_axi_interconnect_0_S_AXI_HP3_WSTRB
PORT S_AXI_ACP_RVALID = ps7_axi_interconnect_0_S_AXI_ACP_RVALID
PORT S_AXI_ACP_WLAST = ps7_axi_interconnect_0_S_AXI_ACP_WLAST
PORT S_AXI_ACP_RRESP = ps7_axi_interconnect_0_S_AXI_ACP_RRESP
PORT S_AXI_ACP_BID = ps7_axi_interconnect_0_S_AXI_ACP_BID
PORT S_AXI_ACP_AWVALID = ps7_axi_interconnect_0_S_AXI_ACP_AWVALID
PORT S_AXI_HP1_AWCACHE = ps7_axi_interconnect_0_S_AXI_HP1_AWCACHE
PORT S_AXI_HP2_BRESP = ps7_axi_interconnect_0_S_AXI_HP2_BRESP
PORT S_AXI_HP1_AWQOS = ps7_axi_interconnect_0_S_AXI_HP1_AWQOS
PORT S_AXI_HP1_AWLEN = ps7_axi_interconnect_0_S_AXI_HP1_AWLEN
PORT S_AXI_HP1_ARID = ps7_axi_interconnect_0_S_AXI_HP1_ARID
PORT S_AXI_HP2_BVALID = ps7_axi_interconnect_0_S_AXI_HP2_BVALID
PORT S_AXI_HP1_AWID = ps7_axi_interconnect_0_S_AXI_HP1_AWID
PORT S_AXI_HP1_WID = ps7_axi_interconnect_0_S_AXI_HP1_WID
PORT S_AXI_HP1_WDATA = ps7_axi_interconnect_0_S_AXI_HP1_WDATA
PORT S_AXI_HP1_WSTRB = ps7_axi_interconnect_0_S_AXI_HP1_WSTRB
PORT S_AXI_HP3_RLAST = ps7_axi_interconnect_0_S_AXI_HP3_RLAST
PORT S_AXI_HP3_AWREADY = ps7_axi_interconnect_0_S_AXI_HP3_AWREADY
PORT S_AXI_HP2_RVALID = ps7_axi_interconnect_0_S_AXI_HP2_RVALID
PORT S_AXI_HP2_RRESP = ps7_axi_interconnect_0_S_AXI_HP2_RRESP
PORT S_AXI_HP2_AWVALID = ps7_axi_interconnect_0_S_AXI_HP2_AWVALID
PORT S_AXI_HP2_RREADY = ps7_axi_interconnect_0_S_AXI_HP2_RREADY
PORT S_AXI_HP2_BID = ps7_axi_interconnect_0_S_AXI_HP2_BID
PORT S_AXI_HP2_WLAST = ps7_axi_interconnect_0_S_AXI_HP2_WLAST
PORT S_AXI_HP2_RID = ps7_axi_interconnect_0_S_AXI_HP2_RID
PORT S_AXI_HP2_RDATA = ps7_axi_interconnect_0_S_AXI_HP2_RDATA
PORT S_AXI_HP2_ACLK = ps7_axi_interconnect_0_S_AXI_HP2_ACLK
PORT S_AXI_HP2_ARVALID = ps7_axi_interconnect_0_S_AXI_HP2_ARVALID
PORT S_AXI_HP2_BREADY = ps7_axi_interconnect_0_S_AXI_HP2_BREADY
PORT S_AXI_HP2_WVALID = ps7_axi_interconnect_0_S_AXI_HP2_WVALID
PORT S_AXI_HP2_ARSIZE = ps7_axi_interconnect_0_S_AXI_HP2_ARSIZE
PORT S_AXI_HP2_ARBURST = ps7_axi_interconnect_0_S_AXI_HP2_ARBURST
PORT S_AXI_HP3_ARREADY = ps7_axi_interconnect_0_S_AXI_HP3_ARREADY
PORT S_AXI_HP2_ARLOCK = ps7_axi_interconnect_0_S_AXI_HP2_ARLOCK
PORT S_AXI_HP2_AWBURST = ps7_axi_interconnect_0_S_AXI_HP2_AWBURST
PORT S_AXI_HP2_AWLOCK = ps7_axi_interconnect_0_S_AXI_HP2_AWLOCK
PORT S_AXI_HP0_RRESP = ps7_axi_interconnect_0_S_AXI_HP0_RRESP
PORT S_AXI_HP0_AWVALID = ps7_axi_interconnect_0_S_AXI_HP0_AWVALID
PORT S_AXI_HP0_RREADY = ps7_axi_interconnect_0_S_AXI_HP0_RREADY
PORT S_AXI_HP0_BID = ps7_axi_interconnect_0_S_AXI_HP0_BID
PORT S_AXI_HP0_WLAST = ps7_axi_interconnect_0_S_AXI_HP0_WLAST
PORT S_AXI_HP0_RID = ps7_axi_interconnect_0_S_AXI_HP0_RID
PORT S_AXI_HP0_RDATA = ps7_axi_interconnect_0_S_AXI_HP0_RDATA
PORT S_AXI_HP0_ACLK = ps7_axi_interconnect_0_S_AXI_HP0_ACLK
PORT S_AXI_HP0_ARVALID = ps7_axi_interconnect_0_S_AXI_HP0_ARVALID
PORT S_AXI_HP0_BREADY = ps7_axi_interconnect_0_S_AXI_HP0_BREADY
PORT S_AXI_HP0_WVALID = ps7_axi_interconnect_0_S_AXI_HP0_WVALID
PORT S_AXI_HP0_ARSIZE = ps7_axi_interconnect_0_S_AXI_HP0_ARSIZE
PORT S_AXI_HP0_ARBURST = ps7_axi_interconnect_0_S_AXI_HP0_ARBURST
PORT S_AXI_HP1_ARREADY = ps7_axi_interconnect_0_S_AXI_HP1_ARREADY
PORT S_AXI_HP0_ARLOCK = ps7_axi_interconnect_0_S_AXI_HP0_ARLOCK
PORT S_AXI_HP0_AWBURST = ps7_axi_interconnect_0_S_AXI_HP0_AWBURST
PORT S_AXI_HP0_AWLOCK = ps7_axi_interconnect_0_S_AXI_HP0_AWLOCK
PORT S_AXI_HP0_AWSIZE = ps7_axi_interconnect_0_S_AXI_HP0_AWSIZE
PORT S_AXI_HP0_ARPROT = ps7_axi_interconnect_0_S_AXI_HP0_ARPROT
PORT S_AXI_HP0_AWPROT = ps7_axi_interconnect_0_S_AXI_HP0_AWPROT
PORT S_AXI_HP0_ARADDR = ps7_axi_interconnect_0_S_AXI_HP0_ARADDR
PORT S_AXI_HP0_AWADDR = ps7_axi_interconnect_0_S_AXI_HP0_AWADDR
PORT S_AXI_HP0_ARCACHE = ps7_axi_interconnect_0_S_AXI_HP0_ARCACHE
PORT S_AXI_HP0_ARLEN = ps7_axi_interconnect_0_S_AXI_HP0_ARLEN
PORT S_AXI_HP0_ARQOS = ps7_axi_interconnect_0_S_AXI_HP0_ARQOS
PORT S_AXI_HP0_AWCACHE = ps7_axi_interconnect_0_S_AXI_HP0_AWCACHE
PORT S_AXI_HP1_BRESP = ps7_axi_interconnect_0_S_AXI_HP1_BRESP
PORT S_AXI_HP0_AWQOS = ps7_axi_interconnect_0_S_AXI_HP0_AWQOS
PORT S_AXI_HP0_AWLEN = ps7_axi_interconnect_0_S_AXI_HP0_AWLEN
PORT S_AXI_HP0_ARID = ps7_axi_interconnect_0_S_AXI_HP0_ARID
PORT S_AXI_HP1_BVALID = ps7_axi_interconnect_0_S_AXI_HP1_BVALID
PORT S_AXI_GP0_WREADY = ps7_axi_interconnect_0_S_AXI_GP0_WREADY
PORT M_AXI_GP0_ARESETN = ps7_axi_interconnect_0_M_AXI_GP0_ARESETN
PORT S_AXI_HP0_WRISSUECAP1_EN = ps7_axi_interconnect_0_S_AXI_HP0_WRISSUECAP1_EN
PORT S_AXI_GP1_ARESETN = ps7_axi_interconnect_0_S_AXI_GP1_ARESETN
PORT S_AXI_GP0_ARESETN = ps7_axi_interconnect_0_S_AXI_GP0_ARESETN
PORT S_AXI_ACP_ARESETN = ps7_axi_interconnect_0_S_AXI_ACP_ARESETN
PORT S_AXI_HP0_ARESETN = ps7_axi_interconnect_0_S_AXI_HP0_ARESETN
PORT S_AXI_HP0_RCOUNT = ps7_axi_interconnect_0_S_AXI_HP0_RCOUNT
PORT S_AXI_HP0_WCOUNT = ps7_axi_interconnect_0_S_AXI_HP0_WCOUNT
PORT S_AXI_HP0_RACOUNT = ps7_axi_interconnect_0_S_AXI_HP0_RACOUNT
PORT S_AXI_HP0_WACOUNT = ps7_axi_interconnect_0_S_AXI_HP0_WACOUNT
PORT S_AXI_HP0_RDISSUECAP1_EN = ps7_axi_interconnect_0_S_AXI_HP0_RDISSUECAP1_EN
PORT S_AXI_HP1_ARESETN = ps7_axi_interconnect_0_S_AXI_HP1_ARESETN
PORT S_AXI_HP1_WRISSUECAP1_EN = ps7_axi_interconnect_0_S_AXI_HP1_WRISSUECAP1_EN
PORT S_AXI_HP1_RCOUNT = ps7_axi_interconnect_0_S_AXI_HP1_RCOUNT
PORT S_AXI_HP1_WCOUNT = ps7_axi_interconnect_0_S_AXI_HP1_WCOUNT
PORT S_AXI_HP1_RACOUNT = ps7_axi_interconnect_0_S_AXI_HP1_RACOUNT
PORT S_AXI_HP1_WACOUNT = ps7_axi_interconnect_0_S_AXI_HP1_WACOUNT
PORT S_AXI_HP1_RDISSUECAP1_EN = ps7_axi_interconnect_0_S_AXI_HP1_RDISSUECAP1_EN
PORT S_AXI_HP2_ARESETN = ps7_axi_interconnect_0_S_AXI_HP2_ARESETN
PORT S_AXI_HP2_WRISSUECAP1_EN = ps7_axi_interconnect_0_S_AXI_HP2_WRISSUECAP1_EN
PORT S_AXI_HP2_RCOUNT = ps7_axi_interconnect_0_S_AXI_HP2_RCOUNT
PORT S_AXI_HP2_WCOUNT = ps7_axi_interconnect_0_S_AXI_HP2_WCOUNT
PORT S_AXI_HP2_RACOUNT = ps7_axi_interconnect_0_S_AXI_HP2_RACOUNT
PORT S_AXI_HP2_WACOUNT = ps7_axi_interconnect_0_S_AXI_HP2_WACOUNT
PORT S_AXI_HP2_RDISSUECAP1_EN = ps7_axi_interconnect_0_S_AXI_HP2_RDISSUECAP1_EN
PORT S_AXI_HP3_ARESETN = ps7_axi_interconnect_0_S_AXI_HP3_ARESETN
PORT S_AXI_HP3_WRISSUECAP1_EN = ps7_axi_interconnect_0_S_AXI_HP3_WRISSUECAP1_EN
PORT S_AXI_HP3_RCOUNT = ps7_axi_interconnect_0_S_AXI_HP3_RCOUNT
PORT S_AXI_HP3_WCOUNT = ps7_axi_interconnect_0_S_AXI_HP3_WCOUNT
PORT S_AXI_HP3_RACOUNT = ps7_axi_interconnect_0_S_AXI_HP3_RACOUNT
PORT S_AXI_HP3_WACOUNT = ps7_axi_interconnect_0_S_AXI_HP3_WACOUNT
PORT S_AXI_HP3_RDISSUECAP1_EN = ps7_axi_interconnect_0_S_AXI_HP3_RDISSUECAP1_EN
PORT M_AXI_GP1_ARESETN = ps7_axi_interconnect_0_M_AXI_GP1_ARESETN
END
BEGIN ps7_uart
PARAMETER INSTANCE = ps7_uart_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xE0000000
PARAMETER C_S_AXI_HIGHADDR = 0xE0000FFF
PARAMETER C_UART_CLK_FREQ_HZ = 50000000
PARAMETER C_HAS_MODEM = 0
END
BEGIN ps7_uart
PARAMETER INSTANCE = ps7_uart_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xE0001000
PARAMETER C_S_AXI_HIGHADDR = 0xE0001FFF
PARAMETER C_UART_CLK_FREQ_HZ = 50000000
PARAMETER C_HAS_MODEM = 0
END
BEGIN ps7_i2c
PARAMETER INSTANCE = ps7_i2c_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xE0004000
PARAMETER C_S_AXI_HIGHADDR = 0xE0004FFF
PARAMETER C_I2C_CLK_FREQ_HZ = 108333336
PARAMETER C_HAS_INTERRUPT = 0
PARAMETER C_I2C_RESET = -1
END
BEGIN ps7_afi
PARAMETER INSTANCE = ps7_afi_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xF8008000
PARAMETER C_S_AXI_HIGHADDR = 0xF8008FFF
END
BEGIN ps7_afi
PARAMETER INSTANCE = ps7_afi_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xF8009000
PARAMETER C_S_AXI_HIGHADDR = 0xF8009FFF
END
BEGIN ps7_afi
PARAMETER INSTANCE = ps7_afi_2
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xF800A000
PARAMETER C_S_AXI_HIGHADDR = 0xF800AFFF
END
BEGIN ps7_afi
PARAMETER INSTANCE = ps7_afi_3
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xF800B000
PARAMETER C_S_AXI_HIGHADDR = 0xF800BFFF
END
BEGIN ps7_sdio
PARAMETER INSTANCE = ps7_sd_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xE0100000
PARAMETER C_S_AXI_HIGHADDR = 0xE0100FFF
PARAMETER C_SDIO_CLK_FREQ_HZ = 50000000
PARAMETER C_HAS_CD = 1
PARAMETER C_HAS_WP = 1
PARAMETER C_HAS_POWER = 0
END
BEGIN ps7_ethernet
PARAMETER INSTANCE = ps7_ethernet_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xE000B000
PARAMETER C_S_AXI_HIGHADDR = 0xE000BFFF
PARAMETER C_ENET_CLK_FREQ_HZ = 125000000
PARAMETER C_ENET_SLCR_1000Mbps_DIV0 = 8
PARAMETER C_ENET_SLCR_1000Mbps_DIV1 = 1
PARAMETER C_ENET_SLCR_100Mbps_DIV0 = 8
PARAMETER C_ENET_SLCR_100Mbps_DIV1 = 5
PARAMETER C_ENET_SLCR_10Mbps_DIV0 = 8
PARAMETER C_ENET_SLCR_10Mbps_DIV1 = 50
PARAMETER C_HAS_MDIO = 1
PARAMETER C_ETH_MODE = 1
PARAMETER C_ENET_RESET = -1
END
BEGIN ps7_usb
PARAMETER INSTANCE = ps7_usb_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xE0002000
PARAMETER C_S_AXI_HIGHADDR = 0xE0002FFF
PARAMETER C_USB_RESET = MIO 46
END
BEGIN ps7_qspi
PARAMETER INSTANCE = ps7_qspi_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xE000D000
PARAMETER C_S_AXI_HIGHADDR = 0xE000DFFF
PARAMETER C_QSPI_CLK_FREQ_HZ = 200000000
PARAMETER C_QSPI_MODE = 0
PARAMETER C_FB_CLK = 1
END
BEGIN ps7_qspi_linear
PARAMETER INSTANCE = ps7_qspi_linear_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xFC000000
PARAMETER C_S_AXI_HIGHADDR = 0xFCFFFFFF
END
BEGIN ps7_ddr
PARAMETER INSTANCE = ps7_ddr_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0x00100000
PARAMETER C_S_AXI_HIGHADDR = 0x1FFFFFFF
PARAMETER C_S_AXI_HP0_BASEADDR = 0x00000000
PARAMETER C_S_AXI_HP0_HIGHADDR = 0x1FFFFFFF
PARAMETER C_S_AXI_HP1_BASEADDR = 0x00000000
PARAMETER C_S_AXI_HP1_HIGHADDR = 0x1FFFFFFF
PARAMETER C_S_AXI_HP2_BASEADDR = 0x00000000
PARAMETER C_S_AXI_HP2_HIGHADDR = 0x1FFFFFFF
PARAMETER C_S_AXI_HP3_BASEADDR = 0x00000000
PARAMETER C_S_AXI_HP3_HIGHADDR = 0x1FFFFFFF
END
BEGIN ps7_gpio
PARAMETER INSTANCE = ps7_gpio_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xE000A000
PARAMETER C_S_AXI_HIGHADDR = 0xE000AFFF
PARAMETER C_MIO_GPIO_MASK = 0xc00000000f281
PARAMETER C_EMIO_GPIO_WIDTH = 64
END
###
### TODO
###
BEGIN ps7_cortexa9
PARAMETER INSTANCE = ps7_cortexa9_0
PARAMETER HW_VER = 5.02.a
BUS_INTERFACE M_AXI_DP = ps7_axi_interconnect_0
PARAMETER C_CPU_CLK_FREQ_HZ = 650000000
PARAMETER C_CPU_1X_CLK_FREQ_HZ = 108333336
PARAMETER C_CPU_REF_CLK_FREQ_HZ = 50000000
END
BEGIN ps7_cortexa9
PARAMETER INSTANCE = ps7_cortexa9_1
PARAMETER HW_VER = 5.02.a
BUS_INTERFACE M_AXI_DP = ps7_axi_interconnect_0
PARAMETER C_CPU_CLK_FREQ_HZ = 650000000
PARAMETER C_CPU_1X_CLK_FREQ_HZ = 108333336
PARAMETER C_CPU_REF_CLK_FREQ_HZ = 50000000
END
BEGIN ps7_ddrc
PARAMETER INSTANCE = ps7_ddrc_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xF8006000
PARAMETER C_S_AXI_HIGHADDR = 0xF8006FFF
PARAMETER C_HAS_ECC = 0
END
BEGIN ps7_dev_cfg
PARAMETER INSTANCE = ps7_dev_cfg_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xF8007000
PARAMETER C_S_AXI_HIGHADDR = 0xF80070FF
END
BEGIN ps7_xadc
PARAMETER INSTANCE = ps7_xadc_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xF8007100
PARAMETER C_S_AXI_HIGHADDR = 0xF8007120
END
BEGIN ps7_coresight_comp
PARAMETER INSTANCE = ps7_coresight_comp_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xF8800000
PARAMETER C_S_AXI_HIGHADDR = 0xF88FFFFF
END
BEGIN ps7_ocmc
PARAMETER INSTANCE = ps7_ocmc_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xF800C000
PARAMETER C_S_AXI_HIGHADDR = 0xF800CFFF
END
BEGIN ps7_gpv
PARAMETER INSTANCE = ps7_gpv_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xF8900000
PARAMETER C_S_AXI_HIGHADDR = 0xF89FFFFF
END
BEGIN ps7_scuc
PARAMETER INSTANCE = ps7_scuc_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xF8F00000
PARAMETER C_S_AXI_HIGHADDR = 0xF8F000FC
END
BEGIN ps7_intc_dist
PARAMETER INSTANCE = ps7_intc_dist_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xF8F01000
PARAMETER C_S_AXI_HIGHADDR = 0xF8F01FFF
END
BEGIN ps7_globaltimer
PARAMETER INSTANCE = ps7_globaltimer_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xF8F00200
PARAMETER C_S_AXI_HIGHADDR = 0xF8F002FF
END
BEGIN ps7_l2cachec
PARAMETER INSTANCE = ps7_l2cachec_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xF8F02000
PARAMETER C_S_AXI_HIGHADDR = 0xF8F02FFF
END
BEGIN ps7_dma
PARAMETER INSTANCE = ps7_dma_s
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_LITE_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI_LITE = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xF8003000
PARAMETER C_S_AXI_HIGHADDR = 0xF8003FFF
END
BEGIN ps7_iop_bus_config
PARAMETER INSTANCE = ps7_iop_bus_config_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xE0200000
PARAMETER C_S_AXI_HIGHADDR = 0xE0200FFF
END
BEGIN ps7_ram
PARAMETER INSTANCE = ps7_ram_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0x00000000
PARAMETER C_S_AXI_HIGHADDR = 0x0002FFFF
END
BEGIN ps7_ram
PARAMETER INSTANCE = ps7_ram_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xFFFF0000
PARAMETER C_S_AXI_HIGHADDR = 0xFFFFFDFF
END
BEGIN ps7_scugic
PARAMETER INSTANCE = ps7_scugic_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xF8F00100
PARAMETER C_S_AXI_HIGHADDR = 0xF8F001FF
PORT IRQ_F2P = ps7_IRQ_F2P
PORT Core0_nFIQ = ps7_Core0_nFIQ
PORT Core0_nIRQ = ps7_Core0_nIRQ
PORT Core1_nFIQ = ps7_Core1_nFIQ
PORT Core1_nIRQ = ps7_Core1_nIRQ
END
BEGIN ps7_scutimer
PARAMETER INSTANCE = ps7_scutimer_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_1.M_AXI_DP & ps7_cortexa9_0.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xF8F00600
PARAMETER C_S_AXI_HIGHADDR = 0xF8F0061F
END
BEGIN ps7_scuwdt
PARAMETER INSTANCE = ps7_scuwdt_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xF8F00620
PARAMETER C_S_AXI_HIGHADDR = 0xF8F006FF
END
BEGIN ps7_slcr
PARAMETER INSTANCE = ps7_slcr_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xF8000000
PARAMETER C_S_AXI_HIGHADDR = 0xF8000FFF
END
BEGIN ps7_dma
PARAMETER INSTANCE = ps7_dma_ns
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERCONNECT_S_AXI_LITE_MASTERS = ps7_cortexa9_0.M_AXI_DP & ps7_cortexa9_1.M_AXI_DP
BUS_INTERFACE S_AXI_LITE = ps7_axi_interconnect_0
PARAMETER C_S_AXI_BASEADDR = 0xF8004000
PARAMETER C_S_AXI_HIGHADDR = 0xF8004FFF
END
quad/sytem/__xps/simgen.opt 0 → 100644
View file @ f6378157
-p zynq -lang vhdl$(PROJECT_SEARCHPATHOPT) $(GLOBAL_SEARCHPATHOPT) -msg __xps/ise/xmsgprops.lst -s isim
quad/sytem/__xps/system.xml 0 → 100644
View file @ f6378157
Source diff could not be displayed: it is too large. Options to address this: view the blob.
quad/sytem/__xps/xplorer.opt 0 → 100644
View file @ f6378157
-device xc7z010clg400-1 data/system.ucf 7 0
quad/sytem/__xps/xpsxflow.opt 0 → 100644
View file @ f6378157
-device xc7z010clg400-1 data/system.ucf 0
quad/sytem/clock_generator_0.log 0 → 100644
View file @ f6378157
------------------------------------------------------------------------------
-- clock_generator_0.log
------------------------------------------------------------------------------
quad/sytem/data/ps7_constraints.ucf 0 → 100644
View file @ f6378157
############################################################################
##
## Xilinx, Inc. 2006 www.xilinx.com
############################################################################
## File name : data/ps7_constraints.ucf
##
## Details : Constraints file
## FPGA family: zynq
## FPGA: xc7z010clg400-1
## Device Size: xc7z010
## Package: clg400
## Speedgrade: -1
##
##Note: This is a generated file. Configuration settings should not be edited
##
############################################################################
############################################################################
############################################################################
# I/O STANDARDS and Location Constraints #
############################################################################
NET "MIO[53]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "C11" ; # Enet 0 / mdio / MIO[53]
NET "MIO[52]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "C10" ; # Enet 0 / mdc / MIO[52]
NET "MIO[51]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "B9" ; # GPIO / gpio[51] / MIO[51]
NET "MIO[50]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "B13" ; # GPIO / gpio[50] / MIO[50]
NET "MIO[49]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "C12" ; # UART 1 / rx / MIO[49]
NET "MIO[48]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "B12" ; # UART 1 / tx / MIO[48]
NET "MIO[47]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "B14" ; # SD 0 / cd / MIO[47]
NET "MIO[46]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "D16" ; # USB 0 / reset / MIO[46]
NET "MIO[45]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "B15" ; # SD 0 / data[3] / MIO[45]
NET "MIO[44]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "F13" ; # SD 0 / data[2] / MIO[44]
NET "MIO[43]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "A9" ; # SD 0 / data[1] / MIO[43]
NET "MIO[42]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "E12" ; # SD 0 / data[0] / MIO[42]
NET "MIO[41]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "C17" ; # SD 0 / cmd / MIO[41]
NET "MIO[40]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "D14" ; # SD 0 / clk / MIO[40]
NET "MIO[39]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "C18" ; # USB 0 / data[7] / MIO[39]
NET "MIO[38]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "E13" ; # USB 0 / data[6] / MIO[38]
NET "MIO[37]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "A10" ; # USB 0 / data[5] / MIO[37]
NET "MIO[36]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "A11" ; # USB 0 / clk / MIO[36]
NET "MIO[35]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "F12" ; # USB 0 / data[3] / MIO[35]
NET "MIO[34]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "A12" ; # USB 0 / data[2] / MIO[34]
NET "MIO[33]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "D15" ; # USB 0 / data[1] / MIO[33]
NET "MIO[32]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "A14" ; # USB 0 / data[0] / MIO[32]
NET "MIO[31]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "E16" ; # USB 0 / nxt / MIO[31]
NET "MIO[30]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "C15" ; # USB 0 / stp / MIO[30]
NET "MIO[29]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "C13" ; # USB 0 / dir / MIO[29]
NET "MIO[28]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "C16" ; # USB 0 / data[4] / MIO[28]
NET "MIO[27]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "D13" ; # Enet 0 / rx_ctl / MIO[27]
NET "MIO[26]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "A15" ; # Enet 0 / rxd[3] / MIO[26]
NET "MIO[25]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "F15" ; # Enet 0 / rxd[2] / MIO[25]
NET "MIO[24]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "A16" ; # Enet 0 / rxd[1] / MIO[24]
NET "MIO[23]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "D11" ; # Enet 0 / rxd[0] / MIO[23]
NET "MIO[22]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "B17" ; # Enet 0 / rx_clk / MIO[22]
NET "MIO[21]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "F14" ; # Enet 0 / tx_ctl / MIO[21]
NET "MIO[20]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "A17" ; # Enet 0 / txd[3] / MIO[20]
NET "MIO[19]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "D10" ; # Enet 0 / txd[2] / MIO[19]
NET "MIO[18]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "B18" ; # Enet 0 / txd[1] / MIO[18]
NET "MIO[17]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "E14" ; # Enet 0 / txd[0] / MIO[17]
NET "MIO[16]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "A19" ; # Enet 0 / tx_clk / MIO[16]
NET "MIO[15]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "slow" | LOC = "C8" ; # GPIO / gpio[15] / MIO[15]
NET "MIO[14]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "slow" | LOC = "C5" ; # GPIO / gpio[14] / MIO[14]
NET "MIO[13]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "slow" | LOC = "E8" ; # GPIO / gpio[13] / MIO[13]
NET "MIO[12]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "slow" | LOC = "D9" ; # GPIO / gpio[12] / MIO[12]
NET "MIO[11]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "slow" | LOC = "C6" | PULLUP = "TRUE" ; # I2C 0 / sda / MIO[11]
NET "MIO[10]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "slow" | LOC = "E9" | PULLUP = "TRUE" ; # I2C 0 / scl / MIO[10]
NET "MIO[9]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "slow" | LOC = "B5" ; # GPIO / gpio[9] / MIO[9]
NET "MIO[8]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "fast" | LOC = "D5" ; # Quad SPI Flash / qspi_fbclk / MIO[8]
NET "MIO[7]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "slow" | LOC = "D8" ; # GPIO / gpio[7] / MIO[7]
NET "MIO[6]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "fast" | LOC = "A5" ; # Quad SPI Flash / qspi0_sclk / MIO[6]
NET "MIO[5]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "fast" | LOC = "A6" ; # Quad SPI Flash / qspi0_io[3] / MIO[5]
NET "MIO[4]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "fast" | LOC = "B7" ; # Quad SPI Flash / qspi0_io[2] / MIO[4]
NET "MIO[3]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "fast" | LOC = "D6" ; # Quad SPI Flash / qspi0_io[1] / MIO[3]
NET "MIO[2]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "fast" | LOC = "B8" ; # Quad SPI Flash / qspi0_io[0] / MIO[2]
NET "MIO[1]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "fast" | LOC = "A7" ; # Quad SPI Flash / qspi0_ss_b / MIO[1]
NET "MIO[0]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "slow" | LOC = "E6" ; # GPIO / gpio[0] / MIO[0]
NET "DDR_WEB" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "M5" ;
NET "DDR_VRP" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "H5" ;
NET "DDR_VRN" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "G5" ;
NET "DDR_RAS_n" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "P4" ;
NET "DDR_ODT" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "N5" ;
NET "DDR_DRSTB" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "B4" ;
NET "DDR_DQS[3]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "W5" ;
NET "DDR_DQS[2]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "R2" ;
NET "DDR_DQS[1]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "G2" ;
NET "DDR_DQS[0]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "C2" ;
NET "DDR_DQS_n[3]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "W4" ;
NET "DDR_DQS_n[2]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "T2" ;
NET "DDR_DQS_n[1]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "F2" ;
NET "DDR_DQS_n[0]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "B2" ;
NET "DDR_DQ[9]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "E3" ;
NET "DDR_DQ[8]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "E2" ;
NET "DDR_DQ[7]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "E1" ;
NET "DDR_DQ[6]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "C1" ;
NET "DDR_DQ[5]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "D1" ;
NET "DDR_DQ[4]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "D3" ;
NET "DDR_DQ[3]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "A4" ;
NET "DDR_DQ[31]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "V3" ;
NET "DDR_DQ[30]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "V2" ;
NET "DDR_DQ[2]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "A2" ;
NET "DDR_DQ[29]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "W3" ;
NET "DDR_DQ[28]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "Y2" ;
NET "DDR_DQ[27]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "Y4" ;
NET "DDR_DQ[26]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "W1" ;
NET "DDR_DQ[25]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "Y3" ;
NET "DDR_DQ[24]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "V1" ;
NET "DDR_DQ[23]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "U3" ;
NET "DDR_DQ[22]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "U2" ;
NET "DDR_DQ[21]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "U4" ;
NET "DDR_DQ[20]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "T4" ;
NET "DDR_DQ[1]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "B3" ;
NET "DDR_DQ[19]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "R1" ;
NET "DDR_DQ[18]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "R3" ;
NET "DDR_DQ[17]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "P3" ;
NET "DDR_DQ[16]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "P1" ;
NET "DDR_DQ[15]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "J1" ;
NET "DDR_DQ[14]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "H1" ;
NET "DDR_DQ[13]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "H2" ;
NET "DDR_DQ[12]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "J3" ;
NET "DDR_DQ[11]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "H3" ;
NET "DDR_DQ[10]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "G3" ;
NET "DDR_DQ[0]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "C3" ;
NET "DDR_DM[3]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "Y1" ;
NET "DDR_DM[2]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "T1" ;
NET "DDR_DM[1]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "F1" ;
NET "DDR_DM[0]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "A1" ;
NET "DDR_CS_n" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "N1" ;
NET "DDR_CKE" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "N3" ;
NET "DDR_Clk" IOSTANDARD = DIFF_SSTL15 | SLEW = "FAST" | LOC = "L2" ;
NET "DDR_Clk_n" IOSTANDARD = DIFF_SSTL15 | SLEW = "FAST" | LOC = "M2" ;
NET "DDR_CAS_n" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "P5" ;
NET "DDR_BankAddr[2]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "J5" ;
NET "DDR_BankAddr[1]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "R4" ;
NET "DDR_BankAddr[0]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "L5" ;
NET "DDR_Addr[9]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "J4" ;
NET "DDR_Addr[8]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "K1" ;
NET "DDR_Addr[7]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "K4" ;
NET "DDR_Addr[6]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "L4" ;
NET "DDR_Addr[5]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "L1" ;
NET "DDR_Addr[4]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "M4" ;
NET "DDR_Addr[3]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "K3" ;
NET "DDR_Addr[2]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "M3" ;
NET "DDR_Addr[1]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "K2" ;
NET "DDR_Addr[14]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "F4" ;
NET "DDR_Addr[13]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "D4" ;
NET "DDR_Addr[12]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "E4" ;
NET "DDR_Addr[11]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "G4" ;
NET "DDR_Addr[10]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "F5" ;
NET "DDR_Addr[0]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "N2" ;
NET "PS_PORB" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "slow" | LOC = "C7" ;
NET "PS_SRSTB" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "slow" | LOC = "B10" ;
NET "PS_CLK" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "slow" | LOC = "E7" ;
quad/sytem/data/ps7_constraints.xdc 0 → 100644
View file @ f6378157
############################################################################
##
## Xilinx, Inc. 2006 www.xilinx.com
############################################################################
## File name : data/ps7_constraints.xdc
##
## Details : Constraints file
## FPGA family: zynq
## FPGA: xc7z010clg400-1
## Device Size: xc7z010
## Package: clg400
## Speedgrade: -1
##
##Note: This is a generated file. Configuration settings should not be edited
##
############################################################################
############################################################################
############################################################################
# I/O STANDARDS and Location Constraints #
############################################################################
# Enet 0 / mdio / MIO[53]
set_property iostandard "LVCMOS18" [get_ports "MIO[53]"]
set_property PACKAGE_PIN "C11" [get_ports "MIO[53]"]
set_property slew "slow" [get_ports "MIO[53]"]
set_property drive "8" [get_ports "MIO[53]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[53]"]
# Enet 0 / mdc / MIO[52]
set_property iostandard "LVCMOS18" [get_ports "MIO[52]"]
set_property PACKAGE_PIN "C10" [get_ports "MIO[52]"]
set_property slew "slow" [get_ports "MIO[52]"]
set_property drive "8" [get_ports "MIO[52]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[52]"]
# GPIO / gpio[51] / MIO[51]
set_property iostandard "LVCMOS18" [get_ports "MIO[51]"]
set_property PACKAGE_PIN "B9" [get_ports "MIO[51]"]
set_property slew "slow" [get_ports "MIO[51]"]
set_property drive "8" [get_ports "MIO[51]"]
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[51]"]
# GPIO / gpio[50] / MIO[50]
set_property iostandard "LVCMOS18" [get_ports "MIO[50]"]
set_property PACKAGE_PIN "B13" [get_ports "MIO[50]"]
set_property slew "slow" [get_ports "MIO[50]"]
set_property drive "8" [get_ports "MIO[50]"]
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[50]"]
# UART 1 / rx / MIO[49]
set_property iostandard "LVCMOS18" [get_ports "MIO[49]"]
set_property PACKAGE_PIN "C12" [get_ports "MIO[49]"]
set_property slew "slow" [get_ports "MIO[49]"]
set_property drive "8" [get_ports "MIO[49]"]
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[49]"]
# UART 1 / tx / MIO[48]
set_property iostandard "LVCMOS18" [get_ports "MIO[48]"]
set_property PACKAGE_PIN "B12" [get_ports "MIO[48]"]
set_property slew "slow" [get_ports "MIO[48]"]
set_property drive "8" [get_ports "MIO[48]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[48]"]
# SD 0 / cd / MIO[47]
set_property iostandard "LVCMOS18" [get_ports "MIO[47]"]
set_property PACKAGE_PIN "B14" [get_ports "MIO[47]"]
set_property slew "slow" [get_ports "MIO[47]"]
set_property drive "8" [get_ports "MIO[47]"]
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[47]"]
# USB 0 / reset / MIO[46]
set_property iostandard "LVCMOS18" [get_ports "MIO[46]"]
set_property PACKAGE_PIN "D16" [get_ports "MIO[46]"]
set_property slew "slow" [get_ports "MIO[46]"]
set_property drive "8" [get_ports "MIO[46]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[46]"]
# SD 0 / data[3] / MIO[45]
set_property iostandard "LVCMOS18" [get_ports "MIO[45]"]
set_property PACKAGE_PIN "B15" [get_ports "MIO[45]"]
set_property slew "fast" [get_ports "MIO[45]"]
set_property drive "8" [get_ports "MIO[45]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[45]"]
# SD 0 / data[2] / MIO[44]
set_property iostandard "LVCMOS18" [get_ports "MIO[44]"]
set_property PACKAGE_PIN "F13" [get_ports "MIO[44]"]
set_property slew "fast" [get_ports "MIO[44]"]
set_property drive "8" [get_ports "MIO[44]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[44]"]
# SD 0 / data[1] / MIO[43]
set_property iostandard "LVCMOS18" [get_ports "MIO[43]"]
set_property PACKAGE_PIN "A9" [get_ports "MIO[43]"]
set_property slew "fast" [get_ports "MIO[43]"]
set_property drive "8" [get_ports "MIO[43]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[43]"]
# SD 0 / data[0] / MIO[42]
set_property iostandard "LVCMOS18" [get_ports "MIO[42]"]
set_property PACKAGE_PIN "E12" [get_ports "MIO[42]"]
set_property slew "fast" [get_ports "MIO[42]"]
set_property drive "8" [get_ports "MIO[42]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[42]"]
# SD 0 / cmd / MIO[41]
set_property iostandard "LVCMOS18" [get_ports "MIO[41]"]
set_property PACKAGE_PIN "C17" [get_ports "MIO[41]"]
set_property slew "fast" [get_ports "MIO[41]"]
set_property drive "8" [get_ports "MIO[41]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[41]"]
# SD 0 / clk / MIO[40]
set_property iostandard "LVCMOS18" [get_ports "MIO[40]"]
set_property PACKAGE_PIN "D14" [get_ports "MIO[40]"]
set_property slew "fast" [get_ports "MIO[40]"]
set_property drive "8" [get_ports "MIO[40]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[40]"]
# USB 0 / data[7] / MIO[39]
set_property iostandard "LVCMOS18" [get_ports "MIO[39]"]
set_property PACKAGE_PIN "C18" [get_ports "MIO[39]"]
set_property slew "fast" [get_ports "MIO[39]"]
set_property drive "8" [get_ports "MIO[39]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[39]"]
# USB 0 / data[6] / MIO[38]
set_property iostandard "LVCMOS18" [get_ports "MIO[38]"]
set_property PACKAGE_PIN "E13" [get_ports "MIO[38]"]
set_property slew "fast" [get_ports "MIO[38]"]
set_property drive "8" [get_ports "MIO[38]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[38]"]
# USB 0 / data[5] / MIO[37]
set_property iostandard "LVCMOS18" [get_ports "MIO[37]"]
set_property PACKAGE_PIN "A10" [get_ports "MIO[37]"]
set_property slew "fast" [get_ports "MIO[37]"]
set_property drive "8" [get_ports "MIO[37]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[37]"]
# USB 0 / clk / MIO[36]
set_property iostandard "LVCMOS18" [get_ports "MIO[36]"]
set_property PACKAGE_PIN "A11" [get_ports "MIO[36]"]
set_property slew "fast" [get_ports "MIO[36]"]
set_property drive "8" [get_ports "MIO[36]"]
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[36]"]
# USB 0 / data[3] / MIO[35]
set_property iostandard "LVCMOS18" [get_ports "MIO[35]"]
set_property PACKAGE_PIN "F12" [get_ports "MIO[35]"]
set_property slew "fast" [get_ports "MIO[35]"]
set_property drive "8" [get_ports "MIO[35]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[35]"]
# USB 0 / data[2] / MIO[34]
set_property iostandard "LVCMOS18" [get_ports "MIO[34]"]
set_property PACKAGE_PIN "A12" [get_ports "MIO[34]"]
set_property slew "fast" [get_ports "MIO[34]"]
set_property drive "8" [get_ports "MIO[34]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[34]"]
# USB 0 / data[1] / MIO[33]
set_property iostandard "LVCMOS18" [get_ports "MIO[33]"]
set_property PACKAGE_PIN "D15" [get_ports "MIO[33]"]
set_property slew "fast" [get_ports "MIO[33]"]
set_property drive "8" [get_ports "MIO[33]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[33]"]
# USB 0 / data[0] / MIO[32]
set_property iostandard "LVCMOS18" [get_ports "MIO[32]"]
set_property PACKAGE_PIN "A14" [get_ports "MIO[32]"]
set_property slew "fast" [get_ports "MIO[32]"]
set_property drive "8" [get_ports "MIO[32]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[32]"]
# USB 0 / nxt / MIO[31]
set_property iostandard "LVCMOS18" [get_ports "MIO[31]"]
set_property PACKAGE_PIN "E16" [get_ports "MIO[31]"]
set_property slew "fast" [get_ports "MIO[31]"]
set_property drive "8" [get_ports "MIO[31]"]
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[31]"]
# USB 0 / stp / MIO[30]
set_property iostandard "LVCMOS18" [get_ports "MIO[30]"]
set_property PACKAGE_PIN "C15" [get_ports "MIO[30]"]
set_property slew "fast" [get_ports "MIO[30]"]
set_property drive "8" [get_ports "MIO[30]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[30]"]
# USB 0 / dir / MIO[29]
set_property iostandard "LVCMOS18" [get_ports "MIO[29]"]
set_property PACKAGE_PIN "C13" [get_ports "MIO[29]"]
set_property slew "fast" [get_ports "MIO[29]"]
set_property drive "8" [get_ports "MIO[29]"]
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[29]"]
# USB 0 / data[4] / MIO[28]
set_property iostandard "LVCMOS18" [get_ports "MIO[28]"]
set_property PACKAGE_PIN "C16" [get_ports "MIO[28]"]
set_property slew "fast" [get_ports "MIO[28]"]
set_property drive "8" [get_ports "MIO[28]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[28]"]
# Enet 0 / rx_ctl / MIO[27]
set_property iostandard "HSTL_I_18" [get_ports "MIO[27]"]
set_property PACKAGE_PIN "D13" [get_ports "MIO[27]"]
set_property slew "fast" [get_ports "MIO[27]"]
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[27]"]
# Enet 0 / rxd[3] / MIO[26]
set_property iostandard "HSTL_I_18" [get_ports "MIO[26]"]
set_property PACKAGE_PIN "A15" [get_ports "MIO[26]"]
set_property slew "fast" [get_ports "MIO[26]"]
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[26]"]
# Enet 0 / rxd[2] / MIO[25]
set_property iostandard "HSTL_I_18" [get_ports "MIO[25]"]
set_property PACKAGE_PIN "F15" [get_ports "MIO[25]"]
set_property slew "fast" [get_ports "MIO[25]"]
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[25]"]
# Enet 0 / rxd[1] / MIO[24]
set_property iostandard "HSTL_I_18" [get_ports "MIO[24]"]
set_property PACKAGE_PIN "A16" [get_ports "MIO[24]"]
set_property slew "fast" [get_ports "MIO[24]"]
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[24]"]
# Enet 0 / rxd[0] / MIO[23]
set_property iostandard "HSTL_I_18" [get_ports "MIO[23]"]
set_property PACKAGE_PIN "D11" [get_ports "MIO[23]"]
set_property slew "fast" [get_ports "MIO[23]"]
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[23]"]
# Enet 0 / rx_clk / MIO[22]
set_property iostandard "HSTL_I_18" [get_ports "MIO[22]"]
set_property PACKAGE_PIN "B17" [get_ports "MIO[22]"]
set_property slew "fast" [get_ports "MIO[22]"]
set_property PIO_DIRECTION "INPUT" [get_ports "MIO[22]"]
# Enet 0 / tx_ctl / MIO[21]
set_property iostandard "HSTL_I_18" [get_ports "MIO[21]"]
set_property PACKAGE_PIN "F14" [get_ports "MIO[21]"]
set_property slew "fast" [get_ports "MIO[21]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[21]"]
# Enet 0 / txd[3] / MIO[20]
set_property iostandard "HSTL_I_18" [get_ports "MIO[20]"]
set_property PACKAGE_PIN "A17" [get_ports "MIO[20]"]
set_property slew "fast" [get_ports "MIO[20]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[20]"]
# Enet 0 / txd[2] / MIO[19]
set_property iostandard "HSTL_I_18" [get_ports "MIO[19]"]
set_property PACKAGE_PIN "D10" [get_ports "MIO[19]"]
set_property slew "fast" [get_ports "MIO[19]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[19]"]
# Enet 0 / txd[1] / MIO[18]
set_property iostandard "HSTL_I_18" [get_ports "MIO[18]"]
set_property PACKAGE_PIN "B18" [get_ports "MIO[18]"]
set_property slew "fast" [get_ports "MIO[18]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[18]"]
# Enet 0 / txd[0] / MIO[17]
set_property iostandard "HSTL_I_18" [get_ports "MIO[17]"]
set_property PACKAGE_PIN "E14" [get_ports "MIO[17]"]
set_property slew "fast" [get_ports "MIO[17]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[17]"]
# Enet 0 / tx_clk / MIO[16]
set_property iostandard "HSTL_I_18" [get_ports "MIO[16]"]
set_property PACKAGE_PIN "A19" [get_ports "MIO[16]"]
set_property slew "fast" [get_ports "MIO[16]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[16]"]
# GPIO / gpio[15] / MIO[15]
set_property iostandard "LVCMOS33" [get_ports "MIO[15]"]
set_property PACKAGE_PIN "C8" [get_ports "MIO[15]"]
set_property slew "slow" [get_ports "MIO[15]"]
set_property drive "8" [get_ports "MIO[15]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[15]"]
# GPIO / gpio[14] / MIO[14]
set_property iostandard "LVCMOS33" [get_ports "MIO[14]"]
set_property PACKAGE_PIN "C5" [get_ports "MIO[14]"]
set_property slew "slow" [get_ports "MIO[14]"]
set_property drive "8" [get_ports "MIO[14]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[14]"]
# GPIO / gpio[13] / MIO[13]
set_property iostandard "LVCMOS33" [get_ports "MIO[13]"]
set_property PACKAGE_PIN "E8" [get_ports "MIO[13]"]
set_property slew "slow" [get_ports "MIO[13]"]
set_property drive "8" [get_ports "MIO[13]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[13]"]
# GPIO / gpio[12] / MIO[12]
set_property iostandard "LVCMOS33" [get_ports "MIO[12]"]
set_property PACKAGE_PIN "D9" [get_ports "MIO[12]"]
set_property slew "slow" [get_ports "MIO[12]"]
set_property drive "8" [get_ports "MIO[12]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[12]"]
# I2C 0 / sda / MIO[11]
set_property iostandard "LVCMOS33" [get_ports "MIO[11]"]
set_property PACKAGE_PIN "C6" [get_ports "MIO[11]"]
set_property slew "slow" [get_ports "MIO[11]"]
set_property drive "8" [get_ports "MIO[11]"]
set_property pullup "TRUE" [get_ports "MIO[11]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[11]"]
# I2C 0 / scl / MIO[10]
set_property iostandard "LVCMOS33" [get_ports "MIO[10]"]
set_property PACKAGE_PIN "E9" [get_ports "MIO[10]"]
set_property slew "slow" [get_ports "MIO[10]"]
set_property drive "8" [get_ports "MIO[10]"]
set_property pullup "TRUE" [get_ports "MIO[10]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[10]"]
# GPIO / gpio[9] / MIO[9]
set_property iostandard "LVCMOS33" [get_ports "MIO[9]"]
set_property PACKAGE_PIN "B5" [get_ports "MIO[9]"]
set_property slew "slow" [get_ports "MIO[9]"]
set_property drive "8" [get_ports "MIO[9]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[9]"]
# Quad SPI Flash / qspi_fbclk / MIO[8]
set_property iostandard "LVCMOS33" [get_ports "MIO[8]"]
set_property PACKAGE_PIN "D5" [get_ports "MIO[8]"]
set_property slew "fast" [get_ports "MIO[8]"]
set_property drive "8" [get_ports "MIO[8]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[8]"]
# GPIO / gpio[7] / MIO[7]
set_property iostandard "LVCMOS33" [get_ports "MIO[7]"]
set_property PACKAGE_PIN "D8" [get_ports "MIO[7]"]
set_property slew "slow" [get_ports "MIO[7]"]
set_property drive "8" [get_ports "MIO[7]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[7]"]
# Quad SPI Flash / qspi0_sclk / MIO[6]
set_property iostandard "LVCMOS33" [get_ports "MIO[6]"]
set_property PACKAGE_PIN "A5" [get_ports "MIO[6]"]
set_property slew "fast" [get_ports "MIO[6]"]
set_property drive "8" [get_ports "MIO[6]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[6]"]
# Quad SPI Flash / qspi0_io[3] / MIO[5]
set_property iostandard "LVCMOS33" [get_ports "MIO[5]"]
set_property PACKAGE_PIN "A6" [get_ports "MIO[5]"]
set_property slew "fast" [get_ports "MIO[5]"]
set_property drive "8" [get_ports "MIO[5]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[5]"]
# Quad SPI Flash / qspi0_io[2] / MIO[4]
set_property iostandard "LVCMOS33" [get_ports "MIO[4]"]
set_property PACKAGE_PIN "B7" [get_ports "MIO[4]"]
set_property slew "fast" [get_ports "MIO[4]"]
set_property drive "8" [get_ports "MIO[4]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[4]"]
# Quad SPI Flash / qspi0_io[1] / MIO[3]
set_property iostandard "LVCMOS33" [get_ports "MIO[3]"]
set_property PACKAGE_PIN "D6" [get_ports "MIO[3]"]
set_property slew "fast" [get_ports "MIO[3]"]
set_property drive "8" [get_ports "MIO[3]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[3]"]
# Quad SPI Flash / qspi0_io[0] / MIO[2]
set_property iostandard "LVCMOS33" [get_ports "MIO[2]"]
set_property PACKAGE_PIN "B8" [get_ports "MIO[2]"]
set_property slew "fast" [get_ports "MIO[2]"]
set_property drive "8" [get_ports "MIO[2]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[2]"]
# Quad SPI Flash / qspi0_ss_b / MIO[1]
set_property iostandard "LVCMOS33" [get_ports "MIO[1]"]
set_property PACKAGE_PIN "A7" [get_ports "MIO[1]"]
set_property slew "fast" [get_ports "MIO[1]"]
set_property drive "8" [get_ports "MIO[1]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[1]"]
# GPIO / gpio[0] / MIO[0]
set_property iostandard "LVCMOS33" [get_ports "MIO[0]"]
set_property PACKAGE_PIN "E6" [get_ports "MIO[0]"]
set_property slew "slow" [get_ports "MIO[0]"]
set_property drive "8" [get_ports "MIO[0]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[0]"]
set_property iostandard "SSTL15" [get_ports "DDR_WEB"]
set_property PACKAGE_PIN "M5" [get_ports "DDR_WEB"]
set_property slew "SLOW" [get_ports "DDR_WEB"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_WEB"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRP"]
set_property PACKAGE_PIN "H5" [get_ports "DDR_VRP"]
set_property slew "FAST" [get_ports "DDR_VRP"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRP"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRN"]
set_property PACKAGE_PIN "G5" [get_ports "DDR_VRN"]
set_property slew "FAST" [get_ports "DDR_VRN"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRN"]
set_property iostandard "SSTL15" [get_ports "DDR_RAS_n"]
set_property PACKAGE_PIN "P4" [get_ports "DDR_RAS_n"]
set_property slew "SLOW" [get_ports "DDR_RAS_n"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_RAS_n"]
set_property iostandard "SSTL15" [get_ports "DDR_ODT"]
set_property PACKAGE_PIN "N5" [get_ports "DDR_ODT"]
set_property slew "SLOW" [get_ports "DDR_ODT"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_ODT"]
set_property iostandard "SSTL15" [get_ports "DDR_DRSTB"]
set_property PACKAGE_PIN "B4" [get_ports "DDR_DRSTB"]
set_property slew "FAST" [get_ports "DDR_DRSTB"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_DRSTB"]
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[3]"]
set_property PACKAGE_PIN "W5" [get_ports "DDR_DQS[3]"]
set_property slew "FAST" [get_ports "DDR_DQS[3]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[3]"]
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[2]"]
set_property PACKAGE_PIN "R2" [get_ports "DDR_DQS[2]"]
set_property slew "FAST" [get_ports "DDR_DQS[2]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[2]"]
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[1]"]
set_property PACKAGE_PIN "G2" [get_ports "DDR_DQS[1]"]
set_property slew "FAST" [get_ports "DDR_DQS[1]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[1]"]
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[0]"]
set_property PACKAGE_PIN "C2" [get_ports "DDR_DQS[0]"]
set_property slew "FAST" [get_ports "DDR_DQS[0]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[0]"]
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[3]"]
set_property PACKAGE_PIN "W4" [get_ports "DDR_DQS_n[3]"]
set_property slew "FAST" [get_ports "DDR_DQS_n[3]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[3]"]
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[2]"]
set_property PACKAGE_PIN "T2" [get_ports "DDR_DQS_n[2]"]
set_property slew "FAST" [get_ports "DDR_DQS_n[2]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[2]"]
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[1]"]
set_property PACKAGE_PIN "F2" [get_ports "DDR_DQS_n[1]"]
set_property slew "FAST" [get_ports "DDR_DQS_n[1]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[1]"]
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[0]"]
set_property PACKAGE_PIN "B2" [get_ports "DDR_DQS_n[0]"]
set_property slew "FAST" [get_ports "DDR_DQS_n[0]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[0]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[9]"]
set_property PACKAGE_PIN "E3" [get_ports "DDR_DQ[9]"]
set_property slew "FAST" [get_ports "DDR_DQ[9]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[9]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[8]"]
set_property PACKAGE_PIN "E2" [get_ports "DDR_DQ[8]"]
set_property slew "FAST" [get_ports "DDR_DQ[8]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[8]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[7]"]
set_property PACKAGE_PIN "E1" [get_ports "DDR_DQ[7]"]
set_property slew "FAST" [get_ports "DDR_DQ[7]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[7]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[6]"]
set_property PACKAGE_PIN "C1" [get_ports "DDR_DQ[6]"]
set_property slew "FAST" [get_ports "DDR_DQ[6]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[6]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[5]"]
set_property PACKAGE_PIN "D1" [get_ports "DDR_DQ[5]"]
set_property slew "FAST" [get_ports "DDR_DQ[5]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[5]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[4]"]
set_property PACKAGE_PIN "D3" [get_ports "DDR_DQ[4]"]
set_property slew "FAST" [get_ports "DDR_DQ[4]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[4]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[3]"]
set_property PACKAGE_PIN "A4" [get_ports "DDR_DQ[3]"]
set_property slew "FAST" [get_ports "DDR_DQ[3]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[3]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[31]"]
set_property PACKAGE_PIN "V3" [get_ports "DDR_DQ[31]"]
set_property slew "FAST" [get_ports "DDR_DQ[31]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[31]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[30]"]
set_property PACKAGE_PIN "V2" [get_ports "DDR_DQ[30]"]
set_property slew "FAST" [get_ports "DDR_DQ[30]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[30]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[2]"]
set_property PACKAGE_PIN "A2" [get_ports "DDR_DQ[2]"]
set_property slew "FAST" [get_ports "DDR_DQ[2]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[2]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[29]"]
set_property PACKAGE_PIN "W3" [get_ports "DDR_DQ[29]"]
set_property slew "FAST" [get_ports "DDR_DQ[29]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[29]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[28]"]
set_property PACKAGE_PIN "Y2" [get_ports "DDR_DQ[28]"]
set_property slew "FAST" [get_ports "DDR_DQ[28]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[28]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[27]"]
set_property PACKAGE_PIN "Y4" [get_ports "DDR_DQ[27]"]
set_property slew "FAST" [get_ports "DDR_DQ[27]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[27]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[26]"]
set_property PACKAGE_PIN "W1" [get_ports "DDR_DQ[26]"]
set_property slew "FAST" [get_ports "DDR_DQ[26]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[26]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[25]"]
set_property PACKAGE_PIN "Y3" [get_ports "DDR_DQ[25]"]
set_property slew "FAST" [get_ports "DDR_DQ[25]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[25]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[24]"]
set_property PACKAGE_PIN "V1" [get_ports "DDR_DQ[24]"]
set_property slew "FAST" [get_ports "DDR_DQ[24]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[24]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[23]"]
set_property PACKAGE_PIN "U3" [get_ports "DDR_DQ[23]"]
set_property slew "FAST" [get_ports "DDR_DQ[23]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[23]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[22]"]
set_property PACKAGE_PIN "U2" [get_ports "DDR_DQ[22]"]
set_property slew "FAST" [get_ports "DDR_DQ[22]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[22]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[21]"]
set_property PACKAGE_PIN "U4" [get_ports "DDR_DQ[21]"]
set_property slew "FAST" [get_ports "DDR_DQ[21]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[21]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[20]"]
set_property PACKAGE_PIN "T4" [get_ports "DDR_DQ[20]"]
set_property slew "FAST" [get_ports "DDR_DQ[20]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[20]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[1]"]
set_property PACKAGE_PIN "B3" [get_ports "DDR_DQ[1]"]
set_property slew "FAST" [get_ports "DDR_DQ[1]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[1]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[19]"]
set_property PACKAGE_PIN "R1" [get_ports "DDR_DQ[19]"]
set_property slew "FAST" [get_ports "DDR_DQ[19]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[19]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[18]"]
set_property PACKAGE_PIN "R3" [get_ports "DDR_DQ[18]"]
set_property slew "FAST" [get_ports "DDR_DQ[18]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[18]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[17]"]
set_property PACKAGE_PIN "P3" [get_ports "DDR_DQ[17]"]
set_property slew "FAST" [get_ports "DDR_DQ[17]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[17]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[16]"]
set_property PACKAGE_PIN "P1" [get_ports "DDR_DQ[16]"]
set_property slew "FAST" [get_ports "DDR_DQ[16]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[16]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[15]"]
set_property PACKAGE_PIN "J1" [get_ports "DDR_DQ[15]"]
set_property slew "FAST" [get_ports "DDR_DQ[15]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[15]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[14]"]
set_property PACKAGE_PIN "H1" [get_ports "DDR_DQ[14]"]
set_property slew "FAST" [get_ports "DDR_DQ[14]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[14]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[13]"]
set_property PACKAGE_PIN "H2" [get_ports "DDR_DQ[13]"]
set_property slew "FAST" [get_ports "DDR_DQ[13]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[13]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[12]"]
set_property PACKAGE_PIN "J3" [get_ports "DDR_DQ[12]"]
set_property slew "FAST" [get_ports "DDR_DQ[12]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[12]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[11]"]
set_property PACKAGE_PIN "H3" [get_ports "DDR_DQ[11]"]
set_property slew "FAST" [get_ports "DDR_DQ[11]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[11]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[10]"]
set_property PACKAGE_PIN "G3" [get_ports "DDR_DQ[10]"]
set_property slew "FAST" [get_ports "DDR_DQ[10]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[10]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[0]"]
set_property PACKAGE_PIN "C3" [get_ports "DDR_DQ[0]"]
set_property slew "FAST" [get_ports "DDR_DQ[0]"]
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[0]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[3]"]
set_property PACKAGE_PIN "Y1" [get_ports "DDR_DM[3]"]
set_property slew "FAST" [get_ports "DDR_DM[3]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_DM[3]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[2]"]
set_property PACKAGE_PIN "T1" [get_ports "DDR_DM[2]"]
set_property slew "FAST" [get_ports "DDR_DM[2]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_DM[2]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[1]"]
set_property PACKAGE_PIN "F1" [get_ports "DDR_DM[1]"]
set_property slew "FAST" [get_ports "DDR_DM[1]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_DM[1]"]
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[0]"]
set_property PACKAGE_PIN "A1" [get_ports "DDR_DM[0]"]
set_property slew "FAST" [get_ports "DDR_DM[0]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_DM[0]"]
set_property iostandard "SSTL15" [get_ports "DDR_CS_n"]
set_property PACKAGE_PIN "N1" [get_ports "DDR_CS_n"]
set_property slew "SLOW" [get_ports "DDR_CS_n"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CS_n"]
set_property iostandard "SSTL15" [get_ports "DDR_CKE"]
set_property PACKAGE_PIN "N3" [get_ports "DDR_CKE"]
set_property slew "SLOW" [get_ports "DDR_CKE"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CKE"]
set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk"]
set_property PACKAGE_PIN "L2" [get_ports "DDR_Clk"]
set_property slew "FAST" [get_ports "DDR_Clk"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Clk"]
set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk_n"]
set_property PACKAGE_PIN "M2" [get_ports "DDR_Clk_n"]
set_property slew "FAST" [get_ports "DDR_Clk_n"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Clk_n"]
set_property iostandard "SSTL15" [get_ports "DDR_CAS_n"]
set_property PACKAGE_PIN "P5" [get_ports "DDR_CAS_n"]
set_property slew "SLOW" [get_ports "DDR_CAS_n"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CAS_n"]
set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[2]"]
set_property PACKAGE_PIN "J5" [get_ports "DDR_BankAddr[2]"]
set_property slew "SLOW" [get_ports "DDR_BankAddr[2]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[2]"]
set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[1]"]
set_property PACKAGE_PIN "R4" [get_ports "DDR_BankAddr[1]"]
set_property slew "SLOW" [get_ports "DDR_BankAddr[1]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[1]"]
set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[0]"]
set_property PACKAGE_PIN "L5" [get_ports "DDR_BankAddr[0]"]
set_property slew "SLOW" [get_ports "DDR_BankAddr[0]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[0]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[9]"]
set_property PACKAGE_PIN "J4" [get_ports "DDR_Addr[9]"]
set_property slew "SLOW" [get_ports "DDR_Addr[9]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[9]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[8]"]
set_property PACKAGE_PIN "K1" [get_ports "DDR_Addr[8]"]
set_property slew "SLOW" [get_ports "DDR_Addr[8]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[8]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[7]"]
set_property PACKAGE_PIN "K4" [get_ports "DDR_Addr[7]"]
set_property slew "SLOW" [get_ports "DDR_Addr[7]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[7]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[6]"]
set_property PACKAGE_PIN "L4" [get_ports "DDR_Addr[6]"]
set_property slew "SLOW" [get_ports "DDR_Addr[6]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[6]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[5]"]
set_property PACKAGE_PIN "L1" [get_ports "DDR_Addr[5]"]
set_property slew "SLOW" [get_ports "DDR_Addr[5]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[5]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[4]"]
set_property PACKAGE_PIN "M4" [get_ports "DDR_Addr[4]"]
set_property slew "SLOW" [get_ports "DDR_Addr[4]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[4]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[3]"]
set_property PACKAGE_PIN "K3" [get_ports "DDR_Addr[3]"]
set_property slew "SLOW" [get_ports "DDR_Addr[3]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[3]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[2]"]
set_property PACKAGE_PIN "M3" [get_ports "DDR_Addr[2]"]
set_property slew "SLOW" [get_ports "DDR_Addr[2]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[2]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[1]"]
set_property PACKAGE_PIN "K2" [get_ports "DDR_Addr[1]"]
set_property slew "SLOW" [get_ports "DDR_Addr[1]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[1]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[14]"]
set_property PACKAGE_PIN "F4" [get_ports "DDR_Addr[14]"]
set_property slew "SLOW" [get_ports "DDR_Addr[14]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[14]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[13]"]
set_property PACKAGE_PIN "D4" [get_ports "DDR_Addr[13]"]
set_property slew "SLOW" [get_ports "DDR_Addr[13]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[13]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[12]"]
set_property PACKAGE_PIN "E4" [get_ports "DDR_Addr[12]"]
set_property slew "SLOW" [get_ports "DDR_Addr[12]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[12]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[11]"]
set_property PACKAGE_PIN "G4" [get_ports "DDR_Addr[11]"]
set_property slew "SLOW" [get_ports "DDR_Addr[11]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[11]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[10]"]
set_property PACKAGE_PIN "F5" [get_ports "DDR_Addr[10]"]
set_property slew "SLOW" [get_ports "DDR_Addr[10]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[10]"]
set_property iostandard "SSTL15" [get_ports "DDR_Addr[0]"]
set_property PACKAGE_PIN "N2" [get_ports "DDR_Addr[0]"]
set_property slew "SLOW" [get_ports "DDR_Addr[0]"]
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[0]"]
set_property iostandard "LVCMOS33" [get_ports "PS_PORB"]
set_property PACKAGE_PIN "C7" [get_ports "PS_PORB"]
set_property slew "slow" [get_ports "PS_PORB"]
set_property drive "8" [get_ports "PS_PORB"]
set_property PIO_DIRECTION "INPUT" [get_ports "PS_PORB"]
set_property iostandard "LVCMOS33" [get_ports "PS_SRSTB"]
set_property PACKAGE_PIN "B10" [get_ports "PS_SRSTB"]
set_property slew "slow" [get_ports "PS_SRSTB"]
set_property drive "8" [get_ports "PS_SRSTB"]
set_property PIO_DIRECTION "INPUT" [get_ports "PS_SRSTB"]
set_property iostandard "LVCMOS33" [get_ports "PS_CLK"]
set_property PACKAGE_PIN "E7" [get_ports "PS_CLK"]
set_property slew "slow" [get_ports "PS_CLK"]
set_property drive "8" [get_ports "PS_CLK"]
set_property PIO_DIRECTION "INPUT" [get_ports "PS_CLK"]
quad/sytem/data/ps7_system_prj.xml 0 → 100644
View file @ f6378157
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE project PUBLIC "project" "project.dtd" >
<project version="1.0" >
<set param="PCW::UART0::PERIPHERAL::ENABLE" value="1" />
<set param="PCW::UART1::UART1::IO" value="MIO 48 .. 49" />
<set param="PCW::UART1::GRP_FULL::ENABLE" value="0" />
<set param="PCW::I2C0::I2C0::IO" value="MIO 10 .. 11" />
<set param="PCW::UART1::PERIPHERAL::ENABLE" value="1" />
<set param="PCW::SD0::PERIPHERAL::ENABLE" value="1" />
<set param="PCW::ENET0::PERIPHERAL::ENABLE" value="1" />
<set param="PCW::I2C0::PERIPHERAL::ENABLE" value="1" />
<set param="PCW::ENET0::GRP_MDIO::ENABLE" value="1" />
<set param="PCW::ENET0::ENET0::IO" value="MIO 16 .. 27" />
<set param="PCW::ENET0::RESET::ENABLE" value="0" />
<set param="PCW::ENET0::GRP_MDIO::IO" value="MIO 52 .. 53" />
<set param="PCW::SD0::GRP_CD::ENABLE" value="1" />
<set param="PCW::SD0::GRP_WP::ENABLE" value="1" />
<set param="PCW::SD0::GRP_POW::ENABLE" value="0" />
<set param="PCW::SD0::SD0::IO" value="MIO 40 .. 45" />
<set param="PCW::SD0::GRP_CD::IO" value="MIO 47" />
<set param="PCW::USB1::PERIPHERAL::ENABLE" value="0" />
<set param="PCW::QSPI::PERIPHERAL::ENABLE" value="1" />
<set param="PCW::QSPI::QSPI::IO" value="MIO 1 .. 6" />
<set param="PCW::TTC0::PERIPHERAL::ENABLE" value="0" />
<set param="PCW::USB0::PERIPHERAL::ENABLE" value="1" />
<set param="PCW::USB0::RESET::ENABLE" value="1" />
<set param="PCW::USB0::RESET::IO" value="MIO 46" />
<set param="PCW::USB0::USB0::IO" value="MIO 28 .. 39" />
<set param="PCW::MIO::MIO[1]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[1]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[1]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[2]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[2]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[2]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[3]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[3]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[3]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[4]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[4]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[4]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[5]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[5]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[5]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[6]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[6]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[6]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[7]::SLEW" value="slow" />
<set param="PCW::MIO::MIO[7]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[7]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[8]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[8]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[8]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[9]::SLEW" value="slow" />
<set param="PCW::MIO::MIO[9]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[9]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[10]::SLEW" value="slow" />
<set param="PCW::MIO::MIO[10]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[10]::PULLUP" value="enabled" />
<set param="PCW::MIO::MIO[11]::SLEW" value="slow" />
<set param="PCW::MIO::MIO[11]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[11]::PULLUP" value="enabled" />
<set param="PCW::MIO::MIO[12]::SLEW" value="slow" />
<set param="PCW::MIO::MIO[12]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[12]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[13]::SLEW" value="slow" />
<set param="PCW::MIO::MIO[13]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[13]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[14]::SLEW" value="slow" />
<set param="PCW::MIO::MIO[14]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[14]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[15]::SLEW" value="slow" />
<set param="PCW::MIO::MIO[15]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[15]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[16]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[16]::IOTYPE" value="HSTL 1.8V" />
<set param="PCW::MIO::MIO[16]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[17]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[17]::IOTYPE" value="HSTL 1.8V" />
<set param="PCW::MIO::MIO[17]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[18]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[18]::IOTYPE" value="HSTL 1.8V" />
<set param="PCW::MIO::MIO[18]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[19]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[19]::IOTYPE" value="HSTL 1.8V" />
<set param="PCW::MIO::MIO[19]::PULLUP" value="disabled" />
<set param="PCW::PJTAG::PERIPHERAL::ENABLE" value="0" />
<set param="PCW::MIO::MIO[0]::SLEW" value="slow" />
<set param="PCW::MIO::MIO[0]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[0]::PULLUP" value="disabled" />
<set param="PCW::UIPARAM::DDR::BL" value="8" />
<set param="PCW::UIPARAM::DDR::DQS_TO_CLK_DELAY_1" value="-0.034" />
<set param="PCW::UIPARAM::DDR::DQS_TO_CLK_DELAY_2" value="-0.03" />
<set param="PCW::UIPARAM::DDR::DQS_TO_CLK_DELAY_3" value="-0.082" />
<set param="PCW::UIPARAM::DDR::PARTNO" value="MT41K128M16 JT-125" />
<set param="PCW::UIPARAM::DDR::MEMORY_TYPE" value="DDR 3" />
<set param="PCW:GPIO::EMIO_GPIO::WIDTH" value="64" />
<set param="PCW::GPIO::V2.00.A::C_EN_EMIO_GPIO" value="0" />
<set param="PCW::UART::PERIPHERAL::FREQMHZ" value="50" />
<set param="PCW::CAN::PERIPHERAL::FREQMHZ" value="100" />
<set param="PCW::PRESET::FPGA::PARTNUMBER" value="xc7z010clg400-1" />
<set param="PCW::PRESET::FPGA::SPEED" value="-1" />
<set param="PCW::PRESET::BANK0::VOLTAGE" value="LVCMOS 3.3V" />
<set param="PCW::PRESET::BANK1::VOLTAGE" value="LVCMOS 1.8V" />
<set param="PCW::GPIO::PERIPHERAL::ENABLE" value="1" />
<set param="PCW::GPIO::GPIO::IO" value="MIO" />
<set param="PCW::CRYSTAL::PERIPHERAL::FREQMHZ" value="50.000000" />
<set param="PCW::APU::PERIPHERAL::FREQMHZ" value="650.000000" />
<set param="PCW::APU::CLK_RATIO::ENABLE" value="6:2:1" />
<set param="PCW::FPGA0::PERIPHERAL::FREQMHZ" value="100.000000" />
<set param="PCW::FPGA1::PERIPHERAL::FREQMHZ" value="175.000000" />
<set param="PCW::FPGA2::PERIPHERAL::FREQMHZ" value="12.288000" />
<set param="PCW::FPGA3::PERIPHERAL::FREQMHZ" value="100.000000" />
<set param="PCW::QSPI::PERIPHERAL::FREQMHZ" value="200.000000" />
<set param="PCW::ENET0::PERIPHERAL::FREQMHZ" value="1000 Mbps" />
<set param="PCW::SDIO::PERIPHERAL::FREQMHZ" value="50" />
<set param="PCW::UIPARAM::DDR::DRAM_WIDTH" value="16 Bits" />
<set param="PCW::PRESET::GLOBAL::CONFIG" value="Default" />
<set param="PCW::PRESET::GLOBAL::DEFAULT" value="powerup" />
<set param="PCW::UIPARAM::DDR::DEVICE_CAPACITY" value="2048 MBits" />
<set param="PCW::UIPARAM::DDR::SPEED_BIN" value="DDR3_1066F" />
<set param="PCW::UIPARAM::DDR::FREQ_MHZ" value="525.000000" />
<set param="PCW::UIPARAM::DDR::ROW_ADDR_COUNT" value="14" />
<set param="PCW::UIPARAM::DDR::CL" value="7" />
<set param="PCW::UIPARAM::DDR::CWL" value="6" />
<set param="PCW::UIPARAM::DDR::T_RCD" value="7" />
<set param="PCW::UIPARAM::DDR::T_RP" value="7" />
<set param="PCW::UIPARAM::DDR::T_RC" value="48.75" />
<set param="PCW::UIPARAM::DDR::T_RAS_MIN" value="35.0" />
<set param="PCW::UIPARAM::DDR::T_FAW" value="40.0" />
<set param="PCW::UIPARAM::DDR::DQS_TO_CLK_DELAY_0" value="-0.073" />
<set param="PCW::MIO::MIO[20]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[20]::IOTYPE" value="HSTL 1.8V" />
<set param="PCW::MIO::MIO[20]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[21]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[21]::IOTYPE" value="HSTL 1.8V" />
<set param="PCW::MIO::MIO[21]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[22]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[22]::IOTYPE" value="HSTL 1.8V" />
<set param="PCW::MIO::MIO[22]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[23]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[23]::IOTYPE" value="HSTL 1.8V" />
<set param="PCW::FCLK1::PERIPHERAL::CLKSRC" value="DDR PLL" />
<set param="PCW::FCLK2::PERIPHERAL::CLKSRC" value="ARM PLL" />
<set param="PCW::ENET0::PERIPHERAL::CLKSRC" value="IO PLL" />
<set param="PCW::MIO::MIO[23]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[24]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[24]::IOTYPE" value="HSTL 1.8V" />
<set param="PCW::MIO::MIO[24]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[25]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[25]::IOTYPE" value="HSTL 1.8V" />
<set param="PCW::MIO::MIO[25]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[26]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[26]::IOTYPE" value="HSTL 1.8V" />
<set param="PCW::MIO::MIO[26]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[27]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[27]::IOTYPE" value="HSTL 1.8V" />
<set param="PCW::MIO::MIO[27]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[28]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[28]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[28]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[29]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[29]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[29]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[30]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[30]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[30]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[31]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[31]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[31]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[32]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[32]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[32]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[33]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[33]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[33]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[34]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[34]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[34]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[35]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[35]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[35]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[36]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[36]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[36]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[37]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[37]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[37]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[38]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[38]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[38]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[39]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[39]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[39]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[40]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[40]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[40]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[41]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[41]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[41]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[42]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[42]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[42]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[43]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[43]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[43]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[44]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[44]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[44]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[45]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[45]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[45]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[46]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[46]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[47]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[47]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[48]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[48]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[49]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[49]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[50]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[50]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[50]::DIRECTION" value="in" />
<set param="PCW::MIO::MIO[51]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[51]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[51]::DIRECTION" value="in" />
<set param="PCW::MIO::MIO[52]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[52]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[53]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[53]::PULLUP" value="disabled" />
<set param="PCW::UIPARAM::DDR::TRAIN_WRITE_LEVEL" value="1" />
<set param="PCW::UIPARAM::DDR::TRAIN_READ_GATE" value="1" />
<set param="PCW::UIPARAM::DDR::TRAIN_DATA_EYE" value="1" />
<set param="PCW::UIPARAM::DDR::USE_INTERNAL_VREF" value="0" />
<set param="PCW::UIPARAM::DDR::BOARD_DELAY0" value="0.176" />
<set param="PCW::UIPARAM::DDR::BOARD_DELAY1" value="0.159" />
<set param="PCW::UIPARAM::DDR::BOARD_DELAY2" value="0.162" />
<set param="PCW::UIPARAM::DDR::BOARD_DELAY3" value="0.187" />
<set param="PCW::DDR::V4.00.A::C_S_AXI_HP0_BASEADDR" value="0x00000000" />
<set param="PCW::DDR::V4.00.A::C_S_AXI_HP0_HIGHADDR" value="0x1FFFFFFF" />
<set param="PCW::DDR::V4.00.A::C_S_AXI_HP1_BASEADDR" value="0x00000000" />
<set param="PCW::DDR::V4.00.A::C_S_AXI_HP1_HIGHADDR" value="0x1FFFFFFF" />
<set param="PCW::DDR::V4.00.A::C_S_AXI_HP2_BASEADDR" value="0x00000000" />
<set param="PCW::DDR::V4.00.A::C_S_AXI_HP2_HIGHADDR" value="0x1FFFFFFF" />
<set param="PCW::DDR::V4.00.A::C_S_AXI_HP3_BASEADDR" value="0x00000000" />
<set param="PCW::DDR::V4.00.A::C_S_AXI_HP3_HIGHADDR" value="0x1FFFFFFF" />
<set param="PCW::UIPARAM::DDR::DQS_0_LENGTH_MM" value="27.85" />
<set param="PCW::UIPARAM::DDR::DQS_1_LENGTH_MM" value="22.87" />
<set param="PCW::UIPARAM::DDR::DQS_2_LENGTH_MM" value="22.9" />
<set param="PCW::UIPARAM::DDR::DQS_3_LENGTH_MM" value="29.9" />
<set param="PCW::UIPARAM::DDR::DQ_0_LENGTH_MM" value="27" />
<set param="PCW::UIPARAM::DDR::DQ_1_LENGTH_MM" value="22.8" />
<set param="PCW::UIPARAM::DDR::DQ_2_LENGTH_MM" value="24" />
<set param="PCW::UIPARAM::DDR::DQ_3_LENGTH_MM" value="30.45" />
<set param="PCW::UIPARAM::DDR::CLOCK_0_LENGTH_MM" value="20.6" />
<set param="PCW::UIPARAM::DDR::CLOCK_1_LENGTH_MM" value="20.6" />
<set param="PCW::UIPARAM::DDR::CLOCK_2_LENGTH_MM" value="20.6" />
<set param="PCW::UIPARAM::DDR::CLOCK_3_LENGTH_MM" value="20.6" />
<set param="PCW::UIPARAM::DDR::DQS_0_PROPOGATION_DELAY" value="180" />
<set param="PCW::UIPARAM::DDR::DQS_1_PROPOGATION_DELAY" value="180" />
<set param="PCW::UIPARAM::DDR::DQS_2_PROPOGATION_DELAY" value="180" />
<set param="PCW::UIPARAM::DDR::DQS_3_PROPOGATION_DELAY" value="180" />
<set param="PCW::UIPARAM::DDR::DQ_0_PROPOGATION_DELAY" value="180" />
<set param="PCW::UIPARAM::DDR::DQ_1_PROPOGATION_DELAY" value="180" />
<set param="PCW::UIPARAM::DDR::DQ_2_PROPOGATION_DELAY" value="180" />
<set param="PCW::UIPARAM::DDR::DQ_3_PROPOGATION_DELAY" value="180" />
<set param="PCW::UIPARAM::DDR::CLOCK_0_PROPOGATION_DELAY" value="165" />
<set param="PCW::UIPARAM::DDR::CLOCK_1_PROPOGATION_DELAY" value="165" />
<set param="PCW::UIPARAM::DDR::CLOCK_2_PROPOGATION_DELAY" value="165" />
<set param="PCW::UIPARAM::DDR::CLOCK_3_PROPOGATION_DELAY" value="165" />
</project>
quad/sytem/data/system.ucf 0 → 100644
View file @ f6378157
NET pwm_recorder_0_pwm_in_master_pin LOC = "V12" | IOSTANDARD = "LVCMOS33"; #JE1
NET pwm_recorder_1_pwm_in_master_pin LOC = "W16" | IOSTANDARD = "LVCMOS33"; #JE2
NET pwm_recorder_2_pwm_in_master_pin LOC = "J15" | IOSTANDARD = "LVCMOS33"; #JE3
NET pwm_recorder_3_pwm_in_master_pin LOC = "H15" | IOSTANDARD = "LVCMOS33"; #JE4
NET pwm_recorder_4_pwm_in_master_pin LOC = "U14" | IOSTANDARD = "LVCMOS33"; #JD7
NET pwm_recorder_5_pwm_in_master_pin LOC = "U15" | IOSTANDARD = "LVCMOS33"; #JD8
NET pwm_signal_out_wkillswitch_0_pwm_out_sm_pin LOC = "V13" | IOSTANDARD = "LVCMOS33"; #JE7
NET pwm_signal_out_wkillswitch_1_pwm_out_sm_pin LOC = "U17" | IOSTANDARD = "LVCMOS33"; #JE8
NET pwm_signal_out_wkillswitch_2_pwm_out_sm_pin LOC = "T17" | IOSTANDARD = "LVCMOS33"; #JE9
NET pwm_signal_out_wkillswitch_3_pwm_out_sm_pin LOC = "Y17" | IOSTANDARD = "LVCMOS33"; #JE10
#
# pin constraints
#
NET BTNs_4Bits_TRI_IO_GPIO_IO_I_pin[0] LOC = "R18" | IOSTANDARD = "LVCMOS33";
NET BTNs_4Bits_TRI_IO_GPIO_IO_I_pin[1] LOC = "P16" | IOSTANDARD = "LVCMOS33";
NET BTNs_4Bits_TRI_IO_GPIO_IO_I_pin[2] LOC = "V16" | IOSTANDARD = "LVCMOS33";
NET BTNs_4Bits_TRI_IO_GPIO_IO_I_pin[3] LOC = "Y16" | IOSTANDARD = "LVCMOS33";
#UART STUFF:
NET "processing_system7_0_UART0_TX_pin" LOC=W15 | IOSTANDARD=LVCMOS33; #IO_L22P_T3_AD7P_35 #JC2
NET "processing_system7_0_UART0_RX_pin" LOC=T11 | IOSTANDARD=LVCMOS33; #IO_L24P_T3_AD15P_35 #JC3
\ No newline at end of file
quad/sytem/etc/bitgen.ut 0 → 100644
View file @ f6378157
##bitgen options for zynq architecture
quad/sytem/etc/download.cmd 0 → 100644
View file @ f6378157
quad/sytem/etc/fast_runtime.opt 0 → 100644
View file @ f6378157
FLOWTYPE = FPGA;
###############################################################
## Filename: fast_runtime.opt
##
## Option File For Xilinx FPGA Implementation Flow for Fast
## Runtime.
##
## Version: 4.1.1
###############################################################
#
# Options for Translator
#
# Type "ngdbuild -h" for a detailed list of ngdbuild command line options
#
Program ngdbuild
-p <partname>; # Partname to use - picked from xflow commandline
-nt timestamp; # NGO File generation. Regenerate only when
# source netlist is newer than existing
# NGO file (default)
-bm <design>.bmm # Block RAM memory map file
<userdesign>; # User design - pick from xflow command line
-uc <design>.ucf; # ucf constraints
<design>.ngd; # Name of NGD file. Filebase same as design filebase
End Program ngdbuild
#
# Options for Mapper
#
# Type "map -h <arch>" for a detailed list of map command line options
#
Program map
-o <design>_map.ncd; # Output Mapped ncd file
-w; # Overwrite output files.
-pr b; # Pack internal FF/latches into IOBs
#-fp <design>.mfp; # Floorplan file
-ol high;
-timing;
-detail;
<inputdir><design>.ngd; # Input NGD file
<inputdir><design>.pcf; # Physical constraints file
END Program map
#
# Options for Post Map Trace
#
# Type "trce -h" for a detailed list of trce command line options
#
Program post_map_trce
-e 3; # Produce error report limited to 3 items per constraint
#-o <design>_map.twr; # Output trace report file
-xml <design>_map.twx; # Output XML version of the timing report
#-tsi <design>_map.tsi; # Produce Timing Specification Interaction report
<inputdir><design>_map.ncd; # Input mapped ncd
<inputdir><design>.pcf; # Physical constraints file
END Program post_map_trce
#
# Options for Place and Route
#
# Type "par -h" for a detailed list of par command line options
#
Program par
-w; # Overwrite existing placed and routed ncd
-ol high; # Overall effort level
<inputdir><design>_map.ncd; # Input mapped NCD file
<design>.ncd; # Output placed and routed NCD
<inputdir><design>.pcf; # Input physical constraints file
END Program par
#
# Options for Post Par Trace
#
# Type "trce -h" for a detailed list of trce command line options
#
Program post_par_trce
-e 3; # Produce error report limited to 3 items per constraint
#-o <design>.twr; # Output trace report file
-xml <design>.twx; # Output XML version of the timing report
#-tsi <design>.tsi; # Produce Timing Specification Interaction report
<inputdir><design>.ncd; # Input placed and routed ncd
<inputdir><design>.pcf; # Physical constraints file
END Program post_par_trce
quad/sytem/etc/system.filters 0 → 100644
View file @ f6378157
<FILTERS>
<IDENTIFICATION VERSION="1.2" XTLVERSION="1.2"/>
<SET CLASS="PROJECT" VIEW_ID="BUSINTERFACE">
<HEADERS HSCROLL="0" VSCROLL="0">
<VARIABLE COL_INDEX="0" COL_WIDTH="208" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="HEADER"/>
</HEADERS>
<SET CLASS="FILTER_GROUP" ID="By Connection" IS_EXPANDED="TRUE">
<VARIABLE NAME="By Connection" VALUE="By Connection" VIEWDISP="Bus Interface Filters" VIEWTYPE="STATIC"/>
<SET CLASS="FILTER" ID="Connected" ROW_INDEX="0">
<VARIABLE IS_LABELED="TRUE" NAME="Connected" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Unconnected" ROW_INDEX="1">
<VARIABLE IS_LABELED="TRUE" NAME="Unconnected" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
</SET>
<SET CLASS="FILTER_GROUP" ID="By Bus Standard" IS_EXPANDED="TRUE">
<VARIABLE COL_INDEX="0" NAME="By Bus Standard" VALUE="By Bus Standard" VIEWDISP="Bus Interface Filters" VIEWTYPE="STATIC"/>
<SET CLASS="FILTER" ID="AXI" ROW_INDEX="0">
<VARIABLE IS_LABELED="TRUE" NAME="AXI" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="AXIS" IS_VISIBLE="FALSE" ROW_INDEX="1">
<VARIABLE IS_LABELED="TRUE" NAME="AXIS" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="OPB" IS_VISIBLE="FALSE" ROW_INDEX="2">
<VARIABLE IS_LABELED="TRUE" NAME="OPB" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="LMB" IS_VISIBLE="FALSE" ROW_INDEX="3">
<VARIABLE IS_LABELED="TRUE" NAME="LMB" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="PLBV34" IS_VISIBLE="FALSE" ROW_INDEX="4">
<VARIABLE IS_LABELED="TRUE" NAME="PLBV34" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="PLBV46" IS_VISIBLE="FALSE" ROW_INDEX="5">
<VARIABLE IS_LABELED="TRUE" NAME="PLBV46" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="OCM" IS_VISIBLE="FALSE" ROW_INDEX="6">
<VARIABLE IS_LABELED="TRUE" NAME="OCM" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="FSL" IS_VISIBLE="FALSE" ROW_INDEX="7">
<VARIABLE IS_LABELED="TRUE" NAME="FSL" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="DCR" IS_VISIBLE="FALSE" ROW_INDEX="8">
<VARIABLE IS_LABELED="TRUE" NAME="DCR" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="FCB" IS_VISIBLE="FALSE" ROW_INDEX="9">
<VARIABLE IS_LABELED="TRUE" NAME="FCB" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="XIL" IS_VISIBLE="FALSE" ROW_INDEX="10">
<VARIABLE IS_LABELED="TRUE" NAME="Xilinx Point To Point" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="USER" IS_VISIBLE="FALSE" ROW_INDEX="11">
<VARIABLE IS_LABELED="TRUE" NAME="User Defined" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="XCL" IS_VISIBLE="FALSE" ROW_INDEX="12">
<VARIABLE IS_LABELED="TRUE" NAME="XCL" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
</SET>
<SET CLASS="FILTER_GROUP" ID="By Interface Type" IS_EXPANDED="TRUE">
<VARIABLE NAME="By Interface Type" VALUE="By Interface Type" VIEWDISP="Bus Interface Filters" VIEWTYPE="STATIC"/>
<SET CLASS="FILTER" ID="Slaves" ROW_INDEX="0">
<VARIABLE IS_LABELED="TRUE" NAME="Slaves" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Masters" ROW_INDEX="1">
<VARIABLE IS_LABELED="TRUE" NAME="Masters" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Master Slaves" ROW_INDEX="2">
<VARIABLE IS_LABELED="TRUE" NAME="Master Slaves" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Monitors" ROW_INDEX="3">
<VARIABLE IS_LABELED="TRUE" NAME="Monitors" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Targets" ROW_INDEX="4">
<VARIABLE IS_LABELED="TRUE" NAME="Targets" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Initiators" ROW_INDEX="5">
<VARIABLE IS_LABELED="TRUE" NAME="Initiators" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
</SET>
</SET>
<SET CLASS="PROJECT" VIEW_ID="PORT">
<HEADERS HSCROLL="0" VSCROLL="0">
<VARIABLE COL_INDEX="0" COL_WIDTH="213" IS_VISIBLE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="HEADER"/>
</HEADERS>
<SET CLASS="FILTER_GROUP" ID="By Interface" IS_EXPANDED="TRUE">
<VARIABLE NAME="By Interface" VALUE="By Interface" VIEWDISP="Port Filters" VIEWTYPE="STATIC"/>
<SET CLASS="FILTER" ID="BUS" ROW_INDEX="0">
<VARIABLE IS_LABELED="TRUE" NAME="BUS" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="IO" ROW_INDEX="1">
<VARIABLE IS_LABELED="TRUE" NAME="IO" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
</SET>
<SET CLASS="FILTER_GROUP" ID="By Connection" IS_EXPANDED="TRUE">
<VARIABLE NAME="By Connection" VALUE="By Connection" VIEWDISP="Port Filters" VIEWTYPE="STATIC"/>
<SET CLASS="FILTER" ID="Defaults" ROW_INDEX="0">
<VARIABLE IS_LABELED="TRUE" NAME="Defaults" VALUE="FALSE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Connected" ROW_INDEX="1">
<VARIABLE IS_LABELED="TRUE" NAME="Connected" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Unconnected" ROW_INDEX="2">
<VARIABLE IS_LABELED="TRUE" NAME="Unconnected" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
</SET>
<SET CLASS="FILTER_GROUP" ID="By Class" IS_EXPANDED="TRUE">
<VARIABLE COL_INDEX="0" NAME="By Class" VALUE="By Class" VIEWDISP="Port Filters" VIEWTYPE="STATIC"/>
<SET CLASS="FILTER" ID="Clocks Only" ROW_INDEX="0">
<VARIABLE NAME="Clocks Only" VALUE="Clocks Only" VIEWDISP="Port Filters" VIEWTYPE="BUTTON"/>
</SET>
<SET CLASS="FILTER" ID="Clocks" ROW_INDEX="1">
<VARIABLE IS_LABELED="TRUE" NAME="Clocks" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Resets Only" ROW_INDEX="2">
<VARIABLE NAME="Resets Only" VALUE="Resets Only" VIEWDISP="Port Filters" VIEWTYPE="BUTTON"/>
</SET>
<SET CLASS="FILTER" ID="Resets" ROW_INDEX="3">
<VARIABLE IS_LABELED="TRUE" NAME="Resets" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Interrupts Only" ROW_INDEX="4">
<VARIABLE NAME="Interrupts Only" VALUE="Interrupts Only" VIEWDISP="Port Filters" VIEWTYPE="BUTTON"/>
</SET>
<SET CLASS="FILTER" ID="Interrupts" ROW_INDEX="5">
<VARIABLE IS_LABELED="TRUE" NAME="Interrupts" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Others" ROW_INDEX="6">
<VARIABLE IS_LABELED="TRUE" NAME="Others" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
</SET>
<SET CLASS="FILTER_GROUP" ID="By Direction" IS_EXPANDED="TRUE">
<VARIABLE NAME="By Direction" VALUE="By Direction" VIEWDISP="Port Filters" VIEWTYPE="STATIC"/>
<SET CLASS="FILTER" ID="Inputs" ROW_INDEX="0">
<VARIABLE IS_LABELED="TRUE" NAME="Inputs" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Outputs" ROW_INDEX="1">
<VARIABLE IS_LABELED="TRUE" NAME="Outputs" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="InOuts" ROW_INDEX="2">
<VARIABLE IS_LABELED="TRUE" NAME="InOuts" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
</SET>
</SET>
</FILTERS>
\ No newline at end of file
quad/sytem/etc/system.gui 0 → 100644
View file @ f6378157
<SETTINGS>
<IDENTIFICATION VERSION="1.2" XTLVERSION="1.2"/>
<SET CLASS="PROJECT" DISPLAYMODE="TREE" VIEW_ID="BUSINTERFACE">
<HEADERS HSCROLL="0" VSCROLL="0">
<VARIABLE COL_INDEX="0" COL_WIDTH="290" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" COL_WIDTH="981" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" IS_VISIBLE="FALSE" VIEWDISP="Bus Standard" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" COL_WIDTH="981" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" IS_VISIBLE="FALSE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="FALSE" VIEWDISP="Type" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="-1" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="75,962,200" VERSION="0"/>
<STATUS>
<SELECTIONS/>
</STATUS>
<SEQUENCES IS_DEF_SEQUENCES="TRUE">
<VARIABLE ID="clock_generator_0" ROW_INDEX="14"/>
<VARIABLE ID="reset_0" ROW_INDEX="15"/>
<VARIABLE ID="processing_system7_0" ROW_INDEX="1"/>
<VARIABLE ID="pwm_recorder_0" ROW_INDEX="4"/>
<VARIABLE ID="axi_interconnect_1" ROW_INDEX="0"/>
<VARIABLE ID="pwm_recorder_1" ROW_INDEX="5"/>
<VARIABLE ID="pwm_recorder_2" ROW_INDEX="6"/>
<VARIABLE ID="pwm_recorder_3" ROW_INDEX="7"/>
<VARIABLE ID="pwm_recorder_4" ROW_INDEX="8"/>
<VARIABLE ID="pwm_recorder_5" ROW_INDEX="9"/>
<VARIABLE ID="BTNs_4Bits_TRI_IO" ROW_INDEX="2"/>
<VARIABLE ID="pwm_signal_out_wkillswitch_0" ROW_INDEX="10"/>
<VARIABLE ID="pwm_signal_out_wkillswitch_1" ROW_INDEX="11"/>
<VARIABLE ID="pwm_signal_out_wkillswitch_2" ROW_INDEX="12"/>
<VARIABLE ID="pwm_signal_out_wkillswitch_3" ROW_INDEX="13"/>
<VARIABLE ID="axi_timer_0" ROW_INDEX="3"/>
</SEQUENCES>
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="FOCUS_TREE" VIEW_ID="BUSINTERFACE">
<HEADERS>
<VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" IS_VISIBLE="FALSE" VIEWDISP="Bus Standard" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" IS_VISIBLE="FALSE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="FALSE" VIEWDISP="Type" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="180,450,180" VERSION="0"/>
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="FLAT" VIEW_ID="BUSINTERFACE">
<HEADERS>
<VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Instance" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" IS_VISIBLE="FALSE" VIEWDISP="Bus Standard" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="FALSE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" IS_VISIBLE="FALSE" VIEWDISP="Type" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="180,450,180" VERSION="0"/>
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="FOCUS_FLAT" VIEW_ID="BUSINTERFACE">
<HEADERS>
<VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Instance" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" IS_VISIBLE="FALSE" VIEWDISP="Bus Standard" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="FALSE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" IS_VISIBLE="FALSE" VIEWDISP="Type" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="180,450,180" VERSION="0"/>
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="TREE" VIEW_ID="PORT">
<HEADERS HSCROLL="0" VSCROLL="353">
<VARIABLE COL_INDEX="0" COL_WIDTH="258" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" COL_WIDTH="400" IS_VISIBLE="TRUE" VIEWDISP="Connected Port" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" IS_VISIBLE="FALSE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Range" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Frequency(Hz)" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Reset Polarity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="8" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="9" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="10" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="11" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="11" COL_WIDTH="103" IS_VISIBLE="TRUE" VIEWDISP="Differential Polarity" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="-1" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="75,962,200" VERSION="0"/>
<SET ID="processing_system7_0" IS_EXPANDED="TRUE"/>
<STATUS>
<SELECTIONS>
<VARIABLE ID="IRQ_P2F_UART0" PARENT="processing_system7_0"/>
</SELECTIONS>
</STATUS>
<SEQUENCES IS_DEF_SEQUENCES="TRUE">
<VARIABLE ID="ExternalPorts" ROW_INDEX="0"/>
<VARIABLE ID="clock_generator_0" ROW_INDEX="15"/>
<VARIABLE ID="reset_0" ROW_INDEX="16"/>
<VARIABLE ID="processing_system7_0" IS_EXPANDED="TRUE" ROW_INDEX="2"/>
<VARIABLE ID="pwm_recorder_0" ROW_INDEX="5"/>
<VARIABLE ID="axi_interconnect_1" ROW_INDEX="1"/>
<VARIABLE ID="pwm_recorder_1" ROW_INDEX="6"/>
<VARIABLE ID="pwm_recorder_2" ROW_INDEX="7"/>
<VARIABLE ID="pwm_recorder_3" ROW_INDEX="8"/>
<VARIABLE ID="pwm_recorder_4" ROW_INDEX="9"/>
<VARIABLE ID="pwm_recorder_5" ROW_INDEX="10"/>
<VARIABLE ID="BTNs_4Bits_TRI_IO" ROW_INDEX="3"/>
<VARIABLE ID="pwm_signal_out_wkillswitch_0" ROW_INDEX="11"/>
<VARIABLE ID="pwm_signal_out_wkillswitch_1" ROW_INDEX="12"/>
<VARIABLE ID="pwm_signal_out_wkillswitch_2" ROW_INDEX="13"/>
<VARIABLE ID="pwm_signal_out_wkillswitch_3" ROW_INDEX="14"/>
<VARIABLE ID="axi_timer_0" ROW_INDEX="4"/>
</SEQUENCES>
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="FOCUS_TREE" VIEW_ID="PORT">
<HEADERS>
<VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Connected Port" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" IS_VISIBLE="FALSE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="Range" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="TRUE" VIEWDISP="Frequency(Hz)" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" IS_VISIBLE="TRUE" VIEWDISP="Reset Polarity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="8" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="9" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="10" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="11" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,630,180" VERSION="0"/>
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="FLAT" VIEW_ID="PORT">
<HEADERS>
<VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Instance" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Port Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="Range" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="TRUE" VIEWDISP="Frequency(Hz)" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" IS_VISIBLE="TRUE" VIEWDISP="Reset Polarity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="8" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="9" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="10" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="11" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,630,180" VERSION="0"/>
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="FOCUS_FLAT" VIEW_ID="PORT">
<HEADERS>
<VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Instance" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Port Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="Range" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="TRUE" VIEWDISP="Frequency(Hz)" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" IS_VISIBLE="TRUE" VIEWDISP="Reset Polarity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="8" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="9" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="10" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="11" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,630,180" VERSION="0"/>
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="TREE" VIEW_ID="ADDRESS">
<HEADERS HSCROLL="0" VSCROLL="0">
<VARIABLE COL_INDEX="0" COL_WIDTH="200" IS_VISIBLE="TRUE" VIEWDISP="Instance" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Base Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Base Address" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="High Address" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Size" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" COL_WIDTH="105" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface(s)" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" IS_VISIBLE="FALSE" VIEWDISP="ICache" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="8" IS_VISIBLE="FALSE" VIEWDISP="DCache" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="8" IS_VISIBLE="FALSE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="10" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" IS_VISIBLE="FALSE" VIEWDISP="Address Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="9" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Lock" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="-1" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="75,962,200" VERSION="0"/>
<STATUS>
<SELECTIONS>
<VARIABLE ID="axi_gpio_0"/>
</SELECTIONS>
</STATUS>
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="FLAT" VIEW_ID="ADDRESS">
<HEADERS>
<VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Instance" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Base Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" IS_VISIBLE="TRUE" VIEWDISP="Base Address" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" IS_VISIBLE="TRUE" VIEWDISP="High Address" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="Size" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface(s)" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" IS_VISIBLE="FALSE" VIEWDISP="ICache" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="8" IS_VISIBLE="FALSE" VIEWDISP="DCache" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="9" IS_VISIBLE="FALSE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="10" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="11" IS_VISIBLE="FALSE" VIEWDISP="Address Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="12" IS_VISIBLE="TRUE" VIEWDISP="Lock" VIEWTYPE="HEADER"/>
</HEADERS>
</SET>
</SETTINGS>
\ No newline at end of file
quad/sytem/hdl/elaborate/clock_generator_0_v4_03_a/hdl/vhdl/clock_generator.vhd 0 → 100644
View file @ f6378157
------------------------------------------------------------------------------
-- /local/ucart/microcart1630/tasks/Quad/system/hdl/elaborate/clock_generator_0_v4_03_a/hdl/vhdl/clock_generator.vhd
------------------------------------------------------------------------------
-- ClkGen Wrapper HDL file generated by ClkGen's TCL generator
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.vcomponents.all;
library clock_generator_v4_03_a;
use clock_generator_v4_03_a.all;
entity clock_generator is
generic (
C_FAMILY : string := "zynq" ;
C_DEVICE : string := "7z010";
C_PACKAGE : string := "clg400";
C_SPEEDGRADE : string := "-1";
C_CLK_GEN : string := "PASSED"
);
port (
-- clock generation
CLKIN : in std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUT6 : out std_logic;
CLKOUT7 : out std_logic;
CLKOUT8 : out std_logic;
CLKOUT9 : out std_logic;
CLKOUT10 : out std_logic;
CLKOUT11 : out std_logic;
CLKOUT12 : out std_logic;
CLKOUT13 : out std_logic;
CLKOUT14 : out std_logic;
CLKOUT15 : out std_logic;
-- external feedback
CLKFBIN : in std_logic;
CLKFBOUT : out std_logic;
-- variable phase shift
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSDONE : out std_logic;
-- reset
RST : in std_logic;
LOCKED : out std_logic
);
end clock_generator;
architecture STRUCTURE of clock_generator is
----------------------------------------------------------------------------
-- Functions
----------------------------------------------------------------------------
-- Note : The string functions are put here to remove dependency to other pcore level libraries
function UpperCase_Char(char : character) return character is
begin
-- If char is not an upper case letter then return char
if char < 'a' or char > 'z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'a' => return 'A'; when 'b' => return 'B'; when 'c' => return 'C'; when 'd' => return 'D';
when 'e' => return 'E'; when 'f' => return 'F'; when 'g' => return 'G'; when 'h' => return 'H';
when 'i' => return 'I'; when 'j' => return 'J'; when 'k' => return 'K'; when 'l' => return 'L';
when 'm' => return 'M'; when 'n' => return 'N'; when 'o' => return 'O'; when 'p' => return 'P';
when 'q' => return 'Q'; when 'r' => return 'R'; when 's' => return 'S'; when 't' => return 'T';
when 'u' => return 'U'; when 'v' => return 'V'; when 'w' => return 'W'; when 'x' => return 'X';
when 'y' => return 'Y'; when 'z' => return 'Z';
when others => return char;
end case;
end UpperCase_Char;
function UpperCase_String (s : string) return string is
variable res : string(s'range);
begin -- function LoweerCase_String
for I in s'range loop
res(I) := UpperCase_Char(s(I));
end loop; -- I
return res;
end function UpperCase_String;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function equalString( str1, str2 : string ) return boolean is
constant len1 : integer := str1'length;
constant len2 : integer := str2'length;
variable equal : boolean := true;
begin
if not (len1 = len2) then
equal := false;
else
for i in str1'range loop
if not (UpperCase_Char(str1(i)) = UpperCase_Char(str2(i))) then
equal := false;
end if;
end loop;
end if;
return equal;
end equalString;
----------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------
-- signals: gnd
signal net_gnd0 : std_logic;
signal net_gnd1 : std_logic_vector(0 to 0);
signal net_gnd16 : std_logic_vector(0 to 15);
-- signals: vdd
signal net_vdd0 : std_logic;
begin
----------------------------------------------------------------------------
-- GND and VCC signals
----------------------------------------------------------------------------
net_gnd0 <= '0';
net_gnd1(0 to 0) <= B"0";
net_gnd16(0 to 15) <= B"0000000000000000";
net_vdd0 <= '1';
----------------------------------------------------------------------------
-- DCM wrappers
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- PLL wrappers
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- MMCM wrappers
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- PLLE wrappers
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- DCMs CLKIN, CLKFB and RST signal connection
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- PLLs CLKIN1, CLKFBIN and RST signal connection
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- MMCMs CLKIN1, CLKFBIN, RST and Variable_Phase_Control signal connection
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- PLLEs CLKIN1, CLKFBIN, RST and Variable_Phase_Control signal connection
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- CLKGEN CLKOUT, CLKFBOUT and LOCKED signal connection
----------------------------------------------------------------------------
-- CLKGEN CLKOUT
CLKOUT0 <= '0';
CLKOUT1 <= '0';
CLKOUT2 <= '0';
CLKOUT3 <= '0';
CLKOUT4 <= '0';
CLKOUT5 <= '0';
CLKOUT6 <= '0';
CLKOUT7 <= '0';
CLKOUT8 <= '0';
CLKOUT9 <= '0';
CLKOUT10 <= '0';
CLKOUT11 <= '0';
CLKOUT12 <= '0';
CLKOUT13 <= '0';
CLKOUT14 <= '0';
CLKOUT15 <= '0';
-- CLKGEN CLKFBOUT
-- CLKGEN LOCKED
LOCKED <= net_gnd0;
end architecture STRUCTURE;
------------------------------------------------------------------------------
-- High level parameters
------------------------------------------------------------------------------
-- C_CLK_GEN = PASSED
-- C_ELABORATE_DIR =
-- C_ELABORATE_RES =
-- C_FAMILY = zynq
-- C_DEVICE = 7z010
-- C_PACKAGE = clg400
-- C_SPEEDGRADE = -1
----------------------------------------
-- C_EXTRA_MMCM_FOR_DESKEW =
-- C_MMCMExtra_CLKIN_FREQ =
-- C_MMCMExtra_CLKOUT0 =
-- C_MMCMExtra_CLKOUT1 =
-- C_MMCMExtra_CLKOUT2 =
-- C_MMCMExtra_CLKOUT3 =
-- C_MMCMExtra_CLKOUT4 =
-- C_MMCMExtra_CLKOUT5 =
-- C_MMCMExtra_CLKOUT6 =
-- C_MMCMExtra_CLKOUT7 =
-- C_MMCMExtra_CLKOUT8 =
-- C_MMCMExtra_CLKOUT9 =
-- C_MMCMExtra_CLKOUT10 =
-- C_MMCMExtra_CLKOUT11 =
-- C_MMCMExtra_CLKOUT12 =
-- C_MMCMExtra_CLKOUT13 =
-- C_MMCMExtra_CLKOUT14 =
-- C_MMCMExtra_CLKOUT15 =
-- C_MMCMExtra_CLKFBOUT_MULT =
-- C_MMCMExtra_DIVCLK_DIVIDE =
-- C_MMCMExtra_CLKOUT0_DIVIDE =
-- C_MMCMExtra_CLKOUT1_DIVIDE =
-- C_MMCMExtra_CLKOUT2_DIVIDE =
-- C_MMCMExtra_CLKOUT3_DIVIDE =
-- C_MMCMExtra_CLKOUT4_DIVIDE =
-- C_MMCMExtra_CLKOUT5_DIVIDE =
-- C_MMCMExtra_CLKOUT6_DIVIDE =
-- C_MMCMExtra_CLKOUT0_BUF =
-- C_MMCMExtra_CLKOUT1_BUF =
-- C_MMCMExtra_CLKOUT2_BUF =
-- C_MMCMExtra_CLKOUT3_BUF =
-- C_MMCMExtra_CLKOUT4_BUF =
-- C_MMCMExtra_CLKOUT5_BUF =
-- C_MMCMExtra_CLKOUT6_BUF =
-- C_MMCMExtra_CLKFBOUT_BUF =
-- C_MMCMExtra_CLKOUT0_PHASE =
-- C_MMCMExtra_CLKOUT1_PHASE =
-- C_MMCMExtra_CLKOUT2_PHASE =
-- C_MMCMExtra_CLKOUT3_PHASE =
-- C_MMCMExtra_CLKOUT4_PHASE =
-- C_MMCMExtra_CLKOUT5_PHASE =
-- C_MMCMExtra_CLKOUT6_PHASE =
----------------------------------------
-- C_CLKIN_FREQ = 0
-- C_CLKOUT0_FREQ = 0
-- C_CLKOUT0_PHASE = 0
-- C_CLKOUT0_GROUP = NONE
-- C_CLKOUT0_BUF = TRUE
-- C_CLKOUT0_VARIABLE_PHASE = FALSE
-- C_CLKOUT1_FREQ = 0
-- C_CLKOUT1_PHASE = 0
-- C_CLKOUT1_GROUP = NONE
-- C_CLKOUT1_BUF = TRUE
-- C_CLKOUT1_VARIABLE_PHASE = FALSE
-- C_CLKOUT2_FREQ = 0
-- C_CLKOUT2_PHASE = 0
-- C_CLKOUT2_GROUP = NONE
-- C_CLKOUT2_BUF = TRUE
-- C_CLKOUT2_VARIABLE_PHASE = FALSE
-- C_CLKOUT3_FREQ = 0
-- C_CLKOUT3_PHASE = 0
-- C_CLKOUT3_GROUP = NONE
-- C_CLKOUT3_BUF = TRUE
-- C_CLKOUT3_VARIABLE_PHASE = FALSE
-- C_CLKOUT4_FREQ = 0
-- C_CLKOUT4_PHASE = 0
-- C_CLKOUT4_GROUP = NONE
-- C_CLKOUT4_BUF = TRUE
-- C_CLKOUT4_VARIABLE_PHASE = FALSE
-- C_CLKOUT5_FREQ = 0
-- C_CLKOUT5_PHASE = 0
-- C_CLKOUT5_GROUP = NONE
-- C_CLKOUT5_BUF = TRUE
-- C_CLKOUT5_VARIABLE_PHASE = FALSE
-- C_CLKOUT6_FREQ = 0
-- C_CLKOUT6_PHASE = 0
-- C_CLKOUT6_GROUP = NONE
-- C_CLKOUT6_BUF = TRUE
-- C_CLKOUT6_VARIABLE_PHASE = FALSE
-- C_CLKOUT7_FREQ = 0
-- C_CLKOUT7_PHASE = 0
-- C_CLKOUT7_GROUP = NONE
-- C_CLKOUT7_BUF = TRUE
-- C_CLKOUT7_VARIABLE_PHASE = FALSE
-- C_CLKOUT8_FREQ = 0
-- C_CLKOUT8_PHASE = 0
-- C_CLKOUT8_GROUP = NONE
-- C_CLKOUT8_BUF = TRUE
-- C_CLKOUT8_VARIABLE_PHASE = FALSE
-- C_CLKOUT9_FREQ = 0
-- C_CLKOUT9_PHASE = 0
-- C_CLKOUT9_GROUP = NONE
-- C_CLKOUT9_BUF = TRUE
-- C_CLKOUT9_VARIABLE_PHASE = FALSE
-- C_CLKOUT10_FREQ = 0
-- C_CLKOUT10_PHASE = 0
-- C_CLKOUT10_GROUP = NONE
-- C_CLKOUT10_BUF = TRUE
-- C_CLKOUT10_VARIABLE_PHASE = FALSE
-- C_CLKOUT11_FREQ = 0
-- C_CLKOUT11_PHASE = 0
-- C_CLKOUT11_GROUP = NONE
-- C_CLKOUT11_BUF = TRUE
-- C_CLKOUT11_VARIABLE_PHASE = FALSE
-- C_CLKOUT12_FREQ = 0
-- C_CLKOUT12_PHASE = 0
-- C_CLKOUT12_GROUP = NONE
-- C_CLKOUT12_BUF = TRUE
-- C_CLKOUT12_VARIABLE_PHASE = FALSE
-- C_CLKOUT13_FREQ = 0
-- C_CLKOUT13_PHASE = 0
-- C_CLKOUT13_GROUP = NONE
-- C_CLKOUT13_BUF = TRUE
-- C_CLKOUT13_VARIABLE_PHASE = FALSE
-- C_CLKOUT14_FREQ = 0
-- C_CLKOUT14_PHASE = 0
-- C_CLKOUT14_GROUP = NONE
-- C_CLKOUT14_BUF = TRUE
-- C_CLKOUT14_VARIABLE_PHASE = FALSE
-- C_CLKOUT15_FREQ = 0
-- C_CLKOUT15_PHASE = 0
-- C_CLKOUT15_GROUP = NONE
-- C_CLKOUT15_BUF = TRUE
-- C_CLKOUT15_VARIABLE_PHASE = FALSE
----------------------------------------
-- C_CLKFBIN_FREQ = 0
-- C_CLKFBIN_DESKEW = NONE
-- C_CLKFBOUT_FREQ = 0
-- C_CLKFBOUT_GROUP = NONE
-- C_CLKFBOUT_BUF = TRUE
----------------------------------------
-- C_PSDONE_GROUP = NONE
------------------------------------------------------------------------------
-- Low level parameters
------------------------------------------------------------------------------
-- C_CLKOUT0_MODULE = NONE
-- C_CLKOUT0_PORT = NONE
-- C_CLKOUT1_MODULE = NONE
-- C_CLKOUT1_PORT = NONE
-- C_CLKOUT2_MODULE = NONE
-- C_CLKOUT2_PORT = NONE
-- C_CLKOUT3_MODULE = NONE
-- C_CLKOUT3_PORT = NONE
-- C_CLKOUT4_MODULE = NONE
-- C_CLKOUT4_PORT = NONE
-- C_CLKOUT5_MODULE = NONE
-- C_CLKOUT5_PORT = NONE
-- C_CLKOUT6_MODULE = NONE
-- C_CLKOUT6_PORT = NONE
-- C_CLKOUT7_MODULE = NONE
-- C_CLKOUT7_PORT = NONE
-- C_CLKOUT8_MODULE = NONE
-- C_CLKOUT8_PORT = NONE
-- C_CLKOUT9_MODULE = NONE
-- C_CLKOUT9_PORT = NONE
-- C_CLKOUT10_MODULE = NONE
-- C_CLKOUT10_PORT = NONE
-- C_CLKOUT11_MODULE = NONE
-- C_CLKOUT11_PORT = NONE
-- C_CLKOUT12_MODULE = NONE
-- C_CLKOUT12_PORT = NONE
-- C_CLKOUT13_MODULE = NONE
-- C_CLKOUT13_PORT = NONE
-- C_CLKOUT14_MODULE = NONE
-- C_CLKOUT14_PORT = NONE
-- C_CLKOUT15_MODULE = NONE
-- C_CLKOUT15_PORT = NONE
----------------------------------------
-- C_CLKFBOUT_MODULE = NONE
-- C_CLKFBOUT_PORT = NONE
-- C_CLKFBOUT_get_clkgen_dcm_default_params = NONE
----------------------------------------
-- C_PSDONE_MODULE = NONE
----------------------------------------
-- C_DCM0_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM0_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM0_DUTY_CYCLE_CORRECTION = true
-- C_DCM0_CLKIN_DIVIDE_BY_2 = false
-- C_DCM0_CLK_FEEDBACK = "1X"
-- C_DCM0_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM0_DSS_MODE = "NONE"
-- C_DCM0_STARTUP_WAIT = false
-- C_DCM0_PHASE_SHIFT = 0
-- C_DCM0_CLKFX_MULTIPLY = 4
-- C_DCM0_CLKFX_DIVIDE = 1
-- C_DCM0_CLKDV_DIVIDE = 2.0
-- C_DCM0_CLKIN_PERIOD = 41.6666666
-- C_DCM0_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM0_CLKIN_BUF = false
-- C_DCM0_CLKFB_BUF = false
-- C_DCM0_CLK0_BUF = false
-- C_DCM0_CLK90_BUF = false
-- C_DCM0_CLK180_BUF = false
-- C_DCM0_CLK270_BUF = false
-- C_DCM0_CLKDV_BUF = false
-- C_DCM0_CLK2X_BUF = false
-- C_DCM0_CLK2X180_BUF = false
-- C_DCM0_CLKFX_BUF = false
-- C_DCM0_CLKFX180_BUF = false
-- C_DCM0_EXT_RESET_HIGH = 1
-- C_DCM0_FAMILY = "spartan6"
-- C_DCM0_CLKIN_MODULE = NONE
-- C_DCM0_CLKIN_PORT = NONE
-- C_DCM0_CLKFB_MODULE = NONE
-- C_DCM0_CLKFB_PORT = NONE
-- C_DCM0_RST_MODULE = NONE
-- C_DCM1_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM1_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM1_DUTY_CYCLE_CORRECTION = true
-- C_DCM1_CLKIN_DIVIDE_BY_2 = false
-- C_DCM1_CLK_FEEDBACK = "1X"
-- C_DCM1_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM1_DSS_MODE = "NONE"
-- C_DCM1_STARTUP_WAIT = false
-- C_DCM1_PHASE_SHIFT = 0
-- C_DCM1_CLKFX_MULTIPLY = 4
-- C_DCM1_CLKFX_DIVIDE = 1
-- C_DCM1_CLKDV_DIVIDE = 2.0
-- C_DCM1_CLKIN_PERIOD = 41.6666666
-- C_DCM1_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM1_CLKIN_BUF = false
-- C_DCM1_CLKFB_BUF = false
-- C_DCM1_CLK0_BUF = false
-- C_DCM1_CLK90_BUF = false
-- C_DCM1_CLK180_BUF = false
-- C_DCM1_CLK270_BUF = false
-- C_DCM1_CLKDV_BUF = false
-- C_DCM1_CLK2X_BUF = false
-- C_DCM1_CLK2X180_BUF = false
-- C_DCM1_CLKFX_BUF = false
-- C_DCM1_CLKFX180_BUF = false
-- C_DCM1_EXT_RESET_HIGH = 1
-- C_DCM1_FAMILY = "spartan6"
-- C_DCM1_CLKIN_MODULE = NONE
-- C_DCM1_CLKIN_PORT = NONE
-- C_DCM1_CLKFB_MODULE = NONE
-- C_DCM1_CLKFB_PORT = NONE
-- C_DCM1_RST_MODULE = NONE
-- C_DCM2_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM2_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM2_DUTY_CYCLE_CORRECTION = true
-- C_DCM2_CLKIN_DIVIDE_BY_2 = false
-- C_DCM2_CLK_FEEDBACK = "1X"
-- C_DCM2_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM2_DSS_MODE = "NONE"
-- C_DCM2_STARTUP_WAIT = false
-- C_DCM2_PHASE_SHIFT = 0
-- C_DCM2_CLKFX_MULTIPLY = 4
-- C_DCM2_CLKFX_DIVIDE = 1
-- C_DCM2_CLKDV_DIVIDE = 2.0
-- C_DCM2_CLKIN_PERIOD = 41.6666666
-- C_DCM2_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM2_CLKIN_BUF = false
-- C_DCM2_CLKFB_BUF = false
-- C_DCM2_CLK0_BUF = false
-- C_DCM2_CLK90_BUF = false
-- C_DCM2_CLK180_BUF = false
-- C_DCM2_CLK270_BUF = false
-- C_DCM2_CLKDV_BUF = false
-- C_DCM2_CLK2X_BUF = false
-- C_DCM2_CLK2X180_BUF = false
-- C_DCM2_CLKFX_BUF = false
-- C_DCM2_CLKFX180_BUF = false
-- C_DCM2_EXT_RESET_HIGH = 1
-- C_DCM2_FAMILY = "spartan6"
-- C_DCM2_CLKIN_MODULE = NONE
-- C_DCM2_CLKIN_PORT = NONE
-- C_DCM2_CLKFB_MODULE = NONE
-- C_DCM2_CLKFB_PORT = NONE
-- C_DCM2_RST_MODULE = NONE
-- C_DCM3_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM3_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM3_DUTY_CYCLE_CORRECTION = true
-- C_DCM3_CLKIN_DIVIDE_BY_2 = false
-- C_DCM3_CLK_FEEDBACK = "1X"
-- C_DCM3_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM3_DSS_MODE = "NONE"
-- C_DCM3_STARTUP_WAIT = false
-- C_DCM3_PHASE_SHIFT = 0
-- C_DCM3_CLKFX_MULTIPLY = 4
-- C_DCM3_CLKFX_DIVIDE = 1
-- C_DCM3_CLKDV_DIVIDE = 2.0
-- C_DCM3_CLKIN_PERIOD = 41.6666666
-- C_DCM3_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM3_CLKIN_BUF = false
-- C_DCM3_CLKFB_BUF = false
-- C_DCM3_CLK0_BUF = false
-- C_DCM3_CLK90_BUF = false
-- C_DCM3_CLK180_BUF = false
-- C_DCM3_CLK270_BUF = false
-- C_DCM3_CLKDV_BUF = false
-- C_DCM3_CLK2X_BUF = false
-- C_DCM3_CLK2X180_BUF = false
-- C_DCM3_CLKFX_BUF = false
-- C_DCM3_CLKFX180_BUF = false
-- C_DCM3_EXT_RESET_HIGH = 1
-- C_DCM3_FAMILY = "spartan6"
-- C_DCM3_CLKIN_MODULE = NONE
-- C_DCM3_CLKIN_PORT = NONE
-- C_DCM3_CLKFB_MODULE = NONE
-- C_DCM3_CLKFB_PORT = NONE
-- C_DCM3_RST_MODULE = NONE
----------------------------------------
-- C_PLL0_BANDWIDTH = "OPTIMIZED"
-- C_PLL0_CLKFBOUT_MULT = 1
-- C_PLL0_CLKFBOUT_PHASE = 0.0
-- C_PLL0_CLKIN1_PERIOD = 0.000
-- C_PLL0_CLKOUT0_DIVIDE = 1
-- C_PLL0_CLKOUT0_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT0_PHASE = 0.0
-- C_PLL0_CLKOUT1_DIVIDE = 1
-- C_PLL0_CLKOUT1_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT1_PHASE = 0.0
-- C_PLL0_CLKOUT2_DIVIDE = 1
-- C_PLL0_CLKOUT2_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT2_PHASE = 0.0
-- C_PLL0_CLKOUT3_DIVIDE = 1
-- C_PLL0_CLKOUT3_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT3_PHASE = 0.0
-- C_PLL0_CLKOUT4_DIVIDE = 1
-- C_PLL0_CLKOUT4_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT4_PHASE = 0.0
-- C_PLL0_CLKOUT5_DIVIDE = 1
-- C_PLL0_CLKOUT5_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT5_PHASE = 0.0
-- C_PLL0_COMPENSATION = "SYSTEM_SYNCHRONOUS"
-- C_PLL0_DIVCLK_DIVIDE = 1
-- C_PLL0_REF_JITTER = 0.100
-- C_PLL0_RESET_ON_LOSS_OF_LOCK = false
-- C_PLL0_RST_DEASSERT_CLK = "CLKIN1"
-- C_PLL0_CLKOUT0_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT1_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT2_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT3_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT4_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT5_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKFBOUT_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKIN1_BUF = false
-- C_PLL0_CLKFBOUT_BUF = false
-- C_PLL0_CLKOUT0_BUF = false
-- C_PLL0_CLKOUT1_BUF = false
-- C_PLL0_CLKOUT2_BUF = false
-- C_PLL0_CLKOUT3_BUF = false
-- C_PLL0_CLKOUT4_BUF = false
-- C_PLL0_CLKOUT5_BUF = false
-- C_PLL0_EXT_RESET_HIGH = 1
-- C_PLL0_FAMILY = "spartan6"
-- C_PLL0_CLKIN1_MODULE = NONE
-- C_PLL0_CLKIN1_PORT = NONE
-- C_PLL0_CLKFBIN_MODULE = NONE
-- C_PLL0_CLKFBIN_PORT = NONE
-- C_PLL0_RST_MODULE = NONE
-- C_PLL1_BANDWIDTH = "OPTIMIZED"
-- C_PLL1_CLKFBOUT_MULT = 1
-- C_PLL1_CLKFBOUT_PHASE = 0.0
-- C_PLL1_CLKIN1_PERIOD = 0.000
-- C_PLL1_CLKOUT0_DIVIDE = 1
-- C_PLL1_CLKOUT0_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT0_PHASE = 0.0
-- C_PLL1_CLKOUT1_DIVIDE = 1
-- C_PLL1_CLKOUT1_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT1_PHASE = 0.0
-- C_PLL1_CLKOUT2_DIVIDE = 1
-- C_PLL1_CLKOUT2_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT2_PHASE = 0.0
-- C_PLL1_CLKOUT3_DIVIDE = 1
-- C_PLL1_CLKOUT3_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT3_PHASE = 0.0
-- C_PLL1_CLKOUT4_DIVIDE = 1
-- C_PLL1_CLKOUT4_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT4_PHASE = 0.0
-- C_PLL1_CLKOUT5_DIVIDE = 1
-- C_PLL1_CLKOUT5_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT5_PHASE = 0.0
-- C_PLL1_COMPENSATION = "SYSTEM_SYNCHRONOUS"
-- C_PLL1_DIVCLK_DIVIDE = 1
-- C_PLL1_REF_JITTER = 0.100
-- C_PLL1_RESET_ON_LOSS_OF_LOCK = false
-- C_PLL1_RST_DEASSERT_CLK = "CLKIN1"
-- C_PLL1_CLKOUT0_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT1_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT2_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT3_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT4_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT5_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKFBOUT_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKIN1_BUF = false
-- C_PLL1_CLKFBOUT_BUF = false
-- C_PLL1_CLKOUT0_BUF = false
-- C_PLL1_CLKOUT1_BUF = false
-- C_PLL1_CLKOUT2_BUF = false
-- C_PLL1_CLKOUT3_BUF = false
-- C_PLL1_CLKOUT4_BUF = false
-- C_PLL1_CLKOUT5_BUF = false
-- C_PLL1_EXT_RESET_HIGH = 1
-- C_PLL1_FAMILY = "spartan6"
-- C_PLL1_CLKIN1_MODULE = NONE
-- C_PLL1_CLKIN1_PORT = NONE
-- C_PLL1_CLKFBIN_MODULE = NONE
-- C_PLL1_CLKFBIN_PORT = NONE
-- C_PLL1_RST_MODULE = NONE
----------------------------------------
-- C_MMCM0_BANDWIDTH = "OPTIMIZED"
-- C_MMCM0_CLKFBOUT_MULT_F = 1.0
-- C_MMCM0_CLKFBOUT_PHASE = 0.0
-- C_MMCM0_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM0_CLKIN1_PERIOD = 0.000
-- C_MMCM0_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM0_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT0_PHASE = 0.0
-- C_MMCM0_CLKOUT1_DIVIDE = 1
-- C_MMCM0_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT1_PHASE = 0.0
-- C_MMCM0_CLKOUT2_DIVIDE = 1
-- C_MMCM0_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT2_PHASE = 0.0
-- C_MMCM0_CLKOUT3_DIVIDE = 1
-- C_MMCM0_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT3_PHASE = 0.0
-- C_MMCM0_CLKOUT4_DIVIDE = 1
-- C_MMCM0_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT4_PHASE = 0.0
-- C_MMCM0_CLKOUT4_CASCADE = false
-- C_MMCM0_CLKOUT5_DIVIDE = 1
-- C_MMCM0_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT5_PHASE = 0.0
-- C_MMCM0_CLKOUT6_DIVIDE = 1
-- C_MMCM0_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT6_PHASE = 0.0
-- C_MMCM0_CLKOUT0_USE_FINE_PS = false
-- C_MMCM0_CLKOUT1_USE_FINE_PS = false
-- C_MMCM0_CLKOUT2_USE_FINE_PS = false
-- C_MMCM0_CLKOUT3_USE_FINE_PS = false
-- C_MMCM0_CLKOUT4_USE_FINE_PS = false
-- C_MMCM0_CLKOUT5_USE_FINE_PS = false
-- C_MMCM0_CLKOUT6_USE_FINE_PS = false
-- C_MMCM0_COMPENSATION = "ZHOLD"
-- C_MMCM0_DIVCLK_DIVIDE = 1
-- C_MMCM0_REF_JITTER1 = 0.010
-- C_MMCM0_CLKIN1_BUF = false
-- C_MMCM0_CLKFBOUT_BUF = false
-- C_MMCM0_CLKOUT0_BUF = false
-- C_MMCM0_CLKOUT1_BUF = false
-- C_MMCM0_CLKOUT2_BUF = false
-- C_MMCM0_CLKOUT3_BUF = false
-- C_MMCM0_CLKOUT4_BUF = false
-- C_MMCM0_CLKOUT5_BUF = false
-- C_MMCM0_CLKOUT6_BUF = false
-- C_MMCM0_CLOCK_HOLD = false
-- C_MMCM0_STARTUP_WAIT = false
-- C_MMCM0_EXT_RESET_HIGH = 1
-- C_MMCM0_FAMILY = "virtex6"
-- C_MMCM0_CLKIN1_MODULE = NONE
-- C_MMCM0_CLKIN1_PORT = NONE
-- C_MMCM0_CLKFBIN_MODULE = NONE
-- C_MMCM0_CLKFBIN_PORT = NONE
-- C_MMCM0_RST_MODULE = NONE
-- C_MMCM1_BANDWIDTH = "OPTIMIZED"
-- C_MMCM1_CLKFBOUT_MULT_F = 1.0
-- C_MMCM1_CLKFBOUT_PHASE = 0.0
-- C_MMCM1_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM1_CLKIN1_PERIOD = 0.000
-- C_MMCM1_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM1_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT0_PHASE = 0.0
-- C_MMCM1_CLKOUT1_DIVIDE = 1
-- C_MMCM1_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT1_PHASE = 0.0
-- C_MMCM1_CLKOUT2_DIVIDE = 1
-- C_MMCM1_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT2_PHASE = 0.0
-- C_MMCM1_CLKOUT3_DIVIDE = 1
-- C_MMCM1_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT3_PHASE = 0.0
-- C_MMCM1_CLKOUT4_DIVIDE = 1
-- C_MMCM1_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT4_PHASE = 0.0
-- C_MMCM1_CLKOUT4_CASCADE = false
-- C_MMCM1_CLKOUT5_DIVIDE = 1
-- C_MMCM1_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT5_PHASE = 0.0
-- C_MMCM1_CLKOUT6_DIVIDE = 1
-- C_MMCM1_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT6_PHASE = 0.0
-- C_MMCM1_CLKOUT0_USE_FINE_PS = false
-- C_MMCM1_CLKOUT1_USE_FINE_PS = false
-- C_MMCM1_CLKOUT2_USE_FINE_PS = false
-- C_MMCM1_CLKOUT3_USE_FINE_PS = false
-- C_MMCM1_CLKOUT4_USE_FINE_PS = false
-- C_MMCM1_CLKOUT5_USE_FINE_PS = false
-- C_MMCM1_CLKOUT6_USE_FINE_PS = false
-- C_MMCM1_COMPENSATION = "ZHOLD"
-- C_MMCM1_DIVCLK_DIVIDE = 1
-- C_MMCM1_REF_JITTER1 = 0.010
-- C_MMCM1_CLKIN1_BUF = false
-- C_MMCM1_CLKFBOUT_BUF = false
-- C_MMCM1_CLKOUT0_BUF = false
-- C_MMCM1_CLKOUT1_BUF = false
-- C_MMCM1_CLKOUT2_BUF = false
-- C_MMCM1_CLKOUT3_BUF = false
-- C_MMCM1_CLKOUT4_BUF = false
-- C_MMCM1_CLKOUT5_BUF = false
-- C_MMCM1_CLKOUT6_BUF = false
-- C_MMCM1_CLOCK_HOLD = false
-- C_MMCM1_STARTUP_WAIT = false
-- C_MMCM1_EXT_RESET_HIGH = 1
-- C_MMCM1_FAMILY = "virtex6"
-- C_MMCM1_CLKIN1_MODULE = NONE
-- C_MMCM1_CLKIN1_PORT = NONE
-- C_MMCM1_CLKFBIN_MODULE = NONE
-- C_MMCM1_CLKFBIN_PORT = NONE
-- C_MMCM1_RST_MODULE = NONE
-- C_MMCM2_BANDWIDTH = "OPTIMIZED"
-- C_MMCM2_CLKFBOUT_MULT_F = 1.0
-- C_MMCM2_CLKFBOUT_PHASE = 0.0
-- C_MMCM2_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM2_CLKIN1_PERIOD = 0.000
-- C_MMCM2_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM2_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT0_PHASE = 0.0
-- C_MMCM2_CLKOUT1_DIVIDE = 1
-- C_MMCM2_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT1_PHASE = 0.0
-- C_MMCM2_CLKOUT2_DIVIDE = 1
-- C_MMCM2_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT2_PHASE = 0.0
-- C_MMCM2_CLKOUT3_DIVIDE = 1
-- C_MMCM2_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT3_PHASE = 0.0
-- C_MMCM2_CLKOUT4_DIVIDE = 1
-- C_MMCM2_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT4_PHASE = 0.0
-- C_MMCM2_CLKOUT4_CASCADE = false
-- C_MMCM2_CLKOUT5_DIVIDE = 1
-- C_MMCM2_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT5_PHASE = 0.0
-- C_MMCM2_CLKOUT6_DIVIDE = 1
-- C_MMCM2_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT6_PHASE = 0.0
-- C_MMCM2_CLKOUT0_USE_FINE_PS = false
-- C_MMCM2_CLKOUT1_USE_FINE_PS = false
-- C_MMCM2_CLKOUT2_USE_FINE_PS = false
-- C_MMCM2_CLKOUT3_USE_FINE_PS = false
-- C_MMCM2_CLKOUT4_USE_FINE_PS = false
-- C_MMCM2_CLKOUT5_USE_FINE_PS = false
-- C_MMCM2_CLKOUT6_USE_FINE_PS = false
-- C_MMCM2_COMPENSATION = "ZHOLD"
-- C_MMCM2_DIVCLK_DIVIDE = 1
-- C_MMCM2_REF_JITTER1 = 0.010
-- C_MMCM2_CLKIN1_BUF = false
-- C_MMCM2_CLKFBOUT_BUF = false
-- C_MMCM2_CLKOUT0_BUF = false
-- C_MMCM2_CLKOUT1_BUF = false
-- C_MMCM2_CLKOUT2_BUF = false
-- C_MMCM2_CLKOUT3_BUF = false
-- C_MMCM2_CLKOUT4_BUF = false
-- C_MMCM2_CLKOUT5_BUF = false
-- C_MMCM2_CLKOUT6_BUF = false
-- C_MMCM2_CLOCK_HOLD = false
-- C_MMCM2_STARTUP_WAIT = false
-- C_MMCM2_EXT_RESET_HIGH = 1
-- C_MMCM2_FAMILY = "virtex6"
-- C_MMCM2_CLKIN1_MODULE = NONE
-- C_MMCM2_CLKIN1_PORT = NONE
-- C_MMCM2_CLKFBIN_MODULE = NONE
-- C_MMCM2_CLKFBIN_PORT = NONE
-- C_MMCM2_RST_MODULE = NONE
-- C_MMCM3_BANDWIDTH = "OPTIMIZED"
-- C_MMCM3_CLKFBOUT_MULT_F = 1.0
-- C_MMCM3_CLKFBOUT_PHASE = 0.0
-- C_MMCM3_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM3_CLKIN1_PERIOD = 0.000
-- C_MMCM3_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM3_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT0_PHASE = 0.0
-- C_MMCM3_CLKOUT1_DIVIDE = 1
-- C_MMCM3_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT1_PHASE = 0.0
-- C_MMCM3_CLKOUT2_DIVIDE = 1
-- C_MMCM3_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT2_PHASE = 0.0
-- C_MMCM3_CLKOUT3_DIVIDE = 1
-- C_MMCM3_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT3_PHASE = 0.0
-- C_MMCM3_CLKOUT4_DIVIDE = 1
-- C_MMCM3_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT4_PHASE = 0.0
-- C_MMCM3_CLKOUT4_CASCADE = false
-- C_MMCM3_CLKOUT5_DIVIDE = 1
-- C_MMCM3_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT5_PHASE = 0.0
-- C_MMCM3_CLKOUT6_DIVIDE = 1
-- C_MMCM3_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT6_PHASE = 0.0
-- C_MMCM3_CLKOUT0_USE_FINE_PS = false
-- C_MMCM3_CLKOUT1_USE_FINE_PS = false
-- C_MMCM3_CLKOUT2_USE_FINE_PS = false
-- C_MMCM3_CLKOUT3_USE_FINE_PS = false
-- C_MMCM3_CLKOUT4_USE_FINE_PS = false
-- C_MMCM3_CLKOUT5_USE_FINE_PS = false
-- C_MMCM3_CLKOUT6_USE_FINE_PS = false
-- C_MMCM3_COMPENSATION = "ZHOLD"
-- C_MMCM3_DIVCLK_DIVIDE = 1
-- C_MMCM3_REF_JITTER1 = 0.010
-- C_MMCM3_CLKIN1_BUF = false
-- C_MMCM3_CLKFBOUT_BUF = false
-- C_MMCM3_CLKOUT0_BUF = false
-- C_MMCM3_CLKOUT1_BUF = false
-- C_MMCM3_CLKOUT2_BUF = false
-- C_MMCM3_CLKOUT3_BUF = false
-- C_MMCM3_CLKOUT4_BUF = false
-- C_MMCM3_CLKOUT5_BUF = false
-- C_MMCM3_CLKOUT6_BUF = false
-- C_MMCM3_CLOCK_HOLD = false
-- C_MMCM3_STARTUP_WAIT = false
-- C_MMCM3_EXT_RESET_HIGH = 1
-- C_MMCM3_FAMILY = "virtex6"
-- C_MMCM3_CLKIN1_MODULE = NONE
-- C_MMCM3_CLKIN1_PORT = NONE
-- C_MMCM3_CLKFBIN_MODULE = NONE
-- C_MMCM3_CLKFBIN_PORT = NONE
-- C_MMCM3_RST_MODULE = NONE
----------------------------------------
-- C_PLLE0_BANDWIDTH = "OPTIMIZED"
-- C_PLLE0_CLKFBOUT_MULT = 1
-- C_PLLE0_CLKFBOUT_PHASE = 0.0
-- C_PLLE0_CLKIN1_PERIOD = 0.000
-- C_PLLE0_CLKOUT0_DIVIDE = 1
-- C_PLLE0_CLKOUT0_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT0_PHASE = 0.0
-- C_PLLE0_CLKOUT1_DIVIDE = 1
-- C_PLLE0_CLKOUT1_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT1_PHASE = 0.0
-- C_PLLE0_CLKOUT2_DIVIDE = 1
-- C_PLLE0_CLKOUT2_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT2_PHASE = 0.0
-- C_PLLE0_CLKOUT3_DIVIDE = 1
-- C_PLLE0_CLKOUT3_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT3_PHASE = 0.0
-- C_PLLE0_CLKOUT4_DIVIDE = 1
-- C_PLLE0_CLKOUT4_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT4_PHASE = 0.0
-- C_PLLE0_CLKOUT5_DIVIDE = 1
-- C_PLLE0_CLKOUT5_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT5_PHASE = 0.0
-- C_PLLE0_COMPENSATION = "ZHOLD"
-- C_PLLE0_DIVCLK_DIVIDE = 1
-- C_PLLE0_REF_JITTER1 = 0.010
-- C_PLLE0_CLKIN1_BUF = false
-- C_PLLE0_CLKFBOUT_BUF = false
-- C_PLLE0_CLKOUT0_BUF = false
-- C_PLLE0_CLKOUT1_BUF = false
-- C_PLLE0_CLKOUT2_BUF = false
-- C_PLLE0_CLKOUT3_BUF = false
-- C_PLLE0_CLKOUT4_BUF = false
-- C_PLLE0_CLKOUT5_BUF = false
-- C_PLLE0_STARTUP_WAIT = "false"
-- C_PLLE0_EXT_RESET_HIGH = 1
-- C_PLLE0_FAMILY = "virtex7"
-- C_PLLE0_CLKIN1_MODULE = NONE
-- C_PLLE0_CLKIN1_PORT = NONE
-- C_PLLE0_CLKFBIN_MODULE = NONE
-- C_PLLE0_CLKFBIN_PORT = NONE
-- C_PLLE0_RST_MODULE = NONE
----------------------------------------