diff --git a/quad/sw/system_bsp/.cproject b/quad/sw/system_bsp/.cproject deleted file mode 100644 index 685a84bf5443e4d79ba10aa824f36bdead76fb0e..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/.cproject +++ /dev/null @@ -1,15 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no"?> -<?fileVersion 4.0.0?> - -<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - <storageModule moduleId="org.eclipse.cdt.core.settings"> - <cconfiguration id="org.eclipse.cdt.core.default.config.1372124342"> - <storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1372124342" moduleId="org.eclipse.cdt.core.settings" name="Configuration"> - <externalSettings/> - <extensions/> - </storageModule> - <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> - </cconfiguration> - </storageModule> - <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> -</cproject> diff --git a/quad/sw/system_bsp/.project b/quad/sw/system_bsp/.project deleted file mode 100644 index 922cddb11b529d10df5598fa8248359e0be5db72..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/.project +++ /dev/null @@ -1,76 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<projectDescription> - <name>system_bsp</name> - <comment></comment> - <projects> - <project>system_hw_platform</project> - </projects> - <buildSpec> - <buildCommand> - <name>org.eclipse.cdt.make.core.makeBuilder</name> - <arguments> - <dictionary> - <key>org.eclipse.cdt.core.errorOutputParser</key> - <value>org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser;</value> - </dictionary> - <dictionary> - <key>org.eclipse.cdt.make.core.append_environment</key> - <value>true</value> - </dictionary> - <dictionary> - <key>org.eclipse.cdt.make.core.build.arguments</key> - <value></value> - </dictionary> - <dictionary> - <key>org.eclipse.cdt.make.core.build.command</key> - <value>make</value> - </dictionary> - <dictionary> - <key>org.eclipse.cdt.make.core.build.target.auto</key> - <value>all</value> - </dictionary> - <dictionary> - <key>org.eclipse.cdt.make.core.build.target.clean</key> - <value>clean</value> - </dictionary> - <dictionary> - <key>org.eclipse.cdt.make.core.build.target.inc</key> - <value>all</value> - </dictionary> - <dictionary> - <key>org.eclipse.cdt.make.core.enableAutoBuild</key> - <value>true</value> - </dictionary> - <dictionary> - <key>org.eclipse.cdt.make.core.enableCleanBuild</key> - <value>true</value> - </dictionary> - <dictionary> - <key>org.eclipse.cdt.make.core.enableFullBuild</key> - <value>true</value> - </dictionary> - <dictionary> - <key>org.eclipse.cdt.make.core.enabledIncrementalBuild</key> - <value>true</value> - </dictionary> - <dictionary> - <key>org.eclipse.cdt.make.core.environment</key> - <value></value> - </dictionary> - <dictionary> - <key>org.eclipse.cdt.make.core.stopOnError</key> - <value>false</value> - </dictionary> - <dictionary> - <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key> - <value>true</value> - </dictionary> - </arguments> - </buildCommand> - </buildSpec> - <natures> - <nature>com.xilinx.sdk.sw.SwProjectNature</nature> - <nature>org.eclipse.cdt.core.cnature</nature> - <nature>org.eclipse.cdt.make.core.makeNature</nature> - </natures> -</projectDescription> diff --git a/quad/sw/system_bsp/.sdkproject b/quad/sw/system_bsp/.sdkproject deleted file mode 100644 index 3135ec9f796f86108f3510421221835514fcc15f..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/.sdkproject +++ /dev/null @@ -1,3 +0,0 @@ -THIRPARTY=false -PROCESSOR=ps7_cortexa9_0 -MSS_FILE=system.mss diff --git a/quad/sw/system_bsp/Makefile b/quad/sw/system_bsp/Makefile deleted file mode 100644 index fe2a0efc7cc39ff9edfdbb9064b229a72106cb58..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/Makefile +++ /dev/null @@ -1,21 +0,0 @@ -# Makefile generated by Xilinx SDK. - --include libgen.options - -LIBRARIES = ${PROCESSOR}/lib/libxil.a -MSS = system.mss - -all: libs - @echo 'Finished building libraries' - -libs: $(LIBRARIES) - -$(LIBRARIES): $(MSS) - libgen -hw ${HWSPEC}\ - ${REPOSITORIES}\ - -pe ${PROCESSOR} \ - -log libgen.log \ - $(MSS) - -clean: - rm -rf ${PROCESSOR} diff --git a/quad/sw/system_bsp/libgen.log b/quad/sw/system_bsp/libgen.log deleted file mode 100644 index d0027f5bc560088710c3d4f5f68bf2cfa1d8c280..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/libgen.log +++ /dev/null @@ -1,20 +0,0 @@ -Release 14.7 - libgen Xilinx EDK 14.7 Build EDK_P.20131013 - (lin64) -Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. - -Command Line: libgen -hw ../system_hw_platform/system.xml -pe ps7_cortexa9_0 --log libgen.log system.mss - - -Staging source files. -Running DRCs. -Running generate. -Running post_generate. -Running include - 'gmake -s include "COMPILER=arm-xilinx-eabi-gcc" -"ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g --O0"'. - -Running libs - 'gmake -s libs "COMPILER=arm-xilinx-eabi-gcc" -"ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g --O0"'. -Running execs_generate. diff --git a/quad/sw/system_bsp/libgen.options b/quad/sw/system_bsp/libgen.options deleted file mode 100644 index ac5ba396687b73316827155661d71b9247b953be..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/libgen.options +++ /dev/null @@ -1,3 +0,0 @@ -PROCESSOR=ps7_cortexa9_0 -REPOSITORIES= -HWSPEC=../system_hw_platform/system.xml diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h deleted file mode 100644 index 19499f7c5b33e404a6548723db1e165b8bd8db31..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h +++ /dev/null @@ -1,292 +0,0 @@ -////////////////////////////////////////////////////////////////////// -// -// Copyright (c) 2004-11 Xilinx, Inc. All rights reserved. -// Xilinx, Inc. -// -// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR -// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION -// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE -// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO -// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY -// AND FITNESS FOR A PARTICULAR PURPOSE. -// -// $Id: _profile_timer_hw.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $ -// -// _program_timer_hw.h: -// Timer related functions -// -////////////////////////////////////////////////////////////////////// - -#ifndef _PROFILE_TIMER_HW_H -#define _PROFILE_TIMER_HW_H - -#include "profile.h" - -#ifdef PROC_PPC -#if defined __GNUC__ -# define SYNCHRONIZE_IO __asm__ volatile ("eieio") -#elif defined __DCC__ -# define SYNCHRONIZE_IO __asm volatile(" eieio") -#else -# define SYNCHRONIZE_IO -#endif -#endif - -#ifdef PROC_PPC -#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; -#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; } -#else -#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr)); -#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); } -#endif - -#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\ - ProfIo_Out32(((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \ - (RegOffset)), (ValueToWrite)) - -#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \ - ProfIo_In32((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + (RegOffset)) - -#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\ - ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \ - (RegisterValue)) - -#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \ - ProfTimerCtr_mReadReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET) - - - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef PROC_PPC -#include "xexception_l.h" -#include "xtime_l.h" -#include "xpseudo_asm.h" -#endif - -#ifdef TIMER_CONNECT_INTC -#include "xintc_l.h" -#include "xintc.h" -#endif // TIMER_CONNECT_INTC - -#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9) -#include "xtmrctr_l.h" -#endif - -#ifdef PROC_CORTEXA9 -#include "xscutimer_hw.h" -#include "xscugic.h" -#endif - -extern unsigned int timer_clk_ticks ; - -//-------------------------------------------------------------------- -// PowerPC Target - Timer related functions -//-------------------------------------------------------------------- -#ifdef PROC_PPC - -#ifdef PPC_PIT_INTERRUPT -unsigned long timer_lo_clk_ticks ; // Clk ticks when Timer is disabled in CG -#endif - -#ifdef PROC_PPC440 -#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE -#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS -#define XREG_SPR_PIT XREG_SPR_DEC -#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT -#endif - -//-------------------------------------------------------------------- -// Disable the Timer - During Profiling -// -// For PIT Timer - -// 1. XTime_PITDisableInterrupt() ; -// 2. Store the remaining timer clk tick -// 3. Stop the PIT Timer -//-------------------------------------------------------------------- - -#ifdef PPC_PIT_INTERRUPT -#define disable_timer() \ - { \ - unsigned long val; \ - val=mfspr(XREG_SPR_TCR); \ - mtspr(XREG_SPR_TCR, val & ~XREG_TCR_PIT_INTERRUPT_ENABLE); \ - timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \ - mtspr(XREG_SPR_PIT, 0); \ - } -#else -#define disable_timer() \ - { \ - u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \ - u32 tmp_v = ProfIo_In32(addr); \ - tmp_v = tmp_v & ~XTC_CSR_ENABLE_TMR_MASK; \ - ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \ - } -#endif - - - -//-------------------------------------------------------------------- -// Enable the Timer -// -// For PIT Timer - -// 1. Load the remaining timer clk ticks -// 2. XTime_PITEnableInterrupt() ; -//-------------------------------------------------------------------- -#ifdef PPC_PIT_INTERRUPT -#define enable_timer() \ - { \ - unsigned long val; \ - val=mfspr(XREG_SPR_TCR); \ - mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \ - mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \ - } -#else -#define enable_timer() \ - { \ - u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \ - u32 tmp_v = ProfIo_In32(addr); \ - tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \ - ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \ - } -#endif - - - -//-------------------------------------------------------------------- -// Send Ack to Timer Interrupt -// -// For PIT Timer - -// 1. Load the timer clk ticks -// 2. Enable AutoReload and Interrupt -// 3. Clear PIT Timer Status bits -//-------------------------------------------------------------------- -#ifdef PPC_PIT_INTERRUPT -#define timer_ack() \ - { \ - unsigned long val; \ - mtspr(XREG_SPR_PIT, timer_clk_ticks); \ - mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \ - val=mfspr(XREG_SPR_TCR); \ - mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \ - } -#else -#define timer_ack() \ - { \ - unsigned int csr; \ - csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \ - ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \ - } -#endif - -//-------------------------------------------------------------------- -#endif // PROC_PPC -//-------------------------------------------------------------------- - - - - -//-------------------------------------------------------------------- -// MicroBlaze Target - Timer related functions -//-------------------------------------------------------------------- -#ifdef PROC_MICROBLAZE - -//-------------------------------------------------------------------- -// Disable the Timer during Call-Graph Data collection -// -//-------------------------------------------------------------------- -#define disable_timer() \ - { \ - u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \ - u32 tmp_v = ProfIo_In32(addr); \ - tmp_v = tmp_v & ~XTC_CSR_ENABLE_TMR_MASK; \ - ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \ - } - - -//-------------------------------------------------------------------- -// Enable the Timer after Call-Graph Data collection -// -//-------------------------------------------------------------------- -#define enable_timer() \ - { \ - u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \ - u32 tmp_v = ProfIo_In32(addr); \ - tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \ - ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \ - } - - -//-------------------------------------------------------------------- -// Send Ack to Timer Interrupt -// -//-------------------------------------------------------------------- -#define timer_ack() \ - { \ - unsigned int csr; \ - csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \ - ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \ - } - -//-------------------------------------------------------------------- -#endif // PROC_MICROBLAZE -//-------------------------------------------------------------------- - -//-------------------------------------------------------------------- -// Cortex A9 Target - Timer related functions -//-------------------------------------------------------------------- -#ifdef PROC_CORTEXA9 - -//-------------------------------------------------------------------- -// Disable the Timer during Call-Graph Data collection -// -//-------------------------------------------------------------------- -#define disable_timer() \ -{ \ - u32 Reg; \ - Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \ - Reg &= ~XSCUTIMER_CONTROL_ENABLE_MASK;\ - Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\ -} \ - - -//-------------------------------------------------------------------- -// Enable the Timer after Call-Graph Data collection -// -//-------------------------------------------------------------------- -#define enable_timer() \ -{ \ - u32 Reg; \ - Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \ - Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \ - Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\ -} \ - - -//-------------------------------------------------------------------- -// Send Ack to Timer Interrupt -// -//-------------------------------------------------------------------- -#define timer_ack() \ -{ \ - Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_ISR_OFFSET, \ - XSCUTIMER_ISR_EVENT_FLAG_MASK);\ -} - -//-------------------------------------------------------------------- -#endif // PROC_CORTEXA9 -//-------------------------------------------------------------------- - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/bspconfig.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/bspconfig.h deleted file mode 100644 index a7fdebbc69da581bcb2a49e2875b35e0c66d64f3..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/bspconfig.h +++ /dev/null @@ -1,15 +0,0 @@ - -/******************************************************************* -* -* CAUTION: This file is automatically generated by libgen. -* Version: Xilinx EDK 14.7 EDK_P.20131013 -* DO NOT EDIT. -* -* Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. - -* -* Description: Configurations for Standalone BSP -* -*******************************************************************/ - -#define MICROBLAZE_PVR_NONE diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h deleted file mode 100644 index 2cf77fe837c322816705985c52c53d8c49c97fb1..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h +++ /dev/null @@ -1,51 +0,0 @@ -////////////////////////////////////////////////////////////////////// -// -// Copyright (c) 2002-11 Xilinx, Inc. All rights reserved. -// Xilinx, Inc. -// -// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR -// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION -// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE -// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO -// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY -// AND FITNESS FOR A PARTICULAR PURPOSE. -// -// $Id: mblaze_nt_types.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $ -// -////////////////////////////////////////////////////////////////////// - -#ifndef _MBLAZE_NT_TYPES_H -#define _MBLAZE_NT_TYPES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef char byte; -typedef short half; -typedef int word; -typedef unsigned char ubyte; -typedef unsigned short uhalf; -typedef unsigned int uword; -typedef ubyte boolean; - -//typedef unsigned char u_char; -//typedef unsigned short u_short; -//typedef unsigned int u_int; -//typedef unsigned long u_long; - -typedef short int16_t; -typedef unsigned short uint16_t; -typedef int int32_t; -typedef unsigned int uint32_t; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/profile.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/profile.h deleted file mode 100644 index 0657e6f9959fab9deee68f749e63ebfae6c4d336..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/profile.h +++ /dev/null @@ -1,127 +0,0 @@ -////////////////////////////////////////////////////////////////////// -// -// Copyright (c) 2002-11 Xilinx, Inc. All rights reserved. -// Xilinx, Inc. -// -// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR -// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION -// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE -// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO -// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY -// AND FITNESS FOR A PARTICULAR PURPOSE. -// -// $Id: profile.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $ -// -////////////////////////////////////////////////////////////////////// - -#ifndef _PROFILE_H -#define _PROFILE_H 1 - -#include <stdio.h> -#include "mblaze_nt_types.h" -#include "profile_config.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void _system_init( void ) ; -void _system_clean( void ) ; -void mcount(unsigned long frompc, unsigned long selfpc); -void profile_intr_handler( void ) ; - - - -/**************************************************************************** - * Profiling on hardware - Hash table maintained on hardware and data sent - * to xmd for gmon.out generation. - ****************************************************************************/ -/* - * histogram counters are unsigned shorts (according to the kernel). - */ -#define HISTCOUNTER unsigned short - -struct tostruct { - unsigned long selfpc; - long count; - short link; - unsigned short pad; -}; - -struct fromstruct { - unsigned long frompc ; - short link ; - unsigned short pad ; -} ; - -/* - * general rounding functions. - */ -#define ROUNDDOWN(x,y) (((x)/(y))*(y)) -#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y)) - -/* - * The profiling data structures are housed in this structure. - */ -struct gmonparam { - long int state; - - // Histogram Information - unsigned short *kcount; /* No. of bins in histogram */ - unsigned long kcountsize; /* Histogram samples */ - - // Call-graph Information - struct fromstruct *froms; - unsigned long fromssize; - struct tostruct *tos; - unsigned long tossize; - - // Initialization I/Ps - unsigned long lowpc; - unsigned long highpc; - unsigned long textsize; - //unsigned long cg_froms; - //unsigned long cg_tos; -}; -extern struct gmonparam *_gmonparam; -extern int n_gmon_sections; - -/* - * Possible states of profiling. - */ -#define GMON_PROF_ON 0 -#define GMON_PROF_BUSY 1 -#define GMON_PROF_ERROR 2 -#define GMON_PROF_OFF 3 - -/* - * Sysctl definitions for extracting profiling information from the kernel. - */ -#define GPROF_STATE 0 /* int: profiling enabling variable */ -#define GPROF_COUNT 1 /* struct: profile tick count buffer */ -#define GPROF_FROMS 2 /* struct: from location hash bucket */ -#define GPROF_TOS 3 /* struct: destination/count structure */ -#define GPROF_GMONPARAM 4 /* struct: profiling parameters (see above) */ - -#ifdef __cplusplus -} -#endif - -#endif /* _PROFILE_H */ - - - - - - - - - - - - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/sleep.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/sleep.h deleted file mode 100644 index 4d9dd5abde56a317894d979c67bb6cc20fa4f1eb..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/sleep.h +++ /dev/null @@ -1,58 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ - -#ifndef SLEEP_H -#define SLEEP_H - -#ifdef __cplusplus -extern "C" { -#endif - -void nanosleep(unsigned int nanoseconds); -int usleep(unsigned int useconds); -int sleep(unsigned int seconds); - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/smc.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/smc.h deleted file mode 100644 index fcfccebaa6c02fe0dbd282304e0eace4ce037b4b..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/smc.h +++ /dev/null @@ -1,124 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* @file smc.h -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- --------------------------------------------------- -* 1.00a sdm 11/03/09 Initial release. -* </pre> -* -* @note None. -* -******************************************************************************/ - -#ifndef SMC_H /* prevent circular inclusions */ -#define SMC_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xparameters.h" -#include "xil_io.h" - -/***************** Macros (Inline Functions) Definitions *********************/ - -/**************************** Type Definitions *******************************/ - -/************************** Constant Definitions *****************************/ - -/* Memory controller configuration register offset */ -#define XSMCPSS_MC_STATUS 0x000 /* Controller status reg, RO */ -#define XSMCPSS_MC_INTERFACE_CONFIG 0x004 /* Interface config reg, RO */ -#define XSMCPSS_MC_SET_CONFIG 0x008 /* Set configuration reg, WO */ -#define XSMCPSS_MC_CLR_CONFIG 0x00C /* Clear config reg, WO */ -#define XSMCPSS_MC_DIRECT_CMD 0x010 /* Direct command reg, WO */ -#define XSMCPSS_MC_SET_CYCLES 0x014 /* Set cycles register, WO */ -#define XSMCPSS_MC_SET_OPMODE 0x018 /* Set opmode register, WO */ -#define XSMCPSS_MC_REFRESH_PERIOD_0 0x020 /* Refresh period_0 reg, RW */ -#define XSMCPSS_MC_REFRESH_PERIOD_1 0x024 /* Refresh period_1 reg, RW */ - -/* Chip select configuration register offset */ -#define XSMCPSS_CS_IF0_CHIP_0_OFFSET 0x100 /* Interface 0 chip 0 config */ -#define XSMCPSS_CS_IF0_CHIP_1_OFFSET 0x120 /* Interface 0 chip 1 config */ -#define XSMCPSS_CS_IF0_CHIP_2_OFFSET 0x140 /* Interface 0 chip 2 config */ -#define XSMCPSS_CS_IF0_CHIP_3_OFFSET 0x160 /* Interface 0 chip 3 config */ -#define XSMCPSS_CS_IF1_CHIP_0_OFFSET 0x180 /* Interface 1 chip 0 config */ -#define XSMCPSS_CS_IF1_CHIP_1_OFFSET 0x1A0 /* Interface 1 chip 1 config */ -#define XSMCPSS_CS_IF1_CHIP_2_OFFSET 0x1C0 /* Interface 1 chip 2 config */ -#define XSMCPSS_CS_IF1_CHIP_3_OFFSET 0x1E0 /* Interface 1 chip 3 config */ - -/* User configuration register offset */ -#define XSMCPSS_UC_STATUS_OFFSET 0x200 /* User status reg, RO */ -#define XSMCPSS_UC_CONFIG_OFFSET 0x204 /* User config reg, WO */ - -/* Integration test register offset */ -#define XSMCPSS_IT_OFFSET 0xE00 - -/* ID configuration register offset */ -#define XSMCPSS_ID_PERIP_0_OFFSET 0xFE0 -#define XSMCPSS_ID_PERIP_1_OFFSET 0xFE4 -#define XSMCPSS_ID_PERIP_2_OFFSET 0xFE8 -#define XSMCPSS_ID_PERIP_3_OFFSET 0xFEC -#define XSMCPSS_ID_PCELL_0_OFFSET 0xFF0 -#define XSMCPSS_ID_PCELL_1_OFFSET 0xFF4 -#define XSMCPSS_ID_PCELL_2_OFFSET 0xFF8 -#define XSMCPSS_ID_PCELL_3_OFFSET 0xFFC - -/************************** Variable Definitions *****************************/ - -/************************** Function Prototypes ******************************/ - -void XSmc_SramInit (void); -void XSmc_NorInit(void); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* SMC_H */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/vectors.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/vectors.h deleted file mode 100644 index 1b094cd177f030e4eabc8413da1a3584955da49f..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/vectors.h +++ /dev/null @@ -1,90 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* @file vectors.h -* -* This file contains the C level vector prototypes for the ARM Cortex A9 core. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- --------------------------------------------------- -* 1.00a ecm 10/20/10 Initial version, moved over from bsp area -* </pre> -* -* @note -* -* None. -* -******************************************************************************/ - -#ifndef _VECTORS_H_ -#define _VECTORS_H_ - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif -/***************** Macros (Inline Functions) Definitions *********************/ - -/**************************** Type Definitions *******************************/ - -/************************** Constant Definitions *****************************/ - -/************************** Function Prototypes ******************************/ -void FIQInterrupt(void); -void IRQInterrupt(void); -void SWInterrupt(void); -void DataAbortInterrupt(void); -void PrefetchAbortInterrupt(void); - - -#ifdef __cplusplus -} -#endif - -#endif /* protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xadcps.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xadcps.h deleted file mode 100644 index 7c53621effb3bba8f941d69255d94b5925f8fac4..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xadcps.h +++ /dev/null @@ -1,566 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file xadcps.h -* -* The XAdcPs driver supports the Xilinx XADC/ADC device. -* -* The XADC/ADC device has the following features: -* - 10-bit, 200-KSPS (kilo samples per second) -* Analog-to-Digital Converter (ADC) -* - Monitoring of on-chip supply voltages and temperature -* - 1 dedicated differential analog-input pair and -* 16 auxiliary differential analog-input pairs -* - Automatic alarms based on user defined limits for the on-chip -* supply voltages and temperature -* - Automatic Channel Sequencer, programmable averaging, programmable -* acquisition time for the external inputs, unipolar or differential -* input selection for the external inputs -* - Inbuilt Calibration -* - Optional interrupt request generation -* -* -* The user should refer to the hardware device specification for detailed -* information about the device. -* -* This header file contains the prototypes of driver functions that can -* be used to access the XADC/ADC device. -* -* -* <b> XADC Channel Sequencer Modes </b> -* -* The XADC Channel Sequencer supports the following operating modes: -* -* - <b> Default </b>: This is the default mode after power up. -* In this mode of operation the XADC operates in -* a sequence mode, monitoring the on chip sensors: -* Temperature, VCCINT, and VCCAUX. -* - <b> One pass through sequence </b>: In this mode the XADC -* converts the channels enabled in the Sequencer Channel Enable -* registers for a single pass and then stops. -* - <b> Continuous cycling of sequence </b>: In this mode the XADC -* converts the channels enabled in the Sequencer Channel Enable -* registers continuously. -* - <b> Single channel mode</b>: In this mode the XADC Channel -* Sequencer is disabled and the XADC operates in a -* Single Channel Mode. -* The XADC can operate either in a Continuous or Event -* driven sampling mode in the single channel mode. -* - <b> Simultaneous Sampling Mode</b>: In this mode the XADC Channel -* Sequencer will automatically sequence through eight fixed pairs -* of auxiliary analog input channels for simulataneous conversion. -* - <b> Independent ADC mode</b>: In this mode the first ADC (A) is used to -* is used to implement a fixed monitoring mode similar to the -* default mode but the alarm fucntions ar eenabled. -* The second ADC (B) is available to be used with external analog -* input channels only. -* -* Read the XADC spec for more information about the sequencer modes. -* -* <b> Initialization and Configuration </b> -* -* The device driver enables higher layer software (e.g., an application) to -* communicate to the XADC/ADC device. -* -* XAdcPs_CfgInitialize() API is used to initialize the XADC/ADC -* device. The user needs to first call the XAdcPs_LookupConfig() API which -* returns the Configuration structure pointer which is passed as a parameter to -* the XAdcPs_CfgInitialize() API. -* -* -* <b>Interrupts</b> -* -* The XADC/ADC device supports interrupt driven mode and the default -* operation mode is polling mode. -* -* The interrupt mode is available only if hardware is configured to support -* interrupts. -* -* This driver does not provide a Interrupt Service Routine (ISR) for the device. -* It is the responsibility of the application to provide one if needed. Refer to -* the interrupt example provided with this driver for details on using the -* device in interrupt mode. -* -* -* <b> Virtual Memory </b> -* -* This driver supports Virtual Memory. The RTOS is responsible for calculating -* the correct device base address in Virtual Memory space. -* -* -* <b> Threads </b> -* -* This driver is not thread safe. Any needs for threads or thread mutual -* exclusion must be satisfied by the layer above this driver. -* -* -* <b> Asserts </b> -* -* Asserts are used within all Xilinx drivers to enforce constraints on argument -* values. Asserts can be turned off on a system-wide basis by defining, at -* compile time, the NDEBUG identifier. By default, asserts are turned on and it -* is recommended that users leave asserts on during development. -* -* -* <b> Building the driver </b> -* -* The XAdcPs driver is composed of several source files. This allows the user -* to build and link only those parts of the driver that are necessary. -* -* <b> Limitations of the driver </b> -* -* XADC/ADC device can be accessed through the JTAG port and the PLB -* interface. The driver implementation does not support the simultaneous access -* of the device by both these interfaces. The user has to care of this situation -* in the user application code. -* -* <br><br> -* -* <pre> -* -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ----- -------- ----------------------------------------------------- -* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver -* 1.01a bss 02/18/13 Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables -* XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs -* in xadcps.c to fix CR #693371 -* </pre> -* -*****************************************************************************/ -#ifndef XADCPS_H /* Prevent circular inclusions */ -#define XADCPS_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files ********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xstatus.h" -#include "xadcps_hw.h" - -/************************** Constant Definitions ****************************/ - - -/** - * @name Indexes for the different channels. - * @{ - */ -#define XADCPS_CH_TEMP 0x0 /**< On Chip Temperature */ -#define XADCPS_CH_VCCINT 0x1 /**< VCCINT */ -#define XADCPS_CH_VCCAUX 0x2 /**< VCCAUX */ -#define XADCPS_CH_VPVN 0x3 /**< VP/VN Dedicated analog inputs */ -#define XADCPS_CH_VREFP 0x4 /**< VREFP */ -#define XADCPS_CH_VREFN 0x5 /**< VREFN */ -#define XADCPS_CH_VBRAM 0x6 /**< On-chip VBRAM Data Reg, 7 series */ -#define XADCPS_CH_SUPPLY_CALIB 0x07 /**< Supply Calib Data Reg */ -#define XADCPS_CH_ADC_CALIB 0x08 /**< ADC Offset Channel Reg */ -#define XADCPS_CH_GAINERR_CALIB 0x09 /**< Gain Error Channel Reg */ -#define XADCPS_CH_VCCPINT 0x0D /**< On-chip PS VCCPINT Channel , Zynq */ -#define XADCPS_CH_VCCPAUX 0x0E /**< On-chip PS VCCPAUX Channel , Zynq */ -#define XADCPS_CH_VCCPDRO 0x0F /**< On-chip PS VCCPDRO Channel , Zynq */ -#define XADCPS_CH_AUX_MIN 16 /**< Channel number for 1st Aux Channel */ -#define XADCPS_CH_AUX_MAX 31 /**< Channel number for Last Aux channel */ - -/*@}*/ - - -/** - * @name Indexes for reading the Calibration Coefficient Data. - * @{ - */ -#define XADCPS_CALIB_SUPPLY_COEFF 0 /**< Supply Offset Calib Coefficient */ -#define XADCPS_CALIB_ADC_COEFF 1 /**< ADC Offset Calib Coefficient */ -#define XADCPS_CALIB_GAIN_ERROR_COEFF 2 /**< Gain Error Calib Coefficient*/ -/*@}*/ - - -/** - * @name Indexes for reading the Minimum/Maximum Measurement Data. - * @{ - */ -#define XADCPS_MAX_TEMP 0 /**< Maximum Temperature Data */ -#define XADCPS_MAX_VCCINT 1 /**< Maximum VCCINT Data */ -#define XADCPS_MAX_VCCAUX 2 /**< Maximum VCCAUX Data */ -#define XADCPS_MAX_VBRAM 3 /**< Maximum VBRAM Data */ -#define XADCPS_MIN_TEMP 4 /**< Minimum Temperature Data */ -#define XADCPS_MIN_VCCINT 5 /**< Minimum VCCINT Data */ -#define XADCPS_MIN_VCCAUX 6 /**< Minimum VCCAUX Data */ -#define XADCPS_MIN_VBRAM 7 /**< Minimum VBRAM Data */ -#define XADCPS_MAX_VCCPINT 8 /**< Maximum VCCPINT Register , Zynq */ -#define XADCPS_MAX_VCCPAUX 9 /**< Maximum VCCPAUX Register , Zynq */ -#define XADCPS_MAX_VCCPDRO 0xA /**< Maximum VCCPDRO Register , Zynq */ -#define XADCPS_MIN_VCCPINT 0xC /**< Minimum VCCPINT Register , Zynq */ -#define XADCPS_MIN_VCCPAUX 0xD /**< Minimum VCCPAUX Register , Zynq */ -#define XADCPS_MIN_VCCPDRO 0xE /**< Minimum VCCPDRO Register , Zynq */ - -/*@}*/ - - -/** - * @name Alarm Threshold(Limit) Register (ATR) indexes. - * @{ - */ -#define XADCPS_ATR_TEMP_UPPER 0 /**< High user Temperature */ -#define XADCPS_ATR_VCCINT_UPPER 1 /**< VCCINT high voltage limit register */ -#define XADCPS_ATR_VCCAUX_UPPER 2 /**< VCCAUX high voltage limit register */ -#define XADCPS_ATR_OT_UPPER 3 /**< VCCAUX high voltage limit register */ -#define XADCPS_ATR_TEMP_LOWER 4 /**< Upper Over Temperature limit Reg */ -#define XADCPS_ATR_VCCINT_LOWER 5 /**< VCCINT high voltage limit register */ -#define XADCPS_ATR_VCCAUX_LOWER 6 /**< VCCAUX low voltage limit register */ -#define XADCPS_ATR_OT_LOWER 7 /**< Lower Over Temperature limit */ -#define XADCPS_ATR_VBRAM_UPPER_ 8 /**< VRBAM Upper Alarm Reg, 7 Series */ -#define XADCPS_ATR_VCCPINT_UPPER 9 /**< VCCPINT Upper Alarm Reg, Zynq */ -#define XADCPS_ATR_VCCPAUX_UPPER 0xA /**< VCCPAUX Upper Alarm Reg, Zynq */ -#define XADCPS_ATR_VCCPDRO_UPPER 0xB /**< VCCPDRO Upper Alarm Reg, Zynq */ -#define XADCPS_ATR_VBRAM_LOWER 0xC /**< VRBAM Lower Alarm Reg, 7 Series */ -#define XADCPS_ATR_VCCPINT_LOWER 0xD /**< VCCPINT Lower Alarm Reg , Zynq */ -#define XADCPS_ATR_VCCPAUX_LOWER 0xE /**< VCCPAUX Lower Alarm Reg , Zynq */ -#define XADCPS_ATR_VCCPDRO_LOWER 0xF /**< VCCPDRO Lower Alarm Reg , Zynq */ - -/*@}*/ - - -/** - * @name Averaging to be done for the channels. - * @{ - */ -#define XADCPS_AVG_0_SAMPLES 0 /**< No Averaging */ -#define XADCPS_AVG_16_SAMPLES 1 /**< Average 16 samples */ -#define XADCPS_AVG_64_SAMPLES 2 /**< Average 64 samples */ -#define XADCPS_AVG_256_SAMPLES 3 /**< Average 256 samples */ - -/*@}*/ - - -/** - * @name Channel Sequencer Modes of operation - * @{ - */ -#define XADCPS_SEQ_MODE_SAFE 0 /**< Default Safe Mode */ -#define XADCPS_SEQ_MODE_ONEPASS 1 /**< Onepass through Sequencer */ -#define XADCPS_SEQ_MODE_CONTINPASS 2 /**< Continuous Cycling Sequencer */ -#define XADCPS_SEQ_MODE_SINGCHAN 3 /**< Single channel -No Sequencing */ -#define XADCPS_SEQ_MODE_SIMUL_SAMPLING 4 /**< Simultaneous sampling */ -#define XADCPS_SEQ_MODE_INDEPENDENT 8 /**< Independent mode */ - -/*@}*/ - - - -/** - * @name Power Down Modes - * @{ - */ -#define XADCPS_PD_MODE_NONE 0 /**< No Power Down */ -#define XADCPS_PD_MODE_ADCB 1 /**< Power Down ADC B */ -#define XADCPS_PD_MODE_XADC 2 /**< Power Down ADC A and ADC B */ -/*@}*/ - -/**************************** Type Definitions ******************************/ - -/** - * This typedef contains configuration information for the XADC/ADC - * device. - */ -typedef struct { - u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddress; /**< Device base address */ -} XAdcPs_Config; - - -/** - * The driver's instance data. The user is required to allocate a variable - * of this type for every XADC/ADC device in the system. A pointer to - * a variable of this type is then passed to the driver API functions. - */ -typedef struct { - XAdcPs_Config Config; /**< XAdcPs_Config of current device */ - u32 IsReady; /**< Device is initialized and ready */ - -} XAdcPs; - -/***************** Macros (Inline Functions) Definitions ********************/ - -/****************************************************************************/ -/** -* -* This macro checks if the XADC device is in Event Sampling mode. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* -* @return -* - TRUE if the device is in Event Sampling Mode. -* - FALSE if the device is in Continuous Sampling Mode. -* -* @note C-Style signature: -* int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr); -* -*****************************************************************************/ -#define XAdcPs_IsEventSamplingModeSet(InstancePtr) \ - (((XAdcPs_ReadInternalReg(InstancePtr, \ - XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ? \ - TRUE : FALSE)) - - -/****************************************************************************/ -/** -* -* This macro checks if the XADC device is in External Mux mode. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* -* @return -* - TRUE if the device is in External Mux Mode. -* - FALSE if the device is NOT in External Mux Mode. -* -* @note C-Style signature: -* int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr); -* -*****************************************************************************/ -#define XAdcPs_IsExternalMuxModeSet(InstancePtr) \ - (((XAdcPs_ReadInternalReg(InstancePtr, \ - XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ? \ - TRUE : FALSE)) - -/****************************************************************************/ -/** -* -* This macro converts XADC Raw Data to Temperature(centigrades). -* -* @param AdcData is the Raw ADC Data from XADC. -* -* @return The Temperature in centigrades. -* -* @note C-Style signature: -* float XAdcPs_RawToTemperature(u32 AdcData); -* -*****************************************************************************/ -#define XAdcPs_RawToTemperature(AdcData) \ - ((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f) - -/****************************************************************************/ -/** -* -* This macro converts XADC/ADC Raw Data to Voltage(volts). -* -* @param AdcData is the XADC/ADC Raw Data. -* -* @return The Voltage in volts. -* -* @note C-Style signature: -* float XAdcPs_RawToVoltage(u32 AdcData); -* -*****************************************************************************/ -#define XAdcPs_RawToVoltage(AdcData) \ - ((((float)(AdcData))* (3.0f))/65536.0f) - -/****************************************************************************/ -/** -* -* This macro converts Temperature in centigrades to XADC/ADC Raw Data. -* -* @param Temperature is the Temperature in centigrades to be -* converted to XADC/ADC Raw Data. -* -* @return The XADC/ADC Raw Data. -* -* @note C-Style signature: -* int XAdcPs_TemperatureToRaw(float Temperature); -* -*****************************************************************************/ -#define XAdcPs_TemperatureToRaw(Temperature) \ - ((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f)) - -/****************************************************************************/ -/** -* -* This macro converts Voltage in Volts to XADC/ADC Raw Data. -* -* @param Voltage is the Voltage in volts to be converted to -* XADC/ADC Raw Data. -* -* @return The XADC/ADC Raw Data. -* -* @note C-Style signature: -* int XAdcPs_VoltageToRaw(float Voltage); -* -*****************************************************************************/ -#define XAdcPs_VoltageToRaw(Voltage) \ - ((int)((Voltage)*65536.0f/3.0f)) - - -/****************************************************************************/ -/** -* -* This macro is used for writing to the XADC Registers using the -* command FIFO. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* -* @return None. -* -* @note C-Style signature: -* void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data); -* -*****************************************************************************/ -#define XAdcPs_WriteFifo(InstancePtr, Data) \ - XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, \ - XADCPS_CMDFIFO_OFFSET, Data); - - -/****************************************************************************/ -/** -* -* This macro is used for reading from the XADC Registers using the -* data FIFO. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* -* @return Data read from the FIFO -* -* @note C-Style signature: -* u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr); -* -*****************************************************************************/ -#define XAdcPs_ReadFifo(InstancePtr) \ - XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress, \ - XADCPS_RDFIFO_OFFSET); - - -/************************** Function Prototypes *****************************/ - - - -/** - * Functions in xadcps_sinit.c - */ -XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId); - -/** - * Functions in xadcps.c - */ -int XAdcPs_CfgInitialize(XAdcPs *InstancePtr, - XAdcPs_Config *ConfigPtr, - u32 EffectiveAddr); - - -u32 XAdcPs_GetStatus(XAdcPs *InstancePtr); - -u32 XAdcPs_GetAlarmOutputStatus(XAdcPs *InstancePtr); - -void XAdcPs_StartAdcConversion(XAdcPs *InstancePtr); - -void XAdcPs_Reset(XAdcPs *InstancePtr); - -u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel); - -u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType); - -u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType); - -void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average); -u8 XAdcPs_GetAvg(XAdcPs *InstancePtr); - -int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr, - u8 Channel, - int IncreaseAcqCycles, - int IsEventMode, - int IsDifferentialMode); - - -void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask); -u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr); - -void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration); -u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr); - -void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode); -u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr); - -void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor); -u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr); - -int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask); -u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr); - -int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask); -u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr); - -int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask); -u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr); - -int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask); -u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr); - -void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value); -u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg); - -void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr); -void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr); - -/** - * Functions in xadcps_selftest.c - */ -int XAdcPs_SelfTest(XAdcPs *InstancePtr); - -/** - * Functions in xadcps_intr.c - */ -void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask); -void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask); -u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr); - -u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr); -void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask); - - -#ifdef __cplusplus -} -#endif - -#endif /* End of protection macro. */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xadcps_hw.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xadcps_hw.h deleted file mode 100644 index 75054277442ffdd3621266f56bcf3e97b77f2955..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xadcps_hw.h +++ /dev/null @@ -1,506 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file xadcps_hw.h -* -* This header file contains identifiers and basic driver functions (or -* macros) that can be used to access the XADC device through the Device -* Config Interface of the Zynq. -* -* -* Refer to the device specification for more information about this driver. -* -* @note None. -* -* -* <pre> -* -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ----- -------- ----------------------------------------------------- -* 1.00a bss 12/22/11 First release based on the XPS/AXI xadc driver -* -* </pre> -* -*****************************************************************************/ -#ifndef XADCPS_HW_H /* Prevent circular inclusions */ -#define XADCPS_HW_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files ********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xil_io.h" - -/************************** Constant Definitions ****************************/ - - -/**@name Register offsets of XADC in the Device Config - * - * The following constants provide access to each of the registers of the - * XADC device. - * @{ - */ - -#define XADCPS_CFG_OFFSET 0x100 /**< Configuration Register */ -#define XADCPS_INT_STS_OFFSET 0x104 /**< Interrupt Status Register */ -#define XADCPS_INT_MASK_OFFSET 0x108 /**< Interrupt Mask Register */ -#define XADCPS_MSTS_OFFSET 0x10C /**< Misc status register */ -#define XADCPS_CMDFIFO_OFFSET 0x110 /**< Command FIFO Register */ -#define XADCPS_RDFIFO_OFFSET 0x114 /**< Read FIFO Register */ -#define XADCPS_MCTL_OFFSET 0x118 /**< Misc control register */ - -/* @} */ - - - - - -/** @name XADC Config Register Bit definitions - * @{ - */ -#define XADCPS_CFG_ENABLE_MASK 0x80000000 /**< Enable access from PS mask */ -#define XADCPS_CFG_CFIFOTH_MASK 0x00F00000 /**< Command FIFO Threshold mask */ -#define XADCPS_CFG_DFIFOTH_MASK 0x000F0000 /**< Data FIFO Threshold mask */ -#define XADCPS_CFG_WEDGE_MASK 0x00002000 /**< Write Edge Mask */ -#define XADCPS_CFG_REDGE_MASK 0x00001000 /**< Read Edge Mask */ -#define XADCPS_CFG_TCKRATE_MASK 0x00000300 /**< Clock freq control */ -#define XADCPS_CFG_IGAP_MASK 0x0000001F /**< Idle Gap between - * successive commands */ -/* @} */ - - -/** @name XADC Interrupt Status/Mask Register Bit definitions - * - * The definitions are same for the Interrupt Status Register and - * Interrupt Mask Register. They are defined only once. - * @{ - */ -#define XADCPS_INTX_ALL_MASK 0x000003FF /**< Alarm Signals Mask */ -#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200 /**< CMD FIFO less than threshold */ -#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100 /**< Data FIFO greater than threshold */ -#define XADCPS_INTX_OT_MASK 0x00000080 /**< Over temperature Alarm Status */ -#define XADCPS_INTX_ALM_ALL_MASK 0x0000007F /**< Alarm Signals Mask */ -#define XADCPS_INTX_ALM6_MASK 0x00000040 /**< Alarm 6 Mask */ -#define XADCPS_INTX_ALM5_MASK 0x00000020 /**< Alarm 5 Mask */ -#define XADCPS_INTX_ALM4_MASK 0x00000010 /**< Alarm 4 Mask */ -#define XADCPS_INTX_ALM3_MASK 0x00000008 /**< Alarm 3 Mask */ -#define XADCPS_INTX_ALM2_MASK 0x00000004 /**< Alarm 2 Mask */ -#define XADCPS_INTX_ALM1_MASK 0x00000002 /**< Alarm 1 Mask */ -#define XADCPS_INTX_ALM0_MASK 0x00000001 /**< Alarm 0 Mask */ - -/* @} */ - - -/** @name XADC Miscellaneous Register Bit definitions - * @{ - */ -#define XADCPS_MSTS_CFIFO_LVL_MASK 0x000F0000 /**< Command FIFO Level mask */ -#define XADCPS_MSTS_DFIFO_LVL_MASK 0x0000F000 /**< Data FIFO Level Mask */ -#define XADCPS_MSTS_CFIFOF_MASK 0x00000800 /**< Command FIFO Full Mask */ -#define XADCPS_MSTS_CFIFOE_MASK 0x00000400 /**< Command FIFO Empty Mask */ -#define XADCPS_MSTS_DFIFOF_MASK 0x00000200 /**< Data FIFO Full Mask */ -#define XADCPS_MSTS_DFIFOE_MASK 0x00000100 /**< Data FIFO Empty Mask */ -#define XADCPS_MSTS_OT_MASK 0x00000080 /**< Over Temperature Mask */ -#define XADCPS_MSTS_ALM_MASK 0x0000007F /**< Alarms Mask */ -/* @} */ - - -/** @name XADC Miscellaneous Control Register Bit definitions - * @{ - */ -#define XADCPS_MCTL_RESET_MASK 0x00000010 /**< Reset XADC */ -#define XADCPS_MCTL_FLUSH_MASK 0x00000001 /**< Flush the FIFOs */ -/* @} */ - - -/**@name Internal Register offsets of the XADC - * - * The following constants provide access to each of the internal registers of - * the XADC device. - * @{ - */ - -/* - * XADC Internal Channel Registers - */ -#define XADCPS_TEMP_OFFSET 0x00 /**< On-chip Temperature Reg */ -#define XADCPS_VCCINT_OFFSET 0x01 /**< On-chip VCCINT Data Reg */ -#define XADCPS_VCCAUX_OFFSET 0x02 /**< On-chip VCCAUX Data Reg */ -#define XADCPS_VPVN_OFFSET 0x03 /**< ADC out of VP/VN */ -#define XADCPS_VREFP_OFFSET 0x04 /**< On-chip VREFP Data Reg */ -#define XADCPS_VREFN_OFFSET 0x05 /**< On-chip VREFN Data Reg */ -#define XADCPS_VBRAM_OFFSET 0x06 /**< On-chip VBRAM , 7 Series */ -#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET 0x08 /**< ADC A Supply Offset Reg */ -#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET 0x09 /**< ADC A Offset Data Reg */ -#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0A /**< ADC A Gain Error Reg */ -#define XADCPS_VCCPINT_OFFSET 0x0D /**< On-chip VCCPINT Reg, Zynq */ -#define XADCPS_VCCPAUX_OFFSET 0x0E /**< On-chip VCCPAUX Reg, Zynq */ -#define XADCPS_VCCPDRO_OFFSET 0x0F /**< On-chip VCCPDRO Reg, Zynq */ - -/* - * XADC External Channel Registers - */ -#define XADCPS_AUX00_OFFSET 0x10 /**< ADC out of VAUXP0/VAUXN0 */ -#define XADCPS_AUX01_OFFSET 0x11 /**< ADC out of VAUXP1/VAUXN1 */ -#define XADCPS_AUX02_OFFSET 0x12 /**< ADC out of VAUXP2/VAUXN2 */ -#define XADCPS_AUX03_OFFSET 0x13 /**< ADC out of VAUXP3/VAUXN3 */ -#define XADCPS_AUX04_OFFSET 0x14 /**< ADC out of VAUXP4/VAUXN4 */ -#define XADCPS_AUX05_OFFSET 0x15 /**< ADC out of VAUXP5/VAUXN5 */ -#define XADCPS_AUX06_OFFSET 0x16 /**< ADC out of VAUXP6/VAUXN6 */ -#define XADCPS_AUX07_OFFSET 0x17 /**< ADC out of VAUXP7/VAUXN7 */ -#define XADCPS_AUX08_OFFSET 0x18 /**< ADC out of VAUXP8/VAUXN8 */ -#define XADCPS_AUX09_OFFSET 0x19 /**< ADC out of VAUXP9/VAUXN9 */ -#define XADCPS_AUX10_OFFSET 0x1A /**< ADC out of VAUXP10/VAUXN10 */ -#define XADCPS_AUX11_OFFSET 0x1B /**< ADC out of VAUXP11/VAUXN11 */ -#define XADCPS_AUX12_OFFSET 0x1C /**< ADC out of VAUXP12/VAUXN12 */ -#define XADCPS_AUX13_OFFSET 0x1D /**< ADC out of VAUXP13/VAUXN13 */ -#define XADCPS_AUX14_OFFSET 0x1E /**< ADC out of VAUXP14/VAUXN14 */ -#define XADCPS_AUX15_OFFSET 0x1F /**< ADC out of VAUXP15/VAUXN15 */ - -/* - * XADC Registers for Maximum/Minimum data captured for the - * on chip Temperature/VCCINT/VCCAUX data. - */ -#define XADCPS_MAX_TEMP_OFFSET 0x20 /**< Max Temperature Reg */ -#define XADCPS_MAX_VCCINT_OFFSET 0x21 /**< Max VCCINT Register */ -#define XADCPS_MAX_VCCAUX_OFFSET 0x22 /**< Max VCCAUX Register */ -#define XADCPS_MAX_VCCBRAM_OFFSET 0x23 /**< Max BRAM Register, 7 series */ -#define XADCPS_MIN_TEMP_OFFSET 0x24 /**< Min Temperature Reg */ -#define XADCPS_MIN_VCCINT_OFFSET 0x25 /**< Min VCCINT Register */ -#define XADCPS_MIN_VCCAUX_OFFSET 0x26 /**< Min VCCAUX Register */ -#define XADCPS_MIN_VCCBRAM_OFFSET 0x27 /**< Min BRAM Register, 7 series */ -#define XADCPS_MAX_VCCPINT_OFFSET 0x28 /**< Max VCCPINT Register, Zynq */ -#define XADCPS_MAX_VCCPAUX_OFFSET 0x29 /**< Max VCCPAUX Register, Zynq */ -#define XADCPS_MAX_VCCPDRO_OFFSET 0x2A /**< Max VCCPDRO Register, Zynq */ -#define XADCPS_MIN_VCCPINT_OFFSET 0x2C /**< Min VCCPINT Register, Zynq */ -#define XADCPS_MIN_VCCPAUX_OFFSET 0x2D /**< Min VCCPAUX Register, Zynq */ -#define XADCPS_MIN_VCCPDRO_OFFSET 0x2E /**< Min VCCPDRO Register,Zynq */ - /* Undefined 0x2F to 0x3E */ -#define XADCPS_FLAG_OFFSET 0x3F /**< Flag Register */ - -/* - * XADC Configuration Registers - */ -#define XADCPS_CFR0_OFFSET 0x40 /**< Configuration Register 0 */ -#define XADCPS_CFR1_OFFSET 0x41 /**< Configuration Register 1 */ -#define XADCPS_CFR2_OFFSET 0x42 /**< Configuration Register 2 */ - -/* Test Registers 0x43 to 0x47 */ - -/* - * XADC Sequence Registers - */ -#define XADCPS_SEQ00_OFFSET 0x48 /**< Seq Reg 00 Adc Channel Selection */ -#define XADCPS_SEQ01_OFFSET 0x49 /**< Seq Reg 01 Adc Channel Selection */ -#define XADCPS_SEQ02_OFFSET 0x4A /**< Seq Reg 02 Adc Average Enable */ -#define XADCPS_SEQ03_OFFSET 0x4B /**< Seq Reg 03 Adc Average Enable */ -#define XADCPS_SEQ04_OFFSET 0x4C /**< Seq Reg 04 Adc Input Mode Select */ -#define XADCPS_SEQ05_OFFSET 0x4D /**< Seq Reg 05 Adc Input Mode Select */ -#define XADCPS_SEQ06_OFFSET 0x4E /**< Seq Reg 06 Adc Acquisition Select */ -#define XADCPS_SEQ07_OFFSET 0x4F /**< Seq Reg 07 Adc Acquisition Select */ - -/* - * XADC Alarm Threshold/Limit Registers (ATR) - */ -#define XADCPS_ATR_TEMP_UPPER_OFFSET 0x50 /**< Temp Upper Alarm Register */ -#define XADCPS_ATR_VCCINT_UPPER_OFFSET 0x51 /**< VCCINT Upper Alarm Reg */ -#define XADCPS_ATR_VCCAUX_UPPER_OFFSET 0x52 /**< VCCAUX Upper Alarm Reg */ -#define XADCPS_ATR_OT_UPPER_OFFSET 0x53 /**< Over Temp Upper Alarm Reg */ -#define XADCPS_ATR_TEMP_LOWER_OFFSET 0x54 /**< Temp Lower Alarm Register */ -#define XADCPS_ATR_VCCINT_LOWER_OFFSET 0x55 /**< VCCINT Lower Alarm Reg */ -#define XADCPS_ATR_VCCAUX_LOWER_OFFSET 0x56 /**< VCCAUX Lower Alarm Reg */ -#define XADCPS_ATR_OT_LOWER_OFFSET 0x57 /**< Over Temp Lower Alarm Reg */ -#define XADCPS_ATR_VBRAM_UPPER_OFFSET 0x58 /**< VBRAM Upper Alarm, 7 series */ -#define XADCPS_ATR_VCCPINT_UPPER_OFFSET 0x59 /**< VCCPINT Upper Alarm, Zynq */ -#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET 0x5A /**< VCCPAUX Upper Alarm, Zynq */ -#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET 0x5B /**< VCCPDRO Upper Alarm, Zynq */ -#define XADCPS_ATR_VBRAM_LOWER_OFFSET 0x5C /**< VRBAM Lower Alarm, 7 Series */ -#define XADCPS_ATR_VCCPINT_LOWER_OFFSET 0x5D /**< VCCPINT Lower Alarm, Zynq */ -#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET 0x5E /**< VCCPAUX Lower Alarm, Zynq */ -#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET 0x5F /**< VCCPDRO Lower Alarm, Zynq */ - -/* Undefined 0x60 to 0x7F */ - -/*@}*/ - - - -/** - * @name Configuration Register 0 (CFR0) mask(s) - * @{ - */ -#define XADCPS_CFR0_CAL_AVG_MASK 0x8000 /**< Averaging enable Mask */ -#define XADCPS_CFR0_AVG_VALID_MASK 0x3000 /**< Averaging bit Mask */ -#define XADCPS_CFR0_AVG1_MASK 0x0000 /**< No Averaging */ -#define XADCPS_CFR0_AVG16_MASK 0x1000 /**< Average 16 samples */ -#define XADCPS_CFR0_AVG64_MASK 0x2000 /**< Average 64 samples */ -#define XADCPS_CFR0_AVG256_MASK 0x3000 /**< Average 256 samples */ -#define XADCPS_CFR0_AVG_SHIFT 12 /**< Averaging bits shift */ -#define XADCPS_CFR0_MUX_MASK 0x0800 /**< External Mask Enable */ -#define XADCPS_CFR0_DU_MASK 0x0400 /**< Bipolar/Unipolar mode */ -#define XADCPS_CFR0_EC_MASK 0x0200 /**< Event driven/ - * Continuous mode selection - */ -#define XADCPS_CFR0_ACQ_MASK 0x0100 /**< Add acquisition by 6 ADCCLK */ -#define XADCPS_CFR0_CHANNEL_MASK 0x001F /**< Channel number bit Mask */ - -/*@}*/ - -/** - * @name Configuration Register 1 (CFR1) mask(s) - * @{ - */ -#define XADCPS_CFR1_SEQ_VALID_MASK 0xF000 /**< Sequence bit Mask */ -#define XADCPS_CFR1_SEQ_SAFEMODE_MASK 0x0000 /**< Default Safe Mode */ -#define XADCPS_CFR1_SEQ_ONEPASS_MASK 0x1000 /**< Onepass through Seq */ -#define XADCPS_CFR1_SEQ_CONTINPASS_MASK 0x2000 /**< Continuous Cycling Seq */ -#define XADCPS_CFR1_SEQ_SINGCHAN_MASK 0x3000 /**< Single channel - No Seq */ -#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x4000 /**< Simulataneous Sampling Mask */ -#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK 0x8000 /**< Independent Mode */ -#define XADCPS_CFR1_SEQ_SHIFT 12 /**< Sequence bit shift */ -#define XADCPS_CFR1_ALM_VCCPDRO_MASK 0x0800 /**< Alm 6 - VCCPDRO, Zynq */ -#define XADCPS_CFR1_ALM_VCCPAUX_MASK 0x0400 /**< Alm 5 - VCCPAUX, Zynq */ -#define XADCPS_CFR1_ALM_VCCPINT_MASK 0x0200 /**< Alm 4 - VCCPINT, Zynq */ -#define XADCPS_CFR1_ALM_VBRAM_MASK 0x0100 /**< Alm 3 - VBRAM, 7 series */ -#define XADCPS_CFR1_CAL_VALID_MASK 0x00F0 /**< Valid Calibration Mask */ -#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x0080 /**< Calibration 3 -Power - Supply Gain/Offset - Enable */ -#define XADCPS_CFR1_CAL_PS_OFFSET_MASK 0x0040 /**< Calibration 2 -Power - Supply Offset Enable */ -#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x0020 /**< Calibration 1 -ADC Gain - Offset Enable */ -#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK 0x0010 /**< Calibration 0 -ADC Offset - Enable */ -#define XADCPS_CFR1_CAL_DISABLE_MASK 0x0000 /**< No Calibration */ -#define XADCPS_CFR1_ALM_ALL_MASK 0x0F0F /**< Mask for all alarms */ -#define XADCPS_CFR1_ALM_VCCAUX_MASK 0x0008 /**< Alarm 2 - VCCAUX Enable */ -#define XADCPS_CFR1_ALM_VCCINT_MASK 0x0004 /**< Alarm 1 - VCCINT Enable */ -#define XADCPS_CFR1_ALM_TEMP_MASK 0x0002 /**< Alarm 0 - Temperature */ -#define XADCPS_CFR1_OT_MASK 0x0001 /**< Over Temperature Enable */ - -/*@}*/ - -/** - * @name Configuration Register 2 (CFR2) mask(s) - * @{ - */ -#define XADCPS_CFR2_CD_VALID_MASK 0xFF00 /**<Clock Divisor bit Mask */ -#define XADCPS_CFR2_CD_SHIFT 8 /**<Num of shift on division */ -#define XADCPS_CFR2_CD_MIN 8 /**<Minimum value of divisor */ -#define XADCPS_CFR2_CD_MAX 255 /**<Maximum value of divisor */ - -#define XADCPS_CFR2_CD_MIN 8 /**<Minimum value of divisor */ -#define XADCPS_CFR2_PD_MASK 0x0030 /**<Power Down Mask */ -#define XADCPS_CFR2_PD_XADC_MASK 0x0030 /**<Power Down XADC Mask */ -#define XADCPS_CFR2_PD_ADC1_MASK 0x0020 /**<Power Down ADC1 Mask */ -#define XADCPS_CFR2_PD_SHIFT 4 /**<Power Down Shift */ -/*@}*/ - -/** - * @name Sequence Register (SEQ) Bit Definitions - * @{ - */ -#define XADCPS_SEQ_CH_CALIB 0x00000001 /**< ADC Calibration Channel */ -#define XADCPS_SEQ_CH_VCCPINT 0x00000020 /**< VCCPINT, Zynq Only */ -#define XADCPS_SEQ_CH_VCCPAUX 0x00000040 /**< VCCPAUX, Zynq Only */ -#define XADCPS_SEQ_CH_VCCPDRO 0x00000080 /**< VCCPDRO, Zynq Only */ -#define XADCPS_SEQ_CH_TEMP 0x00000100 /**< On Chip Temperature Channel */ -#define XADCPS_SEQ_CH_VCCINT 0x00000200 /**< VCCINT Channel */ -#define XADCPS_SEQ_CH_VCCAUX 0x00000400 /**< VCCAUX Channel */ -#define XADCPS_SEQ_CH_VPVN 0x00000800 /**< VP/VN analog inputs Channel */ -#define XADCPS_SEQ_CH_VREFP 0x00001000 /**< VREFP Channel */ -#define XADCPS_SEQ_CH_VREFN 0x00002000 /**< VREFN Channel */ -#define XADCPS_SEQ_CH_VBRAM 0x00004000 /**< VBRAM Channel, 7 series */ -#define XADCPS_SEQ_CH_AUX00 0x00010000 /**< 1st Aux Channel */ -#define XADCPS_SEQ_CH_AUX01 0x00020000 /**< 2nd Aux Channel */ -#define XADCPS_SEQ_CH_AUX02 0x00040000 /**< 3rd Aux Channel */ -#define XADCPS_SEQ_CH_AUX03 0x00080000 /**< 4th Aux Channel */ -#define XADCPS_SEQ_CH_AUX04 0x00100000 /**< 5th Aux Channel */ -#define XADCPS_SEQ_CH_AUX05 0x00200000 /**< 6th Aux Channel */ -#define XADCPS_SEQ_CH_AUX06 0x00400000 /**< 7th Aux Channel */ -#define XADCPS_SEQ_CH_AUX07 0x00800000 /**< 8th Aux Channel */ -#define XADCPS_SEQ_CH_AUX08 0x01000000 /**< 9th Aux Channel */ -#define XADCPS_SEQ_CH_AUX09 0x02000000 /**< 10th Aux Channel */ -#define XADCPS_SEQ_CH_AUX10 0x04000000 /**< 11th Aux Channel */ -#define XADCPS_SEQ_CH_AUX11 0x08000000 /**< 12th Aux Channel */ -#define XADCPS_SEQ_CH_AUX12 0x10000000 /**< 13th Aux Channel */ -#define XADCPS_SEQ_CH_AUX13 0x20000000 /**< 14th Aux Channel */ -#define XADCPS_SEQ_CH_AUX14 0x40000000 /**< 15th Aux Channel */ -#define XADCPS_SEQ_CH_AUX15 0x80000000 /**< 16th Aux Channel */ - -#define XADCPS_SEQ00_CH_VALID_MASK 0x7FE1 /**< Mask for the valid channels */ -#define XADCPS_SEQ01_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */ - -#define XADCPS_SEQ02_CH_VALID_MASK 0x7FE0 /**< Mask for the valid channels */ -#define XADCPS_SEQ03_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */ - -#define XADCPS_SEQ04_CH_VALID_MASK 0x0800 /**< Mask for the valid channels */ -#define XADCPS_SEQ05_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */ - -#define XADCPS_SEQ06_CH_VALID_MASK 0x0800 /**< Mask for the valid channels */ -#define XADCPS_SEQ07_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */ - - -#define XADCPS_SEQ_CH_AUX_SHIFT 16 /**< Shift for the Aux Channel */ - -/*@}*/ - -/** - * @name OT Upper Alarm Threshold Register Bit Definitions - * @{ - */ - -#define XADCPS_ATR_OT_UPPER_ENB_MASK 0x000F /**< Mask for OT enable */ -#define XADCPS_ATR_OT_UPPER_VAL_MASK 0xFFF0 /**< Mask for OT value */ -#define XADCPS_ATR_OT_UPPER_VAL_SHIFT 4 /**< Shift for OT value */ -#define XADCPS_ATR_OT_UPPER_ENB_VAL 0x0003 /**< Value for OT enable */ -#define XADCPS_ATR_OT_UPPER_VAL_MAX 0x0FFF /**< Max OT value */ - -/*@}*/ - - -/** - * @name JTAG DRP Bit Definitions - * @{ - */ -#define XADCPS_JTAG_DATA_MASK 0x0000FFFF /**< Mask for the Data */ -#define XADCPS_JTAG_ADDR_MASK 0x03FF0000 /**< Mask for the Addr */ -#define XADCPS_JTAG_ADDR_SHIFT 16 /**< Shift for the Addr */ -#define XADCPS_JTAG_CMD_MASK 0x3C000000 /**< Mask for the Cmd */ -#define XADCPS_JTAG_CMD_WRITE_MASK 0x08000000 /**< Mask for CMD Write */ -#define XADCPS_JTAG_CMD_READ_MASK 0x04000000 /**< Mask for CMD Read */ -#define XADCPS_JTAG_CMD_SHIFT 26 /**< Shift for the Cmd */ - -/*@}*/ - -/** @name Unlock Register Definitions - * @{ - */ - #define XADCPS_UNLK_OFFSET 0x034 /**< Unlock Register */ - #define XADCPS_UNLK_VALUE 0x757BDF0D /**< Unlock Value */ - - /* @} */ - - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/*****************************************************************************/ -/** -* -* Read a register of the XADC device. This macro provides register -* access to all registers using the register offsets defined above. -* -* @param BaseAddress contains the base address of the device. -* @param RegOffset is the offset of the register to read. -* -* @return The contents of the register. -* -* @note C-style Signature: -* u32 XAdcPs_ReadReg(u32 BaseAddress, u32 RegOffset); -* -******************************************************************************/ -#define XAdcPs_ReadReg(BaseAddress, RegOffset) \ - (Xil_In32((BaseAddress) + (RegOffset))) - -/*****************************************************************************/ -/** -* -* Write a register of the XADC device. This macro provides -* register access to all registers using the register offsets defined above. -* -* @param BaseAddress contains the base address of the device. -* @param RegOffset is the offset of the register to write. -* @param Data is the value to write to the register. -* -* @return None. -* -* @note C-style Signature: -* void XAdcPs_WriteReg(u32 BaseAddress, -* u32 RegOffset,u32 Data) -* -******************************************************************************/ -#define XAdcPs_WriteReg(BaseAddress, RegOffset, Data) \ - (Xil_Out32((BaseAddress) + (RegOffset), (Data))) - -/************************** Function Prototypes ******************************/ - - -/*****************************************************************************/ -/** -* -* Formats the data to be written to the the XADC registers. -* -* @param RegOffset is the offset of the Register -* @param Data is the data to be written to the Register if it is -* a write. -* @param ReadWrite specifies whether it is a Read or a Write. -* Use 0 for Read, 1 for Write. -* -* @return None. -* -* @note C-style Signature: -* void XAdcPs_FormatWriteData(u32 RegOffset, -* u16 Data, int ReadWrite) -* -******************************************************************************/ -#define XAdcPs_FormatWriteData(RegOffset, Data, ReadWrite) \ - ((ReadWrite ? XADCPS_JTAG_CMD_WRITE_MASK : XADCPS_JTAG_CMD_READ_MASK ) | \ - ((RegOffset << XADCPS_JTAG_ADDR_SHIFT) & XADCPS_JTAG_ADDR_MASK) | \ - (Data & XADCPS_JTAG_DATA_MASK)) - - - -#ifdef __cplusplus -} -#endif - -#endif /* End of protection macro. */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xbasic_types.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xbasic_types.h deleted file mode 100644 index d5db3f7b04c17220dc4199eafcecd53ed5d8fb66..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xbasic_types.h +++ /dev/null @@ -1,300 +0,0 @@ -/* $Id: xbasic_types.h,v 1.19.10.4 2011/06/28 11:00:54 sadanan Exp $ */ -/****************************************************************************** -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND -* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, -* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION -* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE. -* -* (c) Copyright 2002-2007 Xilinx Inc. -* All rights reserved. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xbasic_types.h -* -* This file contains basic types for Xilinx software IP. These types do not -* follow the standard naming convention with respect to using the component -* name in front of each name because they are considered to be primitives. -* -* @note -* -* This file contains items which are architecture dependent. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.00a rmm 12/14/01 First release -* rmm 05/09/03 Added "xassert always" macros to rid ourselves of diab -* compiler warnings -* 1.00a rpm 11/07/03 Added XNullHandler function as a stub interrupt handler -* 1.00a rpm 07/21/04 Added XExceptionHandler typedef for processor exceptions -* 1.00a xd 11/03/04 Improved support for doxygen. -* 1.00a wre 01/25/07 Added Linux style data types u32, u16, u8, TRUE, FALSE -* 1.00a rpm 04/02/07 Added ifndef KERNEL around u32, u16, u8 data types -* </pre> -* -******************************************************************************/ - -#ifndef XBASIC_TYPES_H /* prevent circular inclusions */ -#define XBASIC_TYPES_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - - -/***************************** Include Files *********************************/ - - -/************************** Constant Definitions *****************************/ - -#ifndef TRUE -# define TRUE 1 -#endif - -#ifndef FALSE -# define FALSE 0 -#endif - -#ifndef NULL -#define NULL 0 -#endif - -/** Xilinx NULL, TRUE and FALSE legacy support. Deprecated. */ -#define XNULL NULL -#define XTRUE TRUE -#define XFALSE FALSE - - -#define XCOMPONENT_IS_READY 0x11111111 /**< component has been initialized */ -#define XCOMPONENT_IS_STARTED 0x22222222 /**< component has been started */ - -/* the following constants and declarations are for unit test purposes and are - * designed to be used in test applications. - */ -#define XTEST_PASSED 0 -#define XTEST_FAILED 1 - -#define XASSERT_NONE 0 -#define XASSERT_OCCURRED 1 - -extern unsigned int XAssertStatus; -extern void XAssert(char *, int); - -/**************************** Type Definitions *******************************/ - -/** @name Legacy types - * Deprecated legacy types. - * @{ - */ -typedef unsigned char Xuint8; /**< unsigned 8-bit */ -typedef char Xint8; /**< signed 8-bit */ -typedef unsigned short Xuint16; /**< unsigned 16-bit */ -typedef short Xint16; /**< signed 16-bit */ -typedef unsigned long Xuint32; /**< unsigned 32-bit */ -typedef long Xint32; /**< signed 32-bit */ -typedef float Xfloat32; /**< 32-bit floating point */ -typedef double Xfloat64; /**< 64-bit double precision FP */ -typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */ - -#if !defined __XUINT64__ -typedef struct -{ - Xuint32 Upper; - Xuint32 Lower; -} Xuint64; -#endif - -/** @name New types - * New simple types. - * @{ - */ -#ifndef __KERNEL__ -#ifndef XIL_TYPES_H -typedef Xuint32 u32; -typedef Xuint16 u16; -typedef Xuint8 u8; -#endif -#else -#include <linux/types.h> -#endif - -/*@}*/ - -/** - * This data type defines an interrupt handler for a device. - * The argument points to the instance of the component - */ -typedef void (*XInterruptHandler) (void *InstancePtr); - -/** - * This data type defines an exception handler for a processor. - * The argument points to the instance of the component - */ -typedef void (*XExceptionHandler) (void *InstancePtr); - -/** - * This data type defines a callback to be invoked when an - * assert occurs. The callback is invoked only when asserts are enabled - */ -typedef void (*XAssertCallback) (char *FilenamePtr, int LineNumber); - -/***************** Macros (Inline Functions) Definitions *********************/ - -/*****************************************************************************/ -/** -* Return the most significant half of the 64 bit data type. -* -* @param x is the 64 bit word. -* -* @return The upper 32 bits of the 64 bit word. -* -* @note None. -* -******************************************************************************/ -#define XUINT64_MSW(x) ((x).Upper) - -/*****************************************************************************/ -/** -* Return the least significant half of the 64 bit data type. -* -* @param x is the 64 bit word. -* -* @return The lower 32 bits of the 64 bit word. -* -* @note None. -* -******************************************************************************/ -#define XUINT64_LSW(x) ((x).Lower) - - -#ifndef NDEBUG - -/*****************************************************************************/ -/** -* This assert macro is to be used for functions that do not return anything -* (void). This in conjunction with the XWaitInAssert boolean can be used to -* accomodate tests so that asserts which fail allow execution to continue. -* -* @param expression is the expression to evaluate. If it evaluates to -* false, the assert occurs. -* -* @return Returns void unless the XWaitInAssert variable is true, in which -* case no return is made and an infinite loop is entered. -* -* @note None. -* -******************************************************************************/ -#define XASSERT_VOID(expression) \ -{ \ - if (expression) \ - { \ - XAssertStatus = XASSERT_NONE; \ - } \ - else \ - { \ - XAssert(__FILE__, __LINE__); \ - XAssertStatus = XASSERT_OCCURRED; \ - return; \ - } \ -} - -/*****************************************************************************/ -/** -* This assert macro is to be used for functions that do return a value. This in -* conjunction with the XWaitInAssert boolean can be used to accomodate tests so -* that asserts which fail allow execution to continue. -* -* @param expression is the expression to evaluate. If it evaluates to false, -* the assert occurs. -* -* @return Returns 0 unless the XWaitInAssert variable is true, in which case -* no return is made and an infinite loop is entered. -* -* @note None. -* -******************************************************************************/ -#define XASSERT_NONVOID(expression) \ -{ \ - if (expression) \ - { \ - XAssertStatus = XASSERT_NONE; \ - } \ - else \ - { \ - XAssert(__FILE__, __LINE__); \ - XAssertStatus = XASSERT_OCCURRED; \ - return 0; \ - } \ -} - -/*****************************************************************************/ -/** -* Always assert. This assert macro is to be used for functions that do not -* return anything (void). Use for instances where an assert should always -* occur. -* -* @return Returns void unless the XWaitInAssert variable is true, in which case -* no return is made and an infinite loop is entered. -* -* @note None. -* -******************************************************************************/ -#define XASSERT_VOID_ALWAYS() \ -{ \ - XAssert(__FILE__, __LINE__); \ - XAssertStatus = XASSERT_OCCURRED; \ - return; \ -} - -/*****************************************************************************/ -/** -* Always assert. This assert macro is to be used for functions that do return -* a value. Use for instances where an assert should always occur. -* -* @return Returns void unless the XWaitInAssert variable is true, in which case -* no return is made and an infinite loop is entered. -* -* @note None. -* -******************************************************************************/ -#define XASSERT_NONVOID_ALWAYS() \ -{ \ - XAssert(__FILE__, __LINE__); \ - XAssertStatus = XASSERT_OCCURRED; \ - return 0; \ -} - - -#else - -#define XASSERT_VOID(expression) -#define XASSERT_VOID_ALWAYS() -#define XASSERT_NONVOID(expression) -#define XASSERT_NONVOID_ALWAYS() -#endif - -/************************** Function Prototypes ******************************/ - -void XAssertSetCallback(XAssertCallback Routine); -void XNullHandler(void *NullParameter); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h deleted file mode 100644 index 0933143a44a91ebe1715c5b6f129ad3ea1df1be2..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h +++ /dev/null @@ -1,49 +0,0 @@ -/* $Id: xcpu_cortexa9.h,v 1.1.2.1 2011/02/11 09:30:37 kkatna Exp $ */ -/****************************************************************************** -* -* (c) Copyright 2011 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xcpu_cortexa9.h -* -* dummy file -* -******************************************************************************/ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xdebug.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xdebug.h deleted file mode 100644 index 8ab5e212c629109f827084c8a7202a41af4cb453..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xdebug.h +++ /dev/null @@ -1,61 +0,0 @@ -#ifndef XDEBUG -#define XDEBUG - -#undef DEBUG - -#if defined(DEBUG) && !defined(NDEBUG) - -#ifndef XDEBUG_WARNING -#define XDEBUG_WARNING -#warning DEBUG is enabled -#endif - -int printf(const char *format, ...); - -#define XDBG_DEBUG_ERROR 0x00000001 /* error condition messages */ -#define XDBG_DEBUG_GENERAL 0x00000002 /* general debug messages */ -#define XDBG_DEBUG_ALL 0xFFFFFFFF /* all debugging data */ - -#define XDBG_DEBUG_FIFO_REG 0x00000100 /* display register reads/writes */ -#define XDBG_DEBUG_FIFO_RX 0x00000101 /* receive debug messages */ -#define XDBG_DEBUG_FIFO_TX 0x00000102 /* transmit debug messages */ -#define XDBG_DEBUG_FIFO_ALL 0x0000010F /* all fifo debug messages */ - -#define XDBG_DEBUG_TEMAC_REG 0x00000400 /* display register reads/writes */ -#define XDBG_DEBUG_TEMAC_RX 0x00000401 /* receive debug messages */ -#define XDBG_DEBUG_TEMAC_TX 0x00000402 /* transmit debug messages */ -#define XDBG_DEBUG_TEMAC_ALL 0x0000040F /* all temac debug messages */ - -#define XDBG_DEBUG_TEMAC_ADPT_RX 0x00000800 /* receive debug messages */ -#define XDBG_DEBUG_TEMAC_ADPT_TX 0x00000801 /* transmit debug messages */ -#define XDBG_DEBUG_TEMAC_ADPT_IOCTL 0x00000802 /* ioctl debug messages */ -#define XDBG_DEBUG_TEMAC_ADPT_MISC 0x00000803 /* debug msg for other routines */ -#define XDBG_DEBUG_TEMAC_ADPT_ALL 0x0000080F /* all temac adapter debug messages */ - -#define xdbg_current_types (XDBG_DEBUG_ERROR) - -#define xdbg_stmnt(x) x - -/* In VxWorks, if _WRS_GNU_VAR_MACROS is defined, special syntax is needed for - * macros that accept variable number of arguments - */ -#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS) -#define xdbg_printf(type, args...) (((type) & xdbg_current_types) ? printf (## args) : 0) -#else /* ANSI Syntax */ -#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0) -#endif - -#else /* defined(DEBUG) && !defined(NDEBUG) */ - -#define xdbg_stmnt(x) - -/* See VxWorks comments above */ -#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS) -#define xdbg_printf(type, args...) -#else /* ANSI Syntax */ -#define xdbg_printf(...) -#endif - -#endif /* defined(DEBUG) && !defined(NDEBUG) */ - -#endif /* XDEBUG */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xdevcfg.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xdevcfg.h deleted file mode 100644 index 12483849643b144689b9e587b218cb4c79d47137..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xdevcfg.h +++ /dev/null @@ -1,385 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file xdevcfg.h -* -* The is the main header file for the Device Configuration Interface of the Zynq -* device. The device configuration interface has three main functionality. -* 1. AXI-PCAP -* 2. Security Policy -* 3. XADC -* This current version of the driver supports only the AXI-PCAP and Security -* Policy blocks. There is a separate driver for XADC. -* -* AXI-PCAP is used for download/upload an encrypted or decrypted bitstream. -* DMA embedded in the AXI PCAP provides the master interface to -* the Device configuration block for any DMA transfers. The data transfer can -* take place between the Tx/RxFIFOs of AXI-PCAP and memory (on chip -* RAM/DDR/peripheral memory). -* -* The current driver only supports the downloading the FPGA bitstream and -* readback of the decrypted image (sort of loopback). -* The driver does not know what information needs to be written to the FPGA to -* readback FPGA configuration register or memory data. The application above the -* driver should take care of creating the data that needs to be downloaded to -* the FPGA so that the bitstream can be readback. -* This driver also does not support the reading of the internal registers of the -* PCAP. The driver has no knowledge of the PCAP internals. -* -* <b> Initialization and Configuration </b> -* -* The device driver enables higher layer software (e.g., an application) to -* communicate with the Device Configuration device. -* -* XDcfg_CfgInitialize() API is used to initialize the Device Configuration -* Interface. The user needs to first call the XDcfg_LookupConfig() API which -* returns the Configuration structure pointer which is passed as a parameter to -* the XDcfg_CfgInitialize() API. -* -* <b>Interrupts</b> -* The Driver implements an interrupt handler to support the interrupts provided -* by this interface. -* -* <b> Threads </b> -* -* This driver is not thread safe. Any needs for threads or thread mutual -* exclusion must be satisfied by the layer above this driver. -* -* <b> Asserts </b> -* -* Asserts are used within all Xilinx drivers to enforce constraints on argument -* values. Asserts can be turned off on a system-wide basis by defining, at -* compile time, the NDEBUG identifier. By default, asserts are turned on and it -* is recommended that users leave asserts on during development. -* -* <b> Building the driver </b> -* -* The XDcfg driver is composed of several source files. This allows the user -* to build and link only those parts of the driver that are necessary. -* -* <br><br> -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- --------------------------------------------- -* 1.00a hvm 02/07/11 First release -* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for -* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer -* APIs is words (32 bit) and not bytes. -* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs -* to add information that 2 LSBs of the Source/Destination -* address when equal to 2’b01 indicate the last DMA command -* of an overall transfer. -* Destination Address passed to this API for secure transfers -* instead of using 0xFFFFFFFF for CR 662197. This issue was -* resulting in the failure of secure transfers of -* non-bitstream images. -* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly -* set the mask instead of oring it with the -* value read from the interrupt status register -* Added defines for the PS Version bits, -* removed the FIFO Flush bits from the -* Miscellaneous Control Reg. -* Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface -* and XDcfg_SelectPcapInterface APIs for CR 643295 -* The user has to call the XDcfg_SelectIcapInterface API -* for the PL reconfiguration using AXI HwIcap. -* Updated the XDcfg_Transfer API to clear the -* QUARTER_PCAP_RATE_EN bit in the control register for -* non secure writes for CR 675543. -* 2.02a nm 01/31/13 Fixed CR# 679335. -* Added Setting and Clearing the internal PCAP loopback. -* Removed code for enabling/disabling AES engine as BootROM -* locks down this setting. -* Fixed CR# 681976. -* Skip Checking the PCFG_INIT in case of non-secure DMA -* loopback. -* Fixed CR# 699558. -* XDcfg_Transfer fails to transfer data in loopback mode. -* Fixed CR# 701348. -* Peripheral test fails with Running -* DcfgSelfTestExample() in SECURE bootmode. -* 2.03a nm 04/19/13 Fixed CR# 703728. -* Updated the register definitions as per the latest TRM -* version UG585 (v1.4) November 16, 2012. -* </pre> -* -******************************************************************************/ -#ifndef XDCFG_H /* prevent circular inclusions */ -#define XDCFG_H /* by using protection macros */ - -/***************************** Include Files *********************************/ - -#include "xdevcfg_hw.h" -#include "xstatus.h" -#include "xil_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/************************** Constant Definitions *****************************/ - -/* Types of PCAP transfers */ - -#define XDCFG_NON_SECURE_PCAP_WRITE 1 -#define XDCFG_SECURE_PCAP_WRITE 2 -#define XDCFG_PCAP_READBACK 3 -#define XDCFG_CONCURRENT_SECURE_READ_WRITE 4 -#define XDCFG_CONCURRENT_NONSEC_READ_WRITE 5 - - -/**************************** Type Definitions *******************************/ -/** -* The handler data type allows the user to define a callback function to -* respond to interrupt events in the system. This function is executed -* in interrupt context, so amount of processing should be minimized. -* -* @param CallBackRef is the callback reference passed in by the upper -* layer when setting the callback functions, and passed back to -* the upper layer when the callback is invoked. Its type is -* unimportant to the driver component, so it is a void pointer. -* @param Status is the Interrupt status of the XDcfg device. -*/ -typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status); - -/** - * This typedef contains configuration information for the device. - */ -typedef struct { - u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddr; /**< Base address of the device */ -} XDcfg_Config; - -/** - * The XDcfg driver instance data. - */ -typedef struct { - XDcfg_Config Config; /**< Hardware Configuration */ - u32 IsReady; /**< Device is initialized and ready */ - u32 IsStarted; /**< Device Configuration Interface - * is running - */ - XDcfg_IntrHandler StatusHandler; /* Event handler function */ - void *CallBackRef; /* Callback reference for event handler */ -} XDcfg; - -/****************************************************************************/ -/** -* -* Unlock the Device Config Interface block. -* -* @param InstancePtr is a pointer to the instance of XDcfg driver. -* -* @return None. -* -* @note C-style signature: -* void XDcfg_Unlock(XDcfg* InstancePtr) -* -*****************************************************************************/ -#define XDcfg_Unlock(InstancePtr) \ - XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \ - XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA) - - - -/****************************************************************************/ -/** -* -* Get the version number of the PS from the Miscellaneous Control Register. -* -* @param InstancePtr is a pointer to the instance of XDcfg driver. -* -* @return Version of the PS. -* -* @note C-style signature: -* void XDcfg_GetPsVersion(XDcfg* InstancePtr) -* -*****************************************************************************/ -#define XDcfg_GetPsVersion(InstancePtr) \ - ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \ - XDCFG_MCTRL_OFFSET)) & \ - XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \ - XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT - - - -/****************************************************************************/ -/** -* -* Read the multiboot config register value. -* -* @param InstancePtr is a pointer to the instance of XDcfg driver. -* -* @return None. -* -* @note C-style signature: -* u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr) -* -*****************************************************************************/ -#define XDcfg_ReadMultiBootConfig(InstancePtr) \ - XDcfg_ReadReg((InstancePtr)->Config.BaseAddr + \ - XDCFG_MULTIBOOT_ADDR_OFFSET) - - -/****************************************************************************/ -/** -* -* Selects ICAP interface for reconfiguration after the initial configuration -* of the PL. -* -* @param InstancePtr is a pointer to the instance of XDcfg driver. -* -* @return None. -* -* @note C-style signature: -* void XDcfg_SelectIcapInterface(XDcfg* InstancePtr) -* -*****************************************************************************/ -#define XDcfg_SelectIcapInterface(InstancePtr) \ - XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \ - ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \ - & ( ~XDCFG_CTRL_PCAP_PR_MASK))) - -/****************************************************************************/ -/** -* -* Selects PCAP interface for reconfiguration after the initial configuration -* of the PL. -* -* @param InstancePtr is a pointer to the instance of XDcfg driver. -* -* @return None. -* -* @note C-style signature: -* void XDcfg_SelectPcapInterface(XDcfg* InstancePtr) -* -*****************************************************************************/ -#define XDcfg_SelectPcapInterface(InstancePtr) \ - XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \ - ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \ - | XDCFG_CTRL_PCAP_PR_MASK)) - - - -/************************** Function Prototypes ******************************/ - -/* - * Lookup configuration in xdevcfg_sinit.c. - */ -XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId); - -/* - * Selftest function in xdevcfg_selftest.c - */ -int XDcfg_SelfTest(XDcfg *InstancePtr); - -/* - * Interface functions in xdevcfg.c - */ -int XDcfg_CfgInitialize(XDcfg *InstancePtr, - XDcfg_Config *ConfigPtr, u32 EffectiveAddress); - -void XDcfg_EnablePCAP(XDcfg *InstancePtr); - -void XDcfg_DisablePCAP(XDcfg *InstancePtr); - -void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask); - -u32 XDcfg_GetControlRegister(XDcfg *InstancePtr); - -void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data); - -u32 XDcfg_GetLockRegister(XDcfg *InstancePtr); - -void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data); - -u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr); - -void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data); - -u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr); - -void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data); - -u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr); - -void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask); - -u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr); - -u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr); - -void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr, - u32 SrcWordLength, u32 DestWordLength); - -u32 XDcfg_Transfer(XDcfg *InstancePtr, - void *SourcePtr, u32 SrcWordLength, - void *DestPtr, u32 DestWordLength, - u32 TransferType); - -/* - * Interrupt related function prototypes implemented in xdevcfg_intr.c - */ -void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask); - -void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask); - -u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr); - -u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr); - -void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask); - -void XDcfg_InterruptHandler(XDcfg *InstancePtr); - -void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc, - void *CallBackRef); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h deleted file mode 100644 index ccac60abb236e8f028cc7ee68b8042ca44cc6ca0..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h +++ /dev/null @@ -1,400 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file xdevcfg_hw.h -* -* This file contains the hardware interface to the Device Config Interface. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- --------------------------------------------- -* 1.00a hvm 02/07/11 First release -* 2.01a nm 08/01/12 Added defines for the PS Version bits, -* removed the FIFO Flush bits from the -* Miscellaneous Control Reg -* 2.03a nm 04/19/13 Fixed CR# 703728. -* Updated the register definitions as per the latest TRM -* version UG585 (v1.4) November 16, 2012. -* 2.04a kpc 10/07/13 Added function prototype. -* </pre> -* -******************************************************************************/ -#ifndef XDCFG_HW_H /* prevent circular inclusions */ -#define XDCFG_HW_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_io.h" - -/************************** Constant Definitions *****************************/ - -/** @name Register Map - * Offsets of registers from the start of the device - * @{ - */ - -#define XDCFG_CTRL_OFFSET 0x00 /**< Control Register */ -#define XDCFG_LOCK_OFFSET 0x04 /**< Lock Register */ -#define XDCFG_CFG_OFFSET 0x08 /**< Configuration Register */ -#define XDCFG_INT_STS_OFFSET 0x0C /**< Interrupt Status Register */ -#define XDCFG_INT_MASK_OFFSET 0x10 /**< Interrupt Mask Register */ -#define XDCFG_STATUS_OFFSET 0x14 /**< Status Register */ -#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**< DMA Source Address Register */ -#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**< DMA Destination Address Reg */ -#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**< DMA Source Transfer Length */ -#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**< DMA Destination Transfer */ -#define XDCFG_ROM_SHADOW_OFFSET 0x28 /**< DMA ROM Shadow Register */ -#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**< Multi BootAddress Pointer */ -#define XDCFG_SW_ID_OFFSET 0x30 /**< Software ID Register */ -#define XDCFG_UNLOCK_OFFSET 0x34 /**< Unlock Register */ -#define XDCFG_MCTRL_OFFSET 0x80 /**< Miscellaneous Control Reg */ - -/* @} */ - -/** @name Control Register Bit definitions - * @{ - */ - -#define XDCFG_CTRL_FORCE_RST_MASK 0x80000000 /**< Force into - * Secure Reset - */ -#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /**< Program signal to - * Reset FPGA - */ -#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */ -#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /**< Enable PCAP for PR */ -#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /**< Enable PCAP */ -#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /**< Enable PCAP send data - * to FPGA every 4 PCAP - * cycles - */ -#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000 /**< Multiboot Enable */ -#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000 /**< JTAG Chain Disable */ -#define XDCFG_CTRL_USER_MODE_MASK 0x00008000 /**< User Mode Mask */ -#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000 /**< AES key source */ -#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**< AES Enable Mask */ -#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /**< SEU Enable Mask */ -#define XDCFG_CTRL_SEC_EN_MASK 0x00000080 /**< Secure/Non Secure - * Status mask - */ -#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /**< Secure Non Invasive - * Debug Enable - */ -#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /**< Secure Invasive - * Debug Enable - */ -#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /**< Non-Invasive Debug - * Enable - */ -#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /**< Invasive Debug - * Enable - */ -#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /**< DAP Enable Mask */ - -/* @} */ - -/** @name Lock register bit definitions - * @{ - */ - -#define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010 /**< Lock AES Efuse bit */ -#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /**< Lock AES_EN update */ -#define XDCFG_LOCK_SEU_MASK 0x00000004 /**< Lock SEU_En update */ -#define XDCFG_LOCK_SEC_MASK 0x00000002 /**< Lock SEC_EN and - * USER_MODE - */ -#define XDCFG_LOCK_DBG_MASK 0x00000001 /**< This bit locks - * security config - * including: DAP_En, - * DBGEN,, - * NIDEN, SPNIEN - */ -/*@}*/ - - - -/** @name Config Register Bit definitions - * @{ - */ -#define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00 /**< Read FIFO - * Threshold Mask - */ -#define XDCFG_CFG_WFIFO_TH_MASK 0x00000300 /**< Write FIFO Threshold - * Mask - */ -#define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080 /**< Read data active - * clock edge - */ -#define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040 /**< Write data active - * clock edge - */ -#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020 /**< Disable Source address - * increment mask - */ -#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010 /**< Disable Destination - * address increment - * mask - */ -/* @} */ - - -/** @name Interrupt Status/Mask Register Bit definitions - * @{ - */ -#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000 /**< Tri-state IO during - * HIZ - */ -#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000 /**< First configuration - * done - */ -#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000 /**< Global power down */ -#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000 /**< Tri-state IO during - * configuration - */ -#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000 /**< PL configuration - * reset - */ -#define XDCFG_IXR_AXI_WTO_MASK 0x00800000 /**< AXI Write Address - * or Data or response - * timeout - */ -#define XDCFG_IXR_AXI_WERR_MASK 0x00400000 /**< AXI Write response - * error - */ -#define XDCFG_IXR_AXI_RTO_MASK 0x00200000 /**< AXI Read Address or - * response timeout - */ -#define XDCFG_IXR_AXI_RERR_MASK 0x00100000 /**< AXI Read response - * error - */ -#define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000 /**< Rx FIFO Overflow */ -#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000 /**< Tx FIFO less than - * threshold */ -#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000 /**< Rx FIFO greater than - * threshold */ -#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000 /**< Illegal DMA command */ -#define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000 /**< DMA command queue - * overflow - */ -#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /**< DMA Command Done */ -#define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /**< DMA and PCAP - * transfers Done - */ -#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800 /**< PCAP to DMA transfer - * length error - */ -#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040 /**< HMAC error mask */ -#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020 /**< SEU Error mask */ -#define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010 /**< FPGA POR mask */ -#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008 /**< FPGA Reset mask */ -#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /**< Done Signal Mask */ -#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002 /**< Detect Positive edge - * of Init Signal - */ -#define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001 /**< Detect Negative edge - * of Init Signal - */ -#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \ - XDCFG_IXR_AXI_WERR_MASK | \ - XDCFG_IXR_AXI_RTO_MASK | \ - XDCFG_IXR_AXI_RERR_MASK | \ - XDCFG_IXR_RX_FIFO_OV_MASK | \ - XDCFG_IXR_DMA_CMD_ERR_MASK |\ - XDCFG_IXR_DMA_Q_OV_MASK | \ - XDCFG_IXR_P2D_LEN_ERR_MASK |\ - XDCFG_IXR_PCFG_HMAC_ERR_MASK) - - -#define XDCFG_IXR_ALL_MASK 0x00F7F8EF - - - -/* @} */ - - -/** @name Status Register Bit definitions - * @{ - */ -#define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000 /**< DMA command - * Queue full - */ -#define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000 /**< DMA command - * Queue empty - */ -#define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 /**< Number of - * completed DMA - * transfers - */ -#define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000 /**< Rx FIFO level */ -#define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000 /**< Tx FIFO level */ - -#define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800 /**< Tri-state IO - * during HIZ - */ -#define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400 /**< First PL config - * done - */ -#define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200 /**< Global power down */ -#define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100 /**< Tri-state IO during - * config - */ -#define XDCFG_STATUS_SECURE_RST_MASK 0x00000080 /**< Secure Reset - * POR Status - */ -#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040 /**< Illegal APB - * access - */ -#define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020 /**< PL config - * reset status - */ -#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /**< FPGA Init - * Status - */ -#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008 - /**< BBRAM key - * disable - */ -#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security - * Enable Status - */ -#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002 /**< EFuse JTAG - * Disable - * status - */ -/* @} */ - - -/** @name DMA Source/Destination Transfer Length Register Bit definitions - * @{ - */ -#define XDCFG_DMA_LEN_MASK 0x7FFFFFF /**< Length Mask */ -/*@}*/ - - - - -/** @name Miscellaneous Control Register Bit definitions - * @{ - */ -#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000 /**< PS Version Mask */ -#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28 /**< PS Version Shift */ -#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /**< PCAP loopback mask */ -/* @} */ - -/** @name FIFO Threshold Bit definitions - * @{ - */ - -#define XDCFG_CFG_FIFO_QUARTER 0x0 /**< Quarter empty */ -#define XDCFG_CFG_FIFO_HALF 0x1 /**< Half empty */ -#define XDCFG_CFG_FIFO_3QUARTER 0x2 /**< 3/4 empty */ -#define XDCFG_CFG_FIFO_EMPTY 0x4 /**< Empty */ -/* @}*/ - - -/* Miscellaneous constant values */ -#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /**< Invalid DMA address */ -#define XDCFG_UNLOCK_DATA 0x757BDF0D /**< First APB access data*/ -#define XDCFG_BASE_ADDRESS 0xFE007000 /**< Device Config base - * address - */ -#define XDCFG_CONFIG_RESET_VALUE 0x508 /**< Config reg reset value */ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/****************************************************************************/ -/** -* -* Read the given register. -* -* @param BaseAddr is the base address of the device -* @param RegOffset is the register offset to be read -* -* @return The 32-bit value of the register -* -* @note C-style signature: -* u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset) -* -*****************************************************************************/ -#define XDcfg_ReadReg(BaseAddr, RegOffset) \ - Xil_In32((BaseAddr) + (RegOffset)) - -/****************************************************************************/ -/** -* -* Write to the given register. -* -* @param BaseAddr is the base address of the device -* @param RegOffset is the register offset to be written -* @param Data is the 32-bit value to write to the register -* -* @return None. -* -* @note C-style signature: -* void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data) -* -*****************************************************************************/ -#define XDcfg_WriteReg(BaseAddr, RegOffset, Data) \ - Xil_Out32((BaseAddr) + (RegOffset), (Data)) - -/************************** Function Prototypes ******************************/ -/* - * Perform reset operation to the devcfg interface - */ -void XDcfg_ResetHw(u32 BaseAddr); -/************************** Variable Definitions *****************************/ - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xdmaps.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xdmaps.h deleted file mode 100644 index f44608a07cf2ada6bee70823e986aefcc8172975..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xdmaps.h +++ /dev/null @@ -1,317 +0,0 @@ -/***************************************************************************** -* -* (c) Copyright 2009-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -*****************************************************************************/ -/****************************************************************************/ -/** -* -* @file xdmaps.h -* -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------ -------- ---------------------------------------------- -* 1.00 hbm 08/19/10 First Release -* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies -* the maximum number of channels. -* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV -* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h. -* Added the tcl file to automatically generate the -* xparameters.h -* 1.02a sg 05/16/12 Made changes for doxygen and moved some function -* header from the xdmaps.h file to xdmaps.c file -* Other cleanup for coding guidelines and CR 657109 -* and CR 657898 -* The xdmaps_example_no_intr.c example is removed -* as it is using interrupts and is similar to -* the interrupt example - CR 652477 -* 1.03a sg 07/16/2012 changed inline to __inline for CR665681 -* 1.04a nm 10/22/2012 Fixed CR# 681671. -* 1.05a nm 04/15/2013 Fixed CR# 704396. Removed warnings when compiled -* with -Wall and -Wextra option in bsp. -* 05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg() -* function description. -* Fixed CR# 704396. Removed unused variables -* UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg() -* function. -* </pre> -* -*****************************************************************************/ - -#ifndef XDMAPS_H /* prevent circular inclusions */ -#define XDMAPS_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files ********************************/ - -#include "xparameters.h" -#include "xil_types.h" -#include "xil_assert.h" -#include "xstatus.h" - -#include "xdmaps_hw.h" - -/************************** Constant Definitions ****************************/ - -/**************************** Type Definitions ******************************/ - -/** - * This typedef contains configuration information for the device. - */ -typedef struct { - u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddress; /**< Base address of device (IPIF) */ -} XDmaPs_Config; - - -/** DMA channle control structure. It's for AXI bus transaction. - * This struct will be translated into a 32-bit channel control register value. - */ -typedef struct { - unsigned int EndianSwapSize; /**< Endian swap size. */ - unsigned int DstCacheCtrl; /**< Destination cache control */ - unsigned int DstProtCtrl; /**< Destination protection control */ - unsigned int DstBurstLen; /**< Destination burst length */ - unsigned int DstBurstSize; /**< Destination burst size */ - unsigned int DstInc; /**< Destination incrementing or fixed - * address */ - unsigned int SrcCacheCtrl; /**< Source cache control */ - unsigned int SrcProtCtrl; /**< Source protection control */ - unsigned int SrcBurstLen; /**< Source burst length */ - unsigned int SrcBurstSize; /**< Source burst size */ - unsigned int SrcInc; /**< Source incrementing or fixed - * address */ -} XDmaPs_ChanCtrl; - -/** DMA block descriptor stucture. - */ -typedef struct { - u32 SrcAddr; /**< Source starting address */ - u32 DstAddr; /**< Destination starting address */ - unsigned int Length; /**< Number of bytes for the block */ -} XDmaPs_BD; - -/** - * A DMA command consisits of a channel control struct, a block descriptor, - * a user defined program, a pointer pointing to generated DMA program, and - * execution result. - * - */ -typedef struct { - XDmaPs_ChanCtrl ChanCtrl; /**< Channel Control Struct */ - XDmaPs_BD BD; /**< Together with SgLength field, - * it's a scatter-gather list. - */ - void *UserDmaProg; /**< If user wants the driver to - * execute their own DMA program, - * this field points to the DMA - * program. - */ - int UserDmaProgLength; /**< The length of user defined - * DMA program. - */ - - void *GeneratedDmaProg; /**< The DMA program genreated - * by the driver. This field will be - * set if a user invokes the DMA - * program generation function. Or - * the DMA command is finished and - * a user informs the driver not to - * release the program buffer. - * This field has two purposes, one - * is to ask the driver to generate - * a DMA program while the DMAC is - * performaning DMA transactions. The - * other purpose is to debug the - * driver. - */ - int GeneratedDmaProgLength; /**< The length of the DMA program - * generated by the driver - */ - int DmaStatus; /**< 0 on success, otherwise error code - */ - u32 ChanFaultType; /**< Channel fault type in case of fault - */ - u32 ChanFaultPCAddr; /**< Channel fault PC address - */ -} XDmaPs_Cmd; - -/** - * It's the done handler a user can set for a channel - */ -typedef void (*XDmaPsDoneHandler) (unsigned int Channel, - XDmaPs_Cmd *DmaCmd, - void *CallbackRef); - -/** - * It's the fault handler a user can set for a channel - */ -typedef void (*XDmaPsFaultHandler) (unsigned int Channel, - XDmaPs_Cmd *DmaCmd, - void *CallbackRef); - -#define XDMAPS_MAX_CHAN_BUFS 2 -#define XDMAPS_CHAN_BUF_LEN 128 - -/** - * The XDmaPs_ProgBuf is the struct for a DMA program buffer. - */ -typedef struct { - char Buf[XDMAPS_CHAN_BUF_LEN]; /**< The actual buffer the holds the - * content */ - unsigned Len; /**< The actual length of the DMA - * program in bytes. */ - int Allocated; /**< A tag indicating whether the - * buffer is allocated or not */ -} XDmaPs_ProgBuf; - -/** - * The XDmaPs_ChannelData is a struct to book keep individual channel of - * the DMAC. - */ -typedef struct { - unsigned DevId; /**< Device id indicating which DMAC */ - unsigned ChanId; /**< Channel number of the DMAC */ - XDmaPs_ProgBuf ProgBufPool[XDMAPS_MAX_CHAN_BUFS]; /**< A pool of - program buffers*/ - XDmaPsDoneHandler DoneHandler; /**< Done interrupt handler */ - void *DoneRef; /**< Done interrupt callback data */ - XDmaPs_Cmd *DmaCmdToHw; /**< DMA command being executed */ - XDmaPs_Cmd *DmaCmdFromHw; /**< DMA command that is finished. - * This field is for debugging purpose - */ - int HoldDmaProg; /**< A tag indicating whether to hold the - * DMA program after the DMA is done. - */ - -} XDmaPs_ChannelData; - -/** - * The XDmaPs driver instance data structure. A pointer to an instance data - * structure is passed around by functions to refer to a specific driver - * instance. - */ -typedef struct { - XDmaPs_Config Config; /**< Configuration data structure */ - int IsReady; /**< Device is Ready */ - int CacheLength; /**< icache length */ - XDmaPsFaultHandler FaultHandler; /**< fault interrupt handler */ - void *FaultRef; /**< fault call back data */ - XDmaPs_ChannelData Chans[XDMAPS_CHANNELS_PER_DEV]; - /**< - * channel data - */ -} XDmaPs; - -/* - * Functions implemented in xdmaps.c - */ -int XDmaPs_CfgInitialize(XDmaPs *InstPtr, - XDmaPs_Config *Config, - u32 EffectiveAddr); - -int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel, - XDmaPs_Cmd *Cmd, - int HoldDmaProg); - -int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel); -int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel, - XDmaPs_Cmd *Cmd); -int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel, - XDmaPs_Cmd *Cmd); -void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd); - - -int XDmaPs_ResetManager(XDmaPs *InstPtr); -int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel); - - -int XDmaPs_SetDoneHandler(XDmaPs *InstPtr, - unsigned Channel, - XDmaPsDoneHandler DoneHandler, - void *CallbackRef); - -int XDmaPs_SetFaultHandler(XDmaPs *InstPtr, - XDmaPsFaultHandler FaultHandler, - void *CallbackRef); - -void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd); - -/** - * Driver done interrupt service routines for the channels. - * We need this done ISR mainly because the driver needs to release the - * DMA program buffer. This is the one that connects the GIC - */ -void XDmaPs_DoneISR_0(XDmaPs *InstPtr); -void XDmaPs_DoneISR_1(XDmaPs *InstPtr); -void XDmaPs_DoneISR_2(XDmaPs *InstPtr); -void XDmaPs_DoneISR_3(XDmaPs *InstPtr); -void XDmaPs_DoneISR_4(XDmaPs *InstPtr); -void XDmaPs_DoneISR_5(XDmaPs *InstPtr); -void XDmaPs_DoneISR_6(XDmaPs *InstPtr); -void XDmaPs_DoneISR_7(XDmaPs *InstPtr); - -/** - * Driver fault interrupt service routine - */ -void XDmaPs_FaultISR(XDmaPs *InstPtr); - - -/* - * Static loopup function implemented in xdmaps_sinit.c - */ -XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId); - - -/* - * self-test functions in xdmaps_selftest.c - */ -int XDmaPs_SelfTest(XDmaPs *InstPtr); - - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xdmaps_hw.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xdmaps_hw.h deleted file mode 100644 index 1fc33e547f42af3c5b9873114aa7a5de4c46cc55..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xdmaps_hw.h +++ /dev/null @@ -1,299 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xdmaps_hw.h -* -* This header file contains the hardware interface of an XDmaPs device. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ---------------------------------------------- -* 1.00a hbm 08/18/10 First Release -* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies -* the maximum number of channels. -* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV -* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h -* 1.02a sg 05/16/12 Made changes for doxygen -* 1.06a kpc 07/10/13 Added function prototype -* </pre> -* -******************************************************************************/ - -#ifndef XDMAPS_HW_H /* prevent circular inclusions */ -#define XDMAPS_HW_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xil_io.h" - -/************************** Constant Definitions *****************************/ - -/** @name Register Map - * - * Register offsets for the DMAC. - * @{ - */ - -#define XDMAPS_DS_OFFSET 0x000 /* DMA Status Register */ -#define XDMAPS_DPC_OFFSET 0x004 /* DMA Program Counter Rregister */ -#define XDMAPS_INTEN_OFFSET 0X020 /* DMA Interrupt Enable Register */ -#define XDMAPS_ES_OFFSET 0x024 /* DMA Event Status Register */ -#define XDMAPS_INTSTATUS_OFFSET 0x028 /* DMA Interrupt Status Register - */ -#define XDMAPS_INTCLR_OFFSET 0x02c /* DMA Interrupt Clear Register */ -#define XDMAPS_FSM_OFFSET 0x030 /* DMA Fault Status DMA Manager - * Register - */ -#define XDMAPS_FSC_OFFSET 0x034 /* DMA Fault Status DMA Chanel Register - */ -#define XDMAPS_FTM_OFFSET 0x038 /* DMA Fault Type DMA Manager Register */ - -#define XDMAPS_FTC0_OFFSET 0x040 /* DMA Fault Type for DMA Channel 0 */ -/* - * The offset for the rest of the FTC registers is calculated as - * FTC0 + dev_chan_num * 4 - */ -#define XDmaPs_FTCn_OFFSET(ch) (XDMAPS_FTC0_OFFSET + (ch) * 4) - -#define XDMAPS_CS0_OFFSET 0x100 /* Channel Status for DMA Channel 0 */ -/* - * The offset for the rest of the CS registers is calculated as - * CS0 + * dev_chan_num * 0x08 - */ -#define XDmaPs_CSn_OFFSET(ch) (XDMAPS_CS0_OFFSET + (ch) * 8) - -#define XDMAPS_CPC0_OFFSET 0x104 /* Channel Program Counter for DMA - * Channel 0 - */ -/* - * The offset for the rest of the CPC registers is calculated as - * CPC0 + dev_chan_num * 0x08 - */ -#define XDmaPs_CPCn_OFFSET(ch) (XDMAPS_CPC0_OFFSET + (ch) * 8) - -#define XDMAPS_SA_0_OFFSET 0x400 /* Source Address Register for DMA - * Channel 0 - */ -/* The offset for the rest of the SA registers is calculated as - * SA_0 + dev_chan_num * 0x20 - */ -#define XDmaPs_SA_n_OFFSET(ch) (XDMAPS_SA_0_OFFSET + (ch) * 0x20) - -#define XDMAPS_DA_0_OFFSET 0x404 /* Destination Address Register for - * DMA Channel 0 - */ -/* The offset for the rest of the DA registers is calculated as - * DA_0 + dev_chan_num * 0x20 - */ -#define XDmaPs_DA_n_OFFSET(ch) (XDMAPS_DA_0_OFFSET + (ch) * 0x20) - -#define XDMAPS_CC_0_OFFSET 0x408 /* Channel Control Register for - * DMA Channel 0 - */ -/* - * The offset for the rest of the CC registers is calculated as - * CC_0 + dev_chan_num * 0x20 - */ -#define XDmaPs_CC_n_OFFSET(ch) (XDMAPS_CC_0_OFFSET + (ch) * 0x20) - -#define XDMAPS_LC0_0_OFFSET 0x40C /* Loop Counter 0 for DMA Channel 0 */ -/* - * The offset for the rest of the LC0 registers is calculated as - * LC_0 + dev_chan_num * 0x20 - */ -#define XDmaPs_LC0_n_OFFSET(ch) (XDMAPS_LC0_0_OFFSET + (ch) * 0x20) -#define XDMAPS_LC1_0_OFFSET 0x410 /* Loop Counter 1 for DMA Channel 0 */ -/* - * The offset for the rest of the LC1 registers is calculated as - * LC_0 + dev_chan_num * 0x20 - */ -#define XDmaPs_LC1_n_OFFSET(ch) (XDMAPS_LC1_0_OFFSET + (ch) * 0x20) - -#define XDMAPS_DBGSTATUS_OFFSET 0xD00 /* Debug Status Register */ -#define XDMAPS_DBGCMD_OFFSET 0xD04 /* Debug Command Register */ -#define XDMAPS_DBGINST0_OFFSET 0xD08 /* Debug Instruction 0 Register */ -#define XDMAPS_DBGINST1_OFFSET 0xD0C /* Debug Instruction 1 Register */ - -#define XDMAPS_CR0_OFFSET 0xE00 /* Configuration Register 0 */ -#define XDMAPS_CR1_OFFSET 0xE04 /* Configuration Register 1 */ -#define XDMAPS_CR2_OFFSET 0xE08 /* Configuration Register 2 */ -#define XDMAPS_CR3_OFFSET 0xE0C /* Configuration Register 3 */ -#define XDMAPS_CR4_OFFSET 0xE10 /* Configuration Register 4 */ -#define XDMAPS_CRDN_OFFSET 0xE14 /* Configuration Register Dn */ - -#define XDMAPS_PERIPH_ID_0_OFFSET 0xFE0 /* Peripheral Identification - * Register 0 - */ -#define XDMAPS_PERIPH_ID_1_OFFSET 0xFE4 /* Peripheral Identification - * Register 1 - */ -#define XDMAPS_PERIPH_ID_2_OFFSET 0xFE8 /* Peripheral Identification - * Register 2 - */ -#define XDMAPS_PERIPH_ID_3_OFFSET 0xFEC /* Peripheral Identification - * Register 3 - */ -#define XDMAPS_PCELL_ID_0_OFFSET 0xFF0 /* PrimeCell Identification - * Register 0 - */ -#define XDMAPS_PCELL_ID_1_OFFSET 0xFF4 /* PrimeCell Identification - * Register 1 - */ -#define XDMAPS_PCELL_ID_2_OFFSET 0xFF8 /* PrimeCell Identification - * Register 2 - */ -#define XDMAPS_PCELL_ID_3_OFFSET 0xFFC /* PrimeCell Identification - * Register 3 - */ - -/* - * Some useful register masks - */ -#define XDMAPS_DS_DMA_STATUS 0x0F /* DMA status mask */ -#define XDMAPS_DS_DMA_STATUS_STOPPED 0x00 /* debug status busy mask */ - -#define XDMAPS_DBGSTATUS_BUSY 0x01 /* debug status busy mask */ - -#define XDMAPS_CS_ACTIVE_MASK 0x07 /* channel status active mask, - * llast 3 bits of CS register - */ - -#define XDMAPS_CR1_I_CACHE_LEN_MASK 0x07 /* i_cache_len mask */ - - -/* - * XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register. - * @b1: Instruction byte 1 - * @b0: Instruction byte 0 - * @ch: Channel number - * @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel - */ -#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \ - (((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1))) - -/* @} */ - -/** @name Control Register - * - * The Control register (CR) controls the major functions of the device. - * - * Control Register Bit Definition - */ - -/* @}*/ - - -#define XDMAPS_CHANNELS_PER_DEV 8 - - -/** @name Mode Register - * - * The mode register (MR) defines the mode of transfer as well as the data - * format. If this register is modified during transmission or reception, - * data validity cannot be guaranteed. - * - * Mode Register Bit Definition - * @{ - */ - -/* @} */ - - -/** @name Interrupt Registers - * - * Interrupt control logic uses the interrupt enable register (IER) and the - * interrupt disable register (IDR) to set the value of the bits in the - * interrupt mask register (IMR). The IMR determines whether to pass an - * interrupt to the interrupt status register (ISR). - * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an - * interrupt. IMR and ISR are read only, and IER and IDR are write only. - * Reading either IER or IDR returns 0x00. - * - * All four registers have the same bit definitions. - * - * @{ - */ - -/* @} */ -#define XDMAPS_INTCLR_ALL_MASK 0xFF - -#define XDmaPs_ReadReg(BaseAddress, RegOffset) \ - Xil_In32((BaseAddress) + (RegOffset)) - -/***************************************************************************/ -/** -* Write a DMAC register. -* -* @param BaseAddress contains the base address of the device. -* @param RegOffset contains the offset from the base address of the device. -* @param RegisterValue is the value to be written to the register. -* -* @return None. -* -* @note -* C-Style signature: -* void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset, -* u32 RegisterValue) -******************************************************************************/ -#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ - Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue)) -/************************** Variable Definitions *****************************/ - -/************************** Function Prototypes *****************************/ -/* - * Perform reset operation to the dmaps interface - */ -void XDmaPs_ResetHw(u32 BaseAddr); -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xemacps.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xemacps.h deleted file mode 100644 index 81e750c06c82484285dc6b1e48f75ad0593875f7..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xemacps.h +++ /dev/null @@ -1,716 +0,0 @@ -/***************************************************************************** -* -* (c) Copyright 2010-11 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -*****************************************************************************/ -/****************************************************************************/ -/** - * - * @file xemacps.h - * - * The Xilinx Embedded Processor Block Ethernet driver. - * - * For a full description of XEMACPS features, please see the hardware spec. - * This driver supports the following features: - * - Memory mapped access to host interface registers - * - Statistics counter registers for RMON/MIB - * - API for interrupt driven frame transfers for hardware configured DMA - * - Virtual memory support - * - Unicast, broadcast, and multicast receive address filtering - * - Full and half duplex operation - * - Automatic PAD & FCS insertion and stripping - * - Flow control - * - Support up to four 48bit addresses - * - Address checking for four specific 48bit addresses - * - VLAN frame support - * - Pause frame support - * - Large frame support up to 1536 bytes - * - Checksum offload - * - * <b>Driver Description</b> - * - * The device driver enables higher layer software (e.g., an application) to - * communicate to the XEmacPs. The driver handles transmission and reception - * of Ethernet frames, as well as configuration and control. No pre or post - * processing of frame data is performed. The driver does not validate the - * contents of an incoming frame in addition to what has already occurred in - * hardware. - * A single device driver can support multiple devices even when those devices - * have significantly different configurations. - * - * <b>Initialization & Configuration</b> - * - * The XEmacPs_Config structure is used by the driver to configure itself. - * This configuration structure is typically created by the tool-chain based - * on hardware build properties. - * - * The driver instance can be initialized in - * - * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a - * configuration structure provided by the caller. If running in a system - * with address translation, the provided virtual memory base address - * replaces the physical address present in the configuration structure. - * - * The device supports DMA only as current development plan. No FIFO mode is - * supported. The driver expects to start the DMA channels and expects that - * the user has set up the buffer descriptor lists. - * - * <b>Interrupts and Asynchronous Callbacks</b> - * - * The driver has no dependencies on the interrupt controller. When an - * interrupt occurs, the handler will perform a small amount of - * housekeeping work, determine the source of the interrupt, and call the - * appropriate callback function. All callbacks are registered by the user - * level application. - * - * <b>Virtual Memory</b> - * - * All virtual to physical memory mappings must occur prior to accessing the - * driver API. - * - * For DMA transactions, user buffers supplied to the driver must be in terms - * of their physical address. - * - * <b>DMA</b> - * - * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames. - * These BDs are typically chained together into a list the hardware follows - * when transferring data in and out of the packet buffers. Each BD describes - * a memory region containing either a full or partial Ethernet packet. - * - * Interrupt coalescing is not suppoted from this built-in DMA engine. - * - * This API requires the user to understand how the DMA operates. The - * following paragraphs provide some explanation, but the user is encouraged - * to read documentation in xemacps_bdring.h as well as study example code - * that accompanies this driver. - * - * The API is designed to get BDs to and from the DMA engine in the most - * efficient means possible. The first step is to establish a memory region - * to contain all BDs for a specific channel. This is done with - * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will - * follow as BDs are processed. The ring will consist of a user defined number - * of BDs which will all be partially initialized. For example on the transmit - * channel, the driver will initialize all BDs' so that they are configured - * for transmit. The more fields that can be permanently setup at - * initialization, then the fewer accesses will be needed to each BD while - * the DMA engine is in operation resulting in better throughput and CPU - * utilization. The best case initialization would require the user to set - * only a frame buffer address and length prior to submitting the BD to the - * engine. - * - * BDs move through the engine with the help of functions - * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(), - * and XEmacPs_BdRingFree(). - * All these functions handle BDs that are in place. That is, there are no - * copies of BDs kept anywhere and any BD the user interacts with is an actual - * BD from the same ring hardware accesses. - * - * BDs in the ring go through a series of states as follows: - * 1. Idle. The driver controls BDs in this state. - * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to - * reserve BD(s). Once allocated, the user may setup the BD(s) with - * frame buffer address, length, and other attributes. The user controls - * BDs in this state. - * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs - * in this state are either waiting to be processed by hardware, are in - * process, or have been processed. The DMA engine controls BDs in this - * state. - * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the - * user. Once retrieved, the user can examine each BD for the outcome of - * the DMA transfer. The user controls BDs in this state. After examining - * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back - * into state 1. - * - * Each of the four BD accessor functions operate on a set of BDs. A set is - * defined as a segment of the BD ring consisting of one or more BDs. The user - * views the set as a pointer to the first BD along with the number of BDs for - * that set. The set can be navigated by using macros XEmacPs_BdNext(). The - * user must exercise extreme caution when changing BDs in a set as there is - * nothing to prevent doing a mBdNext past the end of the set and modifying a - * BD out of bounds. - * - * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as - * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in - * tandem. The same BD set retrieved with BdRingAlloc should be the same one - * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and - * BdRIngFree. - * - * <b>Alignment & Data Cache Restrictions</b> - * - * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte - * aligned. Please reference xemacps_bd.h for cache related macros. - * - * DMA Tx: - * - * - If frame buffers exist in cached memory, then they must be flushed - * prior to committing them to hardware. - * - * DMA Rx: - * - * - If frame buffers exist in cached memory, then the cache must be - * invalidated for the memory region containing the frame prior to data - * access - * - * Both cache invalidate/flush are taken care of in driver code. - * - * <b>Buffer Copying</b> - * - * The driver is designed for a zero-copy buffer scheme. That is, the driver - * will not copy buffers. This avoids potential throughput bottlenecks within - * the driver. If byte copying is required, then the transfer will take longer - * to complete. - * - * <b>Checksum Offloading</b> - * - * The Embedded Processor Block Ethernet can be configured to perform IP, TCP - * and UDP checksum offloading in both receive and transmit directions. - * - * IP packets contain a 16-bit checksum field, which is the 16-bit 1s - * complement of the 1s complement sum of all 16-bit words in the header. - * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit - * 1s complement of the 1s complement sum of all 16-bit words in the header, - * the data and a conceptual pseudo header. - * - * To calculate these checksums in software requires each byte of the packet - * to be read. For TCP and UDP this can use a large amount of processing power. - * Offloading the checksum calculation to hardware can result in significant - * performance improvements. - * - * The transmit checksum offload is only available to use DMA in packet buffer - * mode. This is because the complete frame to be transmitted must be read - * into the packet buffer memory before the checksum can be calculated and - * written to the header at the beginning of the frame. - * - * For IP, TCP or UDP receive checksum offload to be useful, the operating - * system containing the protocol stack must be aware that this offload is - * available so that it can make use of the fact that the hardware has verified - * the checksum. - * - * When receive checksum offloading is enabled in the hardware, the IP header - * checksum is checked, where the packet meets the following criteria: - * - * 1. If present, the VLAN header must be four octets long and the CFI bit - * must not be set. - * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP - * encoding. - * 3. IP v4 packet. - * 4. IP header is of a valid length. - * 5. Good IP header checksum. - * 6. No IP fragmentation. - * 7. TCP or UDP packet. - * - * When an IP, TCP or UDP frame is received, the receive buffer descriptor - * gives an indication if the hardware was able to verify the checksums. - * There is also an indication if the frame had SNAP encapsulation. These - * indication bits will replace the type ID match indication bits when the - * receive checksum offload is enabled. - * - * If any of the checksums are verified incorrect by the hardware, the packet - * is discarded and the appropriate statistics counter incremented. - * - * <b>PHY Interfaces</b> - * - * RGMII 1.3 is the only interface supported. - * - * <b>Asserts</b> - * - * Asserts are used within all Xilinx drivers to enforce constraints on - * parameters. Asserts can be turned off on a system-wide basis by defining, - * at compile time, the NDEBUG identifier. By default, asserts are turned on - * and it is recommended that users leave asserts on during development. For - * deployment use -DNDEBUG compiler switch to remove assert code. - * - * @note - * - * Xilinx drivers are typically composed of two parts, one is the driver - * and the other is the adapter. The driver is independent of OS and processor - * and is intended to be highly portable. The adapter is OS-specific and - * facilitates communication between the driver and an OS. - * This driver is intended to be RTOS and processor independent. Any needs for - * dynamic memory management, threads or thread mutual exclusion, or cache - * control must be satisfied bythe layer above this driver. - * - * <pre> - * MODIFICATION HISTORY: - * - * Ver Who Date Changes - * ----- ---- -------- ------------------------------------------------------- - * 1.00a wsy 01/10/10 First release - * 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx in file - * xemacps_bdring.c is modified. Earlier it was checking for - * "BdLimit"(passed argument) number of BDs for finding out - * which BDs are successfully processed. Now one more check - * is added. It looks for BDs till the current BD pointer - * reaches HwTail. By doing this processing time is saved. - * 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file - * xemacps_bdring.c is modified. Now start of packet is - * searched for returning the number of BDs processed. - * 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH - * registers. Added a new API to set the bust length. - * Added some new hash-defines. - * 1.03a asa 01/23/12 Fix for CR #692702 which updates error handling for - * Rx errors. Under heavy Rx traffic, there will be a large - * number of errors related to receive buffer not available. - * Because of a HW bug (SI #692601), under such heavy errors, - * the Rx data path can become unresponsive. To reduce the - * probabilities for hitting this HW bug, the SW writes to - * bit 18 to flush a packet from Rx DPRAM immediately. The - * changes for it are done in the function - * XEmacPs_IntrHandler. - * 1.05a asa 09/23/13 Cache operations on BDs are not required and hence - * removed. It is expected that all BDs are allocated in - * from uncached area. - * </pre> - * - ****************************************************************************/ - -#ifndef XEMACPS_H /* prevent circular inclusions */ -#define XEMACPS_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files ********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xstatus.h" -#include "xemacps_hw.h" -#include "xemacps_bd.h" -#include "xemacps_bdring.h" - -/************************** Constant Definitions ****************************/ - -/* - * Device information - */ -#define XEMACPS_DEVICE_NAME "xemacps" -#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC" - - -/** @name Configuration options - * - * Device configuration options. See the XEmacPs_SetOptions(), - * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to - * use options. - * - * The default state of the options are noted and are what the device and - * driver will be set to after calling XEmacPs_Reset() or - * XEmacPs_Initialize(). - * - * @{ - */ - -#define XEMACPS_PROMISC_OPTION 0x00000001 -/**< Accept all incoming packets. - * This option defaults to disabled (cleared) */ - -#define XEMACPS_FRAME1536_OPTION 0x00000002 -/**< Frame larger than 1516 support for Tx & Rx. - * This option defaults to disabled (cleared) */ - -#define XEMACPS_VLAN_OPTION 0x00000004 -/**< VLAN Rx & Tx frame support. - * This option defaults to disabled (cleared) */ - -#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010 -/**< Enable recognition of flow control frames on Rx - * This option defaults to enabled (set) */ - -#define XEMACPS_FCS_STRIP_OPTION 0x00000020 -/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not - * stripped. - * This option defaults to enabled (set) */ - -#define XEMACPS_FCS_INSERT_OPTION 0x00000040 -/**< Generate FCS field and add PAD automatically for outgoing frames. - * This option defaults to disabled (cleared) */ - -#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080 -/**< Enable Length/Type error checking for incoming frames. When this option is - * set, the MAC will filter frames that have a mismatched type/length field - * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these - * types of frames are encountered. When this option is cleared, the MAC will - * allow these types of frames to be received. - * - * This option defaults to disabled (cleared) */ - -#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100 -/**< Enable the transmitter. - * This option defaults to enabled (set) */ - -#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200 -/**< Enable the receiver - * This option defaults to enabled (set) */ - -#define XEMACPS_BROADCAST_OPTION 0x00000400 -/**< Allow reception of the broadcast address - * This option defaults to enabled (set) */ - -#define XEMACPS_MULTICAST_OPTION 0x00000800 -/**< Allows reception of multicast addresses programmed into hash - * This option defaults to disabled (clear) */ - -#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000 -/**< Enable the RX checksum offload - * This option defaults to enabled (set) */ - -#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000 -/**< Enable the TX checksum offload - * This option defaults to enabled (set) */ - - -#define XEMACPS_DEFAULT_OPTIONS \ - (XEMACPS_FLOW_CONTROL_OPTION | \ - XEMACPS_FCS_INSERT_OPTION | \ - XEMACPS_FCS_STRIP_OPTION | \ - XEMACPS_BROADCAST_OPTION | \ - XEMACPS_LENTYPE_ERR_OPTION | \ - XEMACPS_TRANSMITTER_ENABLE_OPTION | \ - XEMACPS_RECEIVER_ENABLE_OPTION | \ - XEMACPS_RX_CHKSUM_ENABLE_OPTION | \ - XEMACPS_TX_CHKSUM_ENABLE_OPTION) - -/**< Default options set when device is initialized or reset */ -/*@}*/ - -/** @name Callback identifiers - * - * These constants are used as parameters to XEmacPs_SetHandler() - * @{ - */ -#define XEMACPS_HANDLER_DMASEND 1 -#define XEMACPS_HANDLER_DMARECV 2 -#define XEMACPS_HANDLER_ERROR 3 -/*@}*/ - -/* Constants to determine the configuration of the hardware device. They are - * used to allow the driver to verify it can operate with the hardware. - */ -#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */ - -/* The next few constants help upper layers determine the size of memory - * pools used for Ethernet buffers and descriptor lists. - */ -#define XEMACPS_MAC_ADDR_SIZE 6 /* size of Ethernet header */ - -#define XEMACPS_MTU 1500 /* max MTU size of Ethernet frame */ -#define XEMACPS_HDR_SIZE 14 /* size of Ethernet header */ -#define XEMACPS_HDR_VLAN_SIZE 18 /* size of Ethernet header with VLAN */ -#define XEMACPS_TRL_SIZE 4 /* size of Ethernet trailer (FCS) */ -#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \ - XEMACPS_TRL_SIZE) -#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \ - XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE) - -/* DMACR Bust length hash defines */ - -#define XEMACPS_SINGLE_BURST 1 -#define XEMACPS_4BYTE_BURST 4 -#define XEMACPS_8BYTE_BURST 8 -#define XEMACPS_16BYTE_BURST 16 - - -/**************************** Type Definitions ******************************/ -/** @name Typedefs for callback functions - * - * These callbacks are invoked in interrupt context. - * @{ - */ -/** - * Callback invoked when frame(s) have been sent or received in interrupt - * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler(). - * - * @param CallBackRef is user data assigned when the callback was set. - * - * @note - * See xemacps_hw.h for bitmasks definitions and the device hardware spec for - * further information on their meaning. - * - */ -typedef void (*XEmacPs_Handler) (void *CallBackRef); - -/** - * Callback when an asynchronous error occurs. To set this callback, invoke - * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType - * paramter. - * - * @param CallBackRef is user data assigned when the callback was set. - * @param Direction defines either receive or transmit error(s) has occurred. - * @param ErrorWord definition varies with Direction - * - */ -typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction, - u32 ErrorWord); - -/*@}*/ - -/** - * This typedef contains configuration information for a device. - */ -typedef struct { - u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddress;/**< Physical base address of IPIF registers */ -} XEmacPs_Config; - - -/** - * The XEmacPs driver instance data. The user is required to allocate a - * structure of this type for every XEmacPs device in the system. A pointer - * to a structure of this type is then passed to the driver API functions. - */ -typedef struct XEmacPs { - XEmacPs_Config Config; /* Hardware configuration */ - u32 IsStarted; /* Device is currently started */ - u32 IsReady; /* Device is initialized and ready */ - u32 Options; /* Current options word */ - - XEmacPs_BdRing TxBdRing; /* Transmit BD ring */ - XEmacPs_BdRing RxBdRing; /* Receive BD ring */ - - XEmacPs_Handler SendHandler; - XEmacPs_Handler RecvHandler; - void *SendRef; - void *RecvRef; - - XEmacPs_ErrHandler ErrorHandler; - void *ErrorRef; - -} XEmacPs; - - -/***************** Macros (Inline Functions) Definitions ********************/ - -/****************************************************************************/ -/** -* Retrieve the Tx ring object. This object can be used in the various Ring -* API functions. -* -* @param InstancePtr is the DMA channel to operate on. -* -* @return TxBdRing attribute -* -* @note -* C-style signature: -* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr) -* -*****************************************************************************/ -#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing) - -/****************************************************************************/ -/** -* Retrieve the Rx ring object. This object can be used in the various Ring -* API functions. -* -* @param InstancePtr is the DMA channel to operate on. -* -* @return RxBdRing attribute -* -* @note -* C-style signature: -* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr) -* -*****************************************************************************/ -#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing) - -/****************************************************************************/ -/** -* -* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for -* each bit set to 1 in <i>Mask</i>, will be enabled. -* -* @param InstancePtr is a pointer to the instance to be worked on. -* @param Mask contains a bit mask of interrupts to enable. The mask can -* be formed using a set of bitwise or'd values. -* -* @note -* The state of the transmitter and receiver are not modified by this function. -* C-style signature -* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask) -* -*****************************************************************************/ -#define XEmacPs_IntEnable(InstancePtr, Mask) \ - XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ - XEMACPS_IER_OFFSET, \ - (Mask & XEMACPS_IXR_ALL_MASK)); - -/****************************************************************************/ -/** -* -* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for -* each bit set to 1 in <i>Mask</i>, will be enabled. -* -* @param InstancePtr is a pointer to the instance to be worked on. -* @param Mask contains a bit mask of interrupts to disable. The mask can -* be formed using a set of bitwise or'd values. -* -* @note -* The state of the transmitter and receiver are not modified by this function. -* C-style signature -* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask) -* -*****************************************************************************/ -#define XEmacPs_IntDisable(InstancePtr, Mask) \ - XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ - XEMACPS_IDR_OFFSET, \ - (Mask & XEMACPS_IXR_ALL_MASK)); - -/****************************************************************************/ -/** -* -* This macro triggers trasmit circuit to send data currently in TX buffer(s). -* -* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. -* -* @return -* -* @note -* -* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr) -* -*****************************************************************************/ -#define XEmacPs_Transmit(InstancePtr) \ - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, \ - XEMACPS_NWCTRL_OFFSET, \ - (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, \ - XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK)) - -/****************************************************************************/ -/** -* -* This macro determines if the device is configured with checksum offloading -* on the receive channel -* -* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. -* -* @return -* -* Boolean TRUE if the device is configured with checksum offloading, or -* FALSE otherwise. -* -* @note -* -* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr) -* -*****************************************************************************/ -#define XEmacPs_IsRxCsum(InstancePtr) \ - ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ - XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) \ - ? TRUE : FALSE) - -/****************************************************************************/ -/** -* -* This macro determines if the device is configured with checksum offloading -* on the transmit channel -* -* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. -* -* @return -* -* Boolean TRUE if the device is configured with checksum offloading, or -* FALSE otherwise. -* -* @note -* -* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr) -* -*****************************************************************************/ -#define XEmacPs_IsTxCsum(InstancePtr) \ - ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ - XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) \ - ? TRUE : FALSE) - -/************************** Function Prototypes *****************************/ - -/* - * Initialization functions in xemacps.c - */ -int XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr, - u32 EffectiveAddress); -void XEmacPs_Start(XEmacPs *InstancePtr); -void XEmacPs_Stop(XEmacPs *InstancePtr); -void XEmacPs_Reset(XEmacPs *InstancePtr); - -/* - * Lookup configuration in xemacps_sinit.c - */ -XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId); - -/* - * Interrupt-related functions in xemacps_intr.c - * DMA only and FIFO is not supported. This DMA does not support coalescing. - */ -int XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType, - void *FuncPtr, void *CallBackRef); -void XEmacPs_IntrHandler(void *InstancePtr); - -/* - * MAC configuration/control functions in XEmacPs_control.c - */ -int XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options); -int XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options); -u32 XEmacPs_GetOptions(XEmacPs *InstancePtr); - -int XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index); -void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index); - -int XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr); -void XEmacPs_ClearHash(XEmacPs *InstancePtr); -void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr); - -void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, - XEmacPs_MdcDiv Divisor); -void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed); -u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr); -int XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress, - u32 RegisterNum, u16 *PhyDataPtr); -int XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress, - u32 RegisterNum, u16 PhyData); -int XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index); - -int XEmacPs_SendPausePacket(XEmacPs *InstancePtr); -void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, int BLength); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xemacps_bd.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xemacps_bd.h deleted file mode 100644 index 8bf33cfa5bb5b6f92bb43049d869e68708aabd12..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xemacps_bd.h +++ /dev/null @@ -1,737 +0,0 @@ -/* $Id: xemacps_bd.h,v 1.1.2.1 2011/01/20 03:39:02 sadanan Exp $ */ -/****************************************************************************** -* -* (c) Copyright 2010 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** - * - * @file xemacps_bd.h - * - * This header provides operations to manage buffer descriptors in support - * of scatter-gather DMA. - * - * The API exported by this header defines abstracted macros that allow the - * user to read/write specific BD fields. - * - * <b>Buffer Descriptors</b> - * - * A buffer descriptor (BD) defines a DMA transaction. The macros defined by - * this header file allow access to most fields within a BD to tailor a DMA - * transaction according to user and hardware requirements. See the hardware - * IP DMA spec for more information on BD fields and how they affect transfers. - * - * The XEmacPs_Bd structure defines a BD. The organization of this structure - * is driven mainly by the hardware for use in scatter-gather DMA transfers. - * - * <b>Performance</b> - * - * Limiting I/O to BDs can improve overall performance of the DMA channel. - * - * <pre> - * MODIFICATION HISTORY: - * - * Ver Who Date Changes - * ----- ---- -------- ------------------------------------------------------- - * 1.00a wsy 01/10/10 First release - * </pre> - * - * *************************************************************************** - */ - -#ifndef XEMACPS_BD_H /* prevent circular inclusions */ -#define XEMACPS_BD_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include <string.h> -#include "xil_types.h" -#include "xil_assert.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/* Minimum BD alignment */ -#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4 - -/** - * The XEmacPs_Bd is the type for buffer descriptors (BDs). - */ -#define XEMACPS_BD_NUM_WORDS 2 -typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS]; - - -/***************** Macros (Inline Functions) Definitions *********************/ - -/*****************************************************************************/ -/** - * Zero out BD fields - * - * @param BdPtr is the BD pointer to operate on - * - * @return Nothing - * - * @note - * C-style signature: - * void XEmacPs_BdClear(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdClear(BdPtr) \ - memset((BdPtr), 0, sizeof(XEmacPs_Bd)) - -/****************************************************************************/ -/** -* -* Read the given Buffer Descriptor word. -* -* @param BaseAddress is the base address of the BD to read -* @param Offset is the word offset to be read -* -* @return The 32-bit value of the field -* -* @note -* C-style signature: -* u32 XEmacPs_BdRead(u32 BaseAddress, u32 Offset) -* -*****************************************************************************/ -#define XEmacPs_BdRead(BaseAddress, Offset) \ - (*(u32*)((u32)(BaseAddress) + (u32)(Offset))) - -/****************************************************************************/ -/** -* -* Write the given Buffer Descriptor word. -* -* @param BaseAddress is the base address of the BD to write -* @param Offset is the word offset to be written -* @param Data is the 32-bit value to write to the field -* -* @return None. -* -* @note -* C-style signature: -* void XEmacPs_BdWrite(u32 BaseAddress, u32 Offset, u32 Data) -* -*****************************************************************************/ -#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \ - (*(u32*)((u32)(BaseAddress) + (u32)(Offset)) = (Data)) - -/*****************************************************************************/ -/** - * Set the BD's Address field (word 0). - * - * @param BdPtr is the BD pointer to operate on - * @param Addr is the value to write to BD's status field. - * - * @note : - * - * C-style signature: - * void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, u32 Addr) - * - *****************************************************************************/ -#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \ - (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))) - - -/*****************************************************************************/ -/** - * Set the BD's Address field (word 0). - * - * @param BdPtr is the BD pointer to operate on - * @param Addr is the value to write to BD's status field. - * - * @note : Due to some bits are mixed within recevie BD's address field, - * read-modify-write is performed. - * - * C-style signature: - * void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, u32 Addr) - * - *****************************************************************************/ -#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \ - XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ - ~XEMACPS_RXBUF_ADD_MASK) | (u32)(Addr))) - - -/*****************************************************************************/ -/** - * Set the BD's Status field (word 1). - * - * @param BdPtr is the BD pointer to operate on - * @param Data is the value to write to BD's status field. - * - * @note - * C-style signature: - * void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, u32 Data) - * - *****************************************************************************/ -#define XEmacPs_BdSetStatus(BdPtr, Data) \ - XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ - XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | Data) - - -/*****************************************************************************/ -/** - * Retrieve the BD's Packet DMA transfer status word (word 1). - * - * @param BdPtr is the BD pointer to operate on - * - * @return Status word - * - * @note - * C-style signature: - * u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr) - * - * Due to the BD bit layout differences in transmit and receive. User's - * caution is required. - *****************************************************************************/ -#define XEmacPs_BdGetStatus(BdPtr) \ - XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) - - -/*****************************************************************************/ -/** - * Get the address (bits 0..31) of the BD's buffer address (word 0) - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdGetBufAddr(BdPtr) \ - (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET)) - - -/*****************************************************************************/ -/** - * Set transfer length in bytes for the given BD. The length must be set each - * time a BD is submitted to hardware. - * - * @param BdPtr is the BD pointer to operate on - * @param LenBytes is the number of bytes to transfer. - * - * @note - * C-style signature: - * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes) - * - *****************************************************************************/ -#define XEmacPs_BdSetLength(BdPtr, LenBytes) \ - XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes))) - - -/*****************************************************************************/ -/** - * Retrieve the BD length field. - * - * For Tx channels, the returned value is the same as that written with - * XEmacPs_BdSetLength(). - * - * For Rx channels, the returned value is the size of the received packet. - * - * @param BdPtr is the BD pointer to operate on - * - * @return Length field processed by hardware or set by - * XEmacPs_BdSetLength(). - * - * @note - * C-style signature: - * u32 XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr) - * XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK. - * - *****************************************************************************/ -#define XEmacPs_BdGetLength(BdPtr) \ - (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_RXBUF_LEN_MASK) - - -/*****************************************************************************/ -/** - * Test whether the given BD has been marked as the last BD of a packet. - * - * @param BdPtr is the BD pointer to operate on - * - * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise - * - * @note - * C-style signature: - * u32 XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsLast(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_RXBUF_EOF_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * Tell the DMA engine that the given transmit BD marks the end of the current - * packet to be processed. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdSetLast(BdPtr) \ - (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ - XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ - XEMACPS_TXBUF_LAST_MASK)) - - -/*****************************************************************************/ -/** - * Tell the DMA engine that the current packet does not end with the given - * BD. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdClearLast(BdPtr) \ - (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ - XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - ~XEMACPS_TXBUF_LAST_MASK)) - - -/*****************************************************************************/ -/** - * Set this bit to mark the last descriptor in the receive buffer descriptor - * list. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdSetRxWrap(BdPtr) \ - (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ - XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \ - XEMACPS_RXBUF_WRAP_MASK)) - - -/*****************************************************************************/ -/** - * Determine the wrap bit of the receive BD which indicates end of the - * BD list. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsRxWrap(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ - XEMACPS_RXBUF_WRAP_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * Sets this bit to mark the last descriptor in the transmit buffer - * descriptor list. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdSetTxWrap(BdPtr) \ - (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ - XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ - XEMACPS_TXBUF_WRAP_MASK)) - - -/*****************************************************************************/ -/** - * Determine the wrap bit of the transmit BD which indicates end of the - * BD list. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsTxWrap(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_TXBUF_WRAP_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/* - * Must clear this bit to enable the MAC to write data to the receive - * buffer. Hardware sets this bit once it has successfully written a frame to - * memory. Once set, software has to clear the bit before the buffer can be - * used again. This macro clear the new bit of the receive BD. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdClearRxNew(BdPtr) \ - (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ - XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ - ~XEMACPS_RXBUF_NEW_MASK)) - - -/*****************************************************************************/ -/** - * Determine the new bit of the receive BD. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsRxNew(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ - XEMACPS_RXBUF_NEW_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * Software sets this bit to disable the buffer to be read by the hardware. - * Hardware sets this bit for the first buffer of a frame once it has been - * successfully transmitted. This macro sets this bit of transmit BD to avoid - * confusion. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdSetTxUsed(BdPtr) \ - (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ - XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ - XEMACPS_TXBUF_USED_MASK)) - - -/*****************************************************************************/ -/** - * Software clears this bit to enable the buffer to be read by the hardware. - * Hardware sets this bit for the first buffer of a frame once it has been - * successfully transmitted. This macro clears this bit of transmit BD. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdClearTxUsed(BdPtr) \ - (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ - XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - ~XEMACPS_TXBUF_USED_MASK)) - - -/*****************************************************************************/ -/** - * Determine the used bit of the transmit BD. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsTxUsed(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_TXBUF_USED_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * Determine if a frame fails to be transmitted due to too many retries. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsTxRetry(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_TXBUF_RETRY_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * Determine if a frame fails to be transmitted due to data can not be - * feteched in time or buffers are exhausted. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsTxUrun(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_TXBUF_URUN_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * Determine if a frame fails to be transmitted due to buffer is exhausted - * mid-frame. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsTxExh(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_TXBUF_EXH_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * Sets this bit, no CRC will be appended to the current frame. This control - * bit must be set for the first buffer in a frame and will be ignored for - * the subsequent buffers of a frame. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * This bit must be clear when using the transmit checksum generation offload, - * otherwise checksum generation and substitution will not occur. - * - * C-style signature: - * u32 XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdSetTxNoCRC(BdPtr) \ - (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ - XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ - XEMACPS_TXBUF_NOCRC_MASK)) - - -/*****************************************************************************/ -/** - * Clear this bit, CRC will be appended to the current frame. This control - * bit must be set for the first buffer in a frame and will be ignored for - * the subsequent buffers of a frame. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * This bit must be clear when using the transmit checksum generation offload, - * otherwise checksum generation and substitution will not occur. - * - * C-style signature: - * u32 XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdClearTxNoCRC(BdPtr) \ - (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ - XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - ~XEMACPS_TXBUF_NOCRC_MASK)) - - -/*****************************************************************************/ -/** - * Determine the broadcast bit of the receive BD. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsRxBcast(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_RXBUF_BCAST_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * Determine the multicast hash bit of the receive BD. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsRxMultiHash(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_RXBUF_MULTIHASH_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * Determine the unicast hash bit of the receive BD. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsRxUniHash(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_RXBUF_UNIHASH_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * Determine if the received frame is a VLAN Tagged frame. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsRxVlan(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_RXBUF_VLAN_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * Determine if the received frame has Type ID of 8100h and null VLAN - * identifier(Priority tag). - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsRxPri(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_RXBUF_PRI_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * Determine if the received frame's Concatenation Format Indicator (CFI) of - * the frames VLANTCI field was set. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsRxCFI(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_RXBUF_CFI_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * Determine the End Of Frame (EOF) bit of the receive BD. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsRxEOF(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_RXBUF_EOF_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * Determine the Start Of Frame (SOF) bit of the receive BD. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsRxSOF(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_RXBUF_SOF_MASK) ? TRUE : FALSE) - - -/************************** Function Prototypes ******************************/ - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xemacps_bdring.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xemacps_bdring.h deleted file mode 100644 index 9c50d618e26160a92cffbc04f3f3a6d06da318db..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xemacps_bdring.h +++ /dev/null @@ -1,242 +0,0 @@ -/* $Id: xemacps_bdring.h,v 1.1.2.1 2011/01/20 03:39:02 sadanan Exp $ */ -/****************************************************************************** -* -* (c) Copyright 2010 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xemacps_bdring.h -* -* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs -* DMA functionalities. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.00a wsy 01/10/10 First release -* </pre> -* -******************************************************************************/ - -#ifndef XEMACPS_BDRING_H /* prevent curcular inclusions */ -#define XEMACPS_BDRING_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - - -/**************************** Type Definitions *******************************/ - -/** This is an internal structure used to maintain the DMA list */ -typedef struct { - u32 PhysBaseAddr;/**< Physical address of 1st BD in list */ - u32 BaseBdAddr; /**< Virtual address of 1st BD in list */ - u32 HighBdAddr; /**< Virtual address of last BD in the list */ - u32 Length; /**< Total size of ring in bytes */ - u32 RunState; /**< Flag to indicate DMA is started */ - u32 Separation; /**< Number of bytes between the starting address - of adjacent BDs */ - XEmacPs_Bd *FreeHead; - /**< First BD in the free group */ - XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */ - XEmacPs_Bd *HwHead; /**< First BD in the work group */ - XEmacPs_Bd *HwTail; /**< Last BD in the work group */ - XEmacPs_Bd *PostHead; - /**< First BD in the post-work group */ - XEmacPs_Bd *BdaRestart; - /**< BDA to load when channel is started */ - unsigned HwCnt; /**< Number of BDs in work group */ - unsigned PreCnt; /**< Number of BDs in pre-work group */ - unsigned FreeCnt; /**< Number of allocatable BDs in the free group */ - unsigned PostCnt; /**< Number of BDs in post-work group */ - unsigned AllCnt; /**< Total Number of BDs for channel */ -} XEmacPs_BdRing; - - -/***************** Macros (Inline Functions) Definitions *********************/ - -/*****************************************************************************/ -/** -* Use this macro at initialization time to determine how many BDs will fit -* in a BD list within the given memory constraints. -* -* The results of this macro can be provided to XEmacPs_BdRingCreate(). -* -* @param Alignment specifies what byte alignment the BDs must fall on and -* must be a power of 2 to get an accurate calculation (32, 64, 128,...) -* @param Bytes is the number of bytes to be used to store BDs. -* -* @return Number of BDs that can fit in the given memory area -* -* @note -* C-style signature: -* u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes) -* -******************************************************************************/ -#define XEmacPs_BdRingCntCalc(Alignment, Bytes) \ - (u32)((Bytes) / ((sizeof(XEmacPs_Bd) + ((Alignment)-1)) & \ - ~((Alignment)-1))) - -/*****************************************************************************/ -/** -* Use this macro at initialization time to determine how many bytes of memory -* is required to contain a given number of BDs at a given alignment. -* -* @param Alignment specifies what byte alignment the BDs must fall on. This -* parameter must be a power of 2 to get an accurate calculation (32, 64, -* 128,...) -* @param NumBd is the number of BDs to calculate memory size requirements for -* -* @return The number of bytes of memory required to create a BD list with the -* given memory constraints. -* -* @note -* C-style signature: -* u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd) -* -******************************************************************************/ -#define XEmacPs_BdRingMemCalc(Alignment, NumBd) \ - (u32)((sizeof(XEmacPs_Bd) + ((Alignment)-1)) & \ - ~((Alignment)-1)) * (NumBd) - -/****************************************************************************/ -/** -* Return the total number of BDs allocated by this channel with -* XEmacPs_BdRingCreate(). -* -* @param RingPtr is the DMA channel to operate on. -* -* @return The total number of BDs allocated for this channel. -* -* @note -* C-style signature: -* u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr) -* -*****************************************************************************/ -#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt) - -/****************************************************************************/ -/** -* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre- -* processing. -* -* @param RingPtr is the DMA channel to operate on. -* -* @return The number of BDs currently allocatable. -* -* @note -* C-style signature: -* u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr) -* -*****************************************************************************/ -#define XEmacPs_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt) - -/****************************************************************************/ -/** -* Return the next BD from BdPtr in a list. -* -* @param RingPtr is the DMA channel to operate on. -* @param BdPtr is the BD to operate on. -* -* @return The next BD in the list relative to the BdPtr parameter. -* -* @note -* C-style signature: -* XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr, -* XEmacPs_Bd *BdPtr) -* -*****************************************************************************/ -#define XEmacPs_BdRingNext(RingPtr, BdPtr) \ - (((u32)(BdPtr) >= (RingPtr)->HighBdAddr) ? \ - (XEmacPs_Bd*)(RingPtr)->BaseBdAddr : \ - (XEmacPs_Bd*)((u32)(BdPtr) + (RingPtr)->Separation)) - -/****************************************************************************/ -/** -* Return the previous BD from BdPtr in the list. -* -* @param RingPtr is the DMA channel to operate on. -* @param BdPtr is the BD to operate on -* -* @return The previous BD in the list relative to the BdPtr parameter. -* -* @note -* C-style signature: -* XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr, -* XEmacPs_Bd *BdPtr) -* -*****************************************************************************/ -#define XEmacPs_BdRingPrev(RingPtr, BdPtr) \ - (((u32)(BdPtr) <= (RingPtr)->BaseBdAddr) ? \ - (XEmacPs_Bd*)(RingPtr)->HighBdAddr : \ - (XEmacPs_Bd*)((u32)(BdPtr) - (RingPtr)->Separation)) - -/************************** Function Prototypes ******************************/ - -/* - * Scatter gather DMA related functions in xemacps_bdring.c - */ -int XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, u32 PhysAddr, - u32 VirtAddr, u32 Alignment, unsigned BdCount); -int XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr, - u8 Direction); -int XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, unsigned NumBd, - XEmacPs_Bd ** BdSetPtr); -int XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, unsigned NumBd, - XEmacPs_Bd * BdSetPtr); -int XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, unsigned NumBd, - XEmacPs_Bd * BdSetPtr); -int XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, unsigned NumBd, - XEmacPs_Bd * BdSetPtr); -unsigned XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, unsigned BdLimit, - XEmacPs_Bd ** BdSetPtr); -unsigned XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, unsigned BdLimit, - XEmacPs_Bd ** BdSetPtr); -int XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction); - -#ifdef __cplusplus -} -#endif - - -#endif /* end of protection macros */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xemacps_hw.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xemacps_hw.h deleted file mode 100644 index 4f81fc1a7dcd0a4069bbc25a0aad244c81115b2c..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xemacps_hw.h +++ /dev/null @@ -1,603 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xemacps_hw.h -* -* This header file contains identifiers and low-level driver functions (or -* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device. -* High-level driver functions are defined in xemacps.h. -* -* @note -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.00a wsy 01/10/10 First release. -* 1.02a asa 11/05/12 Added hash defines for DMACR burst length configuration. -* 1.05a kpc 28/06/13 Added XEmacPs_ResetHw function prototype -* </pre> -* -******************************************************************************/ - -#ifndef XEMACPS_HW_H /* prevent circular inclusions */ -#define XEMACPS_HW_H /* by using protection macros */ - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xil_io.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/************************** Constant Definitions *****************************/ - -#define XEMACPS_MAX_MAC_ADDR 4 /**< Maxmum number of mac address - supported */ -#define XEMACPS_MAX_TYPE_ID 4 /**< Maxmum number of type id supported */ -#define XEMACPS_BD_ALIGNMENT 4 /**< Minimum buffer descriptor alignment - on the local bus */ -#define XEMACPS_RX_BUF_ALIGNMENT 4 /**< Minimum buffer alignment when using - options that impose alignment - restrictions on the buffer data on - the local bus */ - -/** @name Direction identifiers - * - * These are used by several functions and callbacks that need - * to specify whether an operation specifies a send or receive channel. - * @{ - */ -#define XEMACPS_SEND 1 /**< send direction */ -#define XEMACPS_RECV 2 /**< receive direction */ -/*@}*/ - -/** @name MDC clock division - * currently supporting 8, 16, 32, 48, 64, 96, 128, 224. - * @{ - */ -typedef enum { MDC_DIV_8 = 0, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48, - MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224 -} XEmacPs_MdcDiv; - -/*@}*/ - -#define XEMACPS_RX_BUF_SIZE 1536 /**< Specify the receive buffer size in - bytes, 64, 128, ... 10240 */ -#define XEMACPS_RX_BUF_UNIT 64 /**< Number of receive buffer bytes as a - unit, this is HW setup */ - -#define XEMACPS_MAX_RXBD 128 /**< Size of RX buffer descriptor queues */ -#define XEMACPS_MAX_TXBD 128 /**< Size of TX buffer descriptor queues */ - -#define XEMACPS_MAX_HASH_BITS 64 /**< Maximum value for hash bits. 2**6 */ - -/* Register offset definitions. Unless otherwise noted, register access is - * 32 bit. Names are self explained here. - */ - -#define XEMACPS_NWCTRL_OFFSET 0x00000000 /**< Network Control reg */ -#define XEMACPS_NWCFG_OFFSET 0x00000004 /**< Network Config reg */ -#define XEMACPS_NWSR_OFFSET 0x00000008 /**< Network Status reg */ - -#define XEMACPS_DMACR_OFFSET 0x00000010 /**< DMA Control reg */ -#define XEMACPS_TXSR_OFFSET 0x00000014 /**< TX Status reg */ -#define XEMACPS_RXQBASE_OFFSET 0x00000018 /**< RX Q Base address reg */ -#define XEMACPS_TXQBASE_OFFSET 0x0000001C /**< TX Q Base address reg */ -#define XEMACPS_RXSR_OFFSET 0x00000020 /**< RX Status reg */ - -#define XEMACPS_ISR_OFFSET 0x00000024 /**< Interrupt Status reg */ -#define XEMACPS_IER_OFFSET 0x00000028 /**< Interrupt Enable reg */ -#define XEMACPS_IDR_OFFSET 0x0000002C /**< Interrupt Disable reg */ -#define XEMACPS_IMR_OFFSET 0x00000030 /**< Interrupt Mask reg */ - -#define XEMACPS_PHYMNTNC_OFFSET 0x00000034 /**< Phy Maintaince reg */ -#define XEMACPS_RXPAUSE_OFFSET 0x00000038 /**< RX Pause Time reg */ -#define XEMACPS_TXPAUSE_OFFSET 0x0000003C /**< TX Pause Time reg */ - -#define XEMACPS_HASHL_OFFSET 0x00000080 /**< Hash Low address reg */ -#define XEMACPS_HASHH_OFFSET 0x00000084 /**< Hash High address reg */ - -#define XEMACPS_LADDR1L_OFFSET 0x00000088 /**< Specific1 addr low reg */ -#define XEMACPS_LADDR1H_OFFSET 0x0000008C /**< Specific1 addr high reg */ -#define XEMACPS_LADDR2L_OFFSET 0x00000090 /**< Specific2 addr low reg */ -#define XEMACPS_LADDR2H_OFFSET 0x00000094 /**< Specific2 addr high reg */ -#define XEMACPS_LADDR3L_OFFSET 0x00000098 /**< Specific3 addr low reg */ -#define XEMACPS_LADDR3H_OFFSET 0x0000009C /**< Specific3 addr high reg */ -#define XEMACPS_LADDR4L_OFFSET 0x000000A0 /**< Specific4 addr low reg */ -#define XEMACPS_LADDR4H_OFFSET 0x000000A4 /**< Specific4 addr high reg */ - -#define XEMACPS_MATCH1_OFFSET 0x000000A8 /**< Type ID1 Match reg */ -#define XEMACPS_MATCH2_OFFSET 0x000000AC /**< Type ID2 Match reg */ -#define XEMACPS_MATCH3_OFFSET 0x000000B0 /**< Type ID3 Match reg */ -#define XEMACPS_MATCH4_OFFSET 0x000000B4 /**< Type ID4 Match reg */ - -#define XEMACPS_STRETCH_OFFSET 0x000000BC /**< IPG Stretch reg */ - -#define XEMACPS_OCTTXL_OFFSET 0x00000100 /**< Octects transmitted Low - reg */ -#define XEMACPS_OCTTXH_OFFSET 0x00000104 /**< Octects transmitted High - reg */ - -#define XEMACPS_TXCNT_OFFSET 0x00000108 /**< Error-free Frmaes - transmitted counter */ -#define XEMACPS_TXBCCNT_OFFSET 0x0000010C /**< Error-free Broadcast - Frames counter*/ -#define XEMACPS_TXMCCNT_OFFSET 0x00000110 /**< Error-free Multicast - Frame counter */ -#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114 /**< Pause Frames Transmitted - Counter */ -#define XEMACPS_TX64CNT_OFFSET 0x00000118 /**< Error-free 64 byte Frames - Transmitted counter */ -#define XEMACPS_TX65CNT_OFFSET 0x0000011C /**< Error-free 65-127 byte - Frames Transmitted - counter */ -#define XEMACPS_TX128CNT_OFFSET 0x00000120 /**< Error-free 128-255 byte - Frames Transmitted - counter*/ -#define XEMACPS_TX256CNT_OFFSET 0x00000124 /**< Error-free 256-511 byte - Frames transmitted - counter */ -#define XEMACPS_TX512CNT_OFFSET 0x00000128 /**< Error-free 512-1023 byte - Frames transmitted - counter */ -#define XEMACPS_TX1024CNT_OFFSET 0x0000012C /**< Error-free 1024-1518 byte - Frames transmitted - counter */ -#define XEMACPS_TX1519CNT_OFFSET 0x00000130 /**< Error-free larger than - 1519 byte Frames - transmitted counter */ -#define XEMACPS_TXURUNCNT_OFFSET 0x00000134 /**< TX under run error - counter */ - -#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138 /**< Single Collision Frame - Counter */ -#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013C /**< Multiple Collision Frame - Counter */ -#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140 /**< Excessive Collision Frame - Counter */ -#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144 /**< Late Collision Frame - Counter */ -#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148 /**< Deferred Transmission - Frame Counter */ -#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014C /**< Transmit Carrier Sense - Error Counter */ - -#define XEMACPS_OCTRXL_OFFSET 0x00000150 /**< Octects Received register - Low */ -#define XEMACPS_OCTRXH_OFFSET 0x00000154 /**< Octects Received register - High */ - -#define XEMACPS_RXCNT_OFFSET 0x00000158 /**< Error-free Frames - Received Counter */ -#define XEMACPS_RXBROADCNT_OFFSET 0x0000015C /**< Error-free Broadcast - Frames Received Counter */ -#define XEMACPS_RXMULTICNT_OFFSET 0x00000160 /**< Error-free Multicast - Frames Received Counter */ -#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164 /**< Pause Frames - Received Counter */ -#define XEMACPS_RX64CNT_OFFSET 0x00000168 /**< Error-free 64 byte Frames - Received Counter */ -#define XEMACPS_RX65CNT_OFFSET 0x0000016C /**< Error-free 65-127 byte - Frames Received Counter */ -#define XEMACPS_RX128CNT_OFFSET 0x00000170 /**< Error-free 128-255 byte - Frames Received Counter */ -#define XEMACPS_RX256CNT_OFFSET 0x00000174 /**< Error-free 256-512 byte - Frames Received Counter */ -#define XEMACPS_RX512CNT_OFFSET 0x00000178 /**< Error-free 512-1023 byte - Frames Received Counter */ -#define XEMACPS_RX1024CNT_OFFSET 0x0000017C /**< Error-free 1024-1518 byte - Frames Received Counter */ -#define XEMACPS_RX1519CNT_OFFSET 0x00000180 /**< Error-free 1519-max byte - Frames Received Counter */ -#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184 /**< Undersize Frames Received - Counter */ -#define XEMACPS_RXOVRCNT_OFFSET 0x00000188 /**< Oversize Frames Received - Counter */ -#define XEMACPS_RXJABCNT_OFFSET 0x0000018C /**< Jabbers Received - Counter */ -#define XEMACPS_RXFCSCNT_OFFSET 0x00000190 /**< Frame Check Sequence - Error Counter */ -#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194 /**< Length Field Error - Counter */ -#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198 /**< Symbol Error Counter */ -#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019C /**< Alignment Error Counter */ -#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0 /**< Receive Resource Error - Counter */ -#define XEMACPS_RXORCNT_OFFSET 0x000001A4 /**< Receive Overrun Counter */ -#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8 /**< IP header Checksum Error - Counter */ -#define XEMACPS_RXTCPCCNT_OFFSET 0x000001AC /**< TCP Checksum Error - Counter */ -#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0 /**< UDP Checksum Error - Counter */ -#define XEMACPS_LAST_OFFSET 0x000001B4 /**< Last statistic counter - offset, for clearing */ - -#define XEMACPS_1588_SEC_OFFSET 0x000001D0 /**< 1588 second counter */ -#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4 /**< 1588 nanosecond counter */ -#define XEMACPS_1588_ADJ_OFFSET 0x000001D8 /**< 1588 nanosecond - adjustment counter */ -#define XEMACPS_1588_INC_OFFSET 0x000001DC /**< 1588 nanosecond - increment counter */ -#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0 /**< 1588 PTP transmit second - counter */ -#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4 /**< 1588 PTP transmit - nanosecond counter */ -#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8 /**< 1588 PTP receive second - counter */ -#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001EC /**< 1588 PTP receive - nanosecond counter */ -#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0 /**< 1588 PTP peer transmit - second counter */ -#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4 /**< 1588 PTP peer transmit - nanosecond counter */ -#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8 /**< 1588 PTP peer receive - second counter */ -#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FC /**< 1588 PTP peer receive - nanosecond counter */ - -/* Define some bit positions for registers. */ - -/** @name network control register bit definitions - * @{ - */ -#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000 /**< Flush a packet from - Rx SRAM */ -#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800 /**< Transmit zero quantum - pause frame */ -#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800 /**< Transmit pause frame */ -#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400 /**< Halt transmission - after current frame */ -#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200 /**< Start tx (tx_go) */ - -#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080 /**< Enable writing to - stat counters */ -#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040 /**< Increment statistic - registers */ -#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020 /**< Clear statistic - registers */ -#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010 /**< Enable MDIO port */ -#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008 /**< Enable transmit */ -#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004 /**< Enable receive */ -#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002 /**< local loopback */ -/*@}*/ - -/** @name network configuration register bit definitions - * @{ - */ -#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000 /**< disable rejection of - non-standard preamble */ -#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000 /**< enable transmit IPG */ -#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000 /**< disable rejection of - FCS error */ -#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000 /**< RX half duplex */ -#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000 /**< enable RX checksum - offload */ -#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000 /**< Do not copy pause - Frames to memory */ -#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18 /**< shift bits for MDC */ -#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000 /**< MDC Mask PCLK divisor */ -#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000 /**< Discard FCS from - received frames */ -#define XEMACPS_NWCFG_LENGTHERRDSCRD_MASK 0x00010000 -/**< RX length error discard */ -#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000 /**< RX buffer offset */ -#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000 /**< Enable pause RX */ -#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000 /**< Retry test */ -#define XEMACPS_NWCFG_EXTADDRMATCHEN_MASK 0x00000200 -/**< External address match enable */ -#define XEMACPS_NWCFG_1000_MASK 0x00000400 /**< 1000 Mbps */ -#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100 /**< Enable 1536 byte - frames reception */ -#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080 /**< Receive unicast hash - frames */ -#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040 /**< Receive multicast hash - frames */ -#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020 /**< Do not receive - broadcast frames */ -#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010 /**< Copy all frames */ -#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008 /**< Jumbo frames */ -#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004 /**< Receive only VLAN - frames */ -#define XEMACPS_NWCFG_FDEN_MASK 0x00000002 /**< full duplex */ -#define XEMACPS_NWCFG_100_MASK 0x00000001 /**< 100 Mbps */ -#define XEMACPS_NWCFG_RESET_MASK 0x00080000 /**< reset value */ -/*@}*/ - -/** @name network status register bit definitaions - * @{ - */ -#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004 /**< PHY management idle */ -#define XEMACPS_NWSR_MDIO_MASK 0x00000002 /**< Status of mdio_in */ -/*@}*/ - - -/** @name MAC address register word 1 mask - * @{ - */ -#define XEMACPS_LADDR_MACH_MASK 0x0000FFFF /**< Address bits[47:32] - bit[31:0] are in BOTTOM */ -/*@}*/ - - -/** @name DMA control register bit definitions - * @{ - */ -#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000 /**< Mask bit for RX buffer - size */ -#define XEMACPS_DMACR_RXBUF_SHIFT 16 /**< Shift bit for RX buffer - size */ -#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800 /**< enable/disable TX - checksum offload */ -#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400 /**< TX buffer memory size */ -#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300 /**< RX buffer memory size */ -#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080 /**< endian configuration */ -#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001F /**< buffer burst length */ -#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001 /**< single AHB bursts */ -#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004 /**< 4 bytes AHB bursts */ -#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008 /**< 8 bytes AHB bursts */ -#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010 /**< 16 bytes AHB bursts */ -/*@}*/ - -/** @name transmit status register bit definitions - * @{ - */ -#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100 /**< Transmit hresp not OK */ -#define XEMACPS_TXSR_URUN_MASK 0x00000040 /**< Transmit underrun */ -#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020 /**< Transmit completed OK */ -#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010 /**< Transmit buffs exhausted - mid frame */ -#define XEMACPS_TXSR_TXGO_MASK 0x00000008 /**< Status of go flag */ -#define XEMACPS_TXSR_RXOVR_MASK 0x00000004 /**< Retry limit exceeded */ -#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002 /**< Collision tx frame */ -#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001 /**< TX buffer used bit set */ - -#define XEMACPS_TXSR_ERROR_MASK (XEMACPS_TXSR_HRESPNOK_MASK | \ - XEMACPS_TXSR_URUN_MASK | \ - XEMACPS_TXSR_BUFEXH_MASK | \ - XEMACPS_TXSR_RXOVR_MASK | \ - XEMACPS_TXSR_FRAMERX_MASK | \ - XEMACPS_TXSR_USEDREAD_MASK) -/*@}*/ - -/** - * @name receive status register bit definitions - * @{ - */ -#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008 /**< Receive hresp not OK */ -#define XEMACPS_RXSR_RXOVR_MASK 0x00000004 /**< Receive overrun */ -#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002 /**< Frame received OK */ -#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001 /**< RX buffer used bit set */ - -#define XEMACPS_RXSR_ERROR_MASK (XEMACPS_RXSR_HRESPNOK_MASK | \ - XEMACPS_RXSR_RXOVR_MASK | \ - XEMACPS_RXSR_BUFFNA_MASK) -/*@}*/ - -/** - * @name interrupts bit definitions - * Bits definitions are same in XEMACPS_ISR_OFFSET, - * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET - * @{ - */ -#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000 /**< PTP Psync transmitted */ -#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000 /**< PTP Pdelay_req - transmitted */ -#define XEMACPS_IXR_PTPSTX_MASK 0x00800000 /**< PTP Sync transmitted */ -#define XEMACPS_IXR_PTPDRTX_MASK 0x00400000 /**< PTP Delay_req transmitted - */ -#define XEMACPS_IXR_PTPPSRX_MASK 0x00200000 /**< PTP Psync received */ -#define XEMACPS_IXR_PTPPDRRX_MASK 0x00100000 /**< PTP Pdelay_req received */ -#define XEMACPS_IXR_PTPSRX_MASK 0x00080000 /**< PTP Sync received */ -#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000 /**< PTP Delay_req received */ -#define XEMACPS_IXR_PAUSETX_MASK 0x00004000 /**< Pause frame transmitted */ -#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000 /**< Pause time has reached - zero */ -#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000 /**< Pause frame received */ -#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800 /**< hresp not ok */ -#define XEMACPS_IXR_RXOVR_MASK 0x00000400 /**< Receive overrun occurred */ -#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080 /**< Frame transmitted ok */ -#define XEMACPS_IXR_TXEXH_MASK 0x00000040 /**< Transmit err occurred or - no buffers*/ -#define XEMACPS_IXR_RETRY_MASK 0x00000020 /**< Retry limit exceeded */ -#define XEMACPS_IXR_URUN_MASK 0x00000010 /**< Transmit underrun */ -#define XEMACPS_IXR_TXUSED_MASK 0x00000008 /**< Tx buffer used bit read */ -#define XEMACPS_IXR_RXUSED_MASK 0x00000004 /**< Rx buffer used bit read */ -#define XEMACPS_IXR_FRAMERX_MASK 0x00000002 /**< Frame received ok */ -#define XEMACPS_IXR_MGMNT_MASK 0x00000001 /**< PHY management complete */ -#define XEMACPS_IXR_ALL_MASK 0x00007FFF /**< Everything! */ - -#define XEMACPS_IXR_TX_ERR_MASK (XEMACPS_IXR_TXEXH_MASK | \ - XEMACPS_IXR_RETRY_MASK | \ - XEMACPS_IXR_URUN_MASK | \ - XEMACPS_IXR_TXUSED_MASK) - - -#define XEMACPS_IXR_RX_ERR_MASK (XEMACPS_IXR_HRESPNOK_MASK | \ - XEMACPS_IXR_RXUSED_MASK | \ - XEMACPS_IXR_RXOVR_MASK) - -/*@}*/ - -/** @name PHY Maintenance bit definitions - * @{ - */ -#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000 /**< operation mask bits */ -#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000 /**< read operation */ -#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000 /**< write operation */ -#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000 /**< Address bits */ -#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000 /**< register bits */ -#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFF /**< data bits */ -#define XEMACPS_PHYMNTNC_PHYAD_SHIFT_MASK 23 /**< Shift bits for PHYAD */ -#define XEMACPS_PHYMNTNC_PHREG_SHIFT_MASK 18 /**< Shift bits for PHREG */ -/*@}*/ - -/* Transmit buffer descriptor status words offset - * @{ - */ -#define XEMACPS_BD_ADDR_OFFSET 0x00000000 /**< word 0/addr of BDs */ -#define XEMACPS_BD_STAT_OFFSET 0x00000004 /**< word 1/status of BDs */ -/* - * @} - */ - -/* Transmit buffer descriptor status words bit positions. - * Transmit buffer descriptor consists of two 32-bit registers, - * the first - word0 contains a 32-bit address pointing to the location of - * the transmit data. - * The following register - word1, consists of various information to control - * the XEmacPs transmit process. After transmit, this is updated with status - * information, whether the frame was transmitted OK or why it had failed. - * @{ - */ -#define XEMACPS_TXBUF_USED_MASK 0x80000000 /**< Used bit. */ -#define XEMACPS_TXBUF_WRAP_MASK 0x40000000 /**< Wrap bit, last descriptor */ -#define XEMACPS_TXBUF_RETRY_MASK 0x20000000 /**< Retry limit exceeded */ -#define XEMACPS_TXBUF_URUN_MASK 0x10000000 /**< Transmit underrun occurred */ -#define XEMACPS_TXBUF_EXH_MASK 0x08000000 /**< Buffers exhausted */ -#define XEMACPS_TXBUF_TCP_MASK 0x04000000 /**< Late collision. */ -#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000 /**< No CRC */ -#define XEMACPS_TXBUF_LAST_MASK 0x00008000 /**< Last buffer */ -#define XEMACPS_TXBUF_LEN_MASK 0x00003FFF /**< Mask for length field */ -/* - * @} - */ - -/* Receive buffer descriptor status words bit positions. - * Receive buffer descriptor consists of two 32-bit registers, - * the first - word0 contains a 32-bit word aligned address pointing to the - * address of the buffer. The lower two bits make up the wrap bit indicating - * the last descriptor and the ownership bit to indicate it has been used by - * the XEmacPs. - * The following register - word1, contains status information regarding why - * the frame was received (the filter match condition) as well as other - * useful info. - * @{ - */ -#define XEMACPS_RXBUF_BCAST_MASK 0x80000000 /**< Broadcast frame */ -#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000 /**< Multicast hashed frame */ -#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000 /**< Unicast hashed frame */ -#define XEMACPS_RXBUF_EXH_MASK 0x08000000 /**< buffer exhausted */ -#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000 /**< Specific address - matched */ -#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000 /**< Type ID matched */ -#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000 /**< ID matched mask */ -#define XEMACPS_RXBUF_VLAN_MASK 0x00200000 /**< VLAN tagged */ -#define XEMACPS_RXBUF_PRI_MASK 0x00100000 /**< Priority tagged */ -#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000 /**< Vlan priority */ -#define XEMACPS_RXBUF_CFI_MASK 0x00010000 /**< CFI frame */ -#define XEMACPS_RXBUF_EOF_MASK 0x00008000 /**< End of frame. */ -#define XEMACPS_RXBUF_SOF_MASK 0x00004000 /**< Start of frame. */ -#define XEMACPS_RXBUF_LEN_MASK 0x00003FFF /**< Mask for length field */ - -#define XEMACPS_RXBUF_WRAP_MASK 0x00000002 /**< Wrap bit, last BD */ -#define XEMACPS_RXBUF_NEW_MASK 0x00000001 /**< Used bit.. */ -#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFC /**< Mask for address */ -/* - * @} - */ - -/* - * Define appropriate I/O access method to mempry mapped I/O or other - * intarfce if necessary. - */ - -#define XEmacPs_In32 Xil_In32 -#define XEmacPs_Out32 Xil_Out32 - - -/****************************************************************************/ -/** -* -* Read the given register. -* -* @param BaseAddress is the base address of the device -* @param RegOffset is the register offset to be read -* -* @return The 32-bit value of the register -* -* @note -* C-style signature: -* u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset) -* -*****************************************************************************/ -#define XEmacPs_ReadReg(BaseAddress, RegOffset) \ - XEmacPs_In32((BaseAddress) + (RegOffset)) - - -/****************************************************************************/ -/** -* -* Write the given register. -* -* @param BaseAddress is the base address of the device -* @param RegOffset is the register offset to be written -* @param Data is the 32-bit value to write to the register -* -* @return None. -* -* @note -* C-style signature: -* void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset, -* u32 Data) -* -*****************************************************************************/ -#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \ - XEmacPs_Out32((BaseAddress) + (RegOffset), (Data)) - -/************************** Function Prototypes *****************************/ -/* - * Perform reset operation to the emacps interface - */ -void XEmacPs_ResetHw(u32 BaseAddr); - -#ifdef __cplusplus - } -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xenv.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xenv.h deleted file mode 100644 index 27cb76810b26ae9a6c249c9fd3eef028f6cf540b..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xenv.h +++ /dev/null @@ -1,177 +0,0 @@ -/****************************************************************************** -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND -* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, -* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION -* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE. -* -* (c) Copyright 2002 Xilinx Inc. -* All rights reserved. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xenv.h -* -* Defines common services that are typically found in a host operating. -* environment. This include file simply includes an OS specific file based -* on the compile-time constant BUILD_ENV_*, where * is the name of the target -* environment. -* -* All services are defined as macros. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00b ch 10/24/02 Added XENV_LINUX -* 1.00a rmm 04/17/02 First release -* </pre> -* -******************************************************************************/ - -#ifndef XENV_H /* prevent circular inclusions */ -#define XENV_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Select which target environment we are operating under - */ - -/* VxWorks target environment */ -#if defined XENV_VXWORKS -#include "xenv_vxworks.h" - -/* Linux target environment */ -#elif defined XENV_LINUX -#include "xenv_linux.h" - -/* Unit test environment */ -#elif defined XENV_UNITTEST -#include "ut_xenv.h" - -/* Integration test environment */ -#elif defined XENV_INTTEST -#include "int_xenv.h" - -/* Standalone environment selected */ -#else -#include "xenv_standalone.h" -#endif - - -/* - * The following comments specify the types and macro wrappers that are - * expected to be defined by the target specific header files - */ - -/**************************** Type Definitions *******************************/ - -/*****************************************************************************/ -/** - * - * XENV_TIME_STAMP - * - * A structure that contains a time stamp used by other time stamp macros - * defined below. This structure is processor dependent. - */ - - -/***************** Macros (Inline Functions) Definitions *********************/ - -/*****************************************************************************/ -/** - * - * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes) - * - * Copies a non-overlapping block of memory. - * - * @param DestPtr is the destination address to copy data to. - * @param SrcPtr is the source address to copy data from. - * @param Bytes is the number of bytes to copy. - * - * @return None - */ - -/*****************************************************************************/ -/** - * - * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes) - * - * Fills an area of memory with constant data. - * - * @param DestPtr is the destination address to set. - * @param Data contains the value to set. - * @param Bytes is the number of bytes to set. - * - * @return None - */ -/*****************************************************************************/ -/** - * - * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr) - * - * Samples the processor's or external timer's time base counter. - * - * @param StampPtr is the storage for the retrieved time stamp. - * - * @return None - */ - -/*****************************************************************************/ -/** - * - * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr) - * - * Computes the delta between the two time stamps. - * - * @param Stamp1Ptr - First sampled time stamp. - * @param Stamp1Ptr - Sedond sampled time stamp. - * - * @return An unsigned int value with units of microseconds. - */ - -/*****************************************************************************/ -/** - * - * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr) - * - * Computes the delta between the two time stamps. - * - * @param Stamp1Ptr - First sampled time stamp. - * @param Stamp1Ptr - Sedond sampled time stamp. - * - * @return An unsigned int value with units of milliseconds. - */ - -/*****************************************************************************//** - * - * XENV_USLEEP(unsigned delay) - * - * Delay the specified number of microseconds. - * - * @param delay is the number of microseconds to delay. - * - * @return None - */ - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xenv_none.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xenv_none.h deleted file mode 100644 index bc837860fc6d961bd9beb2bdfd71414cadb9f633..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xenv_none.h +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************** -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND -* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, -* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION -* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE. -* -* (c) Copyright 2002 Xilinx Inc. -* All rights reserved. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xenv_none.h -* -* This is a legacy file kept for backwards compatibility. -* -* Please modify your code to #include "xenv_standalone.h" instead. -* -* -******************************************************************************/ - -#warning ******************************************************************** -#warning * -#warning * Use of xenv_none.h deprecated. -#warning * Please include the new xenv_standalone.h file instead. -#warning * -#warning ******************************************************************** - -#include "xenv_standalone.h" - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xenv_standalone.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xenv_standalone.h deleted file mode 100644 index f2b2b68871f6a4e8466e8a827257e3e57e453d7f..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xenv_standalone.h +++ /dev/null @@ -1,356 +0,0 @@ -/****************************************************************************** -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND -* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, -* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION -* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE. -* -* (c) Copyright 2002-2008 Xilinx Inc. -* All rights reserved. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xenv_standalone.h -* -* Defines common services specified by xenv.h. -* -* @note -* This file is not intended to be included directly by driver code. -* Instead, the generic xenv.h file is intended to be included by driver -* code. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a wgr 02/28/07 Added cache handling macros. -* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names. -* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being -* used under Xilinx standalone BSP. -* 1.00a xd 11/03/04 Improved support for doxygen. -* 1.00a rmm 03/21/02 First release -* 1.00a wgr 03/22/07 Converted to new coding style. -* 1.00a rpm 06/29/07 Added udelay macro for standalone -* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred -* to in MICROBLAZE section -* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality -* -* </pre> -* -* -******************************************************************************/ - -#ifndef XENV_STANDALONE_H -#define XENV_STANDALONE_H - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ -/****************************************************************************** - * - * Get the processor dependent includes - * - ******************************************************************************/ - -#include <string.h> - -#if defined __MICROBLAZE__ -# include "mb_interface.h" -# include "xparameters.h" /* XPAR constants used below in MB section */ - -#elif defined __PPC__ -# include "sleep.h" -# include "xcache_l.h" /* also include xcache_l.h for caching macros */ -#endif - -/****************************************************************************** - * - * MEMCPY / MEMSET related macros. - * - * The following are straight forward implementations of memset and memcpy. - * - * NOTE: memcpy may not work if source and target memory area are overlapping. - * - ******************************************************************************/ -/*****************************************************************************/ -/** - * - * Copies a non-overlapping block of memory. - * - * @param DestPtr - * Destination address to copy data to. - * - * @param SrcPtr - * Source address to copy data from. - * - * @param Bytes - * Number of bytes to copy. - * - * @return None. - * - * @note - * The use of XENV_MEM_COPY is deprecated. Use memcpy() instead. - * - * @note - * This implemention MAY BREAK work if source and target memory - * area are overlapping. - * - *****************************************************************************/ - -#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \ - memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes) - - - -/*****************************************************************************/ -/** - * - * Fills an area of memory with constant data. - * - * @param DestPtr - * Destination address to copy data to. - * - * @param Data - * Value to set. - * - * @param Bytes - * Number of bytes to copy. - * - * @return None. - * - * @note - * The use of XENV_MEM_FILL is deprecated. Use memset() instead. - * - *****************************************************************************/ - -#define XENV_MEM_FILL(DestPtr, Data, Bytes) \ - memset((void *) DestPtr, (int) Data, (size_t) Bytes) - - - -/****************************************************************************** - * - * TIME related macros - * - ******************************************************************************/ - -/** - * A structure that contains a time stamp used by other time stamp macros - * defined below. This structure is processor dependent. - */ -typedef int XENV_TIME_STAMP; - -/*****************************************************************************/ -/** - * - * Time is derived from the 64 bit PPC timebase register - * - * @param StampPtr is the storage for the retrieved time stamp. - * - * @return None. - * - * @note - * - * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr) - * <br><br> - * This macro must be implemented by the user. - * - *****************************************************************************/ -#define XENV_TIME_STAMP_GET(StampPtr) - -/*****************************************************************************/ -/** - * - * This macro is not yet implemented and always returns 0. - * - * @param Stamp1Ptr is the first sampled time stamp. - * @param Stamp2Ptr is the second sampled time stamp. - * - * @return 0 - * - * @note - * - * This macro must be implemented by the user. - * - *****************************************************************************/ -#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0) - -/*****************************************************************************/ -/** - * - * This macro is not yet implemented and always returns 0. - * - * @param Stamp1Ptr is the first sampled time stamp. - * @param Stamp2Ptr is the second sampled time stamp. - * - * @return 0 - * - * @note - * - * This macro must be implemented by the user. - * - *****************************************************************************/ -#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0) - -/*****************************************************************************/ -/** - * XENV_USLEEP(unsigned delay) - * - * Delay the specified number of microseconds. Not implemented without OS - * support. - * - * @param delay - * Number of microseconds to delay. - * - * @return None. - * - *****************************************************************************/ - -#ifdef __PPC__ -#define XENV_USLEEP(delay) usleep(delay) -#define udelay(delay) usleep(delay) -#else -#define XENV_USLEEP(delay) -#define udelay(delay) -#endif - - -/****************************************************************************** - * - * CACHE handling macros / mappings - * - ******************************************************************************/ -/****************************************************************************** - * - * Processor independent macros - * - ******************************************************************************/ - -#define XCACHE_ENABLE_CACHE() \ - { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); } - -#define XCACHE_DISABLE_CACHE() \ - { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); } - - -/****************************************************************************** - * - * MicroBlaze case - * - * NOTE: Currently the following macros will only work on systems that contain - * only ONE MicroBlaze processor. Also, the macros will only be enabled if the - * system is built using a xparameters.h file. - * - ******************************************************************************/ - -#if defined __MICROBLAZE__ - -/* Check if MicroBlaze data cache was built into the core. - */ -#if (XPAR_MICROBLAZE_USE_DCACHE == 1) -# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache() -# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache() -# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache() - -# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \ - microblaze_invalidate_dcache_range((int)(Addr), (int)(Len)) - -#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1) -# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache() -# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ - microblaze_flush_dcache_range((int)(Addr), (int)(Len)) -#else -# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache() -# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ - microblaze_invalidate_dcache_range((int)(Addr), (int)(Len)) -#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/ - -#else -# define XCACHE_ENABLE_DCACHE() -# define XCACHE_DISABLE_DCACHE() -# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) -# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) -#endif /*XPAR_MICROBLAZE_USE_DCACHE*/ - - -/* Check if MicroBlaze instruction cache was built into the core. - */ -#if (XPAR_MICROBLAZE_USE_ICACHE == 1) -# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache() -# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache() - -# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache() - -# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \ - microblaze_invalidate_icache_range((int)(Addr), (int)(Len)) - -#else -# define XCACHE_ENABLE_ICACHE() -# define XCACHE_DISABLE_ICACHE() -#endif /*XPAR_MICROBLAZE_USE_ICACHE*/ - - -/****************************************************************************** - * - * PowerPC case - * - * Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a - * specific memory region (0x80000001). Each bit (0-30) in the regions - * bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB - * range. - * - * regions --> cached address range - * ------------|-------------------------------------------------- - * 0x80000000 | [0, 0x7FFFFFF] - * 0x00000001 | [0xF8000000, 0xFFFFFFFF] - * 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF] - * - ******************************************************************************/ - -#elif defined __PPC__ - -#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001) -#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache() -#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001) -#define XCACHE_DISABLE_ICACHE() XCache_DisableICache() - -#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \ - XCache_InvalidateDCacheRange((unsigned int)(Addr), (unsigned)(Len)) - -#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ - XCache_FlushDCacheRange((unsigned int)(Addr), (unsigned)(Len)) - -#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache() - - -/****************************************************************************** - * - * Unknown processor / architecture - * - ******************************************************************************/ - -#else -/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */ -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* #ifndef XENV_STANDALONE_H */ - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xenv_vxworks.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xenv_vxworks.h deleted file mode 100644 index 4269f10e0af24750fa9feb76048d7e24ce1a95eb..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xenv_vxworks.h +++ /dev/null @@ -1,258 +0,0 @@ -/****************************************************************************** -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND -* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, -* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION -* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE. -* -* (c) Copyright 2002-2007 Xilinx Inc. -* All rights reserved. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xenv_vxworks.h -* -* Defines common services specified by xenv.h. -* -* @note -* This file is not intended to be included directly by driver code. -* Instead, the generic xenv.h file is intended to be included by driver -* code. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a wgr 02/28/07 Added cache handling macros. -* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names. -* 1.00a xd 11/03/04 Improved support for doxygen. -* rmm 09/13/03 CR 177068: Fix compiler warning in XENV_MEM_FILL -* rmm 10/24/02 Added XENV_USLEEP macro -* 1.00a rmm 07/16/01 First release -* 1.10a wgr 03/22/07 Converted to new coding style. -* </pre> -* -* -******************************************************************************/ - -#ifndef XENV_VXWORKS_H -#define XENV_VXWORKS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xbasic_types.h" -#include "vxWorks.h" -#include "vxLib.h" -#include "sysLibExtra.h" -#include "cacheLib.h" -#include <string.h> - -/*****************************************************************************/ -/** - * - * Copies a non-overlapping block of memory. - * - * @param DestPtr - * Destination address to copy data to. - * - * @param SrcPtr - * Source address to copy data from. - * - * @param Bytes - * Number of bytes to copy. - * - * @return None. - * - * @note XENV_MEM_COPY is deprecated. Use memcpy() instead. - * - *****************************************************************************/ - -#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \ - memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes) - - -/*****************************************************************************/ -/** - * - * Fills an area of memory with constant data. - * - * @param DestPtr - * Destination address to copy data to. - * - * @param Data - * Value to set. - * - * @param Bytes - * Number of bytes to copy. - * - * @return None. - * - * @note XENV_MEM_FILL is deprecated. Use memset() instead. - * - *****************************************************************************/ - -#define XENV_MEM_FILL(DestPtr, Data, Bytes) \ - memset((void *) DestPtr, (int) Data, (size_t) Bytes) - - -#if (CPU_FAMILY==PPC) -/** - * A structure that contains a time stamp used by other time stamp macros - * defined below. This structure is processor dependent. - */ -typedef struct -{ - u32 TimeBaseUpper; - u32 TimeBaseLower; -} XENV_TIME_STAMP; - -/*****************************************************************************/ -/** - * - * Time is derived from the 64 bit PPC timebase register - * - * @param StampPtr is the storage for the retrieved time stamp. - * - * @return None. - * - * @note - * - * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr) - * - *****************************************************************************/ -#define XENV_TIME_STAMP_GET(StampPtr) \ -{ \ - vxTimeBaseGet((UINT32*)&(StampPtr)->TimeBaseUpper, \ - (UINT32*)&(StampPtr)->TimeBaseLower); \ -} - -/*****************************************************************************/ -/** - * - * This macro is not yet implemented and always returns 0. - * - * @param Stamp1Ptr is the first sampled time stamp. - * @param Stamp2Ptr is the second sampled time stamp. - * - * @return 0 - * - * @note None. - * - *****************************************************************************/ -#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0) - -/*****************************************************************************/ -/** - * - * This macro is not yet implemented and always returns 0. - * - * @param Stamp1Ptr is the first sampled time stamp. - * @param Stamp2Ptr is the second sampled time stamp. - * - * @return 0 - * - * @note - * - * None. - * - *****************************************************************************/ -#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0) - - -/* For non-PPC systems the above macros are not defined. Generate a error to - * make the developer aware of the problem. - */ -#else -#error "XENV_TIME_STAMP_GET used in a non-PPC system. Aborting." -#endif - - -/*****************************************************************************/ -/** - * - * Delay the specified number of microseconds. - * - * @param delay - * Number of microseconds to delay. - * - * @return None. - * - *****************************************************************************/ - -#define XENV_USLEEP(delay) sysUsDelay(delay) - -#define udelay(delay) sysUsDelay(delay) - - -/****************************************************************************** - * - * CACHE handling macros / mappings - * - ******************************************************************************/ -/****************************************************************************** - * - * PowerPC case - * - ******************************************************************************/ - -#if (CPU_FAMILY==PPC) - -#define XCACHE_ENABLE_CACHE() \ - { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); } - -#define XCACHE_DISABLE_CACHE() \ - { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); } - - -#define XCACHE_ENABLE_DCACHE() cacheEnable(DATA_CACHE) -#define XCACHE_DISABLE_DCACHE() cacheDisable(DATA_CACHE) -#define XCACHE_ENABLE_ICACHE() cacheEnable(INSTRUCTION_CACHE) -#define XCACHE_DISABLE_ICACHE() cacheDisable(INSTRUCTION_CACHE) - - -#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \ - cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len)) - -#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ - cacheFlush(DATA_CACHE, (void *)(Addr), (Len)) - -#define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \ - cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len)) - -#define XCACHE_FLUSH_ICACHE_RANGE(Addr, Len) \ - cacheFlush(INSTRUCTION_CACHE, (void *)(Addr), (Len)) - - -/****************************************************************************** - * - * Unknown processor / architecture - * - ******************************************************************************/ - -#else -#error "Unknown processor / architecture. Must be PPC for VxWorks." -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* #ifdef XENV_VXWORKS_H */ - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xgpio.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xgpio.h deleted file mode 100644 index bd77b92044c866518ed2ba3a0cc2b578445da1ac..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xgpio.h +++ /dev/null @@ -1,203 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2002-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* @file xgpio.h -* -* This file contains the software API definition of the Xilinx General Purpose -* I/O (XGpio) device driver. -* -* The Xilinx GPIO controller is a soft IP core designed for Xilinx FPGAs and -* contains the following general features: -* - Support for up to 32 I/O discretes for each channel (64 bits total). -* - Each of the discretes can be configured for input or output. -* - Configurable support for dual channels and interrupt generation. -* -* The driver provides interrupt management functions. Implementation of -* interrupt handlers is left to the user. Refer to the provided interrupt -* example in the examples directory for details. -* -* This driver is intended to be RTOS and processor independent. Any needs for -* dynamic memory management, threads or thread mutual exclusion, virtual -* memory, or cache control must be satisfied by the layer above this driver. -* -* <b>Initialization & Configuration</b> -* -* The XGpio_Config structure is used by the driver to configure itself. This -* configuration structure is typically created by the tool-chain based on HW -* build properties. -* -* To support multiple runtime loading and initialization strategies employed -* by various operating systems, the driver instance can be initialized in one -* of the following ways: -* -* - XGpio_Initialize(InstancePtr, DeviceId) - The driver looks up its own -* configuration structure created by the tool-chain based on an ID provided -* by the tool-chain. -* -* - XGpio_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a -* configuration structure provided by the caller. If running in a system -* with address translation, the provided virtual memory base address -* replaces the physical address present in the configuration structure. -* -* @note -* -* This API utilizes 32 bit I/O to the GPIO registers. With less than 32 bits, -* the unused bits from registers are read as zero and written as don't cares. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a rmm 03/13/02 First release -* 2.00a jhl 11/26/03 Added support for dual channels and interrupts -* 2.01a jvb 12/14/05 I separated dependency on the static config table and -* xparameters.h from the driver initialization by moving -* _Initialize and _LookupConfig to _sinit.c. I also added -* the new _CfgInitialize routine. -* 2.11a mta 03/21/07 Updated to new coding style, added GetDataDirection -* 2.12a sv 11/21/07 Updated driver to support access through DCR bus -* 2.12a sv 06/05/08 Updated driver to fix the XGpio_InterruptDisable function -* to properly update the Interrupt Enable register -* 2.13a sdm 08/22/08 Removed support for static interrupt handlers from the MDD -* file -* 3.00a sv 11/21/09 Updated to use HAL Processor APIs. -* Renamed the macros XGpio_mWriteReg to XGpio_WriteReg and -* XGpio_mReadReg to XGpio_ReadReg. Removed the macros -* XGpio_mSetDataDirection, XGpio_mGetDataReg and -* XGpio_mSetDataReg. Users should use XGpio_WriteReg and -* XGpio_ReadReg to achieve the same functionality. -* 3.01a bss 04/18/13 Updated driver tcl to generate Canonical params in -* xparameters.h. CR#698589 -* </pre> -*****************************************************************************/ - -#ifndef XGPIO_H /* prevent circular inclusions */ -#define XGPIO_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files ********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xstatus.h" -#include "xgpio_l.h" - -/************************** Constant Definitions ****************************/ - -/**************************** Type Definitions ******************************/ - -/** - * This typedef contains configuration information for the device. - */ -typedef struct { - u16 DeviceId; /* Unique ID of device */ - u32 BaseAddress; /* Device base address */ - int InterruptPresent; /* Are interrupts supported in h/w */ - int IsDual; /* Are 2 channels supported in h/w */ -} XGpio_Config; - -/** - * The XGpio driver instance data. The user is required to allocate a - * variable of this type for every GPIO device in the system. A pointer - * to a variable of this type is then passed to the driver API functions. - */ -typedef struct { - u32 BaseAddress; /* Device base address */ - u32 IsReady; /* Device is initialized and ready */ - int InterruptPresent; /* Are interrupts supported in h/w */ - int IsDual; /* Are 2 channels supported in h/w */ -} XGpio; - -/***************** Macros (Inline Functions) Definitions ********************/ - - -/************************** Function Prototypes *****************************/ - -/* - * Initialization functions in xgpio_sinit.c - */ -int XGpio_Initialize(XGpio *InstancePtr, u16 DeviceId); -XGpio_Config *XGpio_LookupConfig(u16 DeviceId); - -/* - * API Basic functions implemented in xgpio.c - */ -int XGpio_CfgInitialize(XGpio *InstancePtr, XGpio_Config * Config, - u32 EffectiveAddr); -void XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel, - u32 DirectionMask); -u32 XGpio_GetDataDirection(XGpio *InstancePtr, unsigned Channel); -u32 XGpio_DiscreteRead(XGpio *InstancePtr, unsigned Channel); -void XGpio_DiscreteWrite(XGpio *InstancePtr, unsigned Channel, u32 Mask); - - -/* - * API Functions implemented in xgpio_extra.c - */ -void XGpio_DiscreteSet(XGpio *InstancePtr, unsigned Channel, u32 Mask); -void XGpio_DiscreteClear(XGpio *InstancePtr, unsigned Channel, u32 Mask); - -/* - * API Functions implemented in xgpio_selftest.c - */ -int XGpio_SelfTest(XGpio *InstancePtr); - -/* - * API Functions implemented in xgpio_intr.c - */ -void XGpio_InterruptGlobalEnable(XGpio *InstancePtr); -void XGpio_InterruptGlobalDisable(XGpio *InstancePtr); -void XGpio_InterruptEnable(XGpio *InstancePtr, u32 Mask); -void XGpio_InterruptDisable(XGpio *InstancePtr, u32 Mask); -void XGpio_InterruptClear(XGpio *InstancePtr, u32 Mask); -u32 XGpio_InterruptGetEnabled(XGpio *InstancePtr); -u32 XGpio_InterruptGetStatus(XGpio *InstancePtr); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xgpio_l.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xgpio_l.h deleted file mode 100644 index 5b3480706f8dffa08c7a080af2af1709f57be955..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xgpio_l.h +++ /dev/null @@ -1,235 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2002-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xgpio_l.h -* -* This header file contains identifiers and driver functions (or -* macros) that can be used to access the device. The user should refer to the -* hardware device specification for more details of the device operation. -* -* The macros that are available in this file use a multiply to calculate the -* addresses of registers. The user can control whether that multiply is done -* at run time or at compile time. A constant passed as the channel parameter -* will cause the multiply to be done at compile time. A variable passed as the -* channel parameter will cause it to occur at run time. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a jhl 04/24/02 First release of low level driver -* 2.00a jhl 11/26/03 Added support for dual channels and interrupts. This -* change required the functions to be changed such that -* the interface is not compatible with previous versions. -* See the examples in the example directory for macros -* to help compile an application that was designed for -* previous versions of the driver. The interrupt registers -* are accessible using the ReadReg and WriteReg macros and -* a channel parameter was added to the other macros. -* 2.11a mta 03/21/07 Updated to new coding style -* 2.12a sv 11/21/07 Updated driver to support access through DCR bus. -* 3.00a sv 11/21/09 Renamed the macros XGpio_mWriteReg to XGpio_WriteReg -* XGpio_mReadReg to XGpio_ReadReg. -* Removed the macros XGpio_mSetDataDirection, -* XGpio_mGetDataReg and XGpio_mSetDataReg. Users -* should use XGpio_WriteReg/XGpio_ReadReg to achieve the -* same functionality. -* </pre> -* -******************************************************************************/ - -#ifndef XGPIO_L_H /* prevent circular inclusions */ -#define XGPIO_L_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xil_io.h" - -/* - * XPAR_XGPIO_USE_DCR_BRIDGE has to be set to 1 if the GPIO device is - * accessed through a DCR bus connected to a bridge - */ -#define XPAR_XGPIO_USE_DCR_BRIDGE 0 - - -#if (XPAR_XGPIO_USE_DCR_BRIDGE != 0) -#include "xio_dcr.h" -#endif - -/************************** Constant Definitions *****************************/ - -/** @name Registers - * - * Register offsets for this device. - * @{ - */ -#if (XPAR_XGPIO_USE_DCR_BRIDGE != 0) - -#define XGPIO_DATA_OFFSET 0x0 /**< Data register for 1st channel */ -#define XGPIO_TRI_OFFSET 0x1 /**< I/O direction reg for 1st channel */ -#define XGPIO_DATA2_OFFSET 0x2 /**< Data register for 2nd channel */ -#define XGPIO_TRI2_OFFSET 0x3 /**< I/O direction reg for 2nd channel */ - -#define XGPIO_GIE_OFFSET 0x47 /**< Global interrupt enable register */ -#define XGPIO_ISR_OFFSET 0x48 /**< Interrupt status register */ -#define XGPIO_IER_OFFSET 0x4A /**< Interrupt enable register */ - -#else - -#define XGPIO_DATA_OFFSET 0x0 /**< Data register for 1st channel */ -#define XGPIO_TRI_OFFSET 0x4 /**< I/O direction reg for 1st channel */ -#define XGPIO_DATA2_OFFSET 0x8 /**< Data register for 2nd channel */ -#define XGPIO_TRI2_OFFSET 0xC /**< I/O direction reg for 2nd channel */ - -#define XGPIO_GIE_OFFSET 0x11C /**< Glogal interrupt enable register */ -#define XGPIO_ISR_OFFSET 0x120 /**< Interrupt status register */ -#define XGPIO_IER_OFFSET 0x128 /**< Interrupt enable register */ - -#endif - -/* @} */ - -/* The following constant describes the offset of each channels data and - * tristate register from the base address. - */ -#define XGPIO_CHAN_OFFSET 8 - -/** @name Interrupt Status and Enable Register bitmaps and masks - * - * Bit definitions for the interrupt status register and interrupt enable - * registers. - * @{ - */ -#define XGPIO_IR_MASK 0x3 /**< Mask of all bits */ -#define XGPIO_IR_CH1_MASK 0x1 /**< Mask for the 1st channel */ -#define XGPIO_IR_CH2_MASK 0x2 /**< Mask for the 2nd channel */ -/*@}*/ - - -/** @name Global Interrupt Enable Register bitmaps and masks - * - * Bit definitions for the Global Interrupt Enable register - * @{ - */ -#define XGPIO_GIE_GINTR_ENABLE_MASK 0x80000000 -/*@}*/ - - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - /* - * Define the appropriate I/O access method to memory mapped I/O or DCR. - */ -#if (XPAR_XGPIO_USE_DCR_BRIDGE != 0) - -#define XGpio_In32 XIo_DcrIn -#define XGpio_Out32 XIo_DcrOut - -#else - -#define XGpio_In32 Xil_In32 -#define XGpio_Out32 Xil_Out32 - -#endif - - -/****************************************************************************/ -/** -* -* Write a value to a GPIO register. A 32 bit write is performed. If the -* GPIO core is implemented in a smaller width, only the least significant data -* is written. -* -* @param BaseAddress is the base address of the GPIO device. -* @param RegOffset is the register offset from the base to write to. -* @param Data is the data written to the register. -* -* @return None. -* -* @note C-style signature: -* void XGpio_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) -* -****************************************************************************/ -#define XGpio_WriteReg(BaseAddress, RegOffset, Data) \ - XGpio_Out32((BaseAddress) + (RegOffset), (u32)(Data)) - -/****************************************************************************/ -/** -* -* Read a value from a GPIO register. A 32 bit read is performed. If the -* GPIO core is implemented in a smaller width, only the least -* significant data is read from the register. The most significant data -* will be read as 0. -* -* @param BaseAddress is the base address of the GPIO device. -* @param RegOffset is the register offset from the base to read from. -* -* @return Data read from the register. -* -* @note C-style signature: -* u32 XGpio_ReadReg(u32 BaseAddress, u32 RegOffset) -* -****************************************************************************/ -#define XGpio_ReadReg(BaseAddress, RegOffset) \ - XGpio_In32((BaseAddress) + (RegOffset)) - -/************************** Function Prototypes ******************************/ - -/************************** Variable Definitions *****************************/ - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xgpiops.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xgpiops.h deleted file mode 100644 index 1b8eb4ff27eaa05ebcc1ce84c43a71f3b8fd4a5e..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xgpiops.h +++ /dev/null @@ -1,262 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xgpiops.h -* -* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO -* Controller. -* -* The GPIO Controller supports the following features: -* - 4 banks -* - Masked writes (There are no masked reads) -* - Bypass mode -* - Configurable Interrupts (Level/Edge) -* -* This driver is intended to be RTOS and processor independent. Any needs for -* dynamic memory management, threads or thread mutual exclusion, virtual -* memory, or cache control must be satisfied by the layer above this driver. - -* This driver supports all the features listed above, if applicable. -* -* <b>Driver Description</b> -* -* The device driver enables higher layer software (e.g., an application) to -* communicate to the GPIO. -* -* <b>Interrupts</b> -* -* The driver provides interrupt management functions and an interrupt handler. -* Users of this driver need to provide callback functions. An interrupt handler -* example is available with the driver. -* -* <b>Threads</b> -* -* This driver is not thread safe. Any needs for threads or thread mutual -* exclusion must be satisfied by the layer above this driver. -* -* <b>Asserts</b> -* -* Asserts are used within all Xilinx drivers to enforce constraints on argument -* values. Asserts can be turned off on a system-wide basis by defining, at -* compile time, the NDEBUG identifier. By default, asserts are turned on and it -* is recommended that users leave asserts on during development. -* -* <b>Building the driver</b> -* -* The XGpioPs driver is composed of several source files. This allows the user -* to build and link only those parts of the driver that are necessary. -* <br><br> -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a sv 01/15/10 First Release -* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin -* XGpioPs_GetMode, XGpioPs_GetModePin as they are not -* relevant to Zynq device.The interrupts are disabled -* for output pins on all banks during initialization. -* 1.02a hk 08/22/13 Added low level reset API -* </pre> -* -******************************************************************************/ -#ifndef XGPIOPS_H /* prevent circular inclusions */ -#define XGPIOPS_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xstatus.h" -#include "xgpiops_hw.h" - -/************************** Constant Definitions *****************************/ - -/** @name Interrupt types - * @{ - * The following constants define the interrupt types that can be set for each - * GPIO pin. - */ -#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0 /**< Interrupt on Rising edge */ -#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 1 /**< Interrupt Falling edge */ -#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 2 /**< Interrupt on both edges */ -#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 3 /**< Interrupt on high level */ -#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 4 /**< Interrupt on low level */ -/*@}*/ - -#define XGPIOPS_BANK0 0 /**< GPIO Bank 0 */ -#define XGPIOPS_BANK1 1 /**< GPIO Bank 1 */ -#define XGPIOPS_BANK2 2 /**< GPIO Bank 2 */ -#define XGPIOPS_BANK3 3 /**< GPIO Bank 3 */ - -#define XGPIOPS_MAX_BANKS 4 /**< Max banks in a GPIO device */ -#define XGPIOPS_BANK_MAX_PINS 32 /**< Max pins in a GPIO bank */ - -#define XGPIOPS_DEVICE_MAX_PIN_NUM 118 /*< Max pins in the GPIO device - * 0 - 31, Bank 0 - * 32 - 53, Bank 1 - * 54 - 85, Bank 2 - * 86 - 117, Bank 3 - */ - -/**************************** Type Definitions *******************************/ - -/****************************************************************************/ -/** - * This handler data type allows the user to define a callback function to - * handle the interrupts for the GPIO device. The application using this - * driver is expected to define a handler of this type, to support interrupt - * driven mode. The handler executes in an interrupt context such that minimal - * processing should be performed. - * - * @param CallBackRef is a callback reference passed in by the upper layer - * when setting the callback functions for a GPIO bank. It is - * passed back to the upper layer when the callback is invoked. Its - * type is not important to the driver component, so it is a void - * pointer. - * @param Bank is the bank for which the interrupt status has changed. - * @param Status is the Interrupt status of the GPIO bank. - * - *****************************************************************************/ -typedef void (*XGpioPs_Handler) (void *CallBackRef, int Bank, u32 Status); - -/** - * This typedef contains configuration information for a device. - */ -typedef struct { - u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddr; /**< Register base address */ -} XGpioPs_Config; - -/** - * The XGpioPs driver instance data. The user is required to allocate a - * variable of this type for the GPIO device in the system. A pointer - * to a variable of this type is then passed to the driver API functions. - */ -typedef struct { - XGpioPs_Config GpioConfig; /**< Device configuration */ - u32 IsReady; /**< Device is initialized and ready */ - XGpioPs_Handler Handler; /**< Status handlers for all banks */ - void *CallBackRef; /**< Callback ref for bank handlers */ -} XGpioPs; - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/* - * Functions in xgpiops.c - */ -int XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr, - u32 EffectiveAddr); - -/* - * Bank APIs in xgpiops.c - */ -u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank); -void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data); -void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction); -u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank); -void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 Enable); -u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank); -void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank); - -/* - * Pin APIs in xgpiops.c - */ -int XGpioPs_ReadPin(XGpioPs *InstancePtr, int Pin); -void XGpioPs_WritePin(XGpioPs *InstancePtr, int Pin, int Data); -void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, int Pin, int Direction); -int XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, int Pin); -void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, int Pin, int Enable); -int XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, int Pin); - -/* - * Diagnostic functions in xgpiops_selftest.c - */ -int XGpioPs_SelfTest(XGpioPs *InstancePtr); - -/* - * Functions in xgpiops_intr.c - */ -/* - * Bank APIs in xgpiops_intr.c - */ -void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask); -void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask); -u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank); -u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank); -void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask); -void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType, - u32 IntrPolarity, u32 IntrOnAny); -void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType, - u32 *IntrPolarity, u32 *IntrOnAny); -void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef, - XGpioPs_Handler FuncPtr); -void XGpioPs_IntrHandler(XGpioPs *InstancePtr); - -/* - * Pin APIs in xgpiops_intr.c - */ -void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, int Pin, u8 IrqType); -u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, int Pin); - -void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, int Pin); -void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, int Pin); -int XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, int Pin); -int XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, int Pin); -void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, int Pin); - -/* - * Functions in xgpiops_sinit.c - */ -XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xgpiops_hw.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xgpiops_hw.h deleted file mode 100644 index 28c4993fa4d352ac1fecba11a2ed31e81f17c7f0..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xgpiops_hw.h +++ /dev/null @@ -1,158 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xgpiops_hw.h -* -* This header file contains the identifiers and basic driver functions (or -* macros) that can be used to access the device. Other driver functions -* are defined in xgpiops.h. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------- -* 1.00a sv 01/15/10 First Release -* 1.02a hk 08/22/13 Added low level reset API function prototype and -* related constant definitions -* </pre> -* -******************************************************************************/ -#ifndef XGPIOPS_HW_H /* prevent circular inclusions */ -#define XGPIOPS_HW_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xil_io.h" - -/************************** Constant Definitions *****************************/ - -/** @name Register offsets for the GPIO. Each register is 32 bits. - * @{ - */ -#define XGPIOPS_DATA_LSW_OFFSET 0x000 /* Mask and Data Register LSW, WO */ -#define XGPIOPS_DATA_MSW_OFFSET 0x004 /* Mask and Data Register MSW, WO */ -#define XGPIOPS_DATA_OFFSET 0x040 /* Data Register, RW */ -#define XGPIOPS_DIRM_OFFSET 0x204 /* Direction Mode Register, RW */ -#define XGPIOPS_OUTEN_OFFSET 0x208 /* Output Enable Register, RW */ -#define XGPIOPS_INTMASK_OFFSET 0x20C /* Interrupt Mask Register, RO */ -#define XGPIOPS_INTEN_OFFSET 0x210 /* Interrupt Enable Register, WO */ -#define XGPIOPS_INTDIS_OFFSET 0x214 /* Interrupt Disable Register, WO*/ -#define XGPIOPS_INTSTS_OFFSET 0x218 /* Interrupt Status Register, RO */ -#define XGPIOPS_INTTYPE_OFFSET 0x21C /* Interrupt Type Register, RW */ -#define XGPIOPS_INTPOL_OFFSET 0x220 /* Interrupt Polarity Register, RW */ -#define XGPIOPS_INTANY_OFFSET 0x224 /* Interrupt On Any Register, RW */ -/* @} */ - -/** @name Register offsets for each Bank. - * @{ - */ -#define XGPIOPS_DATA_MASK_OFFSET 0x8 /* Data/Mask Registers offset */ -#define XGPIOPS_DATA_BANK_OFFSET 0x4 /* Data Registers offset */ -#define XGPIOPS_REG_MASK_OFFSET 0x40 /* Registers offset */ -/* @} */ - -/* For backwards compatibility */ -#define XGPIOPS_BYPM_MASK_OFFSET XGPIOPS_REG_MASK_OFFSET - -/** @name Interrupt type reset values for each bank - * @{ - */ -#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFF -#define XGPIOPS_INTTYPE_BANK1_RESET 0x3FFFFFFF -#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFF -#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFF -/* @} */ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/****************************************************************************/ -/** -* -* This macro reads the given register. -* -* @param BaseAddr is the base address of the device. -* @param RegOffset is the register offset to be read. -* -* @return The 32-bit value of the register -* -* @note None. -* -*****************************************************************************/ -#define XGpioPs_ReadReg(BaseAddr, RegOffset) \ - Xil_In32((BaseAddr) + (RegOffset)) - -/****************************************************************************/ -/** -* -* This macro writes to the given register. -* -* @param BaseAddr is the base address of the device. -* @param RegOffset is the offset of the register to be written. -* @param Data is the 32-bit value to write to the register. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \ - Xil_Out32((BaseAddr) + (RegOffset), (Data)) - -/************************** Function Prototypes ******************************/ - -void XGpioPs_ResetHw(u32 BaseAddress); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* XGPIOPS_HW_H */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xiicps.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xiicps.h deleted file mode 100644 index de89a99018a598d245faa47e42bfe8a715068c72..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xiicps.h +++ /dev/null @@ -1,394 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xiicps.h -* -* This is an implementation of IIC driver in the PS block. The device can -* be either a master or a slave on the IIC bus. This implementation supports -* both interrupt mode transfer and polled mode transfer. Only 7-bit address -* is used in the driver, although the hardware also supports 10-bit address. -* -* IIC is a 2-wire serial interface. The master controls the clock, so it can -* regulate when it wants to send or receive data. The slave is under control of -* the master, it must respond quickly since it has no control of the clock and -* must send/receive data as fast or as slow as the master does. -* -* The higher level software must implement a higher layer protocol to inform -* the slave what to send to the master. -* -* <b>Initialization & Configuration</b> -* -* The XIicPs_Config structure is used by the driver to configure itself. This -* configuration structure is typically created by the tool-chain based on HW -* build properties. -* -* To support multiple runtime loading and initialization strategies employed by -* various operating systems, the driver instance can be initialized in the -* following way: -* -* - XIicPs_LookupConfig(DeviceId) - Use the device identifier to find -* the static configuration structure defined in xiicps_g.c. This is -* setup by the tools. For some operating systems the config structure -* will be initialized by the software and this call is not needed. -* -* - XIicPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a -* configuration structure provided by the caller. If running in a -* system with address translation, the provided virtual memory base -* address replaces the physical address in the configuration -* structure. -* -* <b>Multiple Masters</b> -* -* More than one master can exist, bus arbitration is defined in the IIC -* standard. Lost of arbitration causes arbitration loss interrupt on the device. -* -* <b>Multiple Slaves</b> -* -* Multiple slaves are supported by selecting them with unique addresses. It is -* up to the system designer to be sure all devices on the IIC bus have -* unique addresses. -* -* <b>Addressing</b> -* -* The IIC hardware can use 7 or 10 bit addresses. The driver provides the -* ability to control which address size is sent in messages as a master to a -* slave device. -* -* <b>FIFO Size </b> -* The hardware FIFO is 32 bytes deep. The user must know the limitations of -* other IIC devices on the bus. Some are only able to receive a limited number -* of bytes in a single transfer. -* -* <b>Data Rates</b> -* -* The data rate is set by values in the control register. The formula for -* determining the correct register values is: -* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1)) -* -* When the device is configured as a slave, the slck setting controls the -* sample rate and so must be set to be at least as fast as the fastest scl -* expected to be seen in the system. -* -* <b>Polled Mode Operation</b> -* -* This driver supports polled mode transfers. -* -* <b>Interrupts</b> -* -* The user must connect the interrupt handler of the driver, -* XIicPs_InterruptHandler to an interrupt system such that it will be called -* when an interrupt occurs. This function does not save and restore the -* processor context such that the user must provide this processing. -* -* The driver handles the following interrupts: -* - Transfer complete -* - More Data -* - Transfer not Acknowledged -* - Transfer Time out -* - Monitored slave ready - master mode only -* - Receive Overflow -* - Transmit FIFO overflow -* - Receive FIFO underflow -* - Arbitration lost -* -* <b>Bus Busy</b> -* -* Bus busy is checked before the setup of a master mode device, to avoid -* unnecessary arbitration loss interrupt. -* -* <b>RTOS Independence</b> -* -* This driver is intended to be RTOS and processor independent. It works with -* physical addresses only. Any needs for dynamic memory management, threads or -* thread mutual exclusion, virtual memory, or cache control must be satisfied by -* the layer above this driver. -* -* @note -* . Less than FIFO size transfers work for both 100 KHz and 400 KHz. -* . Larger than FIFO size interrupt-driven transfers are not reliable on -* busy systems where interrupt latency is high. -* . Larger than FIFO size interrupt-driven transfers are not reliable for -* data rate of 400 KHz. -* . Larger than FIFO size polled mode transfers work reliably. -* -* <pre> MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------ -------- ----------------------------------------------- -* 1.00a drg/jz 01/30/08 First release -* 1.00a sdm 09/21/11 Fixed an issue in the XIicPs_SetOptions and -* XIicPs_ClearOptions where the InstancePtr->Options -* was not updated correctly. -* Updated the InstancePtr->Options in the -* XIicPs_CfgInitialize by calling XIicPs_GetOptions. -* Updated the XIicPs_SetupMaster to not check for -* Bus Busy condition when the Hold Bit is set. -* Removed some unused variables. -* 1.01a sg 03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a -* check for transfer completion is added, which indicates -* the completion of current transfer. -* 1.02a sg 08/29/12 Updated the logic to arrive at the best divisors -* to achieve I2C clock with minimum error for -* CR #674195 -* 1.03a hk 05/04/13 Initialized BestDivA and BestDivB to 0. -* This is fix for CR#704398 to remove warning. -* -* </pre> -* -******************************************************************************/ - -#ifndef XIICPS_H /* prevent circular inclusions */ -#define XIICPS_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xstatus.h" -#include "xiicps_hw.h" - -/************************** Constant Definitions *****************************/ - -/** @name Configuration options - * - * The following options may be specified or retrieved for the device and - * enable/disable additional features of the IIC. Each of the options - * are bit fields, so more than one may be specified. - * - * @{ - */ -#define XIICPS_7_BIT_ADDR_OPTION 0x01 /**< 7-bit address mode */ -#define XIICPS_10_BIT_ADDR_OPTION 0x02 /**< 10-bit address mode */ -#define XIICPS_SLAVE_MON_OPTION 0x04 /**< Slave monitor mode */ -#define XIICPS_REP_START_OPTION 0x08 /**< Repeated Start */ -/*@}*/ - -/** @name Callback events - * - * These constants specify the handler events that are passed to an application - * event handler from the driver. These constants are bit masks such that - * more than one event can be passed to the handler. - * - * @{ - */ -#define XIICPS_EVENT_COMPLETE_SEND 0x0001 /**< Transmit Complete Event*/ -#define XIICPS_EVENT_COMPLETE_RECV 0x0002 /**< Receive Complete Event*/ -#define XIICPS_EVENT_TIME_OUT 0x0004 /**< Transfer timed out */ -#define XIICPS_EVENT_ERROR 0x0008 /**< Receive error */ -#define XIICPS_EVENT_ARB_LOST 0x0010 /**< Arbitration lost */ -#define XIICPS_EVENT_NACK 0x0020 /**< NACK Received */ -#define XIICPS_EVENT_SLAVE_RDY 0x0040 /**< Slave ready */ -#define XIICPS_EVENT_RX_OVR 0x0080 /**< RX overflow */ -#define XIICPS_EVENT_TX_OVR 0x0100 /**< TX overflow */ -#define XIICPS_EVENT_RX_UNF 0x0200 /**< RX underflow */ -/*@}*/ - -/** @name Role constants - * - * These constants are used to pass into the device setup routines to - * set up the device according to transfer direction. - */ -#define SENDING_ROLE 1 /**< Transfer direction is sending */ -#define RECVING_ROLE 0 /**< Transfer direction is receiving */ - - -/**************************** Type Definitions *******************************/ - -/** -* The handler data type allows the user to define a callback function to -* respond to interrupt events in the system. This function is executed -* in interrupt context, so amount of processing should be minimized. -* -* @param CallBackRef is the callback reference passed in by the upper -* layer when setting the callback functions, and passed back to -* the upper layer when the callback is invoked. Its type is -* not important to the driver, so it is a void pointer. -* @param StatusEvent indicates one or more status events that occurred. -*/ -typedef void (*XIicPs_IntrHandler) (void *CallBackRef, u32 StatusEvent); - -/** - * This typedef contains configuration information for the device. - */ -typedef struct { - u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddress; /**< Base address of the device */ - u32 InputClockHz; /**< Input clock frequency */ -} XIicPs_Config; - -/** - * The XIicPs driver instance data. The user is required to allocate a - * variable of this type for each IIC device in the system. A pointer - * to a variable of this type is then passed to the driver API functions. - */ -typedef struct { - XIicPs_Config Config; /* Configuration structure */ - u32 IsReady; /* Device is initialized and ready */ - u32 Options; /* Options set in the device */ - - u8 *SendBufferPtr; /* Pointer to send buffer */ - u8 *RecvBufferPtr; /* Pointer to recv buffer */ - int SendByteCount; /* Number of bytes still expected to send */ - int RecvByteCount; /* Number of bytes still expected to receive */ - - XIicPs_IntrHandler StatusHandler; /* Event handler function */ - void *CallBackRef; /* Callback reference for event handler */ -} XIicPs; - -/***************** Macros (Inline Functions) Definitions *********************/ -/****************************************************************************/ -/* -* -* Place one byte into the transmit FIFO. -* -* @param InstancePtr is the instance of IIC -* -* @return None. -* -* @note C-Style signature: -* void XIicPs_SendByte(XIicPs *InstancePtr) -* -*****************************************************************************/ -#define XIicPs_SendByte(InstancePtr) \ -{ \ - XIicPs_Out32((InstancePtr)->Config.BaseAddress \ - + XIICPS_DATA_OFFSET, \ - *(InstancePtr)->SendBufferPtr ++); \ - (InstancePtr)->SendByteCount --; \ -} - -/****************************************************************************/ -/* -* -* Receive one byte from FIFO. -* -* @param InstancePtr is the instance of IIC -* -* @return None. -* -* @note C-Style signature: -* u8 XIicPs_RecvByte(XIicPs *InstancePtr) -* -*****************************************************************************/ -#define XIicPs_RecvByte(InstancePtr) \ -{ \ - *(InstancePtr)->RecvBufferPtr ++ = \ - (u8)XIicPs_In32((InstancePtr)->Config.BaseAddress \ - + XIICPS_DATA_OFFSET); \ - (InstancePtr)->RecvByteCount --; \ -} - -/************************** Function Prototypes ******************************/ - -/* - * Function for configuration lookup, in xiicps_sinit.c - */ -XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId); - -/* - * Functions for general setup, in xiicps.c - */ -int XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config * Config, - u32 EffectiveAddr); - -void XIicPs_Abort(XIicPs *InstancePtr); -void XIicPs_Reset(XIicPs *InstancePtr); - -int XIicPs_BusIsBusy(XIicPs *InstancePtr); - -/* - * Functions for interrupts, in xiicps_intr.c - */ -void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef, - XIicPs_IntrHandler FuncPtr); - -/* - * Functions for device as master, in xiicps_master.c - */ -void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount, - u16 SlaveAddr); -void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount, - u16 SlaveAddr); -int XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount, - u16 SlaveAddr); -int XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount, - u16 SlaveAddr); -void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr); -void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr); -void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr); - -/* - * Functions for device as slave, in xiicps_slave.c - */ -void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr); -void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount); -void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount); -int XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount); -int XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount); -void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr); - -/* - * Functions for selftest, in xiicps_selftest.c - */ -int XIicPs_SelfTest(XIicPs *InstancePtr); - -/* - * Functions for setting and getting data rate, in xiicps_options.c - */ -int XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options); -int XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options); -u32 XIicPs_GetOptions(XIicPs *InstancePtr); - -int XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz); -u32 XIicPs_GetSClk(XIicPs *InstancePtr); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xiicps_hw.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xiicps_hw.h deleted file mode 100644 index 69b71ce09c70dc9e5c0c4ba3147b2f9a5db45523..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xiicps_hw.h +++ /dev/null @@ -1,388 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xiicps_hw.h -* -* This header file contains the hardware definition for an IIC device. -* It includes register definitions and interface functions to read/write -* the registers. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------ -------- ----------------------------------------------- -* 1.00a drg/jz 01/30/10 First release -* 1.04a kpc 11/07/13 Added function prototype. -* </pre> -* -******************************************************************************/ -#ifndef XIICPS_HW_H /* prevent circular inclusions */ -#define XIICPS_HW_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xil_io.h" - -/************************** Constant Definitions *****************************/ - -/** @name Register Map - * - * Register offsets for the IIC. - * @{ - */ -#define XIICPS_CR_OFFSET 0x00 /**< 32-bit Control */ -#define XIICPS_SR_OFFSET 0x04 /**< Status */ -#define XIICPS_ADDR_OFFSET 0x08 /**< IIC Address */ -#define XIICPS_DATA_OFFSET 0x0C /**< IIC FIFO Data */ -#define XIICPS_ISR_OFFSET 0x10 /**< Interrupt Status */ -#define XIICPS_TRANS_SIZE_OFFSET 0x14 /**< Transfer Size */ -#define XIICPS_SLV_PAUSE_OFFSET 0x18 /**< Slave monitor pause */ -#define XIICPS_TIME_OUT_OFFSET 0x1C /**< Time Out */ -#define XIICPS_IMR_OFFSET 0x20 /**< Interrupt Enabled Mask */ -#define XIICPS_IER_OFFSET 0x24 /**< Interrupt Enable */ -#define XIICPS_IDR_OFFSET 0x28 /**< Interrupt Disable */ -/* @} */ - -/** @name Control Register - * - * This register contains various control bits that - * affects the operation of the IIC controller. Read/Write. - * @{ - */ - -#define XIICPS_CR_DIV_A_MASK 0x0000C000 /**< Clock Divisor A */ -#define XIICPS_CR_DIV_A_SHIFT 14 /**< Clock Divisor A shift */ -#define XIICPS_DIV_A_MAX 4 /**< Maximum value of Divisor A */ -#define XIICPS_CR_DIV_B_MASK 0x00003F00 /**< Clock Divisor B */ -#define XIICPS_CR_DIV_B_SHIFT 8 /**< Clock Divisor B shift */ -#define XIICPS_CR_CLR_FIFO_MASK 0x00000040 /**< Clear FIFO, auto clears*/ -#define XIICPS_CR_SLVMON_MASK 0x00000020 /**< Slave monitor mode */ -#define XIICPS_CR_HOLD_MASK 0x00000010 /**< Hold bus 1=Hold scl, - 0=terminate transfer */ -#define XIICPS_CR_ACKEN_MASK 0x00000008 /**< Enable TX of ACK when - Master receiver*/ -#define XIICPS_CR_NEA_MASK 0x00000004 /**< Addressing Mode 1=7 bit, - 0=10 bit */ -#define XIICPS_CR_MS_MASK 0x00000002 /**< Master mode bit 1=Master, - 0=Slave */ -#define XIICPS_CR_RD_WR_MASK 0x00000001 /**< Read or Write Master - transfer 0=Transmitter, - 1=Receiver*/ -#define XIICPS_CR_RESET_VALUE 0 /**< Reset value of the Control - register */ -/* @} */ - -/** @name IIC Status Register - * - * This register is used to indicate status of the IIC controller. Read only - * @{ - */ -#define XIICPS_SR_BA_MASK 0x00000100 /**< Bus Active Mask */ -#define XIICPS_SR_RXOVF_MASK 0x00000080 /**< Receiver Overflow Mask */ -#define XIICPS_SR_TXDV_MASK 0x00000040 /**< Transmit Data Valid Mask */ -#define XIICPS_SR_RXDV_MASK 0x00000020 /**< Receiver Data Valid Mask */ -#define XIICPS_SR_RXRW_MASK 0x00000008 /**< Receive read/write Mask */ -/* @} */ - -/** @name IIC Address Register - * - * Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0]. - * A write access to this register always initiates a transfer if the IIC is in - * master mode. Read/Write - * @{ - */ -#define XIICPS_ADDR_MASK 0x000003FF /**< IIC Address Mask */ -/* @} */ - -/** @name IIC Data Register - * - * When written to, the data register sets data to transmit. When read from, the - * data register reads the last received byte of data. Read/Write - * @{ - */ -#define XIICPS_DATA_MASK 0x000000FF /**< IIC Data Mask */ -/* @} */ - -/** @name IIC Interrupt Registers - * - * <b>IIC Interrupt Status Register</b> - * - * This register holds the interrupt status flags for the IIC controller. Some - * of the flags are level triggered - * - i.e. are set as long as the interrupt condition exists. Other flags are - * edge triggered, which means they are set one the interrupt condition occurs - * then remain set until they are cleared by software. - * The interrupts are cleared by writing a one to the interrupt bit position - * in the Interrupt Status Register. Read/Write. - * - * <b>IIC Interrupt Enable Register</b> - * - * This register is used to enable interrupt sources for the IIC controller. - * Writing a '1' to a bit in this register clears the corresponding bit in the - * IIC Interrupt Mask register. Write only. - * - * <b>IIC Interrupt Disable Register </b> - * - * This register is used to disable interrupt sources for the IIC controller. - * Writing a '1' to a bit in this register sets the corresponding bit in the - * IIC Interrupt Mask register. Write only. - * - * <b>IIC Interrupt Mask Register</b> - * - * This register shows the enabled/disabled status of each IIC controller - * interrupt source. A bit set to 1 will ignore the corresponding interrupt in - * the status register. A bit set to 0 means the interrupt is enabled. - * All mask bits are set and all interrupts are disabled after reset. Read only. - * - * All four registers have the same bit definitions. They are only defined once - * for each of the Interrupt Enable Register, Interrupt Disable Register, - * Interrupt Mask Register, and Interrupt Status Register - * @{ - */ - -#define XIICPS_IXR_ARB_LOST_MASK 0x00000200 /**< Arbitration Lost Interrupt - mask */ -#define XIICPS_IXR_RX_UNF_MASK 0x00000080 /**< FIFO Recieve Underflow - Interrupt mask */ -#define XIICPS_IXR_TX_OVR_MASK 0x00000040 /**< Transmit Overflow - Interrupt mask */ -#define XIICPS_IXR_RX_OVR_MASK 0x00000020 /**< Receive Overflow Interrupt - mask */ -#define XIICPS_IXR_SLV_RDY_MASK 0x00000010 /**< Monitored Slave Ready - Interrupt mask */ -#define XIICPS_IXR_TO_MASK 0x00000008 /**< Transfer Time Out - Interrupt mask */ -#define XIICPS_IXR_NACK_MASK 0x00000004 /**< NACK Interrupt mask */ -#define XIICPS_IXR_DATA_MASK 0x00000002 /**< Data Interrupt mask */ -#define XIICPS_IXR_COMP_MASK 0x00000001 /**< Transfer Complete - Interrupt mask */ -#define XIICPS_IXR_DEFAULT_MASK 0x000002FF /**< Default ISR Mask */ -#define XIICPS_IXR_ALL_INTR_MASK 0x000002FF /**< All ISR Mask */ -/* @} */ - - -/** @name IIC Transfer Size Register -* -* The register's meaning varies according to the operating mode as follows: -* - Master transmitter mode: number of data bytes still not transmitted minus -* one -* - Master receiver mode: number of data bytes that are still expected to be -* received -* - Slave transmitter mode: number of bytes remaining in the FIFO after the -* master terminates the transfer -* - Slave receiver mode: number of valid data bytes in the FIFO -* -* This register is cleared if CLR_FIFO bit in the control register is set. -* Read/Write -* @{ -*/ -#define XIICPS_TRANS_SIZE_MASK 0x0000003F /**< IIC Transfer Size Mask */ -#define XIICPS_FIFO_DEPTH 16 /**< Number of bytes in the FIFO */ -#define XIICPS_DATA_INTR_DEPTH 14 /**< Number of bytes at DATA intr */ -/* @} */ - - -/** @name IIC Slave Monitor Pause Register -* -* This register is associated with the slave monitor mode of the I2C interface. -* It is meaningful only when the module is in master mode and bit SLVMON in the -* control register is set. -* -* This register defines the pause interval between consecutive attempts to -* address the slave once a write to an I2C address register is done by the -* host. It represents the number of sclk cycles minus one between two attempts. -* -* The reset value of the register is 0, which results in the master repeatedly -* trying to access the slave immediately after unsuccessful attempt. -* Read/Write -* @{ -*/ -#define XIICPS_SLV_PAUSE_MASK 0x0000000F /**< Slave monitor pause mask */ -/* @} */ - - -/** @name IIC Time Out Register -* -* The value of time out register represents the time out interval in number of -* sclk cycles minus one. -* -* When the accessed slave holds the sclk line low for longer than the time out -* period, thus prohibiting the I2C interface in master mode to complete the -* current transfer, an interrupt is generated and TO interrupt flag is set. -* -* The reset value of the register is 0x1f. -* Read/Write -* @{ - */ -#define XIICPS_TIME_OUT_MASK 0x000000FF /**< IIC Time Out mask */ -#define XIICPS_TO_RESET_VALUE 0x0000001F /**< IIC Time Out reset value */ -/* @} */ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -#define XIicPs_In32 Xil_In32 -#define XIicPs_Out32 Xil_Out32 - -/****************************************************************************/ -/** -* Read an IIC register. -* -* @param BaseAddress contains the base address of the device. -* @param RegOffset contains the offset from the 1st register of the -* device to select the specific register. -* -* @return The value read from the register. -* -* @note C-Style signature: -* u32 XIicPs_ReadReg(u32 BaseAddress. int RegOffset) -* -******************************************************************************/ -#define XIicPs_ReadReg(BaseAddress, RegOffset) \ - XIicPs_In32((BaseAddress) + (RegOffset)) - -/***************************************************************************/ -/** -* Write an IIC register. -* -* @param BaseAddress contains the base address of the device. -* @param RegOffset contains the offset from the 1st register of the -* device to select the specific register. -* @param RegisterValue is the value to be written to the register. -* -* @return None. -* -* @note C-Style signature: -* void XIicPs_WriteReg(u32 BaseAddress, int RegOffset, u32 RegisterValue) -* -******************************************************************************/ -#define XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ - XIicPs_Out32((BaseAddress) + (RegOffset), (RegisterValue)) - -/***************************************************************************/ -/** -* Read the interrupt enable register. -* -* @param BaseAddress contains the base address of the device. -* -* @return Current bit mask that represents currently enabled interrupts. -* -* @note C-Style signature: -* u32 XIicPs_ReadIER(u32 BaseAddress) -* -******************************************************************************/ -#define XIicPs_ReadIER(BaseAddress) \ - XIicPs_ReadReg((BaseAddress), XIICPS_IER_OFFSET) - -/***************************************************************************/ -/** -* Write to the interrupt enable register. -* -* @param BaseAddress contains the base address of the device. -* -* @param IntrMask is the interrupts to be enabled. -* -* @return None. -* -* @note C-Style signature: -* void XIicPs_EnabledInterrupts(u32 BaseAddress, u32 IntrMask) -* -******************************************************************************/ -#define XIicPs_EnableInterrupts(BaseAddress, IntrMask) \ - XIicPs_WriteReg((BaseAddress), XIICPS_IER_OFFSET, (IntrMask)) - -/***************************************************************************/ -/** -* Disable all interrupts. -* -* @param BaseAddress contains the base address of the device. -* -* @return None. -* -* @note C-Style signature: -* void XIicPs_DisableAllInterrupts(u32 BaseAddress) -* -******************************************************************************/ -#define XIicPs_DisableAllInterrupts(BaseAddress) \ - XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \ - XIICPS_IXR_ALL_INTR_MASK) - -/***************************************************************************/ -/** -* Disable selected interrupts. -* -* @param BaseAddress contains the base address of the device. -* -* @param IntrMask is the interrupts to be disabled. -* -* @return None. -* -* @note C-Style signature: -* void XIicPs_DisableInterrupts(u32 BaseAddress, u32 IntrMask) -* -******************************************************************************/ -#define XIicPs_DisableInterrupts(BaseAddress, IntrMask) \ - XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \ - (IntrMask)) - -/************************** Variable Definitions *****************************/ - -/************************** Function Prototypes ******************************/ -/* - * Perform reset operation to the I2c interface - */ -void XIicPs_ResetHw(u32 BaseAddr); -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_assert.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_assert.h deleted file mode 100644 index 419492f94d45d6e03122ba361f986222901cbada..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_assert.h +++ /dev/null @@ -1,195 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_assert.h -* -* This file contains assert related functions. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.00a hbm 07/14/09 First release -* </pre> -* -******************************************************************************/ - -#ifndef XIL_ASSERT_H /* prevent circular inclusions */ -#define XIL_ASSERT_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - - -/***************************** Include Files *********************************/ - - -/************************** Constant Definitions *****************************/ - -#define XIL_ASSERT_NONE 0 -#define XIL_ASSERT_OCCURRED 1 - -extern unsigned int Xil_AssertStatus; -extern void Xil_Assert(const char *, int); - - -/** - * This data type defines a callback to be invoked when an - * assert occurs. The callback is invoked only when asserts are enabled - */ -typedef void (*Xil_AssertCallback) (const char *File, int Line); - -/***************** Macros (Inline Functions) Definitions *********************/ - -#ifndef NDEBUG - -/*****************************************************************************/ -/** -* This assert macro is to be used for functions that do not return anything -* (void). This in conjunction with the Xil_AssertWait boolean can be used to -* accomodate tests so that asserts which fail allow execution to continue. -* -* @param expression is the expression to evaluate. If it evaluates to -* false, the assert occurs. -* -* @return Returns void unless the Xil_AssertWait variable is true, in which -* case no return is made and an infinite loop is entered. -* -* @note None. -* -******************************************************************************/ -#define Xil_AssertVoid(Expression) \ -{ \ - if (Expression) { \ - Xil_AssertStatus = XIL_ASSERT_NONE; \ - } else { \ - Xil_Assert(__FILE__, __LINE__); \ - Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ - return; \ - } \ -} - -/*****************************************************************************/ -/** -* This assert macro is to be used for functions that do return a value. This in -* conjunction with the Xil_AssertWait boolean can be used to accomodate tests -* so that asserts which fail allow execution to continue. -* -* @param expression is the expression to evaluate. If it evaluates to false, -* the assert occurs. -* -* @return Returns 0 unless the Xil_AssertWait variable is true, in which -* case no return is made and an infinite loop is entered. -* -* @note None. -* -******************************************************************************/ -#define Xil_AssertNonvoid(Expression) \ -{ \ - if (Expression) { \ - Xil_AssertStatus = XIL_ASSERT_NONE; \ - } else { \ - Xil_Assert(__FILE__, __LINE__); \ - Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ - return 0; \ - } \ -} - -/*****************************************************************************/ -/** -* Always assert. This assert macro is to be used for functions that do not -* return anything (void). Use for instances where an assert should always -* occur. -* -* @return Returns void unless the Xil_AssertWait variable is true, in which -* case no return is made and an infinite loop is entered. -* -* @note None. -* -******************************************************************************/ -#define Xil_AssertVoidAlways() \ -{ \ - Xil_Assert(__FILE__, __LINE__); \ - Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ - return; \ -} - -/*****************************************************************************/ -/** -* Always assert. This assert macro is to be used for functions that do return -* a value. Use for instances where an assert should always occur. -* -* @return Returns void unless the Xil_AssertWait variable is true, in which -* case no return is made and an infinite loop is entered. -* -* @note None. -* -******************************************************************************/ -#define Xil_AssertNonvoidAlways() \ -{ \ - Xil_Assert(__FILE__, __LINE__); \ - Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ - return 0; \ -} - - -#else - -#define Xil_AssertVoid(Expression) -#define Xil_AssertVoidAlways() -#define Xil_AssertNonvoid(Expression) -#define Xil_AssertNonvoidAlways() - -#endif - -/************************** Function Prototypes ******************************/ - -void Xil_AssertSetCallback(Xil_AssertCallback Routine); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_cache.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_cache.h deleted file mode 100644 index e1e0adaacd90a7ad1ce8326ddfaa330b493a549d..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_cache.h +++ /dev/null @@ -1,84 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_cache.h -* -* Contains required functions for the ARM cache functionality -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a ecm 01/29/10 First release -* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance -* APIs. -* </pre> -* -******************************************************************************/ -#ifndef XIL_CACHE_H -#define XIL_CACHE_H - -#include "xil_types.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void Xil_DCacheEnable(void); -void Xil_DCacheDisable(void); -void Xil_DCacheInvalidate(void); -void Xil_DCacheInvalidateRange(unsigned int adr, unsigned len); -void Xil_DCacheFlush(void); -void Xil_DCacheFlushRange(unsigned int adr, unsigned len); - -void Xil_ICacheEnable(void); -void Xil_ICacheDisable(void); -void Xil_ICacheInvalidate(void); -void Xil_ICacheInvalidateRange(unsigned int adr, unsigned len); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_cache_l.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_cache_l.h deleted file mode 100644 index d0c3f40e6793ca07a354b32cc0cf9a2657b3428f..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_cache_l.h +++ /dev/null @@ -1,103 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_cache_l.h -* -* Contains L1 and L2 specific functions for the ARM cache functionality -* used by xcache.c. This functionality is being made available here for -* more sophisticated users. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a ecm 01/24/10 First release -* </pre> -* -******************************************************************************/ -#ifndef XIL_CACHE_MACH_H -#define XIL_CACHE_MACH_H - -#ifdef __cplusplus -extern "C" { -#endif - -/************************** Function Prototypes ******************************/ - -void Xil_DCacheInvalidateLine(unsigned int adr); -void Xil_DCacheFlushLine(unsigned int adr); -void Xil_DCacheStoreLine(unsigned int adr); -void Xil_ICacheInvalidateLine(unsigned int adr); - -void Xil_L1DCacheEnable(void); -void Xil_L1DCacheDisable(void); -void Xil_L1DCacheInvalidate(void); -void Xil_L1DCacheInvalidateLine(unsigned int adr); -void Xil_L1DCacheInvalidateRange(unsigned int adr, unsigned len); -void Xil_L1DCacheFlush(void); -void Xil_L1DCacheFlushLine(unsigned int adr); -void Xil_L1DCacheFlushRange(unsigned int adr, unsigned len); -void Xil_L1DCacheStoreLine(unsigned int adr); - -void Xil_L1ICacheEnable(void); -void Xil_L1ICacheDisable(void); -void Xil_L1ICacheInvalidate(void); -void Xil_L1ICacheInvalidateLine(unsigned int adr); -void Xil_L1ICacheInvalidateRange(unsigned int adr, unsigned len); - -void Xil_L2CacheEnable(void); -void Xil_L2CacheDisable(void); -void Xil_L2CacheInvalidate(void); -void Xil_L2CacheInvalidateLine(unsigned int adr); -void Xil_L2CacheInvalidateRange(unsigned int adr, unsigned len); -void Xil_L2CacheFlush(void); -void Xil_L2CacheFlushLine(unsigned int adr); -void Xil_L2CacheFlushRange(unsigned int adr, unsigned len); -void Xil_L2CacheStoreLine(unsigned int adr); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h deleted file mode 100644 index 3ad8965dfc8eba8a24f5f9f7cd1a03375eaaca0e..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h +++ /dev/null @@ -1,103 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_cache_vxworks.h -* -* Contains the cache related functions for VxWorks that is wrapped by -* xil_cache. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.00a hbm 12/11/09 Initial release -* -* </pre> -* -* @note -* -******************************************************************************/ - -#ifndef XIL_CACHE_VXWORKS_H -#define XIL_CACHE_VXWORKS_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "vxWorks.h" -#include "vxLib.h" -#include "sysLibExtra.h" -#include "cacheLib.h" - -#if (CPU_FAMILY==PPC) - -#define Xil_DCacheEnable() cacheEnable(DATA_CACHE) - -#define Xil_DCacheDisable() cacheDisable(DATA_CACHE) - -#define Xil_DCacheInvalidateRange(Addr, Len) \ - cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len)) - -#define Xil_DCacheFlushRange(Addr, Len) \ - cacheFlush(DATA_CACHE, (void *)(Addr), (Len)) - -#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE) - -#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE) - -#define Xil_ICacheInvalidateRange(Addr, Len) \ - cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len)) - - -#else -#error "Unknown processor / architecture. Must be PPC for VxWorks." -#endif - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_errata.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_errata.h deleted file mode 100644 index bb09eef3fe4c23dfe9206faf56690245dd104c11..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_errata.h +++ /dev/null @@ -1,117 +0,0 @@ -/******************************************************************************* -* -* (c) Copyright 2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -*******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_errata.h -* -* This header file contains Cortex A9 and PL310 Errata definitions. -* -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a srt 04/18/13 First release -* </pre> -* -******************************************************************************/ -#ifndef XIL_ERRATA_H -#define XIL_ERRATA_H - -#define ENABLE_ARM_ERRATA 1 - -#ifdef ENABLE_ARM_ERRATA -/* Cortex A9 ARM Errata */ - -/* - * Errata No: 742230 - * Description: DMB operation may be faulty - */ -#define CONFIG_ARM_ERRATA_742230 1 - -/* - * Errata No: 743622 - * Description: Faulty hazard checking in the Store Buffer may lead - * to data corruption. - */ -#define CONFIG_ARM_ERRATA_743622 1 - -/* - * Errata No: 775420 - * Description: A data cache maintenance operation which aborts, - * might lead to deadlock - */ -#define CONFIG_ARM_ERRATA_775420 1 - -/* - * Errata No: 794073 - * Description: Speculative instruction fetches with MMU disabled - * might not comply with architectural requirements - */ -#define CONFIG_ARM_ERRATA_794073 1 - - -/* PL310 L2 Cache Errata */ - -/* - * Errata No: 588369 - * Description: Clean & Invalidate maintenance operations do not - * invalidate clean lines - */ -#define CONFIG_PL310_ERRATA_588369 1 - -/* - * Errata No: 727915 - * Description: Background Clean and Invalidate by Way operation - * can cause data corruption - */ -#define CONFIG_PL310_ERRATA_727915 1 - -/* - * Errata No: 753970 - * Description: Cache sync operation may be faulty - */ -#define CONFIG_PL310_ERRATA_753970 1 - -#endif /* ENABLE_ARM_ERRATA */ - -#endif /* XIL_ERRATA_H */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_exception.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_exception.h deleted file mode 100644 index dfa50d7fafc5cf8c1a393dd550638b721981b904..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_exception.h +++ /dev/null @@ -1,241 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_exception.h -* -* This header file contains ARM Cortex A9 specific exception related APIs. -* For exception related functions that can be used across all Xilinx supported -* processors, please use xil_exception.h. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- -------- -------- ----------------------------------------------- -* 1.00a ecm/sdm 11/04/09 First release -* </pre> -* -******************************************************************************/ - -#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */ -#define XIL_EXCEPTION_H /* by using protection macros */ - -/***************************** Include Files ********************************/ - -#include "xil_types.h" -#include "xpseudo_asm.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/************************** Constant Definitions ****************************/ - -#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE -#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE -#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE) - -#define XIL_EXCEPTION_ID_FIRST 0 -#define XIL_EXCEPTION_ID_RESET 0 -#define XIL_EXCEPTION_ID_UNDEFINED_INT 1 -#define XIL_EXCEPTION_ID_SWI_INT 2 -#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3 -#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4 -#define XIL_EXCEPTION_ID_IRQ_INT 5 -#define XIL_EXCEPTION_ID_FIQ_INT 6 -#define XIL_EXCEPTION_ID_LAST 6 - -/* - * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors. - */ -#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT - -/**************************** Type Definitions ******************************/ - -/** - * This typedef is the exception handler function. - */ -typedef void (*Xil_ExceptionHandler)(void *data); -typedef void (*Xil_InterruptHandler)(void *data); - -/***************** Macros (Inline Functions) Definitions ********************/ - -/****************************************************************************/ -/** -* Enable Exceptions. -* -* @param Mask for exceptions to be enabled. -* -* @return None. -* -* @note If bit is 0, exception is enabled. -* C-Style signature: void Xil_ExceptionEnableMask(Mask); -* -******************************************************************************/ -#ifdef __GNUC__ -#define Xil_ExceptionEnableMask(Mask) \ - mtcpsr(mfcpsr() & ~ (Mask & XIL_EXCEPTION_ALL)) -#elif defined (__ICCARM__) -#define Xil_ExceptionEnableMask(Mask) \ - { register unsigned int rval; \ - mfcpsr(rval); \ - mtcpsr(rval & ~ (Mask & XIL_EXCEPTION_ALL)) ;} -#else -#define Xil_ExceptionEnableMask(Mask) \ - { register unsigned int Reg __asm("cpsr"); \ - mtcpsr(Reg & ~ (Mask & XIL_EXCEPTION_ALL)) } -#endif - -/****************************************************************************/ -/** -* Enable the IRQ exception. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -#define Xil_ExceptionEnable() \ - Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ) - -/****************************************************************************/ -/** -* Disable Exceptions. -* -* @param Mask for exceptions to be enabled. -* -* @return None. -* -* @note If bit is 1, exception is disabled. -* C-Style signature: Xil_ExceptionDisableMask(Mask); -* -******************************************************************************/ -#ifdef __GNUC__ -#define Xil_ExceptionDisableMask(Mask) \ - mtcpsr(mfcpsr() | (Mask & XIL_EXCEPTION_ALL)) -#elif defined (__ICCARM__) -#define Xil_ExceptionDisableMask(Mask) \ - { register unsigned int rval; \ - mfcpsr(rval); \ - mtcpsr(rval | (Mask & XIL_EXCEPTION_ALL)) ;} -#else -#define Xil_ExceptionDisableMask(Mask) \ - { register unsigned int Reg __asm("cpsr"); \ - mtcpsr(Reg | (Mask & XIL_EXCEPTION_ALL)) } -#endif - -/****************************************************************************/ -/** -* Disable the IRQ exception. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -#define Xil_ExceptionDisable() \ - Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ) - -/****************************************************************************/ -/** -* Enable nested interrupts by clearing the I and F bits it CPSR -* -* @return None. -* -* @note This macro is supposed to be used from interrupt handlers. In the -* interrupt handler the interrupts are disabled by default (I and F -* are 1). To allow nesting of interrupts, this macro should be -* used. It clears the I and F bits by changing the ARM mode to -* system mode. Once these bits are cleared and provided the -* preemption of interrupt conditions are met in the GIC, nesting of -* interrupts will start happening. -* Caution: This macro must be used with caution. Before calling this -* macro, the user must ensure that the source of the current IRQ -* is appropriately cleared. Otherwise, as soon as we clear the I and -* F bits, there can be an infinite loop of interrupts with an -* eventual crash (all the stack space getting consumed). -******************************************************************************/ -#define Xil_EnableNestedInterrupts() \ - __asm__ __volatile__ ("mrs lr, spsr"); \ - __asm__ __volatile__ ("stmfd sp!, {lr}"); \ - __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \ - __asm__ __volatile__ ("stmfd sp!, {lr}"); - -/****************************************************************************/ -/** -* Disable the nested interrupts by setting the I and F bits. -* -* @return None. -* -* @note This macro is meant to be called in the interrupt service routines. -* This macro cannot be used independently. It can only be used when -* nesting of interrupts have been enabled by using the macro -* Xil_EnableNestedInterrupts(). In a typical flow, the user first -* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate -* point. The user then must call this macro before exiting the interrupt -* service routine. This macro puts the ARM back in IRQ/FIQ mode and -* hence sets back the I and F bits. -******************************************************************************/ -#define Xil_DisableNestedInterrupts() \ - __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ - __asm__ __volatile__ ("msr cpsr_c, #0x92"); \ - __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ - __asm__ __volatile__ ("msr spsr_cxsf, lr"); - -/************************** Variable Definitions ****************************/ - -/************************** Function Prototypes *****************************/ - -extern void Xil_ExceptionRegisterHandler(u32 id, - Xil_ExceptionHandler handler, - void *data); - -extern void Xil_ExceptionRemoveHandler(u32 id); - -extern void Xil_ExceptionInit(void); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* XIL_EXCEPTION_H */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_hal.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_hal.h deleted file mode 100644 index b58c7eb8af67a90dc3e8a81648537aa9b12014df..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_hal.h +++ /dev/null @@ -1,71 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_hal.h -* -* Contains all the HAL header files. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.00a hbm 07/28/09 Initial release -* -* </pre> -* -* @note -* -******************************************************************************/ - -#ifndef XIL_HAL_H -#define XIL_HAL_H - -#include "xil_cache.h" -#include "xil_io.h" -#include "xil_assert.h" -#include "xil_exception.h" -#include "xil_types.h" - -#endif - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_io.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_io.h deleted file mode 100644 index 06e83bfa8f7988b01fbd9b3ed787e383a16a0dc3..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_io.h +++ /dev/null @@ -1,254 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_io.h -* -* This file contains the interface for the general IO component, which -* encapsulates the Input/Output functions for processors that do not -* require any special I/O handling. -* -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- -------- -------- ----------------------------------------------- -* 1.00a ecm/sdm 10/24/09 First release -* 1.00a sdm 07/21/10 Added Xil_Htonl/s, Xil_Ntohl/s -* 3.07a asa 08/31/12 Added xil_printf.h include -* 3.08a sgd 11/05/12 Reverted SYNC macros definitions -* </pre> -******************************************************************************/ - -#ifndef XIL_IO_H /* prevent circular inclusions */ -#define XIL_IO_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xpseudo_asm.h" -#include "xil_printf.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -#if defined __GNUC__ -# define SYNCHRONIZE_IO dmb() -# define INST_SYNC isb() -# define DATA_SYNC dsb() -#else -# define SYNCHRONIZE_IO -# define INST_SYNC -# define DATA_SYNC -#endif /* __GNUC__ */ - -/*****************************************************************************/ -/** -* -* Perform an big-endian input operation for a 16-bit memory location -* by reading from the specified address and returning the Value read from -* that address. -* -* @param Addr contains the address to perform the input operation at. -* -* @return The Value read from the specified input address with the -* proper endianness. The return Value has the same endianness -* as that of the processor, i.e. if the processor is -* little-engian, the return Value is the byte-swapped Value read -* from the address. -* -* @note None. -* -******************************************************************************/ -#define Xil_In16LE(Addr) Xil_In16(Addr) - -/*****************************************************************************/ -/** -* -* Perform a big-endian input operation for a 32-bit memory location -* by reading from the specified address and returning the Value read from -* that address. -* -* @param Addr contains the address to perform the input operation at. -* -* @return The Value read from the specified input address with the -* proper endianness. The return Value has the same endianness -* as that of the processor, i.e. if the processor is -* little-engian, the return Value is the byte-swapped Value read -* from the address. -* -* -* @note None. -* -******************************************************************************/ -#define Xil_In32LE(Addr) Xil_In32(Addr) - -/*****************************************************************************/ -/** -* -* Perform a big-endian output operation for a 16-bit memory location -* by writing the specified Value to the specified address. -* -* @param Addr contains the address to perform the output operation at. -* @param Value contains the Value to be output at the specified address. -* The Value has the same endianness as that of the processor. -* If the processor is little-endian, the byte-swapped Value is -* written to the address. -* -* -* @return None -* -* @note None. -* -******************************************************************************/ -#define Xil_Out16LE(Addr, Value) Xil_Out16(Addr, Value) - -/*****************************************************************************/ -/** -* -* Perform a big-endian output operation for a 32-bit memory location -* by writing the specified Value to the specified address. -* -* @param Addr contains the address to perform the output operation at. -* @param Value contains the Value to be output at the specified address. -* The Value has the same endianness as that of the processor. -* If the processor is little-endian, the byte-swapped Value is -* written to the address. -* -* @return None -* -* @note None. -* -******************************************************************************/ -#define Xil_Out32LE(Addr, Value) Xil_Out32(Addr, Value) - -/*****************************************************************************/ -/** -* -* Convert a 32-bit number from host byte order to network byte order. -* -* @param Data the 32-bit number to be converted. -* -* @return The converted 32-bit number in network byte order. -* -* @note None. -* -******************************************************************************/ -#define Xil_Htonl(Data) Xil_EndianSwap32(Data) - -/*****************************************************************************/ -/** -* -* Convert a 16-bit number from host byte order to network byte order. -* -* @param Data the 16-bit number to be converted. -* -* @return The converted 16-bit number in network byte order. -* -* @note None. -* -******************************************************************************/ -#define Xil_Htons(Data) Xil_EndianSwap16(Data) - -/*****************************************************************************/ -/** -* -* Convert a 32-bit number from network byte order to host byte order. -* -* @param Data the 32-bit number to be converted. -* -* @return The converted 32-bit number in host byte order. -* -* @note None. -* -******************************************************************************/ -#define Xil_Ntohl(Data) Xil_EndianSwap32(Data) - -/*****************************************************************************/ -/** -* -* Convert a 16-bit number from network byte order to host byte order. -* -* @param Data the 16-bit number to be converted. -* -* @return The converted 16-bit number in host byte order. -* -* @note None. -* -******************************************************************************/ -#define Xil_Ntohs(Data) Xil_EndianSwap16(Data) - -/************************** Function Prototypes ******************************/ - -/* The following functions allow the software to be transportable across - * processors which may use memory mapped I/O or I/O which is mapped into a - * seperate address space. - */ -u8 Xil_In8(u32 Addr); -u16 Xil_In16(u32 Addr); -u32 Xil_In32(u32 Addr); - -void Xil_Out8(u32 Addr, u8 Value); -void Xil_Out16(u32 Addr, u16 Value); -void Xil_Out32(u32 Addr, u32 Value); - -u16 Xil_In16BE(u32 Addr); -u32 Xil_In32BE(u32 Addr); -void Xil_Out16BE(u32 Addr, u16 Value); -void Xil_Out32BE(u32 Addr, u32 Value); - -u16 Xil_EndianSwap16(u16 Data); -u32 Xil_EndianSwap32(u32 Data); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_macroback.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_macroback.h deleted file mode 100644 index c614daaf5ec1ec506ee5fa8f6aab2b2d95f2bc97..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_macroback.h +++ /dev/null @@ -1,1069 +0,0 @@ -/*********************************************************************/ -/** - * (c) Copyright 2010 Xilinx, Inc. All rights reserved. - * - * This file contains confidential and proprietary information - * of Xilinx, Inc. and is protected under U.S. and - * international copyright and other intellectual property - * laws. - * - * DISCLAIMER - * This disclaimer is not a license and does not grant any - * rights to the materials distributed herewith. Except as - * otherwise provided in a valid license issued to you by - * Xilinx, and to the maximum extent permitted by applicable - * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND - * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES - * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING - * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- - * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and - * (2) Xilinx shall not be liable (whether in contract or tort, - * including negligence, or under any other theory of - * liability) for any loss or damage of any kind or nature - * related to, arising under or in connection with these - * materials, including for any direct, or any indirect, - * special, incidental, or consequential loss or damage - * (including loss of data, profits, goodwill, or any type of - * loss or damage suffered as a result of any action brought - * by a third party) even if such damage or loss was - * reasonably foreseeable or Xilinx had been advised of the - * possibility of the same. - * - * CRITICAL APPLICATIONS - * Xilinx products are not designed or intended to be fail- - * safe, or for use in any application requiring fail-safe - * performance, such as life-support or safety devices or - * systems, Class III medical devices, nuclear facilities, - * applications related to the deployment of airbags, or any - * other applications that could lead to death, personal - * injury, or severe property or environmental damage - * (individually and collectively, "Critical - * Applications"). Customer assumes the sole risk and - * liability of any use of Xilinx products in Critical - * Applications, subject only to applicable laws and - * regulations governing limitations on product liability. - * - * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS - * PART OF THIS FILE AT ALL TIMES. - *********************************************************************/ - -/*********************************************************************/ -/** - * @file xil_macroback.h - * - * This header file is meant to bring back the removed _m macros. - * This header file must be included last. - * The following macros are not defined here due to the driver change: - * XGpio_mSetDataDirection - * XGpio_mGetDataReg - * XGpio_mSetDataReg - * XIIC_RESET - * XIIC_CLEAR_STATS - * XSpi_mReset - * XSysAce_mSetCfgAddr - * XSysAce_mIsCfgDone - * XTft_mSetPixel - * XTft_mGetPixel - * XWdtTb_mEnableWdt - * XWdtTb_mDisbleWdt - * XWdtTb_mRestartWdt - * XWdtTb_mGetTimebaseReg - * XWdtTb_mHasReset - * - * Please refer the corresonding driver document for replacement. - * - *********************************************************************/ - -#ifndef XIL_MACROBACK_H -#define XIL_MACROBACK_H - -/*********************************************************************/ -/** - * Macros for Driver XCan - * - *********************************************************************/ -#ifndef XCan_mReadReg -#define XCan_mReadReg XCan_ReadReg -#endif - -#ifndef XCan_mWriteReg -#define XCan_mWriteReg XCan_WriteReg -#endif - -#ifndef XCan_mIsTxDone -#define XCan_mIsTxDone XCan_IsTxDone -#endif - -#ifndef XCan_mIsTxFifoFull -#define XCan_mIsTxFifoFull XCan_IsTxFifoFull -#endif - -#ifndef XCan_mIsHighPriorityBufFull -#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull -#endif - -#ifndef XCan_mIsRxEmpty -#define XCan_mIsRxEmpty XCan_IsRxEmpty -#endif - -#ifndef XCan_mIsAcceptFilterBusy -#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy -#endif - -#ifndef XCan_mCreateIdValue -#define XCan_mCreateIdValue XCan_CreateIdValue -#endif - -#ifndef XCan_mCreateDlcValue -#define XCan_mCreateDlcValue XCan_CreateDlcValue -#endif - -/*********************************************************************/ -/** - * Macros for Driver XDmaCentral - * - *********************************************************************/ -#ifndef XDmaCentral_mWriteReg -#define XDmaCentral_mWriteReg XDmaCentral_WriteReg -#endif - -#ifndef XDmaCentral_mReadReg -#define XDmaCentral_mReadReg XDmaCentral_ReadReg -#endif - -/*********************************************************************/ -/** - * Macros for Driver XDsAdc - * - *********************************************************************/ -#ifndef XDsAdc_mWriteReg -#define XDsAdc_mWriteReg XDsAdc_WriteReg -#endif - -#ifndef XDsAdc_mReadReg -#define XDsAdc_mReadReg XDsAdc_ReadReg -#endif - -#ifndef XDsAdc_mIsEmpty -#define XDsAdc_mIsEmpty XDsAdc_IsEmpty -#endif - -#ifndef XDsAdc_mSetFstmReg -#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg -#endif - -#ifndef XDsAdc_mGetFstmReg -#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg -#endif - -#ifndef XDsAdc_mEnableConversion -#define XDsAdc_mEnableConversion XDsAdc_EnableConversion -#endif - -#ifndef XDsAdc_mDisableConversion -#define XDsAdc_mDisableConversion XDsAdc_DisableConversion -#endif - -#ifndef XDsAdc_mGetFifoOccyReg -#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg -#endif - -/*********************************************************************/ -/** - * Macros for Driver XDsDac - * - *********************************************************************/ -#ifndef XDsDac_mWriteReg -#define XDsDac_mWriteReg XDsDac_WriteReg -#endif - -#ifndef XDsDac_mReadReg -#define XDsDac_mReadReg XDsDac_ReadReg -#endif - -#ifndef XDsDac_mIsEmpty -#define XDsDac_mIsEmpty XDsDac_IsEmpty -#endif - -#ifndef XDsDac_mFifoIsFull -#define XDsDac_mFifoIsFull XDsDac_FifoIsFull -#endif - -#ifndef XDsDac_mGetVacancy -#define XDsDac_mGetVacancy XDsDac_GetVacancy -#endif - -/*********************************************************************/ -/** - * Macros for Driver XEmacLite - * - *********************************************************************/ -#ifndef XEmacLite_mReadReg -#define XEmacLite_mReadReg XEmacLite_ReadReg -#endif - -#ifndef XEmacLite_mWriteReg -#define XEmacLite_mWriteReg XEmacLite_WriteReg -#endif - -#ifndef XEmacLite_mGetTxStatus -#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus -#endif - -#ifndef XEmacLite_mSetTxStatus -#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus -#endif - -#ifndef XEmacLite_mGetRxStatus -#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus -#endif - -#ifndef XEmacLite_mSetRxStatus -#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus -#endif - -#ifndef XEmacLite_mIsTxDone -#define XEmacLite_mIsTxDone XEmacLite_IsTxDone -#endif - -#ifndef XEmacLite_mIsRxEmpty -#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty -#endif - -#ifndef XEmacLite_mNextTransmitAddr -#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr -#endif - -#ifndef XEmacLite_mNextReceiveAddr -#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr -#endif - -#ifndef XEmacLite_mIsMdioConfigured -#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured -#endif - -#ifndef XEmacLite_mIsLoopbackConfigured -#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured -#endif - -#ifndef XEmacLite_mGetReceiveDataLength -#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength -#endif - -#ifndef XEmacLite_mGetTxActive -#define XEmacLite_mGetTxActive XEmacLite_GetTxActive -#endif - -#ifndef XEmacLite_mSetTxActive -#define XEmacLite_mSetTxActive XEmacLite_SetTxActive -#endif - -/*********************************************************************/ -/** - * Macros for Driver XGpio - * - *********************************************************************/ -#ifndef XGpio_mWriteReg -#define XGpio_mWriteReg XGpio_WriteReg -#endif - -#ifndef XGpio_mReadReg -#define XGpio_mReadReg XGpio_ReadReg -#endif - -/*********************************************************************/ -/** - * Macros for Driver XHwIcap - * - *********************************************************************/ -#ifndef XHwIcap_mFifoWrite -#define XHwIcap_mFifoWrite XHwIcap_FifoWrite -#endif - -#ifndef XHwIcap_mFifoRead -#define XHwIcap_mFifoRead XHwIcap_FifoRead -#endif - -#ifndef XHwIcap_mSetSizeReg -#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg -#endif - -#ifndef XHwIcap_mGetControlReg -#define XHwIcap_mGetControlReg XHwIcap_GetControlReg -#endif - -#ifndef XHwIcap_mStartConfig -#define XHwIcap_mStartConfig XHwIcap_StartConfig -#endif - -#ifndef XHwIcap_mStartReadBack -#define XHwIcap_mStartReadBack XHwIcap_StartReadBack -#endif - -#ifndef XHwIcap_mGetStatusReg -#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg -#endif - -#ifndef XHwIcap_mIsTransferDone -#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone -#endif - -#ifndef XHwIcap_mIsDeviceBusy -#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy -#endif - -#ifndef XHwIcap_mIntrGlobalEnable -#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable -#endif - -#ifndef XHwIcap_mIntrGlobalDisable -#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable -#endif - -#ifndef XHwIcap_mIntrGetStatus -#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus -#endif - -#ifndef XHwIcap_mIntrDisable -#define XHwIcap_mIntrDisable XHwIcap_IntrDisable -#endif - -#ifndef XHwIcap_mIntrEnable -#define XHwIcap_mIntrEnable XHwIcap_IntrEnable -#endif - -#ifndef XHwIcap_mIntrGetEnabled -#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled -#endif - -#ifndef XHwIcap_mIntrClear -#define XHwIcap_mIntrClear XHwIcap_IntrClear -#endif - -#ifndef XHwIcap_mGetWrFifoVacancy -#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy -#endif - -#ifndef XHwIcap_mGetRdFifoOccupancy -#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy -#endif - -#ifndef XHwIcap_mSliceX2Col -#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col -#endif - -#ifndef XHwIcap_mSliceY2Row -#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row -#endif - -#ifndef XHwIcap_mSliceXY2Slice -#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice -#endif - -#ifndef XHwIcap_mReadReg -#define XHwIcap_mReadReg XHwIcap_ReadReg -#endif - -#ifndef XHwIcap_mWriteReg -#define XHwIcap_mWriteReg XHwIcap_WriteReg -#endif - -/*********************************************************************/ -/** - * Macros for Driver XIic - * - *********************************************************************/ -#ifndef XIic_mReadReg -#define XIic_mReadReg XIic_ReadReg -#endif - -#ifndef XIic_mWriteReg -#define XIic_mWriteReg XIic_WriteReg -#endif - -#ifndef XIic_mEnterCriticalRegion -#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable -#endif - -#ifndef XIic_mExitCriticalRegion -#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable -#endif - -#ifndef XIIC_GINTR_DISABLE -#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable -#endif - -#ifndef XIIC_GINTR_ENABLE -#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable -#endif - -#ifndef XIIC_IS_GINTR_ENABLED -#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled -#endif - -#ifndef XIIC_WRITE_IISR -#define XIIC_WRITE_IISR XIic_WriteIisr -#endif - -#ifndef XIIC_READ_IISR -#define XIIC_READ_IISR XIic_ReadIisr -#endif - -#ifndef XIIC_WRITE_IIER -#define XIIC_WRITE_IIER XIic_WriteIier -#endif - -#ifndef XIic_mClearIisr -#define XIic_mClearIisr XIic_ClearIisr -#endif - -#ifndef XIic_mSend7BitAddress -#define XIic_mSend7BitAddress XIic_Send7BitAddress -#endif - -#ifndef XIic_mDynSend7BitAddress -#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress -#endif - -#ifndef XIic_mDynSendStartStopAddress -#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress -#endif - -#ifndef XIic_mDynSendStop -#define XIic_mDynSendStop XIic_DynSendStop -#endif - -#ifndef XIic_mSend10BitAddrByte1 -#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1 -#endif - -#ifndef XIic_mSend10BitAddrByte2 -#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2 -#endif - -#ifndef XIic_mSend7BitAddr -#define XIic_mSend7BitAddr XIic_Send7BitAddr -#endif - -#ifndef XIic_mDisableIntr -#define XIic_mDisableIntr XIic_DisableIntr -#endif - -#ifndef XIic_mEnableIntr -#define XIic_mEnableIntr XIic_EnableIntr -#endif - -#ifndef XIic_mClearIntr -#define XIic_mClearIntr XIic_ClearIntr -#endif - -#ifndef XIic_mClearEnableIntr -#define XIic_mClearEnableIntr XIic_ClearEnableIntr -#endif - -#ifndef XIic_mFlushRxFifo -#define XIic_mFlushRxFifo XIic_FlushRxFifo -#endif - -#ifndef XIic_mFlushTxFifo -#define XIic_mFlushTxFifo XIic_FlushTxFifo -#endif - -#ifndef XIic_mReadRecvByte -#define XIic_mReadRecvByte XIic_ReadRecvByte -#endif - -#ifndef XIic_mWriteSendByte -#define XIic_mWriteSendByte XIic_WriteSendByte -#endif - -#ifndef XIic_mSetControlRegister -#define XIic_mSetControlRegister XIic_SetControlRegister -#endif - -/*********************************************************************/ -/** - * Macros for Driver XIntc - * - *********************************************************************/ -#ifndef XIntc_mMasterEnable -#define XIntc_mMasterEnable XIntc_MasterEnable -#endif - -#ifndef XIntc_mMasterDisable -#define XIntc_mMasterDisable XIntc_MasterDisable -#endif - -#ifndef XIntc_mEnableIntr -#define XIntc_mEnableIntr XIntc_EnableIntr -#endif - -#ifndef XIntc_mDisableIntr -#define XIntc_mDisableIntr XIntc_DisableIntr -#endif - -#ifndef XIntc_mAckIntr -#define XIntc_mAckIntr XIntc_AckIntr -#endif - -#ifndef XIntc_mGetIntrStatus -#define XIntc_mGetIntrStatus XIntc_GetIntrStatus -#endif - -/*********************************************************************/ -/** - * Macros for Driver XLlDma - * - *********************************************************************/ -#ifndef XLlDma_mBdRead -#define XLlDma_mBdRead XLlDma_BdRead -#endif - -#ifndef XLlDma_mBdWrite -#define XLlDma_mBdWrite XLlDma_BdWrite -#endif - -#ifndef XLlDma_mWriteReg -#define XLlDma_mWriteReg XLlDma_WriteReg -#endif - -#ifndef XLlDma_mReadReg -#define XLlDma_mReadReg XLlDma_ReadReg -#endif - -#ifndef XLlDma_mBdClear -#define XLlDma_mBdClear XLlDma_BdClear -#endif - -#ifndef XLlDma_mBdSetStsCtrl -#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl -#endif - -#ifndef XLlDma_mBdGetStsCtrl -#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl -#endif - -#ifndef XLlDma_mBdSetLength -#define XLlDma_mBdSetLength XLlDma_BdSetLength -#endif - -#ifndef XLlDma_mBdGetLength -#define XLlDma_mBdGetLength XLlDma_BdGetLength -#endif - -#ifndef XLlDma_mBdSetId -#define XLlDma_mBdSetId XLlDma_BdSetId -#endif - -#ifndef XLlDma_mBdGetId -#define XLlDma_mBdGetId XLlDma_BdGetId -#endif - -#ifndef XLlDma_mBdSetBufAddr -#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr -#endif - -#ifndef XLlDma_mBdGetBufAddr -#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr -#endif - -#ifndef XLlDma_mBdGetLength -#define XLlDma_mBdGetLength XLlDma_BdGetLength -#endif - -#ifndef XLlDma_mGetTxRing -#define XLlDma_mGetTxRing XLlDma_GetTxRing -#endif - -#ifndef XLlDma_mGetRxRing -#define XLlDma_mGetRxRing XLlDma_GetRxRing -#endif - -#ifndef XLlDma_mGetCr -#define XLlDma_mGetCr XLlDma_GetCr -#endif - -#ifndef XLlDma_mSetCr -#define XLlDma_mSetCr XLlDma_SetCr -#endif - -#ifndef XLlDma_mBdRingCntCalc -#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc -#endif - -#ifndef XLlDma_mBdRingMemCalc -#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc -#endif - -#ifndef XLlDma_mBdRingGetCnt -#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt -#endif - -#ifndef XLlDma_mBdRingGetFreeCnt -#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt -#endif - -#ifndef XLlDma_mBdRingSnapShotCurrBd -#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd -#endif - -#ifndef XLlDma_mBdRingNext -#define XLlDma_mBdRingNext XLlDma_BdRingNext -#endif - -#ifndef XLlDma_mBdRingPrev -#define XLlDma_mBdRingPrev XLlDma_BdRingPrev -#endif - -#ifndef XLlDma_mBdRingGetSr -#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr -#endif - -#ifndef XLlDma_mBdRingSetSr -#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr -#endif - -#ifndef XLlDma_mBdRingGetCr -#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr -#endif - -#ifndef XLlDma_mBdRingSetCr -#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr -#endif - -#ifndef XLlDma_mBdRingBusy -#define XLlDma_mBdRingBusy XLlDma_BdRingBusy -#endif - -#ifndef XLlDma_mBdRingIntEnable -#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable -#endif - -#ifndef XLlDma_mBdRingIntDisable -#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable -#endif - -#ifndef XLlDma_mBdRingIntGetEnabled -#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled -#endif - -#ifndef XLlDma_mBdRingGetIrq -#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq -#endif - -#ifndef XLlDma_mBdRingAckIrq -#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq -#endif - -/*********************************************************************/ -/** - * Macros for Driver XMbox - * - *********************************************************************/ -#ifndef XMbox_mWriteReg -#define XMbox_mWriteReg XMbox_WriteReg -#endif - -#ifndef XMbox_mReadReg -#define XMbox_mReadReg XMbox_ReadReg -#endif - -#ifndef XMbox_mWriteMBox -#define XMbox_mWriteMBox XMbox_WriteMBox -#endif - -#ifndef XMbox_mReadMBox -#define XMbox_mReadMBox XMbox_ReadMBox -#endif - -#ifndef XMbox_mFSLReadMBox -#define XMbox_mFSLReadMBox XMbox_FSLReadMBox -#endif - -#ifndef XMbox_mFSLWriteMBox -#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox -#endif - -#ifndef XMbox_mFSLIsEmpty -#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty -#endif - -#ifndef XMbox_mFSLIsFull -#define XMbox_mFSLIsFull XMbox_FSLIsFull -#endif - -#ifndef XMbox_mIsEmpty -#define XMbox_mIsEmpty XMbox_IsEmptyHw -#endif - -#ifndef XMbox_mIsFull -#define XMbox_mIsFull XMbox_IsFullHw -#endif - -/*********************************************************************/ -/** - * Macros for Driver XMpmc - * - *********************************************************************/ -#ifndef XMpmc_mReadReg -#define XMpmc_mReadReg XMpmc_ReadReg -#endif - -#ifndef XMpmc_mWriteReg -#define XMpmc_mWriteReg XMpmc_WriteReg -#endif - -/*********************************************************************/ -/** - * Macros for Driver XMutex - * - *********************************************************************/ -#ifndef XMutex_mWriteReg -#define XMutex_mWriteReg XMutex_WriteReg -#endif - -#ifndef XMutex_mReadReg -#define XMutex_mReadReg XMutex_ReadReg -#endif - -/*********************************************************************/ -/** - * Macros for Driver XPcie - * - *********************************************************************/ -#ifndef XPcie_mReadReg -#define XPcie_mReadReg XPcie_ReadReg -#endif - -#ifndef XPcie_mWriteReg -#define XPcie_mWriteReg XPcie_WriteReg -#endif - -/*********************************************************************/ -/** - * Macros for Driver XSpi - * - *********************************************************************/ -#ifndef XSpi_mIntrGlobalEnable -#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable -#endif - -#ifndef XSpi_mIntrGlobalDisable -#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable -#endif - -#ifndef XSpi_mIsIntrGlobalEnabled -#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled -#endif - -#ifndef XSpi_mIntrGetStatus -#define XSpi_mIntrGetStatus XSpi_IntrGetStatus -#endif - -#ifndef XSpi_mIntrClear -#define XSpi_mIntrClear XSpi_IntrClear -#endif - -#ifndef XSpi_mIntrEnable -#define XSpi_mIntrEnable XSpi_IntrEnable -#endif - -#ifndef XSpi_mIntrDisable -#define XSpi_mIntrDisable XSpi_IntrDisable -#endif - -#ifndef XSpi_mIntrGetEnabled -#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled -#endif - -#ifndef XSpi_mSetControlReg -#define XSpi_mSetControlReg XSpi_SetControlReg -#endif - -#ifndef XSpi_mGetControlReg -#define XSpi_mGetControlReg XSpi_GetControlReg -#endif - -#ifndef XSpi_mGetStatusReg -#define XSpi_mGetStatusReg XSpi_GetStatusReg -#endif - -#ifndef XSpi_mSetSlaveSelectReg -#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg -#endif - -#ifndef XSpi_mGetSlaveSelectReg -#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg -#endif - -#ifndef XSpi_mEnable -#define XSpi_mEnable XSpi_Enable -#endif - -#ifndef XSpi_mDisable -#define XSpi_mDisable XSpi_Disable -#endif - -/*********************************************************************/ -/** - * Macros for Driver XSysAce - * - *********************************************************************/ -#ifndef XSysAce_mGetControlReg -#define XSysAce_mGetControlReg XSysAce_GetControlReg -#endif - -#ifndef XSysAce_mSetControlReg -#define XSysAce_mSetControlReg XSysAce_SetControlReg -#endif - -#ifndef XSysAce_mOrControlReg -#define XSysAce_mOrControlReg XSysAce_OrControlReg -#endif - -#ifndef XSysAce_mAndControlReg -#define XSysAce_mAndControlReg XSysAce_AndControlReg -#endif - -#ifndef XSysAce_mGetErrorReg -#define XSysAce_mGetErrorReg XSysAce_GetErrorReg -#endif - -#ifndef XSysAce_mGetStatusReg -#define XSysAce_mGetStatusReg XSysAce_GetStatusReg -#endif - -#ifndef XSysAce_mWaitForLock -#define XSysAce_mWaitForLock XSysAce_WaitForLock -#endif - -#ifndef XSysAce_mEnableIntr -#define XSysAce_mEnableIntr XSysAce_EnableIntr -#endif - -#ifndef XSysAce_mDisableIntr -#define XSysAce_mDisableIntr XSysAce_DisableIntr -#endif - -#ifndef XSysAce_mIsReadyForCmd -#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd -#endif - -#ifndef XSysAce_mIsMpuLocked -#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked -#endif - -#ifndef XSysAce_mIsIntrEnabled -#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled -#endif - -/*********************************************************************/ -/** - * Macros for Driver XSysMon - * - *********************************************************************/ -#ifndef XSysMon_mIsEventSamplingModeSet -#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet -#endif - -#ifndef XSysMon_mIsDrpBusy -#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy -#endif - -#ifndef XSysMon_mIsDrpLocked -#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked -#endif - -#ifndef XSysMon_mRawToTemperature -#define XSysMon_mRawToTemperature XSysMon_RawToTemperature -#endif - -#ifndef XSysMon_mRawToVoltage -#define XSysMon_mRawToVoltage XSysMon_RawToVoltage -#endif - -#ifndef XSysMon_mTemperatureToRaw -#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw -#endif - -#ifndef XSysMon_mVoltageToRaw -#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw -#endif - -#ifndef XSysMon_mReadReg -#define XSysMon_mReadReg XSysMon_ReadReg -#endif - -#ifndef XSysMon_mWriteReg -#define XSysMon_mWriteReg XSysMon_WriteReg -#endif - -/*********************************************************************/ -/** - * Macros for Driver XTmrCtr - * - *********************************************************************/ -#ifndef XTimerCtr_mReadReg -#define XTimerCtr_mReadReg XTimerCtr_ReadReg -#endif - -#ifndef XTmrCtr_mWriteReg -#define XTmrCtr_mWriteReg XTmrCtr_WriteReg -#endif - -#ifndef XTmrCtr_mSetControlStatusReg -#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg -#endif - -#ifndef XTmrCtr_mGetControlStatusReg -#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg -#endif - -#ifndef XTmrCtr_mGetTimerCounterReg -#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg -#endif - -#ifndef XTmrCtr_mSetLoadReg -#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg -#endif - -#ifndef XTmrCtr_mGetLoadReg -#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg -#endif - -#ifndef XTmrCtr_mEnable -#define XTmrCtr_mEnable XTmrCtr_Enable -#endif - -#ifndef XTmrCtr_mDisable -#define XTmrCtr_mDisable XTmrCtr_Disable -#endif - -#ifndef XTmrCtr_mEnableIntr -#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr -#endif - -#ifndef XTmrCtr_mDisableIntr -#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr -#endif - -#ifndef XTmrCtr_mLoadTimerCounterReg -#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg -#endif - -#ifndef XTmrCtr_mHasEventOccurred -#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred -#endif - -/*********************************************************************/ -/** - * Macros for Driver XUartLite - * - *********************************************************************/ -#ifndef XUartLite_mUpdateStats -#define XUartLite_mUpdateStats XUartLite_UpdateStats -#endif - -#ifndef XUartLite_mWriteReg -#define XUartLite_mWriteReg XUartLite_WriteReg -#endif - -#ifndef XUartLite_mReadReg -#define XUartLite_mReadReg XUartLite_ReadReg -#endif - -#ifndef XUartLite_mClearStats -#define XUartLite_mClearStats XUartLite_ClearStats -#endif - -#ifndef XUartLite_mSetControlReg -#define XUartLite_mSetControlReg XUartLite_SetControlReg -#endif - -#ifndef XUartLite_mGetStatusReg -#define XUartLite_mGetStatusReg XUartLite_GetStatusReg -#endif - -#ifndef XUartLite_mIsReceiveEmpty -#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty -#endif - -#ifndef XUartLite_mIsTransmitFull -#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull -#endif - -#ifndef XUartLite_mIsIntrEnabled -#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled -#endif - -#ifndef XUartLite_mEnableIntr -#define XUartLite_mEnableIntr XUartLite_EnableIntr -#endif - -#ifndef XUartLite_mDisableIntr -#define XUartLite_mDisableIntr XUartLite_DisableIntr -#endif - -/*********************************************************************/ -/** - * Macros for Driver XUartNs550 - * - *********************************************************************/ -#ifndef XUartNs550_mUpdateStats -#define XUartNs550_mUpdateStats XUartNs550_UpdateStats -#endif - -#ifndef XUartNs550_mReadReg -#define XUartNs550_mReadReg XUartNs550_ReadReg -#endif - -#ifndef XUartNs550_mWriteReg -#define XUartNs550_mWriteReg XUartNs550_WriteReg -#endif - -#ifndef XUartNs550_mClearStats -#define XUartNs550_mClearStats XUartNs550_ClearStats -#endif - -#ifndef XUartNs550_mGetLineStatusReg -#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg -#endif - -#ifndef XUartNs550_mGetLineControlReg -#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg -#endif - -#ifndef XUartNs550_mSetLineControlReg -#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg -#endif - -#ifndef XUartNs550_mEnableIntr -#define XUartNs550_mEnableIntr XUartNs550_EnableIntr -#endif - -#ifndef XUartNs550_mDisableIntr -#define XUartNs550_mDisableIntr XUartNs550_DisableIntr -#endif - -#ifndef XUartNs550_mIsReceiveData -#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData -#endif - -#ifndef XUartNs550_mIsTransmitEmpty -#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty -#endif - -/*********************************************************************/ -/** - * Macros for Driver XUsb - * - *********************************************************************/ -#ifndef XUsb_mReadReg -#define XUsb_mReadReg XUsb_ReadReg -#endif - -#ifndef XUsb_mWriteReg -#define XUsb_mWriteReg XUsb_WriteReg -#endif - -#endif diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h deleted file mode 100644 index d74906877a1a21cb21308cb48b631af5721dc4ce..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h +++ /dev/null @@ -1,286 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* @file xil_misc_psreset_api.h -* -* This file contains the various register defintions and function prototypes for -* implementing the reset functionality of zynq ps devices -* -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.00b kpc 03/07/13 First release. -* </pre> -* -******************************************************************************/ - -#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */ -#define XIL_MISC_RESET_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - - -/***************************** Include Files *********************************/ -#include "xil_types.h" -#include "xil_io.h" - -/************************** Constant Definitions *****************************/ -#define XDDRC_CTRL_BASEADDR 0xF8006000 -#define XSLCR_BASEADDR 0xF8000000 -/**< OCM configuration register */ -#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x910) -/**< SLCR unlock register */ -#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x8) -/**< SLCR GEM0 rx clock control register */ -#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x138) -/**< SLCR GEM1 rx clock control register */ -#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x13C) -/**< SLCR GEM0 clock control register */ -#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x140) -/**< SLCR GEM1 clock control register */ -#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x144) -/**< SLCR SMC clock control register */ -#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x148) -/**< SLCR GEM reset control register */ -#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x214) -/**< SLCR USB0 clock control register */ -#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x130) -/**< SLCR USB1 clock control register */ -#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x134) -/**< SLCR USB1 reset control register */ -#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x210) -/**< SLCR SMC reset control register */ -#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x234) -/**< SLCR Level shifter enable register */ -#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x900) -/**< SLCR ARM pll control register */ -#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x100) -/**< SLCR DDR pll control register */ -#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x104) -/**< SLCR IO pll control register */ -#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x108) -/**< SLCR ARM pll configuration register */ -#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x110) -/**< SLCR DDR pll configuration register */ -#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x114) -/**< SLCR IO pll configuration register */ -#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x118) -/**< SLCR ARM clock control register */ -#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x120) -/**< SLCR DDR clock control register */ -#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x124) -/**< SLCR MIO pin address register */ -#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x700) -/**< SLCR DMAC reset control address register */ -#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x20C) -/**< SLCR USB reset control address register */ -#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x210) -/**< SLCR GEM reset control address register */ -#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x214) -/**< SLCR SDIO reset control address register */ -#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x218) -/**< SLCR SPI reset control address register */ -#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x21C) -/**< SLCR CAN reset control address register */ -#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x220) -/**< SLCR I2C reset control address register */ -#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x224) -/**< SLCR UART reset control address register */ -#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x228) -/**< SLCR GPIO reset control address register */ -#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x22C) -/**< SLCR LQSPI reset control address register */ -#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x230) -/**< SLCR SMC reset control address register */ -#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x234) -/**< SLCR OCM reset control address register */ -#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x238) - -/**< SMC mem controller clear config register */ -#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0C -/**< SMC idlecount configuration register */ -#define XSMC_REFRESH_PERIOD_0_OFFSET 0x20 -#define XSMC_REFRESH_PERIOD_1_OFFSET 0x24 -/**< SMC ECC configuration register */ -#define XSMC_ECC_MEMCFG1_OFFSET 0x404 -/**< SMC ECC command 1 register */ -#define XSMC_ECC_MEMCMD1_OFFSET 0x404 -/**< SMC ECC command 2 register */ -#define XSMC_ECC_MEMCMD2_OFFSET 0x404 - -/**< SLCR unlock code */ -#define XSLCR_UNLOCK_CODE 0x0000DF0D - -/**< SMC mem clear configuration mask */ -#define XSMC_MEMC_CLR_CONFIG_MASK 0x5F -/**< SMC ECC memconfig 1 reset value */ -#define XSMC_ECC_MEMCFG1_RESET_VAL 0x43 -/**< SMC ECC memcommand 1 reset value */ -#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080 -/**< SMC ECC memcommand 2 reset value */ -#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585 - -/**< DDR controller reset bit mask */ -#define XDDRPS_CTRL_RESET_MASK 0x1 -/**< SLCR OCM configuration reset value*/ -#define XSLCR_OCM_CFG_RESETVAL 0x8 -/**< SLCR OCM bank selection mask*/ -#define XSLCR_OCM_CFG_HIADDR_MASK 0xF -/**< SLCR level shifter enable mask*/ -#define XSLCR_LVL_SHFTR_EN_MASK 0xF - -/**< SLCR PLL register reset values */ -#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008 -#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008 -#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008 -#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0 -#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0 -#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0 -#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400 -#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003 - -/**< SLCR MIO register default values */ -#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601 -#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601 - -/**< SLCR Reset control registers default values */ -#define XSLCR_DMAC_RST_CTRL_VAL 0x1 -#define XSLCR_GEM_RST_CTRL_VAL 0xF3 -#define XSLCR_USB_RST_CTRL_VAL 0x3 -#define XSLCR_I2C_RST_CTRL_VAL 0x3 -#define XSLCR_SPI_RST_CTRL_VAL 0xF -#define XSLCR_UART_RST_CTRL_VAL 0xF -#define XSLCR_QSPI_RST_CTRL_VAL 0x3 -#define XSLCR_GPIO_RST_CTRL_VAL 0x1 -#define XSLCR_SMC_RST_CTRL_VAL 0x3 -#define XSLCR_OCM_RST_CTRL_VAL 0x1 -#define XSLCR_SDIO_RST_CTRL_VAL 0x33 -#define XSLCR_CAN_RST_CTRL_VAL 0x3 -/**************************** Type Definitions *******************************/ - -/* the following data type is used to hold a null terminated version string - * consisting of the following format, "X.YYX" - */ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ -/* - * Performs reset operation to the ddr interface - */ -void XDdr_ResetHw(); -/* - * Map the ocm region to post bootrom state - */ -void XOcm_Remap(); -/* - * Performs the smc interface reset - */ -void XSmc_ResetHw(u32 BaseAddress); -/* - * updates the MIO registers with reset values - */ -void XSlcr_MioWriteResetValues(); -/* - * updates the PLL and clock registers with reset values - */ -void XSlcr_PllWriteResetValues(); -/* - * Disables the level shifters - */ -void XSlcr_DisableLevelShifters(); -/* - * provides softreset to the GPIO interface - */ -void XSlcr_GpioPsReset(void); -/* - * provides softreset to the DMA interface - */ -void XSlcr_DmaPsReset(void); -/* - * provides softreset to the SMC interface - */ -void XSlcr_SmcPsReset(void); -/* - * provides softreset to the CAN interface - */ -void XSlcr_CanPsReset(void); -/* - * provides softreset to the Uart interface - */ -void XSlcr_UartPsReset(void); -/* - * provides softreset to the I2C interface - */ -void XSlcr_I2cPsReset(void); -/* - * provides softreset to the SPI interface - */ -void XSlcr_SpiPsReset(void); -/* - * provides softreset to the QSPI interface - */ -void XSlcr_QspiPsReset(void); -/* - * provides softreset to the USB interface - */ -void XSlcr_UsbPsReset(void); -/* - * provides softreset to the GEM interface - */ -void XSlcr_EmacPsReset(void); -/* - * provides softreset to the OCM interface - */ -void XSlcr_OcmReset(void); - - -#ifdef __cplusplus -} -#endif - -#endif /* XIL_MISC_RESET_H */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_mmu.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_mmu.h deleted file mode 100644 index edbb7e5232afe3b86166f398df07b35a8d8435cb..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_mmu.h +++ /dev/null @@ -1,87 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2012 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -******************************************************************************/ -/*****************************************************************************/ -/** -* @file xil_mmu.h -* -* -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- --------------------------------------------------- -* 1.00a sdm 01/12/12 Initial version -* </pre> -* -* @note -* -* None. -* -******************************************************************************/ - -#ifndef XIL_MMU_H -#define XIL_MMU_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/***************************** Include Files *********************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/**************************** Type Definitions *******************************/ - -/************************** Constant Definitions *****************************/ - -/************************** Variable Definitions *****************************/ - -/************************** Function Prototypes ******************************/ - -void Xil_SetTlbAttributes(u32 addr, u32 attrib); -void Xil_EnableMMU(void); -void Xil_DisableMMU(void); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* XIL_MMU_H */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_printf.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_printf.h deleted file mode 100644 index 89a051c23d3bfed90e15c8ac6d3e169b0e0ac23f..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_printf.h +++ /dev/null @@ -1,47 +0,0 @@ - #ifndef XIL_PRINTF_H - #define XIL_PRINTF_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <ctype.h> -#include <string.h> -#include <stdarg.h> -#include "xparameters.h" -#include "xil_types.h" - -/*----------------------------------------------------*/ -/* Use the following parameter passing structure to */ -/* make xil_printf re-entrant. */ -/*----------------------------------------------------*/ - -struct params_s; - - -/*---------------------------------------------------*/ -/* The purpose of this routine is to output data the */ -/* same as the standard printf function without the */ -/* overhead most run-time libraries involve. Usually */ -/* the printf brings in many kilobytes of code and */ -/* that is unacceptable in most embedded systems. */ -/*---------------------------------------------------*/ - -typedef char* charptr; -typedef int (*func_ptr)(int c); - -/* */ -void padding( const int l_flag, struct params_s *par); -void outs( charptr lp, struct params_s *par); -void outnum( const long n, const long base, struct params_s *par); -int getnum( charptr* linep); -void xil_printf( const char *ctrl1, ...); -void print( const char *ptr); -void outbyte (char); -char inbyte(void); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_testcache.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_testcache.h deleted file mode 100644 index db6d29652e0ed5c79759404d6d6e274dec6e326f..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_testcache.h +++ /dev/null @@ -1,71 +0,0 @@ -/****************************************************************************** -* -* -* (c) Copyright 2009 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_testcache.h -* -* This file contains utility functions to test cache. -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a hbm 07/29/09 First release -* -******************************************************************************/ - -#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */ -#define XIL_TESTCACHE_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -extern int Xil_TestDCacheRange(void); -extern int Xil_TestDCacheAll(void); -extern int Xil_TestICacheRange(void); -extern int Xil_TestICacheAll(void); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_testio.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_testio.h deleted file mode 100644 index 33a8286f17c2be13a43f59c6f07d179fa1384054..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_testio.h +++ /dev/null @@ -1,101 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_testmemend.h -* -* This file contains utility functions to teach endian related memory -* IO functions. -* -* <b>Memory test description</b> -* -* A subset of the memory tests can be selected or all of the tests can be run -* in order. If there is an error detected by a subtest, the test stops and the -* failure code is returned. Further tests are not run even if all of the tests -* are selected. -* -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00 hbm 08/05/09 First release -* </pre> -* -******************************************************************************/ - -#ifndef XIL_TESTIO_H /* prevent circular inclusions */ -#define XIL_TESTIO_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ -#include "xil_types.h" - -/************************** Constant Definitions *****************************/ - - -#define XIL_TESTIO_DEFAULT 0 -#define XIL_TESTIO_LE 1 -#define XIL_TESTIO_BE 2 - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - -extern int Xil_TestIO8(u8 *Addr, int Len, u8 Value); -extern int Xil_TestIO16(u16 *Addr, int Len, u16 Value, int Kind, int Swap); -extern int Xil_TestIO32(u32 *Addr, int Len, u32 Value, int Kind, int Swap); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_testmem.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_testmem.h deleted file mode 100644 index 74e131d5b17e69fa935887c6ba15c00f6a55d7c4..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_testmem.h +++ /dev/null @@ -1,173 +0,0 @@ -/****************************************************************************** -* -* -* (c) Copyright 2009 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_testmem.h -* -* This file contains utility functions to test memory. -* -* <b>Memory test description</b> -* -* A subset of the memory tests can be selected or all of the tests can be run -* in order. If there is an error detected by a subtest, the test stops and the -* failure code is returned. Further tests are not run even if all of the tests -* are selected. -* -* Subtest descriptions: -* <pre> -* XIL_TESTMEM_ALLMEMTESTS: -* Runs all of the following tests -* -* XIL_TESTMEM_INCREMENT: -* Incrementing Value Test. -* This test starts at 'XIL_TESTMEM_INIT_VALUE' and uses the -* incrementing value as the test value for memory. -* -* XIL_TESTMEM_WALKONES: -* Walking Ones Test. -* This test uses a walking '1' as the test value for memory. -* location 1 = 0x00000001 -* location 2 = 0x00000002 -* ... -* -* XIL_TESTMEM_WALKZEROS: -* Walking Zero's Test. -* This test uses the inverse value of the walking ones test -* as the test value for memory. -* location 1 = 0xFFFFFFFE -* location 2 = 0xFFFFFFFD -* ... -* -* XIL_TESTMEM_INVERSEADDR: -* Inverse Address Test. -* This test uses the inverse of the address of the location under test -* as the test value for memory. -* -* XIL_TESTMEM_FIXEDPATTERN: -* Fixed Pattern Test. -* This test uses the provided patters as the test value for memory. -* If zero is provided as the pattern the test uses '0xDEADBEEF". -* </pre> -* -* <i>WARNING</i> -* -* The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces -* have been set up. -* -* The address provided to the memory tests is not checked for -* validity except for the NULL case. It is possible to provide a code-space -* pointer for this test to start with and ultimately destroy executable code -* causing random failures. -* -* @note -* -* Used for spaces where the address range of the region is smaller than -* the data width. If the memory range is greater than 2 ** width, -* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will -* repeat on a boundry of a power of two making it more difficult to detect -* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR -* tests suffer the same problem. Ideally, if large blocks of memory are to be -* tested, break them up into smaller regions of memory to allow the test -* patterns used not to repeat over the region tested. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a hbm 08/25/09 First release -* </pre> -* -******************************************************************************/ - -#ifndef XIL_TESTMEM_H /* prevent circular inclusions */ -#define XIL_TESTMEM_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ -#include "xil_types.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - -/* xutil_memtest defines */ - -#define XIL_TESTMEM_INIT_VALUE 1 - -/** @name Memory subtests - * @{ - */ -/** - * See the detailed description of the subtests in the file description. - */ -#define XIL_TESTMEM_ALLMEMTESTS 0 -#define XIL_TESTMEM_INCREMENT 1 -#define XIL_TESTMEM_WALKONES 2 -#define XIL_TESTMEM_WALKZEROS 3 -#define XIL_TESTMEM_INVERSEADDR 4 -#define XIL_TESTMEM_FIXEDPATTERN 5 -#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN -/* @} */ - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - -/* xutil_testmem prototypes */ - -extern int Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest); -extern int Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest); -extern int Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_types.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_types.h deleted file mode 100644 index f86329e8bd246e3bea2c47571ee75361f764c4c0..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xil_types.h +++ /dev/null @@ -1,160 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_types.h -* -* This file contains basic types for Xilinx software IP. - -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.00a hbm 07/14/09 First release -* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros -* </pre> -* -******************************************************************************/ - -#ifndef XIL_TYPES_H /* prevent circular inclusions */ -#define XIL_TYPES_H /* by using protection macros */ - - -/************************** Constant Definitions *****************************/ - -#ifndef TRUE -# define TRUE 1 -#endif - -#ifndef FALSE -# define FALSE 0 -#endif - -#ifndef NULL -#define NULL 0 -#endif - -#define XIL_COMPONENT_IS_READY 0x11111111 /**< component has been initialized */ -#define XIL_COMPONENT_IS_STARTED 0x22222222 /**< component has been started */ - -/** @name New types - * New simple types. - * @{ - */ -#ifndef __KERNEL__ -#ifndef XBASIC_TYPES_H -/** - * guarded against xbasic_types.h. - */ -typedef unsigned char u8; -typedef unsigned short u16; -typedef unsigned long u32; - -#define __XUINT64__ -typedef struct -{ - u32 Upper; - u32 Lower; -} Xuint64; - -/*****************************************************************************/ -/** -* Return the most significant half of the 64 bit data type. -* -* @param x is the 64 bit word. -* -* @return The upper 32 bits of the 64 bit word. -* -* @note None. -* -******************************************************************************/ -#define XUINT64_MSW(x) ((x).Upper) - -/*****************************************************************************/ -/** -* Return the least significant half of the 64 bit data type. -* -* @param x is the 64 bit word. -* -* @return The lower 32 bits of the 64 bit word. -* -* @note None. -* -******************************************************************************/ -#define XUINT64_LSW(x) ((x).Lower) - -#endif /* XBASIC_TYPES_H */ - -/** - * xbasic_types.h does not typedef s* or u64 - */ -typedef unsigned long long u64; - -typedef char s8; -typedef short s16; -typedef long s32; -typedef long long s64; -#else -#include <linux/types.h> -#endif - - -/*@}*/ - - -/************************** Constant Definitions *****************************/ - -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -#ifndef NULL -#define NULL 0 -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xl2cc.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xl2cc.h deleted file mode 100644 index d7b4cfc94169710616a0067b09cdfc1ac6f8feaf..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xl2cc.h +++ /dev/null @@ -1,180 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2011-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -******************************************************************************/ -/*****************************************************************************/ -/** -* @file xl2cc.h -* -* This file contains the address definitions for the PL310 Level-2 Cache -* Controller. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- --------------------------------------------------- -* 1.00a sdm 02/01/10 Initial version -* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file -* 'xil_errata.h' for errata description -* </pre> -* -* @note -* -* None. -* -******************************************************************************/ - -#ifndef _XL2CC_H_ -#define _XL2CC_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/************************** Constant Definitions *****************************/ -/* L2CC Register Offsets */ -#define XPS_L2CC_ID_OFFSET 0x0000 -#define XPS_L2CC_TYPE_OFFSET 0x0004 -#define XPS_L2CC_CNTRL_OFFSET 0x0100 -#define XPS_L2CC_AUX_CNTRL_OFFSET 0x0104 -#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET 0x0108 -#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET 0x010C - -#define XPS_L2CC_EVNT_CNTRL_OFFSET 0x0200 -#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET 0x0204 -#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET 0x0208 -#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET 0x020C -#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET 0x0210 - -#define XPS_L2CC_IER_OFFSET 0x0214 /* Interrupt Mask */ -#define XPS_L2CC_IPR_OFFSET 0x0218 /* Masked interrupt status */ -#define XPS_L2CC_ISR_OFFSET 0x021C /* Raw Interrupt Status */ -#define XPS_L2CC_IAR_OFFSET 0x0220 /* Interrupt Clear */ - -#define XPS_L2CC_CACHE_SYNC_OFFSET 0x0730 /* Cache Sync */ -#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET 0x0740 /* Dummy Register for Cache Sync */ -#define XPS_L2CC_CACHE_INVLD_PA_OFFSET 0x0770 /* Cache Invalid by PA */ -#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET 0x077C /* Cache Invalid by Way */ -#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET 0x07B0 /* Cache Clean by PA */ -#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET 0x07B8 /* Cache Clean by Index */ -#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET 0x07BC /* Cache Clean by Way */ -#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET 0x07F0 /* Cache Invalidate and Clean by PA */ -#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET 0x07F8 /* Cache Invalidate and Clean by Index */ -#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET 0x07FC /* Cache Invalidate and Clean by Way */ - -#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET 0x0900 /* Cache Data Lockdown 0 by Way */ -#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET 0x0904 /* Cache Instruction Lockdown 0 by Way */ -#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET 0x0908 /* Cache Data Lockdown 1 by Way */ -#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET 0x090C /* Cache Instruction Lockdown 1 by Way */ -#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET 0x0910 /* Cache Data Lockdown 2 by Way */ -#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET 0x0914 /* Cache Instruction Lockdown 2 by Way */ -#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET 0x0918 /* Cache Data Lockdown 3 by Way */ -#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET 0x091C /* Cache Instruction Lockdown 3 by Way */ -#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET 0x0920 /* Cache Data Lockdown 4 by Way */ -#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET 0x0924 /* Cache Instruction Lockdown 4 by Way */ -#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET 0x0928 /* Cache Data Lockdown 5 by Way */ -#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET 0x092C /* Cache Instruction Lockdown 5 by Way */ -#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET 0x0930 /* Cache Data Lockdown 6 by Way */ -#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET 0x0934 /* Cache Instruction Lockdown 6 by Way */ -#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET 0x0938 /* Cache Data Lockdown 7 by Way */ -#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET 0x093C /* Cache Instruction Lockdown 7 by Way */ - -#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950 /* Cache Lockdown Line Enable */ -#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET 0x0954 /* Cache Unlock All Lines by Way */ - -#define XPS_L2CC_ADDR_FILTER_START_OFFSET 0x0C00 /* Start of address filtering */ -#define XPS_L2CC_ADDR_FILTER_END_OFFSET 0x0C04 /* Start of address filtering */ - -#define XPS_L2CC_DEBUG_CTRL_OFFSET 0x0F40 /* Debug Control Register */ - -/* XPS_L2CC_CNTRL_OFFSET bit masks */ -#define XPS_L2CC_ENABLE_MASK 0x00000001 /* enables the L2CC */ - -/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */ -#define XPS_L2CC_AUX_EBRESPE_MASK 0x40000000 /* Early BRESP Enable */ -#define XPS_L2CC_AUX_IPFE_MASK 0x20000000 /* Instruction Prefetch Enable */ -#define XPS_L2CC_AUX_DPFE_MASK 0x10000000 /* Data Prefetch Enable */ -#define XPS_L2CC_AUX_NSIC_MASK 0x08000000 /* Non-secure interrupt access control */ -#define XPS_L2CC_AUX_NSLE_MASK 0x04000000 /* Non-secure lockdown enable */ -#define XPS_L2CC_AUX_CRP_MASK 0x02000000 /* Cache replacement policy */ -#define XPS_L2CC_AUX_FWE_MASK 0x01800000 /* Force write allocate */ -#define XPS_L2CC_AUX_SAOE_MASK 0x00400000 /* Shared attribute override enable */ -#define XPS_L2CC_AUX_PE_MASK 0x00200000 /* Parity enable */ -#define XPS_L2CC_AUX_EMBE_MASK 0x00100000 /* Event monitor bus enable */ -#define XPS_L2CC_AUX_WAY_SIZE_MASK 0x000E0000 /* Way-size */ -#define XPS_L2CC_AUX_ASSOC_MASK 0x00010000 /* Associativity */ -#define XPS_L2CC_AUX_SAIE_MASK 0x00002000 /* Shared attribute invalidate enable */ -#define XPS_L2CC_AUX_EXCL_CACHE_MASK 0x00001000 /* Exclusive cache configuration */ -#define XPS_L2CC_AUX_SBDLE_MASK 0x00000800 /* Store buffer device limitation Enable */ -#define XPS_L2CC_AUX_HPSODRE_MASK 0x00000400 /* High Priority for SO and Dev Reads Enable */ -#define XPS_L2CC_AUX_FLZE_MASK 0x00000001 /* Full line of zero enable */ - -#define XPS_L2CC_AUX_REG_DEFAULT_MASK 0x72360000 /* Enable all prefetching, */ - /* Cache replacement policy, Parity enable, */ - /* Event monitor bus enable and Way Size (64 KB) */ -#define XPS_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFF /* */ - -#define XPS_L2CC_TAG_RAM_DEFAULT_MASK 0x00000111 /* latency for TAG RAM */ -#define XPS_L2CC_DATA_RAM_DEFAULT_MASK 0x00000121 /* latency for DATA RAM */ - -/* Interrupt bit masks */ -#define XPS_L2CC_IXR_DECERR_MASK 0x00000100 /* DECERR from L3 */ -#define XPS_L2CC_IXR_SLVERR_MASK 0x00000080 /* SLVERR from L3 */ -#define XPS_L2CC_IXR_ERRRD_MASK 0x00000040 /* Error on L2 data RAM (Read) */ -#define XPS_L2CC_IXR_ERRRT_MASK 0x00000020 /* Error on L2 tag RAM (Read) */ -#define XPS_L2CC_IXR_ERRWD_MASK 0x00000010 /* Error on L2 data RAM (Write) */ -#define XPS_L2CC_IXR_ERRWT_MASK 0x00000008 /* Error on L2 tag RAM (Write) */ -#define XPS_L2CC_IXR_PARRD_MASK 0x00000004 /* Parity Error on L2 data RAM (Read) */ -#define XPS_L2CC_IXR_PARRT_MASK 0x00000002 /* Parity Error on L2 tag RAM (Read) */ -#define XPS_L2CC_IXR_ECNTR_MASK 0x00000001 /* Event Counter1/0 Overflow Increment */ - -/* Address filtering mask and enable bit */ -#define XPS_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000 /* Address filtering valid bits*/ -#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001 /* Address filtering enable bit*/ - -/* Debug control bits */ -#define XPS_L2CC_DEBUG_SPIDEN_MASK 0x00000004 /* Debug SPIDEN bit */ -#define XPS_L2CC_DEBUG_DWB_MASK 0x00000002 /* Debug DWB bit, forces write through */ -#define XPS_L2CC_DEBUG_DCL_MASK 0x00000002 /* Debug DCL bit, disables cache line fill */ - -#ifdef __cplusplus -} -#endif - -#endif /* protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xl2cc_counter.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xl2cc_counter.h deleted file mode 100644 index 30952b1dca611777b10c00f66d7dab8074fcad89..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xl2cc_counter.h +++ /dev/null @@ -1,117 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2011-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xl2cc_counter.h -* -* This header file contains APIs for configuring and controlling the event -* counters in PL310 L2 cache controller. -* PL310 has 2 event counters which can be used to count a variety of events -* like DRHIT, DRREQ, DWHIT, DWREQ, etc. This file defines configurations, -* where value configures the event counters to count a set of events. -* -* XL2cc_EventCtrInit API can be used to select a set of events and -* XL2cc_EventCtrStart configures the event counters and starts the counters. -* XL2cc_EventCtrStop diables the event counters and returns the counter values. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a sdm 07/11/11 First release -* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address -* inside the APIs -* </pre> -* -******************************************************************************/ - -#ifndef L2CCCOUNTER_H /* prevent circular inclusions */ -#define L2CCCOUNTER_H /* by using protection macros */ - -/***************************** Include Files ********************************/ - -#include "xpseudo_asm.h" -#include "xil_types.h" - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/************************** Constant Definitions ****************************/ - -/* - * The following constants define the event codes for the event counters. - */ -#define XL2CC_CO 0x1 -#define XL2CC_DRHIT 0x2 -#define XL2CC_DRREQ 0x3 -#define XL2CC_DWHIT 0x4 -#define XL2CC_DWREQ 0x5 -#define XL2CC_DWTREQ 0x6 -#define XL2CC_IRHIT 0x7 -#define XL2CC_IRREQ 0x8 -#define XL2CC_WA 0x9 -#define XL2CC_IPFALLOC 0xa -#define XL2CC_EPFHIT 0xb -#define XL2CC_EPFALLOC 0xc -#define XL2CC_SRRCVD 0xd -#define XL2CC_SRCONF 0xe -#define XL2CC_EPFRCVD 0xf - -/**************************** Type Definitions ******************************/ - -/***************** Macros (Inline Functions) Definitions ********************/ - -/************************** Variable Definitions ****************************/ - -/************************** Function Prototypes *****************************/ - -void XL2cc_EventCtrInit(int Event0, int Event1); -void XL2cc_EventCtrStart(void); -void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* L2CCCOUNTER_H */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xparameters.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xparameters.h deleted file mode 100644 index ca53a8df250b173c573c4c7d77e30b4fdb1af8ed..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xparameters.h +++ /dev/null @@ -1,539 +0,0 @@ - -/******************************************************************* -* -* CAUTION: This file is automatically generated by libgen. -* Version: Xilinx EDK 14.7 EDK_P.20131013 -* DO NOT EDIT. -* -* Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. - -* -* Description: Driver parameters -* -*******************************************************************/ - -#include "xparameters_ps.h" - -#define STDIN_BASEADDRESS 0xE0001000 -#define STDOUT_BASEADDRESS 0xE0001000 - -/******************************************************************/ - -/* Definitions for driver TMRCTR */ -#define XPAR_XTMRCTR_NUM_INSTANCES 1 - -/* Definitions for peripheral AXI_TIMER_0 */ -#define XPAR_AXI_TIMER_0_DEVICE_ID 0 -#define XPAR_AXI_TIMER_0_BASEADDR 0x42800000 -#define XPAR_AXI_TIMER_0_HIGHADDR 0x4280FFFF -#define XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ 100000000 - - -/******************************************************************/ - -/* Canonical definitions for peripheral AXI_TIMER_0 */ -#define XPAR_TMRCTR_0_DEVICE_ID XPAR_AXI_TIMER_0_DEVICE_ID -#define XPAR_TMRCTR_0_BASEADDR 0x42800000 -#define XPAR_TMRCTR_0_HIGHADDR 0x4280FFFF -#define XPAR_TMRCTR_0_CLOCK_FREQ_HZ XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ - -/******************************************************************/ - -/* Definitions for driver GPIO */ -#define XPAR_XGPIO_NUM_INSTANCES 1 - -/* Definitions for peripheral BTNS_4BITS_TRI_IO */ -#define XPAR_BTNS_4BITS_TRI_IO_BASEADDR 0x41200000 -#define XPAR_BTNS_4BITS_TRI_IO_HIGHADDR 0x4120FFFF -#define XPAR_BTNS_4BITS_TRI_IO_DEVICE_ID 0 -#define XPAR_BTNS_4BITS_TRI_IO_INTERRUPT_PRESENT 0 -#define XPAR_BTNS_4BITS_TRI_IO_IS_DUAL 0 - - -/******************************************************************/ - -/* Canonical definitions for peripheral BTNS_4BITS_TRI_IO */ -#define XPAR_GPIO_0_BASEADDR 0x41200000 -#define XPAR_GPIO_0_HIGHADDR 0x4120FFFF -#define XPAR_GPIO_0_DEVICE_ID XPAR_BTNS_4BITS_TRI_IO_DEVICE_ID -#define XPAR_GPIO_0_INTERRUPT_PRESENT 0 -#define XPAR_GPIO_0_IS_DUAL 0 - - -/******************************************************************/ - - -/* Definitions for peripheral PS7_AFI_0 */ -#define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000 -#define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF - - -/* Definitions for peripheral PS7_AFI_1 */ -#define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000 -#define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF - - -/* Definitions for peripheral PS7_AFI_2 */ -#define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000 -#define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF - - -/* Definitions for peripheral PS7_AFI_3 */ -#define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000 -#define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF - - -/* Definitions for peripheral PS7_CORESIGHT_COMP_0 */ -#define XPAR_PS7_CORESIGHT_COMP_0_S_AXI_BASEADDR 0xF8800000 -#define XPAR_PS7_CORESIGHT_COMP_0_S_AXI_HIGHADDR 0xF88FFFFF - - -/* Definitions for peripheral PS7_DDR_0 */ -#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000 -#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x1FFFFFFF -#define XPAR_PS7_DDR_0_S_AXI_HP0_BASEADDR 0x00000000 -#define XPAR_PS7_DDR_0_S_AXI_HP0_HIGHADDR 0x1FFFFFFF -#define XPAR_PS7_DDR_0_S_AXI_HP1_BASEADDR 0x00000000 -#define XPAR_PS7_DDR_0_S_AXI_HP1_HIGHADDR 0x1FFFFFFF -#define XPAR_PS7_DDR_0_S_AXI_HP2_BASEADDR 0x00000000 -#define XPAR_PS7_DDR_0_S_AXI_HP2_HIGHADDR 0x1FFFFFFF -#define XPAR_PS7_DDR_0_S_AXI_HP3_BASEADDR 0x00000000 -#define XPAR_PS7_DDR_0_S_AXI_HP3_HIGHADDR 0x1FFFFFFF - - -/* Definitions for peripheral PS7_DDRC_0 */ -#define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000 -#define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF - - -/* Definitions for peripheral PS7_GLOBALTIMER_0 */ -#define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200 -#define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF - - -/* Definitions for peripheral PS7_GPV_0 */ -#define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000 -#define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF - - -/* Definitions for peripheral PS7_INTC_DIST_0 */ -#define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000 -#define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF - - -/* Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */ -#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000 -#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF - - -/* Definitions for peripheral PS7_L2CACHEC_0 */ -#define XPAR_PS7_L2CACHEC_0_S_AXI_BASEADDR 0xF8F02000 -#define XPAR_PS7_L2CACHEC_0_S_AXI_HIGHADDR 0xF8F02FFF - - -/* Definitions for peripheral PS7_OCMC_0 */ -#define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000 -#define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF - - -/* Definitions for peripheral PS7_QSPI_LINEAR_0 */ -#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000 -#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFCFFFFFF - - -/* Definitions for peripheral PS7_RAM_0 */ -#define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000 -#define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0002FFFF -#define XPAR_PS7_RAM_0_S_AXI_HP0_HIGHOCM_BASEADDR 0xFFFC0000 -#define XPAR_PS7_RAM_0_S_AXI_HP0_HIGHOCM_HIGHADDR 0xFFFFFDFF -#define XPAR_PS7_RAM_0_S_AXI_HP1_HIGHOCM_BASEADDR 0xFFFC0000 -#define XPAR_PS7_RAM_0_S_AXI_HP1_HIGHOCM_HIGHADDR 0xFFFFFDFF -#define XPAR_PS7_RAM_0_S_AXI_HP2_HIGHOCM_BASEADDR 0xFFFC0000 -#define XPAR_PS7_RAM_0_S_AXI_HP2_HIGHOCM_HIGHADDR 0xFFFFFDFF -#define XPAR_PS7_RAM_0_S_AXI_HP3_HIGHOCM_BASEADDR 0xFFFC0000 -#define XPAR_PS7_RAM_0_S_AXI_HP3_HIGHOCM_HIGHADDR 0xFFFFFDFF - - -/* Definitions for peripheral PS7_RAM_1 */ -#define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFF0000 -#define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFDFF -#define XPAR_PS7_RAM_1_S_AXI_HP0_HIGHOCM_BASEADDR 0xFFFC0000 -#define XPAR_PS7_RAM_1_S_AXI_HP0_HIGHOCM_HIGHADDR 0xFFFFFDFF -#define XPAR_PS7_RAM_1_S_AXI_HP1_HIGHOCM_BASEADDR 0xFFFC0000 -#define XPAR_PS7_RAM_1_S_AXI_HP1_HIGHOCM_HIGHADDR 0xFFFFFDFF -#define XPAR_PS7_RAM_1_S_AXI_HP2_HIGHOCM_BASEADDR 0xFFFC0000 -#define XPAR_PS7_RAM_1_S_AXI_HP2_HIGHOCM_HIGHADDR 0xFFFFFDFF -#define XPAR_PS7_RAM_1_S_AXI_HP3_HIGHOCM_BASEADDR 0xFFFC0000 -#define XPAR_PS7_RAM_1_S_AXI_HP3_HIGHOCM_HIGHADDR 0xFFFFFDFF - - -/* Definitions for peripheral PS7_SCUC_0 */ -#define XPAR_PS7_SCUC_0_S_AXI_BASEADDR 0xF8F00000 -#define XPAR_PS7_SCUC_0_S_AXI_HIGHADDR 0xF8F000FC - - -/* Definitions for peripheral PS7_SD_0 */ -#define XPAR_PS7_SD_0_S_AXI_BASEADDR 0xE0100000 -#define XPAR_PS7_SD_0_S_AXI_HIGHADDR 0xE0100FFF - - -/* Definitions for peripheral PS7_SLCR_0 */ -#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000 -#define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF - - -/* Definitions for peripheral PWM_RECORDER_0 */ -#define XPAR_PWM_RECORDER_0_BASEADDR 0x76EA0000 -#define XPAR_PWM_RECORDER_0_HIGHADDR 0x76EAFFFF - - -/* Definitions for peripheral PWM_RECORDER_1 */ -#define XPAR_PWM_RECORDER_1_BASEADDR 0x76E80000 -#define XPAR_PWM_RECORDER_1_HIGHADDR 0x76E8FFFF - - -/* Definitions for peripheral PWM_RECORDER_2 */ -#define XPAR_PWM_RECORDER_2_BASEADDR 0x76E60000 -#define XPAR_PWM_RECORDER_2_HIGHADDR 0x76E6FFFF - - -/* Definitions for peripheral PWM_RECORDER_3 */ -#define XPAR_PWM_RECORDER_3_BASEADDR 0x76E40000 -#define XPAR_PWM_RECORDER_3_HIGHADDR 0x76E4FFFF - - -/* Definitions for peripheral PWM_RECORDER_4 */ -#define XPAR_PWM_RECORDER_4_BASEADDR 0x76E20000 -#define XPAR_PWM_RECORDER_4_HIGHADDR 0x76E2FFFF - - -/* Definitions for peripheral PWM_RECORDER_5 */ -#define XPAR_PWM_RECORDER_5_BASEADDR 0x76E00000 -#define XPAR_PWM_RECORDER_5_HIGHADDR 0x76E0FFFF - - -/* Definitions for peripheral PWM_SIGNAL_OUT_WKILLSWITCH_0 */ -#define XPAR_PWM_SIGNAL_OUT_WKILLSWITCH_0_BASEADDR 0x79460000 -#define XPAR_PWM_SIGNAL_OUT_WKILLSWITCH_0_HIGHADDR 0x7946FFFF - - -/* Definitions for peripheral PWM_SIGNAL_OUT_WKILLSWITCH_1 */ -#define XPAR_PWM_SIGNAL_OUT_WKILLSWITCH_1_BASEADDR 0x79440000 -#define XPAR_PWM_SIGNAL_OUT_WKILLSWITCH_1_HIGHADDR 0x7944FFFF - - -/* Definitions for peripheral PWM_SIGNAL_OUT_WKILLSWITCH_2 */ -#define XPAR_PWM_SIGNAL_OUT_WKILLSWITCH_2_BASEADDR 0x79420000 -#define XPAR_PWM_SIGNAL_OUT_WKILLSWITCH_2_HIGHADDR 0x7942FFFF - - -/* Definitions for peripheral PWM_SIGNAL_OUT_WKILLSWITCH_3 */ -#define XPAR_PWM_SIGNAL_OUT_WKILLSWITCH_3_BASEADDR 0x79400000 -#define XPAR_PWM_SIGNAL_OUT_WKILLSWITCH_3_HIGHADDR 0x7940FFFF - - -/******************************************************************/ - -/* Definitions for driver DEVCFG */ -#define XPAR_XDCFG_NUM_INSTANCES 1 - -/* Definitions for peripheral PS7_DEV_CFG_0 */ -#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0 -#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000 -#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FF - - -/******************************************************************/ - -/* Canonical definitions for peripheral PS7_DEV_CFG_0 */ -#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID -#define XPAR_XDCFG_0_BASEADDR 0xF8007000 -#define XPAR_XDCFG_0_HIGHADDR 0xF80070FF - - -/******************************************************************/ - -/* Definitions for driver DMAPS */ -#define XPAR_XDMAPS_NUM_INSTANCES 2 - -/* Definitions for peripheral PS7_DMA_NS */ -#define XPAR_PS7_DMA_NS_DEVICE_ID 0 -#define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000 -#define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF - - -/* Definitions for peripheral PS7_DMA_S */ -#define XPAR_PS7_DMA_S_DEVICE_ID 1 -#define XPAR_PS7_DMA_S_BASEADDR 0xF8003000 -#define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF - - -/******************************************************************/ - -/* Canonical definitions for peripheral PS7_DMA_NS */ -#define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID -#define XPAR_XDMAPS_0_BASEADDR 0xF8004000 -#define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF - -/* Canonical definitions for peripheral PS7_DMA_S */ -#define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID -#define XPAR_XDMAPS_1_BASEADDR 0xF8003000 -#define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF - - -/******************************************************************/ - -/* Definitions for driver EMACPS */ -#define XPAR_XEMACPS_NUM_INSTANCES 1 - -/* Definitions for peripheral PS7_ETHERNET_0 */ -#define XPAR_PS7_ETHERNET_0_DEVICE_ID 0 -#define XPAR_PS7_ETHERNET_0_BASEADDR 0xE000B000 -#define XPAR_PS7_ETHERNET_0_HIGHADDR 0xE000BFFF -#define XPAR_PS7_ETHERNET_0_ENET_CLK_FREQ_HZ 125000000 -#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 8 -#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1 -#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 8 -#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5 -#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 8 -#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50 - - -/******************************************************************/ - -/* Canonical definitions for peripheral PS7_ETHERNET_0 */ -#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID -#define XPAR_XEMACPS_0_BASEADDR 0xE000B000 -#define XPAR_XEMACPS_0_HIGHADDR 0xE000BFFF -#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 125000000 -#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 8 -#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1 -#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 8 -#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5 -#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 8 -#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50 - - -/******************************************************************/ - -/* Definitions for driver GPIOPS */ -#define XPAR_XGPIOPS_NUM_INSTANCES 1 - -/* Definitions for peripheral PS7_GPIO_0 */ -#define XPAR_PS7_GPIO_0_DEVICE_ID 0 -#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000 -#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF - - -/******************************************************************/ - -/* Canonical definitions for peripheral PS7_GPIO_0 */ -#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID -#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000 -#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF - - -/******************************************************************/ - -/* Definitions for driver IICPS */ -#define XPAR_XIICPS_NUM_INSTANCES 1 - -/* Definitions for peripheral PS7_I2C_0 */ -#define XPAR_PS7_I2C_0_DEVICE_ID 0 -#define XPAR_PS7_I2C_0_BASEADDR 0xE0004000 -#define XPAR_PS7_I2C_0_HIGHADDR 0xE0004FFF -#define XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ 108333336 - - -/******************************************************************/ - -/* Canonical definitions for peripheral PS7_I2C_0 */ -#define XPAR_XIICPS_0_DEVICE_ID XPAR_PS7_I2C_0_DEVICE_ID -#define XPAR_XIICPS_0_BASEADDR 0xE0004000 -#define XPAR_XIICPS_0_HIGHADDR 0xE0004FFF -#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 108333336 - - -/******************************************************************/ - -/* Definitions for driver QSPIPS */ -#define XPAR_XQSPIPS_NUM_INSTANCES 1 - -/* Definitions for peripheral PS7_QSPI_0 */ -#define XPAR_PS7_QSPI_0_DEVICE_ID 0 -#define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000 -#define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF -#define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000 -#define XPAR_PS7_QSPI_0_QSPI_MODE 0 - - -/******************************************************************/ - -/* Canonical definitions for peripheral PS7_QSPI_0 */ -#define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID -#define XPAR_XQSPIPS_0_BASEADDR 0xE000D000 -#define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF -#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000 -#define XPAR_XQSPIPS_0_QSPI_MODE 0 - - -/******************************************************************/ - -/* Definitions for Fabric interrupts connected to ps7_scugic_0 */ - -/******************************************************************/ - -/* Canonical definitions for Fabric interrupts connected to ps7_scugic_0 */ - -/******************************************************************/ - -/* Definitions for driver SCUGIC */ -#define XPAR_XSCUGIC_NUM_INSTANCES 1 - -/* Definitions for peripheral PS7_SCUGIC_0 */ -#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0 -#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100 -#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FF -#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000 - - -/******************************************************************/ - -/* Canonical definitions for peripheral PS7_SCUGIC_0 */ -#define XPAR_SCUGIC_0_DEVICE_ID XPAR_PS7_SCUGIC_0_DEVICE_ID -#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100 -#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FF -#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000 - - -/******************************************************************/ - -/* Definitions for driver SCUTIMER */ -#define XPAR_XSCUTIMER_NUM_INSTANCES 1 - -/* Definitions for peripheral PS7_SCUTIMER_0 */ -#define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0 -#define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600 -#define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F - - -/******************************************************************/ - -/* Canonical definitions for peripheral PS7_SCUTIMER_0 */ -#define XPAR_XSCUTIMER_0_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID -#define XPAR_XSCUTIMER_0_BASEADDR 0xF8F00600 -#define XPAR_XSCUTIMER_0_HIGHADDR 0xF8F0061F - - -/******************************************************************/ - -/* Definitions for driver SCUWDT */ -#define XPAR_XSCUWDT_NUM_INSTANCES 1 - -/* Definitions for peripheral PS7_SCUWDT_0 */ -#define XPAR_PS7_SCUWDT_0_DEVICE_ID 0 -#define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620 -#define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF - - -/******************************************************************/ - -/* Canonical definitions for peripheral PS7_SCUWDT_0 */ -#define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID -#define XPAR_SCUWDT_0_BASEADDR 0xF8F00620 -#define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF - - -/******************************************************************/ - -/* Definitions for driver UARTPS */ -#define XPAR_XUARTPS_NUM_INSTANCES 2 - -/* Definitions for peripheral PS7_UART_0 */ -#define XPAR_PS7_UART_0_DEVICE_ID 0 -#define XPAR_PS7_UART_0_BASEADDR 0xE0000000 -#define XPAR_PS7_UART_0_HIGHADDR 0xE0000FFF -#define XPAR_PS7_UART_0_UART_CLK_FREQ_HZ 50000000 -#define XPAR_PS7_UART_0_HAS_MODEM 0 - - -/* Definitions for peripheral PS7_UART_1 */ -#define XPAR_PS7_UART_1_DEVICE_ID 1 -#define XPAR_PS7_UART_1_BASEADDR 0xE0001000 -#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF -#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 50000000 -#define XPAR_PS7_UART_1_HAS_MODEM 0 - - -/******************************************************************/ - -/* Canonical definitions for peripheral PS7_UART_0 */ -#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_0_DEVICE_ID -#define XPAR_XUARTPS_0_BASEADDR 0xE0000000 -#define XPAR_XUARTPS_0_HIGHADDR 0xE0000FFF -#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 50000000 -#define XPAR_XUARTPS_0_HAS_MODEM 0 - -/* Canonical definitions for peripheral PS7_UART_1 */ -#define XPAR_XUARTPS_1_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID -#define XPAR_XUARTPS_1_BASEADDR 0xE0001000 -#define XPAR_XUARTPS_1_HIGHADDR 0xE0001FFF -#define XPAR_XUARTPS_1_UART_CLK_FREQ_HZ 50000000 -#define XPAR_XUARTPS_1_HAS_MODEM 0 - - -/******************************************************************/ - -/* Definitions for driver USBPS */ -#define XPAR_XUSBPS_NUM_INSTANCES 1 - -/* Definitions for peripheral PS7_USB_0 */ -#define XPAR_PS7_USB_0_DEVICE_ID 0 -#define XPAR_PS7_USB_0_BASEADDR 0xE0002000 -#define XPAR_PS7_USB_0_HIGHADDR 0xE0002FFF - - -/******************************************************************/ - -/* Canonical definitions for peripheral PS7_USB_0 */ -#define XPAR_XUSBPS_0_DEVICE_ID XPAR_PS7_USB_0_DEVICE_ID -#define XPAR_XUSBPS_0_BASEADDR 0xE0002000 -#define XPAR_XUSBPS_0_HIGHADDR 0xE0002FFF - - -/******************************************************************/ - -/* Definitions for driver XADCPS */ -#define XPAR_XADCPS_NUM_INSTANCES 1 - -/* Definitions for peripheral PS7_XADC_0 */ -#define XPAR_PS7_XADC_0_DEVICE_ID 0 -#define XPAR_PS7_XADC_0_BASEADDR 0xF8007100 -#define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120 - - -/******************************************************************/ - -/* Canonical definitions for peripheral PS7_XADC_0 */ -#define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID -#define XPAR_XADCPS_0_BASEADDR 0xF8007100 -#define XPAR_XADCPS_0_HIGHADDR 0xF8007120 - - -/******************************************************************/ - -/* Definition for CPU ID */ -#define XPAR_CPU_ID 0 - -/* Definitions for peripheral PS7_CORTEXA9_0 */ -#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 650000000 - - -/******************************************************************/ - -/* Canonical definitions for peripheral PS7_CORTEXA9_0 */ -#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 650000000 - - -/******************************************************************/ - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xparameters_ps.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xparameters_ps.h deleted file mode 100644 index 766e1705ba39fb5d731e58776a41fc0787e63626..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xparameters_ps.h +++ /dev/null @@ -1,334 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -******************************************************************************/ -/*****************************************************************************/ -/** -* @file xparameters_ps.h -* -* This file contains the address definitions for the hard peripherals -* attached to the ARM Cortex A9 core. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------- -------- --------------------------------------------------- -* 1.00a ecm/sdm 02/01/10 Initial version -* 3.04a sdm 02/02/12 Removed some of the defines as they are being generated through -* driver tcl -* </pre> -* -* @note -* -* None. -* -******************************************************************************/ - -#ifndef _XPARAMETERS_PS_H_ -#define _XPARAMETERS_PS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/************************** Constant Definitions *****************************/ - -/* - * This block contains constant declarations for the peripherals - * within the hardblock - */ - -/* Canonical definitions for DDR MEMORY */ -#define XPAR_DDR_MEM_BASEADDR 0x00000000 -#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFF - -/* Canonical definitions for Interrupts */ -#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID -#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID -#define XPAR_XUSBPS_0_INTR XPS_USB0_INT_ID -#define XPAR_XUSBPS_1_INTR XPS_USB1_INT_ID -#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID -#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID -#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID -#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID -#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID -#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID -#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID -#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID -#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID -#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID -#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID -#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID -#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID -#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID -#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID -#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID -#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID -#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID -#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID -#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID -#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID -#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID -#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID -#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID -#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID -#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID -#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID -#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID -#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID -#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID -#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID -#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID -#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID - - -#define XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR -#define XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR - - - -/* Canonical definitions for DMAC */ - - -/* Canonical definitions for WDT */ - -/* Canonical definitions for SLCR */ -#define XPAR_XSLCR_NUM_INSTANCES 1 -#define XPAR_XSLCR_0_DEVICE_ID 0 -#define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR - -/* Canonical definitions for SCU GIC */ -#define XPAR_SCUGIC_NUM_INSTANCES 1 -#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0 -#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x0100) -#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x1000) -#define XPAR_SCUGIC_ACK_BEFORE 0 - -/* Canonical definitions for Global Timer */ -#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1 -#define XPAR_GLOBAL_TMR_DEVICE_ID 0 -#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x200) -#define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID - - -/* Xilinx Parallel Flash Library (XilFlash) User Settings */ -#define XPAR_AXI_EMC - - -#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ - - -/* - * This block contains constant declarations for the peripherals - * within the hardblock. These have been put for bacwards compatibilty - */ - -#define XPS_PERIPHERAL_BASEADDR 0xE0000000 -#define XPS_UART0_BASEADDR 0xE0000000 -#define XPS_UART1_BASEADDR 0xE0001000 -#define XPS_USB0_BASEADDR 0xE0002000 -#define XPS_USB1_BASEADDR 0xE0003000 -#define XPS_I2C0_BASEADDR 0xE0004000 -#define XPS_I2C1_BASEADDR 0xE0005000 -#define XPS_SPI0_BASEADDR 0xE0006000 -#define XPS_SPI1_BASEADDR 0xE0007000 -#define XPS_CAN0_BASEADDR 0xE0008000 -#define XPS_CAN1_BASEADDR 0xE0009000 -#define XPS_GPIO_BASEADDR 0xE000A000 -#define XPS_GEM0_BASEADDR 0xE000B000 -#define XPS_GEM1_BASEADDR 0xE000C000 -#define XPS_QSPI_BASEADDR 0xE000D000 -#define XPS_PARPORT_CRTL_BASEADDR 0xE000E000 -#define XPS_SDIO0_BASEADDR 0xE0100000 -#define XPS_SDIO1_BASEADDR 0xE0101000 -#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000 -#define XPS_NAND_BASEADDR 0xE1000000 -#define XPS_PARPORT0_BASEADDR 0xE2000000 -#define XPS_PARPORT1_BASEADDR 0xE4000000 -#define XPS_QSPI_LINEAR_BASEADDR 0xFC000000 -#define XPS_SYS_CTRL_BASEADDR 0xF8000000 /* AKA SLCR */ -#define XPS_TTC0_BASEADDR 0xF8001000 -#define XPS_TTC1_BASEADDR 0xF8002000 -#define XPS_DMAC0_SEC_BASEADDR 0xF8003000 -#define XPS_DMAC0_NON_SEC_BASEADDR 0xF8004000 -#define XPS_WDT_BASEADDR 0xF8005000 -#define XPS_DDR_CTRL_BASEADDR 0xF8006000 -#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000 -#define XPS_AFI0_BASEADDR 0xF8008000 -#define XPS_AFI1_BASEADDR 0xF8009000 -#define XPS_AFI2_BASEADDR 0xF800A000 -#define XPS_AFI3_BASEADDR 0xF800B000 -#define XPS_OCM_BASEADDR 0xF800C000 -#define XPS_EFUSE_BASEADDR 0xF800D000 -#define XPS_CORESIGHT_BASEADDR 0xF8800000 -#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000 -#define XPS_SCU_PERIPH_BASE 0xF8F00000 -#define XPS_L2CC_BASEADDR 0xF8F02000 -#define XPS_SAM_RAM_BASEADDR 0xFFFC0000 -#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000 -#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000 -#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000 -#define XPS_PERIPH_APB_BASEADDR 0xF8000000 - -/* Shared Peripheral Interrupts (SPI) */ -#define XPS_CORE_PARITY0_INT_ID 32 -#define XPS_CORE_PARITY1_INT_ID 33 -#define XPS_L2CC_INT_ID 34 -#define XPS_OCMINTR_INT_ID 35 -#define XPS_ECC_INT_ID 36 -#define XPS_PMU0_INT_ID 37 -#define XPS_PMU1_INT_ID 38 -#define XPS_SYSMON_INT_ID 39 -#define XPS_DVC_INT_ID 40 -#define XPS_WDT_INT_ID 41 -#define XPS_TTC0_0_INT_ID 42 -#define XPS_TTC0_1_INT_ID 43 -#define XPS_TTC0_2_INT_ID 44 -#define XPS_DMA0_ABORT_INT_ID 45 -#define XPS_DMA0_INT_ID 46 -#define XPS_DMA1_INT_ID 47 -#define XPS_DMA2_INT_ID 48 -#define XPS_DMA3_INT_ID 49 -#define XPS_SMC_INT_ID 50 -#define XPS_QSPI_INT_ID 51 -#define XPS_GPIO_INT_ID 52 -#define XPS_USB0_INT_ID 53 -#define XPS_GEM0_INT_ID 54 -#define XPS_GEM0_WAKE_INT_ID 55 -#define XPS_SDIO0_INT_ID 56 -#define XPS_I2C0_INT_ID 57 -#define XPS_SPI0_INT_ID 58 -#define XPS_UART0_INT_ID 59 -#define XPS_CAN0_INT_ID 60 -#define XPS_FPGA0_INT_ID 61 -#define XPS_FPGA1_INT_ID 62 -#define XPS_FPGA2_INT_ID 63 -#define XPS_FPGA3_INT_ID 64 -#define XPS_FPGA4_INT_ID 65 -#define XPS_FPGA5_INT_ID 66 -#define XPS_FPGA6_INT_ID 67 -#define XPS_FPGA7_INT_ID 68 -#define XPS_TTC1_0_INT_ID 69 -#define XPS_TTC1_1_INT_ID 70 -#define XPS_TTC1_2_INT_ID 71 -#define XPS_DMA4_INT_ID 72 -#define XPS_DMA5_INT_ID 73 -#define XPS_DMA6_INT_ID 74 -#define XPS_DMA7_INT_ID 75 -#define XPS_USB1_INT_ID 76 -#define XPS_GEM1_INT_ID 77 -#define XPS_GEM1_WAKE_INT_ID 78 -#define XPS_SDIO1_INT_ID 79 -#define XPS_I2C1_INT_ID 80 -#define XPS_SPI1_INT_ID 81 -#define XPS_UART1_INT_ID 82 -#define XPS_CAN1_INT_ID 83 -#define XPS_FPGA8_INT_ID 84 -#define XPS_FPGA9_INT_ID 85 -#define XPS_FPGA10_INT_ID 86 -#define XPS_FPGA11_INT_ID 87 -#define XPS_FPGA12_INT_ID 88 -#define XPS_FPGA13_INT_ID 89 -#define XPS_FPGA14_INT_ID 90 -#define XPS_FPGA15_INT_ID 91 - -/* Private Peripheral Interrupts (PPI) */ -#define XPS_GLOBAL_TMR_INT_ID 27 /* SCU Global Timer interrupt */ -#define XPS_FIQ_INT_ID 28 /* FIQ from FPGA fabric */ -#define XPS_SCU_TMR_INT_ID 29 /* SCU Private Timer interrupt */ -#define XPS_SCU_WDT_INT_ID 30 /* SCU Private WDT interrupt */ -#define XPS_IRQ_INT_ID 31 /* IRQ from FPGA fabric */ - - -/* REDEFINES for TEST APP */ -/* Definitions for UART */ -#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID -#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID -#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID -#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID -#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID -#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID -#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID -#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID -#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID -#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID -#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID -#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID -#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID -#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID -#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID -#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID -#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID -#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID -#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID -#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID - -#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID - -/* For backwards compatibilty */ -#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ -#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ -#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ -#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ -#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ -#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ -#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ -#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ -#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ -#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ - -#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ - -#ifdef XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ -#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ -#endif - -#ifdef XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ -#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ -#endif - -#define XPAR_SCUTIMER_DEVICE_ID 0 -#define XPAR_SCUWDT_DEVICE_ID 0 - - -#ifdef __cplusplus -} -#endif - -#endif /* protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xpm_counter.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xpm_counter.h deleted file mode 100644 index 2ef3f9fab63565cc936f87c2335dd090f786c114..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xpm_counter.h +++ /dev/null @@ -1,580 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2011-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xpm_counter.h -* -* This header file contains APIs for configuring and controlling the Cortex-A9 -* Performance Monitor Events. -* Cortex-A9 Performance Monitor has 6 event counters which can be used to -* count a variety of events described in Coretx-A9 TRM. This file defines -* configurations, where value configures the event counters to count a -* set of events. -* -* Xpm_SetEvents can be used to set the event counters to count a set of events -* and Xpm_GetEventCounters can be used to read the counter values. -* -* @note -* -* This file doesn't handle the Cortex-A9 cycle counter, as the cycle counter is -* being used for time keeping. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a sdm 07/11/11 First release -* </pre> -* -******************************************************************************/ - -#ifndef XPMCOUNTER_H /* prevent circular inclusions */ -#define XPMCOUNTER_H /* by using protection macros */ - -/***************************** Include Files ********************************/ - -#include <stdint.h> -#include "xpseudo_asm.h" -#include "xil_types.h" - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/************************** Constant Definitions ****************************/ - -/* Number of performance counters */ -#define XPM_CTRCOUNT 6 - -/* The following constants define the Cortex-A9 Performance Monitor Events */ - -/* - * Software increment. The register is incremented only on writes to the - * Software Increment Register - */ -#define XPM_EVENT_SOFTINCR 0x00 - -/* - * Instruction fetch that causes a refill at (at least) the lowest level(s) of - * instruction or unified cache. Includes the speculative linefills in the - * count - */ -#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01 - -/* - * Instruction fetch that causes a TLB refill at (at least) the lowest level of - * TLB. Includes the speculative requests in the count - */ -#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02 - -/* - * Data read or write operation that causes a refill at (at least) the lowest - * level(s)of data or unified cache. Counts the number of allocations performed - * in the Data Cache due to a read or a write - */ -#define XPM_EVENT_DATA_CACHEREFILL 0x03 - -/* - * Data read or write operation that causes a cache access at (at least) the - * lowest level(s) of data or unified cache. This includes speculative reads - */ -#define XPM_EVENT_DATA_CACHEACCESS 0x04 - -/* - * Data read or write operation that causes a TLB refill at (at least) the - * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI, - * CP15 Cache operation by MVA and CP15 VA to PA operations - */ -#define XPM_EVENT_DATA_TLBREFILL 0x05 - -/* - * Data read architecturally executed. Counts the number of data read - * instructions accepted by the Load Store Unit. This includes counting the - * speculative and aborted LDR/LDM, as well as the reads due to the SWP - * instructions - */ -#define XPM_EVENT_DATA_READS 0x06 - -/* - * Data write architecturally executed. Counts the number of data write - * instructions accepted by the Load Store Unit. This includes counting the - * speculative and aborted STR/STM, as well as the writes due to the SWP - * instructions - */ -#define XPM_EVENT_DATA_WRITE 0x07 - -/* Exception taken. Counts the number of exceptions architecturally taken.*/ -#define XPM_EVENT_EXCEPTION 0x09 - -/* Exception return architecturally executed.*/ -#define XPM_EVENT_EXCEPRETURN 0x0A - -/* - * Change to ContextID retired. Counts the number of instructions - * architecturally executed writing into the ContextID Register - */ -#define XPM_EVENT_CHANGECONTEXT 0x0B - -/* - * Software change of PC, except by an exception, architecturally executed. - * Count the number of PC changes architecturally executed, excluding the PC - * changes due to taken exceptions - */ -#define XPM_EVENT_SW_CHANGEPC 0x0C - -/* - * Immediate branch architecturally executed (taken or not taken). This includes - * the branches which are flushed due to a previous load/store which aborts - * late - */ -#define XPM_EVENT_IMMEDBRANCH 0x0D - -/* - * Unaligned access architecturally executed. Counts the number of aborted - * unaligned accessed architecturally executed, and the number of not-aborted - * unaligned accesses, including the speculative ones - */ -#define XPM_EVENT_UNALIGNEDACCESS 0x0F - -/* - * Branch mispredicted/not predicted. Counts the number of mispredicted or - * not-predicted branches executed. This includes the branches which are flushed - * due to a previous load/store which aborts late - */ -#define XPM_EVENT_BRANCHMISS 0x10 - -/* - * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This - * event is not exported on the PMUEVENT bus - */ -#define XPM_EVENT_CLOCKCYCLES 0x11 - -/* - * Branches or other change in program flow that could have been predicted by - * the branch prediction resources of the processor. This includes the branches - * which are flushed due to a previous load/store which aborts late - */ -#define XPM_EVENT_BRANCHPREDICT 0x12 - -/* - * Java bytecode execute. Counts the number of Java bytecodes being decoded, - * including speculative ones - */ -#define XPM_EVENT_JAVABYTECODE 0x40 - -/* - * Software Java bytecode executed. Counts the number of software java bytecodes - * being decoded, including speculative ones - */ -#define XPM_EVENT_SWJAVABYTECODE 0x41 - -/* - * Jazelle backward branches executed. Counts the number of Jazelle taken - * branches being executed. This includes the branches which are flushed due - * to a previous load/store which aborts late - */ -#define XPM_EVENT_JAVABACKBRANCH 0x42 - -/* - * Coherent linefill miss Counts the number of coherent linefill requests - * performed by the Cortex-A9 processor which also miss in all the other - * Cortex-A9 processors, meaning that the request is sent to the external - * memory - */ -#define XPM_EVENT_COHERLINEMISS 0x50 - -/* - * Coherent linefill hit. Counts the number of coherent linefill requests - * performed by the Cortex-A9 processor which hit in another Cortex-A9 - * processor, meaning that the linefill data is fetched directly from the - * relevant Cortex-A9 cache - */ -#define XPM_EVENT_COHERLINEHIT 0x51 - -/* - * Instruction cache dependent stall cycles. Counts the number of cycles where - * the processor is ready to accept new instructions, but does not receive any - * due to the instruction side not being able to provide any and the - * instruction cache is currently performing at least one linefill - */ -#define XPM_EVENT_INSTRSTALL 0x60 - -/* - * Data cache dependent stall cycles. Counts the number of cycles where the core - * has some instructions that it cannot issue to any pipeline, and the Load - * Store unit has at least one pending linefill request, and no pending - */ -#define XPM_EVENT_DATASTALL 0x61 - -/* - * Main TLB miss stall cycles. Counts the number of cycles where the processor - * is stalled waiting for the completion of translation table walks from the - * main TLB. The processor stalls can be due to the instruction side not being - * able to provide the instructions, or to the data side not being able to - * provide the necessary data, due to them waiting for the main TLB translation - * table walk to complete - */ -#define XPM_EVENT_MAINTLBSTALL 0x62 - -/* - * Counts the number of STREX instructions architecturally executed and - * passed - */ -#define XPM_EVENT_STREXPASS 0x63 - -/* - * Counts the number of STREX instructions architecturally executed and - * failed - */ -#define XPM_EVENT_STREXFAIL 0x64 - -/* - * Data eviction. Counts the number of eviction requests due to a linefill in - * the data cache - */ -#define XPM_EVENT_DATAEVICT 0x65 - -/* - * Counts the number of cycles where the issue stage does not dispatch any - * instruction because it is empty or cannot dispatch any instructions - */ -#define XPM_EVENT_NODISPATCH 0x66 - -/* - * Counts the number of cycles where the issue stage is empty - */ -#define XPM_EVENT_ISSUEEMPTY 0x67 - -/* - * Counts the number of instructions going through the Register Renaming stage. - * This number is an approximate number of the total number of instructions - * speculatively executed, and even more approximate of the total number of - * instructions architecturally executed. The approximation depends mainly on - * the branch misprediction rate. - * The renaming stage can handle two instructions in the same cycle so the event - * is two bits long: - * - b00 no instructions renamed - * - b01 one instruction renamed - * - b10 two instructions renamed - */ -#define XPM_EVENT_INSTRRENAME 0x68 - -/* - * Counts the number of procedure returns whose condition codes do not fail, - * excluding all returns from exception. This count includes procedure returns - * which are flushed due to a previous load/store which aborts late. - * Only the following instructions are reported: - * - BX R14 - * - MOV PC LR - * - POP {..,pc} - * - LDR pc,[sp],#offset - * The following instructions are not reported: - * - LDMIA R9!,{..,PC} (ThumbEE state only) - * - LDR PC,[R9],#offset (ThumbEE state only) - * - BX R0 (Rm != R14) - * - MOV PC,R0 (Rm != R14) - * - LDM SP,{...,PC} (writeback not specified) - * - LDR PC,[SP,#offset] (wrong addressing mode) - */ -#define XPM_EVENT_PREDICTFUNCRET 0x6E - -/* - * Counts the number of instructions being executed in the main execution - * pipeline of the processor, the multiply pipeline and arithmetic logic unit - * pipeline. The counted instructions are still speculative - */ -#define XPM_EVENT_MAINEXEC 0x70 - -/* - * Counts the number of instructions being executed in the processor second - * execution pipeline (ALU). The counted instructions are still speculative - */ -#define XPM_EVENT_SECEXEC 0x71 - -/* - * Counts the number of instructions being executed in the Load/Store unit. The - * counted instructions are still speculative - */ -#define XPM_EVENT_LDRSTR 0x72 - -/* - * Counts the number of Floating-point instructions going through the Register - * Rename stage. Instructions are still speculative in this stage. - *Two floating-point instructions can be renamed in the same cycle so the event - * is two bitslong: - *0b00 no floating-point instruction renamed - *0b01 one floating-point instruction renamed - *0b10 two floating-point instructions renamed - */ -#define XPM_EVENT_FLOATRENAME 0x73 - -/* - * Counts the number of Neon instructions going through the Register Rename - * stage.Instructions are still speculative in this stage. - * Two NEON instructions can be renamed in the same cycle so the event is two - * bits long: - *0b00 no NEON instruction renamed - *0b01 one NEON instruction renamed - *0b10 two NEON instructions renamed - */ -#define XPM_EVENT_NEONRENAME 0x74 - -/* - * Counts the number of cycles where the processor is stalled because PLD slots - * are all full - */ -#define XPM_EVENT_PLDSTALL 0x80 - -/* - * Counts the number of cycles when the processor is stalled and the data side - * is stalled too because it is full and executing writes to the external - * memory - */ -#define XPM_EVENT_WRITESTALL 0x81 - -/* - * Counts the number of stall cycles due to main TLB misses on requests issued - * by the instruction side - */ -#define XPM_EVENT_INSTRTLBSTALL 0x82 - -/* - * Counts the number of stall cycles due to main TLB misses on requests issued - * by the data side - */ -#define XPM_EVENT_DATATLBSTALL 0x83 - -/* - * Counts the number of stall cycles due to micro TLB misses on the instruction - * side. This event does not include main TLB miss stall cycles that are already - * counted in the corresponding main TLB event - */ -#define XPM_EVENT_INSTR_uTLBSTALL 0x84 - -/* - * Counts the number of stall cycles due to micro TLB misses on the data side. - * This event does not include main TLB miss stall cycles that are already - * counted in the corresponding main TLB event - */ -#define XPM_EVENT_DATA_uTLBSTALL 0x85 - -/* - * Counts the number of stall cycles because of the execution of a DMB memory - * barrier. This includes all DMB instructions being executed, even - * speculatively - */ -#define XPM_EVENT_DMB_STALL 0x86 - -/* - * Counts the number of cycles during which the integer core clock is enabled - */ -#define XPM_EVENT_INT_CLKEN 0x8A - -/* - * Counts the number of cycles during which the Data Engine clock is enabled - */ -#define XPM_EVENT_DE_CLKEN 0x8B - -/* - * Counts the number of ISB instructions architecturally executed - */ -#define XPM_EVENT_INSTRISB 0x90 - -/* - * Counts the number of DSB instructions architecturally executed - */ -#define XPM_EVENT_INSTRDSB 0x91 - -/* - * Counts the number of DMB instructions speculatively executed - */ -#define XPM_EVENT_INSTRDMB 0x92 - -/* - * Counts the number of external interrupts executed by the processor - */ -#define XPM_EVENT_EXTINT 0x93 - -/* - * PLE cache line request completed - */ -#define XPM_EVENT_PLE_LRC 0xA0 - -/* - * PLE cache line request skipped - */ -#define XPM_EVENT_PLE_LRS 0xA1 - -/* - * PLE FIFO flush - */ -#define XPM_EVENT_PLE_FLUSH 0xA2 - -/* - * PLE request complete - */ -#define XPM_EVENT_PLE_CMPL 0xA3 - -/* - * PLE FIFO overflow - */ -#define XPM_EVENT_PLE_OVFL 0xA4 - -/* - * PLE request programmed - */ -#define XPM_EVENT_PLE_PROG 0xA5 - -/* - * The following constants define the configurations for Cortex-A9 Performance - * Monitor Events. Each configuration configures the event counters for a set - * of events. - * ----------------------------------------------- - * Config PmCtr0... PmCtr5 - * ----------------------------------------------- - * XPM_CNTRCFG1 { XPM_EVENT_SOFTINCR, - * XPM_EVENT_INSRFETCH_CACHEREFILL, - * XPM_EVENT_INSTRFECT_TLBREFILL, - * XPM_EVENT_DATA_CACHEREFILL, - * XPM_EVENT_DATA_CACHEACCESS, - * XPM_EVENT_DATA_TLBREFILL } - * - * XPM_CNTRCFG2 { XPM_EVENT_DATA_READS, - * XPM_EVENT_DATA_WRITE, - * XPM_EVENT_EXCEPTION, - * XPM_EVENT_EXCEPRETURN, - * XPM_EVENT_CHANGECONTEXT, - * XPM_EVENT_SW_CHANGEPC } - * - * XPM_CNTRCFG3 { XPM_EVENT_IMMEDBRANCH, - * XPM_EVENT_UNALIGNEDACCESS, - * XPM_EVENT_BRANCHMISS, - * XPM_EVENT_CLOCKCYCLES, - * XPM_EVENT_BRANCHPREDICT, - * XPM_EVENT_JAVABYTECODE } - * - * XPM_CNTRCFG4 { XPM_EVENT_SWJAVABYTECODE, - * XPM_EVENT_JAVABACKBRANCH, - * XPM_EVENT_COHERLINEMISS, - * XPM_EVENT_COHERLINEHIT, - * XPM_EVENT_INSTRSTALL, - * XPM_EVENT_DATASTALL } - * - * XPM_CNTRCFG5 { XPM_EVENT_MAINTLBSTALL, - * XPM_EVENT_STREXPASS, - * XPM_EVENT_STREXFAIL, - * XPM_EVENT_DATAEVICT, - * XPM_EVENT_NODISPATCH, - * XPM_EVENT_ISSUEEMPTY } - * - * XPM_CNTRCFG6 { XPM_EVENT_INSTRRENAME, - * XPM_EVENT_PREDICTFUNCRET, - * XPM_EVENT_MAINEXEC, - * XPM_EVENT_SECEXEC, - * XPM_EVENT_LDRSTR, - * XPM_EVENT_FLOATRENAME } - * - * XPM_CNTRCFG7 { XPM_EVENT_NEONRENAME, - * XPM_EVENT_PLDSTALL, - * XPM_EVENT_WRITESTALL, - * XPM_EVENT_INSTRTLBSTALL, - * XPM_EVENT_DATATLBSTALL, - * XPM_EVENT_INSTR_uTLBSTALL } - * - * XPM_CNTRCFG8 { XPM_EVENT_DATA_uTLBSTALL, - * XPM_EVENT_DMB_STALL, - * XPM_EVENT_INT_CLKEN, - * XPM_EVENT_DE_CLKEN, - * XPM_EVENT_INSTRISB, - * XPM_EVENT_INSTRDSB } - * - * XPM_CNTRCFG9 { XPM_EVENT_INSTRDMB, - * XPM_EVENT_EXTINT, - * XPM_EVENT_PLE_LRC, - * XPM_EVENT_PLE_LRS, - * XPM_EVENT_PLE_FLUSH, - * XPM_EVENT_PLE_CMPL } - * - * XPM_CNTRCFG10 { XPM_EVENT_PLE_OVFL, - * XPM_EVENT_PLE_PROG, - * XPM_EVENT_PLE_LRC, - * XPM_EVENT_PLE_LRS, - * XPM_EVENT_PLE_FLUSH, - * XPM_EVENT_PLE_CMPL } - * - * XPM_CNTRCFG11 { XPM_EVENT_DATASTALL, - * XPM_EVENT_INSRFETCH_CACHEREFILL, - * XPM_EVENT_INSTRFECT_TLBREFILL, - * XPM_EVENT_DATA_CACHEREFILL, - * XPM_EVENT_DATA_CACHEACCESS, - * XPM_EVENT_DATA_TLBREFILL } - */ -#define XPM_CNTRCFG1 0 -#define XPM_CNTRCFG2 1 -#define XPM_CNTRCFG3 2 -#define XPM_CNTRCFG4 3 -#define XPM_CNTRCFG5 4 -#define XPM_CNTRCFG6 5 -#define XPM_CNTRCFG7 6 -#define XPM_CNTRCFG8 7 -#define XPM_CNTRCFG9 8 -#define XPM_CNTRCFG10 9 -#define XPM_CNTRCFG11 10 - -/**************************** Type Definitions ******************************/ - -/***************** Macros (Inline Functions) Definitions ********************/ - -/************************** Variable Definitions ****************************/ - -/************************** Function Prototypes *****************************/ - -/* Interface fuctions to access perfromance counters from abstraction layer */ -void Xpm_SetEvents(int PmcrCfg); -void Xpm_GetEventCounters(u32 *PmCtrValue); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xpseudo_asm.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xpseudo_asm.h deleted file mode 100644 index e44a79954063122c428275d4cc0d0e8ed1bd3252..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xpseudo_asm.h +++ /dev/null @@ -1,64 +0,0 @@ -/******************************************************************************* -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -*******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xpseudo_asm.h -* -* This header file contains macros for using inline assembler code. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a ecm 10/18/09 First release -* 3.04a sdm 01/02/12 Remove redundant dsb in mcr instruction. -* </pre> -* -******************************************************************************/ -#include "xreg_cortexa9.h" -#ifdef __GNUC__ - #include "xpseudo_asm_gcc.h" -#elif defined (__ICCARM__) - #include "xpseudo_asm_iccarm.h" -#else - #include "xpseudo_asm_rvct.h" -#endif diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h deleted file mode 100644 index 52fac3b3481d0c6ce0f410384089549cedfcf2b2..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h +++ /dev/null @@ -1,183 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xpseudo_asm_gcc.h -* -* This header file contains macros for using inline assembler code. It is -* written specifically for the GNU compiler. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- -------- -------- ----------------------------------------------- -* 1.00a ecm/sdm 10/28/09 First release -* </pre> -* -******************************************************************************/ - -#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */ -#define XPSEUDO_ASM_GCC_H /* by using protection macros */ - -/***************************** Include Files ********************************/ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/************************** Constant Definitions ****************************/ - -/**************************** Type Definitions ******************************/ - -/***************** Macros (Inline Functions) Definitions ********************/ - -/* necessary for pre-processor */ -#define stringify(s) tostring(s) -#define tostring(s) #s - -/* pseudo assembler instructions */ -#define mfcpsr() ({unsigned int rval; \ - __asm__ __volatile__(\ - "mrs %0, cpsr\n"\ - : "=r" (rval)\ - );\ - rval;\ - }) - -#define mtcpsr(v) __asm__ __volatile__(\ - "msr cpsr,%0\n"\ - : : "r" (v)\ - ) - -#define cpsiei() __asm__ __volatile__("cpsie i\n") -#define cpsidi() __asm__ __volatile__("cpsid i\n") - -#define cpsief() __asm__ __volatile__("cpsie f\n") -#define cpsidf() __asm__ __volatile__("cpsid f\n") - - - -#define mtgpr(rn, v) __asm__ __volatile__(\ - "mov r" stringify(rn) ", %0 \n"\ - : : "r" (v)\ - ) - -#define mfgpr(rn) ({unsigned int rval; \ - __asm__ __volatile__(\ - "mov %0,r" stringify(rn) "\n"\ - : "=r" (rval)\ - );\ - rval;\ - }) - -/* memory synchronization operations */ - -/* Instruction Synchronization Barrier */ -#define isb() __asm__ __volatile__ ("isb" : : : "memory") - -/* Data Synchronization Barrier */ -#define dsb() __asm__ __volatile__ ("dsb" : : : "memory") - -/* Data Memory Barrier */ -#define dmb() __asm__ __volatile__ ("dmb" : : : "memory") - - -/* Memory Operations */ -#define ldr(adr) ({unsigned long rval; \ - __asm__ __volatile__(\ - "ldr %0,[%1]"\ - : "=r" (rval) : "r" (adr)\ - );\ - rval;\ - }) - -#define ldrb(adr) ({unsigned char rval; \ - __asm__ __volatile__(\ - "ldrb %0,[%1]"\ - : "=r" (rval) : "r" (adr)\ - );\ - rval;\ - }) - -#define str(adr, val) __asm__ __volatile__(\ - "str %0,[%1]\n"\ - : : "r" (val), "r" (adr)\ - ) - -#define strb(adr, val) __asm__ __volatile__(\ - "strb %0,[%1]\n"\ - : : "r" (val), "r" (adr)\ - ) - -/* Count leading zeroes (clz) */ -#define clz(arg) ({unsigned char rval; \ - __asm__ __volatile__(\ - "clz %0,%1"\ - : "=r" (rval) : "r" (arg)\ - );\ - rval;\ - }) - -/* CP15 operations */ -#define mtcp(rn, v) __asm__ __volatile__(\ - "mcr " rn "\n"\ - : : "r" (v)\ - ); - -#define mfcp(rn) ({unsigned int rval; \ - __asm__ __volatile__(\ - "mrc " rn "\n"\ - : "=r" (rval)\ - );\ - rval;\ - }) - -/************************** Variable Definitions ****************************/ - -/************************** Function Prototypes *****************************/ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* XPSEUDO_ASM_GCC_H */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xqspips.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xqspips.h deleted file mode 100644 index 3114f5b57e3900496af6933b9e276b3b11179c00..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xqspips.h +++ /dev/null @@ -1,790 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xqspips.h -* -* This file contains the implementation of the XQspiPs driver. It supports only -* master mode. User documentation for the driver functions is contained in this -* file in the form of comment blocks at the front of each function. -* -* A QSPI device connects to an QSPI bus through a 4-wire serial interface. -* The QSPI bus is a full-duplex, synchronous bus that facilitates communication -* between one master and one slave. The device is always full-duplex, -* which means that for every byte sent, one is received, and vice-versa. -* The master controls the clock, so it can regulate when it wants to -* send or receive data. The slave is under control of the master, it must -* respond quickly since it has no control of the clock and must send/receive -* data as fast or as slow as the master does. -* -* <b> Linear Mode </b> -* The Linear Quad-SPI Controller extends the existing Quad-SPI Controller’s -* functionality by adding a linear addressing scheme that allows the SPI flash -* memory subsystem to behave like a typical ROM device. The new feature hides -* the normal SPI protocol from a master reading from the SPI flash memory. The -* feature improves both the user friendliness and the overall read memory -* throughput over that of the current Quad-SPI Controller by lessening the -* amount of software overheads required and by the use of the faster AXI -* interface. -* -* <b>Initialization & Configuration</b> -* -* The XQspiPs_Config structure is used by the driver to configure itself. This -* configuration structure is typically created by the tool-chain based on HW -* build properties. -* -* To support multiple runtime loading and initialization strategies employed by -* various operating systems, the driver instance can be initialized in the -* following way: -* - XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find -* static configuration structure defined in xqspips_g.c. This is setup -* by the tools. For some operating systems the config structure will be -* initialized by the software and this call is not needed. -* - XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a -* configuration structure provided by the caller. If running in a system -* with address translation, the provided virtual memory base address -* replaces the physical address present in the configuration structure. -* -* <b>Multiple Masters</b> -* -* More than one master can exist, but arbitration is the responsibility of -* the higher layer software. The device driver does not perform any type of -* arbitration. -* -* <b>Modes of Operation</b> -* -* There are four modes to perform a data transfer and the selection of a mode -* is based on Chip Select(CS) and Start. These two options individually, can -* be controlled either by software(Manual) or hardware(Auto). -* - Auto CS: Chip select is automatically asserted as soon as the first word -* is written into the TXFIFO and de asserted when the TXFIFO becomes -* empty -* - Manual CS: Software must assert and de assert CS. -* - Auto Start: Data transmission starts as soon as there is data in the -* TXFIFO and stalls when the TXFIFO is empty -* - Manual Start: Software must start data transmission at the beginning of -* the transaction or whenever the TXFIFO has become empty -* -* The preferred combination is Manual CS and Auto Start. -* In this combination, the software asserts CS before loading any data into -* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it -* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the -* data is available. If no further data, software disables CS. -* -* Risks/challenges of other combinations: -* - Manual CS and Manual Start: Manual Start bit should be set after each -* TXFIFO write otherwise there could be a race condition where the TXFIFO -* becomes empty before the new word is written. In that case the -* transmission stops. -* - Auto CS with Manual or Auto Start: It is very difficult for software to -* keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted. -* This results in a single transaction to be split into multiple pieces each -* with its own chip select. This will result in garbage data to be sent. -* -* <b>Interrupts</b> -* -* The user must connect the interrupt handler of the driver, -* XQspiPs_InterruptHandler, to an interrupt system such that it will be -* called when an interrupt occurs. This function does not save and restore -* the processor context such that the user must provide this processing. -* -* The driver handles the following interrupts: -* - Data Transmit Register/FIFO Underflow -* - Data Receive Register/FIFO Not Empty -* - Data Transmit Register/FIFO Overwater -* - Data Receive Register/FIFO Overrun -* -* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the -* QSPI device has transmitted the data available to transmit, and now its data -* register and FIFO is ready to accept more data. The driver uses this -* interrupt to indicate progress while sending data. The driver may have -* more data to send, in which case the data transmit register and FIFO is -* filled for subsequent transmission. When this interrupt arrives and all -* the data has been sent, the driver invokes the status callback with a -* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that -* all data has been sent. -* -* The Data Transmit Register/FIFO Underflow interrupt -- indicates that, -* as slave, the QSPI device was required to transmit but there was no data -* available to transmit in the transmit register (or FIFO). This may not -* be an error if the master is not expecting data. But in the case where -* the master is expecting data, this serves as a notification of such a -* condition. The driver reports this condition to the upper layer -* software through the status handler. -* -* The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI -* device received data and subsequently dropped the data because the data -* receive register and FIFO was full. The driver reports this condition to the -* upper layer software through the status handler. This likely indicates a -* problem with the higher layer protocol, or a problem with the slave -* performance. -* -* -* <b>Polled Operation</b> -* -* Transfer in polled mode is supported through a separate interface function -* XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode, -* this function blocks until all data has been sent/received. -* -* <b>Device Busy</b> -* -* Some operations are disallowed when the device is busy. The driver tracks -* whether a device is busy. The device is considered busy when a data transfer -* request is outstanding, and is considered not busy only when that transfer -* completes (or is aborted with a mode fault error). -* -* <b>Device Configuration</b> -* -* The device can be configured in various ways during the FPGA implementation -* process. Configuration parameters are stored in the xqspips_g.c file or -* passed in via XQspiPs_CfgInitialize(). A table is defined where each entry -* contains configuration information for an QSPI device, including the base -* address for the device. -* -* <b>RTOS Independence</b> -* -* This driver is intended to be RTOS and processor independent. It works with -* physical addresses only. Any needs for dynamic memory management, threads or -* thread mutual exclusion, virtual memory, or cache control must be satisfied -* by the layer above this driver. -* -* NOTE: This driver was always tested with endianess set to little-endian. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- ----------------------------------------------- -* 1.00a sdm 11/25/10 First release, based on the PS SPI driver. -* 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters -* in xparameters.h -* 2.00a kka 07/25/12 Added a few register defines for CR 670297 -* Removed code related to mode fault for CR 671468 -* The XQspiPs_SetSlaveSelect has been modified to remove -* the argument of the slave select as the QSPI controller -* only supports one slave. -* XQspiPs_GetSlaveSelect API has been removed -* Added a flag ShiftReadData to the instance structure -*. and is used in the XQspiPs_GetReadData API. -* The ShiftReadData Flag indicates whether the data -* read from the Rx FIFO needs to be shifted -* in cases where the data is less than 4 bytes -* Removed the selection for the following options: -* Master mode (XQSPIPS_MASTER_OPTION) and -* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option -* as the QSPI driver supports the Master mode -* and Flash Interface mode and doesnot support -* Slave mode or the legacy mode. -* Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer -* APIs so that the last argument (IsInst) specifying whether -* it is instruction or data has been removed. The first byte -* in the SendBufPtr argument of these APIs specify the -* instruction to be sent to the Flash Device. -* This version of the driver fixes CRs 670197/663787/ -* 670297/671468. -* Added the option for setting the Holdb_dr bit in the -* configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION -* is the option to be used for setting this bit in the -* configuration register. -* The XQspiPs_PolledTransfer function has been updated -* to fill the data to fifo depth. -* 2.01a sg 02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ. -* Added macros for Set/Get Rx Watermark. Changed QSPI -* Enable/Disable macro argument from BaseAddress to -* Instance Pointer. Added DelayNss argument to SetDelays -* and GetDelays API's. -* Created macros XQspiPs_IsManualStart and -* XQspiPs_IsManualChipSelect. -* Changed QSPI transfer logic for polled and interrupt -* modes to be based on filled tx fifo count and receive -* based on it. RXNEMPTY interrupt is not used. -* Added assertions to XQspiPs_LqspiRead function. -* SetDelays and GetDelays API's include DelayNss parameter. -* Added defines for DelayNss,Rx Watermark,Interrupts -* which need write to clear. Removed Read zeros mask from -* LQSPI Config register. Renamed Fixed burst error to -* data FSM error in LQSPI Status register. -* -* 2.02a hk 05/07/13 Added ConnectionMode to config structure. -* Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel -* Added enable and disable to the XQspiPs_LqspiRead() function -* Removed XQspi_Reset() in Set_Options() function when -* LQSPI_MODE_OPTION is set. -* Added instructions for bank selection, die erase and -* flag status register to the flash instruction table -* Handling for instructions not in flash instruction -* table added. Checking for Tx FIFO empty when switching from -* TXD1/2/3 to TXD0 added. If WRSR instruction is sent with -* byte count 3 (spansion), instruction size and TXD register -* changed accordingly. CR# 712502 and 703869. -* Added prefix to constant definitions for ConnectionMode -* Added (#ifdef linear base address) in the Linear read function. -* Changed XPAR_XQSPIPS_0_LINEAR_BASEADDR to -* XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in -* XQspiPs_LqspiRead function. Fix for CR#718141. -* -* 2.03a hk 09/17/13 Modified polled and interrupt transfers to make use of -* thresholds. This is to improve performance. -* Added API's for QSPI reset and -* linear mode initialization for boot. -* Added RX and TX threshold reset to one in XQspiPs_Abort. -* Added RX threshold reset(1) after transfer in polled and -* interrupt transfers. Made changes to make sure threshold -* change is done only when no transfer is in progress. -* Updated linear init API for parallel and stacked modes. -* CR#737760. -* -* </pre> -* -******************************************************************************/ -#ifndef XQSPIPS_H /* prevent circular inclusions */ -#define XQSPIPS_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xstatus.h" -#include "xqspips_hw.h" -#include <string.h> - -/************************** Constant Definitions *****************************/ - -/** @name Configuration options - * - * The following options are supported to enable/disable certain features of - * an QSPI device. Each of the options is a bit mask, so more than one may be - * specified. - * - * - * The <b>Active Low Clock option</b> configures the device's clock polarity. - * Setting this option means the clock is active low and the SCK signal idles - * high. By default, the clock is active high and SCK idles low. - * - * The <b>Clock Phase option</b> configures the QSPI device for one of two - * transfer formats. A clock phase of 0, the default, means data is valid on - * the first SCK edge (rising or falling) after the slave select (SS) signal - * has been asserted. A clock phase of 1 means data is valid on the second SCK - * edge (rising or falling) after SS has been asserted. - * - * - * The <b>QSPI Force Slave Select option</b> is used to enable manual control of - * the slave select signal. - * 0: The SPI_SS signal is controlled by the QSPI controller during - * transfers. (Default) - * 1: The SPI_SS signal is forced active (driven low) regardless of any - * transfers in progress. - * - * NOTE: The driver will handle setting and clearing the Slave Select when - * the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the - * QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the - * processor cannot empty and refill the FIFOs before the TX FIFO is empty - * When the QSPI hardware is controlling the Slave Select signals, this - * will cause slave to be de-selected and terminate the transfer. - * - * The <b>Manual Start option</b> is used to enable manual control of - * the Start command to perform data transfer. - * 0: The Start command is controlled by the QSPI controller during - * transfers(Default). Data transmission starts as soon as there is data in - * the TXFIFO and stalls when the TXFIFO is empty - * 1: The Start command must be issued by software to perform data transfer. - * Bit 15 of Configuration register is used to issue Start command. This bit - * must be set whenever TXFIFO is filled with new data. - * - * NOTE: The driver will set the Manual Start Enable bit in Configuration - * Register, if Manual Start option is selected. Software will issue - * Manual Start command whenever TXFIFO is filled with data. When there is - * no further data, driver will clear the Manual Start Enable bit. - * - * @{ - */ -#define XQSPIPS_CLK_ACTIVE_LOW_OPTION 0x2 /**< Active Low Clock option */ -#define XQSPIPS_CLK_PHASE_1_OPTION 0x4 /**< Clock Phase one option */ -#define XQSPIPS_FORCE_SSELECT_OPTION 0x10 /**< Force Slave Select */ -#define XQSPIPS_MANUAL_START_OPTION 0x20 /**< Manual Start enable */ -#define XQSPIPS_LQSPI_MODE_OPTION 0x80 /**< Linear QPSI mode */ -#define XQSPIPS_HOLD_B_DRIVE_OPTION 0x100 /**< Drive HOLD_B Pin */ -/*@}*/ - - -/** @name QSPI Clock Prescaler options - * The QSPI Clock Prescaler Configuration bits are used to program master mode - * bit rate. The bit rate can be programmed in divide-by-two decrements from - * pclk/2 to pclk/256. - * - * @{ - */ -#define XQSPIPS_CLK_PRESCALE_2 0x00 /**< PCLK/2 Prescaler */ -#define XQSPIPS_CLK_PRESCALE_4 0x01 /**< PCLK/4 Prescaler */ -#define XQSPIPS_CLK_PRESCALE_8 0x02 /**< PCLK/8 Prescaler */ -#define XQSPIPS_CLK_PRESCALE_16 0x03 /**< PCLK/16 Prescaler */ -#define XQSPIPS_CLK_PRESCALE_32 0x04 /**< PCLK/32 Prescaler */ -#define XQSPIPS_CLK_PRESCALE_64 0x05 /**< PCLK/64 Prescaler */ -#define XQSPIPS_CLK_PRESCALE_128 0x06 /**< PCLK/128 Prescaler */ -#define XQSPIPS_CLK_PRESCALE_256 0x07 /**< PCLK/256 Prescaler */ - -/*@}*/ - - -/** @name Callback events - * - * These constants specify the handler events that are passed to - * a handler from the driver. These constants are not bit masks such that - * only one will be passed at a time to the handler. - * - * @{ - */ -#define XQSPIPS_EVENT_TRANSFER_DONE 2 /**< Transfer done */ -#define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */ -#define XQSPIPS_EVENT_RECEIVE_OVERRUN 4 /**< Receive data loss because - RX FIFO full */ -/*@}*/ - -/** @name Flash commands - * - * The following constants define most of the commands supported by flash - * devices. Users can add more commands supported by the flash devices - * - * @{ - */ -#define XQSPIPS_FLASH_OPCODE_WRSR 0x01 /* Write status register */ -#define XQSPIPS_FLASH_OPCODE_PP 0x02 /* Page program */ -#define XQSPIPS_FLASH_OPCODE_NORM_READ 0x03 /* Normal read data bytes */ -#define XQSPIPS_FLASH_OPCODE_WRDS 0x04 /* Write disable */ -#define XQSPIPS_FLASH_OPCODE_RDSR1 0x05 /* Read status register 1 */ -#define XQSPIPS_FLASH_OPCODE_WREN 0x06 /* Write enable */ -#define XQSPIPS_FLASH_OPCODE_FAST_READ 0x0B /* Fast read data bytes */ -#define XQSPIPS_FLASH_OPCODE_BE_4K 0x20 /* Erase 4KiB block */ -#define XQSPIPS_FLASH_OPCODE_RDSR2 0x35 /* Read status register 2 */ -#define XQSPIPS_FLASH_OPCODE_DUAL_READ 0x3B /* Dual read data bytes */ -#define XQSPIPS_FLASH_OPCODE_BE_32K 0x52 /* Erase 32KiB block */ -#define XQSPIPS_FLASH_OPCODE_QUAD_READ 0x6B /* Quad read data bytes */ -#define XQSPIPS_FLASH_OPCODE_ERASE_SUS 0x75 /* Erase suspend */ -#define XQSPIPS_FLASH_OPCODE_ERASE_RES 0x7A /* Erase resume */ -#define XQSPIPS_FLASH_OPCODE_RDID 0x9F /* Read JEDEC ID */ -#define XQSPIPS_FLASH_OPCODE_BE 0xC7 /* Erase whole flash block */ -#define XQSPIPS_FLASH_OPCODE_SE 0xD8 /* Sector erase (usually 64KB)*/ -#define XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */ -#define XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */ -#define XQSPIPS_FLASH_OPCODE_BRWR 0x17 /* Bank Register Write */ -#define XQSPIPS_FLASH_OPCODE_BRRD 0x16 /* Bank Register Read */ -/* Extende Address Register Write - Micron's equivalent of Bank Register */ -#define XQSPIPS_FLASH_OPCODE_EARWR 0xC5 -/* Extende Address Register Read - Micron's equivalent of Bank Register */ -#define XQSPIPS_FLASH_OPCODE_EARRD 0xC8 -#define XQSPIPS_FLASH_OPCODE_DIE_ERASE 0xC4 -#define XQSPIPS_FLASH_OPCODE_READ_FLAG_SR 0x70 -#define XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR 0x50 -#define XQSPIPS_FLASH_OPCODE_READ_LOCK_REG 0xE8 /* Lock register Read */ -#define XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG 0xE5 /* Lock Register Write */ - -/*@}*/ - -/** @name Instruction size - * - * The following constants define numbers 1 to 4. - * Used to identify whether TXD0,1,2 or 3 is to be used. - * - * @{ - */ -#define XQSPIPS_SIZE_ONE 1 -#define XQSPIPS_SIZE_TWO 2 -#define XQSPIPS_SIZE_THREE 3 -#define XQSPIPS_SIZE_FOUR 4 - -/*@}*/ - -/** @name ConnectionMode - * - * The following constants are the possible values of ConnectionMode in - * Config structure. - * - * @{ - */ -#define XQSPIPS_CONNECTION_MODE_SINGLE 0 -#define XQSPIPS_CONNECTION_MODE_STACKED 1 -#define XQSPIPS_CONNECTION_MODE_PARALLEL 2 - -/*@}*/ - -/** @name FIFO threshold value - * - * This is the Rx FIFO threshold (in words) that was found to be most - * optimal in terms of performance - * - * @{ - */ -#define XQSPIPS_RXFIFO_THRESHOLD_OPT 32 - -/*@}*/ - -/**************************** Type Definitions *******************************/ -/** - * The handler data type allows the user to define a callback function to - * handle the asynchronous processing for the QSPI device. The application - * using this driver is expected to define a handler of this type to support - * interrupt driven mode. The handler executes in an interrupt context, so - * only minimal processing should be performed. - * - * @param CallBackRef is the callback reference passed in by the upper - * layer when setting the callback functions, and passed back to - * the upper layer when the callback is invoked. Its type is - * not important to the driver, so it is a void pointer. - * @param StatusEvent holds one or more status events that have occurred. - * See the XQspiPs_SetStatusHandler() for details on the status - * events that can be passed in the callback. - * @param ByteCount indicates how many bytes of data were successfully - * transferred. This may be less than the number of bytes - * requested if the status event indicates an error. - */ -typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent, - unsigned ByteCount); - -/** - * This typedef contains configuration information for the device. - */ -typedef struct { - u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddress; /**< Base address of the device */ - u32 InputClockHz; /**< Input clock frequency */ - u8 ConnectionMode; /**< Single, Stacked and Parallel mode */ -} XQspiPs_Config; - -/** - * The XQspiPs driver instance data. The user is required to allocate a - * variable of this type for every QSPI device in the system. A pointer - * to a variable of this type is then passed to the driver API functions. - */ -typedef struct { - XQspiPs_Config Config; /**< Configuration structure */ - u32 IsReady; /**< Device is initialized and ready */ - - u8 *SendBufferPtr; /**< Buffer to send (state) */ - u8 *RecvBufferPtr; /**< Buffer to receive (state) */ - int RequestedBytes; /**< Number of bytes to transfer (state) */ - int RemainingBytes; /**< Number of bytes left to transfer(state) */ - u32 IsBusy; /**< A transfer is in progress (state) */ - XQspiPs_StatusHandler StatusHandler; - void *StatusRef; /**< Callback reference for status handler */ - u32 ShiftReadData; /**< Flag to indicate whether the data - * read from the Rx FIFO needs to be shifted - * in cases where the data is less than 4 - * bytes - */ -} XQspiPs; - -/***************** Macros (Inline Functions) Definitions *********************/ - -/****************************************************************************/ -/* -* -* Check in OptionsTable if Manual Start Option is enabled or disabled. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* -* @return -* - TRUE if option is set -* - FALSE if option is not set -* -* @note C-Style signature: -* u8 XQspiPs_IsManualStart(XQspiPs *InstancePtr); -* -*****************************************************************************/ -#define XQspiPs_IsManualStart(InstancePtr) \ - ((XQspiPs_GetOptions(InstancePtr) & \ - XQSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE) - -/****************************************************************************/ -/* -* -* Check in OptionsTable if Manual Chip Select Option is enabled or disabled. -* -* @param InstancePtr is a pointer to the XSpiPs instance. -* -* @return -* - TRUE if option is set -* - FALSE if option is not set -* -* @note C-Style signature: -* u8 XQspiPs_IsManualChipSelect(XQspiPs *InstancePtr); -* -*****************************************************************************/ -#define XQspiPs_IsManualChipSelect(InstancePtr) \ - ((XQspiPs_GetOptions(InstancePtr) & \ - XQSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE) - -/****************************************************************************/ -/** -* -* Set the contents of the slave idle count register. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* @param RegisterValue is the value to be written, valid values are -* 0-255. -* -* @return None -* -* @note -* C-Style signature: -* void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr, u32 RegisterValue) -* -*****************************************************************************/ -#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue) \ - XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ - XQSPIPS_SICR_OFFSET, (RegisterValue)) - -/****************************************************************************/ -/** -* -* Get the contents of the slave idle count register. Use the XQSPIPS_SICR_* -* constants defined in xqspips_hw.h to interpret the bit-mask returned. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* -* @return An 8-bit value representing Slave Idle Count. -* -* @note C-Style signature: -* u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr) -* -*****************************************************************************/ -#define XQspiPs_GetSlaveIdle(InstancePtr) \ - XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \ - XQSPIPS_SICR_OFFSET) - -/****************************************************************************/ -/** -* -* Set the contents of the transmit FIFO watermark register. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* @param RegisterValue is the value to be written, valid values are 1-63. -* -* @return None. -* -* @note -* C-Style signature: -* void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr, u32 RegisterValue) -* -*****************************************************************************/ -#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue) \ - XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ - XQSPIPS_TXWR_OFFSET, (RegisterValue)) - -/****************************************************************************/ -/** -* -* Get the contents of the transmit FIFO watermark register. -* Valid values are in the range 1-63. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* -* @return A 6-bit value representing Tx Watermark level. -* -* @note C-Style signature: -* u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr) -* -*****************************************************************************/ -#define XQspiPs_GetTXWatermark(InstancePtr) \ - XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET) - -/****************************************************************************/ -/** -* -* Set the contents of the receive FIFO watermark register. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* @param RegisterValue is the value to be written, valid values are 1-63. -* -* @return None. -* -* @note -* C-Style signature: -* void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr, u32 RegisterValue) -* -*****************************************************************************/ -#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue) \ - XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ - XQSPIPS_RXWR_OFFSET, (RegisterValue)) - -/****************************************************************************/ -/** -* -* Get the contents of the receive FIFO watermark register. -* Valid values are in the range 1-63. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* -* @return A 6-bit value representing Rx Watermark level. -* -* @note C-Style signature: -* u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr) -* -*****************************************************************************/ -#define XQspiPs_GetRXWatermark(InstancePtr) \ - XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET) - -/****************************************************************************/ -/** -* -* Enable the device and uninhibit master transactions. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* -* @return None. -* -* @note C-Style signature: -* void XQspiPs_Enable(XQspiPs *InstancePtr) -* -*****************************************************************************/ -#define XQspiPs_Enable(InstancePtr) \ - XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \ - XQSPIPS_ER_ENABLE_MASK) - -/****************************************************************************/ -/** -* -* Disable the device. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* -* @return None. -* -* @note C-Style signature: -* void XQspiPs_Disable(XQspiPs *InstancePtr) -* -*****************************************************************************/ -#define XQspiPs_Disable(InstancePtr) \ - XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0) - -/****************************************************************************/ -/** -* -* Set the contents of the Linear QSPI Configuration register. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* @param RegisterValue is the value to be written to the Linear QSPI -* configuration register. -* -* @return None. -* -* @note -* C-Style signature: -* void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr, -* u32 RegisterValue) -* -*****************************************************************************/ -#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue) \ - XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ - XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue)) - -/****************************************************************************/ -/** -* -* Get the contents of the Linear QSPI Configuration register. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* -* @return A 32-bit value representing the contents of the LQSPI Config -* register. -* -* @note C-Style signature: -* u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr) -* -*****************************************************************************/ -#define XQspiPs_GetLqspiConfigReg(InstancePtr) \ - XQspiPs_In32((InstancePtr->Config.BaseAddress) + \ - XQSPIPS_LQSPI_CR_OFFSET) - -/************************** Function Prototypes ******************************/ - -/* - * Initialization function, implemented in xqspips_sinit.c - */ -XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId); - -/* - * Functions implemented in xqspips.c - */ -int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config * Config, - u32 EffectiveAddr); -void XQspiPs_Reset(XQspiPs *InstancePtr); -void XQspiPs_Abort(XQspiPs *InstancePtr); - -int XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr, - unsigned ByteCount); -int XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr, - u8 *RecvBufPtr, unsigned ByteCount); -int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr, - u32 Address, unsigned ByteCount); - -int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr); - -void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef, - XQspiPs_StatusHandler FuncPtr); -void XQspiPs_InterruptHandler(void *InstancePtr); - -/* - * Functions for selftest, in xqspips_selftest.c - */ -int XQspiPs_SelfTest(XQspiPs *InstancePtr); - -/* - * Functions for options, in xqspips_options.c - */ -int XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options); -u32 XQspiPs_GetOptions(XQspiPs *InstancePtr); - -int XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler); -u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr); - -int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn, - u8 DelayAfter, u8 DelayInit); -void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn, - u8 *DelayAfter, u8 *DelayInit); -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xqspips_hw.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xqspips_hw.h deleted file mode 100644 index 8e77c75abcf174a3a3f59fa46b7dcda03659db6e..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xqspips_hw.h +++ /dev/null @@ -1,381 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xqspips_hw.h -* -* This header file contains the identifiers and basic HW access driver -* functions (or macros) that can be used to access the device. Other driver -* functions are defined in xqspips.h. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- ----------------------------------------------- -* 1.00 sdm 11/25/10 First release -* 2.00a ka 07/25/12 Added a few register defines for CR 670297 -* and removed some defines of reserved fields for -* CR 671468 -* Added define XQSPIPS_CR_HOLD_B_MASK for Holdb_dr -* bit in Configuration register. -* 2.01a sg 02/03/13 Added defines for DelayNss,Rx Watermark,Interrupts -* which need write to clear. Removed Read zeros mask from -* LQSPI Config register. -* 2.03a hk 08/22/13 Added prototypes of API's for QSPI reset and -* linear mode initialization for boot. Added related -* constant definitions. -* -* </pre> -* -******************************************************************************/ -#ifndef XQSPIPS_HW_H /* prevent circular inclusions */ -#define XQSPIPS_HW_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xil_io.h" -#include "xparameters.h" - -/************************** Constant Definitions *****************************/ - -/** @name Register Map - * - * Register offsets from the base address of an QSPI device. - * @{ - */ -#define XQSPIPS_CR_OFFSET 0x00 /**< Configuration Register */ -#define XQSPIPS_SR_OFFSET 0x04 /**< Interrupt Status */ -#define XQSPIPS_IER_OFFSET 0x08 /**< Interrupt Enable */ -#define XQSPIPS_IDR_OFFSET 0x0c /**< Interrupt Disable */ -#define XQSPIPS_IMR_OFFSET 0x10 /**< Interrupt Enabled Mask */ -#define XQSPIPS_ER_OFFSET 0x14 /**< Enable/Disable Register */ -#define XQSPIPS_DR_OFFSET 0x18 /**< Delay Register */ -#define XQSPIPS_TXD_00_OFFSET 0x1C /**< Transmit 4-byte inst/data */ -#define XQSPIPS_RXD_OFFSET 0x20 /**< Data Receive Register */ -#define XQSPIPS_SICR_OFFSET 0x24 /**< Slave Idle Count */ -#define XQSPIPS_TXWR_OFFSET 0x28 /**< Transmit FIFO Watermark */ -#define XQSPIPS_RXWR_OFFSET 0x2C /**< Receive FIFO Watermark */ -#define XQSPIPS_GPIO_OFFSET 0x30 /**< GPIO Register */ -#define XQSPIPS_LPBK_DLY_ADJ_OFFSET 0x38 /**< Loopback Delay Adjust Reg */ -#define XQSPIPS_TXD_01_OFFSET 0x80 /**< Transmit 1-byte inst */ -#define XQSPIPS_TXD_10_OFFSET 0x84 /**< Transmit 2-byte inst */ -#define XQSPIPS_TXD_11_OFFSET 0x88 /**< Transmit 3-byte inst */ -#define XQSPIPS_LQSPI_CR_OFFSET 0xA0 /**< Linear QSPI config register */ -#define XQSPIPS_LQSPI_SR_OFFSET 0xA4 /**< Linear QSPI status register */ -#define XQSPIPS_MOD_ID_OFFSET 0xFC /**< Module ID register */ - -/* @} */ - -/** @name Configuration Register - * - * This register contains various control bits that - * affect the operation of the QSPI device. Read/Write. - * @{ - */ - -#define XQSPIPS_CR_IFMODE_MASK 0x80000000 /**< Flash mem interface mode */ -#define XQSPIPS_CR_ENDIAN_MASK 0x04000000 /**< Tx/Rx FIFO endianness */ -#define XQSPIPS_CR_MANSTRT_MASK 0x00010000 /**< Manual Transmission Start */ -#define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start - Enable */ -#define XQSPIPS_CR_SSFORCE_MASK 0x00004000 /**< Force Slave Select */ -#define XQSPIPS_CR_SSCTRL_MASK 0x00000400 /**< Slave Select Decode */ -#define XQSPIPS_CR_SSCTRL_SHIFT 10 /**< Slave Select Decode shift */ -#define XQSPIPS_CR_DATA_SZ_MASK 0x000000C0 /**< Size of word to be - transferred */ -#define XQSPIPS_CR_PRESC_MASK 0x00000038 /**< Prescaler Setting */ -#define XQSPIPS_CR_PRESC_SHIFT 3 /**< Prescaler shift */ -#define XQSPIPS_CR_PRESC_MAXIMUM 0x07 /**< Prescaler maximum value */ - -#define XQSPIPS_CR_CPHA_MASK 0x00000004 /**< Phase Configuration */ -#define XQSPIPS_CR_CPOL_MASK 0x00000002 /**< Polarity Configuration */ - -#define XQSPIPS_CR_MSTREN_MASK 0x00000001 /**< Master Mode Enable */ - -#define XQSPIPS_CR_HOLD_B_MASK 0x00080000 /**< HOLD_B Pin Drive Enable */ - -/* Deselect the Slave select line and set the transfer size to 32 at reset */ -#define XQSPIPS_CR_RESET_STATE (XQSPIPS_CR_IFMODE_MASK | \ - XQSPIPS_CR_SSCTRL_MASK | \ - XQSPIPS_CR_DATA_SZ_MASK | \ - XQSPIPS_CR_MSTREN_MASK) -/* @} */ - - -/** @name QSPI Interrupt Registers - * - * <b>QSPI Status Register</b> - * - * This register holds the interrupt status flags for an QSPI device. Some - * of the flags are level triggered, which means that they are set as long - * as the interrupt condition exists. Other flags are edge triggered, - * which means they are set once the interrupt condition occurs and remain - * set until they are cleared by software. The interrupts are cleared by - * writing a '1' to the interrupt bit position in the Status Register. - * Read/Write. - * - * <b>QSPI Interrupt Enable Register</b> - * - * This register is used to enable chosen interrupts for an QSPI device. - * Writing a '1' to a bit in this register sets the corresponding bit in the - * QSPI Interrupt Mask register. Write only. - * - * <b>QSPI Interrupt Disable Register </b> - * - * This register is used to disable chosen interrupts for an QSPI device. - * Writing a '1' to a bit in this register clears the corresponding bit in the - * QSPI Interrupt Mask register. Write only. - * - * <b>QSPI Interrupt Mask Register</b> - * - * This register shows the enabled/disabled interrupts of an QSPI device. - * Read only. - * - * All four registers have the same bit definitions. They are only defined once - * for each of the Interrupt Enable Register, Interrupt Disable Register, - * Interrupt Mask Register, and Channel Interrupt Status Register - * @{ - */ - -#define XQSPIPS_IXR_TXUF_MASK 0x00000040 /**< QSPI Tx FIFO Underflow */ -#define XQSPIPS_IXR_RXFULL_MASK 0x00000020 /**< QSPI Rx FIFO Full */ -#define XQSPIPS_IXR_RXNEMPTY_MASK 0x00000010 /**< QSPI Rx FIFO Not Empty */ -#define XQSPIPS_IXR_TXFULL_MASK 0x00000008 /**< QSPI Tx FIFO Full */ -#define XQSPIPS_IXR_TXOW_MASK 0x00000004 /**< QSPI Tx FIFO Overwater */ -#define XQSPIPS_IXR_RXOVR_MASK 0x00000001 /**< QSPI Rx FIFO Overrun */ -#define XQSPIPS_IXR_DFLT_MASK 0x00000025 /**< QSPI default interrupts - mask */ -#define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041 /**< Interrupts which - need write to clear */ -#define XQSPIPS_ISR_RESET_STATE 0x00000004 /**< Default to tx/rx empty */ -#define XQSPIPS_IXR_DISABLE_ALL 0x0000007D /**< Disable all interrupts */ -/* @} */ - - -/** @name Enable Register - * - * This register is used to enable or disable an QSPI device. - * Read/Write - * @{ - */ -#define XQSPIPS_ER_ENABLE_MASK 0x00000001 /**< QSPI Enable Bit Mask */ -/* @} */ - - -/** @name Delay Register - * - * This register is used to program timing delays in - * slave mode. Read/Write - * @{ - */ -#define XQSPIPS_DR_NSS_MASK 0xFF000000 /**< Delay to de-assert slave select - between two words mask */ -#define XQSPIPS_DR_NSS_SHIFT 24 /**< Delay to de-assert slave select - between two words shift */ -#define XQSPIPS_DR_BTWN_MASK 0x00FF0000 /**< Delay Between Transfers - mask */ -#define XQSPIPS_DR_BTWN_SHIFT 16 /**< Delay Between Transfers shift */ -#define XQSPIPS_DR_AFTER_MASK 0x0000FF00 /**< Delay After Transfers mask */ -#define XQSPIPS_DR_AFTER_SHIFT 8 /**< Delay After Transfers shift */ -#define XQSPIPS_DR_INIT_MASK 0x000000FF /**< Delay Initially mask */ -/* @} */ - -/** @name Slave Idle Count Registers - * - * This register defines the number of pclk cycles the slave waits for a the - * QSPI clock to become stable in quiescent state before it can detect the start - * of the next transfer in CPHA = 1 mode. - * Read/Write - * - * @{ - */ -#define XQSPIPS_SICR_MASK 0x000000FF /**< Slave Idle Count Mask */ -/* @} */ - - -/** @name Transmit FIFO Watermark Register - * - * This register defines the watermark setting for the Transmit FIFO. - * - * @{ - */ -#define XQSPIPS_TXWR_MASK 0x0000003F /**< Transmit Watermark Mask */ -#define XQSPIPS_TXWR_RESET_VALUE 0x00000001 /**< Transmit Watermark - * register reset value */ - -/* @} */ - -/** @name Receive FIFO Watermark Register - * - * This register defines the watermark setting for the Receive FIFO. - * - * @{ - */ -#define XQSPIPS_RXWR_MASK 0x0000003F /**< Receive Watermark Mask */ -#define XQSPIPS_RXWR_RESET_VALUE 0x00000001 /**< Receive Watermark - * register reset value */ - -/* @} */ - -/** @name FIFO Depth - * - * This macro provides the depth of transmit FIFO and receive FIFO. - * - * @{ - */ -#define XQSPIPS_FIFO_DEPTH 63 /**< FIFO depth (words) */ -/* @} */ - - -/** @name Linear QSPI Configuration Register - * - * This register contains various control bits that - * affect the operation of the Linear QSPI controller. Read/Write. - * - * @{ - */ -#define XQSPIPS_LQSPI_CR_LINEAR_MASK 0x80000000 /**< LQSPI mode enable */ -#define XQSPIPS_LQSPI_CR_TWO_MEM_MASK 0x40000000 /**< Both memories or one */ -#define XQSPIPS_LQSPI_CR_SEP_BUS_MASK 0x20000000 /**< Seperate memory bus */ -#define XQSPIPS_LQSPI_CR_U_PAGE_MASK 0x10000000 /**< Upper memory page */ -#define XQSPIPS_LQSPI_CR_MODE_EN_MASK 0x02000000 /**< Enable mode bits */ -#define XQSPIPS_LQSPI_CR_MODE_ON_MASK 0x01000000 /**< Mode on */ -#define XQSPIPS_LQSPI_CR_MODE_BITS_MASK 0x00FF0000 /**< Mode value for dual I/O - or quad I/O */ -#define XQSPIPS_LQSPI_CR_DUMMY_MASK 0x00000700 /**< Number of dummy bytes - between addr and return - read data */ -#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF /**< Read instr code */ -#define XQSPIPS_LQSPI_CR_RST_STATE 0x8000016B /**< Default CR value */ -/* @} */ - -/** @name Linear QSPI Status Register - * - * This register contains various status bits of the Linear QSPI controller. - * Read/Write. - * - * @{ - */ -#define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK 0x00000004 /**< AXI Data FSM Error - received */ -#define XQSPIPS_LQSPI_SR_WR_RECVD_MASK 0x00000002 /**< AXI write command - received */ -/* @} */ - - -/** @name Loopback Delay Adjust Register - * - * This register contains various bit masks of Loopback Delay Adjust Register. - * - * @{ - */ - -#define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 /**< Loopback Bit */ - -/* @} */ - - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -#define XQspiPs_In32 Xil_In32 -#define XQspiPs_Out32 Xil_Out32 - -/****************************************************************************/ -/** -* Read a register. -* -* @param BaseAddress contains the base address of the device. -* @param RegOffset contains the offset from the 1st register of the -* device to the target register. -* -* @return The value read from the register. -* -* @note C-Style signature: -* u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset) -* -******************************************************************************/ -#define XQspiPs_ReadReg(BaseAddress, RegOffset) \ - XQspiPs_In32((BaseAddress) + (RegOffset)) - -/***************************************************************************/ -/** -* Write to a register. -* -* @param BaseAddress contains the base address of the device. -* @param RegOffset contains the offset from the 1st register of the -* device to target register. -* @param RegisterValue is the value to be written to the register. -* -* @return None. -* -* @note C-Style signature: -* void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset, -* u32 RegisterValue) -* -******************************************************************************/ -#define XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ - XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue)) - -/************************** Function Prototypes ******************************/ - -/* - * Functions implemented in xqspips_hw.c - */ -void XQspiPs_ResetHw(u32 BaseAddress); -void XQspiPs_LinearInit(u32 BaseAddress); - -/************************** Variable Definitions *****************************/ - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h deleted file mode 100644 index 65e648f5476b77ff3b7e81ed87665072d91e5849..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h +++ /dev/null @@ -1,599 +0,0 @@ -/******************************************************************************* -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -*******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xreg_cortexa9.h -* -* This header file contains definitions for using inline assembler code. It is -* written specifically for the GNU, IAR, ARMCC compiler. -* -* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along -* with the positions of the bits within the registers. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- -------- -------- ----------------------------------------------- -* 1.00a ecm/sdm 10/20/09 First release -* </pre> -* -******************************************************************************/ -#ifndef XREG_CORTEXA9_H -#define XREG_CORTEXA9_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* GPRs */ -#define XREG_GPR0 r0 -#define XREG_GPR1 r1 -#define XREG_GPR2 r2 -#define XREG_GPR3 r3 -#define XREG_GPR4 r4 -#define XREG_GPR5 r5 -#define XREG_GPR6 r6 -#define XREG_GPR7 r7 -#define XREG_GPR8 r8 -#define XREG_GPR9 r9 -#define XREG_GPR10 r10 -#define XREG_GPR11 r11 -#define XREG_GPR12 r12 -#define XREG_GPR13 r13 -#define XREG_GPR14 r14 -#define XREG_GPR15 r15 -#define XREG_CPSR cpsr - -/* Coprocessor number defines */ -#define XREG_CP0 0 -#define XREG_CP1 1 -#define XREG_CP2 2 -#define XREG_CP3 3 -#define XREG_CP4 4 -#define XREG_CP5 5 -#define XREG_CP6 6 -#define XREG_CP7 7 -#define XREG_CP8 8 -#define XREG_CP9 9 -#define XREG_CP10 10 -#define XREG_CP11 11 -#define XREG_CP12 12 -#define XREG_CP13 13 -#define XREG_CP14 14 -#define XREG_CP15 15 - -/* Coprocessor control register defines */ -#define XREG_CR0 cr0 -#define XREG_CR1 cr1 -#define XREG_CR2 cr2 -#define XREG_CR3 cr3 -#define XREG_CR4 cr4 -#define XREG_CR5 cr5 -#define XREG_CR6 cr6 -#define XREG_CR7 cr7 -#define XREG_CR8 cr8 -#define XREG_CR9 cr9 -#define XREG_CR10 cr10 -#define XREG_CR11 cr11 -#define XREG_CR12 cr12 -#define XREG_CR13 cr13 -#define XREG_CR14 cr14 -#define XREG_CR15 cr15 - -/* Current Processor Status Register (CPSR) Bits */ -#define XREG_CPSR_THUMB_MODE 0x20 -#define XREG_CPSR_MODE_BITS 0x1F -#define XREG_CPSR_SYSTEM_MODE 0x1F -#define XREG_CPSR_UNDEFINED_MODE 0x1B -#define XREG_CPSR_DATA_ABORT_MODE 0x17 -#define XREG_CPSR_SVC_MODE 0x13 -#define XREG_CPSR_IRQ_MODE 0x12 -#define XREG_CPSR_FIQ_MODE 0x11 -#define XREG_CPSR_USER_MODE 0x10 - -#define XREG_CPSR_IRQ_ENABLE 0x80 -#define XREG_CPSR_FIQ_ENABLE 0x40 - -#define XREG_CPSR_N_BIT 0x80000000 -#define XREG_CPSR_Z_BIT 0x40000000 -#define XREG_CPSR_C_BIT 0x20000000 -#define XREG_CPSR_V_BIT 0x10000000 - - -/* CP15 defines */ -#if defined (__GNUC__) || defined (__ICCARM__) -/* C0 Register defines */ -#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0" -#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1" -#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2" -#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3" -#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5" - -#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0" -#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1" -#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2" -#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4" -#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5" -#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6" -#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7" - -#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0" -#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1" -#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2" -#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3" -#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4" - -#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0" -#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1" -#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7" - -#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0" - -/* C1 Register Defines */ -#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0" -#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1" -#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2" - -#define XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0" -#define XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1" -#define XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2" -#define XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3" - -#else /* RVCT */ -/* C0 Register defines */ -#define XREG_CP15_MAIN_ID "cp15:0:c0:c0:0" -#define XREG_CP15_CACHE_TYPE "cp15:0:c0:c0:1" -#define XREG_CP15_TCM_TYPE "cp15:0:c0:c0:2" -#define XREG_CP15_TLB_TYPE "cp15:0:c0:c0:3" -#define XREG_CP15_MULTI_PROC_AFFINITY "cp15:0:c0:c0:5" - -#define XREG_CP15_PROC_FEATURE_0 "cp15:0:c0:c1:0" -#define XREG_CP15_PROC_FEATURE_1 "cp15:0:c0:c1:1" -#define XREG_CP15_DEBUG_FEATURE_0 "cp15:0:c0:c1:2" -#define XREG_CP15_MEMORY_FEATURE_0 "cp15:0:c0:c1:4" -#define XREG_CP15_MEMORY_FEATURE_1 "cp15:0:c0:c1:5" -#define XREG_CP15_MEMORY_FEATURE_2 "cp15:0:c0:c1:6" -#define XREG_CP15_MEMORY_FEATURE_3 "cp15:0:c0:c1:7" - -#define XREG_CP15_INST_FEATURE_0 "cp15:0:c0:c2:0" -#define XREG_CP15_INST_FEATURE_1 "cp15:0:c0:c2:1" -#define XREG_CP15_INST_FEATURE_2 "cp15:0:c0:c2:2" -#define XREG_CP15_INST_FEATURE_3 "cp15:0:c0:c2:3" -#define XREG_CP15_INST_FEATURE_4 "cp15:0:c0:c2:4" - -#define XREG_CP15_CACHE_SIZE_ID "cp15:1:c0:c0:0" -#define XREG_CP15_CACHE_LEVEL_ID "cp15:1:c0:c0:1" -#define XREG_CP15_AUXILARY_ID "cp15:1:c0:c0:7" - -#define XREG_CP15_CACHE_SIZE_SEL "cp15:2:c0:c0:0" - -/* C1 Register Defines */ -#define XREG_CP15_SYS_CONTROL "cp15:0:c1:c0:0" -#define XREG_CP15_AUX_CONTROL "cp15:0:c1:c0:1" -#define XREG_CP15_CP_ACCESS_CONTROL "cp15:0:c1:c0:2" - -#define XREG_CP15_SECURE_CONFIG "cp15:0:c1:c1:0" -#define XREG_CP15_SECURE_DEBUG_ENABLE "cp15:0:c1:c1:1" -#define XREG_CP15_NS_ACCESS_CONTROL "cp15:0:c1:c1:2" -#define XREG_CP15_VIRTUAL_CONTROL "cp15:0:c1:c1:3" -#endif - -/* XREG_CP15_CONTROL bit defines */ -#define XREG_CP15_CONTROL_TE_BIT 0x40000000 -#define XREG_CP15_CONTROL_AFE_BIT 0x20000000 -#define XREG_CP15_CONTROL_TRE_BIT 0x10000000 -#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000 -#define XREG_CP15_CONTROL_EE_BIT 0x02000000 -#define XREG_CP15_CONTROL_HA_BIT 0x00020000 -#define XREG_CP15_CONTROL_RR_BIT 0x00004000 -#define XREG_CP15_CONTROL_V_BIT 0x00002000 -#define XREG_CP15_CONTROL_I_BIT 0x00001000 -#define XREG_CP15_CONTROL_Z_BIT 0x00000800 -#define XREG_CP15_CONTROL_SW_BIT 0x00000400 -#define XREG_CP15_CONTROL_B_BIT 0x00000080 -#define XREG_CP15_CONTROL_C_BIT 0x00000004 -#define XREG_CP15_CONTROL_A_BIT 0x00000002 -#define XREG_CP15_CONTROL_M_BIT 0x00000001 - -#if defined (__GNUC__) || defined (__ICCARM__) -/* C2 Register Defines */ -#define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0" -#define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1" -#define XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2" - -/* C3 Register Defines */ -#define XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0" - -/* C4 Register Defines */ -/* Not Used */ - -/* C5 Register Defines */ -#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0" -#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1" - -#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0" -#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1" - -/* C6 Register Defines */ -#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0" -#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2" - -/* C7 Register Defines */ -#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4" - -#define XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0" -#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6" - -#define XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0" - -#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0" -#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1" - -/* The CP15 register access below has been deprecated in favor of the new - * isb instruction in Cortex A9. - */ -#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4" -#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6" - -#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1" -#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2" - -#define XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0" -#define XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1" -#define XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2" -#define XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3" - -#define XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4" -#define XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5" -#define XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6" -#define XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7" - -#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1" -#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2" - -/* The next two CP15 register accesses below have been deprecated in favor - * of the new dsb and dmb instructions in Cortex A9. - */ -#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4" -#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5" - -#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1" - -#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1" - -#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1" -#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2" - -/* C8 Register Defines */ -#define XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0" -#define XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1" -#define XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2" -#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3" - -#define XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0" -#define XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1" -#define XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2" - -#define XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0" -#define XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1" -#define XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2" - -#define XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0" -#define XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1" -#define XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2" -#define XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3" - -/* C9 Register Defines */ -#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0" -#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1" -#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2" -#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3" -#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4" -#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5" - -#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0" -#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1" -#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2" - -#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0" -#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1" -#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2" - -/* C10 Register Defines */ -#define XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0" - -#define XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0" -#define XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1" - -/* C11 Register Defines */ -/* Not used */ - -/* C12 Register Defines */ -#define XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0" -#define XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1" - -#define XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0" -#define XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1" - -/* C13 Register Defines */ -#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1" -#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2" -#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3" -#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4" - -/* C14 Register Defines */ -/* not used */ - -/* C15 Register Defines */ -#define XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0" -#define XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0" - -#define XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2" -#define XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4" - -#define XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2" - -#define XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2" - -#define XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2" - -#else -/* C2 Register Defines */ -#define XREG_CP15_TTBR0 "cp15:0:c2:c0:0" -#define XREG_CP15_TTBR1 "cp15:0:c2:c0:1" -#define XREG_CP15_TTB_CONTROL "cp15:0:c2:c0:2" - -/* C3 Register Defines */ -#define XREG_CP15_DOMAIN_ACCESS_CTRL "cp15:0:c3:c0:0" - -/* C4 Register Defines */ -/* Not Used */ - -/* C5 Register Defines */ -#define XREG_CP15_DATA_FAULT_STATUS "cp15:0:c5:c0:0" -#define XREG_CP15_INST_FAULT_STATUS "cp15:0:c5:c0:1" - -#define XREG_CP15_AUX_DATA_FAULT_STATUS "cp15:0:c5:c1:0" -#define XREG_CP15_AUX_INST_FAULT_STATUS "cp15:0:c5:c1:1" - -/* C6 Register Defines */ -#define XREG_CP15_DATA_FAULT_ADDRESS "cp15:0:c6:c0:0" -#define XREG_CP15_INST_FAULT_ADDRESS "cp15:0:c6:c0:2" - -/* C7 Register Defines */ -#define XREG_CP15_NOP "cp15:0:c7:c0:4" - -#define XREG_CP15_INVAL_IC_POU_IS "cp15:0:c7:c1:0" -#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "cp15:0:c7:c1:6" - -#define XREG_CP15_PHYS_ADDR "cp15:0:c7:c4:0" - -#define XREG_CP15_INVAL_IC_POU "cp15:0:c7:c5:0" -#define XREG_CP15_INVAL_IC_LINE_MVA_POU "cp15:0:c7:c5:1" - -/* The CP15 register access below has been deprecated in favor of the new - * isb instruction in Cortex A9. - */ -#define XREG_CP15_INST_SYNC_BARRIER "cp15:0:c7:c5:4" -#define XREG_CP15_INVAL_BRANCH_ARRAY "cp15:0:c7:c5:6" - -#define XREG_CP15_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c6:1" -#define XREG_CP15_INVAL_DC_LINE_SW "cp15:0:c7:c6:2" - -#define XREG_CP15_VA_TO_PA_CURRENT_0 "cp15:0:c7:c8:0" -#define XREG_CP15_VA_TO_PA_CURRENT_1 "cp15:0:c7:c8:1" -#define XREG_CP15_VA_TO_PA_CURRENT_2 "cp15:0:c7:c8:2" -#define XREG_CP15_VA_TO_PA_CURRENT_3 "cp15:0:c7:c8:3" - -#define XREG_CP15_VA_TO_PA_OTHER_0 "cp15:0:c7:c8:4" -#define XREG_CP15_VA_TO_PA_OTHER_1 "cp15:0:c7:c8:5" -#define XREG_CP15_VA_TO_PA_OTHER_2 "cp15:0:c7:c8:6" -#define XREG_CP15_VA_TO_PA_OTHER_3 "cp15:0:c7:c8:7" - -#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "cp15:0:c7:c10:1" -#define XREG_CP15_CLEAN_DC_LINE_SW "cp15:0:c7:c10:2" - -/* The next two CP15 register accesses below have been deprecated in favor - * of the new dsb and dmb instructions in Cortex A9. - */ -#define XREG_CP15_DATA_SYNC_BARRIER "cp15:0:c7:c10:4" -#define XREG_CP15_DATA_MEMORY_BARRIER "cp15:0:c7:c10:5" - -#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "cp15:0:c7:c11:1" - -#define XREG_CP15_NOP2 "cp15:0:c7:c13:1" - -#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c14:1" -#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "cp15:0:c7:c14:2" - -/* C8 Register Defines */ -#define XREG_CP15_INVAL_TLB_IS "cp15:0:c8:c3:0" -#define XREG_CP15_INVAL_TLB_MVA_IS "cp15:0:c8:c3:1" -#define XREG_CP15_INVAL_TLB_ASID_IS "cp15:0:c8:c3:2" -#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "cp15:0:c8:c3:3" - -#define XREG_CP15_INVAL_ITLB_UNLOCKED "cp15:0:c8:c5:0" -#define XREG_CP15_INVAL_ITLB_MVA "cp15:0:c8:c5:1" -#define XREG_CP15_INVAL_ITLB_ASID "cp15:0:c8:c5:2" - -#define XREG_CP15_INVAL_DTLB_UNLOCKED "cp15:0:c8:c6:0" -#define XREG_CP15_INVAL_DTLB_MVA "cp15:0:c8:c6:1" -#define XREG_CP15_INVAL_DTLB_ASID "cp15:0:c8:c6:2" - -#define XREG_CP15_INVAL_UTLB_UNLOCKED "cp15:0:c8:c7:0" -#define XREG_CP15_INVAL_UTLB_MVA "cp15:0:c8:c7:1" -#define XREG_CP15_INVAL_UTLB_ASID "cp15:0:c8:c7:2" -#define XREG_CP15_INVAL_UTLB_MVA_ASID "cp15:0:c8:c7:3" - -/* C9 Register Defines */ -#define XREG_CP15_PERF_MONITOR_CTRL "cp15:0:c9:c12:0" -#define XREG_CP15_COUNT_ENABLE_SET "cp15:0:c9:c12:1" -#define XREG_CP15_COUNT_ENABLE_CLR "cp15:0:c9:c12:2" -#define XREG_CP15_V_FLAG_STATUS "cp15:0:c9:c12:3" -#define XREG_CP15_SW_INC "cp15:0:c9:c12:4" -#define XREG_CP15_EVENT_CNTR_SEL "cp15:0:c9:c12:5" - -#define XREG_CP15_PERF_CYCLE_COUNTER "cp15:0:c9:c13:0" -#define XREG_CP15_EVENT_TYPE_SEL "cp15:0:c9:c13:1" -#define XREG_CP15_PERF_MONITOR_COUNT "cp15:0:c9:c13:2" - -#define XREG_CP15_USER_ENABLE "cp15:0:c9:c14:0" -#define XREG_CP15_INTR_ENABLE_SET "cp15:0:c9:c14:1" -#define XREG_CP15_INTR_ENABLE_CLR "cp15:0:c9:c14:2" - -/* C10 Register Defines */ -#define XREG_CP15_TLB_LOCKDWN "cp15:0:c10:c0:0" - -#define XREG_CP15_PRI_MEM_REMAP "cp15:0:c10:c2:0" -#define XREG_CP15_NORM_MEM_REMAP "cp15:0:c10:c2:1" - -/* C11 Register Defines */ -/* Not used */ - -/* C12 Register Defines */ -#define XREG_CP15_VEC_BASE_ADDR "cp15:0:c12:c0:0" -#define XREG_CP15_MONITOR_VEC_BASE_ADDR "cp15:0:c12:c0:1" - -#define XREG_CP15_INTERRUPT_STATUS "cp15:0:c12:c1:0" -#define XREG_CP15_VIRTUALIZATION_INTR "cp15:0:c12:c1:1" - -/* C13 Register Defines */ -#define XREG_CP15_CONTEXT_ID "cp15:0:c13:c0:1" -#define USER_RW_THREAD_PID "cp15:0:c13:c0:2" -#define USER_RO_THREAD_PID "cp15:0:c13:c0:3" -#define USER_PRIV_THREAD_PID "cp15:0:c13:c0:4" - -/* C14 Register Defines */ -/* not used */ - -/* C15 Register Defines */ -#define XREG_CP15_POWER_CTRL "cp15:0:c15:c0:0" -#define XREG_CP15_CONFIG_BASE_ADDR "cp15:4:c15:c0:0" - -#define XREG_CP15_READ_TLB_ENTRY "cp15:5:c15:c4:2" -#define XREG_CP15_WRITE_TLB_ENTRY "cp15:5:c15:c4:4" - -#define XREG_CP15_MAIN_TLB_VA "cp15:5:c15:c5:2" - -#define XREG_CP15_MAIN_TLB_PA "cp15:5:c15:c6:2" - -#define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2" -#endif - - -/* MPE register definitions */ -#define XREG_FPSID c0 -#define XREG_FPSCR c1 -#define XREG_MVFR1 c6 -#define XREG_MVFR0 c7 -#define XREG_FPEXC c8 -#define XREG_FPINST c9 -#define XREG_FPINST2 c10 - -/* FPSID bits */ -#define XREG_FPSID_IMPLEMENTER_BIT (24) -#define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT) -#define XREG_FPSID_SOFTWARE (1<<23) -#define XREG_FPSID_ARCH_BIT (16) -#define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT) -#define XREG_FPSID_PART_BIT (8) -#define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT) -#define XREG_FPSID_VARIANT_BIT (4) -#define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT) -#define XREG_FPSID_REV_BIT (0) -#define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT) - -/* FPSCR bits */ -#define XREG_FPSCR_N_BIT (1 << 31) -#define XREG_FPSCR_Z_BIT (1 << 30) -#define XREG_FPSCR_C_BIT (1 << 29) -#define XREG_FPSCR_V_BIT (1 << 28) -#define XREG_FPSCR_QC (1 << 27) -#define XREG_FPSCR_AHP (1 << 26) -#define XREG_FPSCR_DEFAULT_NAN (1 << 25) -#define XREG_FPSCR_FLUSHTOZERO (1 << 24) -#define XREG_FPSCR_ROUND_NEAREST (0 << 22) -#define XREG_FPSCR_ROUND_PLUSINF (1 << 22) -#define XREG_FPSCR_ROUND_MINUSINF (2 << 22) -#define XREG_FPSCR_ROUND_TOZERO (3 << 22) -#define XREG_FPSCR_RMODE_BIT (22) -#define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT) -#define XREG_FPSCR_STRIDE_BIT (20) -#define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT) -#define XREG_FPSCR_LENGTH_BIT (16) -#define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT) -#define XREG_FPSCR_IDC (1 << 7) -#define XREG_FPSCR_IXC (1 << 4) -#define XREG_FPSCR_UFC (1 << 3) -#define XREG_FPSCR_OFC (1 << 2) -#define XREG_FPSCR_DZC (1 << 1) -#define XREG_FPSCR_IOC (1 << 0) - -/* MVFR0 bits */ -#define XREG_MVFR0_RMODE_BIT (28) -#define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT) -#define XREG_MVFR0_SHORT_VEC_BIT (24) -#define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT) -#define XREG_MVFR0_SQRT_BIT (20) -#define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT) -#define XREG_MVFR0_DIVIDE_BIT (16) -#define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT) -#define XREG_MVFR0_EXEC_TRAP_BIT (12) -#define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT) -#define XREG_MVFR0_DP_BIT (8) -#define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT) -#define XREG_MVFR0_SP_BIT (4) -#define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT) -#define XREG_MVFR0_A_SIMD_BIT (0) -#define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT) - -/* FPEXC bits */ -#define XREG_FPEXC_EX (1 << 31) -#define XREG_FPEXC_EN (1 << 30) -#define XREG_FPEXC_DEX (1 << 29) - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* XREG_CORTEXA9_H */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xscugic.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xscugic.h deleted file mode 100644 index d119872e93163065757770548eb75316b6674052..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xscugic.h +++ /dev/null @@ -1,318 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xscugic.h -* -* The generic interrupt controller driver component. -* -* The interrupt controller driver uses the idea of priority for the various -* handlers. Priority is an integer within the range of 1 and 31 inclusive with -* default of 1 being the highest priority interrupt source. The priorities -* of the various sources can be dynamically altered as needed through -* hardware configuration. -* -* The generic interrupt controller supports the following -* features: -* -* - specific individual interrupt enabling/disabling -* - specific individual interrupt acknowledging -* - attaching specific callback function to handle interrupt source -* - assigning desired priority to interrupt source if default is not -* acceptable. -* -* Details about connecting the interrupt handler of the driver are contained -* in the source file specific to interrupt processing, xscugic_intr.c. -* -* This driver is intended to be RTOS and processor independent. It works with -* physical addresses only. Any needs for dynamic memory management, threads -* or thread mutual exclusion, virtual memory, or cache control must be -* satisfied by the layer above this driver. -* -* <b>Interrupt Vector Tables</b> -* -* The device ID of the interrupt controller device is used by the driver as a -* direct index into the configuration data table. The user should populate the -* vector table with handlers and callbacks at run-time using the -* XScuGic_Connect() and XScuGic_Disconnect() functions. -* -* Each vector table entry corresponds to a device that can generate an -* interrupt. Each entry contains an interrupt handler function and an -* argument to be passed to the handler when an interrupt occurs. The -* user must use XScuGic_Connect() when the interrupt handler takes an -* argument other than the base address. -* -* <b>Nested Interrupts Processing</b> -* -* Nested interrupts are not supported by this driver. -* -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- --------------------------------------------------------- -* 1.00a drg 01/19/00 First release -* 1.01a sdm 11/09/11 The XScuGic and XScuGic_Config structures have changed. -* The HandlerTable (of type XScuGic_VectorTableEntry) is -* moved to XScuGic_Config structure from XScuGic structure. -* -* The "Config" entry in XScuGic structure is made as -* pointer for better efficiency. -* -* A new file named as xscugic_hw.c is now added. It is -* to implement low level driver routines without using -* any xscugic instance pointer. They are useful when the -* user wants to use xscugic through device id or -* base address. The driver routines provided are explained -* below. -* XScuGic_DeviceInitialize that takes device id as -* argument and initializes the device (without calling -* XScuGic_CfgInitialize). -* XScuGic_DeviceInterruptHandler that takes device id -* as argument and calls appropriate handlers from the -* HandlerTable. -* XScuGic_RegisterHandler that registers a new handler -* by taking xscugic hardware base address as argument. -* LookupConfigByBaseAddress is used to return the -* corresponding config structure from XScuGic_ConfigTable -* based on the scugic base address passed. -* 1.02a sdm 12/20/11 Removed AckBeforeService from the XScuGic_Config -* structure. -* 1.03a srt 02/27/13 Moved Offset calculation macros from *.c and *_hw.c to -* *_hw.h -* Added APIs -* - XScuGic_SetPriTrigTypeByDistAddr() -* - XScuGic_GetPriTrigTypeByDistAddr() -* (CR 702687) -* Added support to direct interrupts to the appropriate CPU. Earlier -* interrupts were directed to CPU1 (hard coded). Now depending -* upon the CPU selected by the user (xparameters.h), interrupts -* will be directed to the relevant CPU. This fixes CR 699688. -* 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in -* XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings. -* Moved functions XScuGic_SetPriTrigTypeByDistAddr and -* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c. -* This is fix for CR#705621. -* 1.05a hk 06/26/13 Modified tcl to export external interrupts correctly to -* xparameters.h. Fix for CR's 690505, 708928 & 719359. -* -* </pre> -* -******************************************************************************/ - -#ifndef XSCUGIC_H /* prevent circular inclusions */ -#define XSCUGIC_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - - -/***************************** Include Files *********************************/ - -#include "xstatus.h" -#include "xil_io.h" -#include "xscugic_hw.h" -#include "xil_exception.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - -/* The following data type defines each entry in an interrupt vector table. - * The callback reference is the base address of the interrupting device - * for the low level driver and an instance pointer for the high level driver. - */ -typedef struct -{ - Xil_InterruptHandler Handler; - void *CallBackRef; -} XScuGic_VectorTableEntry; - -/** - * This typedef contains configuration information for the device. - */ -typedef struct -{ - u16 DeviceId; /**< Unique ID of device */ - u32 CpuBaseAddress; /**< CPU Interface Register base address */ - u32 DistBaseAddress; /**< Distributor Register base address */ - XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**< - Vector table of interrupt handlers */ -} XScuGic_Config; - -/** - * The XScuGic driver instance data. The user is required to allocate a - * variable of this type for every intc device in the system. A pointer - * to a variable of this type is then passed to the driver API functions. - */ -typedef struct -{ - XScuGic_Config *Config; /**< Configuration table entry */ - u32 IsReady; /**< Device is initialized and ready */ - u32 UnhandledInterrupts; /**< Intc Statistics */ -} XScuGic; - -/***************** Macros (Inline Functions) Definitions *********************/ - -/****************************************************************************/ -/** -* -* Write the given CPU Interface register -* -* @param InstancePtr is a pointer to the instance to be worked on. -* @param RegOffset is the register offset to be written -* @param Data is the 32-bit value to write to the register -* -* @return None. -* -* @note -* C-style signature: -* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) -* -*****************************************************************************/ -#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \ -(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \ - ((u32)Data))) - -/****************************************************************************/ -/** -* -* Read the given CPU Interface register -* -* @param InstancePtr is a pointer to the instance to be worked on. -* @param RegOffset is the register offset to be read -* -* @return The 32-bit value of the register -* -* @note -* C-style signature: -* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset) -* -*****************************************************************************/ -#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \ - (XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset))) - -/****************************************************************************/ -/** -* -* Write the given Distributor Interface register -* -* @param InstancePtr is a pointer to the instance to be worked on. -* @param RegOffset is the register offset to be written -* @param Data is the 32-bit value to write to the register -* -* @return None. -* -* @note -* C-style signature: -* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) -* -*****************************************************************************/ -#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \ -(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \ - ((u32)Data))) - -/****************************************************************************/ -/** -* -* Read the given Distributor Interface register -* -* @param InstancePtr is a pointer to the instance to be worked on. -* @param RegOffset is the register offset to be read -* -* @return The 32-bit value of the register -* -* @note -* C-style signature: -* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset) -* -*****************************************************************************/ -#define XScuGic_DistReadReg(InstancePtr, RegOffset) \ -(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset))) - -/************************** Function Prototypes ******************************/ - -/* - * Required functions in xscugic.c - */ - -int XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id, - Xil_InterruptHandler Handler, void *CallBackRef); -void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id); - -void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id); -void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id); - -int XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr, - u32 EffectiveAddr); - -int XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id); - -void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, - u8 *Priority, u8 *Trigger); -void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, - u8 Priority, u8 Trigger); - -/* - * Initialization functions in xscugic_sinit.c - */ -XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId); - -/* - * Interrupt functions in xscugic_intr.c - */ -void XScuGic_InterruptHandler(XScuGic *InstancePtr); - -/* - * Self-test functions in xscugic_selftest.c - */ -int XScuGic_SelfTest(XScuGic *InstancePtr); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xscugic_hw.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xscugic_hw.h deleted file mode 100644 index 4f8354fe9afcb6aa32092c31a57c4c65d8aee2ce..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xscugic_hw.h +++ /dev/null @@ -1,641 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xscugic_hw.h -* -* This header file contains identifiers and HW access functions (or -* macros) that can be used to access the device. The user should refer to the -* hardware device specification for more details of the device operation. -* The driver functions/APIs are defined in xscugic.h. -* -* This GIC device has two parts, a distributor and CPU interface(s). Each part -* has separate register definition sections. -* -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------------- -* 1.00a drg 01/19/10 First release -* 1.01a sdm 11/09/11 "xil_exception.h" added as include. -* Macros XScuGic_EnableIntr and XScuGic_DisableIntr are -* added to enable or disable interrupts based on -* Distributor Register base address. Normally users use -* XScuGic instance and call XScuGic_Enable or -* XScuGic_Disable to enable/disable interrupts. These -* new macros are provided when user does not want to -* use an instance pointer but still wants to enable or -* disable interrupts. -* Function prototypes for functions (present in newly -* added file xscugic_hw.c) are added. -* 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR -* 702687). -* 1.04a hk 05/04/13 Fix for CR#705621. Moved function prototypes -* XScuGic_SetPriTrigTypeByDistAddr and -* XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h -* -* </pre> -* -******************************************************************************/ - -#ifndef XSCUGIC_HW_H /* prevent circular inclusions */ -#define XSCUGIC_HW_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xil_io.h" -#include "xil_exception.h" - -/************************** Constant Definitions *****************************/ - -/* - * The maximum number of interrupts supported by the hardware. - */ -#define XSCUGIC_MAX_NUM_INTR_INPUTS 95 - -/* - * The maximum priority value that can be used in the GIC. - */ -#define XSCUGIC_MAX_INTR_PRIO_VAL 248 -#define XSCUGIC_INTR_PRIO_MASK 0xF8 - -/** @name Distributor Interface Register Map - * - * Define the offsets from the base address for all Distributor registers of - * the interrupt controller, some registers may be reserved in the hardware - * device. - * @{ - */ -#define XSCUGIC_DIST_EN_OFFSET 0x00000000 /**< Distributor Enable - Register */ -#define XSCUGIC_IC_TYPE_OFFSET 0x00000004 /**< Interrupt Controller - Type Register */ -#define XSCUGIC_DIST_IDENT_OFFSET 0x00000008 /**< Implementor ID - Register */ -#define XSCUGIC_SECURITY_OFFSET 0x00000080 /**< Interrupt Security - Register */ -#define XSCUGIC_ENABLE_SET_OFFSET 0x00000100 /**< Enable Set - Register */ -#define XSCUGIC_DISABLE_OFFSET 0x00000180 /**< Enable Clear Register */ -#define XSCUGIC_PENDING_SET_OFFSET 0x00000200 /**< Pending Set - Register */ -#define XSCUGIC_PENDING_CLR_OFFSET 0x00000280 /**< Pending Clear - Register */ -#define XSCUGIC_ACTIVE_OFFSET 0x00000300 /**< Active Status Register */ -#define XSCUGIC_PRIORITY_OFFSET 0x00000400 /**< Priority Level Register */ -#define XSCUGIC_SPI_TARGET_OFFSET 0x00000800 /**< SPI Target - Register 0x800-0x8FB */ -#define XSCUGIC_INT_CFG_OFFSET 0x00000C00 /**< Interrupt Configuration - Register 0xC00-0xCFC */ -#define XSCUGIC_PPI_STAT_OFFSET 0x00000D00 /**< PPI Status Register */ -#define XSCUGIC_SPI_STAT_OFFSET 0x00000D04 /**< SPI Status Register - 0xd04-0xd7C */ -#define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80 /**< AHB Configuration - Register */ -#define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00 /**< Software Triggered - Interrupt Register */ -#define XSCUGIC_PERPHID_OFFSET 0x00000FD0 /**< Peripheral ID Reg */ -#define XSCUGIC_PCELLID_OFFSET 0x00000FF0 /**< Pcell ID Register */ -/* @} */ - -/** @name Distributor Enable Register - * Controls if the distributor response to external interrupt inputs. - * @{ - */ -#define XSCUGIC_EN_INT_MASK 0x00000001 /**< Interrupt In Enable */ -/* @} */ - -/** @name Interrupt Controller Type Register - * @{ - */ -#define XSCUGIC_LSPI_MASK 0x0000F800 /**< Number of Lockable - Shared Peripheral - Interrupts*/ -#define XSCUGIC_DOMAIN_MASK 0x00000400 /**< Number os Security domains*/ -#define XSCUGIC_CPU_NUM_MASK 0x000000E0 /**< Number of CPU Interfaces */ -#define XSCUGIC_NUM_INT_MASK 0x0000001F /**< Number of Interrupt IDs */ -/* @} */ - -/** @name Implementor ID Register - * Implementor and revision information. - * @{ - */ -#define XSCUGIC_REV_MASK 0x00FFF000 /**< Revision Number */ -#define XSCUGIC_IMPL_MASK 0x00000FFF /**< Implementor */ -/* @} */ - -/** @name Interrupt Security Registers - * Each bit controls the security level of an interrupt, either secure or non - * secure. These registers can only be accessed using secure read and write. - * There are registers for each of the CPU interfaces at offset 0x080. A - * register set for the SPI interrupts is available to all CPU interfaces. - * There are up to 32 of these registers staring at location 0x084. - * @{ - */ -#define XSCUGIC_INT_NS_MASK 0x00000001 /**< Each bit corresponds to an - INT_ID */ -/* @} */ - -/** @name Enable Set Register - * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is - * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a - * bit to 0. - * There are registers for each of the CPU interfaces at offset 0x100. With up - * to 8 registers aliased to the same address. A register set for the SPI - * interrupts is available to all CPU interfaces. - * There are up to 32 of these registers staring at location 0x104. - * @{ - */ -#define XSCUGIC_INT_EN_MASK 0x00000001 /**< Each bit corresponds to an - INT_ID */ -/* @} */ - -/** @name Enable Clear Register - * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is - * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and - * sets the corresponding bit to 0. - * There are registers for each of the CPU interfaces at offset 0x180. With up - * to 8 registers aliased to the same address. - * A register set for the SPI interrupts is available to all CPU interfaces. - * There are up to 32 of these registers staring at location 0x184. - * @{ - */ -#define XSCUGIC_INT_CLR_MASK 0x00000001 /**< Each bit corresponds to an - INT_ID */ -/* @} */ - -/** @name Pending Set Register - * Each bit controls the Pending or Active and Pending state of an interrupt, a - * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets - * an interrupt to the pending state. - * There are registers for each of the CPU interfaces at offset 0x200. With up - * to 8 registers aliased to the same address. - * A register set for the SPI interrupts is available to all CPU interfaces. - * There are up to 32 of these registers staring at location 0x204. - * @{ - */ -#define XSCUGIC_PEND_SET_MASK 0x00000001 /**< Each bit corresponds to an - INT_ID */ -/* @} */ - -/** @name Pending Clear Register - * Each bit can clear the Pending or Active and Pending state of an interrupt, a - * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 - * clears the pending state of an interrupt. - * There are registers for each of the CPU interfaces at offset 0x280. With up - * to 8 registers aliased to the same address. - * A register set for the SPI interrupts is available to all CPU interfaces. - * There are up to 32 of these registers staring at location 0x284. - * @{ - */ -#define XSCUGIC_PEND_CLR_MASK 0x00000001 /**< Each bit corresponds to an - INT_ID */ -/* @} */ - -/** @name Active Status Register - * Each bit provides the Active status of an interrupt, a - * 0 is not Active, a 1 is Active. This is a read only register. - * There are registers for each of the CPU interfaces at offset 0x300. With up - * to 8 registers aliased to each address. - * A register set for the SPI interrupts is available to all CPU interfaces. - * There are up to 32 of these registers staring at location 0x380. - * @{ - */ -#define XSCUGIC_ACTIVE_MASK 0x00000001 /**< Each bit corresponds to an - INT_ID */ -/* @} */ - -/** @name Priority Level Register - * Each byte in a Priority Level Register sets the priority level of an - * interrupt. Reading the register provides the priority level of an interrupt. - * There are registers for each of the CPU interfaces at offset 0x400 through - * 0x41C. With up to 8 registers aliased to each address. - * 0 is highest priority, 0xFF is lowest. - * A register set for the SPI interrupts is available to all CPU interfaces. - * There are up to 255 of these registers staring at location 0x420. - * @{ - */ -#define XSCUGIC_PRIORITY_MASK 0x000000FF /**< Each Byte corresponds to an - INT_ID */ -#define XSCUGIC_PRIORITY_MAX 0x000000FF /**< Highest value of a priority - actually the lowest priority*/ -/* @} */ - -/** @name SPI Target Register 0x800-0x8FB - * Each byte references a separate SPI and programs which of the up to 8 CPU - * interfaces are sent a Pending interrupt. - * There are registers for each of the CPU interfaces at offset 0x800 through - * 0x81C. With up to 8 registers aliased to each address. - * A register set for the SPI interrupts is available to all CPU interfaces. - * There are up to 255 of these registers staring at location 0x820. - * - * This driver does not support multiple CPU interfaces. These are included - * for complete documentation. - * @{ - */ -#define XSCUGIC_SPI_CPU7_MASK 0x00000080 /**< CPU 7 Mask*/ -#define XSCUGIC_SPI_CPU6_MASK 0x00000040 /**< CPU 6 Mask*/ -#define XSCUGIC_SPI_CPU5_MASK 0x00000020 /**< CPU 5 Mask*/ -#define XSCUGIC_SPI_CPU4_MASK 0x00000010 /**< CPU 4 Mask*/ -#define XSCUGIC_SPI_CPU3_MASK 0x00000008 /**< CPU 3 Mask*/ -#define XSCUGIC_SPI_CPU2_MASK 0x00000003 /**< CPU 2 Mask*/ -#define XSCUGIC_SPI_CPU1_MASK 0x00000002 /**< CPU 1 Mask*/ -#define XSCUGIC_SPI_CPU0_MASK 0x00000001 /**< CPU 0 Mask*/ -/* @} */ - -/** @name Interrupt Configuration Register 0xC00-0xCFC - * The interrupt configuration registers program an SFI to be active HIGH level - * sensitive or rising edge sensitive. - * Each bit pair describes the configuration for an INT_ID. - * SFI Read Only b10 always - * PPI Read Only depending on how the PPIs are configured. - * b01 Active HIGH level sensitive - * b11 Rising edge sensitive - * SPI LSB is read only. - * b01 Active HIGH level sensitive - * b11 Rising edge sensitive/ - * There are registers for each of the CPU interfaces at offset 0xC00 through - * 0xC04. With up to 8 registers aliased to each address. - * A register set for the SPI interrupts is available to all CPU interfaces. - * There are up to 255 of these registers staring at location 0xC08. - * @{ - */ -#define XSCUGIC_INT_CFG_MASK 0x00000003 /**< */ -/* @} */ - -/** @name PPI Status Register - * Enables an external AMBA master to access the status of the PPI inputs. - * A CPU can only read the status of its local PPI signals and cannot read the - * status for other CPUs. - * This register is aliased for each CPU interface. - * @{ - */ -#define XSCUGIC_PPI_C15_MASK 0x00008000 /**< PPI Status */ -#define XSCUGIC_PPI_C14_MASK 0x00004000 /**< PPI Status */ -#define XSCUGIC_PPI_C13_MASK 0x00002000 /**< PPI Status */ -#define XSCUGIC_PPI_C12_MASK 0x00001000 /**< PPI Status */ -#define XSCUGIC_PPI_C11_MASK 0x00000800 /**< PPI Status */ -#define XSCUGIC_PPI_C10_MASK 0x00000400 /**< PPI Status */ -#define XSCUGIC_PPI_C09_MASK 0x00000200 /**< PPI Status */ -#define XSCUGIC_PPI_C08_MASK 0x00000100 /**< PPI Status */ -#define XSCUGIC_PPI_C07_MASK 0x00000080 /**< PPI Status */ -#define XSCUGIC_PPI_C06_MASK 0x00000040 /**< PPI Status */ -#define XSCUGIC_PPI_C05_MASK 0x00000020 /**< PPI Status */ -#define XSCUGIC_PPI_C04_MASK 0x00000010 /**< PPI Status */ -#define XSCUGIC_PPI_C03_MASK 0x00000008 /**< PPI Status */ -#define XSCUGIC_PPI_C02_MASK 0x00000004 /**< PPI Status */ -#define XSCUGIC_PPI_C01_MASK 0x00000002 /**< PPI Status */ -#define XSCUGIC_PPI_C00_MASK 0x00000001 /**< PPI Status */ -/* @} */ - -/** @name SPI Status Register 0xd04-0xd7C - * Enables an external AMBA master to access the status of the SPI inputs. - * There are up to 63 registers if the maximum number of SPI inputs are - * configured. - * @{ - */ -#define XSCUGIC_SPI_N_MASK 0x00000001 /**< Each bit corresponds to an SPI - input */ -/* @} */ - -/** @name AHB Configuration Register - * Provides the status of the CFGBIGEND input signal and allows the endianess - * of the GIC to be set. - * @{ - */ -#define XSCUGIC_AHB_END_MASK 0x00000004 /**< 0-GIC uses little Endian, - 1-GIC uses Big Endian */ -#define XSCUGIC_AHB_ENDOVR_MASK 0x00000002 /**< 0-Uses CFGBIGEND control, - 1-use the AHB_END bit */ -#define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001 /**< State of CFGBIGEND */ - -/* @} */ - -/** @name Software Triggered Interrupt Register - * Controls issueing of software interrupts. - * @{ - */ -#define XSCUGIC_SFI_SELFTRIG_MASK 0x02010000 -#define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000 /**< Target List filter - b00-Use the target List - b01-All CPUs except requester - b10-To Requester - b11-reserved */ -#define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000 /**< CPU Target list */ -#define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000 /**< 0= Use a secure interrupt */ -#define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000F /**< Set to the INTID - signaled to the CPU*/ -/* @} */ - -/** @name CPU Interface Register Map - * - * Define the offsets from the base address for all CPU registers of the - * interrupt controller, some registers may be reserved in the hardware device. - * @{ - */ -#define XSCUGIC_CONTROL_OFFSET 0x00000000 /**< CPU Interface Control - Register */ -#define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004 /**< Priority Mask Reg */ -#define XSCUGIC_BIN_PT_OFFSET 0x00000008 /**< Binary Point Register */ -#define XSCUGIC_INT_ACK_OFFSET 0x0000000C /**< Interrupt ACK Reg */ -#define XSCUGIC_EOI_OFFSET 0x00000010 /**< End of Interrupt Reg */ -#define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014 /**< Running Priority Reg */ -#define XSCUGIC_HI_PEND_OFFSET 0x00000018 /**< Highest Pending Interrupt - Register */ -#define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001C /**< Aliased non-Secure - Binary Point Register */ - -/**< 0x00000020 to 0x00000FBC are reserved and should not be read or written - * to. */ -/* @} */ - - -/** @name Control Register - * CPU Interface Control register definitions - * All bits are defined here although some are not available in the non-secure - * mode. - * @{ - */ -#define XSCUGIC_CNTR_SBPR_MASK 0x00000010 /**< Secure Binary Pointer, - 0=separate registers, - 1=both use bin_pt_s */ -#define XSCUGIC_CNTR_FIQEN_MASK 0x00000008 /**< Use nFIQ_C for secure - interrupts, - 0= use IRQ for both, - 1=Use FIQ for secure, IRQ for non*/ -#define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004 /**< Ack control for secure or non secure */ -#define XSCUGIC_CNTR_EN_NS_MASK 0x00000002 /**< Non Secure enable */ -#define XSCUGIC_CNTR_EN_S_MASK 0x00000001 /**< Secure enable, 0=Disabled, 1=Enabled */ -/* @} */ - -/** @name Priority Mask Register - * Priority Mask register definitions - * The CPU interface does not send interrupt if the level of the interrupt is - * lower than the level of the register. - * @{ - */ -#define XSCUGIC_PRIORITY_MASK 0x000000FF /**< All interrupts */ -/* @} */ - -/** @name Binary Point Register - * Binary Point register definitions - * @{ - */ - -#define XSCUGIC_BIN_PT_MASK 0x00000007 /**< Binary point mask value - Value Secure Non-secure - b000 0xFE 0xFF - b001 0xFC 0xFE - b010 0xF8 0xFC - b011 0xF0 0xF8 - b100 0xE0 0xF0 - b101 0xC0 0xE0 - b110 0x80 0xC0 - b111 0x00 0x80 - */ -/*@}*/ - -/** @name Interrupt Acknowledge Register - * Interrupt Acknowledge register definitions - * Identifies the current Pending interrupt, and the CPU ID for software - * interrupts. - */ -#define XSCUGIC_ACK_INTID_MASK 0x000003FF /**< Interrupt ID */ -#define XSCUGIC_CPUID_MASK 0x00000C00 /**< CPU ID */ -/* @} */ - -/** @name End of Interrupt Register - * End of Interrupt register definitions - * Allows the CPU to signal the GIC when it completes an interrupt service - * routine. - */ -#define XSCUGIC_EOI_INTID_MASK 0x000003FF /**< Interrupt ID */ - -/* @} */ - -/** @name Running Priority Register - * Running Priority register definitions - * Identifies the interrupt priority level of the highest priority active - * interrupt. - */ -#define XSCUGIC_RUN_PRIORITY_MASK 0x00000FF /**< Interrupt Priority */ -/* @} */ - -/* - * Highest Pending Interrupt register definitions - * Identifies the interrupt priority of the highest priority pending interupt - */ -#define XSCUGIC_PEND_INTID_MASK 0x000003FF /**< Pending Interrupt ID */ -#define XSCUGIC_CPUID_MASK 0x00000C00 /**< CPU ID */ -/* @} */ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/****************************************************************************/ -/** -* -* Read the Interrupt Configuration Register offset for an interrupt id. -* -* @param InterruptID is the interrupt number. -* -* @return The 32-bit value of the offset -* -* @note -* -*****************************************************************************/ -#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \ - (XSCUGIC_INT_CFG_OFFSET + ((InterruptID/16) * 4)) - -/****************************************************************************/ -/** -* -* Read the Interrupt Priority Register offset for an interrupt id. -* -* @param InterruptID is the interrupt number. -* -* @return The 32-bit value of the offset -* -* @note -* -*****************************************************************************/ -#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \ - (XSCUGIC_PRIORITY_OFFSET + ((InterruptID/4) * 4)) - -/****************************************************************************/ -/** -* -* Read the SPI Target Register offset for an interrupt id. -* -* @param InterruptID is the interrupt number. -* -* @return The 32-bit value of the offset -* -* @note -* -*****************************************************************************/ -#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \ - (XSCUGIC_SPI_TARGET_OFFSET + ((InterruptID/4) * 4)) - -/****************************************************************************/ -/** -* -* Read the Interrupt Clear-Enable Register offset for an interrupt ID -* -* @param Register is the register offset for the clear/enable bank. -* @param InterruptID is the interrupt number. -* -* @return The 32-bit value of the offset -* -* @note -* -*****************************************************************************/ -#define XSCUGIC_ENABLE_DISABLE_OFFSET_CALC(Register, InterruptID) \ - (Register + ((InterruptID/32) * 4)) - -/****************************************************************************/ -/** -* -* Read the given Intc register. -* -* @param BaseAddress is the base address of the device. -* @param RegOffset is the register offset to be read -* -* @return The 32-bit value of the register -* -* @note -* C-style signature: -* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset) -* -*****************************************************************************/ -#define XScuGic_ReadReg(BaseAddress, RegOffset) \ - (Xil_In32((BaseAddress) + (RegOffset))) - - -/****************************************************************************/ -/** -* -* Write the given Intc register. -* -* @param BaseAddress is the base address of the device. -* @param RegOffset is the register offset to be written -* @param Data is the 32-bit value to write to the register -* -* @return None. -* -* @note -* C-style signature: -* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) -* -*****************************************************************************/ -#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \ - (Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)Data))) - - -/****************************************************************************/ -/** -* -* Enable specific interrupt(s) in the interrupt controller. -* -* @param DistBaseAddress is the Distributor Register base address of the -* device -* @param Int_Id is the ID of the interrupt source and should be in the -* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1 -* -* @return None. -* -* @note C-style signature: -* void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id); -* -*****************************************************************************/ -#define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \ - XScuGic_WriteReg((DistBaseAddress), \ - XSCUGIC_ENABLE_SET_OFFSET + ((Int_Id / 32) * 4), \ - (1 << (Int_Id % 32))) - -/****************************************************************************/ -/** -* -* Disable specific interrupt(s) in the interrupt controller. -* -* @param DistBaseAddress is the Distributor Register base address of the -* device -* @param Int_Id is the ID of the interrupt source and should be in the -* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1 -* -* -* @return None. -* -* @note C-style signature: -* void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id); -* -*****************************************************************************/ -#define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \ - XScuGic_WriteReg((DistBaseAddress), \ - XSCUGIC_DISABLE_OFFSET + ((Int_Id / 32) * 4), \ - (1 << (Int_Id % 32))) - - -/************************** Function Prototypes ******************************/ - -void XScuGic_DeviceInterruptHandler(void *DeviceId); -int XScuGic_DeviceInitialize(u32 DeviceId); -void XScuGic_RegisterHandler(u32 BaseAddress, int InterruptId, - Xil_InterruptHandler Handler, void *CallBackRef); -void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, - u8 Priority, u8 Trigger); -void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, - u8 *Priority, u8 *Trigger); -/************************** Variable Definitions *****************************/ -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xscutimer.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xscutimer.h deleted file mode 100644 index 464cf22a15505972c9a91be2f8d66b82838a221a..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xscutimer.h +++ /dev/null @@ -1,365 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file xscutimer.h -* -* The timer driver supports the Cortex A9 private timer. -* -* The timer driver supports the following features: -* - Normal mode and Auto reload mode -* - Interrupts (Interrupt handler is not provided in this driver. Application -* has to register it's own handler) -* -* <b> Initialization and Configuration </b> -* -* The device driver enables higher layer software (e.g., an application) to -* communicate with the Timer. -* -* XScuTimer_CfgInitialize() API is used to initialize the Timer. The -* user needs to first call the XScuTimer_LookupConfig() API which returns -* the Configuration structure pointer which is passed as a parameter to -* the XScuTimer_CfgInitialize() API. -* -* <b> Interrupts </b> -* -* The Timer hardware supports interrupts. -* -* This driver does not provide a Interrupt Service Routine (ISR) for the device. -* It is the responsibility of the application to provide one if needed. Refer to -* the interrupt example provided with this driver for details on using the -* Timer in interrupt mode. -* -* <b> Virtual Memory </b> -* -* This driver supports Virtual Memory. The RTOS is responsible for calculating -* the correct device base address in Virtual Memory space. -* -* <b> Threads </b> -* -* This driver is not thread safe. Any needs for threads or thread mutual -* exclusion must be satisfied by the layer above this driver. -* -* <b> Asserts </b> -* -* Asserts are used within all Xilinx drivers to enforce constraints on argument -* values. Asserts can be turned off on a system-wide basis by defining, at -* compile time, the NDEBUG identifier. By default, asserts are turned on and it -* is recommended that users leave asserts on during development. -* -* <b> Building the driver </b> -* -* The XScuTimer driver is composed of several source files. This allows the user -* to build and link only those parts of the driver that are necessary. -* -* <br><br> -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- --------------------------------------------- -* 1.00a nm 03/10/10 First release -* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue -* when the xstatus.h in the common driver overwrites -* the xstatus.h of the standalone BSP during the -* libgen. -* </pre> -* -******************************************************************************/ -#ifndef XSCUTIMER_H /* prevent circular inclusions */ -#define XSCUTIMER_H /* by using protection macros */ - -/***************************** Include Files *********************************/ - -#include "xstatus.h" -#include "xscutimer_hw.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/** - * This typedef contains configuration information for the device. - */ -typedef struct { - u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddr; /**< Base address of the device */ -} XScuTimer_Config; - -/** - * The XScuTimer driver instance data. The user is required to allocate a - * variable of this type for every timer device in the system. - * A pointer to a variable of this type is then passed to the driver API - * functions. - */ -typedef struct { - XScuTimer_Config Config; /**< Hardware Configuration */ - u32 IsReady; /**< Device is initialized and ready */ - u32 IsStarted; /**< Device timer is running */ -} XScuTimer; - -/***************** Macros (Inline Functions) Definitions *********************/ - -/****************************************************************************/ -/** -* -* Check if the timer has expired. -* -* @param InstancePtr is a pointer to the XScuTimer instance. -* -* @return -* - TRUE if the timer has expired. -* - FALSE if the timer has not expired. -* -* @note C-style signature: -* int XScuTimer_IsExpired(XScuTimer *InstancePtr) -* -******************************************************************************/ -#define XScuTimer_IsExpired(InstancePtr) \ - ((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_ISR_OFFSET) & \ - XSCUTIMER_ISR_EVENT_FLAG_MASK) == \ - XSCUTIMER_ISR_EVENT_FLAG_MASK) - -/****************************************************************************/ -/** -* -* Re-start the timer. This macro will read the timer load register -* and writes the same value to load register to update the counter register. -* -* @param InstancePtr is a pointer to the XScuTimer instance. -* -* @return None. -* -* @note C-style signature: -* void XScuTimer_RestartTimer(XScuTimer *InstancePtr) -* -******************************************************************************/ -#define XScuTimer_RestartTimer(InstancePtr) \ - XScuTimer_LoadTimer(InstancePtr, \ - XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_LOAD_OFFSET)) - -/****************************************************************************/ -/** -* -* Write to the timer load register. This will also update the -* timer counter register with the new value. This macro can be used to -* change the time-out value. -* -* @param InstancePtr is a pointer to the XScuTimer instance. -* @param Value is the count to be loaded in to the load register. -* -* @return None. -* -* @note C-style signature: -* void XScuTimer_LoadTimer(XScuTimer *InstancePtr, u32 Value) -* -******************************************************************************/ -#define XScuTimer_LoadTimer(InstancePtr, Value) \ - XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_LOAD_OFFSET, Value) - -/****************************************************************************/ -/** -* -* Returns the current timer counter register value. It can be called at any -* time. -* -* @param InstancePtr is a pointer to the XScuTimer instance. -* -* @return Contents of the timer counter register. -* -* @note C-style signature: - u32 XScuTimer_GetCounterValue(XScuTimer *InstancePtr) -* -******************************************************************************/ -#define XScuTimer_GetCounterValue(InstancePtr) \ - XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_COUNTER_OFFSET) - -/****************************************************************************/ -/** -* -* Enable auto-reload mode. -* -* @param InstancePtr is a pointer to the XScuTimer instance. -* -* @return None. -* -* @note C-style signature: -* void XScuTimer_EnableAutoReload(XScuTimer *InstancePtr) -* -******************************************************************************/ -#define XScuTimer_EnableAutoReload(InstancePtr) \ - XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET, \ - (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET) | \ - XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)) - -/****************************************************************************/ -/** -* -* Disable auto-reload mode. -* -* @param InstancePtr is a pointer to the XScuTimer instance. -* -* @return None. -* -* @note C-style signature: -* void XScuTimer_DisableAutoReload(XScuTimer *InstancePtr) -* -******************************************************************************/ -#define XScuTimer_DisableAutoReload(InstancePtr) \ - XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET, \ - (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET) & \ - ~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))) - -/****************************************************************************/ -/** -* -* Enable the Timer interrupt. -* -* @param InstancePtr is a pointer to the XScuTimer instance. -* -* @return None. -* -* @note C-style signature: -* void XScuTimer_EnableInterrupt(XScuTimer *InstancePtr) -* -******************************************************************************/ -#define XScuTimer_EnableInterrupt(InstancePtr) \ - XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET, \ - (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET) | \ - XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)) - -/****************************************************************************/ -/** -* -* Disable the Timer interrupt. -* -* @param InstancePtr is a pointer to the XScuTimer instance. -* -* @return None. -* -* @note C-style signature: -* void XScuTimer_DisableInterrupt(XScuTimer *InstancePtr) -* -******************************************************************************/ -#define XScuTimer_DisableInterrupt(InstancePtr) \ - XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET, \ - (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET) & \ - ~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))) - -/*****************************************************************************/ -/** -* -* This function reads the interrupt status. -* -* @param InstancePtr is a pointer to the XScuTimer instance. -* -* @return None. -* -* @note C-style signature: -* void XScuTimer_GetInterruptStatus(XScuTimer *InstancePtr) -* -******************************************************************************/ -#define XScuTimer_GetInterruptStatus(InstancePtr) \ - XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_ISR_OFFSET) - -/*****************************************************************************/ -/** -* -* This function clears the interrupt status. -* -* @param InstancePtr is a pointer to the XScuTimer instance. -* -* @return None. -* -* @note C-style signature: -* void XScuTimer_ClearInterruptStatus(XScuTimer *InstancePtr) -* -******************************************************************************/ -#define XScuTimer_ClearInterruptStatus(InstancePtr) \ - XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK) - -/************************** Function Prototypes ******************************/ - -/* - * Lookup configuration in xscutimer_sinit.c - */ -XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId); - -/* - * Selftest function in xscutimer_selftest.c - */ -int XScuTimer_SelfTest(XScuTimer *InstancePtr); - -/* - * Interface functions in xscutimer.c - */ -int XScuTimer_CfgInitialize(XScuTimer *InstancePtr, - XScuTimer_Config *ConfigPtr, u32 EffectiveAddress); -void XScuTimer_Start(XScuTimer *InstancePtr); -void XScuTimer_Stop(XScuTimer *InstancePtr); -void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue); -u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xscutimer_hw.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xscutimer_hw.h deleted file mode 100644 index d18cf6366254e6e83ef4ea7d76b7baa9993b2810..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xscutimer_hw.h +++ /dev/null @@ -1,292 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file xscutimer_hw.h -* -* This file contains the hardware interface to the Timer. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- --------------------------------------------- -* 1.00a nm 03/10/10 First release -* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control -* and interrupt registers -* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue -* when the xstatus.h in the common driver overwrites -* the xstatus.h of the standalone BSP during the -* libgen. -* </pre> -* -******************************************************************************/ -#ifndef XSCUTIMER_HW_H /* prevent circular inclusions */ -#define XSCUTIMER_HW_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ -#include "xil_types.h" -#include "xil_io.h" -#include "xil_assert.h" -/************************** Constant Definitions *****************************/ - -/** @name Register Map - * Offsets of registers from the start of the device - * @{ - */ - -#define XSCUTIMER_LOAD_OFFSET 0x00 /**< Timer Load Register */ -#define XSCUTIMER_COUNTER_OFFSET 0x04 /**< Timer Counter Register */ -#define XSCUTIMER_CONTROL_OFFSET 0x08 /**< Timer Control Register */ -#define XSCUTIMER_ISR_OFFSET 0x0C /**< Timer Interrupt - Status Register */ -/* @} */ - -/** @name Timer Control register - * This register bits control the prescaler, Intr enable, - * auto-reload and timer enable. - * @{ - */ - -#define XSCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00 /**< Prescaler */ -#define XSCUTIMER_CONTROL_PRESCALER_SHIFT 8 -#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004 /**< Intr enable */ -#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002 /**< Auto-reload */ -#define XSCUTIMER_CONTROL_ENABLE_MASK 0x00000001 /**< Timer enable */ -/* @} */ - -/** @name Interrupt Status register - * This register indicates the Timer counter register has reached zero. - * @{ - */ - -#define XSCUTIMER_ISR_EVENT_FLAG_MASK 0x00000001 /**< Event flag */ -/*@}*/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/****************************************************************************/ -/** -* -* Write to the timer load register. This will also update the -* timer counter register with the new value. This macro can be used to -* change the time-out value. -* -* @param BaseAddr is the base address of the scu timer. -* @param Value is the count to be loaded in to the load register. -* -* @return None. -* -* @note C-style signature: -* void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value) -* -******************************************************************************/ -#define XScuTimer_SetLoadReg(BaseAddr, Value) \ - XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, Value) - -/****************************************************************************/ -/** -* -* Returns the current timer load register value. -* -* @param BaseAddr is the base address of the scu timer. -* -* @return Contents of the timer load register. -* -* @note C-style signature: -* u32 XScuTimer_GetLoadReg(u32 BaseAddr) -* -******************************************************************************/ -#define XScuTimer_GetLoadReg(BaseAddr) \ - XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET) - -/****************************************************************************/ -/** -* -* Write to the timer counter register. -* -* @param BaseAddr is the base address of the scu timer. -* @param Value is the count to be loaded in to the counter register. -* -* @return None. -* -* @note C-style signature: -* void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value) -* -******************************************************************************/ -#define XScuTimer_SetCounterReg(BaseAddr, Value) \ - XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, Value) - -/****************************************************************************/ -/** -* -* Returns the current timer counter register value. -* -* @param BaseAddr is the base address of the scu timer. -* -* @return Contents of the timer counter register. -* -* @note C-style signature: - u32 XScuTimer_GetCounterReg(u32 BaseAddr) -* -******************************************************************************/ -#define XScuTimer_GetCounterReg(BaseAddr) \ - XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET) - -/****************************************************************************/ -/** -* -* Write to the timer load register. This will also update the -* timer counter register with the new value. This macro can be used to -* change the time-out value. -* -* @param BaseAddr is the base address of the scu timer. -* @param Value is the count to be loaded in to the load register. -* -* @return None. -* -* @note C-style signature: -* void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value) -* -******************************************************************************/ -#define XScuTimer_SetControlReg(BaseAddr, Value) \ - XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, Value) - -/****************************************************************************/ -/** -* -* Returns the current timer load register value. -* -* @param BaseAddr is the base address of the scu timer. -* -* @return Contents of the timer load register. -* -* @note C-style signature: - u32 XScuTimer_GetControlReg(u32 BaseAddr) -* -******************************************************************************/ -#define XScuTimer_GetControlReg(BaseAddr) \ - XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET) - -/****************************************************************************/ -/** -* -* Write to the timer counter register. -* -* @param BaseAddr is the base address of the scu timer. -* @param Value is the count to be loaded in to the counter register. -* -* @return None. -* -* @note C-style signature: -* void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value) -* -******************************************************************************/ -#define XScuTimer_SetIntrReg(BaseAddr, Value) \ - XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, Value) - -/****************************************************************************/ -/** -* -* Returns the current timer counter register value. -* -* @param BaseAddr is the base address of the scu timer. -* -* @return Contents of the timer counter register. -* -* @note C-style signature: - u32 XScuTimer_GetIntrReg(u32 BaseAddr) -* -******************************************************************************/ -#define XScuTimer_GetIntrReg(BaseAddr) \ - XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET) - -/****************************************************************************/ -/** -* -* Read from the given Timer register. -* -* @param BaseAddr is the base address of the device -* @param RegOffset is the register offset to be read -* -* @return The 32-bit value of the register -* -* @note C-style signature: -* u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset) -* -*****************************************************************************/ -#define XScuTimer_ReadReg(BaseAddr, RegOffset) \ - Xil_In32((BaseAddr) + (RegOffset)) - -/****************************************************************************/ -/** -* -* Write to the given Timer register. -* -* @param BaseAddr is the base address of the device -* @param RegOffset is the register offset to be written -* @param Data is the 32-bit value to write to the register -* -* @return None. -* -* @note C-style signature: -* void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data) -* -*****************************************************************************/ -#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data) \ - Xil_Out32((BaseAddr) + (RegOffset), (Data)) - -/************************** Function Prototypes ******************************/ - -/************************** Variable Definitions *****************************/ - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xscuwdt.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xscuwdt.h deleted file mode 100644 index 39ecd7d18b9bbf5e32810c3672533457ccfed790..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xscuwdt.h +++ /dev/null @@ -1,384 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file xscuwdt.h -* -* The Xilinx SCU watchdog timer driver (XScuWdt) supports the Xilinx SCU private -* watchdog timer hardware. -* -* The XScuWdt driver supports the following features: -* - Watchdog mode -* - Timer mode -* - Auto reload (timer mode only) -* -* The watchdog counter register is a down counter and starts decrementing when -* the watchdog is started. -* In watchdog mode, when the counter reaches 0, the Reset flag is set in the -* Reset status register and the WDRESETREQ pin is asserted, causing a system -* reset. The Reset flag is not reset by normal processor reset and is cleared -* when written with a value of 1. This enables the user to differentiate a -* normal reset and a reset caused by watchdog time-out. The user needs to call -* XScuWdt_RestartWdt() periodically, to avoid the watchdog from being timed-out. -* -* The IsWdtExpired function can be used to check if the watchdog was the cause -* of the last reset. In this situation, call Initialize then call IsWdtExpired. -* If the result is true, watchdog timeout caused the last system reset. The -* application then needs to clear the Reset flag. -* -* In timer mode, when the counter reaches 0, the Event flag is set in the -* Interrupt status register and if interrupts are enabled, interrupt ID 30 is -* set as pending in the interrupt distributor. The IsTimerExpired function -* is used to check if the watchdog counter has decremented to 0 in timer mode. -* If auto-reload mode is enabled, the Counter register is automatically reloaded -* from the Load register. -* -* <b> Initialization and Configuration </b> -* -* The device driver enables higher layer software (e.g., an application) to -* communicate with the Watchdog Timer. -* -* XScuWdt_CfgInitialize() API is used to initialize the Watchdog Timer. The -* user needs to first call the XScuWdt_LookupConfig() API which returns -* the Configuration structure pointer which is passed as a parameter to -* the XScuWdt_CfgInitialize() API. -* -* <b>Interrupts</b> -* -* The SCU Watchdog Timer supports interrupts in Timer mode. -* -* This driver does not provide a Interrupt Service Routine (ISR) for the device. -* It is the responsibility of the application to provide one if needed. Refer to -* the interrupt example provided with this driver for details on using the -* Timer in interrupt mode. -* -* <b> Virtual Memory </b> -* -* This driver supports Virtual Memory. The RTOS is responsible for calculating -* the correct device base address in Virtual Memory space. -* -* <b> Threads </b> -* -* This driver is not thread safe. Any needs for threads or thread mutual -* exclusion must be satisfied by the layer above this driver. -* -* <b> Asserts </b> -* -* Asserts are used within all Xilinx drivers to enforce constraints on argument -* values. Asserts can be turned off on a system-wide basis by defining, at -* compile time, the NDEBUG identifier. By default, asserts are turned on and it -* is recommended that users leave asserts on during development. -* -* <b> Building the driver </b> -* -* The XScuWdt driver is composed of several source files. This allows the user -* to build and link only those parts of the driver that are necessary. -* -* <br><br> -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- --------------------------------------------- -* 1.00a sdm 01/15/10 First release -* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue -* when the xstatus.h in the common driver overwrites -* the xstatus.h of the standalone BSP during the -* libgen. -* </pre> -* -******************************************************************************/ -#ifndef XSCUWDT_H /* prevent circular inclusions */ -#define XSCUWDT_H /* by using protection macros */ - -/***************************** Include Files *********************************/ - -#include "xstatus.h" -#include "xscuwdt_hw.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/** - * This typedef contains configuration information for the device. - */ -typedef struct { - u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddr; /**< Base address of the device */ -} XScuWdt_Config; - -/** - * The XScuWdt driver instance data. The user is required to allocate a - * variable of this type for every watchdog/timer device in the system. - * A pointer to a variable of this type is then passed to the driver API - * functions. - */ -typedef struct { - XScuWdt_Config Config;/**< Hardware Configuration */ - u32 IsReady; /**< Device is initialized and ready */ - u32 IsStarted; /**< Device watchdog timer is running */ -} XScuWdt; - -/***************** Macros (Inline Functions) Definitions *********************/ -/****************************************************************************/ -/** -* -* This function is used to check if the watchdog has timed-out and the last -* reset was caused by the watchdog reset. -* -* @param InstancePtr is a pointer to the XScuWdt instance. -* -* @return -* - TRUE if the watchdog has expired. -* - FALSE if the watchdog has not expired. -* -* @note C-style signature: -* int XScuWdt_IsWdtExpired(XScuWdt *InstancePtr) -* -******************************************************************************/ -#define XScuWdt_IsWdtExpired(InstancePtr) \ - ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUWDT_RST_STS_OFFSET) & \ - XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK) - -/****************************************************************************/ -/** -* -* This function is used to check if the watchdog counter has reached 0 in timer -* mode. -* -* @param InstancePtr is a pointer to the XScuWdt instance. -* -* @return -* - TRUE if the watchdog has expired. -* - FALSE if the watchdog has not expired. -* -* @note C-style signature: -* int XScuWdt_IsTimerExpired(XScuWdt *InstancePtr) -* -******************************************************************************/ -#define XScuWdt_IsTimerExpired(InstancePtr) \ - ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUWDT_ISR_OFFSET) & \ - XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK) - -/****************************************************************************/ -/** -* -* Re-start the watchdog timer. This macro will read the watchdog load register -* and write the same value to load register to update the counter register. -* An application needs to call this function periodically to keep the watchdog -* from asserting the WDRESETREQ reset request output pin. -* -* @param InstancePtr is a pointer to the XScuWdt instance. -* -* @return None. -* -* @note C-style signature: -* void XScuWdt_RestartWdt(XScuWdt *InstancePtr) -* -******************************************************************************/ -#define XScuWdt_RestartWdt(InstancePtr) \ - XScuWdt_LoadWdt(InstancePtr, \ - (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUWDT_LOAD_OFFSET))) - -/****************************************************************************/ -/** -* -* Write to the watchdog timer load register. This will also update the -* watchdog counter register with the new value. This macro can be used to -* change the time-out value. -* -* @param InstancePtr is a pointer to the XScuWdt instance. -* @param Value is the value to be written to the Watchdog Load register. -* -* @return None. -* -* @note C-style signature: -* void XScuWdt_LoadWdt(XScuWdt *InstancePtr, u32 Value) -* -******************************************************************************/ -#define XScuWdt_LoadWdt(InstancePtr, Value) \ - XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUWDT_LOAD_OFFSET, Value) - -/****************************************************************************/ -/** -* -* Put the watchdog timer in Watchdog mode by setting the WD mode bit of the -* Watchdog control register. -* -* @param InstancePtr is a pointer to the XScuWdt instance. -* -* @return None. -* -* @note C-style signature: -* void XScuWdt_SetWdMode(XScuWdt *InstancePtr) -* -******************************************************************************/ -#define XScuWdt_SetWdMode(InstancePtr) \ - XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUWDT_CONTROL_OFFSET, \ - (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUWDT_CONTROL_OFFSET) | \ - XSCUWDT_CONTROL_WD_MODE_MASK)) - -/****************************************************************************/ -/** -* -* Put the watchdog timer in Timer mode by writing 0x12345678 and 0x87654321 -* successively to the Watchdog Disable Register. -* The software must write 0x12345678 and 0x87654321 successively to the -* Watchdog Disable Register so that the watchdog mode bit in the Watchdog -* Control Register is set to zero. -* -* @param InstancePtr is a pointer to the XScuWdt instance. -* -* @return None. -* -* @note C-style signature: -* void XScuWdt_SetTimerMode(XScuWdt *InstancePtr) -* -******************************************************************************/ -#define XScuWdt_SetTimerMode(InstancePtr) \ -{ \ - XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUWDT_DISABLE_OFFSET, \ - XSCUWDT_DISABLE_VALUE1); \ - XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUWDT_DISABLE_OFFSET, \ - XSCUWDT_DISABLE_VALUE2); \ -} - -/****************************************************************************/ -/** -* -* Get the contents of the watchdog control register. -* -* @param InstancePtr is a pointer to the XScuWdt instance. -* -* @return Contents of the watchdog control register. -* -* @note C-style signature: - u32 XScuWdt_GetControlReg(XScuWdt *InstancePtr) -* -******************************************************************************/ -#define XScuWdt_GetControlReg(InstancePtr) \ - XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUWDT_CONTROL_OFFSET) - -/****************************************************************************/ -/** -* -* Write to the watchdog control register. -* -* @param InstancePtr is a pointer to the XScuWdt instance. -* @param ControlReg is the value to be written to the watchdog control -* register. -* -* @return None. -* -* @note C-style signature: - void XScuWdt_SetControlReg(XScuWdt *InstancePtr, u32 ControlReg) -* -******************************************************************************/ -#define XScuWdt_SetControlReg(InstancePtr, ControlReg) \ - XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUWDT_CONTROL_OFFSET, ControlReg) - -/****************************************************************************/ -/** -* -* Enable auto-reload mode. -* -* @param InstancePtr is a pointer to the XScuWdt instance. -* -* @return None. -* -* @note C-style signature: -* void XScuWdt_EnableAutoReload(XScuWdt *InstancePtr) -* -******************************************************************************/ -#define XScuWdt_EnableAutoReload(InstancePtr) \ - XScuWdt_SetControlReg((InstancePtr), \ - (XScuWdt_GetControlReg(InstancePtr) | \ - XSCUWDT_CONTROL_AUTO_RELOAD_MASK)) - -/************************** Function Prototypes ******************************/ - -/* - * Lookup configuration in xscuwdt_sinit.c. - */ -XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId); - -/* - * Selftest function in xscuwdt_selftest.c - */ -int XScuWdt_SelfTest(XScuWdt *InstancePtr); - -/* - * Interface functions in xscuwdt.c - */ -int XScuWdt_CfgInitialize(XScuWdt *InstancePtr, - XScuWdt_Config *ConfigPtr, u32 EffectiveAddress); - -void XScuWdt_Start(XScuWdt *InstancePtr); - -void XScuWdt_Stop(XScuWdt *InstancePtr); - -/* - * Self-test function in xwdttb_selftest.c. - */ -int XScuWdt_SelfTest(XScuWdt *InstancePtr); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h deleted file mode 100644 index 9bf23046d9fda0868c4233acf5a1a29f1f773b85..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h +++ /dev/null @@ -1,187 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file xscuwdt_hw.h -* -* This file contains the hardware interface to the Xilinx SCU private Watch Dog -* Timer (XSCUWDT). -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- --------------------------------------------- -* 1.00a sdm 01/15/10 First release -* 1.01a bss 02/27/12 Updated the register offsets to start at 0x0 instead -* of 0x20 as the base address obtained from the tools -* starts at 0x20. -* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue -* when the xstatus.h in the common driver overwrites -* the xstatus.h of the standalone BSP during the -* libgen. -* </pre> -* -******************************************************************************/ -#ifndef XSCUWDT_HW_H /* prevent circular inclusions */ -#define XSCUWDT_HW_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_io.h" -#include "xil_assert.h" -/************************** Constant Definitions *****************************/ - -/** @name Register Map - * Offsets of registers from the start of the device. The WDT registers start at - * an offset 0x20 - * @{ - */ - -#define XSCUWDT_LOAD_OFFSET 0x00 /**< Watchdog Load Register */ -#define XSCUWDT_COUNTER_OFFSET 0x04 /**< Watchdog Counter Register */ -#define XSCUWDT_CONTROL_OFFSET 0x08 /**< Watchdog Control Register */ -#define XSCUWDT_ISR_OFFSET 0x0C /**< Watchdog Interrupt Status Register */ -#define XSCUWDT_RST_STS_OFFSET 0x10 /**< Watchdog Reset Status Register */ -#define XSCUWDT_DISABLE_OFFSET 0x14 /**< Watchdog Disable Register */ -/* @} */ - -/** @name Watchdog Control register - * This register bits control the prescaler, WD/Timer mode, Intr enable, - * auto-reload, watchdog enable. - * @{ - */ - -#define XSCUWDT_CONTROL_PRESCALER_MASK 0x0000FF00 /**< Prescaler */ -#define XSCUWDT_CONTROL_PRESCALER_SHIFT 8 -#define XSCUWDT_CONTROL_WD_MODE_MASK 0x00000008 /**< Watchdog/Timer mode */ -#define XSCUWDT_CONTROL_IT_ENABLE_MASK 0x00000004 /**< Intr enable (in - timer mode) */ -#define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002 /**< Auto-reload (in - timer mode) */ -#define XSCUWDT_CONTROL_WD_ENABLE_MASK 0x00000001 /**< Watchdog enable */ -/* @} */ - -/** @name Interrupt Status register - * This register indicates the Counter register has reached zero in Counter - * mode. - * @{ - */ - -#define XSCUWDT_ISR_EVENT_FLAG_MASK 0x00000001 /**< Event flag */ -/*@}*/ - -/** @name Reset Status register - * This register indicates the Counter register has reached zero in Watchdog - * mode and a reset request is sent. - * @{ - */ - -#define XSCUWDT_RST_STS_RESET_FLAG_MASK 0x00000001 /**< Time out occured */ -/*@}*/ - -/** @name Disable register - * This register is used to switch from watchdog mode to timer mode. - * The software must write 0x12345678 and 0x87654321 successively to the - * Watchdog Disable Register so that the watchdog mode bit in the Watchdog - * Control Register is set to zero. - * @{ - */ -#define XSCUWDT_DISABLE_VALUE1 0x12345678 /**< Watchdog mode disable - value 1 */ -#define XSCUWDT_DISABLE_VALUE2 0x87654321 /**< Watchdog mode disable - value 2 */ -/*@}*/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/****************************************************************************/ -/** -* -* Read the given register. -* -* @param BaseAddr is the base address of the device -* @param RegOffset is the register offset to be read -* -* @return The 32-bit value of the register -* -* @note C-style signature: -* u32 XScuWdt_ReadReg(u32 BaseAddr, u32 RegOffset) -* -*****************************************************************************/ -#define XScuWdt_ReadReg(BaseAddr, RegOffset) \ - Xil_In32((BaseAddr) + (RegOffset)) - -/****************************************************************************/ -/** -* -* Write the given register. -* -* @param BaseAddr is the base address of the device -* @param RegOffset is the register offset to be written -* @param Data is the 32-bit value to write to the register -* -* @return None. -* -* @note C-style signature: -* void XScuWdt_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data) -* -*****************************************************************************/ -#define XScuWdt_WriteReg(BaseAddr, RegOffset, Data) \ - Xil_Out32((BaseAddr) + (RegOffset), (Data)) - -/************************** Function Prototypes ******************************/ - -/************************** Variable Definitions *****************************/ - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xstatus.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xstatus.h deleted file mode 100644 index 76d2a94c73eb4640b66c7b09096b5e2f718fb22f..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xstatus.h +++ /dev/null @@ -1,439 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2002-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xstatus.h -* -* This file contains Xilinx software status codes. Status codes have their -* own data type called int. These codes are used throughout the Xilinx -* device drivers. -* -******************************************************************************/ - -#ifndef XSTATUS_H /* prevent circular inclusions */ -#define XSTATUS_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" - -/************************** Constant Definitions *****************************/ - -/*********************** Common statuses 0 - 500 *****************************/ - -#define XST_SUCCESS 0L -#define XST_FAILURE 1L -#define XST_DEVICE_NOT_FOUND 2L -#define XST_DEVICE_BLOCK_NOT_FOUND 3L -#define XST_INVALID_VERSION 4L -#define XST_DEVICE_IS_STARTED 5L -#define XST_DEVICE_IS_STOPPED 6L -#define XST_FIFO_ERROR 7L /* an error occurred during an - operation with a FIFO such as - an underrun or overrun, this - error requires the device to - be reset */ -#define XST_RESET_ERROR 8L /* an error occurred which requires - the device to be reset */ -#define XST_DMA_ERROR 9L /* a DMA error occurred, this error - typically requires the device - using the DMA to be reset */ -#define XST_NOT_POLLED 10L /* the device is not configured for - polled mode operation */ -#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put - the specified data into */ -#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough - to hold the expected data */ -#define XST_NO_DATA 13L /* there was no data available */ -#define XST_REGISTER_ERROR 14L /* a register did not contain the - expected value */ -#define XST_INVALID_PARAM 15L /* an invalid parameter was passed - into the function */ -#define XST_NOT_SGDMA 16L /* the device is not configured for - scatter-gather DMA operation */ -#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */ -#define XST_NO_CALLBACK 18L /* a callback has not yet been - registered */ -#define XST_NO_FEATURE 19L /* device is not configured with - the requested feature */ -#define XST_NOT_INTERRUPT 20L /* device is not configured for - interrupt mode operation */ -#define XST_DEVICE_BUSY 21L /* device is busy */ -#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device - have maxed out */ -#define XST_IS_STARTED 23L /* used when part of device is - already started i.e. - sub channel */ -#define XST_IS_STOPPED 24L /* used when part of device is - already stopped i.e. - sub channel */ -#define XST_DATA_LOST 26L /* driver defined error */ -#define XST_RECV_ERROR 27L /* generic receive error */ -#define XST_SEND_ERROR 28L /* generic transmit error */ -#define XST_NOT_ENABLED 29L /* a requested service is not - available because it has not - been enabled */ - -/***************** Utility Component statuses 401 - 500 *********************/ - -#define XST_MEMTEST_FAILED 401L /* memory test failed */ - - -/***************** Common Components statuses 501 - 1000 *********************/ - -/********************* Packet Fifo statuses 501 - 510 ************************/ - -#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */ -#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */ -#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value - was invalid after reset */ -#define XST_PFIFO_ERROR 504L /* generic packet FIFO error */ -#define XST_PFIFO_DEADLOCK 505L /* packet FIFO is reporting - * empty and full simultaneously - */ - -/************************** DMA statuses 511 - 530 ***************************/ - -#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer - failed */ -#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value - was invalid after reset */ -#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains - no buffer descriptors ready - to be processed */ -#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */ -#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */ -#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of - the scatter gather list are - being used */ -#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer - descriptor which is to be - copied over in the scatter - list is locked */ -#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been - put into the scatter gather - list to be commited */ -#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold - specified was larger than the - total # of buffer descriptors - in the scatter gather list */ -#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has - already been created */ -#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has - been created */ -#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was - being started was not committed - to the list */ -#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start - has already been used by the - hardware so it can't be reused - */ -#define XST_DMA_SG_LIST_ERROR 526L /* general purpose list access - error */ -#define XST_DMA_BD_ERROR 527L /* general buffer descriptor - error */ - -/************************** IPIF statuses 531 - 550 ***************************/ - -#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width - was passed into the function */ -#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at - reset was not valid */ -#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt - status register did not read - back correctly */ -#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status - register did not reset when - acked */ -#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable - register was not updated when - other registers changed */ -#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt - status register did not read - back correctly */ -#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register - did not reset when acked */ -#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was - not updated correctly when other - registers changed */ -#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending - register did not indicate the - expected value */ -#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register - did not indicate the expected - value */ -#define XST_IPIF_ERROR 541L /* generic ipif error */ - -/****************** Device specific statuses 1001 - 4095 *********************/ - -/********************* Ethernet statuses 1001 - 1050 *************************/ - -#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough - * to hold the minimum number of - * buffers or descriptors */ -#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */ -#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */ -#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */ -#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Driver is out of buffers */ -#define XST_EMAC_PARSE_ERROR 1006L /* Invalid driver init string */ -#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late - * collision on polled send */ - -/*********************** UART statuses 1051 - 1075 ***************************/ -#define XST_UART - -#define XST_UART_INIT_ERROR 1051L -#define XST_UART_START_ERROR 1052L -#define XST_UART_CONFIG_ERROR 1053L -#define XST_UART_TEST_FAIL 1054L -#define XST_UART_BAUD_ERROR 1055L -#define XST_UART_BAUD_RANGE 1056L - - -/************************ IIC statuses 1076 - 1100 ***************************/ - -#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */ -#define XST_IIC_BUS_BUSY 1077 /* bus found busy */ -#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */ - /* general call address */ -#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */ - /* value after reset not valid */ -#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */ - /* value after reset not valid */ -#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */ - /* value after reset not valid */ -#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */ - /* value after reset not valid */ -#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */ - /* didn't return value written */ -#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */ - /* didn't return value written */ -#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */ - /* didn't return value written */ -#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */ - /* didn't return value written */ -#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */ - /* didn't return written value */ -#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */ - -/*********************** ATMC statuses 1101 - 1125 ***************************/ - -#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM - controller hit the max value - which requires the statistics - to be cleared */ - -/*********************** Flash statuses 1126 - 1150 **************************/ - -#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming - */ -#define XST_FLASH_READY 1127L /* Flash is ready for commands */ -#define XST_FLASH_ERROR 1128L /* Flash had detected an internal - error. Use XFlash_DeviceControl - to retrieve device specific codes - */ -#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state - */ -#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state - */ -#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by - driver */ -#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */ -#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */ -#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation - aborted due to a timeout */ -#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its - addressible range */ -#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */ -#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from - write/erase function with - XFL_NON_BLOCKING_WRITE/ERASE - option cleared */ -#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */ - -/*********************** SPI statuses 1151 - 1175 ****************************/ - -#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */ -#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */ -#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */ -#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */ -#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */ -#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being - * selected */ -#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */ -#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only - */ -#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */ -#define XST_SPI_SLAVE_MODE 1160 /* device has been addressed as slave */ -#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /* device received data in slave mode */ - -#define XST_SPI_COMMAND_ERROR 1162 /* unrecognised command - qspi only */ - -/********************** OPB Arbiter statuses 1176 - 1200 *********************/ - -#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either - * one master assigned to two or more - * priorities, or one master not - * assigned to any priority - */ -#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the - * priority levels without first - * suspending the use of priority - * levels - */ -#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but - * bus parking was not enabled - */ -#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed - * priority mode to allow the - * priorities to be changed - */ - -/************************ Intc statuses 1201 - 1225 **************************/ - -#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */ -#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */ - -/********************** TmrCtr statuses 1226 - 1250 **************************/ - -#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */ - -/********************** WdtTb statuses 1251 - 1275 ***************************/ - -#define XST_WDTTB_TIMER_FAILED 1251L - -/********************** PlbArb statuses 1276 - 1300 **************************/ - -#define XST_PLBARB_FAIL_SELFTEST 1276L - -/********************** Plb2Opb statuses 1301 - 1325 *************************/ - -#define XST_PLB2OPB_FAIL_SELFTEST 1301L - -/********************** Opb2Plb statuses 1326 - 1350 *************************/ - -#define XST_OPB2PLB_FAIL_SELFTEST 1326L - -/********************** SysAce statuses 1351 - 1360 **************************/ - -#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */ - -/********************** PCI Bridge statuses 1361 - 1375 **********************/ - -#define XST_PCI_INVALID_ADDRESS 1361L - -/********************** FlexRay constants 1400 - 1409 *************************/ - -#define XST_FR_TX_ERROR 1400 -#define XST_FR_TX_BUSY 1401 -#define XST_FR_BUF_LOCKED 1402 -#define XST_FR_NO_BUF 1403 - -/****************** USB constants 1410 - 1420 *******************************/ - -#define XST_USB_ALREADY_CONFIGURED 1410 -#define XST_USB_BUF_ALIGN_ERROR 1411 -#define XST_USB_NO_DESC_AVAILABLE 1412 -#define XST_USB_BUF_TOO_BIG 1413 -#define XST_USB_NO_BUF 1414 - -/****************** HWICAP constants 1421 - 1429 *****************************/ - -#define XST_HWICAP_WRITE_DONE 1421 - - -/****************** AXI VDMA constants 1430 - 1440 *****************************/ - -#define XST_VDMA_MISMATCH_ERROR 1430 - -/*********************** NAND Flash statuses 1441 - 1459 *********************/ - -#define XST_NAND_BUSY 1441L /* Flash is erasing or - * programming - */ -#define XST_NAND_READY 1442L /* Flash is ready for commands - */ -#define XST_NAND_ERROR 1443L /* Flash had detected an - * internal error. - */ -#define XST_NAND_PART_NOT_SUPPORTED 1444L /* Flash type not supported by - * driver - */ -#define XST_NAND_OPT_NOT_SUPPORTED 1445L /* Operation not supported - */ -#define XST_NAND_TIMEOUT_ERROR 1446L /* Programming or erase - * operation aborted due to a - * timeout - */ -#define XST_NAND_ADDRESS_ERROR 1447L /* Accessed flash outside its - * addressible range - */ -#define XST_NAND_ALIGNMENT_ERROR 1448L /* Write alignment error - */ -#define XST_NAND_PARAM_PAGE_ERROR 1449L /* Failed to read parameter - * page of the device - */ -#define XST_NAND_CACHE_ERROR 1450L /* Flash page buffer error - */ - -#define XST_NAND_WRITE_PROTECTED 1451L /* Flash is write protected - */ - -/**************************** Type Definitions *******************************/ - -typedef int XStatus; - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xtime_l.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xtime_l.h deleted file mode 100644 index e6550d3ce6a584cbaa3de8caa63715d8cadd7f31..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xtime_l.h +++ /dev/null @@ -1,96 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* @file xtime_l.h -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------ -------- --------------------------------------------------- -* 1.00a rp/sdm 11/03/09 Initial release. -* 3.06a sgd 05/15/12 Upadted get/set time functions to make use Global Timer -* 3.06a asa 06/17/12 Reverted back the changes to make use Global Timer. -* 3.07a sgd 07/05/12 Upadted get/set time functions to make use Global Timer -* </pre> -* -* @note None. -* -******************************************************************************/ - -#ifndef XTIME_H /* prevent circular inclusions */ -#define XTIME_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ -#include "xparameters.h" - -/***************** Macros (Inline Functions) Definitions *********************/ - -/**************************** Type Definitions *******************************/ - -typedef unsigned long long XTime; - -/************************** Constant Definitions *****************************/ -#define GLOBAL_TMR_BASEADDR XPAR_GLOBAL_TMR_BASEADDR -#define GTIMER_COUNTER_LOWER_OFFSET 0x00 -#define GTIMER_COUNTER_UPPER_OFFSET 0x04 -#define GTIMER_CONTROL_OFFSET 0x08 - - -/* Global Timer is always clocked at half of the CPU frequency */ -#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2) -/************************** Variable Definitions *****************************/ - -/************************** Function Prototypes ******************************/ - -void XTime_SetTime(XTime Xtime); -void XTime_GetTime(XTime *Xtime); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* XTIME_H */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xtmrctr.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xtmrctr.h deleted file mode 100644 index 3ae4800778d037930a75ce5a42aaa39341689cf5..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xtmrctr.h +++ /dev/null @@ -1,309 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2002-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xtmrctr.h -* -* The Xilinx timer/counter component. This component supports the Xilinx -* timer/counter. More detailed description of the driver operation can -* be found in the xtmrctr.c file. -* -* The Xilinx timer/counter supports the following features: -* - Polled mode. -* - Interrupt driven mode -* - enabling and disabling specific timers -* - PWM operation -* - Cascade Operation (This is to be used for getting a 64 bit timer and this -* feature is present in the latest versions of the axi_timer IP) -* -* The driver does not currently support the PWM operation of the device. -* -* The timer counter operates in 2 primary modes, compare and capture. In -* either mode, the timer counter may count up or down, with up being the -* default. -* -* Compare mode is typically used for creating a single time period or multiple -* repeating time periods in the auto reload mode, such as a periodic interrupt. -* When started, the timer counter loads an initial value, referred to as the -* compare value, into the timer counter and starts counting down or up. The -* timer counter expires when it rolls over/under depending upon the mode of -* counting. An external compare output signal may be configured such that a -* pulse is generated with this signal when it hits the compare value. -* -* Capture mode is typically used for measuring the time period between -* external events. This mode uses an external capture input signal to cause -* the value of the timer counter to be captured. When started, the timer -* counter loads an initial value, referred to as the compare value, - -* The timer can be configured to either cause an interrupt when the count -* reaches the compare value in compare mode or latch the current count -* value in the capture register when an external input is asserted -* in capture mode. The external capture input can be enabled/disabled using the -* XTmrCtr_SetOptions function. While in compare mode, it is also possible to -* drive an external output when the compare value is reached in the count -* register The external compare output can be enabled/disabled using the -* XTmrCtr_SetOptions function. -* -* <b>Interrupts</b> -* -* It is the responsibility of the application to connect the interrupt -* handler of the timer/counter to the interrupt source. The interrupt -* handler function, XTmrCtr_InterruptHandler, is visible such that the user -* can connect it to the interrupt source. Note that this interrupt handler -* does not provide interrupt context save and restore processing, the user -* must perform this processing. -* -* The driver services interrupts and passes timeouts to the upper layer -* software through callback functions. The upper layer software must register -* its callback functions during initialization. The driver requires callback -* functions for timers. -* -* @note -* The default settings for the timers are: -* - Interrupt generation disabled -* - Count up mode -* - Compare mode -* - Hold counter (will not reload the timer) -* - External compare output disabled -* - External capture input disabled -* - Pulse width modulation disabled -* - Timer disabled, waits for Start function to be called -* <br><br> -* A timer counter device may contain multiple timer counters. The symbol -* XTC_DEVICE_TIMER_COUNT defines the number of timer counters in the device. -* The device currently contains 2 timer counters. -* <br><br> -* This driver is intended to be RTOS and processor independent. It works with -* physical addresses only. Any needs for dynamic memory management, threads -* or thread mutual exclusion, virtual memory, or cache control must be -* satisfied by the layer above this driver. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a ecm 08/16/01 First release -* 1.00b jhl 02/21/02 Repartitioned the driver for smaller files -* 1.10b mta 03/21/07 Updated to new coding style. -* 1.11a sdm 08/22/08 Removed support for static interrupt handlers from the MDD -* file -* 2.00a ktn 10/30/09 Updated to use HAL API's. _m is removed from all the macro -* definitions. -* 2.01a ktn 07/12/10 Renamed the macro XTimerCtr_ReadReg as XTmrCtr_ReadReg -* for naming consistency (CR 559142). -* 2.02a sdm 09/28/10 Updated the driver tcl to generate the xparameters -* for the timer clock frequency (CR 572679). -* 2.03a rvo 11/30/10 Added check to see if interrupt is enabled before further -* processing for CR 584557. -* 2.04a sdm 07/12/11 Added support for cascade mode operation. -* The cascade mode of operation is present in the latest -* versions of the axi_timer IP. Please check the HW -* Datasheet to see whether this feature is present in the -* version of the IP that you are using. -* 2.05a adk 15/05/13 Fixed the CR:693066 -* Added the IsStartedTmrCtr0/IsStartedTmrCtr1 members to the -* XTmrCtr instance structure. -* The IsStartedTmrCtrX will be assigned XIL_COMPONENT_IS_STARTED in -* the XTmrCtr_Start function. -* The IsStartedTmrCtrX will be cleared in the XTmrCtr_Stop function. -* There will be no Initialization done in the -* XTmrCtr_Initialize if both the timers have already started and -* the XST_DEVICE_IS_STARTED Status is returned. -* Removed the logic in the XTmrCtr_Initialize function -* which was checking the Register Value to know whether -* a timer has started or not. -* </pre> -* -******************************************************************************/ - -#ifndef XTMRCTR_H /* prevent circular inclusions */ -#define XTMRCTR_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xstatus.h" -#include "xtmrctr_l.h" - -/************************** Constant Definitions *****************************/ - -/** - * @name Configuration options - * These options are used in XTmrCtr_SetOptions() and XTmrCtr_GetOptions() - * @{ - */ -/** - * Used to configure the timer counter device. - * <pre> - * XTC_CASCADE_MODE_OPTION Enables the Cascade Mode only valid for TCSRO. - * XTC_ENABLE_ALL_OPTION Enables all timer counters at once. - * XTC_DOWN_COUNT_OPTION Configures the timer counter to count down from - * start value, the default is to count up. - * XTC_CAPTURE_MODE_OPTION Configures the timer to capture the timer - * counter value when the external capture line is - * asserted. The default mode is compare mode. - * XTC_INT_MODE_OPTION Enables the timer counter interrupt output. - * XTC_AUTO_RELOAD_OPTION In compare mode, configures the timer counter to - * reload from the compare value. The default mode - * causes the timer counter to hold when the - * compare value is hit. - * In capture mode, configures the timer counter to - * not hold the previous capture value if a new - * event occurs. The default mode cause the timer - * counter to hold the capture value until - * recognized. - * XTC_EXT_COMPARE_OPTION Enables the external compare output signal. - * </pre> - */ -#define XTC_CASCADE_MODE_OPTION 0x00000080UL -#define XTC_ENABLE_ALL_OPTION 0x00000040UL -#define XTC_DOWN_COUNT_OPTION 0x00000020UL -#define XTC_CAPTURE_MODE_OPTION 0x00000010UL -#define XTC_INT_MODE_OPTION 0x00000008UL -#define XTC_AUTO_RELOAD_OPTION 0x00000004UL -#define XTC_EXT_COMPARE_OPTION 0x00000002UL -/*@}*/ - -/**************************** Type Definitions *******************************/ - -/** - * This typedef contains configuration information for the device. - */ -typedef struct { - u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddress;/**< Register base address */ -} XTmrCtr_Config; - -/** - * Signature for the callback function. - * - * @param CallBackRef is a callback reference passed in by the upper layer - * when setting the callback functions, and passed back to the - * upper layer when the callback is invoked. Its type is - * unimportant to the driver, so it is a void pointer. - * @param TmrCtrNumber is the number of the timer/counter within the - * device. The device typically contains at least two - * timer/counters. The timer number is a zero based number with a - * range of 0 to (XTC_DEVICE_TIMER_COUNT - 1). - */ -typedef void (*XTmrCtr_Handler) (void *CallBackRef, u8 TmrCtrNumber); - - -/** - * Timer/Counter statistics - */ -typedef struct { - u32 Interrupts; /**< The number of interrupts that have occurred */ -} XTmrCtrStats; - -/** - * The XTmrCtr driver instance data. The user is required to allocate a - * variable of this type for every timer/counter device in the system. A - * pointer to a variable of this type is then passed to the driver API - * functions. - */ -typedef struct { - XTmrCtrStats Stats; /**< Component Statistics */ - u32 BaseAddress; /**< Base address of registers */ - u32 IsReady; /**< Device is initialized and ready */ - u32 IsStartedTmrCtr0; /**< Is Timer Counter 0 started */ - u32 IsStartedTmrCtr1; /**< Is Timer Counter 1 started */ - - XTmrCtr_Handler Handler; /**< Callback function */ - void *CallBackRef; /**< Callback reference for handler */ -} XTmrCtr; - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - -/* - * Required functions, in file xtmrctr.c - */ -int XTmrCtr_Initialize(XTmrCtr * InstancePtr, u16 DeviceId); -void XTmrCtr_Start(XTmrCtr * InstancePtr, u8 TmrCtrNumber); -void XTmrCtr_Stop(XTmrCtr * InstancePtr, u8 TmrCtrNumber); -u32 XTmrCtr_GetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber); -void XTmrCtr_SetResetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber, - u32 ResetValue); -u32 XTmrCtr_GetCaptureValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber); -int XTmrCtr_IsExpired(XTmrCtr * InstancePtr, u8 TmrCtrNumber); -void XTmrCtr_Reset(XTmrCtr * InstancePtr, u8 TmrCtrNumber); -XTmrCtr_Config *XTmrCtr_LookupConfig(u16 DeviceId); - -/* - * Functions for options, in file xtmrctr_options.c - */ -void XTmrCtr_SetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber, u32 Options); -u32 XTmrCtr_GetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber); - -/* - * Functions for statistics, in file xtmrctr_stats.c - */ -void XTmrCtr_GetStats(XTmrCtr * InstancePtr, XTmrCtrStats * StatsPtr); -void XTmrCtr_ClearStats(XTmrCtr * InstancePtr); - -/* - * Functions for self-test, in file xtmrctr_selftest.c - */ -int XTmrCtr_SelfTest(XTmrCtr * InstancePtr, u8 TmrCtrNumber); - -/* - * Functions for interrupts, in file xtmrctr_intr.c - */ -void XTmrCtr_SetHandler(XTmrCtr * InstancePtr, XTmrCtr_Handler FuncPtr, - void *CallBackRef); -void XTmrCtr_InterruptHandler(void *InstancePtr); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xtmrctr_i.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xtmrctr_i.h deleted file mode 100644 index bcdb900d36fd00d8bd10a971d5db3d927f958685..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xtmrctr_i.h +++ /dev/null @@ -1,88 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2002-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xtmrctr_i.h -* -* This file contains data which is shared between files internal to the -* XTmrCtr component. It is intended for internal use only. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00b jhl 02/06/02 First release -* 1.10b mta 03/21/07 Updated to new coding style -* 2.00a ktn 10/30/09 _m is removed from all the macro definitions. -* </pre> -* -******************************************************************************/ - -#ifndef XTMRCTR_I_H /* prevent circular inclusions */ -#define XTMRCTR_I_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" - -/************************** Constant Definitions *****************************/ - - -/************************** Function Prototypes ******************************/ - - -/************************** Variable Definitions *****************************/ - -extern XTmrCtr_Config XTmrCtr_ConfigTable[]; - -extern u8 XTmrCtr_Offsets[]; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xtmrctr_l.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xtmrctr_l.h deleted file mode 100644 index f926520351090eacab18d58a8fd92a7f0b15f1e5..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xtmrctr_l.h +++ /dev/null @@ -1,435 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2002-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xtmrctr_l.h -* -* This header file contains identifiers and low-level driver functions (or -* macros) that can be used to access the device. The user should refer to the -* hardware device specification for more details of the device operation. -* High-level driver functions are defined in xtmrctr.h. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00b jhl 04/24/02 First release -* 1.10b mta 03/21/07 Updated to new coding style -* 2.00a ktn 10/30/09 Updated to use HAL API's. _m is removed from all the macro -* definitions. -* 2.01a ktn 07/12/10 Renamed the macro XTimerCtr_ReadReg as XTmrCtr_ReadReg -* for naming consistency (CR 559142). -* 2.04a sdm 07/12/11 Added the CASC mode bit in the TCSRO register for the -* cascade mode operation. -* The cascade mode of operation is present in the latest -* versions of the axi_timer IP. Please check the HW -* Datasheet to see whether this feature is present in the -* version of the IP that you are using. -* </pre> -* -******************************************************************************/ - -#ifndef XTMRCTR_L_H /* prevent circular inclusions */ -#define XTMRCTR_L_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_io.h" - -/************************** Constant Definitions *****************************/ - -/** - * Defines the number of timer counters within a single hardware device. This - * number is not currently parameterized in the hardware but may be in the - * future. - */ -#define XTC_DEVICE_TIMER_COUNT 2 - -/* Each timer counter consumes 16 bytes of address space */ - -#define XTC_TIMER_COUNTER_OFFSET 16 - -/** @name Register Offset Definitions - * Register offsets within a timer counter, there are multiple - * timer counters within a single device - * @{ - */ - -#define XTC_TCSR_OFFSET 0 /**< Control/Status register */ -#define XTC_TLR_OFFSET 4 /**< Load register */ -#define XTC_TCR_OFFSET 8 /**< Timer counter register */ - -/* @} */ - -/** @name Control Status Register Bit Definitions - * Control Status Register bit masks - * Used to configure the timer counter device. - * @{ - */ - -#define XTC_CSR_CASC_MASK 0x00000800 /**< Cascade Mode */ -#define XTC_CSR_ENABLE_ALL_MASK 0x00000400 /**< Enables all timer - counters */ -#define XTC_CSR_ENABLE_PWM_MASK 0x00000200 /**< Enables the Pulse Width - Modulation */ -#define XTC_CSR_INT_OCCURED_MASK 0x00000100 /**< If bit is set, an - interrupt has occured. - If set and '1' is - written to this bit - position, bit is - cleared. */ -#define XTC_CSR_ENABLE_TMR_MASK 0x00000080 /**< Enables only the - specific timer */ -#define XTC_CSR_ENABLE_INT_MASK 0x00000040 /**< Enables the interrupt - output. */ -#define XTC_CSR_LOAD_MASK 0x00000020 /**< Loads the timer using - the load value provided - earlier in the Load - Register, - XTC_TLR_OFFSET. */ -#define XTC_CSR_AUTO_RELOAD_MASK 0x00000010 /**< In compare mode, - configures - the timer counter to - reload from the - Load Register. The - default mode - causes the timer counter - to hold when the compare - value is hit. In capture - mode, configures the - timer counter to not - hold the previous - capture value if a new - event occurs. The - default mode cause the - timer counter to hold - the capture value until - recognized. */ -#define XTC_CSR_EXT_CAPTURE_MASK 0x00000008 /**< Enables the - external input - to the timer counter. */ -#define XTC_CSR_EXT_GENERATE_MASK 0x00000004 /**< Enables the - external generate output - for the timer. */ -#define XTC_CSR_DOWN_COUNT_MASK 0x00000002 /**< Configures the timer - counter to count down - from start value, the - default is to count - up.*/ -#define XTC_CSR_CAPTURE_MODE_MASK 0x00000001 /**< Enables the timer to - capture the timer - counter value when the - external capture line is - asserted. The default - mode is compare mode.*/ -/* @} */ - -/**************************** Type Definitions *******************************/ - -extern u8 XTmrCtr_Offsets[]; - -/***************** Macros (Inline Functions) Definitions *********************/ - -/*****************************************************************************/ -/** -* Read one of the timer counter registers. -* -* @param BaseAddress contains the base address of the timer counter -* device. -* @param TmrCtrNumber contains the specific timer counter within the -* device, a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* @param RegOffset contains the offset from the 1st register of the timer -* counter to select the specific register of the timer counter. -* -* @return The value read from the register, a 32 bit value. -* -* @note C-Style signature: -* u32 XTmrCtr_ReadReg(u32 BaseAddress, u8 TimerNumber, - unsigned RegOffset); -******************************************************************************/ -#define XTmrCtr_ReadReg(BaseAddress, TmrCtrNumber, RegOffset) \ - Xil_In32((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \ - (RegOffset)) - -#ifndef XTimerCtr_ReadReg -#define XTimerCtr_ReadReg XTmrCtr_ReadReg -#endif - -/*****************************************************************************/ -/** -* Write a specified value to a register of a timer counter. -* -* @param BaseAddress is the base address of the timer counter device. -* @param TmrCtrNumber is the specific timer counter within the device, a -* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* @param RegOffset contain the offset from the 1st register of the timer -* counter to select the specific register of the timer counter. -* @param ValueToWrite is the 32 bit value to be written to the register. -* -* @note C-Style signature: -* void XTmrCtr_WriteReg(u32 BaseAddress, u8 TimerNumber, -* unsigned RegOffset, u32 ValueToWrite); -******************************************************************************/ -#define XTmrCtr_WriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\ - Xil_Out32(((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \ - (RegOffset)), (ValueToWrite)) - -/****************************************************************************/ -/** -* -* Set the Control Status Register of a timer counter to the specified value. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, a -* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* @param RegisterValue is the 32 bit value to be written to the register. -* -* @return None. -* -* @note C-Style signature: -* void XTmrCtr_SetControlStatusReg(u32 BaseAddress, -* u8 TmrCtrNumber,u32 RegisterValue); -*****************************************************************************/ -#define XTmrCtr_SetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\ - XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \ - (RegisterValue)) - -/****************************************************************************/ -/** -* -* Get the Control Status Register of a timer counter. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, -* a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return The value read from the register, a 32 bit value. -* -* @note C-Style signature: -* u32 XTmrCtr_GetControlStatusReg(u32 BaseAddress, -* u8 TmrCtrNumber); -*****************************************************************************/ -#define XTmrCtr_GetControlStatusReg(BaseAddress, TmrCtrNumber) \ - XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET) - -/****************************************************************************/ -/** -* -* Get the Timer Counter Register of a timer counter. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, -* a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return The value read from the register, a 32 bit value. -* -* @note C-Style signature: -* u32 XTmrCtr_GetTimerCounterReg(u32 BaseAddress, -* u8 TmrCtrNumber); -*****************************************************************************/ -#define XTmrCtr_GetTimerCounterReg(BaseAddress, TmrCtrNumber) \ - XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TCR_OFFSET) \ - -/****************************************************************************/ -/** -* -* Set the Load Register of a timer counter to the specified value. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, a -* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* @param RegisterValue is the 32 bit value to be written to the register. -* -* @return None. -* -* @note C-Style signature: -* void XTmrCtr_SetLoadReg(u32 BaseAddress, u8 TmrCtrNumber, -* u32 RegisterValue); -*****************************************************************************/ -#define XTmrCtr_SetLoadReg(BaseAddress, TmrCtrNumber, RegisterValue) \ - XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TLR_OFFSET, \ - (RegisterValue)) - -/****************************************************************************/ -/** -* -* Get the Load Register of a timer counter. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, a -* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return The value read from the register, a 32 bit value. -* -* @note C-Style signature: -* u32 XTmrCtr_GetLoadReg(u32 BaseAddress, u8 TmrCtrNumber); -*****************************************************************************/ -#define XTmrCtr_GetLoadReg(BaseAddress, TmrCtrNumber) \ -XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TLR_OFFSET) - -/****************************************************************************/ -/** -* -* Enable a timer counter such that it starts running. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, a -* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return None. -* -* @note C-Style signature: -* void XTmrCtr_Enable(u32 BaseAddress, u8 TmrCtrNumber); -*****************************************************************************/ -#define XTmrCtr_Enable(BaseAddress, TmrCtrNumber) \ - XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \ - (XTmrCtr_ReadReg((BaseAddress), ( TmrCtrNumber), \ - XTC_TCSR_OFFSET) | XTC_CSR_ENABLE_TMR_MASK)) - -/****************************************************************************/ -/** -* -* Disable a timer counter such that it stops running. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, -* a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return None. -* -* @note C-Style signature: -* void XTmrCtr_Disable(u32 BaseAddress, u8 TmrCtrNumber); -*****************************************************************************/ -#define XTmrCtr_Disable(BaseAddress, TmrCtrNumber) \ - XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \ - (XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),\ - XTC_TCSR_OFFSET) & ~ XTC_CSR_ENABLE_TMR_MASK)) - -/****************************************************************************/ -/** -* -* Enable the interrupt for a timer counter. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, a -* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return None. -* -* @note C-Style signature: -* void XTmrCtr_EnableIntr(u32 BaseAddress, u8 TmrCtrNumber); -*****************************************************************************/ -#define XTmrCtr_EnableIntr(BaseAddress, TmrCtrNumber) \ - XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \ - (XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), \ - XTC_TCSR_OFFSET) | XTC_CSR_ENABLE_INT_MASK)) - -/****************************************************************************/ -/** -* -* Disable the interrupt for a timer counter. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, a -* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return None. -* -* @note C-Style signature: -* void XTmrCtr_DisableIntr(u32 BaseAddress, u8 TmrCtrNumber); -*****************************************************************************/ -#define XTmrCtr_DisableIntr(BaseAddress, TmrCtrNumber) \ - XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \ - (XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), \ - XTC_TCSR_OFFSET) & ~ XTC_CSR_ENABLE_INT_MASK)) - -/****************************************************************************/ -/** -* -* Cause the timer counter to load it's Timer Counter Register with the value -* in the Load Register. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, a -* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return None. -* -* @note C-Style signature: -* void XTmrCtr_LoadTimerCounterReg(u32 BaseAddress, - u8 TmrCtrNumber); -*****************************************************************************/ -#define XTmrCtr_LoadTimerCounterReg(BaseAddress, TmrCtrNumber) \ - XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \ - (XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),\ - XTC_TCSR_OFFSET) | XTC_CSR_LOAD_MASK)) - -/****************************************************************************/ -/** -* -* Determine if a timer counter event has occurred. Events are defined to be -* when a capture has occurred or the counter has roller over. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, a -* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @note C-Style signature: -* int XTmrCtr_HasEventOccurred(u32 BaseAddress, u8 TmrCtrNumber); -*****************************************************************************/ -#define XTmrCtr_HasEventOccurred(BaseAddress, TmrCtrNumber) \ - ((XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), \ - XTC_TCSR_OFFSET) & XTC_CSR_INT_OCCURED_MASK) == \ - XTC_CSR_INT_OCCURED_MASK) - -/************************** Function Prototypes ******************************/ -/************************** Variable Definitions *****************************/ -#ifdef __cplusplus -} -#endif -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xuartps.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xuartps.h deleted file mode 100644 index c00060fe544f81f627ab20b042ce9bb44939c3dd..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xuartps.h +++ /dev/null @@ -1,511 +0,0 @@ -/***************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -*****************************************************************************/ -/****************************************************************************/ -/** -* -* @file xuartps.h -* -* This driver supports the following features: -* -* - Dynamic data format (baud rate, data bits, stop bits, parity) -* - Polled mode -* - Interrupt driven mode -* - Transmit and receive FIFOs (32 byte FIFO depth) -* - Access to the external modem control lines -* -* <b>Initialization & Configuration</b> -* -* The XUartPs_Config structure is used by the driver to configure itself. -* Fields inside this structure are properties of XUartPs based on its hardware -* build. -* -* To support multiple runtime loading and initialization strategies employed -* by various operating systems, the driver instance can be initialized in the -* following way: -* -* - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a -* configuration structure provided by the caller. If running in a system -* with address translation, the parameter EffectiveAddr should be the -* virtual address. -* -* <b>Baud Rate</b> -* -* The UART has an internal baud rate generator, which furnishes the baud rate -* clock for both the receiver and the transmitter. Ther input clock frequency -* can be either the master clock or the master clock divided by 8, configured -* through the mode register. -* -* Accompanied with the baud rate divider register, the baud rate is determined -* by: -* <pre> -* baud_rate = input_clock / (bgen * (bdiv + 1) -* </pre> -* where bgen is the value of the baud rate generator, and bdiv is the value of -* baud rate divider. -* -* <b>Interrupts</b> -* -* The FIFOs are not flushed when the driver is initialized, but a function is -* provided to allow the user to reset the FIFOs if desired. -* -* The driver defaults to no interrupts at initialization such that interrupts -* must be enabled if desired. An interrupt is generated for one of the -* following conditions. -* -* - A change in the modem signals -* - Data in the receive FIFO for a configuable time without receiver activity -* - A parity error -* - A framing error -* - An overrun error -* - Transmit FIFO is full -* - Transmit FIFO is empty -* - Receive FIFO is full -* - Receive FIFO is empty -* - Data in the receive FIFO equal to the receive threshold -* -* The application can control which interrupts are enabled using the -* XUartPs_SetInterruptMask() function. -* -* In order to use interrupts, it is necessary for the user to connect the -* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt -* system of the application. A separate handler should be provided by the -* application to communicate with the interrupt system, and conduct -* application specific interrupt handling. An application registers its own -* handler through the XUartPs_SetHandler() function. -* -* <b>Data Transfer</b> -* -* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the -* driver to allow data to be sent and received. They can be used in either -* polled or interrupt mode. -* -* @note -* -* The default configuration for the UART after initialization is: -* -* - 9,600 bps or XPAR_DFT_BAUDRATE if defined -* - 8 data bits -* - 1 stop bit -* - no parity -* - FIFO's are enabled with a receive threshold of 8 bytes -* - The RX timeout is enabled with a timeout of 1 (4 char times) -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------ -------- ---------------------------------------------- -* 1.00a drg/jz 01/12/10 First Release -* 1.00a sdm 09/27/11 Fixed compiler warnings and also a bug -* in XUartPs_SetFlowDelay where the value was not -* being written to the register. -* 1.01a sdm 12/20/11 Removed the InputClockHz parameter from the XUartPs -* instance structure and the driver is updated to use -* InputClockHz parameter from the XUartPs_Config config -* structure. -* Added a parameter to XUartPs_Config structure which -* specifies whether the user has selected Modem pins -* to be connected to MIO or FMIO. -* Added the tcl file to generate the xparameters.h -* 1.02a sg 05/16/12 Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix. -* 1.03a sg 07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS -* with the correct values for CR 666724 -* Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL -* and XUARTPS_IXR_TTRIG. -* Modified the name of these defines -* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD -* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI -* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR -* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS -* 1.05a hk 08/22/13 Added API for uart reset and related -* constant definitions. -* -* </pre> -* -*****************************************************************************/ - -#ifndef XUARTPS_H /* prevent circular inclusions */ -#define XUARTPS_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files ********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xstatus.h" -#include "xuartps_hw.h" - -/************************** Constant Definitions ****************************/ - -/* - * The following constants indicate the max and min baud rates and these - * numbers are based only on the testing that has been done. The hardware - * is capable of other baud rates. - */ -#define XUARTPS_MAX_RATE 115200 -#define XUARTPS_MIN_RATE 110 - -#define XUARTPS_DFT_BAUDRATE 115200 /* Default baud rate */ - -/** @name Configuration options - * @{ - */ -/** - * These constants specify the options that may be set or retrieved - * with the driver, each is a unique bit mask such that multiple options - * may be specified. These constants indicate the available options - * in active state. - * - */ - -#define XUARTPS_OPTION_SET_BREAK 0x0080 /**< Starts break transmission */ -#define XUARTPS_OPTION_STOP_BREAK 0x0040 /**< Stops break transmission */ -#define XUARTPS_OPTION_RESET_TMOUT 0x0020 /**< Reset the receive timeout */ -#define XUARTPS_OPTION_RESET_TX 0x0010 /**< Reset the transmitter */ -#define XUARTPS_OPTION_RESET_RX 0x0008 /**< Reset the receiver */ -#define XUARTPS_OPTION_ASSERT_RTS 0x0004 /**< Assert the RTS bit */ -#define XUARTPS_OPTION_ASSERT_DTR 0x0002 /**< Assert the DTR bit */ -#define XUARTPS_OPTION_SET_FCM 0x0001 /**< Turn on flow control mode */ -/*@}*/ - - -/** @name Channel Operational Mode - * - * The UART can operate in one of four modes: Normal, Local Loopback, Remote - * Loopback, or automatic echo. - * - * @{ - */ - -#define XUARTPS_OPER_MODE_NORMAL 0x00 /**< Normal Mode */ -#define XUARTPS_OPER_MODE_AUTO_ECHO 0x01 /**< Auto Echo Mode */ -#define XUARTPS_OPER_MODE_LOCAL_LOOP 0x02 /**< Local Loopback Mode */ -#define XUARTPS_OPER_MODE_REMOTE_LOOP 0x03 /**< Remote Loopback Mode */ - -/* @} */ - -/** @name Data format values - * - * These constants specify the data format that the driver supports. - * The data format includes the number of data bits, the number of stop - * bits and parity. - * - * @{ - */ -#define XUARTPS_FORMAT_8_BITS 0 /**< 8 data bits */ -#define XUARTPS_FORMAT_7_BITS 2 /**< 7 data bits */ -#define XUARTPS_FORMAT_6_BITS 3 /**< 6 data bits */ - -#define XUARTPS_FORMAT_NO_PARITY 4 /**< No parity */ -#define XUARTPS_FORMAT_MARK_PARITY 3 /**< Mark parity */ -#define XUARTPS_FORMAT_SPACE_PARITY 2 /**< parity */ -#define XUARTPS_FORMAT_ODD_PARITY 1 /**< Odd parity */ -#define XUARTPS_FORMAT_EVEN_PARITY 0 /**< Even parity */ - -#define XUARTPS_FORMAT_2_STOP_BIT 2 /**< 2 stop bits */ -#define XUARTPS_FORMAT_1_5_STOP_BIT 1 /**< 1.5 stop bits */ -#define XUARTPS_FORMAT_1_STOP_BIT 0 /**< 1 stop bit */ -/*@}*/ - -/** @name Callback events - * - * These constants specify the handler events that an application can handle - * using its specific handler function. Note that these constants are not bit - * mask, so only one event can be passed to an application at a time. - * - * @{ - */ -#define XUARTPS_EVENT_RECV_DATA 1 /**< Data receiving done */ -#define XUARTPS_EVENT_RECV_TOUT 2 /**< A receive timeout occurred */ -#define XUARTPS_EVENT_SENT_DATA 3 /**< Data transmission done */ -#define XUARTPS_EVENT_RECV_ERROR 4 /**< A receive error detected */ -#define XUARTPS_EVENT_MODEM 5 /**< Modem status changed */ -/*@}*/ - - -/**************************** Type Definitions ******************************/ - -/** - * This typedef contains configuration information for the device. - */ -typedef struct { - u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddress; /**< Base address of device (IPIF) */ - u32 InputClockHz;/**< Input clock frequency */ - int ModemPinsConnected; /** Specifies whether modem pins are connected - * to MIO or FMIO */ -} XUartPs_Config; - -/* - * Keep track of state information about a data buffer in the interrupt mode. - */ -typedef struct { - u8 *NextBytePtr; - unsigned int RequestedBytes; - unsigned int RemainingBytes; -} XUartPsBuffer; - -/** - * Keep track of data format setting of a device. - */ -typedef struct { - u32 BaudRate; /**< In bps, ie 1200 */ - u32 DataBits; /**< Number of data bits */ - u32 Parity; /**< Parity */ - u8 StopBits; /**< Number of stop bits */ -} XUartPsFormat; - -/******************************************************************************/ -/** - * This data type defines a handler that an application defines to communicate - * with interrupt system to retrieve state information about an application. - * - * @param CallBackRef is a callback reference passed in by the upper layer - * when setting the handler, and is passed back to the upper layer - * when the handler is called. It is used to find the device driver - * instance. - * @param Event contains one of the event constants indicating events that - * have occurred. - * @param EventData contains the number of bytes sent or received at the - * time of the call for send and receive events and contains the - * modem status for modem events. - * - ******************************************************************************/ -typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event, - unsigned int EventData); - -/** - * The XUartPs driver instance data structure. A pointer to an instance data - * structure is passed around by functions to refer to a specific driver - * instance. - */ -typedef struct { - XUartPs_Config Config; /* Configuration data structure */ - u32 InputClockHz; /* Input clock frequency */ - u32 IsReady; /* Device is initialized and ready */ - u32 BaudRate; /* Current baud rate */ - - XUartPsBuffer SendBuffer; - XUartPsBuffer ReceiveBuffer; - - XUartPs_Handler Handler; - void *CallBackRef; /* Callback reference for event handler */ -} XUartPs; - - -/***************** Macros (Inline Functions) Definitions ********************/ - -/****************************************************************************/ -/** -* Get the UART Channel Status Register. -* -* @param InstancePtr is a pointer to the XUartPs instance. -* -* @return The value read from the register. -* -* @note C-Style signature: -* u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr) -* -******************************************************************************/ -#define XUartPs_GetChannelStatus(InstancePtr) \ - Xil_In32(((InstancePtr)->Config.BaseAddress) + XUARTPS_SR_OFFSET) - -/****************************************************************************/ -/** -* Get the UART Mode Control Register. -* -* @param InstancePtr is a pointer to the XUartPs instance. -* -* @return The value read from the register. -* -* @note C-Style signature: -* u32 XUartPs_GetControl(XUartPs *InstancePtr) -* -******************************************************************************/ -#define XUartPs_GetModeControl(InstancePtr) \ - Xil_In32(((InstancePtr)->Config.BaseAddress) + XUARTPS_CR_OFFSET) - -/****************************************************************************/ -/** -* Set the UART Mode Control Register. -* -* @param InstancePtr is a pointer to the XUartPs instance. -* @param RegisterValue is the value to be written to the register. -* -* @return None. -* -* @note C-Style signature: -* void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue) -* -******************************************************************************/ -#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \ - Xil_Out32(((InstancePtr)->Config.BaseAddress) + XUARTPS_CR_OFFSET, \ - (RegisterValue)) - -/****************************************************************************/ -/** -* Enable the transmitter and receiver of the UART. -* -* @param InstancePtr is a pointer to the XUartPs instance. -* -* @return None. -* -* @note C-Style signature: -* void XUartPs_EnableUart(XUartPs *InstancePtr) -* -******************************************************************************/ -#define XUartPs_EnableUart(InstancePtr) \ - Xil_Out32(((InstancePtr)->Config.BaseAddress + XUARTPS_CR_OFFSET), \ - ((Xil_In32((InstancePtr)->Config.BaseAddress + XUARTPS_CR_OFFSET) & \ - ~XUARTPS_CR_EN_DIS_MASK) | (XUARTPS_CR_RX_EN | XUARTPS_CR_TX_EN))) - -/****************************************************************************/ -/** -* Disable the transmitter and receiver of the UART. -* -* @param InstancePtr is a pointer to the XUartPs instance. -* -* @return None. -* -* @note C-Style signature: -* void XUartPs_DisableUart(XUartPs *InstancePtr) -* -******************************************************************************/ -#define XUartPs_DisableUart(InstancePtr) \ - Xil_Out32(((InstancePtr)->Config.BaseAddress + XUARTPS_CR_OFFSET), \ - (((Xil_In32((InstancePtr)->Config.BaseAddress + XUARTPS_CR_OFFSET)) & \ - ~XUARTPS_CR_EN_DIS_MASK) | (XUARTPS_CR_RX_DIS | XUARTPS_CR_TX_DIS))) - -/****************************************************************************/ -/** -* Determine if the transmitter FIFO is empty. -* -* @param InstancePtr is a pointer to the XUartPs instance. -* -* @return -* - TRUE if a byte can be sent -* - FALSE if the Transmitter Fifo is not empty -* -* @note C-Style signature: -* u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr) -* -******************************************************************************/ -#define XUartPs_IsTransmitEmpty(InstancePtr) \ - ((Xil_In32(((InstancePtr)->Config.BaseAddress) + XUARTPS_SR_OFFSET) & \ - XUARTPS_SR_TXEMPTY) == XUARTPS_SR_TXEMPTY) - - -/************************** Function Prototypes *****************************/ - -/* - * Static lookup function implemented in xuartps_sinit.c - */ -XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId); - -/* - * Interface functions implemented in xuartps.c - */ -int XUartPs_CfgInitialize(XUartPs *InstancePtr, - XUartPs_Config * Config, u32 EffectiveAddr); - -unsigned int XUartPs_Send(XUartPs *InstancePtr, u8 *BufferPtr, - unsigned int NumBytes); - -unsigned int XUartPs_Recv(XUartPs *InstancePtr, u8 *BufferPtr, - unsigned int NumBytes); - -int XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate); - -/* - * Options functions in xuartps_options.c - */ -void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options); - -u16 XUartPs_GetOptions(XUartPs *InstancePtr); - -void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel); - -u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr); - -u16 XUartPs_GetModemStatus(XUartPs *InstancePtr); - -u32 XUartPs_IsSending(XUartPs *InstancePtr); - -u8 XUartPs_GetOperMode(XUartPs *InstancePtr); - -void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode); - -u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr); - -void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue); - -u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr); - -void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout); - -int XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * Format); -void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * Format); - -/* - * interrupt functions in xuartps_intr.c - */ -u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr); - -void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask); - -void XUartPs_InterruptHandler(XUartPs *InstancePtr); - -void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr, - void *CallBackRef); - -/* - * self-test functions in xuartps_selftest.c - */ -int XUartPs_SelfTest(XUartPs *InstancePtr); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xuartps_hw.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xuartps_hw.h deleted file mode 100644 index 768e38027c16f60d1ca2b9804e4f1130b24603ae..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xuartps_hw.h +++ /dev/null @@ -1,432 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xuartps_hw.h -* -* This header file contains the hardware interface of an XUartPs device. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------ -------- ---------------------------------------------- -* 1.00 drg/jz 01/12/10 First Release -* 1.03a sg 09/04/12 Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL -* and XUARTPS_IXR_TTRIG. -* Modified the names of these defines -* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD -* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI -* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR -* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS -* 1.05a hk 08/22/13 Added prototype for uart reset and related -* constant definitions. -* -* </pre> -* -******************************************************************************/ -#ifndef XUARTPS_HW_H /* prevent circular inclusions */ -#define XUARTPS_HW_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xil_io.h" - -/************************** Constant Definitions *****************************/ - -/** @name Register Map - * - * Register offsets for the UART. - * @{ - */ -#define XUARTPS_CR_OFFSET 0x00 /**< Control Register [8:0] */ -#define XUARTPS_MR_OFFSET 0x04 /**< Mode Register [9:0] */ -#define XUARTPS_IER_OFFSET 0x08 /**< Interrupt Enable [12:0] */ -#define XUARTPS_IDR_OFFSET 0x0C /**< Interrupt Disable [12:0] */ -#define XUARTPS_IMR_OFFSET 0x10 /**< Interrupt Mask [12:0] */ -#define XUARTPS_ISR_OFFSET 0x14 /**< Interrupt Status [12:0]*/ -#define XUARTPS_BAUDGEN_OFFSET 0x18 /**< Baud Rate Generator [15:0] */ -#define XUARTPS_RXTOUT_OFFSET 0x1C /**< RX Timeout [7:0] */ -#define XUARTPS_RXWM_OFFSET 0x20 /**< RX FIFO Trigger Level [5:0] */ -#define XUARTPS_MODEMCR_OFFSET 0x24 /**< Modem Control [5:0] */ -#define XUARTPS_MODEMSR_OFFSET 0x28 /**< Modem Status [8:0] */ -#define XUARTPS_SR_OFFSET 0x2C /**< Channel Status [14:0] */ -#define XUARTPS_FIFO_OFFSET 0x30 /**< FIFO [7:0] */ -#define XUARTPS_BAUDDIV_OFFSET 0x34 /**< Baud Rate Divider [7:0] */ -#define XUARTPS_FLOWDEL_OFFSET 0x38 /**< Flow Delay [5:0] */ -#define XUARTPS_TXWM_OFFSET 0x44 /**< TX FIFO Trigger Level [5:0] */ -/* @} */ - -/** @name Control Register - * - * The Control register (CR) controls the major functions of the device. - * - * Control Register Bit Definition - */ - -#define XUARTPS_CR_STOPBRK 0x00000100 /**< Stop transmission of break */ -#define XUARTPS_CR_STARTBRK 0x00000080 /**< Set break */ -#define XUARTPS_CR_TORST 0x00000040 /**< RX timeout counter restart */ -#define XUARTPS_CR_TX_DIS 0x00000020 /**< TX disabled. */ -#define XUARTPS_CR_TX_EN 0x00000010 /**< TX enabled */ -#define XUARTPS_CR_RX_DIS 0x00000008 /**< RX disabled. */ -#define XUARTPS_CR_RX_EN 0x00000004 /**< RX enabled */ -#define XUARTPS_CR_EN_DIS_MASK 0x0000003C /**< Enable/disable Mask */ -#define XUARTPS_CR_TXRST 0x00000002 /**< TX logic reset */ -#define XUARTPS_CR_RXRST 0x00000001 /**< RX logic reset */ -/* @}*/ - - -/** @name Mode Register - * - * The mode register (MR) defines the mode of transfer as well as the data - * format. If this register is modified during transmission or reception, - * data validity cannot be guaranteed. - * - * Mode Register Bit Definition - * @{ - */ -#define XUARTPS_MR_CCLK 0x00000400 /**< Input clock selection */ -#define XUARTPS_MR_CHMODE_R_LOOP 0x00000300 /**< Remote loopback mode */ -#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200 /**< Local loopback mode */ -#define XUARTPS_MR_CHMODE_ECHO 0x00000100 /**< Auto echo mode */ -#define XUARTPS_MR_CHMODE_NORM 0x00000000 /**< Normal mode */ -#define XUARTPS_MR_CHMODE_SHIFT 8 /**< Mode shift */ -#define XUARTPS_MR_CHMODE_MASK 0x00000300 /**< Mode mask */ -#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080 /**< 2 stop bits */ -#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040 /**< 1.5 stop bits */ -#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000 /**< 1 stop bit */ -#define XUARTPS_MR_STOPMODE_SHIFT 6 /**< Stop bits shift */ -#define XUARTPS_MR_STOPMODE_MASK 0x000000A0 /**< Stop bits mask */ -#define XUARTPS_MR_PARITY_NONE 0x00000020 /**< No parity mode */ -#define XUARTPS_MR_PARITY_MARK 0x00000018 /**< Mark parity mode */ -#define XUARTPS_MR_PARITY_SPACE 0x00000010 /**< Space parity mode */ -#define XUARTPS_MR_PARITY_ODD 0x00000008 /**< Odd parity mode */ -#define XUARTPS_MR_PARITY_EVEN 0x00000000 /**< Even parity mode */ -#define XUARTPS_MR_PARITY_SHIFT 3 /**< Parity setting shift */ -#define XUARTPS_MR_PARITY_MASK 0x00000038 /**< Parity mask */ -#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006 /**< 6 bits data */ -#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004 /**< 7 bits data */ -#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000 /**< 8 bits data */ -#define XUARTPS_MR_CHARLEN_SHIFT 1 /**< Data Length shift */ -#define XUARTPS_MR_CHARLEN_MASK 0x00000006 /**< Data length mask */ -#define XUARTPS_MR_CLKSEL 0x00000001 /**< Input clock selection */ -/* @} */ - - -/** @name Interrupt Registers - * - * Interrupt control logic uses the interrupt enable register (IER) and the - * interrupt disable register (IDR) to set the value of the bits in the - * interrupt mask register (IMR). The IMR determines whether to pass an - * interrupt to the interrupt status register (ISR). - * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an - * interrupt. IMR and ISR are read only, and IER and IDR are write only. - * Reading either IER or IDR returns 0x00. - * - * All four registers have the same bit definitions. - * - * @{ - */ -#define XUARTPS_IXR_TOVR 0x00001000 /**< Tx FIFO Overflow interrupt */ -#define XUARTPS_IXR_TNFUL 0x00000800 /**< Tx FIFO Nearly Full interrupt */ -#define XUARTPS_IXR_TTRIG 0x00000400 /**< Tx Trig interrupt */ -#define XUARTPS_IXR_DMS 0x00000200 /**< Modem status change interrupt */ -#define XUARTPS_IXR_TOUT 0x00000100 /**< Timeout error interrupt */ -#define XUARTPS_IXR_PARITY 0x00000080 /**< Parity error interrupt */ -#define XUARTPS_IXR_FRAMING 0x00000040 /**< Framing error interrupt */ -#define XUARTPS_IXR_OVER 0x00000020 /**< Overrun error interrupt */ -#define XUARTPS_IXR_TXFULL 0x00000010 /**< TX FIFO full interrupt. */ -#define XUARTPS_IXR_TXEMPTY 0x00000008 /**< TX FIFO empty interrupt. */ -#define XUARTPS_IXR_RXFULL 0x00000004 /**< RX FIFO full interrupt. */ -#define XUARTPS_IXR_RXEMPTY 0x00000002 /**< RX FIFO empty interrupt. */ -#define XUARTPS_IXR_RXOVR 0x00000001 /**< RX FIFO trigger interrupt. */ -#define XUARTPS_IXR_MASK 0x00001FFF /**< Valid bit mask */ -/* @} */ - - -/** @name Baud Rate Generator Register - * - * The baud rate generator control register (BRGR) is a 16 bit register that - * controls the receiver bit sample clock and baud rate. - * Valid values are 1 - 65535. - * - * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit - * in the MR register. - * @{ - */ -#define XUARTPS_BAUDGEN_DISABLE 0x00000000 /**< Disable clock */ -#define XUARTPS_BAUDGEN_MASK 0x0000FFFF /**< Valid bits mask */ -#define XUARTPS_BAUDGEN_RESET_VAL 0x0000028B /**< Reset value */ - -/** @name Baud Divisor Rate register - * - * The baud rate divider register (BDIV) controls how much the bit sample - * rate is divided by. It sets the baud rate. - * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored. - * - * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by - * the MR_CCLK bit in the MR register. - * @{ - */ -#define XUARTPS_BAUDDIV_MASK 0x000000FF /**< 8 bit baud divider mask */ -#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000F /**< Reset value */ -/* @} */ - - -/** @name Receiver Timeout Register - * - * Use the receiver timeout register (RTR) to detect an idle condition on - * the receiver data line. - * - * @{ - */ -#define XUARTPS_RXTOUT_DISABLE 0x00000000 /**< Disable time out */ -#define XUARTPS_RXTOUT_MASK 0x000000FF /**< Valid bits mask */ - -/** @name Receiver FIFO Trigger Level Register - * - * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at - * which the RX FIFO triggers an interrupt event. - * @{ - */ - -#define XUARTPS_RXWM_DISABLE 0x00000000 /**< Disable RX trigger interrupt */ -#define XUARTPS_RXWM_MASK 0x0000003F /**< Valid bits mask */ -#define XUARTPS_RXWM_RESET_VAL 0x00000020 /**< Reset value */ -/* @} */ - -/** @name Transmit FIFO Trigger Level Register - * - * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at - * which the TX FIFO triggers an interrupt event. - * @{ - */ - -#define XUARTPS_TXWM_MASK 0x0000003F /**< Valid bits mask */ -#define XUARTPS_TXWM_RESET_VAL 0x00000020 /**< Reset value */ -/* @} */ - -/** @name Modem Control Register - * - * This register (MODEMCR) controls the interface with the modem or data set, - * or a peripheral device emulating a modem. - * - * @{ - */ -#define XUARTPS_MODEMCR_FCM 0x00000010 /**< Flow control mode */ -#define XUARTPS_MODEMCR_RTS 0x00000002 /**< Request to send */ -#define XUARTPS_MODEMCR_DTR 0x00000001 /**< Data terminal ready */ -/* @} */ - -/** @name Modem Status Register - * - * This register (MODEMSR) indicates the current state of the control lines - * from a modem, or another peripheral device, to the CPU. In addition, four - * bits of the modem status register provide change information. These bits - * are set to a logic 1 whenever a control input from the modem changes state. - * - * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem - * status interrupt is generated and this is reflected in the modem status - * register. - * - * @{ - */ -#define XUARTPS_MODEMSR_FCMS 0x00000100 /**< Flow control mode (FCMS) */ -#define XUARTPS_MODEMSR_DCD 0x00000080 /**< Complement of DCD input */ -#define XUARTPS_MODEMSR_RI 0x00000040 /**< Complement of RI input */ -#define XUARTPS_MODEMSR_DSR 0x00000020 /**< Complement of DSR input */ -#define XUARTPS_MODEMSR_CTS 0x00000010 /**< Complement of CTS input */ -#define XUARTPS_MODEMSR_DDCD 0x00000008 /**< Delta DCD indicator */ -#define XUARTPS_MODEMSR_TERI 0x00000004 /**< Trailing Edge Ring Indicator */ -#define XUARTPS_MODEMSR_DDSR 0x00000002 /**< Change of DSR */ -#define XUARTPS_MODEMSR_DCTS 0x00000001 /**< Change of CTS */ -/* @} */ - -/** @name Channel Status Register - * - * The channel status register (CSR) is provided to enable the control logic - * to monitor the status of bits in the channel interrupt status register, - * even if these are masked out by the interrupt mask register. - * - * @{ - */ -#define XUARTPS_SR_TNFUL 0x00004000 /**< TX FIFO Nearly Full Status */ -#define XUARTPS_SR_TTRIG 0x00002000 /**< TX FIFO Trigger Status */ -#define XUARTPS_SR_FLOWDEL 0x00001000 /**< RX FIFO fill over flow delay */ -#define XUARTPS_SR_TACTIVE 0x00000800 /**< TX active */ -#define XUARTPS_SR_RACTIVE 0x00000400 /**< RX active */ -#define XUARTPS_SR_DMS 0x00000200 /**< Delta modem status change */ -#define XUARTPS_SR_TOUT 0x00000100 /**< RX timeout */ -#define XUARTPS_SR_PARITY 0x00000080 /**< RX parity error */ -#define XUARTPS_SR_FRAME 0x00000040 /**< RX frame error */ -#define XUARTPS_SR_OVER 0x00000020 /**< RX overflow error */ -#define XUARTPS_SR_TXFULL 0x00000010 /**< TX FIFO full */ -#define XUARTPS_SR_TXEMPTY 0x00000008 /**< TX FIFO empty */ -#define XUARTPS_SR_RXFULL 0x00000004 /**< RX FIFO full */ -#define XUARTPS_SR_RXEMPTY 0x00000002 /**< RX FIFO empty */ -#define XUARTPS_SR_RXOVR 0x00000001 /**< RX FIFO fill over trigger */ -/* @} */ - -/** @name Flow Delay Register - * - * Operation of the flow delay register (FLOWDEL) is very similar to the - * receive FIFO trigger register. An internal trigger signal activates when the - * FIFO is filled to the level set by this register. This trigger will not - * cause an interrupt, although it can be read through the channel status - * register. In hardware flow control mode, RTS is deactivated when the trigger - * becomes active. RTS only resets when the FIFO level is four less than the - * level of the flow delay trigger and the flow delay trigger is not activated. - * A value less than 4 disables the flow delay. - * @{ - */ -#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */ -/* @} */ - - - -/* - * Defines for backwards compatabilty, will be removed - * in the next version of the driver - */ -#define XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD -#define XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI -#define XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR -#define XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS - - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - -/****************************************************************************/ -/** -* Read a UART register. -* -* @param BaseAddress contains the base address of the device. -* @param RegOffset contains the offset from the base address of the -* device. -* -* @return The value read from the register. -* -* @note C-Style signature: -* u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset) -* -******************************************************************************/ -#define XUartPs_ReadReg(BaseAddress, RegOffset) \ - Xil_In32((BaseAddress) + (RegOffset)) - -/***************************************************************************/ -/** -* Write a UART register. -* -* @param BaseAddress contains the base address of the device. -* @param RegOffset contains the offset from the base address of the -* device. -* @param RegisterValue is the value to be written to the register. -* -* @return None. -* -* @note C-Style signature: -* void XUartPs_WriteReg(u32 BaseAddress, int RegOffset, -* u16 RegisterValue) -* -******************************************************************************/ -#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ - Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue)) - -/****************************************************************************/ -/** -* Determine if there is receive data in the receiver and/or FIFO. -* -* @param BaseAddress contains the base address of the device. -* -* @return TRUE if there is receive data, FALSE otherwise. -* -* @note C-Style signature: -* u32 XUartPs_IsReceiveData(u32 BaseAddress) -* -******************************************************************************/ -#define XUartPs_IsReceiveData(BaseAddress) \ - !((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \ - XUARTPS_SR_RXEMPTY) == XUARTPS_SR_RXEMPTY) - -/****************************************************************************/ -/** -* Determine if a byte of data can be sent with the transmitter. -* -* @param BaseAddress contains the base address of the device. -* -* @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the -* FIFO. -* -* @note C-Style signature: -* u32 XUartPs_IsTransmitFull(u32 BaseAddress) -* -******************************************************************************/ -#define XUartPs_IsTransmitFull(BaseAddress) \ - ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \ - XUARTPS_SR_TXFULL) == XUARTPS_SR_TXFULL) - -/************************** Function Prototypes ******************************/ - -void XUartPs_SendByte(u32 BaseAddress, u8 Data); - -u8 XUartPs_RecvByte(u32 BaseAddress); - -void XUartPs_ResetHw(u32 BaseAddress); - -/************************** Variable Definitions *****************************/ - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xusbps.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xusbps.h deleted file mode 100644 index a4a552393bb0ddc428ac606be7786ae33e954f12..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xusbps.h +++ /dev/null @@ -1,1091 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** - * - * @file xusbps.h - * - * This file contains the implementation of the XUsbPs driver. It is the - * driver for an USB controller in DEVICE or HOST mode. - * - * <h2>Introduction</h2> - * - * The Spartan-3AF Embedded Peripheral Block contains a USB controller for - * communication with serial peripherals or hosts. The USB controller supports - * Host, Device and On the Go (OTG) applications. - * - * <h2>USB Controller Features</h2> - * - * - Supports Low Speed USB 1.1 (1.5Mbps), Full Speed USB 1.1 (12Mbps), and - * High Speed USB 2.0 (480Mbps) data speeds - * - Supports Device, Host and OTG operational modes - * - ULPI transceiver interface for USB 2.0 operation - * - Integrated USB Full and Low speed serial transceiver interfaces for lowest - * cost connections - * - * <h2>Initialization & Configuration</h2> - * - * The configuration of the USB driver happens in multiple stages: - * - * - (a) Configuration of the basic parameters: - * In this stage the basic parameters for the driver are configured, - * including the base address and the controller ID. - * - * - (b) Configuration of the DEVICE endpoints (if applicable): - * If DEVICE mode is desired, the endpoints of the controller need to be - * configured using the XUsbPs_DeviceConfig data structure. Once the - * endpoint configuration is set up in the data structure, the user needs to - * call XUsbPs_DeviceMemRequired() to obtain the required size of DMAable - * memory that the driver needs for operation with the given configuration. - * The user then needs to allocate the required amount of DMAable memory and - * finalize the configuration of the XUsbPs_DeviceConfig data structure, - * e.g. setting the DMAMemVirt and DMAMemPhys members. - * - * - (c) Configuration of the DEVICE modes: - * In the second stage the parameters for DEVICE are configured. - * The caller only needs to configure the modes that are - * actually used. Configuration is done with the: - * XUsbPs_ConfigureDevice() - * Configuration parameters are defined and passed - * into these functions using the: - * XUsbPs_DeviceConfig data structures. - * - * - * <h2>USB Device Endpoints</h2> - * - * The USB core supports up to 4 endpoints. Each endpoint has two directions, - * an OUT (RX) and an IN (TX) direction. Note that the direction is viewed from - * the host's perspective. Endpoint 0 defaults to be the control endpoint and - * does not need to be set up. Other endpoints need to be configured and set up - * depending on the application. Only endpoints that are actuelly used by the - * application need to be initialized. - * See the example code (xusbps_intr_example.c) for more information. - * - * - * <h2>Interrupt Handling</h2> - * - * The USB core uses one interrupt line to report interrupts to the CPU. - * Interrupts are handled by the driver's interrupt handler function - * XUsbPs_IntrHandler(). - * It has to be registered with the OS's interrupt subsystem. The driver's - * interrupt handler divides incoming interrupts into two categories: - * - * - General device interrupts - * - Endopint related interrupts - * - * The user (typically the adapter layer) can register general interrupt - * handler fucntions and endpoint specific interrupt handler functions with the - * driver to receive those interrupts by calling the - * XUsbPs_IntrSetHandler() - * and - * XUsbPs_EpSetHandler() - * functions respectively. Calling these functions with a NULL pointer as the - * argument for the function pointer will "clear" the handler function. - * - * The user can register one handler function for the generic interrupts and - * two handler functions for each endpoint, one for the RX (OUT) and one for - * the TX (IN) direction. For some applications it may be useful to register a - * single endpoint handler function for muliple endpoints/directions. - * - * When a callback function is called by the driver, parameters identifying the - * type of the interrupt will be passed into the handler functions. For general - * interrupts the interrupt mask will be passed into the handler function. For - * endpoint interrupts the parameters include the number of the endpoint, the - * direction (OUT/IN) and the type of the interrupt. - * - * - * <h2>Data buffer handling</h2> - * - * Data buffers are sent to and received from endpoint using the - * XUsbPs_EpBufferSend() - * and - * XUsbPs_EpBufferReceive() - * functions. - * - * User data buffer size is limited to 16 Kbytes. If the user wants to send a - * data buffer that is bigger than this limit it needs to break down the data - * buffer into multiple fragments and send the fragments individually. - * - * Data buffers can be aligned at any boundary. - * - * - * <h3>Zero copy</h3> - * - * The driver uses a zero copy mechanism which imposes certain restrictions to - * the way the user can handle the data buffers. - * - * One restriction is that the user needs to release a buffer after it is done - * processing the data in the buffer. - * - * Similarly, when the user sends a data buffer it MUST not re-use the buffer - * until it is notified by the driver that the buffer has been transmitted. The - * driver will notify the user via the registered endpoint interrupt handling - * function by sending a XUSBPS_EP_EVENT_DATA_TX event. - * - * - * <h2>DMA</h2> - * - * The driver uses DMA internally to move data from/to memory. This behaviour - * is transparent to the user. Keeping the DMA handling hidden from the user - * has the advantage that the same API can be used with USB cores that do not - * support DMA. - * - * - * <pre> - * MODIFICATION HISTORY: - * - * Ver Who Date Changes - * ----- ---- -------- ---------------------------------------------------------- - * 1.00a wgr 10/10/10 First release - * 1.02a wgr 05/16/12 Removed comments as they are showing up in SDK - * Tabs for CR 657898 - * 1.03a nm 09/21/12 Fixed CR#678977. Added proper sequence for setup packet - * handling. - * 1.04a nm 10/23/12 Fixed CR# 679106. - * 11/02/12 Fixed CR# 683931. Mult bits are set properly in dQH. - * </pre> - * - ******************************************************************************/ - -#ifndef XUSBPS_H -#define XUSBPS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xusbps_hw.h" -#include "xil_types.h" -#include "xstatus.h" - -/************************** Constant Definitions *****************************/ - -/** - * @name System hang prevention Timeout counter value. - * - * This value is used throughout the code to initialize a Timeout counter that - * is used when hard polling a register. The ides is to initialize the Timeout - * counter to a value that is longer than any expected Timeout but short enough - * so the system will continue to work and report an error while the user is - * still paying attention. A reasonable Timeout time would be about 10 seconds. - * The XUSBPS_TIMEOUT_COUNTER value should be chosen so a polling loop would - * run about 10 seconds before a Timeout is detected. For example: - * - * int Timeout = XUSBPS_TIMEOUT_COUNTER; - * while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - * XUSBPS_CMD_OFFSET) & - * XUSBPS_CMD_RST_MASK) && --Timeout) { - * ; - * } - * if (0 == Timeout) { - * return XST_FAILURE; - * } - * - */ -#define XUSBPS_TIMEOUT_COUNTER 1000000 - - -/** - * @name Endpoint Direction (bitmask) - * Definitions to be used with Endpoint related function that require a - * 'Direction' parameter. - * - * NOTE: - * The direction is always defined from the perspective of the HOST! This - * means that an IN endpoint on the controller is used for sending data while - * the OUT endpoint on the controller is used for receiving data. - * @{ - */ -#define XUSBPS_EP_DIRECTION_IN 0x01 /**< Endpoint direction IN. */ -#define XUSBPS_EP_DIRECTION_OUT 0x02 /**< Endpoint direction OUT. */ -/* @} */ - - -/** - * @name Endpoint Type - * Definitions to be used with Endpoint related functions that require a 'Type' - * parameter. - * @{ - */ -#define XUSBPS_EP_TYPE_NONE 0 /**< Endpoint is not used. */ -#define XUSBPS_EP_TYPE_CONTROL 1 /**< Endpoint for Control Transfers */ -#define XUSBPS_EP_TYPE_ISOCHRONOUS 2 /**< Endpoint for isochronous data */ -#define XUSBPS_EP_TYPE_BULK 3 /**< Endpoint for BULK Transfers. */ -#define XUSBPS_EP_TYPE_INTERRUPT 4 /**< Endpoint for interrupt Transfers */ -/* @} */ - -/** - * Endpoint Max Packet Length in DeviceConfig is a coded value, ch9.6.6. - * - * @{ - */ -#define ENDPOINT_MAXP_LENGTH 0x400 -#define ENDPOINT_MAXP_MULT_MASK 0xC00 -#define ENDPOINT_MAXP_MULT_SHIFT 10 -/* @} */ - -/** - * @name Field names for status retrieval - * Definitions for the XUsbPs_GetStatus() function call 'StatusType' - * parameter. - * @{ - */ -#define XUSBPS_EP_STS_ADDRESS 1 /**< Address of controller. */ -#define XUSBPS_EP_STS_CONTROLLER_STATE 2 /**< Current controller state. */ -/* @} */ - - - -/** - * @name USB Default alternate setting - * - * @{ - */ -#define XUSBPS_DEFAULT_ALT_SETTING 0 /**< The default alternate setting is 0 */ -/* @} */ - -/** - * @name Endpoint event types - * Definitions that are used to identify events that occur on endpoints. Passed - * to the endpoint event handler functions registered with - * XUsbPs_EpSetHandler(). - * @{ - */ -#define XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED 0x01 - /**< Setup data has been received on the enpoint. */ -#define XUSBPS_EP_EVENT_DATA_RX 0x02 - /**< Data frame has been received on the endpoint. */ -#define XUSBPS_EP_EVENT_DATA_TX 0x03 - /**< Data frame has been sent on the endpoint. */ -/* @} */ - - -/* - * Maximum packet size for endpoint, 1024 - * @{ - */ -#define XUSBPS_MAX_PACKET_SIZE 1024 - /**< Maximum value can be put into the queue head */ -/* @} */ -/**************************** Type Definitions *******************************/ - -/****************************************************************************** - * This data type defines the callback function to be used for Endpoint - * handlers. - * - * @param CallBackRef is the Callback reference passed in by the upper - * layer when setting the handler, and is passed back to the upper - * layer when the handler is called. - * @param EpNum is the Number of the endpoint that caused the event. - * @param EventType is the type of the event that occured on the endpoint. - * @param Data is a pointer to user data pointer specified when callback - * was registered. - */ -typedef void (*XUsbPs_EpHandlerFunc)(void *CallBackRef, - u8 EpNum, u8 EventType, void *Data); - - -/****************************************************************************** - * This data type defines the callback function to be used for the general - * interrupt handler. - * - * @param CallBackRef is the Callback reference passed in by the upper - * layer when setting the handler, and is passed back to the upper - * layer when the handler is called. - * @param IrqMask is the Content of the interrupt status register. This - * value can be used by the callback function to distinguish the - * individual interrupt types. - */ -typedef void (*XUsbPs_IntrHandlerFunc)(void *CallBackRef, u32 IrqMask); - - -/******************************************************************************/ - -/* The following type definitions are used for referencing Queue Heads and - * Transfer Descriptors. The structures themselves are not used, however, the - * types are used in the API to avoid using (void *) pointers. - */ -typedef u8 XUsbPs_dQH[XUSBPS_dQH_ALIGN]; -typedef u8 XUsbPs_dTD[XUSBPS_dTD_ALIGN]; - - -/** - * The following data structures are used internally by the L0/L1 driver. - * Their contents MUST NOT be changed by the upper layers. - */ - -/** - * The following data structure represents OUT endpoint. - */ -typedef struct { - XUsbPs_dQH *dQH; - /**< Pointer to the Queue Head structure of the endpoint. */ - - XUsbPs_dTD *dTDs; - /**< Pointer to the first dTD of the dTD list for this - * endpoint. */ - - XUsbPs_dTD *dTDCurr; - /**< Buffer to the currently processed descriptor. */ - - u8 *dTDBufs; - /**< Pointer to the first buffer of the buffer list for this - * endpoint. */ - - XUsbPs_EpHandlerFunc HandlerFunc; - /**< Handler function for this endpoint. */ - void *HandlerRef; - /**< User data reference for the handler. */ -} XUsbPs_EpOut; - - -/** - * The following data structure represents IN endpoint. - */ -typedef struct { - XUsbPs_dQH *dQH; - /**< Pointer to the Queue Head structure of the endpoint. */ - - XUsbPs_dTD *dTDs; - /**< List of pointers to the Transfer Descriptors of the - * endpoint. */ - - XUsbPs_dTD *dTDHead; - /**< Buffer to the next available descriptor in the list. */ - - XUsbPs_dTD *dTDTail; - /**< Buffer to the last unsent descriptor in the list*/ - - XUsbPs_EpHandlerFunc HandlerFunc; - /**< Handler function for this endpoint. */ - void *HandlerRef; - /**< User data reference for the handler. */ -} XUsbPs_EpIn; - - -/** - * The following data structure represents an endpoint used internally - * by the L0/L1 driver. - */ -typedef struct { - /* Each endpoint has an OUT and an IN component. - */ - XUsbPs_EpOut Out; /**< OUT endpoint structure */ - XUsbPs_EpIn In; /**< IN endpoint structure */ -} XUsbPs_Endpoint; - - - -/** - * The following structure is used by the user to receive Setup Data from an - * endpoint. Using this structure simplifies the process of interpreting the - * setup data in the core's data fields. - * - * The naming scheme for the members of this structure is different from the - * naming scheme found elsewhere in the code. The members of this structure are - * defined in the Chapter 9 USB reference guide. Using this naming scheme makes - * it easier for people familiar with the standard to read the code. - */ -typedef struct { - u8 bmRequestType; /**< bmRequestType in setup data */ - u8 bRequest; /**< bRequest in setup data */ - u16 wValue; /**< wValue in setup data */ - u16 wIndex; /**< wIndex in setup data */ - u16 wLength; /**< wLength in setup data */ -} -XUsbPs_SetupData; - - -/** - * Data structures used to configure endpoints. - */ -typedef struct { - u32 Type; - /**< Endpoint type: - - XUSBPS_EP_TYPE_CONTROL - - XUSBPS_EP_TYPE_ISOCHRONOUS - - XUSBPS_EP_TYPE_BULK - - XUSBPS_EP_TYPE_INTERRUPT */ - - u32 NumBufs; - /**< Number of buffers to be handled by this endpoint. */ - u32 BufSize; - /**< Buffer size. Only relevant for OUT (receive) Endpoints. */ - - u16 MaxPacketSize; - /**< Maximum packet size for this endpoint. This number will - * define the maximum number of bytes sent on the wire per - * transaction. Range: 0..1024 */ -} XUsbPs_EpSetup; - - -/** - * Endpoint configuration structure. - */ -typedef struct { - XUsbPs_EpSetup Out; /**< OUT component of endpoint. */ - XUsbPs_EpSetup In; /**< IN component of endpoint. */ -} XUsbPs_EpConfig; - - -/** - * The XUsbPs_DeviceConfig structure contains the configuration information to - * configure the USB controller for DEVICE mode. This data structure is used - * with the XUsbPs_ConfigureDevice() function call. - */ -typedef struct { - u8 NumEndpoints; /**< Number of Endpoints for the controller. - This number depends on the runtime - configuration of driver. The driver may - configure fewer endpoints than are available - in the core. */ - - XUsbPs_EpConfig EpCfg[XUSBPS_MAX_ENDPOINTS]; - /**< List of endpoint configurations. */ - - u32 DMAMemVirt; /**< Virtual base address of DMAable memory - allocated for the driver. */ - - u32 DMAMemPhys; /**< Physical base address of DMAable memory - allocated for the driver. */ - - /* The following members are used internally by the L0/L1 driver. They - * MUST NOT be accesses and/or modified in any way by the upper layers. - * - * The reason for having these members is that we generally try to - * avoid allocating memory in the L0/L1 driver as we want to be OS - * independent. In order to avoid allocating memory for this data - * structure wihin L0/L1 we put it into the XUsbPs_DeviceConfig - * structure which is allocated by the caller. - */ - XUsbPs_Endpoint Ep[XUSBPS_MAX_ENDPOINTS]; - /**< List of endpoint metadata structures. */ - - u32 PhysAligned; /**< 64 byte aligned base address of the DMA - memory block. Will be computed and set by - the L0/L1 driver. */ -} XUsbPs_DeviceConfig; - - -/** - * The XUsbPs_Config structure contains configuration information for the USB - * controller. - * - * This structure only contains the basic configuration for the controller. The - * caller also needs to initialize the controller for the DEVICE mode - * using the XUsbPs_DeviceConfig data structures with the - * XUsbPs_ConfigureDevice() function call - */ -typedef struct { - u16 DeviceID; /**< Unique ID of controller. */ - u32 BaseAddress; /**< Core register base address. */ -} XUsbPs_Config; - - -/** - * The XUsbPs driver instance data. The user is required to allocate a - * variable of this type for every USB controller in the system. A pointer to a - * variable of this type is then passed to the driver API functions. - */ -typedef struct { - XUsbPs_Config Config; /**< Configuration structure */ - - int CurrentAltSetting; /**< Current alternative setting of interface */ - - void *UserDataPtr; /**< Data pointer to be used by upper layers to - store application dependent data structures. - The upper layers are responsible to allocated - and free the memory. The driver will not - mofidy this data pointer. */ - - /** - * The following structures hold the configuration for DEVICE mode - * of the controller. They are initialized using the - * XUsbPs_ConfigureDevice() function call. - */ - XUsbPs_DeviceConfig DeviceConfig; - /**< Configuration for the DEVICE mode. */ - - XUsbPs_IntrHandlerFunc HandlerFunc; - /**< Handler function for the controller. */ - void *HandlerRef; - /**< User data reference for the handler. */ - u32 HandlerMask; - /**< User interrupt mask. Defines which interrupts will cause - * the callback to be called. */ -} XUsbPs; - - -/***************** Macros (Inline Functions) Definitions *********************/ - -/****************************************************************************** - * - * USB CONTROLLER RELATED MACROS - * - ******************************************************************************/ -/*****************************************************************************/ -/** - * This macro returns the current frame number. - * - * @param InstancePtr is a pointer to the XUsbPs instance of the - * controller. - * - * @return The current frame number. - * - * @note C-style signature: - * u32 XUsbPs_GetFrameNum(const XUsbPs *InstancePtr) - * - ******************************************************************************/ -#define XUsbPs_GetFrameNum(InstancePtr) \ - XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, XUSBPS_FRAME_OFFSET) - - -/*****************************************************************************/ -/** - * This macro starts the USB engine. - * - * @param InstancePtr is a pointer to the XUsbPs instance of the - * controller. - * - * @note C-style signature: - * void XUsbPs_Start(XUsbPs *InstancePtr) - * - ******************************************************************************/ -#define XUsbPs_Start(InstancePtr) \ - XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK) - - -/*****************************************************************************/ -/** - * This macro stops the USB engine. - * - * @param InstancePtr is a pointer to the XUsbPs instance of the - * controller. - * - * @note C-style signature: - * void XUsbPs_Stop(XUsbPs *InstancePtr) - * - ******************************************************************************/ -#define XUsbPs_Stop(InstancePtr) \ - XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK) - - -/*****************************************************************************/ -/** - * This macro forces the USB engine to be in Full Speed (FS) mode. - * - * @param InstancePtr is a pointer to the XUsbPs instance of the - * controller. - * - * @note C-style signature: - * void XUsbPs_ForceFS(XUsbPs *InstancePtr) - * - ******************************************************************************/ -#define XUsbPs_ForceFS(InstancePtr) \ - XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \ - XUSBPS_PORTSCR_PFSC_MASK) - - -/*****************************************************************************/ -/** - * This macro starts the USB Timer 0, with repeat option for period of - * one second. - * - * @param InstancePtr is a pointer to XUsbPs instance of the controller. - * @param Interval is the interval for Timer0 to generate an interrupt - * - * @note C-style signature: - * void XUsbPs_StartTimer0(XUsbPs *InstancePtr, u32 Interval) - * - ******************************************************************************/ -#define XUsbPs_StartTimer0(InstancePtr, Interval) \ -{ \ - XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \ - XUSBPS_TIMER0_LD_OFFSET, (Interval)); \ - XUsbPs_SetBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \ - XUSBPS_TIMER_RUN_MASK | \ - XUSBPS_TIMER_RESET_MASK | \ - XUSBPS_TIMER_REPEAT_MASK); \ -} \ - - -/*****************************************************************************/ -/** -* This macro stops Timer 0. -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* -* @note C-style signature: -* void XUsbPs_StopTimer0(XUsbPs *InstancePtr) -* -******************************************************************************/ -#define XUsbPs_StopTimer0(InstancePtr) \ - XUsbPs_ClrBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \ - XUSBPS_TIMER_RUN_MASK) - - -/*****************************************************************************/ -/** -* This macro reads Timer 0. -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* -* @note C-style signature: -* void XUsbPs_ReadTimer0(XUsbPs *InstancePtr) -* -******************************************************************************/ -#define XUsbPs_ReadTimer0(InstancePtr) \ - XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ - XUSBPS_TIMER0_CTL_OFFSET) & \ - XUSBPS_TIMER_COUNTER_MASK - - -/*****************************************************************************/ -/** -* This macro force remote wakeup on host -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* -* @note C-style signature: -* void XUsbPs_RemoteWakeup(XUsbPs *InstancePtr) -* -******************************************************************************/ -#define XUsbPs_RemoteWakeup(InstancePtr) \ - XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \ - XUSBPS_PORTSCR_FPR_MASK) - - -/****************************************************************************** - * - * ENDPOINT RELATED MACROS - * - ******************************************************************************/ -/*****************************************************************************/ -/** -* This macro enables the given endpoint for the given direction. -* -* @param InstancePtr is a pointer to the XUsbPs instance of the -* controller. -* @param EpNum is number of the endpoint to enable. -* @param Dir is direction of the endpoint (bitfield): -* - XUSBPS_EP_DIRECTION_OUT -* - XUSBPS_EP_DIRECTION_IN -* -* @note C-style signature: -* void XUsbPs_EpEnable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir) -* -******************************************************************************/ -#define XUsbPs_EpEnable(InstancePtr, EpNum, Dir) \ - XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \ - ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \ - ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0)) - - -/*****************************************************************************/ -/** -* This macro disables the given endpoint for the given direction. -* -* @param InstancePtr is a pointer to the XUsbPs instance of the -* controller. -* @param EpNum is the number of the endpoint to disable. -* @param Dir is the direction of the endpoint (bitfield): -* - XUSBPS_EP_DIRECTION_OUT -* - XUSBPS_EP_DIRECTION_IN -* -* @note C-style signature: -* void XUsbPs_EpDisable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir) -* -******************************************************************************/ -#define XUsbPs_EpDisable(InstancePtr, EpNum, Dir) \ - XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \ - ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \ - ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0)) - - -/*****************************************************************************/ -/** -* This macro stalls the given endpoint for the given direction, and flush -* the buffers. -* -* @param InstancePtr is a pointer to the XUsbPs instance of the -* controller. -* @param EpNum is number of the endpoint to stall. -* @param Dir is the direction of the endpoint (bitfield): -* - XUSBPS_EP_DIRECTION_OUT -* - XUSBPS_EP_DIRECTION_IN -* -* @note C-style signature: -* void XUsbPs_EpStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir) -* -******************************************************************************/ -#define XUsbPs_EpStall(InstancePtr, EpNum, Dir) \ - XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \ - ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \ - ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0)) - - -/*****************************************************************************/ -/** -* This macro unstalls the given endpoint for the given direction. -* -* @param InstancePtr is a pointer to the XUsbPs instance of the -* controller. -* @param EpNum is the Number of the endpoint to unstall. -* @param Dir is the Direction of the endpoint (bitfield): -* - XUSBPS_EP_DIRECTION_OUT -* - XUSBPS_EP_DIRECTION_IN -* -* @note C-style signature: -* void XUsbPs_EpUnStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir) -* -******************************************************************************/ -#define XUsbPs_EpUnStall(InstancePtr, EpNum, Dir) \ - XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \ - ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \ - ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0)) - - -/*****************************************************************************/ -/** -* This macro flush an endpoint upon interface disable -* -* @param InstancePtr is a pointer to the XUsbPs instance of the -* controller. -* @param EpNum is the number of the endpoint to flush. -* @param Dir is the direction of the endpoint (bitfield): -* - XUSBPS_EP_DIRECTION_OUT -* - XUSBPS_EP_DIRECTION_IN -* -* @note C-style signature: -* void XUsbPs_EpFlush(XUsbPs *InstancePtr, u8 EpNum, u8 Dir) -* -******************************************************************************/ -#define XUsbPs_EpFlush(InstancePtr, EpNum, Dir) \ - XUsbPs_SetBits(InstancePtr, XUSBPS_EPFLUSH_OFFSET, \ - EpNum << ((Dir) & XUSBPS_EP_DIRECTION_OUT ? \ - XUSBPS_EPFLUSH_RX_SHIFT:XUSBPS_EPFLUSH_TX_SHIFT)) \ - -/*****************************************************************************/ -/** -* This macro enables the interrupts defined by the bit mask. -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* @param IntrMask is the Bit mask of interrupts to be enabled. -* -* @note C-style signature: -* void XUsbPs_IntrEnable(XUsbPs *InstancePtr, u32 IntrMask) -* -******************************************************************************/ -#define XUsbPs_IntrEnable(InstancePtr, IntrMask) \ - XUsbPs_SetBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask) - - -/*****************************************************************************/ -/** -* This function disables the interrupts defined by the bit mask. -* -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* @param IntrMask is a Bit mask of interrupts to be disabled. -* -* @note C-style signature: -* void XUsbPs_IntrDisable(XUsbPs *InstancePtr, u32 IntrMask) -* -******************************************************************************/ -#define XUsbPs_IntrDisable(InstancePtr, IntrMask) \ - XUsbPs_ClrBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask) - - -/*****************************************************************************/ -/** -* This macro enables the endpoint NAK interrupts defined by the bit mask. -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be -* enabled. -* @note C-style signature: -* void XUsbPs_NakIntrEnable(XUsbPs *InstancePtr, u32 NakIntrMask) -* -******************************************************************************/ -#define XUsbPs_NakIntrEnable(InstancePtr, NakIntrMask) \ - XUsbPs_SetBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask) - - -/*****************************************************************************/ -/** -* This macro disables the endpoint NAK interrupts defined by the bit mask. -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* @param NakIntrMask is a Bit mask of endpoint NAK interrupts to be -* disabled. -* -* @note -* C-style signature: -* void XUsbPs_NakIntrDisable(XUsbPs *InstancePtr, u32 NakIntrMask) -* -******************************************************************************/ -#define XUsbPs_NakIntrDisable(InstancePtr, NakIntrMask) \ - XUsbPs_ClrBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask) - - -/*****************************************************************************/ -/** -* This function clears the endpoint NAK interrupts status defined by the -* bit mask. -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be cleared. -* -* @note C-style signature: -* void XUsbPs_NakIntrClear(XUsbPs *InstancePtr, u32 NakIntrMask) -* -******************************************************************************/ -#define XUsbPs_NakIntrClear(InstancePtr, NakIntrMask) \ - XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \ - XUSBPS_EPNAKISR_OFFSET, NakIntrMask) - - - -/*****************************************************************************/ -/** -* This macro sets the Interrupt Threshold value in the control register -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* @param Threshold is the Interrupt threshold to be set. -* Allowed values: -* - XUSBPS_CMD_ITHRESHOLD_0 - Immediate interrupt -* - XUSBPS_CMD_ITHRESHOLD_1 - 1 Frame -* - XUSBPS_CMD_ITHRESHOLD_2 - 2 Frames -* - XUSBPS_CMD_ITHRESHOLD_4 - 4 Frames -* - XUSBPS_CMD_ITHRESHOLD_8 - 8 Frames -* - XUSBPS_CMD_ITHRESHOLD_16 - 16 Frames -* - XUSBPS_CMD_ITHRESHOLD_32 - 32 Frames -* - XUSBPS_CMD_ITHRESHOLD_64 - 64 Frames -* -* @note -* C-style signature: -* void XUsbPs_SetIntrThreshold(XUsbPs *InstancePtr, u8 Threshold) -* -******************************************************************************/ -#define XUsbPs_SetIntrThreshold(InstancePtr, Threshold) \ - XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \ - XUSBPS_CMD_OFFSET, (Threshold))\ - - -/*****************************************************************************/ -/** -* This macro sets the Tripwire bit in the USB command register. -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* -* @note C-style signature: -* void XUsbPs_SetTripwire(XUsbPs *InstancePtr) -* -******************************************************************************/ -#define XUsbPs_SetTripwire(InstancePtr) \ - XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, \ - XUSBPS_CMD_ATDTW_MASK) - - -/*****************************************************************************/ -/** -* This macro clears the Tripwire bit in the USB command register. -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* -* @note C-style signature: -* void XUsbPs_ClrTripwire(XUsbPs *InstancePtr) -* -******************************************************************************/ -#define XUsbPs_ClrTripwire(InstancePtr) \ - XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, \ - XUSBPS_CMD_ATDTW_MASK) - - -/*****************************************************************************/ -/** -* This macro checks if the Tripwire bit in the USB command register is set. -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* -* @return -* - TRUE: The tripwire bit is still set. -* - FALSE: The tripwire bit has been cleared. -* -* @note C-style signature: -* int XUsbPs_TripwireIsSet(XUsbPs *InstancePtr) -* -******************************************************************************/ -#define XUsbPs_TripwireIsSet(InstancePtr) \ - (XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ - XUSBPS_CMD_OFFSET) & \ - XUSBPS_CMD_ATDTW_MASK ? TRUE : FALSE) - - -/****************************************************************************** -* -* GENERAL REGISTER / BIT MANIPULATION MACROS -* -******************************************************************************/ -/****************************************************************************/ -/** -* This macro sets the given bit mask in the register. -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* @param RegOffset is the register offset to be written. -* @param Bits is the Bits to be set in the register -* -* @return None. -* -* @note C-style signature: -* void XUsbPs_SetBits(u32 BaseAddress, u32 RegOffset, u32 Bits) -* -*****************************************************************************/ -#define XUsbPs_SetBits(InstancePtr, RegOffset, Bits) \ - XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \ - XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ - RegOffset) | (Bits)); - - -/****************************************************************************/ -/** -* -* This macro clears the given bits in the register. -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* @param RegOffset is the register offset to be written. -* @param Bits are the bits to be cleared in the register -* -* @return None. -* -* @note -* C-style signature: -* void XUsbPs_ClrBits(u32 BaseAddress, u32 RegOffset, u32 Bits) -* -*****************************************************************************/ -#define XUsbPs_ClrBits(InstancePtr, RegOffset, Bits) \ - XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \ - XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ - RegOffset) & ~(Bits)); - - -/************************** Function Prototypes ******************************/ - -/** - * Setup / Initialize functions. - * - * Implemented in file xusbps.c - */ -int XUsbPs_CfgInitialize(XUsbPs *InstancePtr, - const XUsbPs_Config *ConfigPtr, u32 BaseAddress); - -int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr, - const XUsbPs_DeviceConfig *CfgPtr); -u32 XUsbPs_DeviceMemRequired(const XUsbPs_DeviceConfig *CfgPtr); - -/** - * Common functions used for DEVICE/HOST mode. - */ -int XUsbPs_Reset(XUsbPs *InstancePtr); - -/** - * DEVICE mode specific functions. - */ -int XUsbPs_BusReset(XUsbPs *InstancePtr); -u32 XUsbPs_DeviceMemRequired(const XUsbPs_DeviceConfig *CfgPtr); -int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address); - - -/** - * Handling Suspend and Resume. - * - * Implemented in xusbps.c - */ -int XUsbPs_Suspend(const XUsbPs *InstancePtr); -int XUsbPs_Resume(const XUsbPs *InstancePtr); -int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr); - - -/* - * Functions for managing Endpoints / Transfers - * - * Implemented in file xusbps_endpoint.c - */ -int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum, - const u8 *BufferPtr, u32 BufferLen); -int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum, - u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle); -void XUsbPs_EpBufferRelease(u32 Handle); - -int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction, - XUsbPs_EpHandlerFunc CallBackFunc, - void *CallBackRef); -int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum, - XUsbPs_SetupData *SetupDataPtr); - -int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction); - -int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr, - int EpNum, unsigned short NewDirection, int DirectionChanged); - -/* - * Interrupt handling functions - * - * Implemented in file xusbps_intr.c - */ -void XUsbPs_IntrHandler(void *InstancePtr); - -int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr, - XUsbPs_IntrHandlerFunc CallBackFunc, - void *CallBackRef, u32 Mask); -/* - * Helper functions for static configuration. - * Implemented in xusbps_sinit.c - */ -XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceId); - -#ifdef __cplusplus -} -#endif - -#endif /* XUSBPS_H */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xusbps_endpoint.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xusbps_endpoint.h deleted file mode 100644 index 98d701c8338e2cab7e5e605a4d5f7643228e6ddb..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xusbps_endpoint.h +++ /dev/null @@ -1,521 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** - * - * @file xusbps_endpoint.h - * - * This is an internal file containung the definitions for endpoints. It is - * included by the xusbps_endpoint.c which is implementing the endpoint - * functions and by xusbps_intr.c. - * - * <pre> - * MODIFICATION HISTORY: - * - * Ver Who Date Changes - * ----- ---- -------- -------------------------------------------------------- - * 1.00a wgr 10/10/10 First release - * </pre> - * - ******************************************************************************/ -#ifndef XUSBPS_ENDPOINT_H -#define XUSBPS_ENDPOINT_H - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_cache.h" -#include "xusbps.h" -#include "xil_types.h" - -/**************************** Type Definitions *******************************/ - -/************************** Constant Definitions *****************************/ - - -/** - * Endpoint Device Transfer Descriptor - * - * The dTD describes to the device controller the location and quantity of data - * to be sent/received for given transfer. The driver does not attempt to - * modify any field in an active dTD except the Next Link Pointer. - */ -#define XUSBPS_dTDNLP 0x00 /**< Pointer to the next descriptor */ -#define XUSBPS_dTDTOKEN 0x04 /**< Descriptor Token */ -#define XUSBPS_dTDBPTR0 0x08 /**< Buffer Pointer 0 */ -#define XUSBPS_dTDBPTR1 0x0C /**< Buffer Pointer 1 */ -#define XUSBPS_dTDBPTR2 0x10 /**< Buffer Pointer 2 */ -#define XUSBPS_dTDBPTR3 0x14 /**< Buffer Pointer 3 */ -#define XUSBPS_dTDBPTR4 0x18 /**< Buffer Pointer 4 */ -#define XUSBPS_dTDBPTR(n) (XUSBPS_dTDBPTR0 + (n) * 0x04) -#define XUSBPS_dTDRSRVD 0x1C /**< Reserved field */ - -/* We use the reserved field in the dTD to store user data. */ -#define XUSBPS_dTDUSERDATA XUSBPS_dTDRSRVD /**< Reserved field */ - - -/** @name dTD Next Link Pointer (dTDNLP) bit positions. - * @{ - */ -#define XUSBPS_dTDNLP_T_MASK 0x00000001 - /**< USB dTD Next Link Pointer Terminate Bit */ -#define XUSBPS_dTDNLP_ADDR_MASK 0xFFFFFFE0 - /**< USB dTD Next Link Pointer Address [31:5] */ -/* @} */ - - -/** @name dTD Token (dTDTOKEN) bit positions. - * @{ - */ -#define XUSBPS_dTDTOKEN_XERR_MASK 0x00000008 /**< dTD Transaction Error */ -#define XUSBPS_dTDTOKEN_BUFERR_MASK 0x00000020 /**< dTD Data Buffer Error */ -#define XUSBPS_dTDTOKEN_HALT_MASK 0x00000040 /**< dTD Halted Flag */ -#define XUSBPS_dTDTOKEN_ACTIVE_MASK 0x00000080 /**< dTD Active Bit */ -#define XUSBPS_dTDTOKEN_MULTO_MASK 0x00000C00 /**< Multiplier Override Field [1:0] */ -#define XUSBPS_dTDTOKEN_IOC_MASK 0x00008000 /**< Interrupt on Complete Bit */ -#define XUSBPS_dTDTOKEN_LEN_MASK 0x7FFF0000 /**< Transfer Length Field */ -/* @} */ - - -/***************** Macros (Inline Functions) Definitions *********************/ - -/*****************************************************************************/ -/** - * - * IMPORTANT NOTE: - * =============== - * - * Many of the following macros modify Device Queue Head (dQH) data structures - * and Device Transfer Descriptor (dTD) data structures. Those structures can - * potentially reside in CACHED memory. Therefore, it's the callers - * responsibility to ensure cache coherency by using provided - * - * XUsbPs_dQHInvalidateCache() - * XUsbPs_dQHFlushCache() - * XUsbPs_dTDInvalidateCache() - * XUsbPs_dTDFlushCache() - * - * function calls. - * - ******************************************************************************/ -#define XUsbPs_dTDInvalidateCache(dTDPtr) \ - Xil_DCacheInvalidateRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD)) - -#define XUsbPs_dTDFlushCache(dTDPtr) \ - Xil_DCacheFlushRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD)) - -#define XUsbPs_dQHInvalidateCache(dQHPtr) \ - Xil_DCacheInvalidateRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH)) - -#define XUsbPs_dQHFlushCache(dQHPtr) \ - Xil_DCacheFlushRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH)) - -/*****************************************************************************/ -/** - * - * This macro sets the Transfer Length for the given Transfer Descriptor. - * - * @param dTDPtr is pointer to the dTD element. - * @param Len is the length to be set. Range: 0..16384 - * - * @note C-style signature: - * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len) - * - ******************************************************************************/ -#define XUsbPs_dTDSetTransferLen(dTDPtr, Len) \ - XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \ - (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \ - ~XUSBPS_dTDTOKEN_LEN_MASK) | ((Len) << 16)) - - -/*****************************************************************************/ -/** - * - * This macro gets the Next Link pointer of the given Transfer Descriptor. - * - * @param dTDPtr is pointer to the dTD element. - * - * @return TransferLength field of the descriptor. - * - * @note C-style signature: - * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr) - * - ******************************************************************************/ -#define XUsbPs_dTDGetNLP(dTDPtr) \ - (XUsbPs_dTD *) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP)\ - & XUSBPS_dTDNLP_ADDR_MASK)) - - -/*****************************************************************************/ -/** - * - * This macro sets the Next Link pointer of the given Transfer Descriptor. - * - * @param dTDPtr is a pointer to the dTD element. - * @param NLP is the Next Link Pointer - * - * @note C-style signature: - * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len) - * - ******************************************************************************/ -#define XUsbPs_dTDSetNLP(dTDPtr, NLP) \ - XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \ - (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \ - ~XUSBPS_dTDNLP_ADDR_MASK) | \ - ((NLP) & XUSBPS_dTDNLP_ADDR_MASK)) - - -/*****************************************************************************/ -/** - * - * This macro gets the Transfer Length for the given Transfer Descriptor. - * - * @param dTDPtr is a pointer to the dTD element. - * - * @return TransferLength field of the descriptor. - * - * @note C-style signature: - * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr) - * - ******************************************************************************/ -#define XUsbPs_dTDGetTransferLen(dTDPtr) \ - (u32) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) \ - & XUSBPS_dTDTOKEN_LEN_MASK) >> 16) - - -/*****************************************************************************/ -/** - * - * This macro sets the Interrupt On Complete (IOC) bit for the given Transfer - * Descriptor. - * - * @param dTDPtr is a pointer to the dTD element. - * - * @note C-style signature: - * void XUsbPs_dTDSetIOC(u32 dTDPtr) - * - ******************************************************************************/ -#define XUsbPs_dTDSetIOC(dTDPtr) \ - XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \ - XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \ - XUSBPS_dTDTOKEN_IOC_MASK) - - -/*****************************************************************************/ -/** - * - * This macro sets the Terminate bit for the given Transfer Descriptor. - * - * @param dTDPtr is a pointer to the dTD element. - * - * @note C-style signature: - * void XUsbPs_dTDSetTerminate(u32 dTDPtr) - * - ******************************************************************************/ -#define XUsbPs_dTDSetTerminate(dTDPtr) \ - XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \ - XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) | \ - XUSBPS_dTDNLP_T_MASK) - - -/*****************************************************************************/ -/** - * - * This macro clears the Terminate bit for the given Transfer Descriptor. - * - * @param dTDPtr is a pointer to the dTD element. - * - * @note C-style signature: - * void XUsbPs_dTDClrTerminate(u32 dTDPtr) - * - ******************************************************************************/ -#define XUsbPs_dTDClrTerminate(dTDPtr) \ - XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \ - XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \ - ~XUSBPS_dTDNLP_T_MASK) - - -/*****************************************************************************/ -/** - * - * This macro checks if the given descriptor is active. - * - * @param dTDPtr is a pointer to the dTD element. - * - * @return - * - TRUE: The buffer is active. - * - FALSE: The buffer is not active. - * - * @note C-style signature: - * int XUsbPs_dTDIsActive(u32 dTDPtr) - * - ******************************************************************************/ -#define XUsbPs_dTDIsActive(dTDPtr) \ - ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \ - XUSBPS_dTDTOKEN_ACTIVE_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * - * This macro sets the Active bit for the given Transfer Descriptor. - * - * @param dTDPtr is a pointer to the dTD element. - * - * @note C-style signature: - * void XUsbPs_dTDSetActive(u32 dTDPtr) - * - ******************************************************************************/ -#define XUsbPs_dTDSetActive(dTDPtr) \ - XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \ - XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \ - XUSBPS_dTDTOKEN_ACTIVE_MASK) - - -/*****************************************************************************/ -/** - * - * This macro reads the content of a field in a Transfer Descriptor. - * - * @param dTDPtr is a pointer to the dTD element. - * @param Id is the field ID inside the dTD element to read. - * - * @note C-style signature: - * u32 XUsbPs_ReaddTD(u32 dTDPtr, u32 Id) - * - ******************************************************************************/ -#define XUsbPs_ReaddTD(dTDPtr, Id) (*(u32 *)((u32)(dTDPtr) + (u32)(Id))) - -/*****************************************************************************/ -/** - * - * This macro writes a value to a field in a Transfer Descriptor. - * - * @param dTDPtr is pointer to the dTD element. - * @param Id is the field ID inside the dTD element to read. - * @param Val is the value to write to the field. - * - * @note C-style signature: - * u32 XUsbPs_WritedTD(u32 dTDPtr, u32 Id, u32 Val) - * - ******************************************************************************/ -#define XUsbPs_WritedTD(dTDPtr, Id, Val) \ - (*(u32 *) ((u32)(dTDPtr) + (u32)(Id)) = (u32)(Val)) - - -/******************************************************************************/ -/** - * Endpoint Device Queue Head - * - * Device queue heads are arranged in an array in a continuous area of memory - * pointed to by the ENDPOINTLISTADDR pointer. The device controller will index - * into this array based upon the endpoint number received from the USB bus. - * All information necessary to respond to transactions for all primed - * transfers is contained in this list so the Device Controller can readily - * respond to incoming requests without having to traverse a linked list. - * - * The device Endpoint Queue Head (dQH) is where all transfers are managed. The - * dQH is a 48-byte data structure, but must be aligned on a 64-byte boundary. - * During priming of an endpoint, the dTD (device transfer descriptor) is - * copied into the overlay area of the dQH, which starts at the nextTD pointer - * DWord and continues through the end of the buffer pointers DWords. After a - * transfer is complete, the dTD status DWord is updated in the dTD pointed to - * by the currentTD pointer. While a packet is in progress, the overlay area of - * the dQH is used as a staging area for the dTD so that the Device Controller - * can access needed information with little minimal latency. - * - * @note - * Software must ensure that no interface data structure reachable by the - * Device Controller spans a 4K-page boundary. The first element of the - * Endpoint Queue Head List must be aligned on a 4K boundary. - */ -#define XUSBPS_dQHCFG 0x00 /**< dQH Configuration */ -#define XUSBPS_dQHCPTR 0x04 /**< dQH Current dTD Pointer */ -#define XUSBPS_dQHdTDNLP 0x08 /**< dTD Next Link Ptr in dQH - overlay */ -#define XUSBPS_dQHdTDTOKEN 0x0C /**< dTD Token in dQH overlay */ -#define XUSBPS_dQHSUB0 0x28 /**< USB dQH Setup Buffer 0 */ -#define XUSBPS_dQHSUB1 0x2C /**< USB dQH Setup Buffer 1 */ - - -/** @name dQH Configuration (dQHCFG) bit positions. - * @{ - */ -#define XUSBPS_dQHCFG_IOS_MASK 0x00008000 - /**< USB dQH Interrupt on Setup Bit */ -#define XUSBPS_dQHCFG_MPL_MASK 0x07FF0000 - /**< USB dQH Maximum Packet Length - * Field [10:0] */ -#define XUSBPS_dQHCFG_MPL_SHIFT 16 -#define XUSBPS_dQHCFG_ZLT_MASK 0x20000000 - /**< USB dQH Zero Length Termination - * Select Bit */ -#define XUSBPS_dQHCFG_MULT_MASK 0xC0000000 - /* USB dQH Number of Transactions Field - * [1:0] */ -#define XUSBPS_dQHCFG_MULT_SHIFT 30 -/* @} */ - - -/*****************************************************************************/ -/** - * - * This macro sets the Maximum Packet Length field of the give Queue Head. - * - * @param dQHPtr is a pointer to the dQH element. - * @param Len is the length to be set. - * - * @note C-style signature: - * void XUsbPs_dQHSetMaxPacketLen(u32 dQHPtr, u32 Len) - * - ******************************************************************************/ -#define XUsbPs_dQHSetMaxPacketLen(dQHPtr, Len) \ - XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ - (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \ - ~XUSBPS_dQHCFG_MPL_MASK) | ((Len) << 16)) - -/*****************************************************************************/ -/** - * - * This macro sets the Interrupt On Setup (IOS) bit for an endpoint. - * - * @param dQHPtr is a pointer to the dQH element. - * - * @note C-style signature: - * void XUsbPs_dQHSetIOS(u32 dQHPtr) - * - ******************************************************************************/ -#define XUsbPs_dQHSetIOS(dQHPtr) \ - XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ - XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \ - XUSBPS_dQHCFG_IOS_MASK) - -/*****************************************************************************/ -/** - * - * This macro clears the Interrupt On Setup (IOS) bit for an endpoint. - * - * @param dQHPtr is a pointer to the dQH element. - * - * @note C-style signature: - * void XUsbPs_dQHClrIOS(u32 dQHPtr) - * - ******************************************************************************/ -#define XUsbPs_dQHClrIOS(dQHPtr) \ - XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ - XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \ - ~XUSBPS_dQHCFG_IOS_MASK) - -/*****************************************************************************/ -/** - * - * This macro enables Zero Length Termination for the endpoint. - * - * @param dQHPtr is a pointer to the dQH element. - * - * @note C-style signature: - * void XUsbPs_dQHEnableZLT(u32 dQHPtr) - * - * - ******************************************************************************/ -#define XUsbPs_dQHEnableZLT(dQHPtr) \ - XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ - XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \ - ~XUSBPS_dQHCFG_ZLT_MASK) - - -/*****************************************************************************/ -/** - * - * This macro disables Zero Length Termination for the endpoint. - * - * @param dQHPtr is a pointer to the dQH element. - * - * @note C-style signature: - * void XUsbPs_dQHDisableZLT(u32 dQHPtr) - * - * - ******************************************************************************/ -#define XUsbPs_dQHDisableZLT(dQHPtr) \ - XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ - XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \ - XUSBPS_dQHCFG_ZLT_MASK) - -/*****************************************************************************/ -/** - * - * This macro reads the content of a field in a Queue Head. - * - * @param dQHPtr is a pointer to the dQH element. - * @param Id is the Field ID inside the dQH element to read. - * - * @note C-style signature: - * u32 XUsbPs_ReaddQH(u32 dQHPtr, u32 Id) - * - ******************************************************************************/ -#define XUsbPs_ReaddQH(dQHPtr, Id) (*(u32 *)((u32)(dQHPtr) + (u32) (Id))) - -/*****************************************************************************/ -/** - * - * This macro writes a value to a field in a Queue Head. - * - * @param dQHPtr is a pointer to the dQH element. - * @param Id is the Field ID inside the dQH element to read. - * @param Val is the Value to write to the field. - * - * @note C-style signature: - * u32 XUsbPs_WritedQH(u32 dQHPtr, u32 Id, u32 Val) - * - ******************************************************************************/ -#define XUsbPs_WritedQH(dQHPtr, Id, Val) \ - (*(u32 *) ((u32)(dQHPtr) + (u32)(Id)) = (u32)(Val)) - - - -#ifdef __cplusplus -} -#endif - -#endif /* XUSBPS_ENDPOINT_H */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xusbps_hw.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xusbps_hw.h deleted file mode 100644 index 5986f65bd885edf99fb8f9c959d190813be5e4e2..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xusbps_hw.h +++ /dev/null @@ -1,531 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** - * - * @file xusbps_hw.h - * - * This header file contains identifiers and low-level driver functions (or - * macros) that can be used to access the device. High-level driver functions - * are defined in xusbps.h. - * - * <pre> - * MODIFICATION HISTORY: - * - * Ver Who Date Changes - * ----- ---- -------- ----------------------------------------------- - * 1.00a wgr 10/10/10 First release - * 1.04a nm 10/23/12 Fixed CR# 679106. - * 1.05a kpc 07/03/13 Added XUsbPs_ResetHw function prototype - * </pre> - * - ******************************************************************************/ -#ifndef XUSBPS_HW_H -#define XUSBPS_HW_H - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xil_io.h" - -/************************** Constant Definitions *****************************/ - - -#define XUSBPS_REG_SPACING 4 - -/** @name Timer 0 Register offsets - * - * @{ - */ -#define XUSBPS_TIMER0_LD_OFFSET 0x00000080 -#define XUSBPS_TIMER0_CTL_OFFSET 0x00000084 -/* @} */ - -/** @name Timer Control Register bit mask - * - * @{ - */ -#define XUSBPS_TIMER_RUN_MASK 0x80000000 -#define XUSBPS_TIMER_STOP_MASK 0x80000000 -#define XUSBPS_TIMER_RESET_MASK 0x40000000 -#define XUSBPS_TIMER_REPEAT_MASK 0x01000000 -/* @} */ - -/** @name Timer Control Register bit mask - * - * @{ - */ -#define XUSBPS_TIMER_COUNTER_MASK 0x00FFFFFF -/* @} */ - -/** @name Device Hardware Parameters - * - * @{ - */ -#define XUSBPS_HWDEVICE_OFFSET 0x0000000C - -#define XUSBPS_EP_NUM_MASK 0x3E -#define XUSBPS_EP_NUM_SHIFT 1 -/* @} */ - -/** @name Capability Regsiter offsets - */ -#define XUSBPS_HCSPARAMS_OFFSET 0x00000104 - -/** @name Operational Register offsets. - * Register comments are tagged with "H:" and "D:" for Host and Device modes, - * respectively. - * Tags are only present for registers that have a different meaning DEVICE and - * HOST modes. Most registers are only valid for either DEVICE or HOST mode. - * Those registers don't have tags. - * @{ - */ -#define XUSBPS_CMD_OFFSET 0x00000140 /**< Configuration */ -#define XUSBPS_ISR_OFFSET 0x00000144 /**< Interrupt Status */ -#define XUSBPS_IER_OFFSET 0x00000148 /**< Interrupt Enable */ -#define XUSBPS_FRAME_OFFSET 0x0000014C /**< USB Frame Index */ -#define XUSBPS_LISTBASE_OFFSET 0x00000154 /**< H: Periodic List Base Address */ -#define XUSBPS_DEVICEADDR_OFFSET 0x00000154 /**< D: Device Address */ -#define XUSBPS_ASYNCLISTADDR_OFFSET 0x00000158 /**< H: Async List Address */ -#define XUSBPS_EPLISTADDR_OFFSET 0x00000158 /**< D: Endpoint List Addr */ -#define XUSBPS_TTCTRL_OFFSET 0x0000015C /**< TT Control */ -#define XUSBPS_BURSTSIZE_OFFSET 0x00000160 /**< Burst Size */ -#define XUSBPS_TXFILL_OFFSET 0x00000164 /**< Tx Fill Tuning */ -#define XUSBPS_ULPIVIEW_OFFSET 0x00000170 /**< ULPI Viewport */ -#define XUSBPS_EPNAKISR_OFFSET 0x00000178 /**< Endpoint NAK IRQ Status */ -#define XUSBPS_EPNAKIER_OFFSET 0x0000017C /**< Endpoint NAK IRQ Enable */ -#define XUSBPS_PORTSCR1_OFFSET 0x00000184 /**< Port Control/Status 1 */ - -/* NOTE: The Port Control / Status Register index is 1-based. */ -#define XUSBPS_PORTSCRn_OFFSET(n) \ - (XUSBPS_PORTSCR1_OFFSET + (((n)-1) * XUSBPS_REG_SPACING)) - - -#define XUSBPS_OTGCSR_OFFSET 0x000001A4 /**< OTG Status and Control */ -#define XUSBPS_MODE_OFFSET 0x000001A8 /**< USB Mode */ -#define XUSBPS_EPSTAT_OFFSET 0x000001AC /**< Endpoint Setup Status */ -#define XUSBPS_EPPRIME_OFFSET 0x000001B0 /**< Endpoint Prime */ -#define XUSBPS_EPFLUSH_OFFSET 0x000001B4 /**< Endpoint Flush */ -#define XUSBPS_EPRDY_OFFSET 0x000001B8 /**< Endpoint Ready */ -#define XUSBPS_EPCOMPL_OFFSET 0x000001BC /**< Endpoint Complete */ -#define XUSBPS_EPCR0_OFFSET 0x000001C0 /**< Endpoint Control 0 */ -#define XUSBPS_EPCR1_OFFSET 0x000001C4 /**< Endpoint Control 1 */ -#define XUSBPS_EPCR2_OFFSET 0x000001C8 /**< Endpoint Control 2 */ -#define XUSBPS_EPCR3_OFFSET 0x000001CC /**< Endpoint Control 3 */ -#define XUSBPS_EPCR4_OFFSET 0x000001D0 /**< Endpoint Control 4 */ - -#define XUSBPS_MAX_ENDPOINTS 4 /**< Number of supported Endpoints in - * this core. */ -#define XUSBPS_EP_OUT_MASK 0x0000001F /**< OUR (RX) endpoint mask */ -#define XUSBPS_EP_IN_MASK 0x001F0000 /**< IN (TX) endpoint mask */ -#define XUSBPS_EP_ALL_MASK 0x001F001F /**< Mask used for endpoint control - * registers */ -#define XUSBPS_EPCRn_OFFSET(n) \ - (XUSBPS_EPCR0_OFFSET + ((n) * XUSBPS_REG_SPACING)) - -#define XUSBPS_EPFLUSH_RX_SHIFT 0 -#define XUSBPS_EPFLUSH_TX_SHIFT 16 - -/* @} */ - - - -/** @name Endpoint Control Register (EPCR) bit positions. - * @{ - */ - -/* Definitions for TX Endpoint bits */ -#define XUSBPS_EPCR_TXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - TX */ -#define XUSBPS_EPCR_TXT_ISO_MASK 0x00040000 /**< Isochronous. Endpoint */ -#define XUSBPS_EPCR_TXT_BULK_MASK 0x00080000 /**< Bulk Endpoint - TX */ -#define XUSBPS_EPCR_TXT_INTR_MASK 0x000C0000 /**< Interrupt Endpoint */ -#define XUSBPS_EPCR_TXS_MASK 0x00010000 /**< Stall TX endpoint */ -#define XUSBPS_EPCR_TXE_MASK 0x00800000 /**< Transmit enable - TX */ -#define XUSBPS_EPCR_TXR_MASK 0x00400000 /**< Data Toggle Reset Bit */ - - -/* Definitions for RX Endpoint bits */ -#define XUSBPS_EPCR_RXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - RX */ -#define XUSBPS_EPCR_RXT_ISO_MASK 0x00000004 /**< Isochronous Endpoint */ -#define XUSBPS_EPCR_RXT_BULK_MASK 0x00000008 /**< Bulk Endpoint - RX */ -#define XUSBPS_EPCR_RXT_INTR_MASK 0x0000000C /**< Interrupt Endpoint */ -#define XUSBPS_EPCR_RXS_MASK 0x00000001 /**< Stall RX endpoint. */ -#define XUSBPS_EPCR_RXE_MASK 0x00000080 /**< Transmit enable. - RX */ -#define XUSBPS_EPCR_RXR_MASK 0x00000040 /**< Data Toggle Reset Bit */ -/* @} */ - - -/** @name USB Command Register (CR) bit positions. - * @{ - */ -#define XUSBPS_CMD_RS_MASK 0x00000001 /**< Run/Stop */ -#define XUSBPS_CMD_RST_MASK 0x00000002 /**< Controller RESET */ -#define XUSBPS_CMD_FS01_MASK 0x0000000C /**< Frame List Size bit 0,1 */ -#define XUSBPS_CMD_PSE_MASK 0x00000010 /**< Periodic Sched Enable */ -#define XUSBPS_CMD_ASE_MASK 0x00000020 /**< Async Sched Enable */ -#define XUSBPS_CMD_IAA_MASK 0x00000040 /**< IRQ Async Advance Doorbell */ -#define XUSBPS_CMD_ASP_MASK 0x00000300 /**< Async Sched Park Mode Cnt */ -#define XUSBPS_CMD_ASPE_MASK 0x00000800 /**< Async Sched Park Mode Enbl */ -#define XUSBPS_CMD_SUTW_MASK 0x00002000 /**< Setup TripWire */ -#define XUSBPS_CMD_ATDTW_MASK 0x00004000 /**< Add dTD TripWire */ -#define XUSBPS_CMD_FS2_MASK 0x00008000 /**< Frame List Size bit 2 */ -#define XUSBPS_CMD_ITC_MASK 0x00FF0000 /**< IRQ Threshold Control */ -/* @} */ - - -/** - * @name Interrupt Threshold - * These definitions are used by software to set the maximum rate at which the - * USB controller will generate interrupt requests. The interrupt interval is - * given in number of micro-frames. - * - * USB defines a full-speed 1 ms frame time indicated by a Start Of Frame (SOF) - * packet each and every 1ms. USB also defines a high-speed micro-frame with a - * 125us frame time. For each micro-frame a SOF (Start Of Frame) packet is - * generated. Data is sent in between the SOF packets. The interrupt threshold - * defines how many micro-frames the controller waits before issuing an - * interrupt after data has been received. - * - * For a threshold of 0 the controller will issue an interrupt immediately - * after the last byte of the data has been received. For a threshold n>0 the - * controller will wait for n micro-frames before issuing an interrupt. - * - * Therefore, a setting of 8 micro-frames (default) means that the controller - * will issue at most 1 interrupt per millisecond. - * - * @{ - */ -#define XUSBPS_CMD_ITHRESHOLD_0 0x00 /**< Immediate interrupt. */ -#define XUSBPS_CMD_ITHRESHOLD_1 0x01 /**< 1 micro-frame */ -#define XUSBPS_CMD_ITHRESHOLD_2 0x02 /**< 2 micro-frames */ -#define XUSBPS_CMD_ITHRESHOLD_4 0x04 /**< 4 micro-frames */ -#define XUSBPS_CMD_ITHRESHOLD_8 0x08 /**< 8 micro-frames */ -#define XUSBPS_CMD_ITHRESHOLD_16 0x10 /**< 16 micro-frames */ -#define XUSBPS_CMD_ITHRESHOLD_32 0x20 /**< 32 micro-frames */ -#define XUSBPS_CMD_ITHRESHOLD_64 0x40 /**< 64 micro-frames */ -#define XUSBPS_CMD_ITHRESHOLD_MAX XUSBPS_CMD_ITHRESHOLD_64 -#define XUSBPS_CMD_ITHRESHOLD_DEFAULT XUSBPS_CMD_ITHRESHOLD_8 -/* @} */ - - - -/** @name USB Interrupt Status Register (ISR) / Interrupt Enable Register (IER) - * bit positions. - * @{ - */ -#define XUSBPS_IXR_UI_MASK 0x00000001 /**< USB Transaction Complete */ -#define XUSBPS_IXR_UE_MASK 0x00000002 /**< Transaction Error */ -#define XUSBPS_IXR_PC_MASK 0x00000004 /**< Port Change Detect */ -#define XUSBPS_IXR_FRE_MASK 0x00000008 /**< Frame List Rollover */ -#define XUSBPS_IXR_AA_MASK 0x00000020 /**< Async Advance */ -#define XUSBPS_IXR_UR_MASK 0x00000040 /**< RESET Received */ -#define XUSBPS_IXR_SR_MASK 0x00000080 /**< Start of Frame */ -#define XUSBPS_IXR_SLE_MASK 0x00000100 /**< Device Controller Suspend */ -#define XUSBPS_IXR_ULPI_MASK 0x00000400 /**< ULPI IRQ */ -#define XUSBPS_IXR_HCH_MASK 0x00001000 /**< Host Controller Halted - * Read Only */ -#define XUSBPS_IXR_RCL_MASK 0x00002000 /**< USB Reclamation Read Only */ -#define XUSBPS_IXR_PS_MASK 0x00004000 /**< Periodic Sched Status - * Read Only */ -#define XUSBPS_IXR_AS_MASK 0x00008000 /**< Async Sched Status Read only */ -#define XUSBPS_IXR_NAK_MASK 0x00010000 /**< NAK IRQ */ -#define XUSBPS_IXR_UA_MASK 0x00040000 /**< USB Host Async IRQ */ -#define XUSBPS_IXR_UP_MASK 0x00080000 /**< USB Host Periodic IRQ */ -#define XUSBPS_IXR_TI0_MASK 0x01000000 /**< Timer 0 Interrupt */ -#define XUSBPS_IXR_TI1_MASK 0x02000000 /**< Timer 1 Interrupt */ - -#define XUSBPS_IXR_ALL (XUSBPS_IXR_UI_MASK | \ - XUSBPS_IXR_UE_MASK | \ - XUSBPS_IXR_PC_MASK | \ - XUSBPS_IXR_FRE_MASK | \ - XUSBPS_IXR_AA_MASK | \ - XUSBPS_IXR_UR_MASK | \ - XUSBPS_IXR_SR_MASK | \ - XUSBPS_IXR_SLE_MASK | \ - XUSBPS_IXR_ULPI_MASK | \ - XUSBPS_IXR_HCH_MASK | \ - XUSBPS_IXR_RCL_MASK | \ - XUSBPS_IXR_PS_MASK | \ - XUSBPS_IXR_AS_MASK | \ - XUSBPS_IXR_NAK_MASK | \ - XUSBPS_IXR_UA_MASK | \ - XUSBPS_IXR_UP_MASK | \ - XUSBPS_IXR_TI0_MASK | \ - XUSBPS_IXR_TI1_MASK) - /**< Mask for ALL IRQ types */ -/* @} */ - - -/** @name USB Mode Register (MODE) bit positions. - * @{ - */ -#define XUSBPS_MODE_CM_MASK 0x00000003 /**< Controller Mode Select */ -#define XUSBPS_MODE_CM_IDLE_MASK 0x00000000 -#define XUSBPS_MODE_CM_DEVICE_MASK 0x00000002 -#define XUSBPS_MODE_CM_HOST_MASK 0x00000003 -#define XUSBPS_MODE_ES_MASK 0x00000004 /**< USB Endian Select */ -#define XUSBPS_MODE_SLOM_MASK 0x00000008 /**< USB Setup Lockout Mode Disable */ -#define XUSBPS_MODE_SDIS_MASK 0x00000010 -#define XUSBPS_MODE_VALID_MASK 0x0000001F - -/* @} */ - - -/** @name USB Device Address Register (DEVICEADDR) bit positions. - * @{ - */ -#define XUSBPS_DEVICEADDR_DEVICEAADV_MASK 0x01000000 - /**< Device Addr Auto Advance */ -#define XUSBPS_DEVICEADDR_ADDR_MASK 0xFE000000 - /**< Device Address */ -#define XUSBPS_DEVICEADDR_ADDR_SHIFT 25 - /**< Address shift */ -#define XUSBPS_DEVICEADDR_MAX 127 - /**< Biggest allowed address */ -/* @} */ - -/** @name USB TT Control Register (TTCTRL) bit positions. - * @{ - */ -#define XUSBPS_TTCTRL_HUBADDR_MASK 0x7F000000 /**< TT Hub Address */ -/* @} */ - - -/** @name USB Burst Size Register (BURSTSIZE) bit posisions. - * @{ - */ -#define XUSBPS_BURSTSIZE_RX_MASK 0x000000FF /**< RX Burst Length */ -#define XUSBPS_BURSTSIZE_TX_MASK 0x0000FF00 /**< TX Burst Length */ -/* @} */ - - -/** @name USB Tx Fill Tuning Register (TXFILL) bit positions. - * @{ - */ -#define XUSBPS_TXFILL_OVERHEAD_MASK 0x000000FF - /**< Scheduler Overhead */ -#define XUSBPS_TXFILL_HEALTH_MASK 0x00001F00 - /**< Scheduler Health Cntr */ -#define XUSBPS_TXFILL_BURST_MASK 0x003F0000 - /**< FIFO Burst Threshold */ -/* @} */ - - -/** @name USB ULPI Viewport Register (ULPIVIEW) bit positions. - * @{ - */ -#define XUSBPS_ULPIVIEW_DATWR_MASK 0x000000FF /**< ULPI Data Write */ -#define XUSBPS_ULPIVIEW_DATRD_MASK 0x0000FF00 /**< ULPI Data Read */ -#define XUSBPS_ULPIVIEW_ADDR_MASK 0x00FF0000 /**< ULPI Data Address */ -#define XUSBPS_ULPIVIEW_PORT_MASK 0x07000000 /**< ULPI Port Number */ -#define XUSBPS_ULPIVIEW_SS_MASK 0x08000000 /**< ULPI Synchronous State */ -#define XUSBPS_ULPIVIEW_RW_MASK 0x20000000 /**< ULPI Read/Write Control */ -#define XUSBPS_ULPIVIEW_RUN_MASK 0x40000000 /**< ULPI Run */ -#define XUSBPS_ULPIVIEW_WU_MASK 0x80000000 /**< ULPI Wakeup */ -/* @} */ - - -/** @name Port Status Control Register bit positions. - * @{ - */ -#define XUSBPS_PORTSCR_CCS_MASK 0x00000001 /**< Current Connect Status */ -#define XUSBPS_PORTSCR_CSC_MASK 0x00000002 /**< Connect Status Change */ -#define XUSBPS_PORTSCR_PE_MASK 0x00000004 /**< Port Enable/Disable */ -#define XUSBPS_PORTSCR_PEC_MASK 0x00000008 /**< Port Enable/Disable Change */ -#define XUSBPS_PORTSCR_OCA_MASK 0x00000010 /**< Over-current Active */ -#define XUSBPS_PORTSCR_OCC_MASK 0x00000020 /**< Over-current Change */ -#define XUSBPS_PORTSCR_FPR_MASK 0x00000040 /**< Force Port Resume */ -#define XUSBPS_PORTSCR_SUSP_MASK 0x00000080 /**< Suspend */ -#define XUSBPS_PORTSCR_PR_MASK 0x00000100 /**< Port Reset */ -#define XUSBPS_PORTSCR_HSP_MASK 0x00000200 /**< High Speed Port */ -#define XUSBPS_PORTSCR_LS_MASK 0x00000C00 /**< Line Status */ -#define XUSBPS_PORTSCR_PP_MASK 0x00001000 /**< Port Power */ -#define XUSBPS_PORTSCR_PO_MASK 0x00002000 /**< Port Owner */ -#define XUSBPS_PORTSCR_PIC_MASK 0x0000C000 /**< Port Indicator Control */ -#define XUSBPS_PORTSCR_PTC_MASK 0x000F0000 /**< Port Test Control */ -#define XUSBPS_PORTSCR_WKCN_MASK 0x00100000 /**< Wake on Connect Enable */ -#define XUSBPS_PORTSCR_WKDS_MASK 0x00200000 /**< Wake on Disconnect Enable */ -#define XUSBPS_PORTSCR_WKOC_MASK 0x00400000 /**< Wake on Over-current Enable */ -#define XUSBPS_PORTSCR_PHCD_MASK 0x00800000 /**< PHY Low Power Suspend - - * Clock Disable */ -#define XUSBPS_PORTSCR_PFSC_MASK 0x01000000 /**< Port Force Full Speed - * Connect */ -#define XUSBPS_PORTSCR_PSPD_MASK 0x0C000000 /**< Port Speed */ -/* @} */ - - -/** @name On-The-Go Status Control Register (OTGCSR) bit positions. - * @{ - */ -#define XUSBPS_OTGSC_VD_MASK 0x00000001 /**< VBus Discharge Bit */ -#define XUSBPS_OTGSC_VC_MASK 0x00000002 /**< VBus Charge Bit */ -#define XUSBPS_OTGSC_HAAR_MASK 0x00000004 /**< HW Assist Auto Reset - * Enable Bit */ -#define XUSBPS_OTGSC_OT_MASK 0x00000008 /**< OTG Termination Bit */ -#define XUSBPS_OTGSC_DP_MASK 0x00000010 /**< Data Pulsing Pull-up - * Enable Bit */ -#define XUSBPS_OTGSC_IDPU_MASK 0x00000020 /**< ID Pull-up Enable Bit */ -#define XUSBPS_OTGSC_HADP_MASK 0x00000040 /**< HW Assist Data Pulse - * Enable Bit */ -#define XUSBPS_OTGSC_HABA_MASK 0x00000080 /**< USB Hardware Assist - * B Disconnect to A - * Connect Enable Bit */ -#define XUSBPS_OTGSC_ID_MASK 0x00000100 /**< ID Status Flag */ -#define XUSBPS_OTGSC_AVV_MASK 0x00000200 /**< USB A VBus Valid Interrupt Status Flag */ -#define XUSBPS_OTGSC_ASV_MASK 0x00000400 /**< USB A Session Valid Interrupt Status Flag */ -#define XUSBPS_OTGSC_BSV_MASK 0x00000800 /**< USB B Session Valid Status Flag */ -#define XUSBPS_OTGSC_BSE_MASK 0x00001000 /**< USB B Session End Status Flag */ -#define XUSBPS_OTGSC_1MST_MASK 0x00002000 /**< USB 1 Millisecond Timer Status Flag */ -#define XUSBPS_OTGSC_DPS_MASK 0x00004000 /**< Data Pulse Status Flag */ -#define XUSBPS_OTGSC_IDIS_MASK 0x00010000 /**< USB ID Interrupt Status Flag */ -#define XUSBPS_OTGSC_AVVIS_MASK 0x00020000 /**< USB A VBus Valid Interrupt Status Flag */ -#define XUSBPS_OTGSC_ASVIS_MASK 0x00040000 /**< USB A Session Valid Interrupt Status Flag */ -#define XUSBPS_OTGSC_BSVIS_MASK 0x00080000 /**< USB B Session Valid Interrupt Status Flag */ -#define XUSBPS_OTGSC_BSEIS_MASK 0x00100000 /**< USB B Session End Interrupt Status Flag */ -#define XUSBPS_OTGSC_1MSS_MASK 0x00200000 /**< 1 Millisecond Timer Interrupt Status Flag */ -#define XUSBPS_OTGSC_DPIS_MASK 0x00400000 /**< Data Pulse Interrupt Status Flag */ -#define XUSBPS_OTGSC_IDIE_MASK 0x01000000 /**< ID Interrupt Enable Bit */ -#define XUSBPS_OTGSC_AVVIE_MASK 0x02000000 /**< USB A VBus Valid Interrupt Enable Bit */ -#define XUSBPS_OTGSC_ASVIE_MASK 0x04000000 /**< USB A Session Valid Interrupt Enable Bit */ -#define XUSBPS_OTGSC_BSVIE_MASK 0x08000000 /**< USB B Session Valid Interrupt Enable Bit */ -#define XUSBPS_OTGSC_BSEE_MASK 0x10000000 /**< USB B Session End Interrupt Enable Bit */ -#define XUSBPS_OTGSC_1MSE_MASK 0x20000000 /**< 1 Millisecond Timer - * Interrupt Enable Bit */ -#define XUSBPS_OTGSC_DPIE_MASK 0x40000000 /**< Data Pulse Interrupt - * Enable Bit */ - -#define XUSBPS_OTG_ISB_ALL (XUSBPS_OTGSC_IDIS_MASK |\ - XUSBPS_OTGSC_AVVIS_MASK | \ - XUSBPS_OTGSC_ASVIS_MASK | \ - XUSBPS_OTGSC_BSVIS_MASK | \ - XUSBPS_OTGSC_BSEIS_MASK | \ - XUSBPS_OTGSC_1MSS_MASK | \ - XUSBPS_OTGSC_DPIS_MASK) - /** Mask for All IRQ status masks */ - -#define XUSBPS_OTG_IEB_ALL (XUSBPS_OTGSC_IDIE_MASK |\ - XUSBPS_OTGSC_AVVIE_MASK | \ - XUSBPS_OTGSC_ASVIE_MASK | \ - XUSBPS_OTGSC_BSVIE_MASK | \ - XUSBPS_OTGSC_BSEE_IEB_MASK | \ - XUSBPS_OTGSC_1MSE_MASK | \ - XUSBPS_OTGSC_DPIE_MASK) - /** Mask for All IRQ Enable masks */ -/* @} */ - - -/**< Alignment of the Device Queue Head List BASE. */ -#define XUSBPS_dQH_BASE_ALIGN 2048 - -/**< Alignment of a Device Queue Head structure. */ -#define XUSBPS_dQH_ALIGN 64 - -/**< Alignment of a Device Transfer Descriptor structure. */ -#define XUSBPS_dTD_ALIGN 32 - -/**< Size of one RX buffer for a OUT Transfer Descriptor. */ -#define XUSBPS_dTD_BUF_SIZE 4096 - -/**< Maximum size of one RX/TX buffer. */ -#define XUSBPS_dTD_BUF_MAX_SIZE 16*1024 - -/**< Alignment requirement for Transfer Descriptor buffers. */ -#define XUSBPS_dTD_BUF_ALIGN 4096 - - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/****************************************************************************/ -/** -* -* This macro reads the given register. -* -* @param BaseAddress is the base address for the USB registers. -* @param RegOffset is the register offset to be read. -* -* @return The 32-bit value of the register. -* -* @note C-style signature: -* u32 XUsbPs_ReadReg(u32 BaseAddress, u32 RegOffset) -* -*****************************************************************************/ -#define XUsbPs_ReadReg(BaseAddress, RegOffset) \ - Xil_In32(BaseAddress + (RegOffset)) - - -/****************************************************************************/ -/** -* -* This macro writes the given register. -* -* @param BaseAddress is the the base address for the USB registers. -* @param RegOffset is the register offset to be written. -* @param Data is the the 32-bit value to write to the register. -* -* @return None. -* -* @note C-style signature: -* void XUsbPs_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) -* - *****************************************************************************/ -#define XUsbPs_WriteReg(BaseAddress, RegOffset, Data) \ - Xil_Out32(BaseAddress + (RegOffset), (Data)) - - -/************************** Function Prototypes ******************************/ -/* - * Perform reset operation to the USB PS interface - */ -void XUsbPs_ResetHw(u32 BaseAddress); -/************************** Variable Definitions ******************************/ - -#ifdef __cplusplus -} -#endif - -#endif /* XUSBPS_L_H */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xutil.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xutil.h deleted file mode 100644 index 39469fef78bf01fda56bc6de7cb446bbaed0996e..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xutil.h +++ /dev/null @@ -1,154 +0,0 @@ -/* $Id: xutil.h,v 1.8 2007/05/04 21:55:59 wre Exp $ */ -/****************************************************************************** -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND -* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, -* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION -* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE. -* -* (c) Copyright 2002 Xilinx Inc. -* All rights reserved. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xutil.h -* -* This file contains utility functions such as memory test functions. -* -* <b>Memory test description</b> -* -* A subset of the memory tests can be selected or all of the tests can be run -* in order. If there is an error detected by a subtest, the test stops and the -* failure code is returned. Further tests are not run even if all of the tests -* are selected. -* -* Subtest descriptions: -* <pre> -* XUT_ALLMEMTESTS: -* Runs all of the following tests -* -* XUT_INCREMENT: -* Incrementing Value Test. -* This test starts at 'XUT_MEMTEST_INIT_VALUE' and uses the incrementing -* value as the test value for memory. -* -* XUT_WALKONES: -* Walking Ones Test. -* This test uses a walking '1' as the test value for memory. -* location 1 = 0x00000001 -* location 2 = 0x00000002 -* ... -* -* XUT_WALKZEROS: -* Walking Zero's Test. -* This test uses the inverse value of the walking ones test -* as the test value for memory. -* location 1 = 0xFFFFFFFE -* location 2 = 0xFFFFFFFD -* ... -* -* XUT_INVERSEADDR: -* Inverse Address Test. -* This test uses the inverse of the address of the location under test -* as the test value for memory. -* -* XUT_FIXEDPATTERN: -* Fixed Pattern Test. -* This test uses the provided patters as the test value for memory. -* If zero is provided as the pattern the test uses '0xDEADBEEF". -* </pre> -* -* <i>WARNING</i> -* -* The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces -* have been set up. -* -* The address, Addr, provided to the memory tests is not checked for -* validity except for the NULL case. It is possible to provide a code-space -* pointer for this test to start with and ultimately destroy executable code -* causing random failures. -* -* @note -* -* Used for spaces where the address range of the region is smaller than -* the data width. If the memory range is greater than 2 ** width, -* the patterns used in XUT_WALKONES and XUT_WALKZEROS will repeat on a -* boundry of a power of two making it more difficult to detect addressing -* errors. The XUT_INCREMENT and XUT_INVERSEADDR tests suffer the same -* problem. Ideally, if large blocks of memory are to be tested, break -* them up into smaller regions of memory to allow the test patterns used -* not to repeat over the region tested. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a ecm 11/01/01 First release -* 1.00a xd 11/03/04 Improved support for doxygen. -* </pre> -* -******************************************************************************/ - -#ifndef XUTIL_H /* prevent circular inclusions */ -#define XUTIL_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ -#include "xbasic_types.h" -#include "xstatus.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - -/* xutil_memtest defines */ - -#define XUT_MEMTEST_INIT_VALUE 1 - -/** @name Memory subtests - * @{ - */ -/** - * See the detailed description of the subtests in the file description. - */ -#define XUT_ALLMEMTESTS 0 -#define XUT_INCREMENT 1 -#define XUT_WALKONES 2 -#define XUT_WALKZEROS 3 -#define XUT_INVERSEADDR 4 -#define XUT_FIXEDPATTERN 5 -#define XUT_MAXTEST XUT_FIXEDPATTERN -/* @} */ - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - -/* xutil_memtest prototypes */ - -int XUtil_MemoryTest32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest); -int XUtil_MemoryTest16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest); -int XUtil_MemoryTest8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/include/xversion.h b/quad/sw/system_bsp/ps7_cortexa9_0/include/xversion.h deleted file mode 100644 index 3a14716f095b879611076aabadc06cba0892424c..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/include/xversion.h +++ /dev/null @@ -1,98 +0,0 @@ -/* $Id: xversion.h,v 1.9 2007/05/07 14:29:23 wre Exp $ */ -/****************************************************************************** -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND -* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, -* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION -* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE. -* -* (c) Copyright 2002 Xilinx Inc. -* All rights reserved. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* @file xversion.h -* -* This file contains the interface for the XVersion component. This -* component represents a version ID. It is encapsulated within a component -* so that it's type and implementation can change without affecting users of -* it. -* -* The version is formatted as X.YYZ where X = 0 - 9, Y = 00 - 99, Z = a - z -* X is the major revision, YY is the minor revision, and Z is the -* compatability revision. -* -* Packed versions are also utilized for the configuration ROM such that -* memory is minimized. A packed version consumes only 16 bits and is -* formatted as follows. -* -* <pre> -* Revision Range Bit Positions -* -* Major Revision 0 - 9 Bits 15 - 12 -* Minor Revision 0 - 99 Bits 11 - 5 -* Compatability Revision a - z Bits 4 - 0 -* -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.00a xd 11/03/04 Improved support for doxygen. -* </pre> -* -******************************************************************************/ - -#ifndef XVERSION_H /* prevent circular inclusions */ -#define XVERSION_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xbasic_types.h" -#include "xstatus.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - -/* the following data type is used to hold a null terminated version string - * consisting of the following format, "X.YYX" - */ -typedef char XVersion[6]; - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - -void XVersion_UnPack(XVersion *InstancePtr, u16 PackedVersion); - -int XVersion_Pack(XVersion *InstancePtr, u16 *PackedVersion); - -int XVersion_IsEqual(XVersion *InstancePtr, XVersion *VersionPtr); - -void XVersion_ToString(XVersion *InstancePtr, char *StringPtr); - -int XVersion_FromString(XVersion *InstancePtr, char *StringPtr); - -void XVersion_Copy(XVersion *InstancePtr, XVersion *VersionPtr); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/lib/libxil.a b/quad/sw/system_bsp/ps7_cortexa9_0/lib/libxil.a deleted file mode 100644 index 51e32c2b08a6aeb9e14d75a0f57f1dc15806080e..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/lib/libxil.a and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/Makefile b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/Makefile deleted file mode 100644 index 8279525091996a6ede84493b83c100e52cb383a7..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -COMPILER= -ARCHIVER= -CP=cp -COMPILER_FLAGS= -EXTRA_COMPILER_FLAGS= -LIB=libxil.a - -RELEASEDIR=../../../lib -INCLUDEDIR=../../../include -INCLUDES=-I${INCLUDEDIR} - -OUTS = *.o - -LIBSOURCES=*.c -INCLUDEFILES=xbasic_types.h xenv.h xenv_none.h xenv_standalone.h xenv_vxworks.h xstatus.h xutil.h xversion.h xdebug.h - -libs: - echo "Compiling common" - $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) - $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} - make clean - -include: - ${CP} $(INCLUDEFILES) $(INCLUDEDIR) - -clean: - rm -rf $(OUTS) - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xbasic_types.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xbasic_types.c deleted file mode 100644 index c3e718330023ca4efc4e5ab387cb696405a9af14..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xbasic_types.c +++ /dev/null @@ -1,137 +0,0 @@ -/* $Id $ */ -/****************************************************************************** -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND -* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, -* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION -* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE. -* -* (c) Copyright 2002-2012 Xilinx Inc. -* All rights reserved. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xbasic_types.c -* -* This file contains basic functions for Xilinx software IP. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.00a rpm 11/07/03 Added XNullHandler function as a stub interrupt handler -* 1.00a xd 11/03/04 Improved support for doxygen. -* 1.00a bss 13/01/12 Removed a compiler warning in XNullHandler; -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xbasic_types.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Variable Definitions *****************************/ - -/** - * This variable allows testing to be done easier with asserts. An assert - * sets this variable such that a driver can evaluate this variable - * to determine if an assert occurred. - */ -unsigned int XAssertStatus; - -/** - * This variable allows the assert functionality to be changed for testing - * such that it does not wait infinitely. Use the debugger to disable the - * waiting during testing of asserts. - */ -int XWaitInAssert = TRUE; - -/* The callback function to be invoked when an assert is taken */ -static XAssertCallback XAssertCallbackRoutine = (XAssertCallback) NULL; - -/************************** Function Prototypes ******************************/ - -/*****************************************************************************/ -/** -* -* Implements assert. Currently, it calls a user-defined callback function -* if one has been set. Then, it potentially enters an infinite loop depending -* on the value of the XWaitInAssert variable. -* -* @param File is the name of the filename of the source -* @param Line is the linenumber within File -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XAssert(char *File, int Line) -{ - /* if the callback has been set then invoke it */ - if (XAssertCallbackRoutine != NULL) { - (*XAssertCallbackRoutine) (File, Line); - } - - /* if specified, wait indefinitely such that the assert will show up - * in testing - */ - while (XWaitInAssert) { - } -} - -/*****************************************************************************/ -/** -* -* Sets up a callback function to be invoked when an assert occurs. If there -* was already a callback installed, then it is replaced. -* -* @param Routine is the callback to be invoked when an assert is taken -* -* @return None. -* -* @note This function has no effect if NDEBUG is set -* -******************************************************************************/ -void XAssertSetCallback(XAssertCallback Routine) -{ - XAssertCallbackRoutine = Routine; -} - - -/*****************************************************************************/ -/** -* -* Null handler function. This follows the XInterruptHandler signature for -* interrupt handlers. It can be used to assign a null handler (a stub) to an -* interrupt controller vector table. -* -* @param NullParameter is an arbitrary void pointer and not used. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XNullHandler(void *NullParameter) -{ - (void) NullParameter; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xbasic_types.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xbasic_types.h deleted file mode 100644 index d5db3f7b04c17220dc4199eafcecd53ed5d8fb66..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xbasic_types.h +++ /dev/null @@ -1,300 +0,0 @@ -/* $Id: xbasic_types.h,v 1.19.10.4 2011/06/28 11:00:54 sadanan Exp $ */ -/****************************************************************************** -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND -* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, -* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION -* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE. -* -* (c) Copyright 2002-2007 Xilinx Inc. -* All rights reserved. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xbasic_types.h -* -* This file contains basic types for Xilinx software IP. These types do not -* follow the standard naming convention with respect to using the component -* name in front of each name because they are considered to be primitives. -* -* @note -* -* This file contains items which are architecture dependent. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.00a rmm 12/14/01 First release -* rmm 05/09/03 Added "xassert always" macros to rid ourselves of diab -* compiler warnings -* 1.00a rpm 11/07/03 Added XNullHandler function as a stub interrupt handler -* 1.00a rpm 07/21/04 Added XExceptionHandler typedef for processor exceptions -* 1.00a xd 11/03/04 Improved support for doxygen. -* 1.00a wre 01/25/07 Added Linux style data types u32, u16, u8, TRUE, FALSE -* 1.00a rpm 04/02/07 Added ifndef KERNEL around u32, u16, u8 data types -* </pre> -* -******************************************************************************/ - -#ifndef XBASIC_TYPES_H /* prevent circular inclusions */ -#define XBASIC_TYPES_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - - -/***************************** Include Files *********************************/ - - -/************************** Constant Definitions *****************************/ - -#ifndef TRUE -# define TRUE 1 -#endif - -#ifndef FALSE -# define FALSE 0 -#endif - -#ifndef NULL -#define NULL 0 -#endif - -/** Xilinx NULL, TRUE and FALSE legacy support. Deprecated. */ -#define XNULL NULL -#define XTRUE TRUE -#define XFALSE FALSE - - -#define XCOMPONENT_IS_READY 0x11111111 /**< component has been initialized */ -#define XCOMPONENT_IS_STARTED 0x22222222 /**< component has been started */ - -/* the following constants and declarations are for unit test purposes and are - * designed to be used in test applications. - */ -#define XTEST_PASSED 0 -#define XTEST_FAILED 1 - -#define XASSERT_NONE 0 -#define XASSERT_OCCURRED 1 - -extern unsigned int XAssertStatus; -extern void XAssert(char *, int); - -/**************************** Type Definitions *******************************/ - -/** @name Legacy types - * Deprecated legacy types. - * @{ - */ -typedef unsigned char Xuint8; /**< unsigned 8-bit */ -typedef char Xint8; /**< signed 8-bit */ -typedef unsigned short Xuint16; /**< unsigned 16-bit */ -typedef short Xint16; /**< signed 16-bit */ -typedef unsigned long Xuint32; /**< unsigned 32-bit */ -typedef long Xint32; /**< signed 32-bit */ -typedef float Xfloat32; /**< 32-bit floating point */ -typedef double Xfloat64; /**< 64-bit double precision FP */ -typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */ - -#if !defined __XUINT64__ -typedef struct -{ - Xuint32 Upper; - Xuint32 Lower; -} Xuint64; -#endif - -/** @name New types - * New simple types. - * @{ - */ -#ifndef __KERNEL__ -#ifndef XIL_TYPES_H -typedef Xuint32 u32; -typedef Xuint16 u16; -typedef Xuint8 u8; -#endif -#else -#include <linux/types.h> -#endif - -/*@}*/ - -/** - * This data type defines an interrupt handler for a device. - * The argument points to the instance of the component - */ -typedef void (*XInterruptHandler) (void *InstancePtr); - -/** - * This data type defines an exception handler for a processor. - * The argument points to the instance of the component - */ -typedef void (*XExceptionHandler) (void *InstancePtr); - -/** - * This data type defines a callback to be invoked when an - * assert occurs. The callback is invoked only when asserts are enabled - */ -typedef void (*XAssertCallback) (char *FilenamePtr, int LineNumber); - -/***************** Macros (Inline Functions) Definitions *********************/ - -/*****************************************************************************/ -/** -* Return the most significant half of the 64 bit data type. -* -* @param x is the 64 bit word. -* -* @return The upper 32 bits of the 64 bit word. -* -* @note None. -* -******************************************************************************/ -#define XUINT64_MSW(x) ((x).Upper) - -/*****************************************************************************/ -/** -* Return the least significant half of the 64 bit data type. -* -* @param x is the 64 bit word. -* -* @return The lower 32 bits of the 64 bit word. -* -* @note None. -* -******************************************************************************/ -#define XUINT64_LSW(x) ((x).Lower) - - -#ifndef NDEBUG - -/*****************************************************************************/ -/** -* This assert macro is to be used for functions that do not return anything -* (void). This in conjunction with the XWaitInAssert boolean can be used to -* accomodate tests so that asserts which fail allow execution to continue. -* -* @param expression is the expression to evaluate. If it evaluates to -* false, the assert occurs. -* -* @return Returns void unless the XWaitInAssert variable is true, in which -* case no return is made and an infinite loop is entered. -* -* @note None. -* -******************************************************************************/ -#define XASSERT_VOID(expression) \ -{ \ - if (expression) \ - { \ - XAssertStatus = XASSERT_NONE; \ - } \ - else \ - { \ - XAssert(__FILE__, __LINE__); \ - XAssertStatus = XASSERT_OCCURRED; \ - return; \ - } \ -} - -/*****************************************************************************/ -/** -* This assert macro is to be used for functions that do return a value. This in -* conjunction with the XWaitInAssert boolean can be used to accomodate tests so -* that asserts which fail allow execution to continue. -* -* @param expression is the expression to evaluate. If it evaluates to false, -* the assert occurs. -* -* @return Returns 0 unless the XWaitInAssert variable is true, in which case -* no return is made and an infinite loop is entered. -* -* @note None. -* -******************************************************************************/ -#define XASSERT_NONVOID(expression) \ -{ \ - if (expression) \ - { \ - XAssertStatus = XASSERT_NONE; \ - } \ - else \ - { \ - XAssert(__FILE__, __LINE__); \ - XAssertStatus = XASSERT_OCCURRED; \ - return 0; \ - } \ -} - -/*****************************************************************************/ -/** -* Always assert. This assert macro is to be used for functions that do not -* return anything (void). Use for instances where an assert should always -* occur. -* -* @return Returns void unless the XWaitInAssert variable is true, in which case -* no return is made and an infinite loop is entered. -* -* @note None. -* -******************************************************************************/ -#define XASSERT_VOID_ALWAYS() \ -{ \ - XAssert(__FILE__, __LINE__); \ - XAssertStatus = XASSERT_OCCURRED; \ - return; \ -} - -/*****************************************************************************/ -/** -* Always assert. This assert macro is to be used for functions that do return -* a value. Use for instances where an assert should always occur. -* -* @return Returns void unless the XWaitInAssert variable is true, in which case -* no return is made and an infinite loop is entered. -* -* @note None. -* -******************************************************************************/ -#define XASSERT_NONVOID_ALWAYS() \ -{ \ - XAssert(__FILE__, __LINE__); \ - XAssertStatus = XASSERT_OCCURRED; \ - return 0; \ -} - - -#else - -#define XASSERT_VOID(expression) -#define XASSERT_VOID_ALWAYS() -#define XASSERT_NONVOID(expression) -#define XASSERT_NONVOID_ALWAYS() -#endif - -/************************** Function Prototypes ******************************/ - -void XAssertSetCallback(XAssertCallback Routine); -void XNullHandler(void *NullParameter); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xdebug.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xdebug.h deleted file mode 100644 index 8ab5e212c629109f827084c8a7202a41af4cb453..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xdebug.h +++ /dev/null @@ -1,61 +0,0 @@ -#ifndef XDEBUG -#define XDEBUG - -#undef DEBUG - -#if defined(DEBUG) && !defined(NDEBUG) - -#ifndef XDEBUG_WARNING -#define XDEBUG_WARNING -#warning DEBUG is enabled -#endif - -int printf(const char *format, ...); - -#define XDBG_DEBUG_ERROR 0x00000001 /* error condition messages */ -#define XDBG_DEBUG_GENERAL 0x00000002 /* general debug messages */ -#define XDBG_DEBUG_ALL 0xFFFFFFFF /* all debugging data */ - -#define XDBG_DEBUG_FIFO_REG 0x00000100 /* display register reads/writes */ -#define XDBG_DEBUG_FIFO_RX 0x00000101 /* receive debug messages */ -#define XDBG_DEBUG_FIFO_TX 0x00000102 /* transmit debug messages */ -#define XDBG_DEBUG_FIFO_ALL 0x0000010F /* all fifo debug messages */ - -#define XDBG_DEBUG_TEMAC_REG 0x00000400 /* display register reads/writes */ -#define XDBG_DEBUG_TEMAC_RX 0x00000401 /* receive debug messages */ -#define XDBG_DEBUG_TEMAC_TX 0x00000402 /* transmit debug messages */ -#define XDBG_DEBUG_TEMAC_ALL 0x0000040F /* all temac debug messages */ - -#define XDBG_DEBUG_TEMAC_ADPT_RX 0x00000800 /* receive debug messages */ -#define XDBG_DEBUG_TEMAC_ADPT_TX 0x00000801 /* transmit debug messages */ -#define XDBG_DEBUG_TEMAC_ADPT_IOCTL 0x00000802 /* ioctl debug messages */ -#define XDBG_DEBUG_TEMAC_ADPT_MISC 0x00000803 /* debug msg for other routines */ -#define XDBG_DEBUG_TEMAC_ADPT_ALL 0x0000080F /* all temac adapter debug messages */ - -#define xdbg_current_types (XDBG_DEBUG_ERROR) - -#define xdbg_stmnt(x) x - -/* In VxWorks, if _WRS_GNU_VAR_MACROS is defined, special syntax is needed for - * macros that accept variable number of arguments - */ -#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS) -#define xdbg_printf(type, args...) (((type) & xdbg_current_types) ? printf (## args) : 0) -#else /* ANSI Syntax */ -#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0) -#endif - -#else /* defined(DEBUG) && !defined(NDEBUG) */ - -#define xdbg_stmnt(x) - -/* See VxWorks comments above */ -#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS) -#define xdbg_printf(type, args...) -#else /* ANSI Syntax */ -#define xdbg_printf(...) -#endif - -#endif /* defined(DEBUG) && !defined(NDEBUG) */ - -#endif /* XDEBUG */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xenv.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xenv.h deleted file mode 100644 index 27cb76810b26ae9a6c249c9fd3eef028f6cf540b..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xenv.h +++ /dev/null @@ -1,177 +0,0 @@ -/****************************************************************************** -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND -* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, -* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION -* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE. -* -* (c) Copyright 2002 Xilinx Inc. -* All rights reserved. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xenv.h -* -* Defines common services that are typically found in a host operating. -* environment. This include file simply includes an OS specific file based -* on the compile-time constant BUILD_ENV_*, where * is the name of the target -* environment. -* -* All services are defined as macros. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00b ch 10/24/02 Added XENV_LINUX -* 1.00a rmm 04/17/02 First release -* </pre> -* -******************************************************************************/ - -#ifndef XENV_H /* prevent circular inclusions */ -#define XENV_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Select which target environment we are operating under - */ - -/* VxWorks target environment */ -#if defined XENV_VXWORKS -#include "xenv_vxworks.h" - -/* Linux target environment */ -#elif defined XENV_LINUX -#include "xenv_linux.h" - -/* Unit test environment */ -#elif defined XENV_UNITTEST -#include "ut_xenv.h" - -/* Integration test environment */ -#elif defined XENV_INTTEST -#include "int_xenv.h" - -/* Standalone environment selected */ -#else -#include "xenv_standalone.h" -#endif - - -/* - * The following comments specify the types and macro wrappers that are - * expected to be defined by the target specific header files - */ - -/**************************** Type Definitions *******************************/ - -/*****************************************************************************/ -/** - * - * XENV_TIME_STAMP - * - * A structure that contains a time stamp used by other time stamp macros - * defined below. This structure is processor dependent. - */ - - -/***************** Macros (Inline Functions) Definitions *********************/ - -/*****************************************************************************/ -/** - * - * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes) - * - * Copies a non-overlapping block of memory. - * - * @param DestPtr is the destination address to copy data to. - * @param SrcPtr is the source address to copy data from. - * @param Bytes is the number of bytes to copy. - * - * @return None - */ - -/*****************************************************************************/ -/** - * - * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes) - * - * Fills an area of memory with constant data. - * - * @param DestPtr is the destination address to set. - * @param Data contains the value to set. - * @param Bytes is the number of bytes to set. - * - * @return None - */ -/*****************************************************************************/ -/** - * - * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr) - * - * Samples the processor's or external timer's time base counter. - * - * @param StampPtr is the storage for the retrieved time stamp. - * - * @return None - */ - -/*****************************************************************************/ -/** - * - * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr) - * - * Computes the delta between the two time stamps. - * - * @param Stamp1Ptr - First sampled time stamp. - * @param Stamp1Ptr - Sedond sampled time stamp. - * - * @return An unsigned int value with units of microseconds. - */ - -/*****************************************************************************/ -/** - * - * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr) - * - * Computes the delta between the two time stamps. - * - * @param Stamp1Ptr - First sampled time stamp. - * @param Stamp1Ptr - Sedond sampled time stamp. - * - * @return An unsigned int value with units of milliseconds. - */ - -/*****************************************************************************//** - * - * XENV_USLEEP(unsigned delay) - * - * Delay the specified number of microseconds. - * - * @param delay is the number of microseconds to delay. - * - * @return None - */ - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xenv_linux.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xenv_linux.h deleted file mode 100644 index 8a69b662d36dc62b43d2b982b5a1849bf9a28e5d..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xenv_linux.h +++ /dev/null @@ -1,241 +0,0 @@ -/****************************************************************************** -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND -* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, -* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION -* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE. -* -* (c) Copyright 2002-2007 Xilinx Inc. -* All rights reserved. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xenv_linux.h -* -* Defines common services specified by xenv.h. -* -* @note -* This file is not intended to be included directly by driver code. -* Instead, the generic xenv.h file is intended to be included by driver -* code. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a wgr 02/28/07 Added cache handling macros. -* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names. -* 1.00a xd 11/03/04 Improved support for doxygen. -* 1.00a ch 10/24/02 First release -* 1.10a wgr 03/22/07 Converted to new coding style. -* </pre> -* -* -******************************************************************************/ - -#ifndef XENV_LINUX_H -#define XENV_LINUX_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/***************************** Include Files *********************************/ - -#include <asm/cache.h> -#include <asm/cacheflush.h> -#include <linux/string.h> -#include <linux/delay.h> - - -/****************************************************************************** - * - * MEMCPY / MEMSET related macros. - * - * Those macros are defined to catch legacy code in Xilinx drivers. The - * XENV_MEM_COPY and XENV_MEM_FILL macros were used in early Xilinx driver - * code. They are being replaced by memcpy() and memset() function calls. These - * macros are defined to catch any remaining occurences of those macros. - * - ******************************************************************************/ - -/*****************************************************************************/ -/** - * - * Copies a non-overlapping block of memory. - * - * @param DestPtr - * Destination address to copy data to. - * - * @param SrcPtr - * Source address to copy data from. - * - * @param Bytes - * Number of bytes to copy. - * - * @return None. - * - *****************************************************************************/ - -#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \ - memcpy(DestPtr, SrcPtr, Bytes) -/* do_not_use_XENV_MEM_COPY_use_memcpy_instead */ - - -/*****************************************************************************/ -/** - * - * Fills an area of memory with constant data. - * - * @param DestPtr - * Destination address to copy data to. - * - * @param Data - * Value to set. - * - * @param Bytes - * Number of bytes to copy. - * - * @return None. - * - *****************************************************************************/ - -#define XENV_MEM_FILL(DestPtr, Data, Bytes) \ - memset(DestPtr, Data, Bytes) -/* do_not_use_XENV_MEM_FILL_use_memset_instead */ - - -/****************************************************************************** - * - * TIME related macros - * - ******************************************************************************/ -/** - * A structure that contains a time stamp used by other time stamp macros - * defined below. This structure is processor dependent. - */ -typedef int XENV_TIME_STAMP; - -/*****************************************************************************/ -/** - * - * Time is derived from the 64 bit PPC timebase register - * - * @param StampPtr is the storage for the retrieved time stamp. - * - * @return None. - * - * @note - * - * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr) - * <br><br> - * This macro must be implemented by the user. - * - *****************************************************************************/ -#define XENV_TIME_STAMP_GET(StampPtr) - -/*****************************************************************************/ -/** - * - * This macro is not yet implemented and always returns 0. - * - * @param Stamp1Ptr is the first sampled time stamp. - * @param Stamp2Ptr is the second sampled time stamp. - * - * @return 0 - * - * @note - * - * This macro must be implemented by the user. - * - *****************************************************************************/ -#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0) - -/*****************************************************************************/ -/** - * - * This macro is not yet implemented and always returns 0. - * - * @param Stamp1Ptr is the first sampled time stamp. - * @param Stamp2Ptr is the second sampled time stamp. - * - * @return 0 - * - * @note - * - * This macro must be implemented by the user - * - *****************************************************************************/ -#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0) - -/*****************************************************************************/ -/** - * - * Delay the specified number of microseconds. - * - * @param delay - * Number of microseconds to delay. - * - * @return None. - * - * @note XENV_USLEEP is deprecated. Use udelay() instead. - * - *****************************************************************************/ - -#define XENV_USLEEP(delay) udelay(delay) -/* do_not_use_XENV_MEM_COPY_use_memcpy_instead */ - - -/****************************************************************************** - * - * CACHE handling macros / mappings - * - * The implementation of the cache handling functions can be found in - * arch/microblaze. - * - * These #defines are simple mappings to the Linux API. - * - * The underlying Linux implementation will take care of taking the right - * actions depending on the configuration of the MicroBlaze processor in the - * system. - * - ******************************************************************************/ - -#define XCACHE_ENABLE_DCACHE() __enable_dcache() -#define XCACHE_DISABLE_DCACHE() __disable_dcache() -#define XCACHE_ENABLE_ICACHE() __enable_icache() -#define XCACHE_DISABLE_ICACHE() __disable_icache() - -#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) invalidate_dcache_range((u32)(Addr), ((u32)(Addr)+(Len))) -#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) flush_dcache_range((u32)(Addr), ((u32)(Addr)+(Len))) - -#define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) "XCACHE_INVALIDATE_ICACHE_RANGE unsupported" -#define XCACHE_FLUSH_ICACHE_RANGE(Addr, Len) flush_icache_range(Addr, Len) - -#define XCACHE_ENABLE_CACHE() \ - { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); } - -#define XCACHE_DISABLE_CACHE() \ - { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); } - - - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xenv_none.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xenv_none.h deleted file mode 100644 index bc837860fc6d961bd9beb2bdfd71414cadb9f633..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xenv_none.h +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************** -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND -* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, -* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION -* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE. -* -* (c) Copyright 2002 Xilinx Inc. -* All rights reserved. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xenv_none.h -* -* This is a legacy file kept for backwards compatibility. -* -* Please modify your code to #include "xenv_standalone.h" instead. -* -* -******************************************************************************/ - -#warning ******************************************************************** -#warning * -#warning * Use of xenv_none.h deprecated. -#warning * Please include the new xenv_standalone.h file instead. -#warning * -#warning ******************************************************************** - -#include "xenv_standalone.h" - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xenv_standalone.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xenv_standalone.h deleted file mode 100644 index f2b2b68871f6a4e8466e8a827257e3e57e453d7f..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xenv_standalone.h +++ /dev/null @@ -1,356 +0,0 @@ -/****************************************************************************** -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND -* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, -* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION -* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE. -* -* (c) Copyright 2002-2008 Xilinx Inc. -* All rights reserved. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xenv_standalone.h -* -* Defines common services specified by xenv.h. -* -* @note -* This file is not intended to be included directly by driver code. -* Instead, the generic xenv.h file is intended to be included by driver -* code. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a wgr 02/28/07 Added cache handling macros. -* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names. -* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being -* used under Xilinx standalone BSP. -* 1.00a xd 11/03/04 Improved support for doxygen. -* 1.00a rmm 03/21/02 First release -* 1.00a wgr 03/22/07 Converted to new coding style. -* 1.00a rpm 06/29/07 Added udelay macro for standalone -* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred -* to in MICROBLAZE section -* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality -* -* </pre> -* -* -******************************************************************************/ - -#ifndef XENV_STANDALONE_H -#define XENV_STANDALONE_H - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ -/****************************************************************************** - * - * Get the processor dependent includes - * - ******************************************************************************/ - -#include <string.h> - -#if defined __MICROBLAZE__ -# include "mb_interface.h" -# include "xparameters.h" /* XPAR constants used below in MB section */ - -#elif defined __PPC__ -# include "sleep.h" -# include "xcache_l.h" /* also include xcache_l.h for caching macros */ -#endif - -/****************************************************************************** - * - * MEMCPY / MEMSET related macros. - * - * The following are straight forward implementations of memset and memcpy. - * - * NOTE: memcpy may not work if source and target memory area are overlapping. - * - ******************************************************************************/ -/*****************************************************************************/ -/** - * - * Copies a non-overlapping block of memory. - * - * @param DestPtr - * Destination address to copy data to. - * - * @param SrcPtr - * Source address to copy data from. - * - * @param Bytes - * Number of bytes to copy. - * - * @return None. - * - * @note - * The use of XENV_MEM_COPY is deprecated. Use memcpy() instead. - * - * @note - * This implemention MAY BREAK work if source and target memory - * area are overlapping. - * - *****************************************************************************/ - -#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \ - memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes) - - - -/*****************************************************************************/ -/** - * - * Fills an area of memory with constant data. - * - * @param DestPtr - * Destination address to copy data to. - * - * @param Data - * Value to set. - * - * @param Bytes - * Number of bytes to copy. - * - * @return None. - * - * @note - * The use of XENV_MEM_FILL is deprecated. Use memset() instead. - * - *****************************************************************************/ - -#define XENV_MEM_FILL(DestPtr, Data, Bytes) \ - memset((void *) DestPtr, (int) Data, (size_t) Bytes) - - - -/****************************************************************************** - * - * TIME related macros - * - ******************************************************************************/ - -/** - * A structure that contains a time stamp used by other time stamp macros - * defined below. This structure is processor dependent. - */ -typedef int XENV_TIME_STAMP; - -/*****************************************************************************/ -/** - * - * Time is derived from the 64 bit PPC timebase register - * - * @param StampPtr is the storage for the retrieved time stamp. - * - * @return None. - * - * @note - * - * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr) - * <br><br> - * This macro must be implemented by the user. - * - *****************************************************************************/ -#define XENV_TIME_STAMP_GET(StampPtr) - -/*****************************************************************************/ -/** - * - * This macro is not yet implemented and always returns 0. - * - * @param Stamp1Ptr is the first sampled time stamp. - * @param Stamp2Ptr is the second sampled time stamp. - * - * @return 0 - * - * @note - * - * This macro must be implemented by the user. - * - *****************************************************************************/ -#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0) - -/*****************************************************************************/ -/** - * - * This macro is not yet implemented and always returns 0. - * - * @param Stamp1Ptr is the first sampled time stamp. - * @param Stamp2Ptr is the second sampled time stamp. - * - * @return 0 - * - * @note - * - * This macro must be implemented by the user. - * - *****************************************************************************/ -#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0) - -/*****************************************************************************/ -/** - * XENV_USLEEP(unsigned delay) - * - * Delay the specified number of microseconds. Not implemented without OS - * support. - * - * @param delay - * Number of microseconds to delay. - * - * @return None. - * - *****************************************************************************/ - -#ifdef __PPC__ -#define XENV_USLEEP(delay) usleep(delay) -#define udelay(delay) usleep(delay) -#else -#define XENV_USLEEP(delay) -#define udelay(delay) -#endif - - -/****************************************************************************** - * - * CACHE handling macros / mappings - * - ******************************************************************************/ -/****************************************************************************** - * - * Processor independent macros - * - ******************************************************************************/ - -#define XCACHE_ENABLE_CACHE() \ - { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); } - -#define XCACHE_DISABLE_CACHE() \ - { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); } - - -/****************************************************************************** - * - * MicroBlaze case - * - * NOTE: Currently the following macros will only work on systems that contain - * only ONE MicroBlaze processor. Also, the macros will only be enabled if the - * system is built using a xparameters.h file. - * - ******************************************************************************/ - -#if defined __MICROBLAZE__ - -/* Check if MicroBlaze data cache was built into the core. - */ -#if (XPAR_MICROBLAZE_USE_DCACHE == 1) -# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache() -# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache() -# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache() - -# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \ - microblaze_invalidate_dcache_range((int)(Addr), (int)(Len)) - -#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1) -# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache() -# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ - microblaze_flush_dcache_range((int)(Addr), (int)(Len)) -#else -# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache() -# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ - microblaze_invalidate_dcache_range((int)(Addr), (int)(Len)) -#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/ - -#else -# define XCACHE_ENABLE_DCACHE() -# define XCACHE_DISABLE_DCACHE() -# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) -# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) -#endif /*XPAR_MICROBLAZE_USE_DCACHE*/ - - -/* Check if MicroBlaze instruction cache was built into the core. - */ -#if (XPAR_MICROBLAZE_USE_ICACHE == 1) -# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache() -# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache() - -# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache() - -# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \ - microblaze_invalidate_icache_range((int)(Addr), (int)(Len)) - -#else -# define XCACHE_ENABLE_ICACHE() -# define XCACHE_DISABLE_ICACHE() -#endif /*XPAR_MICROBLAZE_USE_ICACHE*/ - - -/****************************************************************************** - * - * PowerPC case - * - * Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a - * specific memory region (0x80000001). Each bit (0-30) in the regions - * bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB - * range. - * - * regions --> cached address range - * ------------|-------------------------------------------------- - * 0x80000000 | [0, 0x7FFFFFF] - * 0x00000001 | [0xF8000000, 0xFFFFFFFF] - * 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF] - * - ******************************************************************************/ - -#elif defined __PPC__ - -#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001) -#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache() -#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001) -#define XCACHE_DISABLE_ICACHE() XCache_DisableICache() - -#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \ - XCache_InvalidateDCacheRange((unsigned int)(Addr), (unsigned)(Len)) - -#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ - XCache_FlushDCacheRange((unsigned int)(Addr), (unsigned)(Len)) - -#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache() - - -/****************************************************************************** - * - * Unknown processor / architecture - * - ******************************************************************************/ - -#else -/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */ -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* #ifndef XENV_STANDALONE_H */ - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xenv_vxworks.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xenv_vxworks.h deleted file mode 100644 index 4269f10e0af24750fa9feb76048d7e24ce1a95eb..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xenv_vxworks.h +++ /dev/null @@ -1,258 +0,0 @@ -/****************************************************************************** -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND -* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, -* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION -* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE. -* -* (c) Copyright 2002-2007 Xilinx Inc. -* All rights reserved. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xenv_vxworks.h -* -* Defines common services specified by xenv.h. -* -* @note -* This file is not intended to be included directly by driver code. -* Instead, the generic xenv.h file is intended to be included by driver -* code. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a wgr 02/28/07 Added cache handling macros. -* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names. -* 1.00a xd 11/03/04 Improved support for doxygen. -* rmm 09/13/03 CR 177068: Fix compiler warning in XENV_MEM_FILL -* rmm 10/24/02 Added XENV_USLEEP macro -* 1.00a rmm 07/16/01 First release -* 1.10a wgr 03/22/07 Converted to new coding style. -* </pre> -* -* -******************************************************************************/ - -#ifndef XENV_VXWORKS_H -#define XENV_VXWORKS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xbasic_types.h" -#include "vxWorks.h" -#include "vxLib.h" -#include "sysLibExtra.h" -#include "cacheLib.h" -#include <string.h> - -/*****************************************************************************/ -/** - * - * Copies a non-overlapping block of memory. - * - * @param DestPtr - * Destination address to copy data to. - * - * @param SrcPtr - * Source address to copy data from. - * - * @param Bytes - * Number of bytes to copy. - * - * @return None. - * - * @note XENV_MEM_COPY is deprecated. Use memcpy() instead. - * - *****************************************************************************/ - -#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \ - memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes) - - -/*****************************************************************************/ -/** - * - * Fills an area of memory with constant data. - * - * @param DestPtr - * Destination address to copy data to. - * - * @param Data - * Value to set. - * - * @param Bytes - * Number of bytes to copy. - * - * @return None. - * - * @note XENV_MEM_FILL is deprecated. Use memset() instead. - * - *****************************************************************************/ - -#define XENV_MEM_FILL(DestPtr, Data, Bytes) \ - memset((void *) DestPtr, (int) Data, (size_t) Bytes) - - -#if (CPU_FAMILY==PPC) -/** - * A structure that contains a time stamp used by other time stamp macros - * defined below. This structure is processor dependent. - */ -typedef struct -{ - u32 TimeBaseUpper; - u32 TimeBaseLower; -} XENV_TIME_STAMP; - -/*****************************************************************************/ -/** - * - * Time is derived from the 64 bit PPC timebase register - * - * @param StampPtr is the storage for the retrieved time stamp. - * - * @return None. - * - * @note - * - * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr) - * - *****************************************************************************/ -#define XENV_TIME_STAMP_GET(StampPtr) \ -{ \ - vxTimeBaseGet((UINT32*)&(StampPtr)->TimeBaseUpper, \ - (UINT32*)&(StampPtr)->TimeBaseLower); \ -} - -/*****************************************************************************/ -/** - * - * This macro is not yet implemented and always returns 0. - * - * @param Stamp1Ptr is the first sampled time stamp. - * @param Stamp2Ptr is the second sampled time stamp. - * - * @return 0 - * - * @note None. - * - *****************************************************************************/ -#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0) - -/*****************************************************************************/ -/** - * - * This macro is not yet implemented and always returns 0. - * - * @param Stamp1Ptr is the first sampled time stamp. - * @param Stamp2Ptr is the second sampled time stamp. - * - * @return 0 - * - * @note - * - * None. - * - *****************************************************************************/ -#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0) - - -/* For non-PPC systems the above macros are not defined. Generate a error to - * make the developer aware of the problem. - */ -#else -#error "XENV_TIME_STAMP_GET used in a non-PPC system. Aborting." -#endif - - -/*****************************************************************************/ -/** - * - * Delay the specified number of microseconds. - * - * @param delay - * Number of microseconds to delay. - * - * @return None. - * - *****************************************************************************/ - -#define XENV_USLEEP(delay) sysUsDelay(delay) - -#define udelay(delay) sysUsDelay(delay) - - -/****************************************************************************** - * - * CACHE handling macros / mappings - * - ******************************************************************************/ -/****************************************************************************** - * - * PowerPC case - * - ******************************************************************************/ - -#if (CPU_FAMILY==PPC) - -#define XCACHE_ENABLE_CACHE() \ - { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); } - -#define XCACHE_DISABLE_CACHE() \ - { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); } - - -#define XCACHE_ENABLE_DCACHE() cacheEnable(DATA_CACHE) -#define XCACHE_DISABLE_DCACHE() cacheDisable(DATA_CACHE) -#define XCACHE_ENABLE_ICACHE() cacheEnable(INSTRUCTION_CACHE) -#define XCACHE_DISABLE_ICACHE() cacheDisable(INSTRUCTION_CACHE) - - -#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \ - cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len)) - -#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ - cacheFlush(DATA_CACHE, (void *)(Addr), (Len)) - -#define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \ - cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len)) - -#define XCACHE_FLUSH_ICACHE_RANGE(Addr, Len) \ - cacheFlush(INSTRUCTION_CACHE, (void *)(Addr), (Len)) - - -/****************************************************************************** - * - * Unknown processor / architecture - * - ******************************************************************************/ - -#else -#error "Unknown processor / architecture. Must be PPC for VxWorks." -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* #ifdef XENV_VXWORKS_H */ - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xparameters.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xparameters.h deleted file mode 100644 index be21689f0cc2eb2de4be19d151025af3006468e9..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xparameters.h +++ /dev/null @@ -1,738 +0,0 @@ -/* $Id: xparameters.h,v 1.83.2.11 2011/05/18 03:23:57 svemula Exp $ */ -/****************************************************************************** -* -* (c) Copyright 2002-2011 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xparameters.h -* -* This file contains system parameters for the Xilinx device driver environment. -* It is a representation of the system in that it contains the number of each -* device in the system as well as the parameters and memory map for each -* device. The user can view this file to obtain a summary of the devices in -* their system and the device parameters. -* -* This file may be automatically generated by a design tool such as System -* Generator. -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#ifndef XPARAMETERS_H /* prevent circular inclusions */ -#define XPARAMETERS_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/* unifying driver changes - -added XPAR_INTC_0_ACK_BEFORE, XPAR_INTC_1_ACK_BEFORE -changed XPAR_INTC_MAX_ID to XPAR_INTC_MAX_NUM_INTR_INPUTS -deleted XPAR_INTC_0_MAX_ID, XPAR_INTC_1_MAX_ID - -*/ - -/************************** Constant Definitions *****************************/ - -/* - * The following constants are for each device. - * - * An instance must exist for each physical device that exists in the system. - * The device IDs in the following constants are unique between all devices to - * allow device IDs to be searched in the future. - */ - -/***************************************************************************** - * - * System Level defines. These constants are for devices that do not require - * a device driver. Examples of these types of devices include volatile RAM - * devices. - */ -#define XPAR_ZBT_NUM_INSTANCES 1 -#define XPAR_ZBT_0_BASE 0x00000000 -#define XPAR_ZBT_0_SIZE 0x00100000 - -#define XPAR_SRAM_NUM_INSTANCES 1 -#define XPAR_SRAM_0_BASE 0x00100000 -#define XPAR_SRAM_0_SIZE 0x00200000 - -#define XPAR_DDR_NUM_INSTANCES 1 -#define XPAR_DDR_0_BASE 0xF0000000 -#define XPAR_DDR_0_SIZE 0x01000000 - -#define XPAR_CORE_CLOCK_FREQ_HZ 12500000 - -#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ XPAR_CORE_CLOCK_FREQ_HZ - -/***************************************************************************** - * - * Interrupt Controller (Intc) defines. - * DeviceID starts at 0 - */ -#define XPAR_XINTC_NUM_INSTANCES 2 /* Number of instances */ -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 31 /* max # inputs of all */ -#define XPAR_INTC_SINGLE_BASEADDR 0x70800000 /* low level driver base */ -#define XPAR_INTC_SINGLE_DEVICE_ID 0 /* single instance ID */ -#define XPAR_INTC_SINGLE_ACK_BEFORE 0xFFFF00FF /* low level driver */ - -#define XPAR_INTC_0_DEVICE_ID 1 /* Device ID for instance */ -#define XPAR_INTC_0_ACK_BEFORE 0xFFFF00FF /* Ack timing, before/after */ -#define XPAR_INTC_0_BASEADDR 0x70800000 /* Register base address */ - -#define XPAR_INTC_0_UARTLITE_0_VEC_ID 4 /* Interrupt source for vector */ -#define XPAR_INTC_0_WDTTB_0_VEC_ID 5 /* Interrupt source for vector */ -#define XPAR_INTC_0_WD_0_VEC_ID 6 /* Interrupt source for vector */ -#define XPAR_INTC_0_TMRCTR_0_VEC_ID 7 /* Interrupt source for vector */ -#define XPAR_INTC_0_SPI_0_VEC_ID 11 /* Interrupt source for vector */ -#define XPAR_INTC_0_IIC_0_VEC_ID 12 /* Interrupt source for vector */ -#define XPAR_INTC_0_UARTNS550_0_VEC_ID 13 /* Interrupt source for vector */ -#define XPAR_INTC_0_UARTNS550_1_VEC_ID 14 /* Interrupt source for vector */ -#define XPAR_INTC_0_EMAC_0_VEC_ID 15 /* Interrupt source for vector */ - -#define XPAR_INTC_0_AXIDMA_0_S2MM_INTROUT_VEC_ID 16 /* Intr ID for AXIDMA rx */ -#define XPAR_INTC_0_AXIDMA_0_MM2S_INTROUT_VEC_ID 17 /* Intr ID for AXIDMA tx */ - -#define XPAR_INTC_0_AXICDMA_0_VEC_ID 18 /* Intr ID for AXICDMA */ - -#define XPAR_INTC_0_AXIVDMA_0_S2MM_INTROUT_VEC_ID 19 /* AXIVDMA write intr */ -#define XPAR_INTC_0_AXIVDMA_0_MM2S_INTROUT_VEC_ID 20 /* AXIVDMA read intr */ - -#define XPAR_INTC_1_DEVICE_ID 2 /* Device ID for instance */ -#define XPAR_INTC_1_ACK_BEFORE 0xFFFF00FF /* Ack timing, before/after */ -#define XPAR_INTC_1_BASEADDR 0x70800020 /* Register base address */ - -#define XPAR_INTC_1_OPB_TO_PLB_ERR_VEC_ID 0 /* Interrupt source for vector */ -#define XPAR_INTC_1_PLB_TO_OPB_ERR_VEC_ID 1 /* Interrupt source for vector */ - -/***************************************************************************** - * - * AXI DMA defines - */ - -#define XPAR_XAXIDMA_NUM_INSTANCES 1 - -#define XPAR_AXI_DMA_0_DEVICE_ID 0 -#define XPAR_AXI_DMA_0_BASEADDR 0x40000000 -#define XPAR_AXI_DMA_0_HIGHADDR 0x4000007F -#define XPAR_AXI_DMA_0_SG_INCLUDE_STSCNTRL_STRM 1 -#define XPAR_AXI_DMA_0_INCLUDE_MM2S_DRE 1 -#define XPAR_AXI_DMA_0_INCLUDE_S2MM_DRE 1 -#define XPAR_AXI_DMA_0_INCLUDE_MM2S 1 -#define XPAR_AXI_DMA_0_INCLUDE_S2MM 1 -#define XPAR_AXI_DMA_0_M_AXIS_MM2S_DATA_WIDTH 32 -#define XPAR_AXI_DMA_0_S_AXIS_S2MM_DATA_WIDTH 32 - -/***************************************************************************** - * - * AXI Central DMA defines - */ - -#define XPAR_XAXICDMA_NUM_INSTANCES 1 - -#define XPAR_AXI_CDMA_0_DEVICE_ID 0 -#define XPAR_AXI_CDMA_0_BASEADDR 0x40001000 -#define XPAR_AXI_CDMA_0_HIGHADDR 0x4000107F -#define XPAR_AXI_CDMA_0_INCLUDE_DRE 1 -#define XPAR_AXI_CDMA_0_USE_DATAMOVER_LITE 0 -#define XPAR_AXI_CDMA_0_M_AXI_DATA_WIDTH 32 - -/***************************************************************************** - * - * AXI Video DMA defines - */ -#define XPAR_XAXIVDMA_NUM_INSTANCES 1 - -#define XPAR_AXI_VDMA_0_DEVICE_ID 0 -#define XPAR_AXI_VDMA_0_BASEADDR 0x40002000 -#define XPAR_AXI_VDMA_0_NUM_FSTORES 16 -#define XPAR_AXI_VDMA_0_INCLUDE_MM2S 1 -#define XPAR_AXI_VDMA_0_INCLUDE_MM2S_DRE 1 -#define XPAR_AXI_VDMA_0_M_AXIS_MM2S_DATA_WIDTH 32 -#define XPAR_AXI_VDMA_0_INCLUDE_S2MM 1 -#define XPAR_AXI_VDMA_0_INCLUDE_S2MM_DRE 1 -#define XPAR_AXI_VDMA_0_S_AXIS_S2MM_DATA_WIDTH 32 - -/***************************************************************************** - * - * Ethernet 10/100 MAC defines. - * DeviceID starts at 10 - */ -#define XPAR_XEMAC_NUM_INSTANCES 1 /* Number of instances */ - -#define XPAR_EMAC_0_DEVICE_ID 10 /* Device ID for instance */ -#define XPAR_EMAC_0_BASEADDR 0x60000000/* Device base address */ -#define XPAR_EMAC_0_DMA_PRESENT FALSE /* Does device have DMA? */ -#define XPAR_EMAC_0_ERR_COUNT_EXIST TRUE /* Does device have counters? */ -#define XPAR_EMAC_0_MII_EXIST TRUE /* Does device support MII? */ - -/***************************************************************************** - * - * NS16550 UART defines. - * DeviceID starts at 20 - */ -#define XPAR_XUARTNS550_NUM_INSTANCES 1 /* Number of instances */ - -#define XPAR_UARTNS550_0_DEVICE_ID 20 /* Device ID for instance */ -#define XPAR_UARTNS550_0_BASEADDR 0xA0010000 /* IPIF base address */ -#define XPAR_UARTNS550_0_CLOCK_HZ (66000000L)/* 66 MHz clock */ - -#define XPAR_UARTNS550_1_DEVICE_ID 21 /* Device ID for instance */ -#define XPAR_UARTNS550_1_BASEADDR 0xA0000000 /* IPIF base address */ -#define XPAR_UARTNS550_1_CLOCK_HZ (66000000L)/* 66 MHz clock */ - -/***************************************************************************** - * - * UartLite defines. - * DeviceID starts at 30 - */ -#define XPAR_XUARTLITE_NUM_INSTANCES 1 /* Number of instances */ - -#define XPAR_UARTLITE_0_DEVICE_ID 30 /* Device ID for instance */ -#define XPAR_UARTLITE_0_BASEADDR 0xA0020000 /* Device base address */ -#define XPAR_UARTLITE_0_BAUDRATE 19200 /* Baud rate */ -#define XPAR_UARTLITE_0_USE_PARITY FALSE /* Parity generator enabled */ -#define XPAR_UARTLITE_0_ODD_PARITY FALSE /* Type of parity generated */ -#define XPAR_UARTLITE_0_DATA_BITS 8 /* Data bits */ - -/***************************************************************************** - * - * ATM controller defines. - * DeviceID starts at 40 - */ -#define XPAR_XATMC_NUM_INSTANCES 1 /* Number of instances */ - -#define XPAR_ATMC_0_DEVICE_ID 40 /* Device ID for instance */ -#define XPAR_ATMC_0_BASEADDR 0x70000000 /* Device base address */ -#define XPAR_ATMC_0_DMA_PRESENT FALSE /* Does device have DMA? */ - -/***************************************************************************** - * - * Serial Peripheral Interface (SPI) defines. - * DeviceID starts at 50 - */ -#define XPAR_XSPI_NUM_INSTANCES 2 /* Number of instances */ - -#define XPAR_SPI_0_DEVICE_ID 50 /* Device ID for instance */ -#define XPAR_SPI_0_BASEADDR 0x50000000 /* Device base address */ -#define XPAR_SPI_0_FIFO_EXIST TRUE /* Does device have FIFOs? */ -#define XPAR_SPI_0_SLAVE_ONLY FALSE /* Is the device slave only? */ -#define XPAR_SPI_0_NUM_SS_BITS 32 /* Number of slave select bits */ - -#define XPAR_SPI_1_DEVICE_ID 51 /* Device ID for instance */ -#define XPAR_SPI_1_BASEADDR 0x50000100 /* IPIF base address */ -#define XPAR_SPI_1_FIFO_EXIST TRUE /* Does device have FIFOs? */ -#define XPAR_SPI_1_SLAVE_ONLY FALSE /* Is the device slave only? */ -#define XPAR_SPI_1_NUM_SS_BITS 32 /* Number of slave select bits */ - -/***************************************************************************** - * - * OPB Arbiter defines. - * DeviceID starts at 60 - */ -#define XPAR_XOPBARB_NUM_INSTANCES 1 /* Number of instances */ - -#define XPAR_OPBARB_0_DEVICE_ID 60 /* Device ID for instance */ -#define XPAR_OPBARB_0_BASEADDR 0x80000000 /* Register base address */ -#define XPAR_OPBARB_0_NUM_MASTERS 8 /* Number of masters on bus */ - -/***************************************************************************** - * - * Watchdog timer/timebase (WdtTb) defines. - * DeviceID starts at 70 - */ -#define XPAR_XWDTTB_NUM_INSTANCES 1 /* Number of instances */ - -#define XPAR_WDTTB_0_DEVICE_ID 70 /* Device ID for instance */ -#define XPAR_WDTTB_0_BASEADDR 0x70800040 /* Register base address */ - -/***************************************************************************** - * - * Timer Counter (TmrCtr) defines. - * DeviceID starts at 80 - */ -#define XPAR_XTMRCTR_NUM_INSTANCES 2 /* Number of instances */ - -#define XPAR_TMRCTR_0_DEVICE_ID 80 /* Device ID for instance */ -#define XPAR_TMRCTR_0_BASEADDR 0x70800100 /* Register base address */ - -/***************************************************************************** - * - * IIC defines. - * DeviceID starts at 90 - */ -#define XPAR_XIIC_NUM_INSTANCES 2 /* Number of instances */ - -#define XPAR_IIC_0_DEVICE_ID 90 /* Device ID for instance */ -#define XPAR_IIC_0_BASEADDR 0xA8000000 /* Device base address */ -#define XPAR_IIC_0_TEN_BIT_ADR TRUE /* Supports 10 bit addresses */ - -#define XPAR_IIC_1_DEVICE_ID 91 /* Device ID for instance */ -#define XPAR_IIC_1_BASEADDR 0xA8000000 /* Device base address */ -#define XPAR_IIC_1_TEN_BIT_ADR TRUE /* Supports 10 bit addresses */ - -/***************************************************************************** - * - * Flash defines. - * DeviceID starts at 100 - */ -#define XPAR_XFLASH_NUM_INSTANCES 1 /* Number of instances */ -#define XPAR_FLASH_INTEL_SUPPORT /* Include intel flash support */ - -#define XPAR_FLASH_0_DEVICE_ID 100 /* Device ID for first instance -*/ -#define XPAR_FLASH_0_BASEADDR 0xFF000000 /* Base address of parts */ -#define XPAR_FLASH_0_NUM_PARTS 2 /* Number of parts in array */ -#define XPAR_FLASH_0_PART_WIDTH 2 /* Width of each part in bytes */ -#define XPAR_FLASH_0_PART_MODE 2 /* Mode of each part in bytes */ - -/***************************************************************************** - * - * GPIO defines. - * DeviceID starts at 110 - */ -#define XPAR_XGPIO_NUM_INSTANCES 1 - -#define XPAR_GPIO_0_DEVICE_ID 110 /* Device ID for instance */ -#define XPAR_GPIO_0_BASEADDR 0x90000000 /* Register base address */ -#define XPAR_GPIO_0_INTERRUPT_PRESENT 0 /* Interrupts supported? */ -#define XPAR_GPIO_0_IS_DUAL 0 /* Dual channels supported? */ - -/***************************************************************************** - * - * EMC defines. - * DeviceID starts at 120 - */ -#define XPAR_XEMC_NUM_INSTANCES 1 - -#define XPAR_EMC_0_DEVICE_ID 120 /* Device ID for instance */ -#define XPAR_EMC_0_BASEADDR 0xE0000000 /* Register base address */ -#define XPAR_EMC_0_NUM_BANKS_MEM 3 /* Number of banks */ - -/***************************************************************************** - * - * PLB Arbiter defines. - * DeviceID starts at 130 - */ -#define XPAR_XPLBARB_NUM_INSTANCES 1 - -#define XPAR_PLBARB_0_DEVICE_ID 130 /* Device ID for instance */ -#define XPAR_PLBARB_0_BASEADDR 0x300 /* Register base address */ -#define XPAR_PLBARB_0_NUM_MASTERS 1 /* Number of masters on bus */ - -/***************************************************************************** - * - * PLB To OPB Bridge defines. - * DeviceID starts at 140 - */ -#define XPAR_XPLB2OPB_NUM_INSTANCES 1 - -#define XPAR_PLB2OPB_0_DEVICE_ID 140 /* Device ID for instance */ -#define XPAR_PLB2OPB_0_DCR_BASEADDR 0x0 /* DCR Register base address -*/ -#define XPAR_PLB2OPB_0_NUM_MASTERS 1 /* Number of masters on bus -*/ - - -/***************************************************************************** - * - * OPB To PLB Bridge defines. - * DeviceID starts at 150 - */ -#define XPAR_XOPB2PLB_NUM_INSTANCES 1 -#define XPAR_XOPB2PLB_ANY_OPB_REG_INTF /* Accessible from OPB, not DCR */ - -#define XPAR_OPB2PLB_0_DEVICE_ID 150 /* Device ID for instance */ -#define XPAR_OPB2PLB_0_OPB_BASEADDR 0x0 /* Register base address */ -#define XPAR_OPB2PLB_0_DCR_BASEADDR 0x0 /* DCR Register base address */ - - -/***************************************************************************** - * - * System ACE defines. - * DeviceID starts at 160 - */ -#define XPAR_XSYSACE_NUM_INSTANCES 1 - -#define XPAR_SYSACE_0_DEVICE_ID 160 /* Device ID for instance */ -#define XPAR_SYSACE_0_BASEADDR 0xCF000000 /* Register base address */ - - -/***************************************************************************** - * - * HDLC defines. - * DeviceID starts at 170 - */ -#define XPAR_XHDLC_NUM_INSTANCES 1 - -#define XPAR_HDLC_0_DEVICE_ID 170 /* Device ID for instance */ -#define XPAR_HDLC_0_BASEADDR 0x60010000 /* Register base address */ -#define XPAR_HDLC_0_TX_MEM_DEPTH 2048 /* Tx FIFO depth (bytes) */ -#define XPAR_HDLC_0_RX_MEM_DEPTH 2048 /* Rx FIFO depth (bytes) */ -#define XPAR_HDLC_0_DMA_PRESENT 3 /* DMA SG in hardware */ - - -/***************************************************************************** - * - * PS2 Reference driver defines. - * DeviceID starts at 180 - */ -#define XPAR_XPS2_NUM_INSTANCES 2 - -#define XPAR_PS2_0_DEVICE_ID 180 /* Device ID for instance */ -#define XPAR_PS2_0_BASEADDR 0x40010000 /* Register base address */ - -#define XPAR_PS2_1_DEVICE_ID 181 /* Device ID for instance */ -#define XPAR_PS2_1_BASEADDR 0x40020000 /* Register base address */ - -/***************************************************************************** - * - * Rapid IO defines. - * DeviceID starts at 190 - */ -#define XPAR_XRAPIDIO_NUM_INSTANCES 1 - -#define XPAR_RAPIDIO_0_DEVICE_ID 190 /* Device ID for instance */ -#define XPAR_RAPIDIO_0_BASEADDR 0x60000000 /* Register base address */ - - -/***************************************************************************** - * - * PCI defines. - * DeviceID starts at 200 - */ -#define XPAR_XPCI_NUM_INSTANCES 1 -#define XPAR_OPB_PCI_1_DEVICE_ID 200 -#define XPAR_OPB_PCI_1_BASEADDR 0x86000000 -#define XPAR_OPB_PCI_1_HIGHADDR 0x860001FF -#define XPAR_OPB_PCI_1_PCIBAR_0 0x10000000 -#define XPAR_OPB_PCI_1_PCIBAR_LEN_0 27 -#define XPAR_OPB_PCI_1_PCIBAR2IPIF_0 0xF0000000 -#define XPAR_OPB_PCI_1_PCIBAR_ENDIAN_TRANSLATE_EN_0 0 -#define XPAR_OPB_PCI_1_PCI_PREFETCH_0 1 -#define XPAR_OPB_PCI_1_PCI_SPACETYPE_0 1 -#define XPAR_OPB_PCI_1_PCIBAR_1 0x3F000000 -#define XPAR_OPB_PCI_1_PCIBAR_LEN_1 15 -#define XPAR_OPB_PCI_1_PCIBAR2IPIF_1 0xC0FF8000 -#define XPAR_OPB_PCI_1_PCIBAR_ENDIAN_TRANSLATE_EN_1 0 -#define XPAR_OPB_PCI_1_PCI_PREFETCH_1 1 -#define XPAR_OPB_PCI_1_PCI_SPACETYPE_1 1 -#define XPAR_OPB_PCI_1_PCIBAR_2 0x5F000000 -#define XPAR_OPB_PCI_1_PCIBAR_LEN_2 16 -#define XPAR_OPB_PCI_1_PCIBAR2IPIF_2 0x00000000 -#define XPAR_OPB_PCI_1_PCIBAR_ENDIAN_TRANSLATE_EN_2 0 -#define XPAR_OPB_PCI_1_PCI_PREFETCH_2 1 -#define XPAR_OPB_PCI_1_PCI_SPACETYPE_2 1 -#define XPAR_OPB_PCI_1_IPIFBAR_0 0x80000000 -#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_0 0x81FFFFFF -#define XPAR_OPB_PCI_1_IPIFBAR2PCI_0 0xF0000000 -#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_0 0 -#define XPAR_OPB_PCI_1_IPIF_PREFETCH_0 1 -#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_0 1 -#define XPAR_OPB_PCI_1_IPIFBAR_1 0x82000000 -#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_1 0x820007FF -#define XPAR_OPB_PCI_1_IPIFBAR2PCI_1 0xCE000000 -#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_1 0 -#define XPAR_OPB_PCI_1_IPIF_PREFETCH_1 1 -#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_1 1 -#define XPAR_OPB_PCI_1_IPIFBAR_2 0x82320000 -#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_2 0x8232FFFF -#define XPAR_OPB_PCI_1_IPIFBAR2PCI_2 0x00010000 -#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_2 0 -#define XPAR_OPB_PCI_1_IPIF_PREFETCH_2 1 -#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_2 1 -#define XPAR_OPB_PCI_1_IPIFBAR_3 0x82330000 -#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_3 0x8233FFFF -#define XPAR_OPB_PCI_1_IPIFBAR2PCI_3 0x00010000 -#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_3 0 -#define XPAR_OPB_PCI_1_IPIF_PREFETCH_3 1 -#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_3 0 -#define XPAR_OPB_PCI_1_IPIFBAR_4 0x82340000 -#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_4 0x8234FFFF -#define XPAR_OPB_PCI_1_IPIFBAR2PCI_4 0x00010000 -#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_4 0 -#define XPAR_OPB_PCI_1_IPIF_PREFETCH_4 0 -#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_4 0 -#define XPAR_OPB_PCI_1_IPIFBAR_5 0x82350000 -#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_5 0x8235FFFF -#define XPAR_OPB_PCI_1_IPIFBAR2PCI_5 0x00010000 -#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_5 0 -#define XPAR_OPB_PCI_1_IPIF_PREFETCH_5 1 -#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_5 1 -#define XPAR_OPB_PCI_1_DMA_BASEADDR 0x87000000 -#define XPAR_OPB_PCI_1_DMA_HIGHADDR 0x8700007F -#define XPAR_OPB_PCI_1_DMA_CHAN_TYPE 0 -#define XPAR_OPB_PCI_1_DMA_LENGTH_WIDTH 11 - -/***************************************************************************** - * - * GEmac defines. - * DeviceID starts at 210 - */ -#define XPAR_XGEMAC_NUM_INSTANCES 1 -#define XPAR_GEMAC_0_DEVICE_ID 210 -#define XPAR_GEMAC_0_BASEADDR 0x61000000 -#define XPAR_GEMAC_0_DMA_TYPE 9 -#define XPAR_GEMAC_0_MIIM_EXIST 0 -#define XPAR_GEMAC_0_INCLUDE_STATS 0 - - -/***************************************************************************** - * - * Touchscreen defines . - * DeviceID starts at 220 - */ -#define XPAR_XTOUCHSCREEN_NUM_INSTANCES 1 -#define XPAR_TOUCHSCREEN_0_DEVICE_ID 220 -#define XPAR_TOUCHSCREEN_0_BASEADDR 0x70000000 - - -/***************************************************************************** - * - * DDR defines . - * DeviceID starts at 230 - */ -#define XPAR_XDDR_NUM_INSTANCES 1 -#define XPAR_DDR_0_DEVICE_ID 230 -#define XPAR_DDR_0_BASEADDR 0 -#define XPAR_DDR_0_INTERRUPT_PRESENT 0 - -/***************************************************************************** - * - * EmacLite defines . - * DeviceID starts at 240 - */ -#define XPAR_XEMACLITE_NUM_INSTANCES 1 -#define XPAR_EMACLITE_0_DEVICE_ID 240 -#define XPAR_EMACLITE_0_BASEADDR 0 -#define XPAR_EMACLITE_0_TX_PING_PONG 0 -#define XPAR_EMACLITE_0_RX_PING_PONG 0 - -/***************************************************************************** - * - * DSDAC defines . - * DeviceID starts at 250 - */ -#define XPAR_XDSDAC_NUM_INSTANCES 1 -#define XPAR_DSDAC_0_DEVICE_ID 250 -#define XPAR_DSDAC_0_BASEADDR 0 - -/***************************************************************************** - * - * DSADC defines . - * DeviceID starts at 260 - */ -#define XPAR_XDSADC_NUM_INSTANCES 1 -#define XPAR_DSADC_0_DEVICE_ID 260 -#define XPAR_DSADC_0_BASEADDR 0 - -/***************************************************************************** - * - * PCI Arbiter defines. - * DeviceID starts at 270 - */ -#define XPAR_XPCIARB_NUM_INSTANCES 1 -#define XPAR_OPB_PCI_ARBITER_0_DEVICE_ID 270 -#define XPAR_OPB_PCI_ARBITER_0_BASEADDR 0 -#define XPAR_OPB_PCI_ARBITER_0_NUM_PCI_MSTRS 2 - -/***************************************************************************** - * - * TEMAC defines . - * DeviceID starts at 280 - */ -#define XPAR_XTEMAC_NUM_INSTANCES 1 -#define XPAR_TEMAC_0_DEVICE_ID 280 -#define XPAR_TEMAC_0_BASEADDR 0 -#define XPAR_TEMAC_0_DMA_TYPE 3 -#define XPAR_TEMAC_0_RDFIFO_DEPTH 131072 -#define XPAR_TEMAC_0_WRFIFO_DEPTH 131072 -#define XPAR_TEMAC_0_MAC_FIFO_DEPTH 16 -#define XPAR_TEMAC_0_TEMAC_DCR_HOST 0 -#define XPAR_TEMAC_0_DRE 0 - -/***************************************************************************** - * - * DMACENTRAL defines . - * DeviceID starts at 290 - */ -#define XPAR_XDMACENTRAL_NUM_INSTANCES 1 -#define XPAR_DMACENTRAL_0_DEVICE_ID 290 -#define XPAR_DMACENTRAL_0_BASEADDR 0 -#define XPAR_DMACENTRAL_0_READ_OPTIONAL_REGS 0 - -/***************************************************************************** - * - * CAN defines - * DeviceID starts at 300 - */ -#define XPAR_XCAN_NUM_INSTANCES 1 -#define XPAR_CAN_0_DEVICE_ID 300 - -/* Definitions for FLEXRAY Driver */ -#define XPAR_XFLEXRAY_NUM_INSTANCES 1 -#define XPAR_OPB_FLEXRAY_0_DEVICE_ID 0 -#define XPAR_OPB_FLEXRAY_0_BASEADDR 0x7D80E000 -#define XPAR_OPB_FLEXRAY_MAX_PAYLOAD_SIZE 254 -#define XPAR_OPB_FLEXRAY_NO_OF_TX_BUFFERS 128 -#define XPAR_OPB_FLEXRAY_NO_OF_RX_BUFFERS 128 -#define XPAR_OPB_FLEXRAY_RX_FIFO_DEPTH 16 - -/* Definitions for MOST driver */ -#define XPAR_XMOST_NUM_INSTANCES 1 -#define XPAR_MOST_0_DEVICE_ID 0 -#define XPAR_MOST_0_BASEADDR 0x7D810000 -#define XPAR_MOST_OPMODE 0 -#define XPAR_MOST_FWC 16 -#define XPAR_MOST_EWC 16 - -/* Definitions for USB driver */ -#define XPAR_XUSB_NUM_INSTANCES 1 -#define XPAR_USB_0_DEVICE_ID 0 -#define XPAR_USB_0_BASEADDR 0x7D813000 - -/***************************************************************************** - * - * HWICAP defines . - */ -#define XPAR_XHWICAP_NUM_INSTANCES 1 -#define XPAR_OPB_HWICAP_0_DEVICE_ID 0 -#define XPAR_OPB_HWICAP_0_BASEADDR 0xFFFFFFFF - -/***************************************************************************** - * - * LLTEMAC and LLFIFO defines . - */ -#define XPAR_XLLTEMAC_NUM_INSTANCES 1 -#define XPAR_XLLFIFO_NUM_INSTANCES 1 - -/***************************************************************************** - * - * PCIe defines . - */ -#define XPAR_XPCIE_NUM_INSTANCES 1 - -/***************************************************************************** - * - * MPMC defines . - */ -#define XPAR_XMPMC_NUM_INSTANCES 1 - -/***************************************************************************** - * - * SYSMON defines . - */ -#define XPAR_XSYSMON_NUM_INSTANCES 1 - - -/***************************************************************************** - * - * AXI Ethernet defines . - */ -#define XPAR_XAXIETHERNET_NUM_INSTANCES 1 - -/***************************************************************************** - * - * TFT defines . - */ -#define XPAR_XTFT_NUM_INSTANCES 1 - -/***************************************************************************** - * - * MBox defines . - */ -#define XPAR_XMBOX_NUM_INSTANCES 1 -#define XPAR_XMBOX_0_DEVICE_ID 0 -#define XPAR_XMBOX_0_BASEADDR 0x7D814000 -#define XPAR_XMBOX_0_NUM_CHANNELS 1 -#define XPAR_XMBOX_0_USE_FSL 0 - - -/***************************************************************************** - * - * Mutex defines . - */ -#define XPAR_XMUTEX_NUM_INSTANCES 1 -#define XPAR_XMUTEX_0_DEVICE_ID 0 -#define XPAR_XMUTEX_0_BASEADDR 0x7D815000 -#define XPAR_XMUTEX_0_NUM_MUTEX 2 -#define XPAR_XMUTEX_0_ENABLE_USER 1 - -/* - * MicroBlaze sets this define but for the build check to - * function it needs to be set here - */ -#define XPAR_CPU_ID 0 - - -/***************************************************************************** - * - * BRAM defines . - */ -#define XPAR_XBRAM_NUM_INSTANCES 1 - - -/***************************************************************************** - * - * AXI PCIE defines . - */ -#define XPAR_XAXIPCIE_NUM_INSTANCES 1 - -/***************************************************************************** - * - * V6 DDRX efines . - */ -#define XPAR_XV6DDR_NUM_INSTANCES 1 - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ - - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xstatus.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xstatus.h deleted file mode 100644 index e80558f058f67bf0d93b76715ccca74923132d4d..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xstatus.h +++ /dev/null @@ -1,418 +0,0 @@ -/****************************************************************************** -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND -* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, -* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION -* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE. -* -* (c) Copyright 2002-2011 Xilinx Inc. -* All rights reserved. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xstatus.h -* -* This file contains Xilinx software status codes. Status codes have their -* own data type called int. These codes are used throughout the Xilinx -* device drivers. -* -******************************************************************************/ - -#ifndef XSTATUS_H /* prevent circular inclusions */ -#define XSTATUS_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xbasic_types.h" - -/************************** Constant Definitions *****************************/ - -/*********************** Common statuses 0 - 500 *****************************/ - -#define XST_SUCCESS 0L -#define XST_FAILURE 1L -#define XST_DEVICE_NOT_FOUND 2L -#define XST_DEVICE_BLOCK_NOT_FOUND 3L -#define XST_INVALID_VERSION 4L -#define XST_DEVICE_IS_STARTED 5L -#define XST_DEVICE_IS_STOPPED 6L -#define XST_FIFO_ERROR 7L /* an error occurred during an - operation with a FIFO such as - an underrun or overrun, this - error requires the device to - be reset */ -#define XST_RESET_ERROR 8L /* an error occurred which requires - the device to be reset */ -#define XST_DMA_ERROR 9L /* a DMA error occurred, this error - typically requires the device - using the DMA to be reset */ -#define XST_NOT_POLLED 10L /* the device is not configured for - polled mode operation */ -#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put - the specified data into */ -#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough - to hold the expected data */ -#define XST_NO_DATA 13L /* there was no data available */ -#define XST_REGISTER_ERROR 14L /* a register did not contain the - expected value */ -#define XST_INVALID_PARAM 15L /* an invalid parameter was passed - into the function */ -#define XST_NOT_SGDMA 16L /* the device is not configured for - scatter-gather DMA operation */ -#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */ -#define XST_NO_CALLBACK 18L /* a callback has not yet been - registered */ -#define XST_NO_FEATURE 19L /* device is not configured with - the requested feature */ -#define XST_NOT_INTERRUPT 20L /* device is not configured for - interrupt mode operation */ -#define XST_DEVICE_BUSY 21L /* device is busy */ -#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device - have maxed out */ -#define XST_IS_STARTED 23L /* used when part of device is - already started i.e. - sub channel */ -#define XST_IS_STOPPED 24L /* used when part of device is - already stopped i.e. - sub channel */ -#define XST_DATA_LOST 26L /* driver defined error */ -#define XST_RECV_ERROR 27L /* generic receive error */ -#define XST_SEND_ERROR 28L /* generic transmit error */ -#define XST_NOT_ENABLED 29L /* a requested service is not - available because it has not - been enabled */ - -/***************** Utility Component statuses 401 - 500 *********************/ - -#define XST_MEMTEST_FAILED 401L /* memory test failed */ - - -/***************** Common Components statuses 501 - 1000 *********************/ - -/********************* Packet Fifo statuses 501 - 510 ************************/ - -#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */ -#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */ -#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value - was invalid after reset */ -#define XST_PFIFO_ERROR 504L /* generic packet FIFO error */ -#define XST_PFIFO_DEADLOCK 505L /* packet FIFO is reporting - * empty and full simultaneously - */ - -/************************** DMA statuses 511 - 530 ***************************/ - -#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer - failed */ -#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value - was invalid after reset */ -#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains - no buffer descriptors ready - to be processed */ -#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */ -#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */ -#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of - the scatter gather list are - being used */ -#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer - descriptor which is to be - copied over in the scatter - list is locked */ -#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been - put into the scatter gather - list to be commited */ -#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold - specified was larger than the - total # of buffer descriptors - in the scatter gather list */ -#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has - already been created */ -#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has - been created */ -#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was - being started was not committed - to the list */ -#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start - has already been used by the - hardware so it can't be reused - */ -#define XST_DMA_SG_LIST_ERROR 526L /* general purpose list access - error */ -#define XST_DMA_BD_ERROR 527L /* general buffer descriptor - error */ - -/************************** IPIF statuses 531 - 550 ***************************/ - -#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width - was passed into the function */ -#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at - reset was not valid */ -#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt - status register did not read - back correctly */ -#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status - register did not reset when - acked */ -#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable - register was not updated when - other registers changed */ -#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt - status register did not read - back correctly */ -#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register - did not reset when acked */ -#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was - not updated correctly when other - registers changed */ -#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending - register did not indicate the - expected value */ -#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register - did not indicate the expected - value */ -#define XST_IPIF_ERROR 541L /* generic ipif error */ - -/****************** Device specific statuses 1001 - 4095 *********************/ - -/********************* Ethernet statuses 1001 - 1050 *************************/ - -#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough - * to hold the minimum number of - * buffers or descriptors */ -#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */ -#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */ -#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */ -#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Driver is out of buffers */ -#define XST_EMAC_PARSE_ERROR 1006L /* Invalid driver init string */ -#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late - * collision on polled send */ - -/*********************** UART statuses 1051 - 1075 ***************************/ -#define XST_UART - -#define XST_UART_INIT_ERROR 1051L -#define XST_UART_START_ERROR 1052L -#define XST_UART_CONFIG_ERROR 1053L -#define XST_UART_TEST_FAIL 1054L -#define XST_UART_BAUD_ERROR 1055L -#define XST_UART_BAUD_RANGE 1056L - - -/************************ IIC statuses 1076 - 1100 ***************************/ - -#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */ -#define XST_IIC_BUS_BUSY 1077 /* bus found busy */ -#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */ - /* general call address */ -#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */ - /* value after reset not valid */ -#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */ - /* value after reset not valid */ -#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */ - /* value after reset not valid */ -#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */ - /* value after reset not valid */ -#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */ - /* didn't return value written */ -#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */ - /* didn't return value written */ -#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */ - /* didn't return value written */ -#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */ - /* didn't return value written */ -#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */ - /* didn't return written value */ -#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */ - -/*********************** ATMC statuses 1101 - 1125 ***************************/ - -#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM - controller hit the max value - which requires the statistics - to be cleared */ - -/*********************** Flash statuses 1126 - 1150 **************************/ - -#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming - */ -#define XST_FLASH_READY 1127L /* Flash is ready for commands */ -#define XST_FLASH_ERROR 1128L /* Flash had detected an internal - error. Use XFlash_DeviceControl - to retrieve device specific codes - */ -#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state - */ -#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state - */ -#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by - driver */ -#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */ -#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */ -#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation - aborted due to a timeout */ -#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its - addressible range */ -#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */ -#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from - write/erase function with - XFL_NON_BLOCKING_WRITE/ERASE - option cleared */ -#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */ - -/*********************** SPI statuses 1151 - 1175 ****************************/ - -#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */ -#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */ -#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */ -#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */ -#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */ -#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being - * selected */ -#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */ -#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only - */ -#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */ -#define XST_SPI_SLAVE_MODE 1160 /* device has been addressed as slave */ -#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /* device received data in slave mode */ - -#define XST_SPI_COMMAND_ERROR 1162 /* unrecognised command - qspi only */ - -/********************** OPB Arbiter statuses 1176 - 1200 *********************/ - -#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either - * one master assigned to two or more - * priorities, or one master not - * assigned to any priority - */ -#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the - * priority levels without first - * suspending the use of priority - * levels - */ -#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but - * bus parking was not enabled - */ -#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed - * priority mode to allow the - * priorities to be changed - */ - -/************************ Intc statuses 1201 - 1225 **************************/ - -#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */ -#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */ - -/********************** TmrCtr statuses 1226 - 1250 **************************/ - -#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */ - -/********************** WdtTb statuses 1251 - 1275 ***************************/ - -#define XST_WDTTB_TIMER_FAILED 1251L - -/********************** PlbArb statuses 1276 - 1300 **************************/ - -#define XST_PLBARB_FAIL_SELFTEST 1276L - -/********************** Plb2Opb statuses 1301 - 1325 *************************/ - -#define XST_PLB2OPB_FAIL_SELFTEST 1301L - -/********************** Opb2Plb statuses 1326 - 1350 *************************/ - -#define XST_OPB2PLB_FAIL_SELFTEST 1326L - -/********************** SysAce statuses 1351 - 1360 **************************/ - -#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */ - -/********************** PCI Bridge statuses 1361 - 1375 **********************/ - -#define XST_PCI_INVALID_ADDRESS 1361L - -/********************** FlexRay constants 1400 - 1409 *************************/ - -#define XST_FR_TX_ERROR 1400 -#define XST_FR_TX_BUSY 1401 -#define XST_FR_BUF_LOCKED 1402 -#define XST_FR_NO_BUF 1403 - -/****************** USB constants 1410 - 1420 *******************************/ - -#define XST_USB_ALREADY_CONFIGURED 1410 -#define XST_USB_BUF_ALIGN_ERROR 1411 -#define XST_USB_NO_DESC_AVAILABLE 1412 -#define XST_USB_BUF_TOO_BIG 1413 -#define XST_USB_NO_BUF 1414 - -/****************** HWICAP constants 1421 - 1429 *****************************/ - -#define XST_HWICAP_WRITE_DONE 1421 - - -/****************** AXI VDMA constants 1430 - 1440 *****************************/ - -#define XST_VDMA_MISMATCH_ERROR 1430 - -/*********************** NAND Flash statuses 1441 - 1459 *********************/ - -#define XST_NAND_BUSY 1441L /* Flash is erasing or - * programming - */ -#define XST_NAND_READY 1442L /* Flash is ready for commands - */ -#define XST_NAND_ERROR 1443L /* Flash had detected an - * internal error. - */ -#define XST_NAND_PART_NOT_SUPPORTED 1444L /* Flash type not supported by - * driver - */ -#define XST_NAND_OPT_NOT_SUPPORTED 1445L /* Operation not supported - */ -#define XST_NAND_TIMEOUT_ERROR 1446L /* Programming or erase - * operation aborted due to a - * timeout - */ -#define XST_NAND_ADDRESS_ERROR 1447L /* Accessed flash outside its - * addressible range - */ -#define XST_NAND_ALIGNMENT_ERROR 1448L /* Write alignment error - */ -#define XST_NAND_PARAM_PAGE_ERROR 1449L /* Failed to read parameter - * page of the device - */ -#define XST_NAND_CACHE_ERROR 1450L /* Flash page buffer error - */ - -#define XST_NAND_WRITE_PROTECTED 1451L /* Flash is write protected - */ - -/**************************** Type Definitions *******************************/ - -typedef int XStatus; - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xutil.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xutil.h deleted file mode 100644 index 39469fef78bf01fda56bc6de7cb446bbaed0996e..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xutil.h +++ /dev/null @@ -1,154 +0,0 @@ -/* $Id: xutil.h,v 1.8 2007/05/04 21:55:59 wre Exp $ */ -/****************************************************************************** -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND -* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, -* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION -* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE. -* -* (c) Copyright 2002 Xilinx Inc. -* All rights reserved. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xutil.h -* -* This file contains utility functions such as memory test functions. -* -* <b>Memory test description</b> -* -* A subset of the memory tests can be selected or all of the tests can be run -* in order. If there is an error detected by a subtest, the test stops and the -* failure code is returned. Further tests are not run even if all of the tests -* are selected. -* -* Subtest descriptions: -* <pre> -* XUT_ALLMEMTESTS: -* Runs all of the following tests -* -* XUT_INCREMENT: -* Incrementing Value Test. -* This test starts at 'XUT_MEMTEST_INIT_VALUE' and uses the incrementing -* value as the test value for memory. -* -* XUT_WALKONES: -* Walking Ones Test. -* This test uses a walking '1' as the test value for memory. -* location 1 = 0x00000001 -* location 2 = 0x00000002 -* ... -* -* XUT_WALKZEROS: -* Walking Zero's Test. -* This test uses the inverse value of the walking ones test -* as the test value for memory. -* location 1 = 0xFFFFFFFE -* location 2 = 0xFFFFFFFD -* ... -* -* XUT_INVERSEADDR: -* Inverse Address Test. -* This test uses the inverse of the address of the location under test -* as the test value for memory. -* -* XUT_FIXEDPATTERN: -* Fixed Pattern Test. -* This test uses the provided patters as the test value for memory. -* If zero is provided as the pattern the test uses '0xDEADBEEF". -* </pre> -* -* <i>WARNING</i> -* -* The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces -* have been set up. -* -* The address, Addr, provided to the memory tests is not checked for -* validity except for the NULL case. It is possible to provide a code-space -* pointer for this test to start with and ultimately destroy executable code -* causing random failures. -* -* @note -* -* Used for spaces where the address range of the region is smaller than -* the data width. If the memory range is greater than 2 ** width, -* the patterns used in XUT_WALKONES and XUT_WALKZEROS will repeat on a -* boundry of a power of two making it more difficult to detect addressing -* errors. The XUT_INCREMENT and XUT_INVERSEADDR tests suffer the same -* problem. Ideally, if large blocks of memory are to be tested, break -* them up into smaller regions of memory to allow the test patterns used -* not to repeat over the region tested. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a ecm 11/01/01 First release -* 1.00a xd 11/03/04 Improved support for doxygen. -* </pre> -* -******************************************************************************/ - -#ifndef XUTIL_H /* prevent circular inclusions */ -#define XUTIL_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ -#include "xbasic_types.h" -#include "xstatus.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - -/* xutil_memtest defines */ - -#define XUT_MEMTEST_INIT_VALUE 1 - -/** @name Memory subtests - * @{ - */ -/** - * See the detailed description of the subtests in the file description. - */ -#define XUT_ALLMEMTESTS 0 -#define XUT_INCREMENT 1 -#define XUT_WALKONES 2 -#define XUT_WALKZEROS 3 -#define XUT_INVERSEADDR 4 -#define XUT_FIXEDPATTERN 5 -#define XUT_MAXTEST XUT_FIXEDPATTERN -/* @} */ - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - -/* xutil_memtest prototypes */ - -int XUtil_MemoryTest32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest); -int XUtil_MemoryTest16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest); -int XUtil_MemoryTest8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xutil_memtest.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xutil_memtest.c deleted file mode 100644 index 47e4ce2ad308f8646ca28b9457322eb011ff9f07..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xutil_memtest.c +++ /dev/null @@ -1,1173 +0,0 @@ -/* $Id: xutil_memtest.c,v 1.10 2007/05/04 21:55:59 wre Exp $ */ -/****************************************************************************** -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND -* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, -* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION -* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE. -* -* (c) Copyright 2002 Xilinx Inc. -* All rights reserved. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xutil_memtest.c -* -* Contains the memory test utility functions. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a ecm 11/01/01 First release -* 1.00a xd 11/03/04 Improved support for doxygen. -* </pre> -* -*****************************************************************************/ - -/***************************** Include Files ********************************/ -#include "xbasic_types.h" -#include "xstatus.h" -#include "xutil.h" - -/************************** Constant Definitions ****************************/ -/************************** Function Prototypes *****************************/ - -static u32 RotateLeft(u32 Input, u8 Width); - -/* define ROTATE_RIGHT to give access to this functionality */ -/* #define ROTATE_RIGHT */ -#ifdef ROTATE_RIGHT -static u32 RotateRight(u32 Input, u8 Width); -#endif /* ROTATE_RIGHT */ - - -/*****************************************************************************/ -/** -* -* Performs a destructive 32-bit wide memory test. -* -* @param Addr is a pointer to the region of memory to be tested. -* @param Words is the length of the block. -* @param Pattern is the constant used for the constant pattern test, if 0, -* 0xDEADBEEF is used. -* @param Subtest is the test selected. See xutil.h for possible values. -* -* @return -* -* - XST_MEMTEST_FAILED is returned for a failure -* - XST_SUCCESS is returned for a pass -* -* @note -* -* Used for spaces where the address range of the region is smaller than -* the data width. If the memory range is greater than 2 ** width, -* the patterns used in XUT_WALKONES and XUT_WALKZEROS will repeat on a -* boundry of a power of two making it more difficult to detect addressing -* errors. The XUT_INCREMENT and XUT_INVERSEADDR tests suffer the same -* problem. Ideally, if large blocks of memory are to be tested, break -* them up into smaller regions of memory to allow the test patterns used -* not to repeat over the region tested. -* -*****************************************************************************/ -int XUtil_MemoryTest32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) -{ - u32 i; - u32 j; - u32 Val = XUT_MEMTEST_INIT_VALUE; - u32 FirstVal = XUT_MEMTEST_INIT_VALUE; - u32 Word; - - XASSERT_NONVOID(Words != 0); - XASSERT_NONVOID(Subtest <= XUT_MAXTEST); - - /* - * Select the proper Subtest - */ - - - switch (Subtest) { - - case XUT_ALLMEMTESTS: - - /* this case executes all of the Subtests */ - - /* fall through case statement */ - - case XUT_INCREMENT: - { - - /* - * Fill the memory with incrementing - * values starting from 'FirstVal' - */ - for (i = 0L; i < Words; i++) { - Addr[i] = Val; - - /* write memory location */ - - Val++; - } - - /* - * Restore the reference 'Val' to the - * initial value - */ - - Val = FirstVal; - - /* - * Check every word within the Words - * of tested memory and compare it - * with the incrementing reference - * Val - */ - - for (i = 0L; i < Words; i++) { - Word = Addr[i]; - - if (Word != Val) { - return XST_MEMTEST_FAILED; - } - - Val++; - } - - - if (Subtest != XUT_ALLMEMTESTS) { - return XST_SUCCESS; - } - - - } /* end of case 1 */ - - /* fall through case statement */ - - case XUT_WALKONES: - { - /* - * set up to cycle through all possible initial - * test Patterns for walking ones test - */ - - for (j = 0L; j < 32; j++) { - /* - * Generate an initial value for walking ones test to test for bad - * data bits - */ - - Val = 1 << j; - - /* - * START walking ones test - * Write a one to each data bit indifferent locations - */ - - for (i = 0L; i < 32; i++) { - - /* write memory location */ - - Addr[i] = Val; - Val = (u32) RotateLeft(Val, 32); - - } - - /* - * Restore the reference 'Val' to the - * initial value - */ - Val = 1 << j; - - /* Read the values from each location that was written */ - - for (i = 0L; i < 32; i++) { - /* read memory location */ - - Word = Addr[i]; - - if (Word != Val) { - return XST_MEMTEST_FAILED; - } - - Val = (u32) RotateLeft(Val, 32); - - } - - } - - if (Subtest != XUT_ALLMEMTESTS) { - return XST_SUCCESS; - } - - - } /* end of case 2 */ - - /* fall through case statement */ - - case XUT_WALKZEROS: - { - /* - * set up to cycle through all possible - * initial test Patterns for walking zeros test - */ - - for (j = 0L; j < 32; j++) { - - /* - * Generate an initial value for walking ones test to test for - * bad data bits - */ - - Val = ~(1 << j); - - /* - * START walking zeros test - * Write a one to each data bit indifferent locations - */ - - for (i = 0L; i < 32; i++) { - - /* write memory location */ - - Addr[i] = Val; - Val = ~((u32) RotateLeft(~Val, 32)); - - } - - /* - * Restore the reference 'Val' to the - * initial value - */ - - Val = ~(1 << j); - - /* Read the values from each location that was written */ - - for (i = 0L; i < 32; i++) { - - /* read memory location */ - - Word = Addr[i]; - - if (Word != Val) { - return XST_MEMTEST_FAILED; - } - - Val = ~((u32) RotateLeft(~Val, 32)); - - } - - } - - if (Subtest != XUT_ALLMEMTESTS) { - return XST_SUCCESS; - } - - } /* end of case 3 */ - - /* fall through case statement */ - - case XUT_INVERSEADDR: - { - - /* Fill the memory with inverse of address */ - - for (i = 0L; i < Words; i++) { - - /* write memory location */ - - Val = (u32) (~((u32) (&Addr[i]))); - - Addr[i] = Val; - - } - - /* - * Check every word within the Words - * of tested memory - */ - - for (i = 0L; i < Words; i++) { - - /* Read the location */ - - Word = Addr[i]; - - Val = (u32) (~((u32) (&Addr[i]))); - - if ((Word ^ Val) != 0x00000000) { - return XST_MEMTEST_FAILED; - } - } - - if (Subtest != XUT_ALLMEMTESTS) { - return XST_SUCCESS; - } - - - } /* end of case 4 */ - - - /* fall through case statement */ - - case XUT_FIXEDPATTERN: - { - - /* - * Generate an initial value for - * memory testing - */ - - if (Pattern == 0) { - Val = 0xDEADBEEF; - - } - else { - Val = Pattern; - - } - - /* - * Fill the memory with fixed pattern - */ - - for (i = 0L; i < Words; i++) { - /* write memory location */ - - Addr[i] = Val; - - } - - /* - * Check every word within the Words - * of tested memory and compare it - * with the fixed pattern - */ - - for (i = 0L; i < Words; i++) { - - /* read memory location */ - - Word = Addr[i]; - - if (Word != Val) { - return XST_MEMTEST_FAILED; - } - } - - if (Subtest != XUT_ALLMEMTESTS) { - return XST_SUCCESS; - } - - } /* end of case 5 */ - - /* this break is for the prior fall through case statements */ - - break; - - default: - { - return XST_MEMTEST_FAILED; - } - - } /* end of switch */ - - /* Successfully passed memory test ! */ - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* Performs a destructive 16-bit wide memory test. -* -* @param Addr is a pointer to the region of memory to be tested. -* @param Words is the length of the block. -* @param Pattern is the constant used for the constant pattern test, if 0, -* 0xDEADBEEF is used. -* @param Subtest is the test selected. See xutil.h for possible values. -* -* @return -* -* - XST_MEMTEST_FAILED is returned for a failure -* - XST_SUCCESS is returned for a pass -* -* @note -* -* Used for spaces where the address range of the region is smaller than -* the data width. If the memory range is greater than 2 ** width, -* the patterns used in XUT_WALKONES and XUT_WALKZEROS will repeat on a -* boundry of a power of two making it more difficult to detect addressing -* errors. The XUT_INCREMENT and XUT_INVERSEADDR tests suffer the same -* problem. Ideally, if large blocks of memory are to be tested, break -* them up into smaller regions of memory to allow the test patterns used -* not to repeat over the region tested. -* -*****************************************************************************/ -int XUtil_MemoryTest16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) -{ - u32 i; - u32 j; - u16 Val = XUT_MEMTEST_INIT_VALUE; - u16 FirstVal = XUT_MEMTEST_INIT_VALUE; - u16 Word; - - XASSERT_NONVOID(Words != 0); - XASSERT_NONVOID(Subtest <= XUT_MAXTEST); - - /* - * selectthe proper Subtest(s) - */ - - switch (Subtest) { - - case XUT_ALLMEMTESTS: - - /* this case executes all of the Subtests */ - - /* fall through case statement */ - - case XUT_INCREMENT: - { - - /* - * Fill the memory with incrementing - * values starting from 'FirstVal' - */ - for (i = 0L; i < Words; i++) { - /* write memory location */ - - Addr[i] = Val; - - Val++; - } - - /* - * Restore the reference 'Val' to the - * initial value - */ - - Val = FirstVal; - - /* - * Check every word within the Words - * of tested memory and compare it - * with the incrementing reference - * Val - */ - - for (i = 0L; i < Words; i++) { - - /* read memory location */ - - Word = Addr[i]; - - if (Word != Val) { - return XST_MEMTEST_FAILED; - } - Val++; - } - - if (Subtest != XUT_ALLMEMTESTS) { - return XST_SUCCESS; - } - - } /* end of case 1 */ - - /* fall through case statement */ - - case XUT_WALKONES: - { - /* - * set up to cycle through all possible initial test - * Patterns for walking ones test - */ - - for (j = 0L; j < 16; j++) { - /* - * Generate an initial value for walking ones test to test for bad - * data bits - */ - - Val = 1 << j; - - /* - * START walking ones test - * Write a one to each data bit indifferent locations - */ - - for (i = 0L; i < 16; i++) { - - /* write memory location */ - - Addr[i] = Val; - - Val = (u16) RotateLeft(Val, 16); - - } - - /* - * Restore the reference 'Val' to the - * initial value - */ - - Val = 1 << j; - - /* Read the values from each location that was written */ - - for (i = 0L; i < 16; i++) { - - /* read memory location */ - - Word = Addr[i]; - - if (Word != Val) { - return XST_MEMTEST_FAILED; - } - - Val = (u16) RotateLeft(Val, 16); - - } - - } - - if (Subtest != XUT_ALLMEMTESTS) { - return XST_SUCCESS; - } - - - } /* end of case 2 */ - - /* fall through case statement */ - - case XUT_WALKZEROS: - { - /* - * set up to cycle through all possible initial - * test Patterns for walking zeros test - */ - - for (j = 0L; j < 16; j++) { - - /* - * Generate an initial value for walking ones - * test to test for bad - * data bits - */ - - Val = ~(1 << j); - - /* - * START walking zeros test - * Write a one to each data bit indifferent locations - */ - - for (i = 0L; i < 16; i++) { - - - /* write memory location */ - - Addr[i] = Val; - Val = ~((u16) RotateLeft(~Val, 16)); - - } - - /* - * Restore the reference 'Val' to the - * initial value - */ - - Val = ~(1 << j); - - /* Read the values from each location that was written */ - - for (i = 0L; i < 16; i++) { - - /* read memory location */ - - Word = Addr[i]; - - if (Word != Val) { - return XST_MEMTEST_FAILED; - } - - Val = ~((u16) RotateLeft(~Val, 16)); - - } - - } - - if (Subtest != XUT_ALLMEMTESTS) { - return XST_SUCCESS; - } - - } /* end of case 3 */ - - /* fall through case statement */ - - case XUT_INVERSEADDR: - { - - /* Fill the memory with inverse of address */ - - for (i = 0L; i < Words; i++) { - /* write memory location */ - - Val = (u16) (~((u32) (&Addr[i]))); - Addr[i] = Val; - - } - - /* - * Check every word within the Words - * of tested memory - */ - - for (i = 0L; i < Words; i++) { - - /* read memory location */ - - Word = Addr[i]; - - Val = (u16) (~((u32) (&Addr[i]))); - - if ((Word ^ Val) != 0x0000) { - return XST_MEMTEST_FAILED; - } - } - - if (Subtest != XUT_ALLMEMTESTS) { - return XST_SUCCESS; - } - - - } /* end of case 4 */ - - - /* fall through case statement */ - - case XUT_FIXEDPATTERN: - { - - /* - * Generate an initial value for - * memory testing - */ - - if (Pattern == 0) { - Val = 0xDEAD; - - } - else { - Val = Pattern; - - } - - /* - * Fill the memory with fixed pattern - */ - - for (i = 0L; i < Words; i++) { - - /* write memory location */ - - Addr[i] = Val; - - } - - /* - * Check every word within the Words - * of tested memory and compare it - * with the fixed pattern - */ - - for (i = 0L; i < Words; i++) { - - /* read memory location */ - - Word = Addr[i]; - - if (Word != Val) { - return XST_MEMTEST_FAILED; - } - } - - if (Subtest != XUT_ALLMEMTESTS) { - return XST_SUCCESS; - } - - } /* end of case 5 */ - - /* this break is for the prior fall through case statements */ - - break; - - default: - { - return XST_MEMTEST_FAILED; - } - - } /* end of switch */ - - /* Successfully passed memory test ! */ - - return XST_SUCCESS; -} - - -/*****************************************************************************/ -/** -* -* Performs a destructive 8-bit wide memory test. -* -* @param Addr is a pointer to the region of memory to be tested. -* @param Words is the length of the block. -* @param Pattern is the constant used for the constant pattern test, if 0, -* 0xDEADBEEF is used. -* @param Subtest is the test selected. See xutil.h for possible values. -* -* @return -* -* - XST_MEMTEST_FAILED is returned for a failure -* - XST_SUCCESS is returned for a pass -* -* @note -* -* Used for spaces where the address range of the region is smaller than -* the data width. If the memory range is greater than 2 ** width, -* the patterns used in XUT_WALKONES and XUT_WALKZEROS will repeat on a -* boundry of a power of two making it more difficult to detect addressing -* errors. The XUT_INCREMENT and XUT_INVERSEADDR tests suffer the same -* problem. Ideally, if large blocks of memory are to be tested, break -* them up into smaller regions of memory to allow the test patterns used -* not to repeat over the region tested. -* -*****************************************************************************/ -int XUtil_MemoryTest8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) -{ - u32 i; - u32 j; - u8 Val = XUT_MEMTEST_INIT_VALUE; - u8 FirstVal = XUT_MEMTEST_INIT_VALUE; - u8 Word; - - XASSERT_NONVOID(Words != 0); - XASSERT_NONVOID(Subtest <= XUT_MAXTEST); - - /* - * select the proper Subtest(s) - */ - - switch (Subtest) { - - case XUT_ALLMEMTESTS: - - /* this case executes all of the Subtests */ - - /* fall through case statement */ - - case XUT_INCREMENT: - { - - /* - * Fill the memory with incrementing - * values starting from 'FirstVal' - */ - for (i = 0L; i < Words; i++) { - - /* write memory location */ - - Addr[i] = Val; - Val++; - } - - /* - * Restore the reference 'Val' to the - * initial value - */ - - Val = FirstVal; - - /* - * Check every word within the Words - * of tested memory and compare it - * with the incrementing reference - * Val - */ - - for (i = 0L; i < Words; i++) { - - /* read memory location */ - - Word = Addr[i]; - - if (Word != Val) { - return XST_MEMTEST_FAILED; - } - Val++; - } - - - if (Subtest != XUT_ALLMEMTESTS) { - return XST_SUCCESS; - } - - - } /* end of case 1 */ - - /* fall through case statement */ - - case XUT_WALKONES: - { - /* - * set up to cycle through all possible initial - * test Patterns for walking ones test - */ - - for (j = 0L; j < 8; j++) { - /* - * Generate an initial value for walking ones test to test - * for bad data bits - */ - - Val = 1 << j; - - /* - * START walking ones test - * Write a one to each data bit indifferent locations - */ - - for (i = 0L; i < 8; i++) { - - /* write memory location */ - - Addr[i] = Val; - Val = (u8) RotateLeft(Val, 8); - } - - /* - * Restore the reference 'Val' to the - * initial value - */ - Val = 1 << j; - - /* Read the values from each location that was written */ - - for (i = 0L; i < 8; i++) { - - /* read memory location */ - - Word = Addr[i]; - - if (Word != Val) { - return XST_MEMTEST_FAILED; - } - - Val = (u8) RotateLeft(Val, 8); - - } - - } - - if (Subtest != XUT_ALLMEMTESTS) { - return XST_SUCCESS; - } - - - } /* end of case 2 */ - - /* fall through case statement */ - - case XUT_WALKZEROS: - { - /* - * set up to cycle through all possible initial test - * Patterns for walking zeros test - */ - - for (j = 0L; j < 8; j++) { - - /* - * Generate an initial value for walking ones test to test - * for bad data bits - */ - - Val = ~(1 << j); - - /* - * START walking zeros test - * Write a one to each data bit indifferent locations - */ - - for (i = 0L; i < 8; i++) { - - - /* write memory location */ - - Addr[i] = Val; - Val = ~((u8) RotateLeft(~Val, 8)); - - } - - /* - * Restore the reference 'Val' to the - * initial value - */ - - Val = ~(1 << j); - - /* Read the values from each location that was written */ - - for (i = 0L; i < 8; i++) { - - /* read memory location */ - - Word = Addr[i]; - - if (Word != Val) { - return XST_MEMTEST_FAILED; - } - - Val = ~((u8) RotateLeft(~Val, 8)); - - } - - } - - if (Subtest != XUT_ALLMEMTESTS) { - return XST_SUCCESS; - } - - } /* end of case 3 */ - - /* fall through case statement */ - - case XUT_INVERSEADDR: - { - - /* Fill the memory with inverse of address */ - - for (i = 0L; i < Words; i++) { - - /* write memory location */ - - Val = (u8) (~((u32) (&Addr[i]))); - Addr[i] = Val; - - } - - /* - * Check every word within the Words - * of tested memory - */ - - for (i = 0L; i < Words; i++) { - - /* read memory location */ - - Word = Addr[i]; - - Val = (u8) (~((u32) (&Addr[i]))); - - if ((Word ^ Val) != 0x00) { - return XST_MEMTEST_FAILED; - } - } - - if (Subtest != XUT_ALLMEMTESTS) { - return XST_SUCCESS; - } - - - } /* end of case 4 */ - - - /* fall through case statement */ - - case XUT_FIXEDPATTERN: - { - - /* - * Generate an initial value for - * memory testing - */ - - if (Pattern == 0) { - Val = 0xA5; - - } - else { - Val = Pattern; - - } - - /* - * Fill the memory with fixed pattern - */ - - for (i = 0L; i < Words; i++) { - - /* write memory location */ - - Addr[i] = Val; - - } - - /* - * Check every word within the Words - * of tested memory and compare it - * with the fixed pattern - */ - - for (i = 0L; i < Words; i++) { - - /* read memory location */ - - Word = Addr[i]; - - if (Word != Val) { - return XST_MEMTEST_FAILED; - } - } - - if (Subtest != XUT_ALLMEMTESTS) { - return XST_SUCCESS; - } - - } /* end of case 5 */ - - /* this break is for the prior fall through case statements */ - - break; - - default: - { - return XST_MEMTEST_FAILED; - } - - } /* end of switch */ - - /* Successfully passed memory test ! */ - - return XST_SUCCESS; -} - - -/*****************************************************************************/ -/** -* -* Rotates the provided value to the left one bit position -* -* @param Input is value to be rotated to the left -* @param Width is the number of bits in the input data -* -* @return -* -* The resulting unsigned long value of the rotate left -* -* @note -* -* None. -* -*****************************************************************************/ -static u32 RotateLeft(u32 Input, u8 Width) -{ - u32 Msb; - u32 ReturnVal; - u32 WidthMask; - u32 MsbMask; - - /* - * set up the WidthMask and the MsbMask - */ - - MsbMask = 1 << (Width - 1); - - WidthMask = (MsbMask << 1) - 1; - - /* - * set the width of the Input to the correct width - */ - - Input = Input & WidthMask; - - Msb = Input & MsbMask; - - ReturnVal = Input << 1; - - if (Msb != 0x00000000) { - ReturnVal = ReturnVal | 0x00000001; - } - - ReturnVal = ReturnVal & WidthMask; - - return (ReturnVal); - -} - -#ifdef ROTATE_RIGHT -/*****************************************************************************/ -/** -* -* Rotates the provided value to the right one bit position -* -* @param Input is value to be rotated to the right -* @param Width is the number of bits in the input data -* -* @return -* -* The resulting u32 value of the rotate right -* -* @note -* -* None. -* -*****************************************************************************/ -static u32 RotateRight(u32 Input, u8 Width) -{ - u32 Lsb; - u32 ReturnVal; - u32 WidthMask; - u32 MsbMask; - - /* - * set up the WidthMask and the MsbMask - */ - - MsbMask = 1 << (Width - 1); - - WidthMask = (MsbMask << 1) - 1; - - /* - * set the width of the Input to the correct width - */ - - Input = Input & WidthMask; - - ReturnVal = Input >> 1; - - Lsb = Input & 0x00000001; - - if (Lsb != 0x00000000) { - ReturnVal = ReturnVal | MsbMask; - } - - ReturnVal = ReturnVal & WidthMask; - - return (ReturnVal); - -} -#endif /* ROTATE_RIGHT */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xversion.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xversion.c deleted file mode 100644 index 1c79b5756e07ebd2cff98d4665d9781244b36488..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xversion.c +++ /dev/null @@ -1,344 +0,0 @@ -/* $Id: xversion.c,v 1.10 2007/05/07 14:29:23 wre Exp $ */ -/****************************************************************************** -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND -* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, -* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION -* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE. -* -* (c) Copyright 2002 Xilinx Inc. -* All rights reserved. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xversion.c -* -* This file contains the implementation of the XVersion component. This -* component represents a version ID. It is encapsulated within a component -* so that it's type and implementation can change without affecting users of -* it. -* -* The version is formatted as X.YYZ where X = 0 - 9, Y = 00 - 99, Z = a - z -* X is the major revision, YY is the minor revision, and Z is the -* compatability revision. -* -* Packed versions are also utilized for the configuration ROM such that -* memory is minimized. A packed version consumes only 16 bits and is -* formatted as follows. -* -* <pre> -* Revision Range Bit Positions -* -* Major Revision 0 - 9 Bits 15 - 12 -* Minor Revision 0 - 99 Bits 11 - 5 -* Compatability Revision a - z Bits 4 - 0 -* -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.00a xd 11/03/04 Improved support for doxygen. -</pre> -* -******************************************************************************/ - - -/***************************** Include Files *********************************/ - -#include "xbasic_types.h" -#include "xversion.h" - -/************************** Constant Definitions *****************************/ - -/* the following constants define the masks and shift values to allow the - * revisions to be packed and unpacked, a packed version is packed into a 16 - * bit value in the following format, XXXXYYYYYYYZZZZZ, where XXXX is the - * major revision, YYYYYYY is the minor revision, and ZZZZZ is the compatability - * revision - */ -#define XVE_MAJOR_SHIFT_VALUE 12 -#define XVE_MINOR_ONLY_MASK 0x0FE0 -#define XVE_MINOR_SHIFT_VALUE 5 -#define XVE_COMP_ONLY_MASK 0x001F - -/* the following constants define the specific characters of a version string - * for each character of the revision, a version string is in the following - * format, "X.YYZ" where X is the major revision (0 - 9), YY is the minor - * revision (00 - 99), and Z is the compatability revision (a - z) - */ -#define XVE_MAJOR_CHAR 0 /* major revision 0 - 9 */ -#define XVE_MINOR_TENS_CHAR 2 /* minor revision tens 0 - 9 */ -#define XVE_MINOR_ONES_CHAR 3 /* minor revision ones 0 - 9 */ -#define XVE_COMP_CHAR 4 /* compatability revision a - z */ -#define XVE_END_STRING_CHAR 5 - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - -static int IsVersionStringValid(char *StringPtr); - -/*****************************************************************************/ -/** -* -* Unpacks a packed version into the specified version. Versions are packed -* into the configuration ROM to reduce the amount storage. A packed version -* is a binary format as oppossed to a non-packed version which is implemented -* as a string. -* -* @param InstancePtr points to the version to unpack the packed version into. -* @param PackedVersion contains the packed version to unpack. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XVersion_UnPack(XVersion *InstancePtr, u16 PackedVersion) -{ - (void) InstancePtr; - (void) PackedVersion; - /* not implemented yet since CROM related */ -} - -/*****************************************************************************/ -/** -* -* Packs a version into the specified packed version. Versions are packed into -* the configuration ROM to reduce the amount storage. -* -* @param InstancePtr points to the version to pack. -* @param PackedVersionPtr points to the packed version which will receive -* the new packed version. -* -* @return -* -* A status, XST_SUCCESS, indicating the packing was accomplished -* successfully, or an error, XST_INVALID_VERSION, indicating the specified -* input version was not valid such that the pack did not occur -* <br><br> -* The packed version pointed to by PackedVersionPtr is modified with the new -* packed version if the status indicates success. -* -* @note -* -* None. -* -******************************************************************************/ -int XVersion_Pack(XVersion *InstancePtr, u16 *PackedVersionPtr) -{ - /* not implemented yet since CROM related */ - (void) InstancePtr; - (void) PackedVersionPtr; - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* Determines if two versions are equal. -* -* @param InstancePtr points to the first version to be compared. -* @param VersionPtr points to a second version to be compared. -* -* @return -* -* TRUE if the versions are equal, FALSE otherwise. -* -* @note -* -* None. -* -******************************************************************************/ -int XVersion_IsEqual(XVersion *InstancePtr, XVersion *VersionPtr) -{ - u8 *Version1 = (u8 *) InstancePtr; - u8 *Version2 = (u8 *) VersionPtr; - u32 Index; - - /* assert to verify input arguments */ - - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(VersionPtr != NULL); - - /* check each byte of the versions to see if they are the same, - * return at any point a byte differs between them - */ - for (Index = 0; Index < sizeof(XVersion); Index++) { - if (Version1[Index] != Version2[Index]) { - return FALSE; - } - } - - /* No byte was found to be different between the versions, so indicate - * the versions are equal - */ - return TRUE; -} - -/*****************************************************************************/ -/** -* -* Converts a version to a null terminated string. -* -* @param InstancePtr points to the version to convert. -* @param StringPtr points to the string which will be the result of the -* conversion. This does not need to point to a null terminated -* string as an input, but must point to storage which is an adequate -* amount to hold the result string. -* -* @return -* -* The null terminated string is inserted at the location pointed to by -* StringPtr if the status indicates success. -* -* @note -* -* It is necessary for the caller to have already allocated the storage to -* contain the string. The amount of memory necessary for the string is -* specified in the version header file. -* -******************************************************************************/ -void XVersion_ToString(XVersion *InstancePtr, char *StringPtr) -{ - /* assert to verify input arguments */ - - XASSERT_VOID(InstancePtr != NULL); - XASSERT_VOID(StringPtr != NULL); - - /* since version is implemented as a string, just copy the specified - * input into the specified output - */ - XVersion_Copy(InstancePtr, (XVersion *) StringPtr); -} - -/*****************************************************************************/ -/** -* -* Initializes a version from a null terminated string. Since the string may not -* be a format which is compatible with the version, an error could occur. -* -* @param InstancePtr points to the version which is to be initialized. -* @param StringPtr points to a null terminated string which will be -* converted to a version. The format of the string must match the -* version string format which is X.YYX where X = 0 - 9, YY = 00 - 99, -* Z = a - z. -* -* @return -* -* A status, XST_SUCCESS, indicating the conversion was accomplished -* successfully, or XST_INVALID_VERSION indicating the version string format -* was not valid. -* -* @note -* -* None. -* -******************************************************************************/ -int XVersion_FromString(XVersion *InstancePtr, char *StringPtr) -{ - /* assert to verify input arguments */ - - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(StringPtr != NULL); - - /* if the version string specified is not valid, return an error */ - - if (!IsVersionStringValid(StringPtr)) { - return XST_INVALID_VERSION; - } - - /* copy the specified string into the specified version and indicate the - * conversion was successful - */ - XVersion_Copy((XVersion *) StringPtr, InstancePtr); - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* Copies the contents of a version to another version. -* -* @param InstancePtr points to the version which is the source of data for -* the copy operation. -* @param VersionPtr points to another version which is the destination of -* the copy operation. -* -* @return -* -* None. -* -* @note -* -* None. -* -******************************************************************************/ -void XVersion_Copy(XVersion *InstancePtr, XVersion *VersionPtr) -{ - u8 *Source = (u8 *) InstancePtr; - u8 *Destination = (u8 *) VersionPtr; - u32 Index; - - /* assert to verify input arguments */ - - XASSERT_VOID(InstancePtr != NULL); - XASSERT_VOID(VersionPtr != NULL); - - /* copy each byte of the source version to the destination version */ - - for (Index = 0; Index < sizeof(XVersion); Index++) { - Destination[Index] = Source[Index]; - } -} - -/*****************************************************************************/ -/** -* -* Determines if the specified version is valid. -* -* @param StringPtr points to the string to be validated. -* -* @return -* -* TRUE if the version string is a valid format, FALSE otherwise. -* -* @note -* -* None. -* -******************************************************************************/ -static int IsVersionStringValid(char *StringPtr) -{ - /* if the input string is not a valid format, "X.YYZ" where X = 0 - 9, - * YY = 00 - 99, and Z = a - z, then indicate it's not valid - */ - if ((StringPtr[XVE_MAJOR_CHAR] < '0') || - (StringPtr[XVE_MAJOR_CHAR] > '9') || - (StringPtr[XVE_MINOR_TENS_CHAR] < '0') || - (StringPtr[XVE_MINOR_TENS_CHAR] > '9') || - (StringPtr[XVE_MINOR_ONES_CHAR] < '0') || - (StringPtr[XVE_MINOR_ONES_CHAR] > '9') || - (StringPtr[XVE_COMP_CHAR] < 'a') || - (StringPtr[XVE_COMP_CHAR] > 'z')) { - return FALSE; - } - - return TRUE; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xversion.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xversion.h deleted file mode 100644 index 3a14716f095b879611076aabadc06cba0892424c..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/common_v1_00_a/src/xversion.h +++ /dev/null @@ -1,98 +0,0 @@ -/* $Id: xversion.h,v 1.9 2007/05/07 14:29:23 wre Exp $ */ -/****************************************************************************** -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND -* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, -* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION -* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE. -* -* (c) Copyright 2002 Xilinx Inc. -* All rights reserved. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* @file xversion.h -* -* This file contains the interface for the XVersion component. This -* component represents a version ID. It is encapsulated within a component -* so that it's type and implementation can change without affecting users of -* it. -* -* The version is formatted as X.YYZ where X = 0 - 9, Y = 00 - 99, Z = a - z -* X is the major revision, YY is the minor revision, and Z is the -* compatability revision. -* -* Packed versions are also utilized for the configuration ROM such that -* memory is minimized. A packed version consumes only 16 bits and is -* formatted as follows. -* -* <pre> -* Revision Range Bit Positions -* -* Major Revision 0 - 9 Bits 15 - 12 -* Minor Revision 0 - 99 Bits 11 - 5 -* Compatability Revision a - z Bits 4 - 0 -* -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.00a xd 11/03/04 Improved support for doxygen. -* </pre> -* -******************************************************************************/ - -#ifndef XVERSION_H /* prevent circular inclusions */ -#define XVERSION_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xbasic_types.h" -#include "xstatus.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - -/* the following data type is used to hold a null terminated version string - * consisting of the following format, "X.YYX" - */ -typedef char XVersion[6]; - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - -void XVersion_UnPack(XVersion *InstancePtr, u16 PackedVersion); - -int XVersion_Pack(XVersion *InstancePtr, u16 *PackedVersion); - -int XVersion_IsEqual(XVersion *InstancePtr, XVersion *VersionPtr); - -void XVersion_ToString(XVersion *InstancePtr, char *StringPtr); - -int XVersion_FromString(XVersion *InstancePtr, char *StringPtr); - -void XVersion_Copy(XVersion *InstancePtr, XVersion *VersionPtr); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v1_01_a/src/Makefile b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v1_01_a/src/Makefile deleted file mode 100644 index 77363c67c0ab74ef0be6b490d8bdcd638601b8dc..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v1_01_a/src/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -COMPILER= -ARCHIVER= -CP=cp -COMPILER_FLAGS= -EXTRA_COMPILER_FLAGS= -LIB=libxil.a - -RELEASEDIR=../../../lib -INCLUDEDIR=../../../include -INCLUDES=-I${INCLUDEDIR} - -OUTS = *.o - -LIBSOURCES=*.c -INCLUDEFILES=*.h - -libs: - echo "Compiling cpu_cortexa9" - -.PHONY: include -include: - ${CP} $(INCLUDEFILES) $(INCLUDEDIR) - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v1_01_a/src/xcpu_cortexa9.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v1_01_a/src/xcpu_cortexa9.h deleted file mode 100644 index 0933143a44a91ebe1715c5b6f129ad3ea1df1be2..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v1_01_a/src/xcpu_cortexa9.h +++ /dev/null @@ -1,49 +0,0 @@ -/* $Id: xcpu_cortexa9.h,v 1.1.2.1 2011/02/11 09:30:37 kkatna Exp $ */ -/****************************************************************************** -* -* (c) Copyright 2011 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xcpu_cortexa9.h -* -* dummy file -* -******************************************************************************/ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v2_04_a/src/Makefile b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v2_04_a/src/Makefile deleted file mode 100644 index 2b569563c543a5ee0d33ea849f961b7dc6ee0706..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v2_04_a/src/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -COMPILER= -ARCHIVER= -CP=cp -COMPILER_FLAGS= -EXTRA_COMPILER_FLAGS= -LIB=libxil.a - -CC_FLAGS = $(COMPILER_FLAGS) -ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) - -RELEASEDIR=../../../lib -INCLUDEDIR=../../../include -INCLUDES=-I./. -I${INCLUDEDIR} - -OUTS = *.o - -LIBSOURCES:=*.c -INCLUDEFILES:=*.h - -OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) - -libs: banner xdevcfg_libs clean - -%.o: %.c - ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< - -banner: - echo "Compiling devcfg" - -xdevcfg_libs: ${OBJECTS} - $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} - -.PHONY: include -include: xdevcfg_includes - -xdevcfg_includes: - ${CP} ${INCLUDEFILES} ${INCLUDEDIR} - -clean: - rm -rf ${OBJECTS} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v2_04_a/src/xdevcfg.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v2_04_a/src/xdevcfg.c deleted file mode 100644 index f2f61d020caf65ab9deb79acbc1354335ce4d183..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v2_04_a/src/xdevcfg.c +++ /dev/null @@ -1,909 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file xdevcfg.c -* -* This file contains the implementation of the interface functions for XDcfg -* driver. Refer to the header file xdevcfg.h for more detailed information. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- --------------------------------------------- -* 1.00a hvm 02/07/11 First release -* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for -* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer -* APIs is words (32 bit) and not bytes. -* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs -* to add information that 2 LSBs of the Source/Destination -* address when equal to 2’b01 indicate the last DMA command -* of an overall transfer. -* Updated the XDcfg_Transfer function to use the -* Destination Address passed to this API for secure transfers -* instead of using 0xFFFFFFFF for CR 662197. This issue was -* resulting in the failure of secure transfers of -* non-bitstream images. -* 2.01a nm 08/27/12 Updated the XDcfg_Transfer API to clear the -* QUARTER_PCAP_RATE_EN bit in the control register for -* non secure writes for CR 675543. -* 2.02a nm 01/31/13 Fixed CR# 679335. -* Added Setting and Clearing the internal PCAP loopback. -* Removed code for enabling/disabling AES engine as BootROM -* locks down this setting. -* Fixed CR# 681976. -* Skip Checking the PCFG_INIT in case of non-secure DMA -* loopback. -* Fixed CR# 699558. -* XDcfg_Transfer fails to transfer data in loopback mode. -* 2.03a nm 04/19/13 Fixed CR# 703728. -* Updated the register definitions as per the latest TRM -* version UG585 (v1.4) November 16, 2012. -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xdevcfg.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/************************** Variable Definitions *****************************/ - -/****************************************************************************/ -/** -* -* Initialize the Device Config Interface driver. This function -* must be called before other functions of the driver are called. -* -* @param InstancePtr is a pointer to the XDcfg instance. -* @param ConfigPtr is the config structure. -* @param EffectiveAddress is the base address for the device. It could be -* a virtual address if address translation is supported in the -* system, otherwise it is the physical address. -* -* @return -* - XST_SUCCESS if initialization was successful. -* - XST_DEVICE_IS_STARTED if the device has already been started. -* -* @note The very first APB access to the Device Configuration Interface -* block needs to be a write to the UNLOCK register with the value -* of 0x757BDF0D. This step is to be done once after reset, any -* other APB access has to come after this. The APB access is -* considered illegal if the step is not done or if it is done -* incorrectly. Furthermore, if any of efuse_sec_cfg[5:0] is high, -* the following additional actions would be carried out. -* In other words, if all bits are low, the following steps are not -* done. -* 1. AES is disabled -* 2. All APB writes disabled -* 3. SoC debug fully enabled -* -******************************************************************************/ -int XDcfg_CfgInitialize(XDcfg *InstancePtr, - XDcfg_Config *ConfigPtr, u32 EffectiveAddress) -{ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(ConfigPtr != NULL); - - /* - * If the device is started, disallow the initialize and return a - * status indicating it is started. This allows the user to stop the - * device and reinitialize, but prevents a user from inadvertently - * initializing. - */ - if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) { - return XST_DEVICE_IS_STARTED; - } - - /* - * Copy configuration into instance. - */ - InstancePtr->Config.DeviceId = ConfigPtr->DeviceId; - - /* - * Save the base address pointer such that the registers of the block - * can be accessed and indicate it has not been started yet. - */ - InstancePtr->Config.BaseAddr = EffectiveAddress; - InstancePtr->IsStarted = 0; - - - /* Unlock the Device Configuration Interface */ - XDcfg_Unlock(InstancePtr); - - /* - * Indicate the instance is ready to use, successfully initialized. - */ - InstancePtr->IsReady = XIL_COMPONENT_IS_READY; - - return XST_SUCCESS; -} - -/****************************************************************************/ -/** -* -* The functions enables the PCAP interface by setting the PCAP mode bit in the -* control register. -* -* @param InstancePtr is a pointer to the XDcfg instance. -* -* @return None. -* -* @note Enable FPGA programming from PCAP interface. Enabling this bit -* disables all the external interfaces from programming of FPGA -* except for ICAP. The user needs to ensure that the FPGA is -* programmed through either PCAP or ICAP. -* -*****************************************************************************/ -void XDcfg_EnablePCAP(XDcfg *InstancePtr) -{ - u32 CtrlReg; - /* - * Assert the arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - - CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, - XDCFG_CTRL_OFFSET); - - XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, - (CtrlReg | XDCFG_CTRL_PCAP_MODE_MASK)); - -} - -/****************************************************************************/ -/** -* -* The functions disables the PCAP interface by clearing the PCAP mode bit in -* the control register. -* -* @param InstancePtr is a pointer to the XDcfg instance. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XDcfg_DisablePCAP(XDcfg *InstancePtr) -{ - u32 CtrlReg; - /* - * Assert the arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - - CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, - XDCFG_CTRL_OFFSET); - - XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, - (CtrlReg & ( ~XDCFG_CTRL_PCAP_MODE_MASK))); - -} - -/****************************************************************************/ -/** -* -* The function sets the contents of the Control Register. -* -* @param InstancePtr is a pointer to the XDcfg instance. -* @param Mask is the 32 bit mask data to be written to the Register. -* The mask definitions are defined in the xdevcfg_hw.h file. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask) -{ - u32 CtrlReg; - /* - * Assert the arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - - CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, - XDCFG_CTRL_OFFSET); - - XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, - (CtrlReg | Mask)); - -} - -/****************************************************************************/ -/** -* -* The function reads the contents of the Control Register. -* -* @param InstancePtr is a pointer to the XDcfg instance. -* -* @return A 32-bit value representing the contents of the Control -* Register. -* Use the XDCFG_CTRL_*_MASK constants defined in xdevcfg_hw.h to -* interpret the returned value. -* -* @note None. -* -*****************************************************************************/ -u32 XDcfg_GetControlRegister(XDcfg *InstancePtr) -{ - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the Control Register and return the value. - */ - return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET); -} - -/****************************************************************************/ -/** -* -* The function sets the contents of the Lock Register. These bits -* can only be set to a 1. They will be cleared after a Power On Reset. -* -* @param InstancePtr is a pointer to the XDcfg instance. -* @param Data is the 32 bit data to be written to the Register. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data) -{ - /* - * Assert the arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET, Data); - -} - -/****************************************************************************/ -/** -* -* The function reads the contents of the Lock Register. -* -* @param InstancePtr is a pointer to the XDcfg instance. -* -* @return A 32-bit value representing the contents of the Lock -* Register. -* Use the XDCFG_CR_*_MASK constants defined in xdevcfg_hw.h to -* interpret the returned value. -* -* @note None. -* -*****************************************************************************/ -u32 XDcfg_GetLockRegister(XDcfg *InstancePtr) -{ - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the Lock Register and return the value. - */ - return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET); -} - -/****************************************************************************/ -/** -* -* The function sets the contents of the Configuration Register with the -* given value. -* -* @param InstancePtr is a pointer to the XDcfg instance. -* @param Data is the 32 bit data to be written to the Register. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data) -{ - /* - * Assert the arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET, Data); - -} - -/****************************************************************************/ -/** -* -* The function reads the contents of the Configuration Register with the -* given value. -* -* @param InstancePtr is a pointer to the XDcfg instance. -* -* @return A 32-bit value representing the contents of the Config -* Register. -* Use the XDCFG_CFG_*_MASK constants defined in xdevcfg_hw.h to -* interpret the returned value. -* -* @note None. -* -*****************************************************************************/ -u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr) -{ - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET); - -} - -/****************************************************************************/ -/** -* -* The function sets the contents of the Status Register. -* -* @param InstancePtr is a pointer to the XDcfg instance. -* @param Data is the 32 bit data to be written to the Register. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data) -{ - /* - * Assert the arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET, Data); - -} - -/****************************************************************************/ -/** -* -* The function reads the contents of the Status Register. -* -* @param InstancePtr is a pointer to the XDcfg instance. -* -* @return A 32-bit value representing the contents of the Status -* Register. -* Use the XDCFG_STATUS_*_MASK constants defined in -* xdevcfg_hw.h to interpret the returned value. -* -* @note None. -* -*****************************************************************************/ -u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr) -{ - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the Status Register and return the value. - */ - return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET); -} - -/****************************************************************************/ -/** -* -* The function sets the contents of the ROM Shadow Control Register. -* -* @param InstancePtr is a pointer to the XDcfg instance. -* @param Data is the 32 bit data to be written to the Register. -* -* @return None. -* -* @note This register is can only be written and is used to control the -* RAM shadow of 32 bit 4K page ROM pages in user mode -* -*****************************************************************************/ -void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data) -{ - /* - * Assert the arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_ROM_SHADOW_OFFSET, - Data); - -} - -/****************************************************************************/ -/** -* -* The function reads the contents of the Software ID Register. -* -* @param InstancePtr is a pointer to the XDcfg instance. -* -* @return 32 Bit boot software ID. -* -* @note This register is locked for write once the system enters -* usermode. Hence API for reading the register only is provided. -* -*****************************************************************************/ -u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr) -{ - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the Software ID Register and return the value. - */ - return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_SW_ID_OFFSET); -} - -/****************************************************************************/ -/** -* -* The function sets the bit mask for the feature in Miscellaneous Control -* Register. -* -* @param InstancePtr is a pointer to the XDcfg instance. -* @param Mask is the bit-mask of the feature to be set. -* -* @return None. -* -* @note None -* -*****************************************************************************/ -void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask) -{ - u32 RegData; - - /* - * Assert the arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - - RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, - XDCFG_MCTRL_OFFSET); - - XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET, - (RegData | Mask)); -} - -/****************************************************************************/ -/** -* -* The function reads the contents of the Miscellaneous Control Register. -* -* @param InstancePtr is a pointer to the XDcfg instance. -* -* @return 32 Bit boot software ID. -* -* @note This register is locked for write once the system enters -* usermode. Hence API to reading the register only is provided. -* -*****************************************************************************/ -u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr) -{ - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the Miscellaneous Control Register and return the value. - */ - return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET); -} - -/******************************************************************************/ -/** -* -* This function checks if DMA command queue is full. -* -* @param InstancePtr is a pointer to the XDcfg instance. -* -* @return XST_SUCCESS is the DMA is busy -* XST_FAILURE if the DMA is idle -* -* @note The DMA queue has a depth of two. -* -****************************************************************************/ -u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr) -{ - - u32 RegData; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* Read the PCAP status register for DMA status */ - RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, - XDCFG_STATUS_OFFSET); - - if ((RegData & XDCFG_STATUS_DMA_CMD_Q_F_MASK) == - XDCFG_STATUS_DMA_CMD_Q_F_MASK){ - return XST_SUCCESS; - } - - return XST_FAILURE; -} - -/******************************************************************************/ -/** -* -* This function initiates the DMA transfer. -* -* @param InstancePtr is a pointer to the XDcfg instance. -* @param SourcePtr contains a pointer to the source memory where the data -* is to be transferred from. -* @param SrcWordLength is the number of words (32 bit) to be transferred -* for the source transfer. -* @param DestPtr contains a pointer to the destination memory -* where the data is to be transferred to. -* @param DestWordLength is the number of words (32 bit) to be transferred -* for the Destination transfer. -* -* @return None. -* -* @note It is the responsibility of the caller function to ensure that -* correct values are passed to this function. -* -* The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination) -* address when equal to 2’b01 indicates the last DMA command of -* an overall transfer. -* -****************************************************************************/ -void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr, - u32 SrcWordLength, u32 DestWordLength) -{ - - XDcfg_WriteReg(InstancePtr->Config.BaseAddr, - XDCFG_DMA_SRC_ADDR_OFFSET, - SourcePtr); - - XDcfg_WriteReg(InstancePtr->Config.BaseAddr, - XDCFG_DMA_DEST_ADDR_OFFSET, - DestPtr); - - XDcfg_WriteReg(InstancePtr->Config.BaseAddr, - XDCFG_DMA_SRC_LEN_OFFSET, - SrcWordLength); - - XDcfg_WriteReg(InstancePtr->Config.BaseAddr, - XDCFG_DMA_DEST_LEN_OFFSET, - DestWordLength); -} - -/******************************************************************************/ -/** -* -* This function Implements the DMA Read Command. This command is used to -* transfer the image data from FPGA to the external memory. -* -* @param InstancePtr is a pointer to the XDcfg instance. -* @param SourcePtr contains a pointer to the source memory where the data -* is to be transferred from. -* @param SrcWordLength is the number of words (32 bit) to be transferred -* for the source transfer. -* @param DestPtr contains a pointer to the destination memory -* where the data is to be transferred to. -* @param DestWordLength is the number of words (32 bit) to be transferred -* for the Destination transfer. -* -* @return - XST_INVALID_PARAM if source address/length is invalid. -* - XST_SUCCESS if DMA transfer initiated properly. -* -* @note None. -* -****************************************************************************/ -static u32 XDcfg_PcapReadback(XDcfg *InstancePtr, u32 SourcePtr, - u32 SrcWordLength, u32 DestPtr, - u32 DestWordLength) -{ - u32 IntrReg; - - /* - * Send READ Frame command to FPGA - */ - XDcfg_InitiateDma(InstancePtr, SourcePtr, XDCFG_DMA_INVALID_ADDRESS, - SrcWordLength, 0); - - /* - * Store the enabled interrupts to enable before the actual read - * transfer is initiated and Disable all the interrupts temporarily. - */ - IntrReg = XDcfg_IntrGetEnabled(InstancePtr); - XDcfg_IntrDisable(InstancePtr, XDCFG_IXR_ALL_MASK); - - /* - * Wait till you get the DMA done for the read command sent - */ - while ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr, - XDCFG_INT_STS_OFFSET) & - XDCFG_IXR_D_P_DONE_MASK) == - XDCFG_IXR_D_P_DONE_MASK); - /* - * Enable the previously stored Interrupts . - */ - XDcfg_IntrEnable(InstancePtr, IntrReg); - - /* - * Initiate the DMA write command. - */ - XDcfg_InitiateDma(InstancePtr, XDCFG_DMA_INVALID_ADDRESS, (u32)DestPtr, - 0, DestWordLength); - - return XST_SUCCESS; -} - - -/****************************************************************************/ -/** -* -* This function starts the DMA transfer. This function only starts the -* operation and returns before the operation may be completed. -* If the interrupt is enabled, an interrupt will be generated when the -* operation is completed, otherwise it is necessary to poll the Status register -* to determine when it is completed. It is the responsibility of the caller to -* determine when the operation is completed by handling the generated interrupt -* or polling the Status Register. -* -* @param InstancePtr is a pointer to the XDcfg instance. -* @param SourcePtr contains a pointer to the source memory where the data -* is to be transferred from. -* @param SrcWordLength is the number of words (32 bit) to be transferred -* for the source transfer. -* @param DestPtr contains a pointer to the destination memory -* where the data is to be transferred to. -* @param DestWordLength is the number of words (32 bit) to be transferred -* for the Destination transfer. -* @param TransferType contains the type of PCAP transfer being requested. -* The definitions can be found in the xdevcfg.h file. -* @return -* - XST_SUCCESS.if DMA transfer initiated successfully -* - XST_DEVICE_BUSY if DMA is busy -* - XST_INVALID_PARAM if invalid Source / Destination address -* is sent or an invalid Source / Destination length is -* sent -* -* @note It is the responsibility of the caller to ensure that the cache -* is flushed and invalidated both before the DMA operation is -* started and after the DMA operation completes if the memory -* pointed to is cached. The caller must also ensure that the -* pointers contain physical address rather than a virtual address -* if address translation is being used. -* -* The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination) -* address when equal to 2’b01 indicates the last DMA command of -* an overall transfer. -* -*****************************************************************************/ -u32 XDcfg_Transfer(XDcfg *InstancePtr, - void *SourcePtr, u32 SrcWordLength, - void *DestPtr, u32 DestWordLength, - u32 TransferType) -{ - - u32 CtrlReg; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - - if (XDcfg_IsDmaBusy(InstancePtr) == XST_SUCCESS) { - return XST_DEVICE_BUSY; - } - - /* - * Check whether the fabric is in initialized state - */ - if ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET) - & XDCFG_STATUS_PCFG_INIT_MASK) == 0) { - /* - * We don't need to check PCFG_INIT to be high for - * non-encrypted loopback transfers. - */ - if (TransferType != XDCFG_CONCURRENT_NONSEC_READ_WRITE) { - return XST_FAILURE; - } - } - - if ((TransferType == XDCFG_SECURE_PCAP_WRITE) || - (TransferType == XDCFG_NON_SECURE_PCAP_WRITE)) { - - /* Check for valid source pointer and length */ - if ((!SourcePtr) || (SrcWordLength == 0)) { - return XST_INVALID_PARAM; - } - - /* Clear internal PCAP loopback */ - CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, - XDCFG_MCTRL_OFFSET); - XDcfg_WriteReg(InstancePtr->Config.BaseAddr, - XDCFG_MCTRL_OFFSET, (CtrlReg & - ~(XDCFG_MCTRL_PCAP_LPBK_MASK))); - - if (TransferType == XDCFG_NON_SECURE_PCAP_WRITE) { - /* - * Clear QUARTER_PCAP_RATE_EN bit - * so that the PCAP data is transmitted every clock - */ - CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, - XDCFG_CTRL_OFFSET); - - XDcfg_WriteReg(InstancePtr->Config.BaseAddr, - XDCFG_CTRL_OFFSET, (CtrlReg & - ~XDCFG_CTRL_PCAP_RATE_EN_MASK)); - - } - if (TransferType == XDCFG_SECURE_PCAP_WRITE) { - /* - * AES engine handles only 8 bit data every clock cycle. - * Hence, Encrypted PCAP data which is 32 bit data can - * only be sent in every 4 clock cycles. Set the control - * register QUARTER_PCAP_RATE_EN bit to achieve this - * operation. - */ - XDcfg_SetControlRegister(InstancePtr, - XDCFG_CTRL_PCAP_RATE_EN_MASK); - } - - XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr, - (u32)DestPtr, SrcWordLength, DestWordLength); - - } - - if (TransferType == XDCFG_PCAP_READBACK) { - - if ((!DestPtr) || (DestWordLength == 0)) { - - return XST_INVALID_PARAM; - } - - /* Clear internal PCAP loopback */ - CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, - XDCFG_MCTRL_OFFSET); - XDcfg_WriteReg(InstancePtr->Config.BaseAddr, - XDCFG_MCTRL_OFFSET, (CtrlReg & - ~(XDCFG_MCTRL_PCAP_LPBK_MASK))); - - /* - * For PCAP readback of FPGA configuration register or memory, - * the read command is first sent (written) to the FPGA fabric - * which responds by returning the required read data. Read data - * from the FPGA is captured if pcap_radata_v is active.A DMA - * read transfer is required to obtain the readback command, - * which is then sent to the FPGA, followed by a DMA write - * transfer to support this mode of operation. - */ - return XDcfg_PcapReadback(InstancePtr, - (u32)SourcePtr, SrcWordLength, - (u32)DestPtr, DestWordLength); - } - - - if ((TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) || - (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE)) { - - if ((!SourcePtr) || (SrcWordLength == 0) || - (!DestPtr) || (DestWordLength == 0)) { - return XST_INVALID_PARAM; - } - - if (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE) { - /* Enable internal PCAP loopback */ - CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, - XDCFG_MCTRL_OFFSET); - XDcfg_WriteReg(InstancePtr->Config.BaseAddr, - XDCFG_MCTRL_OFFSET, (CtrlReg | - XDCFG_MCTRL_PCAP_LPBK_MASK)); - - /* - * Clear QUARTER_PCAP_RATE_EN bit - * so that the PCAP data is transmitted every clock - */ - CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, - XDCFG_CTRL_OFFSET); - - XDcfg_WriteReg(InstancePtr->Config.BaseAddr, - XDCFG_CTRL_OFFSET, (CtrlReg & - ~XDCFG_CTRL_PCAP_RATE_EN_MASK)); - - } - if (TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) { - /* Clear internal PCAP loopback */ - CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, - XDCFG_MCTRL_OFFSET); - XDcfg_WriteReg(InstancePtr->Config.BaseAddr, - XDCFG_MCTRL_OFFSET, (CtrlReg & - ~(XDCFG_MCTRL_PCAP_LPBK_MASK))); - - /* - * Set the QUARTER_PCAP_RATE_EN bit - * so that the PCAP data is transmitted every 4 clock - * cycles, this is required for encrypted data. - */ - XDcfg_SetControlRegister(InstancePtr, - XDCFG_CTRL_PCAP_RATE_EN_MASK); - } - - XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr, - (u32)DestPtr, SrcWordLength, DestWordLength); - } - - return XST_SUCCESS; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v2_04_a/src/xdevcfg.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v2_04_a/src/xdevcfg.h deleted file mode 100644 index 12483849643b144689b9e587b218cb4c79d47137..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v2_04_a/src/xdevcfg.h +++ /dev/null @@ -1,385 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file xdevcfg.h -* -* The is the main header file for the Device Configuration Interface of the Zynq -* device. The device configuration interface has three main functionality. -* 1. AXI-PCAP -* 2. Security Policy -* 3. XADC -* This current version of the driver supports only the AXI-PCAP and Security -* Policy blocks. There is a separate driver for XADC. -* -* AXI-PCAP is used for download/upload an encrypted or decrypted bitstream. -* DMA embedded in the AXI PCAP provides the master interface to -* the Device configuration block for any DMA transfers. The data transfer can -* take place between the Tx/RxFIFOs of AXI-PCAP and memory (on chip -* RAM/DDR/peripheral memory). -* -* The current driver only supports the downloading the FPGA bitstream and -* readback of the decrypted image (sort of loopback). -* The driver does not know what information needs to be written to the FPGA to -* readback FPGA configuration register or memory data. The application above the -* driver should take care of creating the data that needs to be downloaded to -* the FPGA so that the bitstream can be readback. -* This driver also does not support the reading of the internal registers of the -* PCAP. The driver has no knowledge of the PCAP internals. -* -* <b> Initialization and Configuration </b> -* -* The device driver enables higher layer software (e.g., an application) to -* communicate with the Device Configuration device. -* -* XDcfg_CfgInitialize() API is used to initialize the Device Configuration -* Interface. The user needs to first call the XDcfg_LookupConfig() API which -* returns the Configuration structure pointer which is passed as a parameter to -* the XDcfg_CfgInitialize() API. -* -* <b>Interrupts</b> -* The Driver implements an interrupt handler to support the interrupts provided -* by this interface. -* -* <b> Threads </b> -* -* This driver is not thread safe. Any needs for threads or thread mutual -* exclusion must be satisfied by the layer above this driver. -* -* <b> Asserts </b> -* -* Asserts are used within all Xilinx drivers to enforce constraints on argument -* values. Asserts can be turned off on a system-wide basis by defining, at -* compile time, the NDEBUG identifier. By default, asserts are turned on and it -* is recommended that users leave asserts on during development. -* -* <b> Building the driver </b> -* -* The XDcfg driver is composed of several source files. This allows the user -* to build and link only those parts of the driver that are necessary. -* -* <br><br> -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- --------------------------------------------- -* 1.00a hvm 02/07/11 First release -* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for -* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer -* APIs is words (32 bit) and not bytes. -* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs -* to add information that 2 LSBs of the Source/Destination -* address when equal to 2’b01 indicate the last DMA command -* of an overall transfer. -* Destination Address passed to this API for secure transfers -* instead of using 0xFFFFFFFF for CR 662197. This issue was -* resulting in the failure of secure transfers of -* non-bitstream images. -* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly -* set the mask instead of oring it with the -* value read from the interrupt status register -* Added defines for the PS Version bits, -* removed the FIFO Flush bits from the -* Miscellaneous Control Reg. -* Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface -* and XDcfg_SelectPcapInterface APIs for CR 643295 -* The user has to call the XDcfg_SelectIcapInterface API -* for the PL reconfiguration using AXI HwIcap. -* Updated the XDcfg_Transfer API to clear the -* QUARTER_PCAP_RATE_EN bit in the control register for -* non secure writes for CR 675543. -* 2.02a nm 01/31/13 Fixed CR# 679335. -* Added Setting and Clearing the internal PCAP loopback. -* Removed code for enabling/disabling AES engine as BootROM -* locks down this setting. -* Fixed CR# 681976. -* Skip Checking the PCFG_INIT in case of non-secure DMA -* loopback. -* Fixed CR# 699558. -* XDcfg_Transfer fails to transfer data in loopback mode. -* Fixed CR# 701348. -* Peripheral test fails with Running -* DcfgSelfTestExample() in SECURE bootmode. -* 2.03a nm 04/19/13 Fixed CR# 703728. -* Updated the register definitions as per the latest TRM -* version UG585 (v1.4) November 16, 2012. -* </pre> -* -******************************************************************************/ -#ifndef XDCFG_H /* prevent circular inclusions */ -#define XDCFG_H /* by using protection macros */ - -/***************************** Include Files *********************************/ - -#include "xdevcfg_hw.h" -#include "xstatus.h" -#include "xil_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/************************** Constant Definitions *****************************/ - -/* Types of PCAP transfers */ - -#define XDCFG_NON_SECURE_PCAP_WRITE 1 -#define XDCFG_SECURE_PCAP_WRITE 2 -#define XDCFG_PCAP_READBACK 3 -#define XDCFG_CONCURRENT_SECURE_READ_WRITE 4 -#define XDCFG_CONCURRENT_NONSEC_READ_WRITE 5 - - -/**************************** Type Definitions *******************************/ -/** -* The handler data type allows the user to define a callback function to -* respond to interrupt events in the system. This function is executed -* in interrupt context, so amount of processing should be minimized. -* -* @param CallBackRef is the callback reference passed in by the upper -* layer when setting the callback functions, and passed back to -* the upper layer when the callback is invoked. Its type is -* unimportant to the driver component, so it is a void pointer. -* @param Status is the Interrupt status of the XDcfg device. -*/ -typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status); - -/** - * This typedef contains configuration information for the device. - */ -typedef struct { - u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddr; /**< Base address of the device */ -} XDcfg_Config; - -/** - * The XDcfg driver instance data. - */ -typedef struct { - XDcfg_Config Config; /**< Hardware Configuration */ - u32 IsReady; /**< Device is initialized and ready */ - u32 IsStarted; /**< Device Configuration Interface - * is running - */ - XDcfg_IntrHandler StatusHandler; /* Event handler function */ - void *CallBackRef; /* Callback reference for event handler */ -} XDcfg; - -/****************************************************************************/ -/** -* -* Unlock the Device Config Interface block. -* -* @param InstancePtr is a pointer to the instance of XDcfg driver. -* -* @return None. -* -* @note C-style signature: -* void XDcfg_Unlock(XDcfg* InstancePtr) -* -*****************************************************************************/ -#define XDcfg_Unlock(InstancePtr) \ - XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \ - XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA) - - - -/****************************************************************************/ -/** -* -* Get the version number of the PS from the Miscellaneous Control Register. -* -* @param InstancePtr is a pointer to the instance of XDcfg driver. -* -* @return Version of the PS. -* -* @note C-style signature: -* void XDcfg_GetPsVersion(XDcfg* InstancePtr) -* -*****************************************************************************/ -#define XDcfg_GetPsVersion(InstancePtr) \ - ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \ - XDCFG_MCTRL_OFFSET)) & \ - XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \ - XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT - - - -/****************************************************************************/ -/** -* -* Read the multiboot config register value. -* -* @param InstancePtr is a pointer to the instance of XDcfg driver. -* -* @return None. -* -* @note C-style signature: -* u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr) -* -*****************************************************************************/ -#define XDcfg_ReadMultiBootConfig(InstancePtr) \ - XDcfg_ReadReg((InstancePtr)->Config.BaseAddr + \ - XDCFG_MULTIBOOT_ADDR_OFFSET) - - -/****************************************************************************/ -/** -* -* Selects ICAP interface for reconfiguration after the initial configuration -* of the PL. -* -* @param InstancePtr is a pointer to the instance of XDcfg driver. -* -* @return None. -* -* @note C-style signature: -* void XDcfg_SelectIcapInterface(XDcfg* InstancePtr) -* -*****************************************************************************/ -#define XDcfg_SelectIcapInterface(InstancePtr) \ - XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \ - ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \ - & ( ~XDCFG_CTRL_PCAP_PR_MASK))) - -/****************************************************************************/ -/** -* -* Selects PCAP interface for reconfiguration after the initial configuration -* of the PL. -* -* @param InstancePtr is a pointer to the instance of XDcfg driver. -* -* @return None. -* -* @note C-style signature: -* void XDcfg_SelectPcapInterface(XDcfg* InstancePtr) -* -*****************************************************************************/ -#define XDcfg_SelectPcapInterface(InstancePtr) \ - XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \ - ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \ - | XDCFG_CTRL_PCAP_PR_MASK)) - - - -/************************** Function Prototypes ******************************/ - -/* - * Lookup configuration in xdevcfg_sinit.c. - */ -XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId); - -/* - * Selftest function in xdevcfg_selftest.c - */ -int XDcfg_SelfTest(XDcfg *InstancePtr); - -/* - * Interface functions in xdevcfg.c - */ -int XDcfg_CfgInitialize(XDcfg *InstancePtr, - XDcfg_Config *ConfigPtr, u32 EffectiveAddress); - -void XDcfg_EnablePCAP(XDcfg *InstancePtr); - -void XDcfg_DisablePCAP(XDcfg *InstancePtr); - -void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask); - -u32 XDcfg_GetControlRegister(XDcfg *InstancePtr); - -void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data); - -u32 XDcfg_GetLockRegister(XDcfg *InstancePtr); - -void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data); - -u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr); - -void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data); - -u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr); - -void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data); - -u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr); - -void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask); - -u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr); - -u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr); - -void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr, - u32 SrcWordLength, u32 DestWordLength); - -u32 XDcfg_Transfer(XDcfg *InstancePtr, - void *SourcePtr, u32 SrcWordLength, - void *DestPtr, u32 DestWordLength, - u32 TransferType); - -/* - * Interrupt related function prototypes implemented in xdevcfg_intr.c - */ -void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask); - -void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask); - -u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr); - -u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr); - -void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask); - -void XDcfg_InterruptHandler(XDcfg *InstancePtr); - -void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc, - void *CallBackRef); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v2_04_a/src/xdevcfg_g.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v2_04_a/src/xdevcfg_g.c deleted file mode 100644 index d7fddc45526f96270a5bd17855039c97a3649e67..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v2_04_a/src/xdevcfg_g.c +++ /dev/null @@ -1,30 +0,0 @@ - -/******************************************************************* -* -* CAUTION: This file is automatically generated by libgen. -* Version: Xilinx EDK 14.7 EDK_P.20131013 -* DO NOT EDIT. -* -* Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. - -* -* Description: Driver configuration -* -*******************************************************************/ - -#include "xparameters.h" -#include "xdevcfg.h" - -/* -* The configuration table for devices -*/ - -XDcfg_Config XDcfg_ConfigTable[] = -{ - { - XPAR_PS7_DEV_CFG_0_DEVICE_ID, - XPAR_PS7_DEV_CFG_0_BASEADDR - } -}; - - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v2_04_a/src/xdevcfg_hw.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v2_04_a/src/xdevcfg_hw.c deleted file mode 100644 index f2422215477f8dfe00b55c90f433e6cd25d89b23..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v2_04_a/src/xdevcfg_hw.c +++ /dev/null @@ -1,119 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file xdevcfg_hw.c -* -* This file contains the implementation of the interface reset functionality -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- --------------------------------------------- -* 2.04a kpc 10/07/13 First release -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xdevcfg_hw.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/************************** Variable Definitions *****************************/ - -/*****************************************************************************/ -/** -* This function perform the reset sequence to the given devcfg interface by -* configuring the appropriate control bits in the devcfg specifc registers -* the devcfg reset squence involves the following steps -* Disable all the interuupts -* Clear the status -* Update relevant config registers with reset values -* Disbale the looopback mode and pcap rate enable -* -* @param BaseAddress of the interface -* -* @return N/A -* -* @note -* This function will not modify the slcr registers that are relavant for -* devcfg controller -******************************************************************************/ -void XDcfg_ResetHw(u32 BaseAddr) -{ - u32 Regval = 0; - - /* Mask the interrupts */ - XDcfg_WriteReg(BaseAddr, XDCFG_INT_MASK_OFFSET, - XDCFG_IXR_ALL_MASK); - /* Clear the interuupt status */ - Regval = XDcfg_ReadReg(BaseAddr, XDCFG_INT_STS_OFFSET); - XDcfg_WriteReg(BaseAddr, XDCFG_INT_STS_OFFSET, Regval); - /* Clear the source address register */ - XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_ADDR_OFFSET, 0x0); - /* Clear the destination address register */ - XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_ADDR_OFFSET, 0x0); - /* Clear the source length register */ - XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_LEN_OFFSET, 0x0); - /* Clear the destination length register */ - XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_LEN_OFFSET, 0x0); - /* Clear the loopback enable bit */ - Regval = XDcfg_ReadReg(BaseAddr, XDCFG_MCTRL_OFFSET); - Regval = Regval & ~XDCFG_MCTRL_PCAP_LPBK_MASK; - XDcfg_WriteReg(BaseAddr, XDCFG_MCTRL_OFFSET, Regval); - /*Reset the configuration register to reset value */ - XDcfg_WriteReg(BaseAddr, XDCFG_CFG_OFFSET, - XDCFG_CONFIG_RESET_VALUE); - /*Disable the PCAP rate enable bit */ - Regval = XDcfg_ReadReg(BaseAddr, XDCFG_CTRL_OFFSET); - Regval = Regval & ~XDCFG_CTRL_PCAP_RATE_EN_MASK; - XDcfg_WriteReg(BaseAddr, XDCFG_CTRL_OFFSET, Regval); - -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v2_04_a/src/xdevcfg_hw.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v2_04_a/src/xdevcfg_hw.h deleted file mode 100644 index ccac60abb236e8f028cc7ee68b8042ca44cc6ca0..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v2_04_a/src/xdevcfg_hw.h +++ /dev/null @@ -1,400 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file xdevcfg_hw.h -* -* This file contains the hardware interface to the Device Config Interface. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- --------------------------------------------- -* 1.00a hvm 02/07/11 First release -* 2.01a nm 08/01/12 Added defines for the PS Version bits, -* removed the FIFO Flush bits from the -* Miscellaneous Control Reg -* 2.03a nm 04/19/13 Fixed CR# 703728. -* Updated the register definitions as per the latest TRM -* version UG585 (v1.4) November 16, 2012. -* 2.04a kpc 10/07/13 Added function prototype. -* </pre> -* -******************************************************************************/ -#ifndef XDCFG_HW_H /* prevent circular inclusions */ -#define XDCFG_HW_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_io.h" - -/************************** Constant Definitions *****************************/ - -/** @name Register Map - * Offsets of registers from the start of the device - * @{ - */ - -#define XDCFG_CTRL_OFFSET 0x00 /**< Control Register */ -#define XDCFG_LOCK_OFFSET 0x04 /**< Lock Register */ -#define XDCFG_CFG_OFFSET 0x08 /**< Configuration Register */ -#define XDCFG_INT_STS_OFFSET 0x0C /**< Interrupt Status Register */ -#define XDCFG_INT_MASK_OFFSET 0x10 /**< Interrupt Mask Register */ -#define XDCFG_STATUS_OFFSET 0x14 /**< Status Register */ -#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**< DMA Source Address Register */ -#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**< DMA Destination Address Reg */ -#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**< DMA Source Transfer Length */ -#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**< DMA Destination Transfer */ -#define XDCFG_ROM_SHADOW_OFFSET 0x28 /**< DMA ROM Shadow Register */ -#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**< Multi BootAddress Pointer */ -#define XDCFG_SW_ID_OFFSET 0x30 /**< Software ID Register */ -#define XDCFG_UNLOCK_OFFSET 0x34 /**< Unlock Register */ -#define XDCFG_MCTRL_OFFSET 0x80 /**< Miscellaneous Control Reg */ - -/* @} */ - -/** @name Control Register Bit definitions - * @{ - */ - -#define XDCFG_CTRL_FORCE_RST_MASK 0x80000000 /**< Force into - * Secure Reset - */ -#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /**< Program signal to - * Reset FPGA - */ -#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */ -#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /**< Enable PCAP for PR */ -#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /**< Enable PCAP */ -#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /**< Enable PCAP send data - * to FPGA every 4 PCAP - * cycles - */ -#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000 /**< Multiboot Enable */ -#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000 /**< JTAG Chain Disable */ -#define XDCFG_CTRL_USER_MODE_MASK 0x00008000 /**< User Mode Mask */ -#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000 /**< AES key source */ -#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**< AES Enable Mask */ -#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /**< SEU Enable Mask */ -#define XDCFG_CTRL_SEC_EN_MASK 0x00000080 /**< Secure/Non Secure - * Status mask - */ -#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /**< Secure Non Invasive - * Debug Enable - */ -#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /**< Secure Invasive - * Debug Enable - */ -#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /**< Non-Invasive Debug - * Enable - */ -#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /**< Invasive Debug - * Enable - */ -#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /**< DAP Enable Mask */ - -/* @} */ - -/** @name Lock register bit definitions - * @{ - */ - -#define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010 /**< Lock AES Efuse bit */ -#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /**< Lock AES_EN update */ -#define XDCFG_LOCK_SEU_MASK 0x00000004 /**< Lock SEU_En update */ -#define XDCFG_LOCK_SEC_MASK 0x00000002 /**< Lock SEC_EN and - * USER_MODE - */ -#define XDCFG_LOCK_DBG_MASK 0x00000001 /**< This bit locks - * security config - * including: DAP_En, - * DBGEN,, - * NIDEN, SPNIEN - */ -/*@}*/ - - - -/** @name Config Register Bit definitions - * @{ - */ -#define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00 /**< Read FIFO - * Threshold Mask - */ -#define XDCFG_CFG_WFIFO_TH_MASK 0x00000300 /**< Write FIFO Threshold - * Mask - */ -#define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080 /**< Read data active - * clock edge - */ -#define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040 /**< Write data active - * clock edge - */ -#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020 /**< Disable Source address - * increment mask - */ -#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010 /**< Disable Destination - * address increment - * mask - */ -/* @} */ - - -/** @name Interrupt Status/Mask Register Bit definitions - * @{ - */ -#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000 /**< Tri-state IO during - * HIZ - */ -#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000 /**< First configuration - * done - */ -#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000 /**< Global power down */ -#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000 /**< Tri-state IO during - * configuration - */ -#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000 /**< PL configuration - * reset - */ -#define XDCFG_IXR_AXI_WTO_MASK 0x00800000 /**< AXI Write Address - * or Data or response - * timeout - */ -#define XDCFG_IXR_AXI_WERR_MASK 0x00400000 /**< AXI Write response - * error - */ -#define XDCFG_IXR_AXI_RTO_MASK 0x00200000 /**< AXI Read Address or - * response timeout - */ -#define XDCFG_IXR_AXI_RERR_MASK 0x00100000 /**< AXI Read response - * error - */ -#define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000 /**< Rx FIFO Overflow */ -#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000 /**< Tx FIFO less than - * threshold */ -#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000 /**< Rx FIFO greater than - * threshold */ -#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000 /**< Illegal DMA command */ -#define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000 /**< DMA command queue - * overflow - */ -#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /**< DMA Command Done */ -#define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /**< DMA and PCAP - * transfers Done - */ -#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800 /**< PCAP to DMA transfer - * length error - */ -#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040 /**< HMAC error mask */ -#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020 /**< SEU Error mask */ -#define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010 /**< FPGA POR mask */ -#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008 /**< FPGA Reset mask */ -#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /**< Done Signal Mask */ -#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002 /**< Detect Positive edge - * of Init Signal - */ -#define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001 /**< Detect Negative edge - * of Init Signal - */ -#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \ - XDCFG_IXR_AXI_WERR_MASK | \ - XDCFG_IXR_AXI_RTO_MASK | \ - XDCFG_IXR_AXI_RERR_MASK | \ - XDCFG_IXR_RX_FIFO_OV_MASK | \ - XDCFG_IXR_DMA_CMD_ERR_MASK |\ - XDCFG_IXR_DMA_Q_OV_MASK | \ - XDCFG_IXR_P2D_LEN_ERR_MASK |\ - XDCFG_IXR_PCFG_HMAC_ERR_MASK) - - -#define XDCFG_IXR_ALL_MASK 0x00F7F8EF - - - -/* @} */ - - -/** @name Status Register Bit definitions - * @{ - */ -#define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000 /**< DMA command - * Queue full - */ -#define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000 /**< DMA command - * Queue empty - */ -#define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 /**< Number of - * completed DMA - * transfers - */ -#define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000 /**< Rx FIFO level */ -#define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000 /**< Tx FIFO level */ - -#define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800 /**< Tri-state IO - * during HIZ - */ -#define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400 /**< First PL config - * done - */ -#define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200 /**< Global power down */ -#define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100 /**< Tri-state IO during - * config - */ -#define XDCFG_STATUS_SECURE_RST_MASK 0x00000080 /**< Secure Reset - * POR Status - */ -#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040 /**< Illegal APB - * access - */ -#define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020 /**< PL config - * reset status - */ -#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /**< FPGA Init - * Status - */ -#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008 - /**< BBRAM key - * disable - */ -#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security - * Enable Status - */ -#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002 /**< EFuse JTAG - * Disable - * status - */ -/* @} */ - - -/** @name DMA Source/Destination Transfer Length Register Bit definitions - * @{ - */ -#define XDCFG_DMA_LEN_MASK 0x7FFFFFF /**< Length Mask */ -/*@}*/ - - - - -/** @name Miscellaneous Control Register Bit definitions - * @{ - */ -#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000 /**< PS Version Mask */ -#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28 /**< PS Version Shift */ -#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /**< PCAP loopback mask */ -/* @} */ - -/** @name FIFO Threshold Bit definitions - * @{ - */ - -#define XDCFG_CFG_FIFO_QUARTER 0x0 /**< Quarter empty */ -#define XDCFG_CFG_FIFO_HALF 0x1 /**< Half empty */ -#define XDCFG_CFG_FIFO_3QUARTER 0x2 /**< 3/4 empty */ -#define XDCFG_CFG_FIFO_EMPTY 0x4 /**< Empty */ -/* @}*/ - - -/* Miscellaneous constant values */ -#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /**< Invalid DMA address */ -#define XDCFG_UNLOCK_DATA 0x757BDF0D /**< First APB access data*/ -#define XDCFG_BASE_ADDRESS 0xFE007000 /**< Device Config base - * address - */ -#define XDCFG_CONFIG_RESET_VALUE 0x508 /**< Config reg reset value */ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/****************************************************************************/ -/** -* -* Read the given register. -* -* @param BaseAddr is the base address of the device -* @param RegOffset is the register offset to be read -* -* @return The 32-bit value of the register -* -* @note C-style signature: -* u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset) -* -*****************************************************************************/ -#define XDcfg_ReadReg(BaseAddr, RegOffset) \ - Xil_In32((BaseAddr) + (RegOffset)) - -/****************************************************************************/ -/** -* -* Write to the given register. -* -* @param BaseAddr is the base address of the device -* @param RegOffset is the register offset to be written -* @param Data is the 32-bit value to write to the register -* -* @return None. -* -* @note C-style signature: -* void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data) -* -*****************************************************************************/ -#define XDcfg_WriteReg(BaseAddr, RegOffset, Data) \ - Xil_Out32((BaseAddr) + (RegOffset), (Data)) - -/************************** Function Prototypes ******************************/ -/* - * Perform reset operation to the devcfg interface - */ -void XDcfg_ResetHw(u32 BaseAddr); -/************************** Variable Definitions *****************************/ - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v2_04_a/src/xdevcfg_intr.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v2_04_a/src/xdevcfg_intr.c deleted file mode 100644 index 0ca44616e4c7475122f66a4b321ee5eae8b59b43..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v2_04_a/src/xdevcfg_intr.c +++ /dev/null @@ -1,316 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file xdevcfg_intr.c -* -* Contains the implementation of interrupt related functions of the XDcfg -* driver. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- --------------------------------------------- -* 1.00a hvm 02/07/11 First release -* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly -* set the mask instead of oring it with the -* value read from the interrupt status register -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xdevcfg.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/************************** Variable Definitions *****************************/ - -/****************************************************************************/ -/** -* -* This function enables the specified interrupts in the device. -* -* @param InstancePtr is a pointer to the XDcfg instance. -* @param Mask is the bit-mask of the interrupts to be enabled. -* Bit positions of 1 will be enabled. Bit positions of 0 will -* keep the previous setting. This mask is formed by OR'ing -* XDCFG_INT_* bits defined in xdevcfg_hw.h. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask) -{ - u32 RegValue; - - /* - * Assert the arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Enable the specified interrupts in the Interrupt Mask Register. - */ - RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, - XDCFG_INT_MASK_OFFSET); - RegValue &= ~(Mask & XDCFG_IXR_ALL_MASK); - XDcfg_WriteReg(InstancePtr->Config.BaseAddr, - XDCFG_INT_MASK_OFFSET, - RegValue); -} - - -/****************************************************************************/ -/** -* -* This function disables the specified interrupts in the device. -* -* @param InstancePtr is a pointer to the XDcfg instance. -* @param Mask is the bit-mask of the interrupts to be disabled. -* Bit positions of 1 will be disabled. Bit positions of 0 will -* keep the previous setting. This mask is formed by OR'ing -* XDCFG_INT_* bits defined in xdevcfg_hw.h. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask) -{ - u32 RegValue; - - /* - * Assert the arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Disable the specified interrupts in the Interrupt Mask Register. - */ - RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, - XDCFG_INT_MASK_OFFSET); - RegValue |= (Mask & XDCFG_IXR_ALL_MASK); - XDcfg_WriteReg(InstancePtr->Config.BaseAddr, - XDCFG_INT_MASK_OFFSET, - RegValue); -} -/****************************************************************************/ -/** -* -* This function returns the enabled interrupts read from the Interrupt Mask -* Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h -* to interpret the returned value. -* -* @param InstancePtr is a pointer to the XDcfg instance. -* -* @return A 32-bit value representing the contents of the IMR. -* -* @note None. -* -*****************************************************************************/ -u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr) -{ - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Return the value read from the Interrupt Mask Register. - */ - return (~ XDcfg_ReadReg(InstancePtr->Config.BaseAddr, - XDCFG_INT_MASK_OFFSET)); -} - -/****************************************************************************/ -/** -* -* This function returns the interrupt status read from Interrupt Status -* Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h -* to interpret the returned value. -* -* @param InstancePtr is a pointer to the XDcfg instance. -* -* @return A 32-bit value representing the contents of the Interrupt -* Status register. -* -* @note None. -* -*****************************************************************************/ -u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr) -{ - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Return the value read from the Interrupt Status register. - */ - return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, - XDCFG_INT_STS_OFFSET); -} - -/****************************************************************************/ -/** -* -* This function clears the specified interrupts in the Interrupt Status -* Register. -* -* @param InstancePtr is a pointer to the XDcfg instance. -* @param Mask is the bit-mask of the interrupts to be cleared. -* Bit positions of 1 will be cleared. Bit positions of 0 will not -* change the previous interrupt status. This mask is formed by -* OR'ing XDCFG_INT_* bits which are defined in xdevcfg_hw.h. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask) -{ - /* - * Assert the arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - XDcfg_WriteReg(InstancePtr->Config.BaseAddr, - XDCFG_INT_STS_OFFSET, - Mask); - -} - -/*****************************************************************************/ -/** -* The interrupt handler for the Device Config Interface. -* -* Events are signaled to upper layer for proper handling. -* -* -* @param InstancePtr is a pointer to the XDcfg instance. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void XDcfg_InterruptHandler(XDcfg *InstancePtr) -{ - u32 IntrStatusReg; - - /* - * Assert validates the input arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the Interrupt status register. - */ - IntrStatusReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, - XDCFG_INT_STS_OFFSET); - - /* - * Write the status back to clear the interrupts so that no - * subsequent interrupts are missed while processing this interrupt. - * This also does the DMA acknowledgment automatically. - */ - XDcfg_WriteReg(InstancePtr->Config.BaseAddr, - XDCFG_INT_STS_OFFSET, IntrStatusReg); - - /* - * Signal application that there are events to handle. - */ - InstancePtr->StatusHandler(InstancePtr->CallBackRef, - IntrStatusReg); - -} - -/****************************************************************************/ -/** -* -* This function sets the handler that will be called when an event (interrupt) -* occurs that needs application's attention. -* -* @param InstancePtr is a pointer to the XDcfg instance -* @param CallBackFunc is the address of the callback function. -* @param CallBackRef is a user data item that will be passed to the -* callback function when it is invoked. -* -* @return None. -* -* @note None. -* -* -*****************************************************************************/ -void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc, - void *CallBackRef) -{ - /* - * Asserts validate the input arguments - * CallBackRef not checked, no way to know what is valid - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(CallBackFunc != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - InstancePtr->StatusHandler = (XDcfg_IntrHandler) CallBackFunc; - InstancePtr->CallBackRef = CallBackRef; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v2_04_a/src/xdevcfg_selftest.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v2_04_a/src/xdevcfg_selftest.c deleted file mode 100644 index cdb2a07610ec96823507b7ffbc1306a9ea0018d5..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v2_04_a/src/xdevcfg_selftest.c +++ /dev/null @@ -1,120 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license1and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file xdevcfg_selftest.c -* -* Contains diagnostic self-test functions for the XDcfg driver. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- --------------------------------------------- -* 1.00a hvm 02/07/11 First release -* 2.02a nm 02/27/13 Fixed CR# 701348. -* Peripheral test fails with Running -* DcfgSelfTestExample() in SECURE bootmode. -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xdevcfg.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/************************** Variable Definitions *****************************/ - -/****************************************************************************/ -/** -* -* Run a self-test on the Device Configuration Interface. This test does a -* control register write and reads back the same value. -* -* @param InstancePtr is a pointer to the XDcfg instance. -* -* @return -* - XST_SUCCESS if self-test was successful. -* - XST_FAILURE if fails. -* -* @note None. -* -******************************************************************************/ -int XDcfg_SelfTest(XDcfg *InstancePtr) -{ - u32 OldCfgReg; - u32 CfgReg; - int Status = XST_SUCCESS; - - /* - * Assert to ensure the inputs are valid and the instance has been - * initialized. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - OldCfgReg = XDcfg_GetControlRegister(InstancePtr); - - XDcfg_SetControlRegister(InstancePtr, XDCFG_CTRL_NIDEN_MASK); - - CfgReg = XDcfg_GetControlRegister(InstancePtr); - - if ((CfgReg & XDCFG_CTRL_NIDEN_MASK) != XDCFG_CTRL_NIDEN_MASK) { - - Status = XST_FAILURE; - } - - /* - * Restore the original values of the register - */ - XDcfg_SetControlRegister(InstancePtr, OldCfgReg); - - return Status; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v2_04_a/src/xdevcfg_sinit.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v2_04_a/src/xdevcfg_sinit.c deleted file mode 100644 index 8964796f060da9202de2412622953538b57b57c7..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/devcfg_v2_04_a/src/xdevcfg_sinit.c +++ /dev/null @@ -1,99 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xdevcfg_sinit.c -* -* This file contains method for static initialization (compile-time) of the -* driver. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- --------------------------------------------- -* 1.00a hvm 02/07/11 First release -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xdevcfg.h" -#include "xparameters.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/*****************************************************************************/ -/** -* Lookup the device configuration based on the unique device ID. The table -* contains the configuration info for each device in the system. -* -* @param DeviceId is the unique device ID of the device being looked up. -* -* @return A pointer to the configuration table entry corresponding to the -* given device ID, or NULL if no match is found. -* -* @note None. -* -******************************************************************************/ -XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId) -{ - extern XDcfg_Config XDcfg_ConfigTable[]; - XDcfg_Config *CfgPtr = NULL; - int Index; - - for (Index = 0; Index < XPAR_XDCFG_NUM_INSTANCES; Index++) { - if (XDcfg_ConfigTable[Index].DeviceId == DeviceId) { - CfgPtr = &XDcfg_ConfigTable[Index]; - break; - } - } - - return (CfgPtr); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v1_06_a/src/Makefile b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v1_06_a/src/Makefile deleted file mode 100644 index d1240c586cd64556950a7826e73c46719a2ce887..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v1_06_a/src/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -COMPILER= -ARCHIVER= -CP=cp -COMPILER_FLAGS= -EXTRA_COMPILER_FLAGS= -LIB=libxil.a - -CC_FLAGS = $(COMPILER_FLAGS) -ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) - -RELEASEDIR=../../../lib -INCLUDEDIR=../../../include -INCLUDES=-I./. -I${INCLUDEDIR} - -OUTS = *.o - -LIBSOURCES:=*.c -INCLUDEFILES:=*.h - -OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) - -libs: banner xdmaps_libs clean - -%.o: %.c - ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< - -banner: - echo "Compiling dmaps" - -xdmaps_libs: ${OBJECTS} - $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} - -.PHONY: include -include: xdmaps_includes - -xdmaps_includes: - ${CP} ${INCLUDEFILES} ${INCLUDEDIR} - -clean: - rm -rf ${OBJECTS} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v1_06_a/src/xdmaps.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v1_06_a/src/xdmaps.c deleted file mode 100644 index 838adda803d510977f95d16ed8289a12ee99b04d..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v1_06_a/src/xdmaps.c +++ /dev/null @@ -1,2091 +0,0 @@ -/***************************************************************************** -* -* (c) Copyright 2009-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -*****************************************************************************/ -/****************************************************************************/ -/** -* -* @file xdmaps.c -* -* This file contains the implementation of the interface functions for XDmaPs -* driver. Refer to the header file xdmaps.h for more detailed information. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------ -------- ---------------------------------------------- -* 1.00 hbm 08/19/2010 First Release -* 1.00 nm 05/25/2011 Updated for minor doxygen corrections -* 1.02a sg 05/16/2012 Made changes for doxygen and moved some function -* header from the xdmaps.h file to xdmaps.c file -* Other cleanup for coding guidelines and CR 657109 -* and CR 657898 -* 1.03a sg 07/16/2012 changed inline to __inline for CR665681 -* 1.04a nm 10/22/2012 Fixed CR# 681671. -* 1.05a nm 04/15/2013 Fixed CR# 704396. Removed warnings when compiled -* with -Wall and -Wextra option in bsp. -* 05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg() -* function description. -* Fixed CR# 704396. Removed unused variables -* UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg() -* function. -* </pre> -* -*****************************************************************************/ - -/***************************** Include Files ********************************/ - -#include <string.h> - -#include "xstatus.h" -#include "xdmaps.h" -#include "xil_io.h" -#include "xil_cache.h" - -#include "xil_printf.h" - -// #define XDMAPS_DEBUG -#undef PDBG -#ifdef XDMAPS_DEBUG -# define PDBG(fmt, args...) xil_printf(fmt, ## args) -#else -# define PDBG(fmt, args...) -#endif - -/************************** Constant Definitions ****************************/ - -/* The following constant defines the amount of error that is allowed for - * a specified baud rate. This error is the difference between the actual - * baud rate that will be generated using the specified clock and the - * desired baud rate. - */ - -/**************************** Type Definitions ******************************/ - -/***************** Macros (Inline Functions) Definitions ********************/ - - -/************************** Function Prototypes *****************************/ -static int XDmaPs_Exec_DMAKILL(u32 BaseAddr, - unsigned int Channel, - unsigned int Thread); - -static void XDmaPs_BufPool_Free(XDmaPs_ProgBuf *Pool, void *Buf); - -static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg); - -static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel); -static void *XDmaPs_BufPool_Allocate(XDmaPs_ProgBuf *Pool); -static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd, - unsigned CacheLength); - -static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length); - - - -/************************** Variable Definitions ****************************/ - -/****************************************************************************/ -/** -* -* Initializes a specific XDmaPs instance such that it is ready to be used. -* The data format of the device is setup for 8 data bits, 1 stop bit, and no -* parity by default. The baud rate is set to a default value specified by -* Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The -* receive FIFO threshold is set for 8 bytes. The default operating mode of the -* driver is polled mode. -* -* @param InstPtr is a pointer to the XDmaPs instance. -* @param Config is a reference to a structure containing information -* about a specific XDmaPs driver. -* @param EffectiveAddr is the device base address in the virtual memory -* address space. The caller is responsible for keeping the -* address mapping from EffectiveAddr to the device physical base -* address unchanged once this function is invoked. Unexpected -* errors may occur if the address mapping changes after this -* function is called. If address translation is not used, pass in -* the physical address instead. -* -* @return -* -* - XST_SUCCESS on initialization completion -* -* @note None. -* -*****************************************************************************/ -int XDmaPs_CfgInitialize(XDmaPs *InstPtr, - XDmaPs_Config *Config, - u32 EffectiveAddr) -{ - int Status = XST_SUCCESS; - unsigned int CacheLength = 0; - u32 CfgReg; - unsigned Channel; - XDmaPs_ChannelData *ChanData; - - /* - * Assert validates the input arguments - */ - Xil_AssertNonvoid(InstPtr != NULL); - Xil_AssertNonvoid(Config != NULL); - - /* - * Setup the driver instance using passed in parameters - */ - InstPtr->Config.DeviceId = Config->DeviceId; - InstPtr->Config.BaseAddress = EffectiveAddr; - - CfgReg = XDmaPs_ReadReg(EffectiveAddr, XDMAPS_CR1_OFFSET); - CacheLength = CfgReg & XDMAPS_CR1_I_CACHE_LEN_MASK; - if (CacheLength < 2 || CacheLength > 5) - CacheLength = 0; - else - CacheLength = 1 << CacheLength; - - InstPtr->CacheLength = CacheLength; - - memset(InstPtr->Chans, 0, - sizeof(XDmaPs_ChannelData[XDMAPS_CHANNELS_PER_DEV])); - - for (Channel = 0; Channel < XDMAPS_CHANNELS_PER_DEV; Channel++) { - ChanData = InstPtr->Chans + Channel; - ChanData->ChanId = Channel; - ChanData->DevId = Config->DeviceId; - } - - InstPtr->IsReady = 1; - - return Status; -} - -/****************************************************************************/ -/** -* -* Reset the DMA Manager. -* -* @param InstPtr is the DMA instance. -* -* @return 0 on success, -1 on time out -* -* @note None. -* -*****************************************************************************/ -int XDmaPs_ResetManager(XDmaPs *InstPtr) -{ - int Status; - Status = XDmaPs_Exec_DMAKILL(InstPtr->Config.BaseAddress, - 0, 0); - - return Status; -} - -/****************************************************************************/ -/** -* -* Reset the specified DMA Channel. -* -* @param InstPtr is the DMA instance. -* @param Channel is the channel to be reset. -* -* @return 0 on success, -1 on time out -* -* @note None. -* -*****************************************************************************/ -int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel) -{ - int Status; - Status = XDmaPs_Exec_DMAKILL(InstPtr->Config.BaseAddress, - Channel, 1); - - return Status; - -} - -/*****************************************************************************/ -/** -* -* Driver fault interrupt service routine -* This is the one that connects the GIC -* -* @param InstPtr is the DMA instance. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XDmaPs_FaultISR(XDmaPs *InstPtr) -{ - - void *DmaProgBuf; - u32 Fsm; /* Fault status DMA manager register value */ - u32 Fsc; /* Fault status DMA channel register value */ - u32 FaultType; /* Fault type DMA manager register value */ - - u32 BaseAddr = InstPtr->Config.BaseAddress; - - u32 Pc; /* DMA Pc or channel Pc */ - XDmaPs_ChannelData *ChanData; - - unsigned Chan; - unsigned DevId; - - XDmaPs_Cmd *DmaCmd; - - PDBG("inside Fault ISR dev %d\r\n", InstPtr->Config.DeviceId); - - Fsm = XDmaPs_ReadReg(BaseAddr, XDMAPS_FSM_OFFSET) & 0x01; - Fsc = XDmaPs_ReadReg(BaseAddr, XDMAPS_FSC_OFFSET) & 0xFF; - - - DevId = InstPtr->Config.DeviceId; - - if (Fsm) { - /* - * if DMA manager is fault - */ - FaultType = XDmaPs_ReadReg(BaseAddr, XDMAPS_FTM_OFFSET); - Pc = XDmaPs_ReadReg(BaseAddr, XDMAPS_DPC_OFFSET); - - xil_printf("PL330 device %d fault with type: %x at Pc %x\n", - DevId, - FaultType, Pc); - - /* kill the DMA manager thread */ - /* Should we disable interrupt?*/ - XDmaPs_Exec_DMAKILL(BaseAddr, 0, 0); - } - - /* - * check which channel faults and kill the channel thread - */ - for (Chan = 0; - Chan < XDMAPS_CHANNELS_PER_DEV; - Chan++) { - if (Fsc & (0x01 << Chan)) { - PDBG("xdmaps_fault_isr: channel %d device %d\n", - Chan, DevId); - FaultType = - XDmaPs_ReadReg(BaseAddr, - XDmaPs_FTCn_OFFSET(Chan)); - Pc = XDmaPs_ReadReg(BaseAddr, - XDmaPs_CPCn_OFFSET(Chan)); - - PDBG("xdmaps_fault_isr: fault type %#x Pc %#x\n", - FaultType, Pc); - - /* kill the channel thread */ - PDBG("xdmaps_fault_isr: " - "killing channel %d for device %d\n", - Chan, - InstPtr->Config.DeviceId); - - /* Should we disable interrupt? */ - XDmaPs_Exec_DMAKILL(BaseAddr, Chan, 1); - - /* - * get the fault type and fault Pc and invoke the - * fault callback. - */ - ChanData = InstPtr->Chans + Chan; - - DmaCmd = ChanData->DmaCmdToHw; - - /* Should we check DmaCmd is not null */ - DmaCmd->DmaStatus = -1; - DmaCmd->ChanFaultType = FaultType; - DmaCmd->ChanFaultPCAddr = Pc; - ChanData->DmaCmdFromHw = DmaCmd; - ChanData->DmaCmdToHw = NULL; - - if (!ChanData->HoldDmaProg) { - DmaProgBuf = (void *)DmaCmd->GeneratedDmaProg; - if (DmaProgBuf) - XDmaPs_BufPool_Free(ChanData->ProgBufPool, - DmaProgBuf); - DmaCmd->GeneratedDmaProg = NULL; - } - - if (InstPtr->FaultHandler) - InstPtr->FaultHandler(Chan, - DmaCmd, - InstPtr->FaultRef); - - } - } - -} - -/*****************************************************************************/ -/** -* -* Set the done handler for a channel. -* -* @param InstPtr is the DMA instance. -* @param Channel is the channel number. -* @param DoneHandler is the done interrupt handler. -* @param CallbackRef is the callback reference data. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -int XDmaPs_SetDoneHandler(XDmaPs *InstPtr, - unsigned Channel, - XDmaPsDoneHandler DoneHandler, - void *CallbackRef) -{ - XDmaPs_ChannelData *ChanData; - - Xil_AssertNonvoid(InstPtr != NULL); - - if (Channel >= XDMAPS_CHANNELS_PER_DEV) - return XST_FAILURE; - - - ChanData = InstPtr->Chans + Channel; - - ChanData->DoneHandler = DoneHandler; - ChanData->DoneRef = CallbackRef; - - return 0; -} - -/*****************************************************************************/ -/** -* -* Set the fault handler for a channel. -* -* @param InstPtr is the DMA instance. -* @param FaultHandler is the fault interrupt handler. -* @param CallbackRef is the callback reference data. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -int XDmaPs_SetFaultHandler(XDmaPs *InstPtr, - XDmaPsFaultHandler FaultHandler, - void *CallbackRef) -{ - Xil_AssertNonvoid(InstPtr != NULL); - - InstPtr->FaultHandler = FaultHandler; - InstPtr->FaultRef = CallbackRef; - - return XST_SUCCESS; -} - - - -/****************************************************************************/ -/** -* Construction function for DMAEND instruction. This function fills the program -* buffer with the constructed instruction. -* -* @param DmaProg the DMA program buffer, it's the starting address for -* the instruction being constructed -* -* @return The number of bytes for this instruction which is 1. -* -* @note None. -* -*****************************************************************************/ -__inline int XDmaPs_Instr_DMAEND(char *DmaProg) -{ - /* - * DMAEND encoding: - * 7 6 5 4 3 2 1 0 - * 0 0 0 0 0 0 0 0 - */ - *DmaProg = 0x0; - - return 1; -} - - -__inline void XDmaPs_Memcpy4(char *Dst, char *Src) -{ - *Dst = *Src; - *(Dst + 1) = *(Src + 1); - *(Dst + 2) = *(Src + 2); - *(Dst + 3) = *(Src + 3); -} - -/****************************************************************************/ -/** -* -* Construction function for DMAGO instruction. This function fills the program -* buffer with the constructed instruction. -* -* @param DmaProg is the DMA program buffer, it's the starting address -* for the instruction being constructed -* @param Cn is the Channel number, 0 - 7 -* @param Imm is 32-bit immediate number written to the Channel Program -* Counter. -* @param Ns is Non-secure flag. If Ns is 1, the DMA channel operates in -* the Non-secure state. If Ns is 0, the execution depends on the -* security state of the DMA manager: -* DMA manager is in the Secure state, DMA channel operates in the -* Secure state. -* DMA manager is in the Non-secure state, DMAC aborts. -* -* @return The number of bytes for this instruction which is 6. -* -* @note None -* -*****************************************************************************/ -__inline int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn, - u32 Imm, unsigned int Ns) -{ - PDBG("entering XDmaPs_Instr_DMAGO(%x, %d, %x, %d)\r\n", - (unsigned int)DmaProg, Cn, Imm, Ns); - /* - * DMAGO encoding: - * 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 - * 0 0 0 0 0 |cn[2:0]| 1 0 1 0 0 0 ns 0 - * - * 47 ... 16 - * imm[32:0] - */ - *DmaProg = 0xA0 | ((Ns << 1) & 0x02); - - *(DmaProg + 1) = (u8)(Cn & 0x07); - - // *((u32 *)(DmaProg + 2)) = Imm; - XDmaPs_Memcpy4(DmaProg + 2, (char *)&Imm); - - /* success */ - return 6; -} - -/****************************************************************************/ -/** -* -* Construction function for DMALD instruction. This function fills the program -* buffer with the constructed instruction. -* -* @param DmaProg the DMA program buffer, it's the starting address for the -* instruction being constructed -* -* @return The number of bytes for this instruction which is 1. -* -* @note None. -* -*****************************************************************************/ -__inline int XDmaPs_Instr_DMALD(char *DmaProg) -{ - /* - * DMALD encoding - * 7 6 5 4 3 2 1 0 - * 0 0 0 0 0 1 bs x - * - * Note: this driver doesn't support conditional load or store, - * so the bs bit is 0 and x bit is 0. - */ - *DmaProg = 0x04; - return 1; -} - -/****************************************************************************/ -/** -* -* Construction function for DMALP instruction. This function fills the program -* buffer with the constructed instruction. -* -* @param DmaProg is the DMA program buffer, it's the starting address -* for the instruction being constructed -* @param Lc is the Loop counter register, can either be 0 or 1. -* @param LoopIterations: the number of interations, LoopInterations - 1 -* will be encoded in the DMALP instruction. -* -* @return The number of bytes for this instruction which is 2. -* -* @note None. -* -*****************************************************************************/ -__inline int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc, - unsigned LoopIterations) -{ - /* - * DMALP encoding - * 15 ... 8 7 6 5 4 3 2 1 0 - * | iter[7:0] |0 0 1 0 0 0 lc 0 - */ - *DmaProg = (u8)(0x20 | ((Lc & 1) << 1)); - *(DmaProg + 1) = (u8)(LoopIterations - 1); - return 2; -} - -/****************************************************************************/ -/** -* -* Construction function for DMALPEND instruction. This function fills the -* program buffer with the constructed instruction. -* -* @param DmaProg is the DMA program buffer, it's the starting address -* for the instruction being constructed -* @param BodyStart is the starting address of the loop body. It is used -* to calculate the bytes of backward jump. -* @param Lc is the Loop counter register, can either be 0 or 1. -* -* @return The number of bytes for this instruction which is 2. -* -* @note None. -* -*****************************************************************************/ -__inline int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc) -{ - /* - * DMALPEND encoding - * 15 ... 8 7 6 5 4 3 2 1 0 - * | backward_jump[7:0] |0 0 1 nf 1 lc bs x - * - * lc: loop counter - * nf is for loop forever. The driver does not support loop forever, - * so nf is 1. - * The driver does not support conditional LPEND, so bs is 0, x is 0. - */ - *DmaProg = 0x38 | ((Lc & 1) << 2); - *(DmaProg + 1) = (u8)(DmaProg - BodyStart); - - return 2; -} - -/* - * Register number for the DMAMOV instruction - */ -#define XDMAPS_MOV_SAR 0x0 -#define XDMAPS_MOV_CCR 0x1 -#define XDMAPS_MOV_DAR 0x2 - -/****************************************************************************/ -/** -* -* Construction function for DMAMOV instruction. This function fills the -* program buffer with the constructed instruction. -* -* @param DmaProg is the DMA program buffer, it's the starting address -* for the instruction being constructed -* @param Rd is the register id, 0 for SAR, 1 for CCR, and 2 for DAR -* @param Imm is the 32-bit immediate number -* -* @return The number of bytes for this instruction which is 6. -* -* @note None. -* -*****************************************************************************/ -__inline int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm) -{ - /* - * DMAMOV encoding - * 15 4 3 2 1 10 ... 8 7 6 5 4 3 2 1 0 - * 0 0 0 0 0 |rd[2:0]|1 0 1 1 1 1 0 0 - * - * 47 ... 16 - * imm[32:0] - * - * rd: b000 for SAR, b001 CCR, b010 DAR - */ - *DmaProg = 0xBC; - *(DmaProg + 1) = Rd & 0x7; - // *((u32 *)(DmaProg + 2)) = Imm; - XDmaPs_Memcpy4(DmaProg + 2, (char *)&Imm); - - return 6; -} - -/****************************************************************************/ -/** -* -* Construction function for DMANOP instruction. This function fills the -* program buffer with the constructed instruction. -* -* @param DmaProg is the DMA program buffer, it's the starting address -* for the instruction being constructed -* @return The number of bytes for this instruction which is 1. -* -* @note None. -* -*****************************************************************************/ -__inline int XDmaPs_Instr_DMANOP(char *DmaProg) -{ - /* - * DMANOP encoding - * 7 6 5 4 3 2 1 0 - * 0 0 0 1 1 0 0 0 - */ - *DmaProg = 0x18; - return 1; -} - -/****************************************************************************/ -/** -* -* Construction function for DMARMB instruction. This function fills the -* program buffer with the constructed instruction. -* -* @param DmaProg is the DMA program buffer, it's the starting address -* for the instruction being constructed -* -* @return The number of bytes for this instruction which is 1. -* -* @note None. -* -*****************************************************************************/ -__inline int XDmaPs_Instr_DMARMB(char *DmaProg) -{ - /* - * DMARMB encoding - * 7 6 5 4 3 2 1 0 - * 0 0 0 1 0 0 1 0 - */ - *DmaProg = 0x12; - return 1; -} - -/****************************************************************************/ -/** -* -* Construction function for DMASEV instruction. This function fills the -* program buffer with the constructed instruction. -* -* @param DmaProg is the DMA program buffer, it's the starting address -* for the instruction being constructed -* @param EventNumber is the Event number to signal. -* -* @return The number of bytes for this instruction which is 2. -* -* @note None. -* -*****************************************************************************/ -__inline int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber) -{ - /* - * DMASEV encoding - * 15 4 3 2 1 10 9 8 7 6 5 4 3 2 1 0 - * |event[4:0]| 0 0 0 0 0 1 1 0 1 0 0 - */ - *DmaProg = 0x34; - *(DmaProg + 1) = (u8)(EventNumber << 3); - - return 2; -} - - -/****************************************************************************/ -/** -* -* Construction function for DMAST instruction. This function fills the -* program buffer with the constructed instruction. -* -* @param DmaProg is the DMA program buffer, it's the starting address -* for the instruction being constructed -* -* @return The number of bytes for this instruction which is 1. -* -* @note None. -* -*****************************************************************************/ -__inline int XDmaPs_Instr_DMAST(char *DmaProg) -{ - /* - * DMAST encoding - * 7 6 5 4 3 2 1 0 - * 0 0 0 0 1 0 bs x - * - * Note: this driver doesn't support conditional load or store, - * so the bs bit is 0 and x bit is 0. - */ - *DmaProg = 0x08; - return 1; -} - - -/****************************************************************************/ -/** -* -* Construction function for DMAWMB instruction. This function fills the -* program buffer with the constructed instruction. -* -* @param DmaProg is the DMA program buffer, it's the starting address -* for the instruction being constructed -* -* @return The number of bytes for this instruction which is 1. -* -* @note None. -* -*****************************************************************************/ -__inline int XDmaPs_Instr_DMAWMB(char *DmaProg) -{ - /* - * DMAWMB encoding - * 7 6 5 4 3 2 1 0 - * 0 0 0 1 0 0 1 0 - */ - *DmaProg = 0x13; - return 1; -} - -/****************************************************************************/ -/** -* -* Conversion function from the endian swap size to the bit encoding of the CCR -* -* @param EndianSwapSize is the endian swap size, in terms of bits, it -* could be 8, 16, 32, 64, or 128(We are using DMA assembly syntax) -* -* @return The endian swap size bit encoding for the CCR. -* -* @note None. -* -*****************************************************************************/ -__inline unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize) -{ - switch (EndianSwapSize) { - case 0: - case 8: - return 0; - case 16: - return 1; - case 32: - return 2; - case 64: - return 3; - case 128: - return 4; - default: - return 0; - } - -} - -/****************************************************************************/ -/** -* -* Conversion function from the burst size to the bit encoding of the CCR -* -* @param BurstSize is the burst size. It's the data width. -* In terms of bytes, it could be 1, 2, 4, 8, 16, 32, 64, or 128. -* It must be no larger than the bus width. -* (We are using DMA assembly syntax.) -* -* @note None. -* -*****************************************************************************/ -__inline unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize) -{ - switch (BurstSize) { - case 1: - return 0; - case 2: - return 1; - case 4: - return 2; - case 8: - return 3; - case 16: - return 4; - case 32: - return 5; - case 64: - return 6; - case 128: - return 7; - default: - return 0; - } -} - - -/****************************************************************************/ -/** -* -* Conversion function from PL330 bus transfer descriptors to CCR value. All the -* values passed to the functions are in terms of assembly languages, not in -* terms of the register bit encoding. -* -* @param ChanCtrl is the Instance of XDmaPs_ChanCtrl. -* -* @return The 32-bit CCR value. -* -* @note None. -* -*****************************************************************************/ -u32 XDmaPs_ToCCRValue(XDmaPs_ChanCtrl *ChanCtrl) -{ - /* - * Channel Control Register encoding - * [31:28] - endian_swap_size - * [27:25] - dst_cache_ctrl - * [24:22] - dst_prot_ctrl - * [21:18] - dst_burst_len - * [17:15] - dst_burst_size - * [14] - dst_inc - * [13:11] - src_cache_ctrl - * [10:8] - src_prot_ctrl - * [7:4] - src_burst_len - * [3:1] - src_burst_size - * [0] - src_inc - */ - - unsigned es = - XDmaPs_ToEndianSwapSizeBits(ChanCtrl->EndianSwapSize); - - unsigned dst_burst_size = - XDmaPs_ToBurstSizeBits(ChanCtrl->DstBurstSize); - unsigned dst_burst_len = (ChanCtrl->DstBurstLen - 1) & 0x0F; - unsigned dst_cache_ctrl = (ChanCtrl->DstCacheCtrl & 0x03) - | ((ChanCtrl->DstCacheCtrl & 0x08) >> 1); - unsigned dst_prot_ctrl = ChanCtrl->DstProtCtrl & 0x07; - unsigned dst_inc_bit = ChanCtrl->DstInc & 1; - - unsigned src_burst_size = - XDmaPs_ToBurstSizeBits(ChanCtrl->SrcBurstSize); - unsigned src_burst_len = (ChanCtrl->SrcBurstLen - 1) & 0x0F; - unsigned src_cache_ctrl = (ChanCtrl->SrcCacheCtrl & 0x03) - | ((ChanCtrl->SrcCacheCtrl & 0x08) >> 1); - unsigned src_prot_ctrl = ChanCtrl->SrcProtCtrl & 0x07; - unsigned src_inc_bit = ChanCtrl->SrcInc & 1; - - u32 ccr_value = (es << 28) - | (dst_cache_ctrl << 25) - | (dst_prot_ctrl << 22) - | (dst_burst_len << 18) - | (dst_burst_size << 15) - | (dst_inc_bit << 14) - | (src_cache_ctrl << 11) - | (src_prot_ctrl << 8) - | (src_burst_len << 4) - | (src_burst_size << 1) - | (src_inc_bit); - - PDBG("CCR: es %x\r\n", es); - PDBG("CCR: dca %x, dpr %x, dbl %x, dbs %x, di %x\r\n", - dst_cache_ctrl, dst_prot_ctrl, - dst_burst_len, dst_burst_size, dst_inc_bit); - PDBG("CCR: sca %x, spr %x, sbl %x, sbs %x, si %x\r\n", - src_cache_ctrl, src_prot_ctrl, - src_burst_len, src_burst_size, src_inc_bit); - - return ccr_value; -} - -/****************************************************************************/ -/** -* Construct a loop with only DMALD and DMAST as the body using loop counter 0. -* The function also makes sure the loop body and the lpend is in the same -* cache line. -* -* @param DmaProgStart is the very start address of the DMA program. -* This is used to calculate whether the loop is in a cache line. -* @param CacheLength is the icache line length, in terms of bytes. -* If it's zero, the performance enhancement feature will be -* turned off. -* @param DmaProgLoopStart The starting address of the loop (DMALP). -* @param LoopCount The inner loop count. Loop count - 1 will be used to -* initialize the loop counter. -* -* @return The number of bytes the loop has. -* -* @note None. -* -*****************************************************************************/ -int XDmaPs_ConstructSingleLoop(char *DmaProgStart, - int CacheLength, - char *DmaProgLoopStart, - int LoopCount) -{ - int CacheStartOffset; - int CacheEndOffset; - int NumNops; - char *DmaProgBuf = DmaProgLoopStart; - - PDBG("Contructing single loop: loop count %d\r\n", LoopCount); - - DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 0, LoopCount); - - if (CacheLength > 0) { - /* - * the CacheLength > 0 switch is ued to turn on/off nop - * insertion - */ - CacheStartOffset = DmaProgBuf - DmaProgStart; - CacheEndOffset = CacheStartOffset + 3; - - /* - * check whether the body and lpend fit in one cache line - */ - if (CacheStartOffset / CacheLength - != CacheEndOffset / CacheLength) { - /* insert the nops */ - NumNops = CacheLength - - CacheStartOffset % CacheLength; - while (NumNops--) { - DmaProgBuf += - XDmaPs_Instr_DMANOP(DmaProgBuf); - } - } - } - - DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf); - DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf); - DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf, - DmaProgBuf - 2, 0); - - return DmaProgBuf - DmaProgLoopStart; -} - -/****************************************************************************/ -/** -* Construct a nested loop with only DMALD and DMAST in the inner loop body. -* It uses loop counter 1 for the outer loop and loop counter 0 for the -* inner loop. -* -* @param DmaProgStart is the very start address of the DMA program. -* This is used to calculate whether the loop is in a cache line. -* @param CacheLength is the icache line length, in terms of bytes. -* If it's zero, the performance enhancement feature will be -* turned off. -* @param DmaProgLoopStart The starting address of the loop (DMALP). -* @param LoopCountOuter The outer loop count. Loop count - 1 will be -* used to initialize the loop counter. -* @param LoopCountInner The inner loop count. Loop count - 1 will be -* used to initialize the loop counter. -* -* @return The number byes the nested loop program has. -* -* @note None. -* -*****************************************************************************/ -int XDmaPs_ConstructNestedLoop(char *DmaProgStart, - int CacheLength, - char *DmaProgLoopStart, - unsigned int LoopCountOuter, - unsigned int LoopCountInner) -{ - int CacheStartOffset; - int CacheEndOffset; - int NumNops; - char *InnerLoopStart; - char *DmaProgBuf = DmaProgLoopStart; - - PDBG("Contructing nested loop outer %d, inner %d\r\n", - LoopCountOuter, LoopCountInner); - - DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 1, LoopCountOuter); - InnerLoopStart = DmaProgBuf; - - if (CacheLength > 0) { - /* - * the CacheLength > 0 switch is ued to turn on/off nop - * insertion - */ - if (CacheLength < 8) { - /* - * if the cache line is too small to fit both loops - * just align the inner loop - */ - DmaProgBuf += - XDmaPs_ConstructSingleLoop(DmaProgStart, - CacheLength, - DmaProgBuf, - LoopCountInner); - /* outer loop end */ - DmaProgBuf += - XDmaPs_Instr_DMALPEND(DmaProgBuf, - InnerLoopStart, - 1); - - /* - * the nested loop is constructed for - * smaller cache line - */ - return DmaProgBuf - DmaProgLoopStart; - } - - /* - * Now let's handle the case where a cache line can - * fit the nested loops. - */ - CacheStartOffset = DmaProgBuf - DmaProgStart; - CacheEndOffset = CacheStartOffset + 7; - - /* - * check whether the body and lpend fit in one cache line - */ - if (CacheStartOffset / CacheLength - != CacheEndOffset / CacheLength) { - /* insert the nops */ - NumNops = CacheLength - - CacheStartOffset % CacheLength; - while (NumNops--) { - DmaProgBuf += - XDmaPs_Instr_DMANOP(DmaProgBuf); - } - } - } - - /* insert the inner DMALP */ - DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 0, LoopCountInner); - - /* DMALD and DMAST instructions */ - DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf); - DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf); - - /* inner DMALPEND */ - DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf, - DmaProgBuf - 2, 0); - /* outer DMALPEND */ - DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf, - InnerLoopStart, 1); - - /* return the number of bytes */ - return DmaProgBuf - DmaProgLoopStart; -} - -/* - * [31:28] endian_swap_size b0000 - * [27:25] dst_cache_ctrl b000 - * [24:22] dst_prot_ctrl b000 - * [21:18] dst_burst_len b0000 - * [17:15] dst_burst_size b000 - * [14] dst_inc b0 - * [27:25] src_cache_ctrl b000 - * [24:22] src_prot_ctrl b000 - * [21:18] src_burst_len b0000 - * [17:15] src_burst_size b000 - * [14] src_inc b0 - */ -#define XDMAPS_CCR_SINGLE_BYTE (0x0) -#define XDMAPS_CCR_M2M_SINGLE_BYTE ((0x1 << 14) | 0x1) - - -/****************************************************************************/ -/** -* -* Construct the DMA program based on the descriptions of the DMA transfer. -* The function handles memory to memory DMA transfers. -* It also handles unalgined head and small amount of residue tail. -* -* @param Channel DMA channel number -* @param Cmd is the DMA command. -* @param CacheLength is the icache line length, in terms of bytes. -* If it's zero, the performance enhancement feature will be -* turned off. -* -* @returns The number of bytes for the program. -* -* @note None. -* -*****************************************************************************/ -static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd, - unsigned CacheLength) -{ - /* - * unpack arguments - */ - char *DmaProgBuf = (char *)Cmd->GeneratedDmaProg; - unsigned DevChan = Channel; - unsigned long DmaLength = Cmd->BD.Length; - u32 SrcAddr = Cmd->BD.SrcAddr; - - unsigned SrcInc = Cmd->ChanCtrl.SrcInc; - u32 DstAddr = Cmd->BD.DstAddr; - unsigned DstInc = Cmd->ChanCtrl.DstInc; - - char *DmaProgStart = DmaProgBuf; - - unsigned int BurstBytes; - unsigned int LoopCount; - unsigned int LoopCount1 = 0; - unsigned int LoopResidue = 0; - unsigned int TailBytes; - unsigned int TailWords; - int DmaProgBytes; - u32 CCRValue; - unsigned int Unaligned; - unsigned int UnalignedCount; - unsigned int MemBurstSize = 1; - u32 MemAddr = 0; - unsigned int Index; - unsigned int SrcUnaligned = 0; - unsigned int DstUnaligned = 0; - - XDmaPs_ChanCtrl *ChanCtrl; - XDmaPs_ChanCtrl WordChanCtrl; - static XDmaPs_ChanCtrl Mem2MemByteCC; - - Mem2MemByteCC.EndianSwapSize = 0; - Mem2MemByteCC.DstCacheCtrl = 0; - Mem2MemByteCC.DstProtCtrl = 0; - Mem2MemByteCC.DstBurstLen = 1; - Mem2MemByteCC.DstBurstSize = 1; - Mem2MemByteCC.DstInc = 1; - Mem2MemByteCC.SrcCacheCtrl = 0; - Mem2MemByteCC.SrcProtCtrl = 0; - Mem2MemByteCC.SrcBurstLen = 1; - Mem2MemByteCC.SrcBurstSize = 1; - Mem2MemByteCC.SrcInc = 1; - - ChanCtrl = &Cmd->ChanCtrl; - - /* insert DMAMOV for SAR and DAR */ - DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf, - XDMAPS_MOV_SAR, - SrcAddr); - DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf, - XDMAPS_MOV_DAR, - DstAddr); - - - if (ChanCtrl->SrcInc) - SrcUnaligned = SrcAddr % ChanCtrl->SrcBurstSize; - - if (ChanCtrl->DstInc) - DstUnaligned = DstAddr % ChanCtrl->DstBurstSize; - - if ((SrcUnaligned && DstInc) || (DstUnaligned && SrcInc)) { - ChanCtrl = &Mem2MemByteCC; - } - - if (ChanCtrl->SrcInc) { - MemBurstSize = ChanCtrl->SrcBurstSize; - MemAddr = SrcAddr; - - } else if (ChanCtrl->DstInc) { - MemBurstSize = ChanCtrl->DstBurstSize; - MemAddr = DstAddr; - } - - /* check whether the head is aligned or not */ - Unaligned = MemAddr % MemBurstSize; - - if (Unaligned) { - /* if head is unaligned, transfer head in bytes */ - UnalignedCount = MemBurstSize - Unaligned; - CCRValue = XDMAPS_CCR_SINGLE_BYTE - | (SrcInc & 1) - | ((DstInc & 1) << 14); - - DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf, - XDMAPS_MOV_CCR, - CCRValue); - - PDBG("unaligned head count %d\r\n", - UnalignedCount); - for (Index = 0; Index < UnalignedCount; Index++) { - DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf); - DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf); - } - - DmaLength -= UnalignedCount; - } - - /* now the burst transfer part */ - CCRValue = XDmaPs_ToCCRValue(ChanCtrl); - DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf, - XDMAPS_MOV_CCR, - CCRValue); - - BurstBytes = ChanCtrl->SrcBurstSize * ChanCtrl->SrcBurstLen; - - LoopCount = DmaLength / BurstBytes; - TailBytes = DmaLength % BurstBytes; - - /* - * the loop count register is 8-bit wide, so if we need - * a larger loop, we need to have nested loops - */ - if (LoopCount > 256) { - LoopCount1 = LoopCount / 256; - if (LoopCount1 > 256) { - xil_printf("DMA operation cannot fit in a 2-level " - "loop for channel %d, please reduce the " - "DMA length or increase the burst size or " - "length", - Channel); - return 0; - } - LoopResidue = LoopCount % 256; - - PDBG("loop count %d is greater than 256\r\n", LoopCount); - if (LoopCount1 > 1) - DmaProgBuf += - XDmaPs_ConstructNestedLoop(DmaProgStart, - CacheLength, - DmaProgBuf, - LoopCount1, - 256); - else - DmaProgBuf += - XDmaPs_ConstructSingleLoop(DmaProgStart, - CacheLength, - DmaProgBuf, - 256); - - /* there will be some that cannot be covered by - * nested loops - */ - LoopCount = LoopResidue; - } - - if (LoopCount > 0) { - PDBG("now loop count is %d \r\n", LoopCount); - DmaProgBuf += XDmaPs_ConstructSingleLoop(DmaProgStart, - CacheLength, - DmaProgBuf, - LoopCount); - } - - if (TailBytes) { - /* handle the tail */ - TailWords = TailBytes / MemBurstSize; - TailBytes = TailBytes % MemBurstSize; - - if (TailWords) { - PDBG("tail words is %d \r\n", TailWords); - WordChanCtrl = *ChanCtrl; - /* - * if we can transfer the tail in words, we will - * transfer words as much as possible - */ - WordChanCtrl.SrcBurstSize = MemBurstSize; - WordChanCtrl.SrcBurstLen = 1; - WordChanCtrl.DstBurstSize = MemBurstSize; - WordChanCtrl.DstBurstLen = 1; - - - /* - * the burst length is 1 - */ - CCRValue = XDmaPs_ToCCRValue(&WordChanCtrl); - - DmaProgBuf += - XDmaPs_Instr_DMAMOV(DmaProgBuf, - XDMAPS_MOV_CCR, - CCRValue); - DmaProgBuf += - XDmaPs_ConstructSingleLoop(DmaProgStart, - CacheLength, - DmaProgBuf, - TailWords); - - } - - if (TailBytes) { - /* - * for the rest, we'll tranfer in bytes - */ - /* - * So far just to be safe, the tail bytes - * are transfered in a loop. We can optimize a little - * to perform a burst. - */ - CCRValue = XDMAPS_CCR_SINGLE_BYTE - | (SrcInc & 1) - | ((DstInc & 1) << 14); - - DmaProgBuf += - XDmaPs_Instr_DMAMOV(DmaProgBuf, - XDMAPS_MOV_CCR, - CCRValue); - - PDBG("tail bytes is %d \r\n", TailBytes); - DmaProgBuf += - XDmaPs_ConstructSingleLoop(DmaProgStart, - CacheLength, - DmaProgBuf, - TailBytes); - - } - } - - DmaProgBuf += XDmaPs_Instr_DMASEV(DmaProgBuf, DevChan); - DmaProgBuf += XDmaPs_Instr_DMAEND(DmaProgBuf); - - DmaProgBytes = DmaProgBuf - DmaProgStart; - - Xil_DCacheFlushRange((u32)DmaProgStart, DmaProgBytes); - - return DmaProgBytes; - -} - - -/****************************************************************************/ -/** -* -* Generate a DMA program based for the DMA command, the buffer will be pointed -* by the GeneratedDmaProg field of the command. -* -* @param InstPtr is then DMA instance. -* @param Channel is the DMA channel number. -* @param Cmd is the DMA command. -* -* @return - XST_SUCCESS on success. -* - XST_FAILURE if it fails -* -* @note None. -* -*****************************************************************************/ -int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd) -{ - void *Buf; - int ProgLen; - XDmaPs_ChannelData *ChanData; - XDmaPs_ChanCtrl *ChanCtrl; - - Xil_AssertNonvoid(InstPtr != NULL); - Xil_AssertNonvoid(Cmd != NULL); - - PDBG("Inside XdmaPs_GenDmaProg\r\n"); - - if (Channel > XDMAPS_CHANNELS_PER_DEV) - return XST_FAILURE; - - ChanData = InstPtr->Chans + Channel; - ChanCtrl = &Cmd->ChanCtrl; - - if (ChanCtrl->SrcBurstSize * ChanCtrl->SrcBurstLen - != ChanCtrl->DstBurstSize * ChanCtrl->DstBurstLen) { - xil_printf("source burst_size * burst_len does not match " - "that of destination\r\n"); - return XST_FAILURE; - } - - - /* - * unaligned fixed address is not supported - */ - if (!ChanCtrl->SrcInc && Cmd->BD.SrcAddr % ChanCtrl->SrcBurstSize) { - xil_printf("source address is fixed but is unaligned\r\n"); - return XST_FAILURE; - } - - if (!ChanCtrl->DstInc && Cmd->BD.DstAddr % ChanCtrl->DstBurstSize) { - xil_printf("destination address is fixed but is " - "unaligned\r\n"); - return XST_FAILURE; - } - - Buf = XDmaPs_BufPool_Allocate(ChanData->ProgBufPool); - if (Buf == NULL) { - xil_printf("failed to allocate program buffer\r\n"); - return XST_FAILURE; - } - PDBG("Buf allocated %x\r\n", (u32)Buf); - - - Cmd->GeneratedDmaProg = Buf; - ProgLen = XDmaPs_BuildDmaProg(Channel, Cmd, - InstPtr->CacheLength); - Cmd->GeneratedDmaProgLength = ProgLen; - - PDBG("Generated DMA Prog length is %d\r\n", ProgLen); - -#ifdef XDMAPS_DEBUG - XDmaPs_Print_DmaProg(Cmd); -#endif - - if (ProgLen <= 0) { - /* something wrong, release the buffer */ - XDmaPs_BufPool_Free(ChanData->ProgBufPool, Buf); - Cmd->GeneratedDmaProgLength = 0; - Cmd->GeneratedDmaProg = NULL; - return XST_FAILURE; - } - - return XST_SUCCESS; -} - - -/****************************************************************************/ -/** - * Free the DMA program buffer that is pointed by the GeneratedDmaProg field - * of the command. - * - * @param InstPtr is then DMA instance. - * @param Channel is the DMA channel number. - * @param Cmd is the DMA command. - * - * @return XST_SUCCESS on success. - * XST_FAILURE if there is any error. - * - * @note None. - * - ****************************************************************************/ -int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd) -{ - - void *Buf; - XDmaPs_ChannelData *ChanData; - - Xil_AssertNonvoid(InstPtr != NULL); - Xil_AssertNonvoid(Cmd != NULL); - - if (Channel > XDMAPS_CHANNELS_PER_DEV) - return XST_FAILURE; - - Buf = (void *)Cmd->GeneratedDmaProg; - ChanData = InstPtr->Chans + Channel; - - if (Buf) { - XDmaPs_BufPool_Free(ChanData->ProgBufPool, Buf); - Cmd->GeneratedDmaProg = 0; - Cmd->GeneratedDmaProgLength = 0; - } - - return XST_SUCCESS; -} - - -/****************************************************************************/ -/** -* -* Start a DMA command. The command can only be invoked when the channel -* is idle. The driver takes the command, generates DMA program if needed, -* then pass the program to DMAC to execute. -* -* @param InstPtr is then DMA instance. -* @param Channel is the DMA channel number. -* @param Cmd is the DMA command. -* @param HoldDmaProg is tag indicating whether the driver can release -* the allocated DMA buffer or not. If a user wants to examine the -* generated DMA program, the flag should be set to 1. After the -* DMA program is finished, a user needs to explicity free the -* buffer. -* -* @return -* - XST_SUCCESS on success -* - XST_DEVICE_BUSY if DMA is busy -* - XST_FAILURE on other failures -* -* @note None. -* -****************************************************************************/ -int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel, - XDmaPs_Cmd *Cmd, - int HoldDmaProg) -{ - int Status; - u32 DmaProg = 0; - u32 Inten; - - Xil_AssertNonvoid(InstPtr != NULL); - Xil_AssertNonvoid(Cmd != NULL); - - PDBG("Inside XDmaPs_Start\r\n"); - - Cmd->DmaStatus = XST_FAILURE; - - if (XDmaPs_IsActive(InstPtr, Channel)) - return XST_DEVICE_BUSY; - - if (!Cmd->UserDmaProg && !Cmd->GeneratedDmaProg) { - Status = XDmaPs_GenDmaProg(InstPtr, Channel, Cmd); - if (Status) - return XST_FAILURE; - } - - InstPtr->Chans[Channel].HoldDmaProg = HoldDmaProg; - - if (Cmd->UserDmaProg) - DmaProg = (u32)Cmd->UserDmaProg; - else if (Cmd->GeneratedDmaProg) - DmaProg = (u32)Cmd->GeneratedDmaProg; - - if (DmaProg) { - /* enable the interrupt */ - // PDBG("enable_dma: enabling interrupt\r\n"); - PDBG("enable_dma: enabling interrupt\r\n"); - Inten = XDmaPs_ReadReg(InstPtr->Config.BaseAddress, - XDMAPS_INTEN_OFFSET); - Inten |= 0x01 << Channel; /* set the correpsonding bit */ - PDBG("enable_dma: writing inten %x\r\n", Inten); - XDmaPs_WriteReg(InstPtr->Config.BaseAddress, - XDMAPS_INTEN_OFFSET, - Inten); - - PDBG("pl330 interrupt enabled for channel %d\r\n", Channel); - Inten = XDmaPs_ReadReg(InstPtr->Config.BaseAddress, - XDMAPS_INTEN_OFFSET); - if ((Inten & (0x01 << Channel)) == 0) { - PDBG("Trouble enabling Intr, INTEN Reg: %x\r\n", - XDmaPs_ReadReg(InstPtr->Config.BaseAddress, - XDMAPS_INTEN_OFFSET)); - } - else { - PDBG("pl330 interrupt enabled for channel %d\r\n", - Channel); - } - - InstPtr->Chans[Channel].DmaCmdToHw = Cmd; - - PDBG("Src %x, Dst %x, Len %x\r\n", - Cmd->BD.SrcAddr, - Cmd->BD.DstAddr, - Cmd->BD.Length); - - if (Cmd->ChanCtrl.SrcInc) { - PDBG("DCachFlushRange for Src 0x%x, Len 0x%x \r\n", - Cmd->BD.SrcAddr, Cmd->BD.Length); - Xil_DCacheFlushRange(Cmd->BD.SrcAddr, Cmd->BD.Length); - } - if (Cmd->ChanCtrl.DstInc) { - PDBG("DCachInvalidateRange for Dst 0x%x, Len 0x%x \r\n", - Cmd->BD.DstAddr, Cmd->BD.Length); - Xil_DCacheInvalidateRange(Cmd->BD.DstAddr, - Cmd->BD.Length); - } - - Status = XDmaPs_Exec_DMAGO(InstPtr->Config.BaseAddress, - Channel, DmaProg); - } - else { - InstPtr->Chans[Channel].DmaCmdToHw = NULL; - Status = XST_FAILURE; - } - - return Status; -} - -/****************************************************************************/ -/** -* -* Checks whether the DMA channel is active or idle. -* -* @param InstPtr is the DMA instance. -* @param Channel is the DMA channel number. -* -* @return 0: if the channel is idle -* 1: otherwise -* -* @note None. -* -*****************************************************************************/ -int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel) -{ - Xil_AssertNonvoid(InstPtr != NULL); - - /* Need to assert Channel is in range */ - if (Channel > XDMAPS_CHANNELS_PER_DEV) - return 0; - - return InstPtr->Chans[Channel].DmaCmdToHw != NULL; -} - - - -/****************************************************************************/ -/** -* -* Allocate a buffer of the DMA program buffer from the pool. -* -* @param Pool the DMA program pool. -* -* @return The allocated buffer, NULL if there is any error. -* -* @note None. -* -*****************************************************************************/ -static void *XDmaPs_BufPool_Allocate(XDmaPs_ProgBuf *Pool) -{ - int Index; - - Xil_AssertNonvoid(Pool != NULL); - - for (Index = 0; Index < XDMAPS_MAX_CHAN_BUFS; Index++) { - if (!Pool[Index].Allocated) { - PDBG("Allocate buf %d\r\n", Index); - Pool[Index].Allocated = 1; - return Pool[Index].Buf; - } - } - - return NULL; - -} - -/*****************************************************************************/ -/** -* -* Driver done interrupt service routine for channel 0. We need this done ISR -* mainly because the driver needs to release the DMA program buffer. -* This is the one that connects the GIC -* -* @param InstPtr is the DMA instance. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XDmaPs_DoneISR_0(XDmaPs *InstPtr) -{ - XDmaPs_DoneISR_n(InstPtr, 0); -} - -/*****************************************************************************/ -/** -* -* Driver done interrupt service routine for channel 1. We need this done ISR -* mainly because the driver needs to release the DMA program buffer. -* This is the one that connects the GIC -* -* @param InstPtr is the DMA instance. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XDmaPs_DoneISR_1(XDmaPs *InstPtr) -{ - XDmaPs_DoneISR_n(InstPtr, 1); -} - -/*****************************************************************************/ -/** -* -* Driver done interrupt service routine for channel 2. We need this done ISR -* mainly because the driver needs to release the DMA program buffer. -* This is the one that connects the GIC -* -* @param InstPtr is the DMA instance. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XDmaPs_DoneISR_2(XDmaPs *InstPtr) -{ - XDmaPs_DoneISR_n(InstPtr, 2); -} - -/*****************************************************************************/ -/** -* -* Driver done interrupt service routine for channel 3. We need this done ISR -* mainly because the driver needs to release the DMA program buffer. -* This is the one that connects the GIC -* -* @param InstPtr is the DMA instance. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XDmaPs_DoneISR_3(XDmaPs *InstPtr) -{ - XDmaPs_DoneISR_n(InstPtr, 3); -} - -/*****************************************************************************/ -/** -* -* Driver done interrupt service routine for channel 4. We need this done ISR -* mainly because the driver needs to release the DMA program buffer. -* This is the one that connects the GIC -* -* @param InstPtr is the DMA instance. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XDmaPs_DoneISR_4(XDmaPs *InstPtr) -{ - XDmaPs_DoneISR_n(InstPtr, 4); -} - -/*****************************************************************************/ -/** -* -* Driver done interrupt service routine for channel 5. We need this done ISR -* mainly because the driver needs to release the DMA program buffer. -* This is the one that connects the GIC -* -* @param InstPtr is the DMA instance. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XDmaPs_DoneISR_5(XDmaPs *InstPtr) -{ - XDmaPs_DoneISR_n(InstPtr, 5); -} - -/*****************************************************************************/ -/** -* -* Driver done interrupt service routine for channel 6. We need this done ISR -* mainly because the driver needs to release the DMA program buffer. -* This is the one that connects the GIC -* -* @param InstPtr is the DMA instance. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XDmaPs_DoneISR_6(XDmaPs *InstPtr) -{ - XDmaPs_DoneISR_n(InstPtr, 6); -} - -/*****************************************************************************/ -/** -* -* Driver done interrupt service routine for channel 7. We need this done ISR -* mainly because the driver needs to release the DMA program buffer. -* This is the one that connects the GIC -* -* @param InstPtr is the DMA instance. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XDmaPs_DoneISR_7(XDmaPs *InstPtr) -{ - XDmaPs_DoneISR_n(InstPtr, 7); -} - -#ifndef XDMAPS_MAX_WAIT -#define XDMAPS_MAX_WAIT 4000 -#endif - -/****************************************************************************/ -/** -* Use the debug registers to kill the DMA thread. -* -* @param BaseAddr is DMA device base address. -* @param Channel is the DMA channel number. -* @param Thread is Debug thread encoding. -* 0: DMA manager thread, 1: DMA channel. -* -* @return 0 on success, -1 on time out -* -* @note None. -* -*****************************************************************************/ -static int XDmaPs_Exec_DMAKILL(u32 BaseAddr, - unsigned int Channel, - unsigned int Thread) -{ - u32 DbgInst0; - int WaitCount; - - PDBG("Inside XDmaPs_Exec_DMAKILL\r\n"); - - DbgInst0 = XDmaPs_DBGINST0(0, 0x01, Channel, Thread); - - /* wait while debug status is busy */ - WaitCount = 0; - PDBG("Checking DBGSTATUS\r\n"); - while ((XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET) - & XDMAPS_DBGSTATUS_BUSY) - && (WaitCount < XDMAPS_MAX_WAIT)) - WaitCount++; - - if (WaitCount >= XDMAPS_MAX_WAIT) { - /* wait time out */ - xil_printf("PL330 device at %x debug status busy time out\n", - BaseAddr); - - return -1; - } - - /* write debug instruction 0 */ - PDBG("XDmaPs_Exec_DMAKILL: writing DbgInst0 %#08x\n", DbgInst0); - XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST0_OFFSET, DbgInst0); - - PDBG("pl330_exec_dmakill: writing DbgInst1 %#08x\n", 0); - XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST1_OFFSET, 0); - - - /* run the command in DbgInst0 and DbgInst1 */ - XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGCMD_OFFSET, 0); - - return 0; -} - -/****************************************************************************/ -/** -* -* -* Free a buffer of the DMA program buffer. -* @param Pool the DMA program pool. -* @param Buf the DMA program buffer to be release. -* -* @return None -* -* @note None. -* -*****************************************************************************/ -static void XDmaPs_BufPool_Free(XDmaPs_ProgBuf *Pool, void *Buf) -{ - int Index; - int Found = 0; - - Xil_AssertVoid(Pool != NULL); - - for (Index = 0; Index < XDMAPS_MAX_CHAN_BUFS; Index++) { - if (Pool[Index].Buf == Buf) { - if (Pool[Index].Allocated) { - PDBG("Freed buf %d\r\n", Index); - Pool[Index].Allocated = 0; - } else { - PDBG("Trying to free a free buf %d\r\n", Index); - } - Found = 1; - } - } - - if (!Found) { - PDBG("Trying to free a buf that is not in the pool\r\n"); - } -} - -/*****************************************************************************/ -/** -* XDmaPs_Exec_DMAGO - Execute the DMAGO to start a channel. -* -* @param BaseAddr PL330 device base address -* @param Channel Channel number for the device -* @param DmaProg DMA program starting address, this should be DMA address -* -* @return 0 on success, -1 on time out -* -* @note None. -* -****************************************************************************/ -static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg) -{ - char DmaGoProg[8]; - u32 DbgInst0; - u32 DbgInst1; - - int WaitCount; - - PDBG("XDmaPs_Exec_DMAGO: entering\r\n"); - - XDmaPs_Instr_DMAGO(DmaGoProg, Channel, DmaProg, 0); - - DbgInst0 = XDmaPs_DBGINST0(*(DmaGoProg + 1), *DmaGoProg, 0, 0); - DbgInst1 = (u32)DmaProg; - - PDBG("inside XDmaPs_Exec_DMAGO: base %x, Channel %d, DmaProg %x\r\n", - BaseAddr, Channel, DmaProg); - PDBG("inside XDmaPs_Exec_DMAGO: DbgInst0 %x, DbgInst1 %x\r\n", - DbgInst0, DbgInst1); - - /* wait while debug status is busy */ - WaitCount = 0; - PDBG("Checking DBGSTATUS\r\n"); - while ((XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET) - & XDMAPS_DBGSTATUS_BUSY) - && (WaitCount < XDMAPS_MAX_WAIT)) { - PDBG("dbgstatus %x\r\n", - XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)); - - WaitCount++; - } - - if (WaitCount >= XDMAPS_MAX_WAIT) { - xil_printf("PL330 device at %x debug status busy time out\r\n", - BaseAddr); - return -1; - } - - PDBG("dbgstatus idle\r\n"); - - /* write debug instruction 0 */ - XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST0_OFFSET, DbgInst0); - /* write debug instruction 1 */ - XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST1_OFFSET, DbgInst1); - - - /* wait while the DMA Manager is busy */ - WaitCount = 0; - while ((XDmaPs_ReadReg(BaseAddr, - XDMAPS_DS_OFFSET) & XDMAPS_DS_DMA_STATUS) - != XDMAPS_DS_DMA_STATUS_STOPPED - && WaitCount <= XDMAPS_MAX_WAIT) { - PDBG("ds %x\r\n", - XDmaPs_ReadReg(BaseAddr, XDMAPS_DS_OFFSET)); - WaitCount++; - } - - if (WaitCount >= XDMAPS_MAX_WAIT) { - xil_printf("PL330 device at %x debug status busy time out\r\n", - BaseAddr); - return -1; - } - - /* run the command in DbgInst0 and DbgInst1 */ - XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGCMD_OFFSET, 0); - PDBG("XDmaPs_Exec_DMAGO done\r\n"); - - return 0; -} - - -/****************************************************************************/ -/** -* -* It's the generic Done ISR. -* @param InstPtr is the DMA instance. -* @param Channel is the DMA channel numer. -* -* @return None.* -* -* @note None. -* -*****************************************************************************/ -static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel) -{ - - void *DmaProgBuf; - XDmaPs_ChannelData *ChanData; - XDmaPs_Cmd *DmaCmd; - u32 Value; - - ChanData = InstPtr->Chans + Channel; - - PDBG("inside Done ISR Channel %d\r\n", ChanData->ChanId); - - Value = XDmaPs_ReadReg(InstPtr->Config.BaseAddress, - XDMAPS_INTSTATUS_OFFSET); - PDBG("Interrupt status before clearing %x\r\n", Value); - - - /* clear the interrupt status */ - PDBG("Clear the interrupt status %x\r\n", 1<< ChanData->ChanId); - XDmaPs_WriteReg(InstPtr->Config.BaseAddress, - XDMAPS_INTCLR_OFFSET, - 1 << ChanData->ChanId); - - Value = XDmaPs_ReadReg(InstPtr->Config.BaseAddress, - XDMAPS_INTSTATUS_OFFSET); - PDBG("Interrupt status after clearing %x\r\n", Value); - - if (Value) { - PDBG("Interrupt status %x\r\n", Value); - } - - if ((DmaCmd = ChanData->DmaCmdToHw)) { - if (!ChanData->HoldDmaProg) { - DmaProgBuf = (void *)DmaCmd->GeneratedDmaProg; - if (DmaProgBuf) - XDmaPs_BufPool_Free(ChanData->ProgBufPool, - DmaProgBuf); - DmaCmd->GeneratedDmaProg = NULL; - } - - DmaCmd->DmaStatus = 0; - ChanData->DmaCmdToHw = NULL; - ChanData->DmaCmdFromHw = DmaCmd; - - if (ChanData->DoneHandler) - ChanData->DoneHandler(Channel, DmaCmd, - ChanData->DoneRef); - } - -} - - -/****************************************************************************/ -/** -* Prints the content of the buffer in bytes -* @param Buf is the buffer. -* @param Length is the length of the DMA program. -* -* @return None. -* -* @note None. -****************************************************************************/ -static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length) -{ - int Index; - for (Index = 0; Index < Length; Index++) - xil_printf("[%x] %x\r\n", Index, Buf[Index]); - -} -/****************************************************************************/ -/** -* Print the Dma Prog Contents. -* -* @param Cmd is the command buffer. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ - void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd) -{ - if (Cmd->GeneratedDmaProg && Cmd->GeneratedDmaProgLength) { - xil_printf("Generated DMA program (%d):\r\n", - Cmd->GeneratedDmaProgLength); - XDmaPs_Print_DmaProgBuf((char *)Cmd->GeneratedDmaProg, - Cmd->GeneratedDmaProgLength); - } - - if (Cmd->UserDmaProg && Cmd->UserDmaProgLength) { - xil_printf("User defined DMA program (%d):\r\n", - Cmd->UserDmaProgLength); - XDmaPs_Print_DmaProgBuf((char *)Cmd->UserDmaProg, - Cmd->UserDmaProgLength); - } -} - - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v1_06_a/src/xdmaps.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v1_06_a/src/xdmaps.h deleted file mode 100644 index f44608a07cf2ada6bee70823e986aefcc8172975..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v1_06_a/src/xdmaps.h +++ /dev/null @@ -1,317 +0,0 @@ -/***************************************************************************** -* -* (c) Copyright 2009-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -*****************************************************************************/ -/****************************************************************************/ -/** -* -* @file xdmaps.h -* -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------ -------- ---------------------------------------------- -* 1.00 hbm 08/19/10 First Release -* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies -* the maximum number of channels. -* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV -* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h. -* Added the tcl file to automatically generate the -* xparameters.h -* 1.02a sg 05/16/12 Made changes for doxygen and moved some function -* header from the xdmaps.h file to xdmaps.c file -* Other cleanup for coding guidelines and CR 657109 -* and CR 657898 -* The xdmaps_example_no_intr.c example is removed -* as it is using interrupts and is similar to -* the interrupt example - CR 652477 -* 1.03a sg 07/16/2012 changed inline to __inline for CR665681 -* 1.04a nm 10/22/2012 Fixed CR# 681671. -* 1.05a nm 04/15/2013 Fixed CR# 704396. Removed warnings when compiled -* with -Wall and -Wextra option in bsp. -* 05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg() -* function description. -* Fixed CR# 704396. Removed unused variables -* UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg() -* function. -* </pre> -* -*****************************************************************************/ - -#ifndef XDMAPS_H /* prevent circular inclusions */ -#define XDMAPS_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files ********************************/ - -#include "xparameters.h" -#include "xil_types.h" -#include "xil_assert.h" -#include "xstatus.h" - -#include "xdmaps_hw.h" - -/************************** Constant Definitions ****************************/ - -/**************************** Type Definitions ******************************/ - -/** - * This typedef contains configuration information for the device. - */ -typedef struct { - u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddress; /**< Base address of device (IPIF) */ -} XDmaPs_Config; - - -/** DMA channle control structure. It's for AXI bus transaction. - * This struct will be translated into a 32-bit channel control register value. - */ -typedef struct { - unsigned int EndianSwapSize; /**< Endian swap size. */ - unsigned int DstCacheCtrl; /**< Destination cache control */ - unsigned int DstProtCtrl; /**< Destination protection control */ - unsigned int DstBurstLen; /**< Destination burst length */ - unsigned int DstBurstSize; /**< Destination burst size */ - unsigned int DstInc; /**< Destination incrementing or fixed - * address */ - unsigned int SrcCacheCtrl; /**< Source cache control */ - unsigned int SrcProtCtrl; /**< Source protection control */ - unsigned int SrcBurstLen; /**< Source burst length */ - unsigned int SrcBurstSize; /**< Source burst size */ - unsigned int SrcInc; /**< Source incrementing or fixed - * address */ -} XDmaPs_ChanCtrl; - -/** DMA block descriptor stucture. - */ -typedef struct { - u32 SrcAddr; /**< Source starting address */ - u32 DstAddr; /**< Destination starting address */ - unsigned int Length; /**< Number of bytes for the block */ -} XDmaPs_BD; - -/** - * A DMA command consisits of a channel control struct, a block descriptor, - * a user defined program, a pointer pointing to generated DMA program, and - * execution result. - * - */ -typedef struct { - XDmaPs_ChanCtrl ChanCtrl; /**< Channel Control Struct */ - XDmaPs_BD BD; /**< Together with SgLength field, - * it's a scatter-gather list. - */ - void *UserDmaProg; /**< If user wants the driver to - * execute their own DMA program, - * this field points to the DMA - * program. - */ - int UserDmaProgLength; /**< The length of user defined - * DMA program. - */ - - void *GeneratedDmaProg; /**< The DMA program genreated - * by the driver. This field will be - * set if a user invokes the DMA - * program generation function. Or - * the DMA command is finished and - * a user informs the driver not to - * release the program buffer. - * This field has two purposes, one - * is to ask the driver to generate - * a DMA program while the DMAC is - * performaning DMA transactions. The - * other purpose is to debug the - * driver. - */ - int GeneratedDmaProgLength; /**< The length of the DMA program - * generated by the driver - */ - int DmaStatus; /**< 0 on success, otherwise error code - */ - u32 ChanFaultType; /**< Channel fault type in case of fault - */ - u32 ChanFaultPCAddr; /**< Channel fault PC address - */ -} XDmaPs_Cmd; - -/** - * It's the done handler a user can set for a channel - */ -typedef void (*XDmaPsDoneHandler) (unsigned int Channel, - XDmaPs_Cmd *DmaCmd, - void *CallbackRef); - -/** - * It's the fault handler a user can set for a channel - */ -typedef void (*XDmaPsFaultHandler) (unsigned int Channel, - XDmaPs_Cmd *DmaCmd, - void *CallbackRef); - -#define XDMAPS_MAX_CHAN_BUFS 2 -#define XDMAPS_CHAN_BUF_LEN 128 - -/** - * The XDmaPs_ProgBuf is the struct for a DMA program buffer. - */ -typedef struct { - char Buf[XDMAPS_CHAN_BUF_LEN]; /**< The actual buffer the holds the - * content */ - unsigned Len; /**< The actual length of the DMA - * program in bytes. */ - int Allocated; /**< A tag indicating whether the - * buffer is allocated or not */ -} XDmaPs_ProgBuf; - -/** - * The XDmaPs_ChannelData is a struct to book keep individual channel of - * the DMAC. - */ -typedef struct { - unsigned DevId; /**< Device id indicating which DMAC */ - unsigned ChanId; /**< Channel number of the DMAC */ - XDmaPs_ProgBuf ProgBufPool[XDMAPS_MAX_CHAN_BUFS]; /**< A pool of - program buffers*/ - XDmaPsDoneHandler DoneHandler; /**< Done interrupt handler */ - void *DoneRef; /**< Done interrupt callback data */ - XDmaPs_Cmd *DmaCmdToHw; /**< DMA command being executed */ - XDmaPs_Cmd *DmaCmdFromHw; /**< DMA command that is finished. - * This field is for debugging purpose - */ - int HoldDmaProg; /**< A tag indicating whether to hold the - * DMA program after the DMA is done. - */ - -} XDmaPs_ChannelData; - -/** - * The XDmaPs driver instance data structure. A pointer to an instance data - * structure is passed around by functions to refer to a specific driver - * instance. - */ -typedef struct { - XDmaPs_Config Config; /**< Configuration data structure */ - int IsReady; /**< Device is Ready */ - int CacheLength; /**< icache length */ - XDmaPsFaultHandler FaultHandler; /**< fault interrupt handler */ - void *FaultRef; /**< fault call back data */ - XDmaPs_ChannelData Chans[XDMAPS_CHANNELS_PER_DEV]; - /**< - * channel data - */ -} XDmaPs; - -/* - * Functions implemented in xdmaps.c - */ -int XDmaPs_CfgInitialize(XDmaPs *InstPtr, - XDmaPs_Config *Config, - u32 EffectiveAddr); - -int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel, - XDmaPs_Cmd *Cmd, - int HoldDmaProg); - -int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel); -int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel, - XDmaPs_Cmd *Cmd); -int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel, - XDmaPs_Cmd *Cmd); -void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd); - - -int XDmaPs_ResetManager(XDmaPs *InstPtr); -int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel); - - -int XDmaPs_SetDoneHandler(XDmaPs *InstPtr, - unsigned Channel, - XDmaPsDoneHandler DoneHandler, - void *CallbackRef); - -int XDmaPs_SetFaultHandler(XDmaPs *InstPtr, - XDmaPsFaultHandler FaultHandler, - void *CallbackRef); - -void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd); - -/** - * Driver done interrupt service routines for the channels. - * We need this done ISR mainly because the driver needs to release the - * DMA program buffer. This is the one that connects the GIC - */ -void XDmaPs_DoneISR_0(XDmaPs *InstPtr); -void XDmaPs_DoneISR_1(XDmaPs *InstPtr); -void XDmaPs_DoneISR_2(XDmaPs *InstPtr); -void XDmaPs_DoneISR_3(XDmaPs *InstPtr); -void XDmaPs_DoneISR_4(XDmaPs *InstPtr); -void XDmaPs_DoneISR_5(XDmaPs *InstPtr); -void XDmaPs_DoneISR_6(XDmaPs *InstPtr); -void XDmaPs_DoneISR_7(XDmaPs *InstPtr); - -/** - * Driver fault interrupt service routine - */ -void XDmaPs_FaultISR(XDmaPs *InstPtr); - - -/* - * Static loopup function implemented in xdmaps_sinit.c - */ -XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId); - - -/* - * self-test functions in xdmaps_selftest.c - */ -int XDmaPs_SelfTest(XDmaPs *InstPtr); - - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v1_06_a/src/xdmaps_g.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v1_06_a/src/xdmaps_g.c deleted file mode 100644 index f1e83ecbcddffb233d3781f75c70bcc916629bb1..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v1_06_a/src/xdmaps_g.c +++ /dev/null @@ -1,34 +0,0 @@ - -/******************************************************************* -* -* CAUTION: This file is automatically generated by libgen. -* Version: Xilinx EDK 14.7 EDK_P.20131013 -* DO NOT EDIT. -* -* Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. - -* -* Description: Driver configuration -* -*******************************************************************/ - -#include "xparameters.h" -#include "xdmaps.h" - -/* -* The configuration table for devices -*/ - -XDmaPs_Config XDmaPs_ConfigTable[] = -{ - { - XPAR_PS7_DMA_NS_DEVICE_ID, - XPAR_PS7_DMA_NS_BASEADDR - }, - { - XPAR_PS7_DMA_S_DEVICE_ID, - XPAR_PS7_DMA_S_BASEADDR - } -}; - - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v1_06_a/src/xdmaps_hw.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v1_06_a/src/xdmaps_hw.c deleted file mode 100644 index 98fbabd8c323fd8a42b5ce950fc02457ddf00d1b..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v1_06_a/src/xdmaps_hw.c +++ /dev/null @@ -1,122 +0,0 @@ -/***************************************************************************** -* -* (c) Copyright 2009-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -*****************************************************************************/ -/****************************************************************************/ -/** -* -* @file xdmaps_hw.c -* -* This file contains the implementation of the interface reset functionality -* for XDmaPs driver. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------ -------- ---------------------------------------------- -* 1.06a kpc 10/07/13 First release -* </pre> -* -*****************************************************************************/ - -/***************************** Include Files ********************************/ -#include "xdmaps_hw.h" - -/************************** Constant Definitions ****************************/ - -/**************************** Type Definitions ******************************/ - -/***************** Macros (Inline Functions) Definitions ********************/ -#ifndef XDMAPS_MAX_WAIT -#define XDMAPS_MAX_WAIT 4000 -#endif -/************************** Function Prototypes *****************************/ - -/************************** Variable Definitions ****************************/ - -/*****************************************************************************/ -/** -* This function perform the reset sequence to the given dmaps interface by -* configuring the appropriate control bits in the dmaps specifc registers -* the dmaps reset squence involves the following steps -* Disable all the interuupts -* Clear the pending interrupts -* Kill all the active channel threads -* Kill the manager thread -* -* @param BaseAddress of the interface -* -* @return N/A -* -* @note -* This function will not modify the slcr registers that are relavant for -* dmaps controller -******************************************************************************/ -void XDmaPs_ResetHw(u32 BaseAddress) -{ - u32 DbgInst; - u32 WaitCount = 0; - u32 ChanIndex; - - /* Disable all the interrupts */ - XDmaPs_WriteReg(BaseAddress, XDMAPS_INTEN_OFFSET, 0x00); - /* Clear the interrupts */ - XDmaPs_WriteReg(BaseAddress, XDMAPS_INTCLR_OFFSET, XDMAPS_INTCLR_ALL_MASK); - /* Kill the dma channel threads */ - for (ChanIndex=0; ChanIndex < XDMAPS_CHANNELS_PER_DEV; ChanIndex++) { - while ((XDmaPs_ReadReg(BaseAddress, XDMAPS_DBGSTATUS_OFFSET) - & XDMAPS_DBGSTATUS_BUSY) - && (WaitCount < XDMAPS_MAX_WAIT)) - WaitCount++; - - DbgInst = XDmaPs_DBGINST0(0, 0x01, ChanIndex, 1); - XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst); - XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0); - XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0); - } - /* Kill the manager thread */ - DbgInst = XDmaPs_DBGINST0(0, 0x01, 0, 0); - XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst); - XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0); - XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0); -} - - - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v1_06_a/src/xdmaps_hw.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v1_06_a/src/xdmaps_hw.h deleted file mode 100644 index 1fc33e547f42af3c5b9873114aa7a5de4c46cc55..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v1_06_a/src/xdmaps_hw.h +++ /dev/null @@ -1,299 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xdmaps_hw.h -* -* This header file contains the hardware interface of an XDmaPs device. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ---------------------------------------------- -* 1.00a hbm 08/18/10 First Release -* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies -* the maximum number of channels. -* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV -* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h -* 1.02a sg 05/16/12 Made changes for doxygen -* 1.06a kpc 07/10/13 Added function prototype -* </pre> -* -******************************************************************************/ - -#ifndef XDMAPS_HW_H /* prevent circular inclusions */ -#define XDMAPS_HW_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xil_io.h" - -/************************** Constant Definitions *****************************/ - -/** @name Register Map - * - * Register offsets for the DMAC. - * @{ - */ - -#define XDMAPS_DS_OFFSET 0x000 /* DMA Status Register */ -#define XDMAPS_DPC_OFFSET 0x004 /* DMA Program Counter Rregister */ -#define XDMAPS_INTEN_OFFSET 0X020 /* DMA Interrupt Enable Register */ -#define XDMAPS_ES_OFFSET 0x024 /* DMA Event Status Register */ -#define XDMAPS_INTSTATUS_OFFSET 0x028 /* DMA Interrupt Status Register - */ -#define XDMAPS_INTCLR_OFFSET 0x02c /* DMA Interrupt Clear Register */ -#define XDMAPS_FSM_OFFSET 0x030 /* DMA Fault Status DMA Manager - * Register - */ -#define XDMAPS_FSC_OFFSET 0x034 /* DMA Fault Status DMA Chanel Register - */ -#define XDMAPS_FTM_OFFSET 0x038 /* DMA Fault Type DMA Manager Register */ - -#define XDMAPS_FTC0_OFFSET 0x040 /* DMA Fault Type for DMA Channel 0 */ -/* - * The offset for the rest of the FTC registers is calculated as - * FTC0 + dev_chan_num * 4 - */ -#define XDmaPs_FTCn_OFFSET(ch) (XDMAPS_FTC0_OFFSET + (ch) * 4) - -#define XDMAPS_CS0_OFFSET 0x100 /* Channel Status for DMA Channel 0 */ -/* - * The offset for the rest of the CS registers is calculated as - * CS0 + * dev_chan_num * 0x08 - */ -#define XDmaPs_CSn_OFFSET(ch) (XDMAPS_CS0_OFFSET + (ch) * 8) - -#define XDMAPS_CPC0_OFFSET 0x104 /* Channel Program Counter for DMA - * Channel 0 - */ -/* - * The offset for the rest of the CPC registers is calculated as - * CPC0 + dev_chan_num * 0x08 - */ -#define XDmaPs_CPCn_OFFSET(ch) (XDMAPS_CPC0_OFFSET + (ch) * 8) - -#define XDMAPS_SA_0_OFFSET 0x400 /* Source Address Register for DMA - * Channel 0 - */ -/* The offset for the rest of the SA registers is calculated as - * SA_0 + dev_chan_num * 0x20 - */ -#define XDmaPs_SA_n_OFFSET(ch) (XDMAPS_SA_0_OFFSET + (ch) * 0x20) - -#define XDMAPS_DA_0_OFFSET 0x404 /* Destination Address Register for - * DMA Channel 0 - */ -/* The offset for the rest of the DA registers is calculated as - * DA_0 + dev_chan_num * 0x20 - */ -#define XDmaPs_DA_n_OFFSET(ch) (XDMAPS_DA_0_OFFSET + (ch) * 0x20) - -#define XDMAPS_CC_0_OFFSET 0x408 /* Channel Control Register for - * DMA Channel 0 - */ -/* - * The offset for the rest of the CC registers is calculated as - * CC_0 + dev_chan_num * 0x20 - */ -#define XDmaPs_CC_n_OFFSET(ch) (XDMAPS_CC_0_OFFSET + (ch) * 0x20) - -#define XDMAPS_LC0_0_OFFSET 0x40C /* Loop Counter 0 for DMA Channel 0 */ -/* - * The offset for the rest of the LC0 registers is calculated as - * LC_0 + dev_chan_num * 0x20 - */ -#define XDmaPs_LC0_n_OFFSET(ch) (XDMAPS_LC0_0_OFFSET + (ch) * 0x20) -#define XDMAPS_LC1_0_OFFSET 0x410 /* Loop Counter 1 for DMA Channel 0 */ -/* - * The offset for the rest of the LC1 registers is calculated as - * LC_0 + dev_chan_num * 0x20 - */ -#define XDmaPs_LC1_n_OFFSET(ch) (XDMAPS_LC1_0_OFFSET + (ch) * 0x20) - -#define XDMAPS_DBGSTATUS_OFFSET 0xD00 /* Debug Status Register */ -#define XDMAPS_DBGCMD_OFFSET 0xD04 /* Debug Command Register */ -#define XDMAPS_DBGINST0_OFFSET 0xD08 /* Debug Instruction 0 Register */ -#define XDMAPS_DBGINST1_OFFSET 0xD0C /* Debug Instruction 1 Register */ - -#define XDMAPS_CR0_OFFSET 0xE00 /* Configuration Register 0 */ -#define XDMAPS_CR1_OFFSET 0xE04 /* Configuration Register 1 */ -#define XDMAPS_CR2_OFFSET 0xE08 /* Configuration Register 2 */ -#define XDMAPS_CR3_OFFSET 0xE0C /* Configuration Register 3 */ -#define XDMAPS_CR4_OFFSET 0xE10 /* Configuration Register 4 */ -#define XDMAPS_CRDN_OFFSET 0xE14 /* Configuration Register Dn */ - -#define XDMAPS_PERIPH_ID_0_OFFSET 0xFE0 /* Peripheral Identification - * Register 0 - */ -#define XDMAPS_PERIPH_ID_1_OFFSET 0xFE4 /* Peripheral Identification - * Register 1 - */ -#define XDMAPS_PERIPH_ID_2_OFFSET 0xFE8 /* Peripheral Identification - * Register 2 - */ -#define XDMAPS_PERIPH_ID_3_OFFSET 0xFEC /* Peripheral Identification - * Register 3 - */ -#define XDMAPS_PCELL_ID_0_OFFSET 0xFF0 /* PrimeCell Identification - * Register 0 - */ -#define XDMAPS_PCELL_ID_1_OFFSET 0xFF4 /* PrimeCell Identification - * Register 1 - */ -#define XDMAPS_PCELL_ID_2_OFFSET 0xFF8 /* PrimeCell Identification - * Register 2 - */ -#define XDMAPS_PCELL_ID_3_OFFSET 0xFFC /* PrimeCell Identification - * Register 3 - */ - -/* - * Some useful register masks - */ -#define XDMAPS_DS_DMA_STATUS 0x0F /* DMA status mask */ -#define XDMAPS_DS_DMA_STATUS_STOPPED 0x00 /* debug status busy mask */ - -#define XDMAPS_DBGSTATUS_BUSY 0x01 /* debug status busy mask */ - -#define XDMAPS_CS_ACTIVE_MASK 0x07 /* channel status active mask, - * llast 3 bits of CS register - */ - -#define XDMAPS_CR1_I_CACHE_LEN_MASK 0x07 /* i_cache_len mask */ - - -/* - * XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register. - * @b1: Instruction byte 1 - * @b0: Instruction byte 0 - * @ch: Channel number - * @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel - */ -#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \ - (((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1))) - -/* @} */ - -/** @name Control Register - * - * The Control register (CR) controls the major functions of the device. - * - * Control Register Bit Definition - */ - -/* @}*/ - - -#define XDMAPS_CHANNELS_PER_DEV 8 - - -/** @name Mode Register - * - * The mode register (MR) defines the mode of transfer as well as the data - * format. If this register is modified during transmission or reception, - * data validity cannot be guaranteed. - * - * Mode Register Bit Definition - * @{ - */ - -/* @} */ - - -/** @name Interrupt Registers - * - * Interrupt control logic uses the interrupt enable register (IER) and the - * interrupt disable register (IDR) to set the value of the bits in the - * interrupt mask register (IMR). The IMR determines whether to pass an - * interrupt to the interrupt status register (ISR). - * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an - * interrupt. IMR and ISR are read only, and IER and IDR are write only. - * Reading either IER or IDR returns 0x00. - * - * All four registers have the same bit definitions. - * - * @{ - */ - -/* @} */ -#define XDMAPS_INTCLR_ALL_MASK 0xFF - -#define XDmaPs_ReadReg(BaseAddress, RegOffset) \ - Xil_In32((BaseAddress) + (RegOffset)) - -/***************************************************************************/ -/** -* Write a DMAC register. -* -* @param BaseAddress contains the base address of the device. -* @param RegOffset contains the offset from the base address of the device. -* @param RegisterValue is the value to be written to the register. -* -* @return None. -* -* @note -* C-Style signature: -* void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset, -* u32 RegisterValue) -******************************************************************************/ -#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ - Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue)) -/************************** Variable Definitions *****************************/ - -/************************** Function Prototypes *****************************/ -/* - * Perform reset operation to the dmaps interface - */ -void XDmaPs_ResetHw(u32 BaseAddr); -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v1_06_a/src/xdmaps_selftest.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v1_06_a/src/xdmaps_selftest.c deleted file mode 100644 index cafbd7dfb6133c66609005ffbfb586292b946922..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v1_06_a/src/xdmaps_selftest.c +++ /dev/null @@ -1,116 +0,0 @@ -/***************************************************************************** -* -* (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -*****************************************************************************/ -/****************************************************************************/ -/** -* -* @file xdmaps_selftest.c -* -* This file contains the self-test functions for the XDmaPs driver. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------ -------- ----------------------------------------------- -* 1.00 hbm 03/29/2010 First Release -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xstatus.h" -#include "xdmaps.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Variable Definitions *****************************/ - - -/************************** Function Prototypes ******************************/ - - -/****************************************************************************/ -/** -* -* This function runs a self-test on the driver and hardware device. This self -* test performs a local loopback and verifies data can be sent and received. -* -* The time for this test is proportional to the baud rate that has been set -* prior to calling this function. -* -* The mode and control registers are restored before return. -* -* @param InstPtr is a pointer to the XDmaPs instance -* -* @return -* -* - XST_SUCCESS if the test was successful -* - XST_FAILURE if the test failed -* -* @note -* -* This function can hang if the hardware is not functioning properly. -* -******************************************************************************/ -int XDmaPs_SelfTest(XDmaPs *InstPtr) -{ - u32 BaseAddr = InstPtr->Config.BaseAddress; - int i; - - if (XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET) - & XDMAPS_DBGSTATUS_BUSY) - return XST_FAILURE; - - for (i = 0; i < XDMAPS_CHANNELS_PER_DEV; i++) { - if (XDmaPs_ReadReg(BaseAddr, - XDmaPs_CSn_OFFSET(i))) - return XST_FAILURE; - } - return XST_SUCCESS; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v1_06_a/src/xdmaps_sinit.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v1_06_a/src/xdmaps_sinit.c deleted file mode 100644 index 447624e365e2049c1ddfbe5acb2dcced54868c49..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/dmaps_v1_06_a/src/xdmaps_sinit.c +++ /dev/null @@ -1,110 +0,0 @@ -/***************************************************************************** -* -* (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -*****************************************************************************/ -/****************************************************************************/ -/** -* -* @file xdmaps_sinit.c -* -* The implementation of the XDmaPs driver's static initialzation -* functionality. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00 hbm 08/13/10 First Release -* </pre> -* -*****************************************************************************/ - -/***************************** Include Files ********************************/ - -#include "xstatus.h" -#include "xparameters.h" -#include "xdmaps.h" - -/************************** Constant Definitions ****************************/ - -/**************************** Type Definitions ******************************/ - - -/***************** Macros (Inline Functions) Definitions ********************/ - - -/************************** Variable Definitions ****************************/ -extern XDmaPs_Config XDmaPs_ConfigTable[]; - -/************************** Function Prototypes *****************************/ - -/****************************************************************************/ -/** -* -* Looks up the device configuration based on the unique device ID. The table -* contains the configuration info for each device in the system. -* -* @param DeviceId contains the ID of the device -* -* @return -* -* A pointer to the configuration structure or NULL if the specified device -* is not in the system. -* -* @note -* -* None. -* -******************************************************************************/ -XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId) -{ - XDmaPs_Config *CfgPtr = NULL; - - int i; - - for (i = 0; i < XPAR_XDMAPS_NUM_INSTANCES; i++) { - if (XDmaPs_ConfigTable[i].DeviceId == DeviceId) { - CfgPtr = &XDmaPs_ConfigTable[i]; - break; - } - } - - return CfgPtr; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/Makefile b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/Makefile deleted file mode 100644 index ba187001dea24d925d971b9e42106ba9f040e43b..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -COMPILER= -ARCHIVER= -CP=cp -COMPILER_FLAGS= -EXTRA_COMPILER_FLAGS= -LIB=libxil.a - -CC_FLAGS = $(COMPILER_FLAGS) -ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) - -RELEASEDIR=../../../lib -INCLUDEDIR=../../../include -INCLUDES=-I./. -I${INCLUDEDIR} - -OUTS = *.o - -LIBSOURCES:=*.c -INCLUDEFILES:=*.h - -OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) - -libs: banner xemacps_libs clean - -%.o: %.c - ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< - -banner: - echo "Compiling emacps" - -xemacps_libs: ${OBJECTS} - $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} - -.PHONY: include -include: xemacps_includes - -xemacps_includes: - ${CP} ${INCLUDEFILES} ${INCLUDEDIR} - -clean: - rm -rf ${OBJECTS} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps.c deleted file mode 100644 index 8064f7aef43eefcd3e623bfc7dd970a8303d7d8d..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps.c +++ /dev/null @@ -1,401 +0,0 @@ -/* $Id: xemacps.c,v 1.1.2.3 2011/05/17 12:00:33 anirudh Exp $ */ -/****************************************************************************** -* -* (c) Copyright 2010 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xemacps.c -* -* The XEmacPs driver. Functions in this file are the minimum required functions -* for this driver. See xemacps.h for a detailed description of the driver. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.00a wsy 01/10/10 First release -* </pre> -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xemacps.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - -void XEmacPs_StubHandler(void); /* Default handler routine */ - -/************************** Variable Definitions *****************************/ - - -/*****************************************************************************/ -/** -* Initialize a specific XEmacPs instance/driver. The initialization entails: -* - Initialize fields of the XEmacPs instance structure -* - Reset hardware and apply default options -* - Configure the DMA channels -* -* The PHY is setup independently from the device. Use the MII or whatever other -* interface may be present for setup. -* -* @param InstancePtr is a pointer to the instance to be worked on. -* @param CfgPtr is the device configuration structure containing required -* hardware build data. -* @param EffectiveAddress is the base address of the device. If address -* translation is not utilized, this parameter can be passed in using -* CfgPtr->Config.BaseAddress to specify the physical base address. -* -* @return -* - XST_SUCCESS if initialization was successful -* -******************************************************************************/ -int XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr, - u32 EffectiveAddress) -{ - /* Verify arguments */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(CfgPtr != NULL); - - /* Set device base address and ID */ - InstancePtr->Config.DeviceId = CfgPtr->DeviceId; - InstancePtr->Config.BaseAddress = EffectiveAddress; - - /* Set callbacks to an initial stub routine */ - InstancePtr->SendHandler = (XEmacPs_Handler) XEmacPs_StubHandler; - InstancePtr->RecvHandler = (XEmacPs_Handler) XEmacPs_StubHandler; - InstancePtr->ErrorHandler = (XEmacPs_ErrHandler) XEmacPs_StubHandler; - - /* Reset the hardware and set default options */ - InstancePtr->IsReady = XIL_COMPONENT_IS_READY; - XEmacPs_Reset(InstancePtr); - - return (XST_SUCCESS); -} - - -/*****************************************************************************/ -/** -* Start the Ethernet controller as follows: -* - Enable transmitter if XTE_TRANSMIT_ENABLE_OPTION is set -* - Enable receiver if XTE_RECEIVER_ENABLE_OPTION is set -* - Start the SG DMA send and receive channels and enable the device -* interrupt -* -* @param InstancePtr is a pointer to the instance to be worked on. -* -* @return N/A -* -* @note -* Hardware is configured with scatter-gather DMA, the driver expects to start -* the scatter-gather channels and expects that the user has previously set up -* the buffer descriptor lists. -* -* This function makes use of internal resources that are shared between the -* Start, Stop, and Set/ClearOptions functions. So if one task might be setting -* device options while another is trying to start the device, the user is -* required to provide protection of this shared data (typically using a -* semaphore). -* -* This function must not be preempted by an interrupt that may service the -* device. -* -******************************************************************************/ -void XEmacPs_Start(XEmacPs *InstancePtr) -{ - u32 Reg; - - /* Assert bad arguments and conditions */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(InstancePtr->RxBdRing.BaseBdAddr != 0); - Xil_AssertVoid(InstancePtr->TxBdRing.BaseBdAddr != 0); - - /* If already started, then there is nothing to do */ - if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) { - return; - } - - /* Start DMA */ - /* When starting the DMA channels, both transmit and receive sides - * need an initialized BD list. - */ - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_RXQBASE_OFFSET, - InstancePtr->RxBdRing.BaseBdAddr); - - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_TXQBASE_OFFSET, - InstancePtr->TxBdRing.BaseBdAddr); - - /* clear any existed int status */ - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET, - XEMACPS_IXR_ALL_MASK); - - /* Enable transmitter if not already enabled */ - if (InstancePtr->Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) { - Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCTRL_OFFSET); - if (!(Reg & XEMACPS_NWCTRL_TXEN_MASK)) { - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCTRL_OFFSET, - Reg | XEMACPS_NWCTRL_TXEN_MASK); - } - } - - /* Enable receiver if not already enabled */ - if (InstancePtr->Options & XEMACPS_RECEIVER_ENABLE_OPTION) { - Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCTRL_OFFSET); - if (!(Reg & XEMACPS_NWCTRL_RXEN_MASK)) { - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCTRL_OFFSET, - Reg | XEMACPS_NWCTRL_RXEN_MASK); - } - } - - /* Enable TX and RX interrupts */ - XEmacPs_IntEnable(InstancePtr, (XEMACPS_IXR_TX_ERR_MASK | - XEMACPS_IXR_RX_ERR_MASK | XEMACPS_IXR_FRAMERX_MASK | - XEMACPS_IXR_TXCOMPL_MASK)); - - /* Mark as started */ - InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED; - - return; -} - - -/*****************************************************************************/ -/** -* Gracefully stop the Ethernet MAC as follows: -* - Disable all interrupts from this device -* - Stop DMA channels -* - Disable the tansmitter and receiver -* -* Device options currently in effect are not changed. -* -* This function will disable all interrupts. Default interrupts settings that -* had been enabled will be restored when XEmacPs_Start() is called. -* -* @param InstancePtr is a pointer to the instance to be worked on. -* -* @note -* This function makes use of internal resources that are shared between the -* Start, Stop, SetOptions, and ClearOptions functions. So if one task might be -* setting device options while another is trying to start the device, the user -* is required to provide protection of this shared data (typically using a -* semaphore). -* -* Stopping the DMA channels causes this function to block until the DMA -* operation is complete. -* -******************************************************************************/ -void XEmacPs_Stop(XEmacPs *InstancePtr) -{ - u32 Reg; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* Disable all interrupts */ - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET, - XEMACPS_IXR_ALL_MASK); - - /* Disable the receiver & transmitter */ - Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCTRL_OFFSET); - Reg &= ~XEMACPS_NWCTRL_RXEN_MASK; - Reg &= ~XEMACPS_NWCTRL_TXEN_MASK; - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCTRL_OFFSET, Reg); - - /* Mark as stopped */ - InstancePtr->IsStarted = 0; -} - - -/*****************************************************************************/ -/** -* Perform a graceful reset of the Ethernet MAC. Resets the DMA channels, the -* transmitter, and the receiver. -* -* Steps to reset -* - Stops transmit and receive channels -* - Stops DMA -* - Configure transmit and receive buffer size to default -* - Clear transmit and receive status register and counters -* - Clear all interrupt sources -* - Clear phy (if there is any previously detected) address -* - Clear MAC addresses (1-4) as well as Type IDs and hash value -* -* All options are placed in their default state. Any frames in the -* descriptor lists will remain in the lists. The side effect of doing -* this is that after a reset and following a restart of the device, frames -* were in the list before the reset may be transmitted or received. -* -* The upper layer software is responsible for re-configuring (if necessary) -* and restarting the MAC after the reset. Note also that driver statistics -* are not cleared on reset. It is up to the upper layer software to clear the -* statistics if needed. -* -* When a reset is required, the driver notifies the upper layer software of -* this need through the ErrorHandler callback and specific status codes. -* The upper layer software is responsible for calling this Reset function -* and then re-configuring the device. -* -* @param InstancePtr is a pointer to the instance to be worked on. -* -******************************************************************************/ -void XEmacPs_Reset(XEmacPs *InstancePtr) -{ - u32 Reg; - u8 i; - char EmacPs_zero_MAC[6] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* Stop the device and reset hardware */ - XEmacPs_Stop(InstancePtr); - InstancePtr->Options = XEMACPS_DEFAULT_OPTIONS; - - /* Setup hardware with default values */ - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCTRL_OFFSET, - (XEMACPS_NWCTRL_STATCLR_MASK | - XEMACPS_NWCTRL_MDEN_MASK) & - ~XEMACPS_NWCTRL_LOOPEN_MASK); - - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCFG_OFFSET, - XEMACPS_NWCFG_100_MASK | - XEMACPS_NWCFG_FDEN_MASK | - XEMACPS_NWCFG_UCASTHASHEN_MASK); - - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_DMACR_OFFSET, - ((((XEMACPS_RX_BUF_SIZE / XEMACPS_RX_BUF_UNIT) + - ((XEMACPS_RX_BUF_SIZE % - XEMACPS_RX_BUF_UNIT) ? 1 : 0)) << - XEMACPS_DMACR_RXBUF_SHIFT) & - XEMACPS_DMACR_RXBUF_MASK) | - XEMACPS_DMACR_RXSIZE_MASK | - XEMACPS_DMACR_TXSIZE_MASK); - - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_TXSR_OFFSET, 0x0); - - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_RXQBASE_OFFSET, 0x0); - - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_TXQBASE_OFFSET, 0x0); - - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_RXSR_OFFSET, 0x0); - - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET, - XEMACPS_IXR_ALL_MASK); - - Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_ISR_OFFSET); - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET, - Reg); - - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_PHYMNTNC_OFFSET, 0x0); - - XEmacPs_ClearHash(InstancePtr); - - for (i = 1; i < 5; i++) { - XEmacPs_SetMacAddress(InstancePtr, EmacPs_zero_MAC, i); - XEmacPs_SetTypeIdCheck(InstancePtr, 0x0, i); - } - - /* clear all counters */ - for (i = 0; i < (XEMACPS_LAST_OFFSET - XEMACPS_OCTTXL_OFFSET) / 4; - i++) { - XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_OCTTXL_OFFSET + i * 4); - } - - /* Disable the receiver */ - Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCTRL_OFFSET); - Reg &= ~XEMACPS_NWCTRL_RXEN_MASK; - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCTRL_OFFSET, Reg); - - /* Sync default options with hardware but leave receiver and - * transmitter disabled. They get enabled with XEmacPs_Start() if - * XEMACPS_TRANSMITTER_ENABLE_OPTION and - * XEMACPS_RECEIVER_ENABLE_OPTION are set. - */ - XEmacPs_SetOptions(InstancePtr, InstancePtr->Options & - ~(XEMACPS_TRANSMITTER_ENABLE_OPTION | - XEMACPS_RECEIVER_ENABLE_OPTION)); - - XEmacPs_ClearOptions(InstancePtr, ~InstancePtr->Options); -} - - -/******************************************************************************/ -/** - * This is a stub for the asynchronous callbacks. The stub is here in case the - * upper layer forgot to set the handler(s). On initialization, all handlers are - * set to this callback. It is considered an error for this handler to be - * invoked. - * - ******************************************************************************/ -void XEmacPs_StubHandler(void) -{ - Xil_AssertVoidAlways(); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps.h deleted file mode 100644 index 81e750c06c82484285dc6b1e48f75ad0593875f7..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps.h +++ /dev/null @@ -1,716 +0,0 @@ -/***************************************************************************** -* -* (c) Copyright 2010-11 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -*****************************************************************************/ -/****************************************************************************/ -/** - * - * @file xemacps.h - * - * The Xilinx Embedded Processor Block Ethernet driver. - * - * For a full description of XEMACPS features, please see the hardware spec. - * This driver supports the following features: - * - Memory mapped access to host interface registers - * - Statistics counter registers for RMON/MIB - * - API for interrupt driven frame transfers for hardware configured DMA - * - Virtual memory support - * - Unicast, broadcast, and multicast receive address filtering - * - Full and half duplex operation - * - Automatic PAD & FCS insertion and stripping - * - Flow control - * - Support up to four 48bit addresses - * - Address checking for four specific 48bit addresses - * - VLAN frame support - * - Pause frame support - * - Large frame support up to 1536 bytes - * - Checksum offload - * - * <b>Driver Description</b> - * - * The device driver enables higher layer software (e.g., an application) to - * communicate to the XEmacPs. The driver handles transmission and reception - * of Ethernet frames, as well as configuration and control. No pre or post - * processing of frame data is performed. The driver does not validate the - * contents of an incoming frame in addition to what has already occurred in - * hardware. - * A single device driver can support multiple devices even when those devices - * have significantly different configurations. - * - * <b>Initialization & Configuration</b> - * - * The XEmacPs_Config structure is used by the driver to configure itself. - * This configuration structure is typically created by the tool-chain based - * on hardware build properties. - * - * The driver instance can be initialized in - * - * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a - * configuration structure provided by the caller. If running in a system - * with address translation, the provided virtual memory base address - * replaces the physical address present in the configuration structure. - * - * The device supports DMA only as current development plan. No FIFO mode is - * supported. The driver expects to start the DMA channels and expects that - * the user has set up the buffer descriptor lists. - * - * <b>Interrupts and Asynchronous Callbacks</b> - * - * The driver has no dependencies on the interrupt controller. When an - * interrupt occurs, the handler will perform a small amount of - * housekeeping work, determine the source of the interrupt, and call the - * appropriate callback function. All callbacks are registered by the user - * level application. - * - * <b>Virtual Memory</b> - * - * All virtual to physical memory mappings must occur prior to accessing the - * driver API. - * - * For DMA transactions, user buffers supplied to the driver must be in terms - * of their physical address. - * - * <b>DMA</b> - * - * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames. - * These BDs are typically chained together into a list the hardware follows - * when transferring data in and out of the packet buffers. Each BD describes - * a memory region containing either a full or partial Ethernet packet. - * - * Interrupt coalescing is not suppoted from this built-in DMA engine. - * - * This API requires the user to understand how the DMA operates. The - * following paragraphs provide some explanation, but the user is encouraged - * to read documentation in xemacps_bdring.h as well as study example code - * that accompanies this driver. - * - * The API is designed to get BDs to and from the DMA engine in the most - * efficient means possible. The first step is to establish a memory region - * to contain all BDs for a specific channel. This is done with - * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will - * follow as BDs are processed. The ring will consist of a user defined number - * of BDs which will all be partially initialized. For example on the transmit - * channel, the driver will initialize all BDs' so that they are configured - * for transmit. The more fields that can be permanently setup at - * initialization, then the fewer accesses will be needed to each BD while - * the DMA engine is in operation resulting in better throughput and CPU - * utilization. The best case initialization would require the user to set - * only a frame buffer address and length prior to submitting the BD to the - * engine. - * - * BDs move through the engine with the help of functions - * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(), - * and XEmacPs_BdRingFree(). - * All these functions handle BDs that are in place. That is, there are no - * copies of BDs kept anywhere and any BD the user interacts with is an actual - * BD from the same ring hardware accesses. - * - * BDs in the ring go through a series of states as follows: - * 1. Idle. The driver controls BDs in this state. - * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to - * reserve BD(s). Once allocated, the user may setup the BD(s) with - * frame buffer address, length, and other attributes. The user controls - * BDs in this state. - * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs - * in this state are either waiting to be processed by hardware, are in - * process, or have been processed. The DMA engine controls BDs in this - * state. - * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the - * user. Once retrieved, the user can examine each BD for the outcome of - * the DMA transfer. The user controls BDs in this state. After examining - * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back - * into state 1. - * - * Each of the four BD accessor functions operate on a set of BDs. A set is - * defined as a segment of the BD ring consisting of one or more BDs. The user - * views the set as a pointer to the first BD along with the number of BDs for - * that set. The set can be navigated by using macros XEmacPs_BdNext(). The - * user must exercise extreme caution when changing BDs in a set as there is - * nothing to prevent doing a mBdNext past the end of the set and modifying a - * BD out of bounds. - * - * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as - * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in - * tandem. The same BD set retrieved with BdRingAlloc should be the same one - * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and - * BdRIngFree. - * - * <b>Alignment & Data Cache Restrictions</b> - * - * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte - * aligned. Please reference xemacps_bd.h for cache related macros. - * - * DMA Tx: - * - * - If frame buffers exist in cached memory, then they must be flushed - * prior to committing them to hardware. - * - * DMA Rx: - * - * - If frame buffers exist in cached memory, then the cache must be - * invalidated for the memory region containing the frame prior to data - * access - * - * Both cache invalidate/flush are taken care of in driver code. - * - * <b>Buffer Copying</b> - * - * The driver is designed for a zero-copy buffer scheme. That is, the driver - * will not copy buffers. This avoids potential throughput bottlenecks within - * the driver. If byte copying is required, then the transfer will take longer - * to complete. - * - * <b>Checksum Offloading</b> - * - * The Embedded Processor Block Ethernet can be configured to perform IP, TCP - * and UDP checksum offloading in both receive and transmit directions. - * - * IP packets contain a 16-bit checksum field, which is the 16-bit 1s - * complement of the 1s complement sum of all 16-bit words in the header. - * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit - * 1s complement of the 1s complement sum of all 16-bit words in the header, - * the data and a conceptual pseudo header. - * - * To calculate these checksums in software requires each byte of the packet - * to be read. For TCP and UDP this can use a large amount of processing power. - * Offloading the checksum calculation to hardware can result in significant - * performance improvements. - * - * The transmit checksum offload is only available to use DMA in packet buffer - * mode. This is because the complete frame to be transmitted must be read - * into the packet buffer memory before the checksum can be calculated and - * written to the header at the beginning of the frame. - * - * For IP, TCP or UDP receive checksum offload to be useful, the operating - * system containing the protocol stack must be aware that this offload is - * available so that it can make use of the fact that the hardware has verified - * the checksum. - * - * When receive checksum offloading is enabled in the hardware, the IP header - * checksum is checked, where the packet meets the following criteria: - * - * 1. If present, the VLAN header must be four octets long and the CFI bit - * must not be set. - * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP - * encoding. - * 3. IP v4 packet. - * 4. IP header is of a valid length. - * 5. Good IP header checksum. - * 6. No IP fragmentation. - * 7. TCP or UDP packet. - * - * When an IP, TCP or UDP frame is received, the receive buffer descriptor - * gives an indication if the hardware was able to verify the checksums. - * There is also an indication if the frame had SNAP encapsulation. These - * indication bits will replace the type ID match indication bits when the - * receive checksum offload is enabled. - * - * If any of the checksums are verified incorrect by the hardware, the packet - * is discarded and the appropriate statistics counter incremented. - * - * <b>PHY Interfaces</b> - * - * RGMII 1.3 is the only interface supported. - * - * <b>Asserts</b> - * - * Asserts are used within all Xilinx drivers to enforce constraints on - * parameters. Asserts can be turned off on a system-wide basis by defining, - * at compile time, the NDEBUG identifier. By default, asserts are turned on - * and it is recommended that users leave asserts on during development. For - * deployment use -DNDEBUG compiler switch to remove assert code. - * - * @note - * - * Xilinx drivers are typically composed of two parts, one is the driver - * and the other is the adapter. The driver is independent of OS and processor - * and is intended to be highly portable. The adapter is OS-specific and - * facilitates communication between the driver and an OS. - * This driver is intended to be RTOS and processor independent. Any needs for - * dynamic memory management, threads or thread mutual exclusion, or cache - * control must be satisfied bythe layer above this driver. - * - * <pre> - * MODIFICATION HISTORY: - * - * Ver Who Date Changes - * ----- ---- -------- ------------------------------------------------------- - * 1.00a wsy 01/10/10 First release - * 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx in file - * xemacps_bdring.c is modified. Earlier it was checking for - * "BdLimit"(passed argument) number of BDs for finding out - * which BDs are successfully processed. Now one more check - * is added. It looks for BDs till the current BD pointer - * reaches HwTail. By doing this processing time is saved. - * 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file - * xemacps_bdring.c is modified. Now start of packet is - * searched for returning the number of BDs processed. - * 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH - * registers. Added a new API to set the bust length. - * Added some new hash-defines. - * 1.03a asa 01/23/12 Fix for CR #692702 which updates error handling for - * Rx errors. Under heavy Rx traffic, there will be a large - * number of errors related to receive buffer not available. - * Because of a HW bug (SI #692601), under such heavy errors, - * the Rx data path can become unresponsive. To reduce the - * probabilities for hitting this HW bug, the SW writes to - * bit 18 to flush a packet from Rx DPRAM immediately. The - * changes for it are done in the function - * XEmacPs_IntrHandler. - * 1.05a asa 09/23/13 Cache operations on BDs are not required and hence - * removed. It is expected that all BDs are allocated in - * from uncached area. - * </pre> - * - ****************************************************************************/ - -#ifndef XEMACPS_H /* prevent circular inclusions */ -#define XEMACPS_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files ********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xstatus.h" -#include "xemacps_hw.h" -#include "xemacps_bd.h" -#include "xemacps_bdring.h" - -/************************** Constant Definitions ****************************/ - -/* - * Device information - */ -#define XEMACPS_DEVICE_NAME "xemacps" -#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC" - - -/** @name Configuration options - * - * Device configuration options. See the XEmacPs_SetOptions(), - * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to - * use options. - * - * The default state of the options are noted and are what the device and - * driver will be set to after calling XEmacPs_Reset() or - * XEmacPs_Initialize(). - * - * @{ - */ - -#define XEMACPS_PROMISC_OPTION 0x00000001 -/**< Accept all incoming packets. - * This option defaults to disabled (cleared) */ - -#define XEMACPS_FRAME1536_OPTION 0x00000002 -/**< Frame larger than 1516 support for Tx & Rx. - * This option defaults to disabled (cleared) */ - -#define XEMACPS_VLAN_OPTION 0x00000004 -/**< VLAN Rx & Tx frame support. - * This option defaults to disabled (cleared) */ - -#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010 -/**< Enable recognition of flow control frames on Rx - * This option defaults to enabled (set) */ - -#define XEMACPS_FCS_STRIP_OPTION 0x00000020 -/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not - * stripped. - * This option defaults to enabled (set) */ - -#define XEMACPS_FCS_INSERT_OPTION 0x00000040 -/**< Generate FCS field and add PAD automatically for outgoing frames. - * This option defaults to disabled (cleared) */ - -#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080 -/**< Enable Length/Type error checking for incoming frames. When this option is - * set, the MAC will filter frames that have a mismatched type/length field - * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these - * types of frames are encountered. When this option is cleared, the MAC will - * allow these types of frames to be received. - * - * This option defaults to disabled (cleared) */ - -#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100 -/**< Enable the transmitter. - * This option defaults to enabled (set) */ - -#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200 -/**< Enable the receiver - * This option defaults to enabled (set) */ - -#define XEMACPS_BROADCAST_OPTION 0x00000400 -/**< Allow reception of the broadcast address - * This option defaults to enabled (set) */ - -#define XEMACPS_MULTICAST_OPTION 0x00000800 -/**< Allows reception of multicast addresses programmed into hash - * This option defaults to disabled (clear) */ - -#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000 -/**< Enable the RX checksum offload - * This option defaults to enabled (set) */ - -#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000 -/**< Enable the TX checksum offload - * This option defaults to enabled (set) */ - - -#define XEMACPS_DEFAULT_OPTIONS \ - (XEMACPS_FLOW_CONTROL_OPTION | \ - XEMACPS_FCS_INSERT_OPTION | \ - XEMACPS_FCS_STRIP_OPTION | \ - XEMACPS_BROADCAST_OPTION | \ - XEMACPS_LENTYPE_ERR_OPTION | \ - XEMACPS_TRANSMITTER_ENABLE_OPTION | \ - XEMACPS_RECEIVER_ENABLE_OPTION | \ - XEMACPS_RX_CHKSUM_ENABLE_OPTION | \ - XEMACPS_TX_CHKSUM_ENABLE_OPTION) - -/**< Default options set when device is initialized or reset */ -/*@}*/ - -/** @name Callback identifiers - * - * These constants are used as parameters to XEmacPs_SetHandler() - * @{ - */ -#define XEMACPS_HANDLER_DMASEND 1 -#define XEMACPS_HANDLER_DMARECV 2 -#define XEMACPS_HANDLER_ERROR 3 -/*@}*/ - -/* Constants to determine the configuration of the hardware device. They are - * used to allow the driver to verify it can operate with the hardware. - */ -#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */ - -/* The next few constants help upper layers determine the size of memory - * pools used for Ethernet buffers and descriptor lists. - */ -#define XEMACPS_MAC_ADDR_SIZE 6 /* size of Ethernet header */ - -#define XEMACPS_MTU 1500 /* max MTU size of Ethernet frame */ -#define XEMACPS_HDR_SIZE 14 /* size of Ethernet header */ -#define XEMACPS_HDR_VLAN_SIZE 18 /* size of Ethernet header with VLAN */ -#define XEMACPS_TRL_SIZE 4 /* size of Ethernet trailer (FCS) */ -#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \ - XEMACPS_TRL_SIZE) -#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \ - XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE) - -/* DMACR Bust length hash defines */ - -#define XEMACPS_SINGLE_BURST 1 -#define XEMACPS_4BYTE_BURST 4 -#define XEMACPS_8BYTE_BURST 8 -#define XEMACPS_16BYTE_BURST 16 - - -/**************************** Type Definitions ******************************/ -/** @name Typedefs for callback functions - * - * These callbacks are invoked in interrupt context. - * @{ - */ -/** - * Callback invoked when frame(s) have been sent or received in interrupt - * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler(). - * - * @param CallBackRef is user data assigned when the callback was set. - * - * @note - * See xemacps_hw.h for bitmasks definitions and the device hardware spec for - * further information on their meaning. - * - */ -typedef void (*XEmacPs_Handler) (void *CallBackRef); - -/** - * Callback when an asynchronous error occurs. To set this callback, invoke - * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType - * paramter. - * - * @param CallBackRef is user data assigned when the callback was set. - * @param Direction defines either receive or transmit error(s) has occurred. - * @param ErrorWord definition varies with Direction - * - */ -typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction, - u32 ErrorWord); - -/*@}*/ - -/** - * This typedef contains configuration information for a device. - */ -typedef struct { - u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddress;/**< Physical base address of IPIF registers */ -} XEmacPs_Config; - - -/** - * The XEmacPs driver instance data. The user is required to allocate a - * structure of this type for every XEmacPs device in the system. A pointer - * to a structure of this type is then passed to the driver API functions. - */ -typedef struct XEmacPs { - XEmacPs_Config Config; /* Hardware configuration */ - u32 IsStarted; /* Device is currently started */ - u32 IsReady; /* Device is initialized and ready */ - u32 Options; /* Current options word */ - - XEmacPs_BdRing TxBdRing; /* Transmit BD ring */ - XEmacPs_BdRing RxBdRing; /* Receive BD ring */ - - XEmacPs_Handler SendHandler; - XEmacPs_Handler RecvHandler; - void *SendRef; - void *RecvRef; - - XEmacPs_ErrHandler ErrorHandler; - void *ErrorRef; - -} XEmacPs; - - -/***************** Macros (Inline Functions) Definitions ********************/ - -/****************************************************************************/ -/** -* Retrieve the Tx ring object. This object can be used in the various Ring -* API functions. -* -* @param InstancePtr is the DMA channel to operate on. -* -* @return TxBdRing attribute -* -* @note -* C-style signature: -* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr) -* -*****************************************************************************/ -#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing) - -/****************************************************************************/ -/** -* Retrieve the Rx ring object. This object can be used in the various Ring -* API functions. -* -* @param InstancePtr is the DMA channel to operate on. -* -* @return RxBdRing attribute -* -* @note -* C-style signature: -* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr) -* -*****************************************************************************/ -#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing) - -/****************************************************************************/ -/** -* -* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for -* each bit set to 1 in <i>Mask</i>, will be enabled. -* -* @param InstancePtr is a pointer to the instance to be worked on. -* @param Mask contains a bit mask of interrupts to enable. The mask can -* be formed using a set of bitwise or'd values. -* -* @note -* The state of the transmitter and receiver are not modified by this function. -* C-style signature -* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask) -* -*****************************************************************************/ -#define XEmacPs_IntEnable(InstancePtr, Mask) \ - XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ - XEMACPS_IER_OFFSET, \ - (Mask & XEMACPS_IXR_ALL_MASK)); - -/****************************************************************************/ -/** -* -* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for -* each bit set to 1 in <i>Mask</i>, will be enabled. -* -* @param InstancePtr is a pointer to the instance to be worked on. -* @param Mask contains a bit mask of interrupts to disable. The mask can -* be formed using a set of bitwise or'd values. -* -* @note -* The state of the transmitter and receiver are not modified by this function. -* C-style signature -* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask) -* -*****************************************************************************/ -#define XEmacPs_IntDisable(InstancePtr, Mask) \ - XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ - XEMACPS_IDR_OFFSET, \ - (Mask & XEMACPS_IXR_ALL_MASK)); - -/****************************************************************************/ -/** -* -* This macro triggers trasmit circuit to send data currently in TX buffer(s). -* -* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. -* -* @return -* -* @note -* -* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr) -* -*****************************************************************************/ -#define XEmacPs_Transmit(InstancePtr) \ - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, \ - XEMACPS_NWCTRL_OFFSET, \ - (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, \ - XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK)) - -/****************************************************************************/ -/** -* -* This macro determines if the device is configured with checksum offloading -* on the receive channel -* -* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. -* -* @return -* -* Boolean TRUE if the device is configured with checksum offloading, or -* FALSE otherwise. -* -* @note -* -* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr) -* -*****************************************************************************/ -#define XEmacPs_IsRxCsum(InstancePtr) \ - ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ - XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) \ - ? TRUE : FALSE) - -/****************************************************************************/ -/** -* -* This macro determines if the device is configured with checksum offloading -* on the transmit channel -* -* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. -* -* @return -* -* Boolean TRUE if the device is configured with checksum offloading, or -* FALSE otherwise. -* -* @note -* -* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr) -* -*****************************************************************************/ -#define XEmacPs_IsTxCsum(InstancePtr) \ - ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ - XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) \ - ? TRUE : FALSE) - -/************************** Function Prototypes *****************************/ - -/* - * Initialization functions in xemacps.c - */ -int XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr, - u32 EffectiveAddress); -void XEmacPs_Start(XEmacPs *InstancePtr); -void XEmacPs_Stop(XEmacPs *InstancePtr); -void XEmacPs_Reset(XEmacPs *InstancePtr); - -/* - * Lookup configuration in xemacps_sinit.c - */ -XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId); - -/* - * Interrupt-related functions in xemacps_intr.c - * DMA only and FIFO is not supported. This DMA does not support coalescing. - */ -int XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType, - void *FuncPtr, void *CallBackRef); -void XEmacPs_IntrHandler(void *InstancePtr); - -/* - * MAC configuration/control functions in XEmacPs_control.c - */ -int XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options); -int XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options); -u32 XEmacPs_GetOptions(XEmacPs *InstancePtr); - -int XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index); -void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index); - -int XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr); -void XEmacPs_ClearHash(XEmacPs *InstancePtr); -void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr); - -void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, - XEmacPs_MdcDiv Divisor); -void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed); -u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr); -int XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress, - u32 RegisterNum, u16 *PhyDataPtr); -int XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress, - u32 RegisterNum, u16 PhyData); -int XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index); - -int XEmacPs_SendPausePacket(XEmacPs *InstancePtr); -void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, int BLength); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps_bd.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps_bd.h deleted file mode 100644 index 8bf33cfa5bb5b6f92bb43049d869e68708aabd12..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps_bd.h +++ /dev/null @@ -1,737 +0,0 @@ -/* $Id: xemacps_bd.h,v 1.1.2.1 2011/01/20 03:39:02 sadanan Exp $ */ -/****************************************************************************** -* -* (c) Copyright 2010 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** - * - * @file xemacps_bd.h - * - * This header provides operations to manage buffer descriptors in support - * of scatter-gather DMA. - * - * The API exported by this header defines abstracted macros that allow the - * user to read/write specific BD fields. - * - * <b>Buffer Descriptors</b> - * - * A buffer descriptor (BD) defines a DMA transaction. The macros defined by - * this header file allow access to most fields within a BD to tailor a DMA - * transaction according to user and hardware requirements. See the hardware - * IP DMA spec for more information on BD fields and how they affect transfers. - * - * The XEmacPs_Bd structure defines a BD. The organization of this structure - * is driven mainly by the hardware for use in scatter-gather DMA transfers. - * - * <b>Performance</b> - * - * Limiting I/O to BDs can improve overall performance of the DMA channel. - * - * <pre> - * MODIFICATION HISTORY: - * - * Ver Who Date Changes - * ----- ---- -------- ------------------------------------------------------- - * 1.00a wsy 01/10/10 First release - * </pre> - * - * *************************************************************************** - */ - -#ifndef XEMACPS_BD_H /* prevent circular inclusions */ -#define XEMACPS_BD_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include <string.h> -#include "xil_types.h" -#include "xil_assert.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/* Minimum BD alignment */ -#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4 - -/** - * The XEmacPs_Bd is the type for buffer descriptors (BDs). - */ -#define XEMACPS_BD_NUM_WORDS 2 -typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS]; - - -/***************** Macros (Inline Functions) Definitions *********************/ - -/*****************************************************************************/ -/** - * Zero out BD fields - * - * @param BdPtr is the BD pointer to operate on - * - * @return Nothing - * - * @note - * C-style signature: - * void XEmacPs_BdClear(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdClear(BdPtr) \ - memset((BdPtr), 0, sizeof(XEmacPs_Bd)) - -/****************************************************************************/ -/** -* -* Read the given Buffer Descriptor word. -* -* @param BaseAddress is the base address of the BD to read -* @param Offset is the word offset to be read -* -* @return The 32-bit value of the field -* -* @note -* C-style signature: -* u32 XEmacPs_BdRead(u32 BaseAddress, u32 Offset) -* -*****************************************************************************/ -#define XEmacPs_BdRead(BaseAddress, Offset) \ - (*(u32*)((u32)(BaseAddress) + (u32)(Offset))) - -/****************************************************************************/ -/** -* -* Write the given Buffer Descriptor word. -* -* @param BaseAddress is the base address of the BD to write -* @param Offset is the word offset to be written -* @param Data is the 32-bit value to write to the field -* -* @return None. -* -* @note -* C-style signature: -* void XEmacPs_BdWrite(u32 BaseAddress, u32 Offset, u32 Data) -* -*****************************************************************************/ -#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \ - (*(u32*)((u32)(BaseAddress) + (u32)(Offset)) = (Data)) - -/*****************************************************************************/ -/** - * Set the BD's Address field (word 0). - * - * @param BdPtr is the BD pointer to operate on - * @param Addr is the value to write to BD's status field. - * - * @note : - * - * C-style signature: - * void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, u32 Addr) - * - *****************************************************************************/ -#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \ - (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))) - - -/*****************************************************************************/ -/** - * Set the BD's Address field (word 0). - * - * @param BdPtr is the BD pointer to operate on - * @param Addr is the value to write to BD's status field. - * - * @note : Due to some bits are mixed within recevie BD's address field, - * read-modify-write is performed. - * - * C-style signature: - * void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, u32 Addr) - * - *****************************************************************************/ -#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \ - XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ - ~XEMACPS_RXBUF_ADD_MASK) | (u32)(Addr))) - - -/*****************************************************************************/ -/** - * Set the BD's Status field (word 1). - * - * @param BdPtr is the BD pointer to operate on - * @param Data is the value to write to BD's status field. - * - * @note - * C-style signature: - * void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, u32 Data) - * - *****************************************************************************/ -#define XEmacPs_BdSetStatus(BdPtr, Data) \ - XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ - XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | Data) - - -/*****************************************************************************/ -/** - * Retrieve the BD's Packet DMA transfer status word (word 1). - * - * @param BdPtr is the BD pointer to operate on - * - * @return Status word - * - * @note - * C-style signature: - * u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr) - * - * Due to the BD bit layout differences in transmit and receive. User's - * caution is required. - *****************************************************************************/ -#define XEmacPs_BdGetStatus(BdPtr) \ - XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) - - -/*****************************************************************************/ -/** - * Get the address (bits 0..31) of the BD's buffer address (word 0) - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdGetBufAddr(BdPtr) \ - (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET)) - - -/*****************************************************************************/ -/** - * Set transfer length in bytes for the given BD. The length must be set each - * time a BD is submitted to hardware. - * - * @param BdPtr is the BD pointer to operate on - * @param LenBytes is the number of bytes to transfer. - * - * @note - * C-style signature: - * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes) - * - *****************************************************************************/ -#define XEmacPs_BdSetLength(BdPtr, LenBytes) \ - XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes))) - - -/*****************************************************************************/ -/** - * Retrieve the BD length field. - * - * For Tx channels, the returned value is the same as that written with - * XEmacPs_BdSetLength(). - * - * For Rx channels, the returned value is the size of the received packet. - * - * @param BdPtr is the BD pointer to operate on - * - * @return Length field processed by hardware or set by - * XEmacPs_BdSetLength(). - * - * @note - * C-style signature: - * u32 XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr) - * XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK. - * - *****************************************************************************/ -#define XEmacPs_BdGetLength(BdPtr) \ - (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_RXBUF_LEN_MASK) - - -/*****************************************************************************/ -/** - * Test whether the given BD has been marked as the last BD of a packet. - * - * @param BdPtr is the BD pointer to operate on - * - * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise - * - * @note - * C-style signature: - * u32 XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsLast(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_RXBUF_EOF_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * Tell the DMA engine that the given transmit BD marks the end of the current - * packet to be processed. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdSetLast(BdPtr) \ - (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ - XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ - XEMACPS_TXBUF_LAST_MASK)) - - -/*****************************************************************************/ -/** - * Tell the DMA engine that the current packet does not end with the given - * BD. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdClearLast(BdPtr) \ - (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ - XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - ~XEMACPS_TXBUF_LAST_MASK)) - - -/*****************************************************************************/ -/** - * Set this bit to mark the last descriptor in the receive buffer descriptor - * list. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdSetRxWrap(BdPtr) \ - (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ - XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \ - XEMACPS_RXBUF_WRAP_MASK)) - - -/*****************************************************************************/ -/** - * Determine the wrap bit of the receive BD which indicates end of the - * BD list. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsRxWrap(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ - XEMACPS_RXBUF_WRAP_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * Sets this bit to mark the last descriptor in the transmit buffer - * descriptor list. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdSetTxWrap(BdPtr) \ - (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ - XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ - XEMACPS_TXBUF_WRAP_MASK)) - - -/*****************************************************************************/ -/** - * Determine the wrap bit of the transmit BD which indicates end of the - * BD list. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsTxWrap(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_TXBUF_WRAP_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/* - * Must clear this bit to enable the MAC to write data to the receive - * buffer. Hardware sets this bit once it has successfully written a frame to - * memory. Once set, software has to clear the bit before the buffer can be - * used again. This macro clear the new bit of the receive BD. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdClearRxNew(BdPtr) \ - (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ - XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ - ~XEMACPS_RXBUF_NEW_MASK)) - - -/*****************************************************************************/ -/** - * Determine the new bit of the receive BD. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsRxNew(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ - XEMACPS_RXBUF_NEW_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * Software sets this bit to disable the buffer to be read by the hardware. - * Hardware sets this bit for the first buffer of a frame once it has been - * successfully transmitted. This macro sets this bit of transmit BD to avoid - * confusion. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdSetTxUsed(BdPtr) \ - (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ - XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ - XEMACPS_TXBUF_USED_MASK)) - - -/*****************************************************************************/ -/** - * Software clears this bit to enable the buffer to be read by the hardware. - * Hardware sets this bit for the first buffer of a frame once it has been - * successfully transmitted. This macro clears this bit of transmit BD. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdClearTxUsed(BdPtr) \ - (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ - XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - ~XEMACPS_TXBUF_USED_MASK)) - - -/*****************************************************************************/ -/** - * Determine the used bit of the transmit BD. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsTxUsed(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_TXBUF_USED_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * Determine if a frame fails to be transmitted due to too many retries. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsTxRetry(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_TXBUF_RETRY_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * Determine if a frame fails to be transmitted due to data can not be - * feteched in time or buffers are exhausted. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsTxUrun(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_TXBUF_URUN_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * Determine if a frame fails to be transmitted due to buffer is exhausted - * mid-frame. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsTxExh(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_TXBUF_EXH_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * Sets this bit, no CRC will be appended to the current frame. This control - * bit must be set for the first buffer in a frame and will be ignored for - * the subsequent buffers of a frame. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * This bit must be clear when using the transmit checksum generation offload, - * otherwise checksum generation and substitution will not occur. - * - * C-style signature: - * u32 XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdSetTxNoCRC(BdPtr) \ - (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ - XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ - XEMACPS_TXBUF_NOCRC_MASK)) - - -/*****************************************************************************/ -/** - * Clear this bit, CRC will be appended to the current frame. This control - * bit must be set for the first buffer in a frame and will be ignored for - * the subsequent buffers of a frame. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * This bit must be clear when using the transmit checksum generation offload, - * otherwise checksum generation and substitution will not occur. - * - * C-style signature: - * u32 XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdClearTxNoCRC(BdPtr) \ - (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ - XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - ~XEMACPS_TXBUF_NOCRC_MASK)) - - -/*****************************************************************************/ -/** - * Determine the broadcast bit of the receive BD. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsRxBcast(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_RXBUF_BCAST_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * Determine the multicast hash bit of the receive BD. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsRxMultiHash(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_RXBUF_MULTIHASH_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * Determine the unicast hash bit of the receive BD. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsRxUniHash(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_RXBUF_UNIHASH_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * Determine if the received frame is a VLAN Tagged frame. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsRxVlan(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_RXBUF_VLAN_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * Determine if the received frame has Type ID of 8100h and null VLAN - * identifier(Priority tag). - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsRxPri(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_RXBUF_PRI_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * Determine if the received frame's Concatenation Format Indicator (CFI) of - * the frames VLANTCI field was set. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsRxCFI(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_RXBUF_CFI_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * Determine the End Of Frame (EOF) bit of the receive BD. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsRxEOF(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_RXBUF_EOF_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * Determine the Start Of Frame (SOF) bit of the receive BD. - * - * @param BdPtr is the BD pointer to operate on - * - * @note - * C-style signature: - * u32 XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr) - * - *****************************************************************************/ -#define XEmacPs_BdIsRxSOF(BdPtr) \ - ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ - XEMACPS_RXBUF_SOF_MASK) ? TRUE : FALSE) - - -/************************** Function Prototypes ******************************/ - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps_bdring.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps_bdring.c deleted file mode 100644 index 40c1e35dc96ec43b151417cb87f8e1ddf57ac062..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps_bdring.c +++ /dev/null @@ -1,1010 +0,0 @@ -/* $Id: xemacps_bdring.c,v 1.1.2.1 2011/01/20 03:39:02 sadanan Exp $ */ -/****************************************************************************** -* -* (c) Copyright 2010 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xemacps_bdring.c -* -* This file implements buffer descriptor ring related functions. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.00a wsy 01/10/10 First release -* 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx is modified. -* Earlier it used to search in "BdLimit" number of BDs to -* know which BDs are processed. Now one more check is -* added. It looks for BDs till the current BD pointer -* reaches HwTail. By doing this processing time is saved. -* 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file -* xemacps_bdring.c is modified. Now start of packet is -* searched for returning the number of BDs processed. -* 1.05a asa 09/23/13 Cache operations on BDs are not required and hence -* removed. It is expected that all BDs are allocated in -* from uncached area. Fix for CR #663885. -* </pre> -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xstatus.h" -#include "xil_cache.h" -#include "xemacps_hw.h" -#include "xemacps_bd.h" -#include "xemacps_bdring.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - -/**************************************************************************** - * Compute the virtual address of a descriptor from its physical address - * - * @param BdPtr is the physical address of the BD - * - * @returns Virtual address of BdPtr - * - * @note Assume BdPtr is always a valid BD in the ring - ****************************************************************************/ -#define XEMACPS_PHYS_TO_VIRT(BdPtr) \ - ((u32)BdPtr + (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr)) - -/**************************************************************************** - * Compute the physical address of a descriptor from its virtual address - * - * @param BdPtr is the physical address of the BD - * - * @returns Physical address of BdPtr - * - * @note Assume BdPtr is always a valid BD in the ring - ****************************************************************************/ -#define XEMACPS_VIRT_TO_PHYS(BdPtr) \ - ((u32)BdPtr - (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr)) - -/**************************************************************************** - * Move the BdPtr argument ahead an arbitrary number of BDs wrapping around - * to the beginning of the ring if needed. - * - * We know if a wrapaound should occur if the new BdPtr is greater than - * the high address in the ring OR if the new BdPtr crosses over the - * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not - * allow a BD space to span this boundary. - * - * @param RingPtr is the ring BdPtr appears in - * @param BdPtr on input is the starting BD position and on output is the - * final BD position - * @param NumBd is the number of BD spaces to increment - * - ****************************************************************************/ -#define XEMACPS_RING_SEEKAHEAD(RingPtr, BdPtr, NumBd) \ - { \ - u32 Addr = (u32)BdPtr; \ - \ - Addr += ((RingPtr)->Separation * NumBd); \ - if ((Addr > (RingPtr)->HighBdAddr) || ((u32)BdPtr > Addr)) \ - { \ - Addr -= (RingPtr)->Length; \ - } \ - \ - BdPtr = (XEmacPs_Bd*)Addr; \ - } - -/**************************************************************************** - * Move the BdPtr argument backwards an arbitrary number of BDs wrapping - * around to the end of the ring if needed. - * - * We know if a wrapaound should occur if the new BdPtr is less than - * the base address in the ring OR if the new BdPtr crosses over the - * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not - * allow a BD space to span this boundary. - * - * @param RingPtr is the ring BdPtr appears in - * @param BdPtr on input is the starting BD position and on output is the - * final BD position - * @param NumBd is the number of BD spaces to increment - * - ****************************************************************************/ -#define XEMACPS_RING_SEEKBACK(RingPtr, BdPtr, NumBd) \ - { \ - u32 Addr = (u32)BdPtr; \ - \ - Addr -= ((RingPtr)->Separation * NumBd); \ - if ((Addr < (RingPtr)->BaseBdAddr) || ((u32)BdPtr < Addr)) \ - { \ - Addr += (RingPtr)->Length; \ - } \ - \ - BdPtr = (XEmacPs_Bd*)Addr; \ - } - - -/************************** Function Prototypes ******************************/ - - -/************************** Variable Definitions *****************************/ - -/*****************************************************************************/ -/** - * Using a memory segment allocated by the caller, create and setup the BD list - * for the given DMA channel. - * - * @param RingPtr is the instance to be worked on. - * @param PhysAddr is the physical base address of user memory region. - * @param VirtAddr is the virtual base address of the user memory region. If - * address translation is not being utilized, then VirtAddr should be - * equivalent to PhysAddr. - * @param Alignment governs the byte alignment of individual BDs. This function - * will enforce a minimum alignment of 4 bytes with no maximum as long - * as it is specified as a power of 2. - * @param BdCount is the number of BDs to setup in the user memory region. It - * is assumed the region is large enough to contain the BDs. - * - * @return - * - * - XST_SUCCESS if initialization was successful - * - XST_NO_FEATURE if the provided instance is a non DMA type - * channel. - * - XST_INVALID_PARAM under any of the following conditions: - * 1) PhysAddr and/or VirtAddr are not aligned to the given Alignment - * parameter; - * 2) Alignment parameter does not meet minimum requirements or is not a - * power of 2 value; - * 3) BdCount is 0. - * - XST_DMA_SG_LIST_ERROR if the memory segment containing the list spans - * over address 0x00000000 in virtual address space. - * - * @note - * Make sure to pass in the right alignment value. - *****************************************************************************/ -int XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, u32 PhysAddr, - u32 VirtAddr, u32 Alignment, unsigned BdCount) -{ - unsigned i; - u32 BdVirtAddr; - u32 BdPhyAddr; - - /* In case there is a failure prior to creating list, make sure the - * following attributes are 0 to prevent calls to other functions - * from doing anything. - */ - RingPtr->AllCnt = 0; - RingPtr->FreeCnt = 0; - RingPtr->HwCnt = 0; - RingPtr->PreCnt = 0; - RingPtr->PostCnt = 0; - - /* Make sure Alignment parameter meets minimum requirements */ - if (Alignment < XEMACPS_DMABD_MINIMUM_ALIGNMENT) { - return (XST_INVALID_PARAM); - } - - /* Make sure Alignment is a power of 2 */ - if ((Alignment - 1) & Alignment) { - return (XST_INVALID_PARAM); - } - - /* Make sure PhysAddr and VirtAddr are on same Alignment */ - if ((PhysAddr % Alignment) || (VirtAddr % Alignment)) { - return (XST_INVALID_PARAM); - } - - /* Is BdCount reasonable? */ - if (BdCount == 0) { - return (XST_INVALID_PARAM); - } - - /* Figure out how many bytes will be between the start of adjacent BDs */ - RingPtr->Separation = - (sizeof(XEmacPs_Bd) + (Alignment - 1)) & ~(Alignment - 1); - - /* Must make sure the ring doesn't span address 0x00000000. If it does, - * then the next/prev BD traversal macros will fail. - */ - if (VirtAddr > (VirtAddr + (RingPtr->Separation * BdCount) - 1)) { - return (XST_DMA_SG_LIST_ERROR); - } - - /* Initial ring setup: - * - Clear the entire space - * - Setup each BD's BDA field with the physical address of the next BD - */ - memset((void *) VirtAddr, 0, (RingPtr->Separation * BdCount)); - - BdVirtAddr = VirtAddr; - BdPhyAddr = PhysAddr + RingPtr->Separation; - for (i = 1; i < BdCount; i++) { - BdVirtAddr += RingPtr->Separation; - BdPhyAddr += RingPtr->Separation; - } - - /* Setup and initialize pointers and counters */ - RingPtr->RunState = XST_DMA_SG_IS_STOPPED; - RingPtr->BaseBdAddr = VirtAddr; - RingPtr->PhysBaseAddr = PhysAddr; - RingPtr->HighBdAddr = BdVirtAddr; - RingPtr->Length = - RingPtr->HighBdAddr - RingPtr->BaseBdAddr + RingPtr->Separation; - RingPtr->AllCnt = BdCount; - RingPtr->FreeCnt = BdCount; - RingPtr->FreeHead = (XEmacPs_Bd *) VirtAddr; - RingPtr->PreHead = (XEmacPs_Bd *) VirtAddr; - RingPtr->HwHead = (XEmacPs_Bd *) VirtAddr; - RingPtr->HwTail = (XEmacPs_Bd *) VirtAddr; - RingPtr->PostHead = (XEmacPs_Bd *) VirtAddr; - RingPtr->BdaRestart = (XEmacPs_Bd *) PhysAddr; - - return (XST_SUCCESS); -} - - -/*****************************************************************************/ -/** - * Clone the given BD into every BD in the list. - * every field of the source BD is replicated in every BD of the list. - * - * This function can be called only when all BDs are in the free group such as - * they are immediately after initialization with XEmacPs_BdRingCreate(). - * This prevents modification of BDs while they are in use by hardware or the - * user. - * - * @param RingPtr is the pointer of BD ring instance to be worked on. - * @param SrcBdPtr is the source BD template to be cloned into the list. This - * BD will be modified. - * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates - * which direction. - * - * @return - * - XST_SUCCESS if the list was modified. - * - XST_DMA_SG_NO_LIST if a list has not been created. - * - XST_DMA_SG_LIST_ERROR if some of the BDs in this channel are under - * hardware or user control. - * - XST_DEVICE_IS_STARTED if the DMA channel has not been stopped. - * - *****************************************************************************/ -int XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr, - u8 Direction) -{ - unsigned i; - u32 CurBd; - - /* Can't do this function if there isn't a ring */ - if (RingPtr->AllCnt == 0) { - return (XST_DMA_SG_NO_LIST); - } - - /* Can't do this function with the channel running */ - if (RingPtr->RunState == XST_DMA_SG_IS_STARTED) { - return (XST_DEVICE_IS_STARTED); - } - - /* Can't do this function with some of the BDs in use */ - if (RingPtr->FreeCnt != RingPtr->AllCnt) { - return (XST_DMA_SG_LIST_ERROR); - } - - if ((Direction != XEMACPS_SEND) && (Direction != XEMACPS_RECV)) { - return (XST_INVALID_PARAM); - } - - /* Starting from the top of the ring, save BD.Next, overwrite the entire - * BD with the template, then restore BD.Next - */ - for (i = 0, CurBd = (u32) RingPtr->BaseBdAddr; - i < RingPtr->AllCnt; i++, CurBd += RingPtr->Separation) { - memcpy((void *)CurBd, SrcBdPtr, sizeof(XEmacPs_Bd)); - } - - CurBd -= RingPtr->Separation; - - if (Direction == XEMACPS_RECV) { - XEmacPs_BdSetRxWrap(CurBd); - } - else { - XEmacPs_BdSetTxWrap(CurBd); - } - - return (XST_SUCCESS); -} - - -/*****************************************************************************/ -/** - * Reserve locations in the BD list. The set of returned BDs may be modified - * in preparation for future DMA transaction(s). Once the BDs are ready to be - * submitted to hardware, the user must call XEmacPs_BdRingToHw() in the same - * order which they were allocated here. Example: - * - * <pre> - * NumBd = 2; - * Status = XEmacPs_BdRingAlloc(MyRingPtr, NumBd, &MyBdSet); - * - * if (Status != XST_SUCCESS) - * { - * // Not enough BDs available for the request - * } - * - * CurBd = MyBdSet; - * for (i=0; i<NumBd; i++) - * { - * // Prepare CurBd..... - * - * // Onto next BD - * CurBd = XEmacPs_BdRingNext(MyRingPtr, CurBd); - * } - * - * // Give list to hardware - * Status = XEmacPs_BdRingToHw(MyRingPtr, NumBd, MyBdSet); - * </pre> - * - * A more advanced use of this function may allocate multiple sets of BDs. - * They must be allocated and given to hardware in the correct sequence: - * <pre> - * // Legal - * XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1); - * XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1); - * - * // Legal - * XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1); - * XEmacPs_BdRingAlloc(MyRingPtr, NumBd2, &MySet2); - * XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1); - * XEmacPs_BdRingToHw(MyRingPtr, NumBd2, MySet2); - * - * // Not legal - * XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1); - * XEmacPs_BdRingAlloc(MyRingPtr, NumBd2, &MySet2); - * XEmacPs_BdRingToHw(MyRingPtr, NumBd2, MySet2); - * XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1); - * </pre> - * - * Use the API defined in xemacps_bd.h to modify individual BDs. Traversal - * of the BD set can be done using XEmacPs_BdRingNext() and - * XEmacPs_BdRingPrev(). - * - * @param RingPtr is a pointer to the BD ring instance to be worked on. - * @param NumBd is the number of BDs to allocate - * @param BdSetPtr is an output parameter, it points to the first BD available - * for modification. - * - * @return - * - XST_SUCCESS if the requested number of BDs was returned in the BdSetPtr - * parameter. - * - XST_FAILURE if there were not enough free BDs to satisfy the request. - * - * @note This function should not be preempted by another XEmacPs_Bd function - * call that modifies the BD space. It is the caller's responsibility to - * provide a mutual exclusion mechanism. - * - * @note Do not modify more BDs than the number requested with the NumBd - * parameter. Doing so will lead to data corruption and system - * instability. - * - *****************************************************************************/ -int XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, unsigned NumBd, - XEmacPs_Bd ** BdSetPtr) -{ - /* Enough free BDs available for the request? */ - if (RingPtr->FreeCnt < NumBd) { - return (XST_FAILURE); - } - - /* Set the return argument and move FreeHead forward */ - *BdSetPtr = RingPtr->FreeHead; - XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->FreeHead, NumBd); - RingPtr->FreeCnt -= NumBd; - RingPtr->PreCnt += NumBd; - return (XST_SUCCESS); -} - -/*****************************************************************************/ -/** - * Fully or partially undo an XEmacPs_BdRingAlloc() operation. Use this - * function if all the BDs allocated by XEmacPs_BdRingAlloc() could not be - * transferred to hardware with XEmacPs_BdRingToHw(). - * - * This function helps out in situations when an unrelated error occurs after - * BDs have been allocated but before they have been given to hardware. - * An example of this type of error would be an OS running out of resources. - * - * This function is not the same as XEmacPs_BdRingFree(). The Free function - * returns BDs to the free list after they have been processed by hardware, - * while UnAlloc returns them before being processed by hardware. - * - * There are two scenarios where this function can be used. Full UnAlloc or - * Partial UnAlloc. A Full UnAlloc means all the BDs Alloc'd will be returned: - * - * <pre> - * Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr); - * ... - * if (Error) - * { - * Status = XEmacPs_BdRingUnAlloc(MyRingPtr, 10, &BdPtr); - * } - * </pre> - * - * A partial UnAlloc means some of the BDs Alloc'd will be returned: - * - * <pre> - * Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr); - * BdsLeft = 10; - * CurBdPtr = BdPtr; - * - * while (BdsLeft) - * { - * if (Error) - * { - * Status = XEmacPs_BdRingUnAlloc(MyRingPtr, BdsLeft, CurBdPtr); - * } - * - * CurBdPtr = XEmacPs_BdRingNext(MyRingPtr, CurBdPtr); - * BdsLeft--; - * } - * </pre> - * - * A partial UnAlloc must include the last BD in the list that was Alloc'd. - * - * @param RingPtr is a pointer to the instance to be worked on. - * @param NumBd is the number of BDs to allocate - * @param BdSetPtr is an output parameter, it points to the first BD available - * for modification. - * - * @return - * - XST_SUCCESS if the BDs were unallocated. - * - XST_FAILURE if NumBd parameter was greater that the number of BDs in - * the preprocessing state. - * - * @note This function should not be preempted by another XEmacPs_Bd function - * call that modifies the BD space. It is the caller's responsibility to - * provide a mutual exclusion mechanism. - * - *****************************************************************************/ -int XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, unsigned NumBd, - XEmacPs_Bd * BdSetPtr) -{ - (void)BdSetPtr; - - /* Enough BDs in the free state for the request? */ - if (RingPtr->PreCnt < NumBd) { - return (XST_FAILURE); - } - - /* Set the return argument and move FreeHead backward */ - XEMACPS_RING_SEEKBACK(RingPtr, RingPtr->FreeHead, NumBd); - RingPtr->FreeCnt += NumBd; - RingPtr->PreCnt -= NumBd; - return (XST_SUCCESS); -} - - -/*****************************************************************************/ -/** - * Enqueue a set of BDs to hardware that were previously allocated by - * XEmacPs_BdRingAlloc(). Once this function returns, the argument BD set goes - * under hardware control. Any changes made to these BDs after this point will - * corrupt the BD list leading to data corruption and system instability. - * - * The set will be rejected if the last BD of the set does not mark the end of - * a packet (see XEmacPs_BdSetLast()). - * - * @param RingPtr is a pointer to the instance to be worked on. - * @param NumBd is the number of BDs in the set. - * @param BdSetPtr is the first BD of the set to commit to hardware. - * - * @return - * - XST_SUCCESS if the set of BDs was accepted and enqueued to hardware. - * - XST_FAILURE if the set of BDs was rejected because the last BD of the set - * did not have its "last" bit set. - * - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with - * XEmacPs_BdRingAlloc(). - * - * @note This function should not be preempted by another XEmacPs_Bd function - * call that modifies the BD space. It is the caller's responsibility to - * provide a mutual exclusion mechanism. - * - *****************************************************************************/ -int XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, unsigned NumBd, - XEmacPs_Bd * BdSetPtr) -{ - XEmacPs_Bd *CurBdPtr; - unsigned i; - - /* if no bds to process, simply return. */ - if (0 == NumBd) - return (XST_SUCCESS); - - /* Make sure we are in sync with XEmacPs_BdRingAlloc() */ - if ((RingPtr->PreCnt < NumBd) || (RingPtr->PreHead != BdSetPtr)) { - return (XST_DMA_SG_LIST_ERROR); - } - - CurBdPtr = BdSetPtr; - for (i = 0; i < NumBd; i++) { - CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr); - } - - /* Adjust ring pointers & counters */ - XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PreHead, NumBd); - RingPtr->PreCnt -= NumBd; - - RingPtr->HwTail = CurBdPtr; - RingPtr->HwCnt += NumBd; - - return (XST_SUCCESS); -} - - -/*****************************************************************************/ -/** - * Returns a set of BD(s) that have been processed by hardware. The returned - * BDs may be examined to determine the outcome of the DMA transaction(s). - * Once the BDs have been examined, the user must call XEmacPs_BdRingFree() - * in the same order which they were retrieved here. Example: - * - * <pre> - * NumBd = XEmacPs_BdRingFromHwTx(MyRingPtr, MaxBd, &MyBdSet); - * - * if (NumBd == 0) - * { - * // hardware has nothing ready for us yet - * } - * - * CurBd = MyBdSet; - * for (i=0; i<NumBd; i++) - * { - * // Examine CurBd for post processing..... - * - * // Onto next BD - * CurBd = XEmacPs_BdRingNext(MyRingPtr, CurBd); - * } - * - * XEmacPs_BdRingFree(MyRingPtr, NumBd, MyBdSet); // Return list - * } - * </pre> - * - * A more advanced use of this function may allocate multiple sets of BDs. - * They must be retrieved from hardware and freed in the correct sequence: - * <pre> - * // Legal - * XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1); - * XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1); - * - * // Legal - * XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1); - * XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd2, &MySet2); - * XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1); - * XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2); - * - * // Not legal - * XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1); - * XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd2, &MySet2); - * XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2); - * XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1); - * </pre> - * - * If hardware has only partially completed a packet spanning multiple BDs, - * then none of the BDs for that packet will be included in the results. - * - * @param RingPtr is a pointer to the instance to be worked on. - * @param BdLimit is the maximum number of BDs to return in the set. - * @param BdSetPtr is an output parameter, it points to the first BD available - * for examination. - * - * @return - * The number of BDs processed by hardware. A value of 0 indicates that no - * data is available. No more than BdLimit BDs will be returned. - * - * @note Treat BDs returned by this function as read-only. - * - * @note This function should not be preempted by another XEmacPs_Bd function - * call that modifies the BD space. It is the caller's responsibility to - * provide a mutual exclusion mechanism. - * - *****************************************************************************/ -unsigned XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, unsigned BdLimit, - XEmacPs_Bd ** BdSetPtr) -{ - XEmacPs_Bd *CurBdPtr; - u32 BdStr = 0; - unsigned BdCount; - unsigned BdPartialCount; - unsigned int Sop = 0; - - - CurBdPtr = RingPtr->HwHead; - BdCount = 0; - BdPartialCount = 0; - - /* If no BDs in work group, then there's nothing to search */ - if (RingPtr->HwCnt == 0) { - *BdSetPtr = NULL; - return (0); - } - - if (BdLimit > RingPtr->HwCnt) - BdLimit = RingPtr->HwCnt; - - /* Starting at HwHead, keep moving forward in the list until: - * - A BD is encountered with its new/used bit set which means - * hardware has not completed processing of that BD. - * - RingPtr->HwTail is reached and RingPtr->HwCnt is reached. - * - The number of requested BDs has been processed - */ - while (BdCount < BdLimit) { - /* Read the status */ - BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET); - - if ((Sop == 0) && (BdStr & XEMACPS_TXBUF_USED_MASK)) - Sop = 1; - - if (Sop == 1) { - BdCount++; - BdPartialCount++; - } - - /* hardware has processed this BD so check the "last" bit. - * If it is clear, then there are more BDs for the current - * packet. Keep a count of these partial packet BDs. - */ - if ((Sop == 1) && (BdStr & XEMACPS_TXBUF_LAST_MASK)) { - Sop = 0; - BdPartialCount = 0; - } - - /* Move on to next BD in work group */ - CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr); - } - - /* Subtract off any partial packet BDs found */ - BdCount -= BdPartialCount; - - /* If BdCount is non-zero then BDs were found to return. Set return - * parameters, update pointers and counters, return success - */ - if (BdCount > 0) { - *BdSetPtr = RingPtr->HwHead; - RingPtr->HwCnt -= BdCount; - RingPtr->PostCnt += BdCount; - XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount); - return (BdCount); - } - else { - *BdSetPtr = NULL; - return (0); - } -} - - -/*****************************************************************************/ -/** - * Returns a set of BD(s) that have been processed by hardware. The returned - * BDs may be examined to determine the outcome of the DMA transaction(s). - * Once the BDs have been examined, the user must call XEmacPs_BdRingFree() - * in the same order which they were retrieved here. Example: - * - * <pre> - * NumBd = XEmacPs_BdRingFromHwRx(MyRingPtr, MaxBd, &MyBdSet); - * - * if (NumBd == 0) - * { - * // hardware has nothing ready for us yet - * } - * - * CurBd = MyBdSet; - * for (i=0; i<NumBd; i++) - * { - * // Examine CurBd for post processing..... - * - * // Onto next BD - * CurBd = XEmacPs_BdRingNext(MyRingPtr, CurBd); - * } - * - * XEmacPs_BdRingFree(MyRingPtr, NumBd, MyBdSet); // Return list - * } - * </pre> - * - * A more advanced use of this function may allocate multiple sets of BDs. - * They must be retrieved from hardware and freed in the correct sequence: - * <pre> - * // Legal - * XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1); - * XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1); - * - * // Legal - * XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1); - * XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd2, &MySet2); - * XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1); - * XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2); - * - * // Not legal - * XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1); - * XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd2, &MySet2); - * XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2); - * XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1); - * </pre> - * - * If hardware has only partially completed a packet spanning multiple BDs, - * then none of the BDs for that packet will be included in the results. - * - * @param RingPtr is a pointer to the instance to be worked on. - * @param BdLimit is the maximum number of BDs to return in the set. - * @param BdSetPtr is an output parameter, it points to the first BD available - * for examination. - * - * @return - * The number of BDs processed by hardware. A value of 0 indicates that no - * data is available. No more than BdLimit BDs will be returned. - * - * @note Treat BDs returned by this function as read-only. - * - * @note This function should not be preempted by another XEmacPs_Bd function - * call that modifies the BD space. It is the caller's responsibility to - * provide a mutual exclusion mechanism. - * - *****************************************************************************/ -unsigned XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, unsigned BdLimit, - XEmacPs_Bd ** BdSetPtr) -{ - XEmacPs_Bd *CurBdPtr; - u32 BdStr = 0; - unsigned BdCount; - unsigned BdPartialCount; - - CurBdPtr = RingPtr->HwHead; - BdCount = 0; - BdPartialCount = 0; - - /* If no BDs in work group, then there's nothing to search */ - if (RingPtr->HwCnt == 0) { - *BdSetPtr = NULL; - return (0); - } - - /* Starting at HwHead, keep moving forward in the list until: - * - A BD is encountered with its new/used bit set which means - * hardware has completed processing of that BD. - * - RingPtr->HwTail is reached and RingPtr->HwCnt is reached. - * - The number of requested BDs has been processed - */ - while (BdCount < BdLimit) { - - /* Read the status */ - BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET); - - if (!(XEmacPs_BdIsRxNew(CurBdPtr))) { - break; - } - - BdCount++; - - /* hardware has processed this BD so check the "last" bit. If - * it is clear, then there are more BDs for the current packet. - * Keep a count of these partial packet BDs. - */ - if (BdStr & XEMACPS_RXBUF_EOF_MASK) { - BdPartialCount = 0; - } - else { - BdPartialCount++; - } - - /* Move on to next BD in work group */ - CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr); - } - - /* Subtract off any partial packet BDs found */ - BdCount -= BdPartialCount; - - /* If BdCount is non-zero then BDs were found to return. Set return - * parameters, update pointers and counters, return success - */ - if (BdCount > 0) { - *BdSetPtr = RingPtr->HwHead; - RingPtr->HwCnt -= BdCount; - RingPtr->PostCnt += BdCount; - XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount); - return (BdCount); - } - else { - *BdSetPtr = NULL; - return (0); - } -} - - -/*****************************************************************************/ -/** - * Frees a set of BDs that had been previously retrieved with - * XEmacPs_BdRingFromHw(). - * - * @param RingPtr is a pointer to the instance to be worked on. - * @param NumBd is the number of BDs to free. - * @param BdSetPtr is the head of a list of BDs returned by - * XEmacPs_BdRingFromHw(). - * - * @return - * - XST_SUCCESS if the set of BDs was freed. - * - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with - * XEmacPs_BdRingFromHw(). - * - * @note This function should not be preempted by another XEmacPs_Bd function - * call that modifies the BD space. It is the caller's responsibility to - * provide a mutual exclusion mechanism. - * - *****************************************************************************/ -int XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, unsigned NumBd, - XEmacPs_Bd * BdSetPtr) -{ - /* if no bds to process, simply return. */ - if (0 == NumBd) - return (XST_SUCCESS); - - /* Make sure we are in sync with XEmacPs_BdRingFromHw() */ - if ((RingPtr->PostCnt < NumBd) || (RingPtr->PostHead != BdSetPtr)) { - return (XST_DMA_SG_LIST_ERROR); - } - - /* Update pointers and counters */ - RingPtr->FreeCnt += NumBd; - RingPtr->PostCnt -= NumBd; - XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PostHead, NumBd); - return (XST_SUCCESS); -} - - -/*****************************************************************************/ -/** - * Check the internal data structures of the BD ring for the provided channel. - * The following checks are made: - * - * - Is the BD ring linked correctly in physical address space. - * - Do the internal pointers point to BDs in the ring. - * - Do the internal counters add up. - * - * The channel should be stopped prior to calling this function. - * - * @param RingPtr is a pointer to the instance to be worked on. - * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates - * which direction. - * - * @return - * - XST_SUCCESS if the set of BDs was freed. - * - XST_DMA_SG_NO_LIST if the list has not been created. - * - XST_IS_STARTED if the channel is not stopped. - * - XST_DMA_SG_LIST_ERROR if a problem is found with the internal data - * structures. If this value is returned, the channel should be reset to - * avoid data corruption or system instability. - * - * @note This function should not be preempted by another XEmacPs_Bd function - * call that modifies the BD space. It is the caller's responsibility to - * provide a mutual exclusion mechanism. - * - *****************************************************************************/ -int XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction) -{ - u32 AddrV, AddrP; - unsigned i; - - if ((Direction != XEMACPS_SEND) && (Direction != XEMACPS_RECV)) { - return (XST_INVALID_PARAM); - } - - /* Is the list created */ - if (RingPtr->AllCnt == 0) { - return (XST_DMA_SG_NO_LIST); - } - - /* Can't check if channel is running */ - if (RingPtr->RunState == XST_DMA_SG_IS_STARTED) { - return (XST_IS_STARTED); - } - - /* RunState doesn't make sense */ - else if (RingPtr->RunState != XST_DMA_SG_IS_STOPPED) { - return (XST_DMA_SG_LIST_ERROR); - } - - /* Verify internal pointers point to correct memory space */ - AddrV = (u32) RingPtr->FreeHead; - if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) { - return (XST_DMA_SG_LIST_ERROR); - } - - AddrV = (u32) RingPtr->PreHead; - if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) { - return (XST_DMA_SG_LIST_ERROR); - } - - AddrV = (u32) RingPtr->HwHead; - if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) { - return (XST_DMA_SG_LIST_ERROR); - } - - AddrV = (u32) RingPtr->HwTail; - if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) { - return (XST_DMA_SG_LIST_ERROR); - } - - AddrV = (u32) RingPtr->PostHead; - if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) { - return (XST_DMA_SG_LIST_ERROR); - } - - /* Verify internal counters add up */ - if ((RingPtr->HwCnt + RingPtr->PreCnt + RingPtr->FreeCnt + - RingPtr->PostCnt) != RingPtr->AllCnt) { - return (XST_DMA_SG_LIST_ERROR); - } - - /* Verify BDs are linked correctly */ - AddrV = RingPtr->BaseBdAddr; - AddrP = RingPtr->PhysBaseAddr + RingPtr->Separation; - - for (i = 1; i < RingPtr->AllCnt; i++) { - /* Check BDA for this BD. It should point to next physical addr */ - if (XEmacPs_BdRead(AddrV, XEMACPS_BD_ADDR_OFFSET) != AddrP) { - return (XST_DMA_SG_LIST_ERROR); - } - - /* Move on to next BD */ - AddrV += RingPtr->Separation; - AddrP += RingPtr->Separation; - } - - /* Last BD should have wrap bit set */ - if (XEMACPS_SEND == Direction) { - if (!XEmacPs_BdIsTxWrap(AddrV)) { - return (XST_DMA_SG_LIST_ERROR); - } - } - else { /* XEMACPS_RECV */ - if (!XEmacPs_BdIsRxWrap(AddrV)) { - return (XST_DMA_SG_LIST_ERROR); - } - } - - /* No problems found */ - return (XST_SUCCESS); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps_bdring.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps_bdring.h deleted file mode 100644 index 9c50d618e26160a92cffbc04f3f3a6d06da318db..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps_bdring.h +++ /dev/null @@ -1,242 +0,0 @@ -/* $Id: xemacps_bdring.h,v 1.1.2.1 2011/01/20 03:39:02 sadanan Exp $ */ -/****************************************************************************** -* -* (c) Copyright 2010 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xemacps_bdring.h -* -* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs -* DMA functionalities. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.00a wsy 01/10/10 First release -* </pre> -* -******************************************************************************/ - -#ifndef XEMACPS_BDRING_H /* prevent curcular inclusions */ -#define XEMACPS_BDRING_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - - -/**************************** Type Definitions *******************************/ - -/** This is an internal structure used to maintain the DMA list */ -typedef struct { - u32 PhysBaseAddr;/**< Physical address of 1st BD in list */ - u32 BaseBdAddr; /**< Virtual address of 1st BD in list */ - u32 HighBdAddr; /**< Virtual address of last BD in the list */ - u32 Length; /**< Total size of ring in bytes */ - u32 RunState; /**< Flag to indicate DMA is started */ - u32 Separation; /**< Number of bytes between the starting address - of adjacent BDs */ - XEmacPs_Bd *FreeHead; - /**< First BD in the free group */ - XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */ - XEmacPs_Bd *HwHead; /**< First BD in the work group */ - XEmacPs_Bd *HwTail; /**< Last BD in the work group */ - XEmacPs_Bd *PostHead; - /**< First BD in the post-work group */ - XEmacPs_Bd *BdaRestart; - /**< BDA to load when channel is started */ - unsigned HwCnt; /**< Number of BDs in work group */ - unsigned PreCnt; /**< Number of BDs in pre-work group */ - unsigned FreeCnt; /**< Number of allocatable BDs in the free group */ - unsigned PostCnt; /**< Number of BDs in post-work group */ - unsigned AllCnt; /**< Total Number of BDs for channel */ -} XEmacPs_BdRing; - - -/***************** Macros (Inline Functions) Definitions *********************/ - -/*****************************************************************************/ -/** -* Use this macro at initialization time to determine how many BDs will fit -* in a BD list within the given memory constraints. -* -* The results of this macro can be provided to XEmacPs_BdRingCreate(). -* -* @param Alignment specifies what byte alignment the BDs must fall on and -* must be a power of 2 to get an accurate calculation (32, 64, 128,...) -* @param Bytes is the number of bytes to be used to store BDs. -* -* @return Number of BDs that can fit in the given memory area -* -* @note -* C-style signature: -* u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes) -* -******************************************************************************/ -#define XEmacPs_BdRingCntCalc(Alignment, Bytes) \ - (u32)((Bytes) / ((sizeof(XEmacPs_Bd) + ((Alignment)-1)) & \ - ~((Alignment)-1))) - -/*****************************************************************************/ -/** -* Use this macro at initialization time to determine how many bytes of memory -* is required to contain a given number of BDs at a given alignment. -* -* @param Alignment specifies what byte alignment the BDs must fall on. This -* parameter must be a power of 2 to get an accurate calculation (32, 64, -* 128,...) -* @param NumBd is the number of BDs to calculate memory size requirements for -* -* @return The number of bytes of memory required to create a BD list with the -* given memory constraints. -* -* @note -* C-style signature: -* u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd) -* -******************************************************************************/ -#define XEmacPs_BdRingMemCalc(Alignment, NumBd) \ - (u32)((sizeof(XEmacPs_Bd) + ((Alignment)-1)) & \ - ~((Alignment)-1)) * (NumBd) - -/****************************************************************************/ -/** -* Return the total number of BDs allocated by this channel with -* XEmacPs_BdRingCreate(). -* -* @param RingPtr is the DMA channel to operate on. -* -* @return The total number of BDs allocated for this channel. -* -* @note -* C-style signature: -* u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr) -* -*****************************************************************************/ -#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt) - -/****************************************************************************/ -/** -* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre- -* processing. -* -* @param RingPtr is the DMA channel to operate on. -* -* @return The number of BDs currently allocatable. -* -* @note -* C-style signature: -* u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr) -* -*****************************************************************************/ -#define XEmacPs_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt) - -/****************************************************************************/ -/** -* Return the next BD from BdPtr in a list. -* -* @param RingPtr is the DMA channel to operate on. -* @param BdPtr is the BD to operate on. -* -* @return The next BD in the list relative to the BdPtr parameter. -* -* @note -* C-style signature: -* XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr, -* XEmacPs_Bd *BdPtr) -* -*****************************************************************************/ -#define XEmacPs_BdRingNext(RingPtr, BdPtr) \ - (((u32)(BdPtr) >= (RingPtr)->HighBdAddr) ? \ - (XEmacPs_Bd*)(RingPtr)->BaseBdAddr : \ - (XEmacPs_Bd*)((u32)(BdPtr) + (RingPtr)->Separation)) - -/****************************************************************************/ -/** -* Return the previous BD from BdPtr in the list. -* -* @param RingPtr is the DMA channel to operate on. -* @param BdPtr is the BD to operate on -* -* @return The previous BD in the list relative to the BdPtr parameter. -* -* @note -* C-style signature: -* XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr, -* XEmacPs_Bd *BdPtr) -* -*****************************************************************************/ -#define XEmacPs_BdRingPrev(RingPtr, BdPtr) \ - (((u32)(BdPtr) <= (RingPtr)->BaseBdAddr) ? \ - (XEmacPs_Bd*)(RingPtr)->HighBdAddr : \ - (XEmacPs_Bd*)((u32)(BdPtr) - (RingPtr)->Separation)) - -/************************** Function Prototypes ******************************/ - -/* - * Scatter gather DMA related functions in xemacps_bdring.c - */ -int XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, u32 PhysAddr, - u32 VirtAddr, u32 Alignment, unsigned BdCount); -int XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr, - u8 Direction); -int XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, unsigned NumBd, - XEmacPs_Bd ** BdSetPtr); -int XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, unsigned NumBd, - XEmacPs_Bd * BdSetPtr); -int XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, unsigned NumBd, - XEmacPs_Bd * BdSetPtr); -int XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, unsigned NumBd, - XEmacPs_Bd * BdSetPtr); -unsigned XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, unsigned BdLimit, - XEmacPs_Bd ** BdSetPtr); -unsigned XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, unsigned BdLimit, - XEmacPs_Bd ** BdSetPtr); -int XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction); - -#ifdef __cplusplus -} -#endif - - -#endif /* end of protection macros */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps_control.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps_control.c deleted file mode 100644 index 2daf8adc30f6455676ffcd67c72ae28fcd8068de..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps_control.c +++ /dev/null @@ -1,1084 +0,0 @@ -/* $Id: xemacps_control.c,v 1.1.2.1 2011/01/20 03:39:02 sadanan Exp $ */ -/****************************************************************************** -* -* (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** - * - * @file xemacps_control.c - * - * Functions in this file implement general purpose command and control related - * functionality. See xemacps.h for a detailed description of the driver. - * - * <pre> - * MODIFICATION HISTORY: - * - * Ver Who Date Changes - * ----- ---- -------- ------------------------------------------------------- - * 1.00a wsy 01/10/10 First release - * 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH - * register. Added a new API for setting the BURST length - * in DMACR register. - * </pre> - *****************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xemacps.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - - -/************************** Variable Definitions *****************************/ - - -/*****************************************************************************/ -/** - * Set the MAC address for this driver/device. The address is a 48-bit value. - * The device must be stopped before calling this function. - * - * @param InstancePtr is a pointer to the instance to be worked on. - * @param AddressPtr is a pointer to a 6-byte MAC address. - * @param Index is a index to which MAC (1-4) address. - * - * @return - * - XST_SUCCESS if the MAC address was set successfully - * - XST_DEVICE_IS_STARTED if the device has not yet been stopped - * - *****************************************************************************/ -int XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index) -{ - u32 MacAddr; - u8 *Aptr = (u8 *) AddressPtr; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(AddressPtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid((Index <= XEMACPS_MAX_MAC_ADDR) && (Index > 0)); - - /* Be sure device has been stopped */ - if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) { - return (XST_DEVICE_IS_STARTED); - } - - /* Index ranges 1 to 4, for offset calculation is 0 to 3. */ - Index--; - - /* Set the MAC bits [31:0] in BOT */ - MacAddr = Aptr[0]; - MacAddr |= Aptr[1] << 8; - MacAddr |= Aptr[2] << 16; - MacAddr |= Aptr[3] << 24; - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - (XEMACPS_LADDR1L_OFFSET + Index * 8), MacAddr); - - /* There are reserved bits in TOP so don't affect them */ - MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - (XEMACPS_LADDR1H_OFFSET + (Index * 8))); - - MacAddr &= ~XEMACPS_LADDR_MACH_MASK; - - /* Set MAC bits [47:32] in TOP */ - MacAddr |= Aptr[4]; - MacAddr |= Aptr[5] << 8; - - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - (XEMACPS_LADDR1H_OFFSET + (Index * 8)), MacAddr); - - return (XST_SUCCESS); -} - - -/*****************************************************************************/ -/** - * Get the MAC address for this driver/device. - * - * @param InstancePtr is a pointer to the instance to be worked on. - * @param AddressPtr is an output parameter, and is a pointer to a buffer into - * which the current MAC address will be copied. - * @param Index is a index to which MAC (1-4) address. - * - *****************************************************************************/ -void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index) -{ - u32 MacAddr; - u8 *Aptr = (u8 *) AddressPtr; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(AddressPtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid((Index <= XEMACPS_MAX_MAC_ADDR) && (Index > 0)); - - /* Index ranges 1 to 4, for offset calculation is 0 to 3. */ - Index--; - - MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - (XEMACPS_LADDR1L_OFFSET + (Index * 8))); - Aptr[0] = (u8) MacAddr; - Aptr[1] = (u8) (MacAddr >> 8); - Aptr[2] = (u8) (MacAddr >> 16); - Aptr[3] = (u8) (MacAddr >> 24); - - /* Read MAC bits [47:32] in TOP */ - MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - (XEMACPS_LADDR1H_OFFSET + (Index * 8))); - Aptr[4] = (u8) MacAddr; - Aptr[5] = (u8) (MacAddr >> 8); -} - - -/*****************************************************************************/ -/** - * Set 48-bit MAC addresses in hash table. - * The device must be stopped before calling this function. - * - * The hash address register is 64 bits long and takes up two locations in - * the memory map. The least significant bits are stored in hash register - * bottom and the most significant bits in hash register top. - * - * The unicast hash enable and the multicast hash enable bits in the network - * configuration register enable the reception of hash matched frames. The - * destination address is reduced to a 6 bit index into the 64 bit hash - * register using the following hash function. The hash function is an XOR - * of every sixth bit of the destination address. - * - * <pre> - * hash_index[05] = da[05]^da[11]^da[17]^da[23]^da[29]^da[35]^da[41]^da[47] - * hash_index[04] = da[04]^da[10]^da[16]^da[22]^da[28]^da[34]^da[40]^da[46] - * hash_index[03] = da[03]^da[09]^da[15]^da[21]^da[27]^da[33]^da[39]^da[45] - * hash_index[02] = da[02]^da[08]^da[14]^da[20]^da[26]^da[32]^da[38]^da[44] - * hash_index[01] = da[01]^da[07]^da[13]^da[19]^da[25]^da[31]^da[37]^da[43] - * hash_index[00] = da[00]^da[06]^da[12]^da[18]^da[24]^da[30]^da[36]^da[42] - * </pre> - * - * da[0] represents the least significant bit of the first byte received, - * that is, the multicast/unicast indicator, and da[47] represents the most - * significant bit of the last byte received. - * - * If the hash index points to a bit that is set in the hash register then - * the frame will be matched according to whether the frame is multicast - * or unicast. - * - * A multicast match will be signaled if the multicast hash enable bit is - * set, da[0] is logic 1 and the hash index points to a bit set in the hash - * register. - * - * A unicast match will be signaled if the unicast hash enable bit is set, - * da[0] is logic 0 and the hash index points to a bit set in the hash - * register. - * - * To receive all multicast frames, the hash register should be set with - * all ones and the multicast hash enable bit should be set in the network - * configuration register. - * - * - * @param InstancePtr is a pointer to the instance to be worked on. - * @param AddressPtr is a pointer to a 6-byte MAC address. - * - * @return - * - XST_SUCCESS if the HASH MAC address was set successfully - * - XST_DEVICE_IS_STARTED if the device has not yet been stopped - * - XST_INVALID_PARAM if the HASH MAC address passed in does not meet - * requirement after calculation - * - * @note - * Having Aptr be unsigned type prevents the following operations from sign - * extending. - *****************************************************************************/ -int XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr) -{ - u32 HashAddr; - u8 *Aptr = (u8 *) AddressPtr; - u8 Temp1, Temp2, Temp3, Temp4, Temp5, Temp6, Temp7, Temp8; - int Result; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(AddressPtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* Be sure device has been stopped */ - if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) { - return (XST_DEVICE_IS_STARTED); - } - Temp1 = Aptr[0] & 0x3F; - Temp2 = ((Aptr[0] >> 6) & 0x3) | ((Aptr[1] & 0xF) << 2); - Temp3 = ((Aptr[1] >> 4) & 0xF) | ((Aptr[2] & 0x3) << 4); - Temp4 = ((Aptr[2] >> 2) & 0x3F); - Temp5 = Aptr[3] & 0x3F; - Temp6 = ((Aptr[3] >> 6) & 0x3) | ((Aptr[4] & 0xF) << 2); - Temp7 = ((Aptr[4] >> 4) & 0xF) | ((Aptr[5] & 0x3) << 4); - Temp8 = ((Aptr[5] >> 2) & 0x3F); - - Result = Temp1 ^ Temp2 ^ Temp3 ^ Temp4 ^ Temp5 ^ Temp6 ^ Temp7 ^ Temp8; - - if (Result >= XEMACPS_MAX_HASH_BITS) { - return (XST_INVALID_PARAM); - } - - if (Result < 32) { - HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_HASHL_OFFSET); - HashAddr |= (1 << Result); - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_HASHL_OFFSET, HashAddr); - } else { - HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_HASHH_OFFSET); - HashAddr |= (1 << (Result - 32)); - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_HASHH_OFFSET, HashAddr); - } - - return (XST_SUCCESS); -} - -/*****************************************************************************/ -/** - * Delete 48-bit MAC addresses in hash table. - * The device must be stopped before calling this function. - * - * @param InstancePtr is a pointer to the instance to be worked on. - * @param AddressPtr is a pointer to a 6-byte MAC address. - * - * @return - * - XST_SUCCESS if the HASH MAC address was deleted successfully - * - XST_DEVICE_IS_STARTED if the device has not yet been stopped - * - XST_INVALID_PARAM if the HASH MAC address passed in does not meet - * requirement after calculation - * - * @note - * Having Aptr be unsigned type prevents the following operations from sign - * extending. - *****************************************************************************/ -int XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr) -{ - u32 HashAddr; - u8 *Aptr = (u8 *) AddressPtr; - u8 Temp1, Temp2, Temp3, Temp4, Temp5, Temp6, Temp7, Temp8; - int Result; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(AddressPtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* Be sure device has been stopped */ - if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) { - return (XST_DEVICE_IS_STARTED); - } - Temp1 = Aptr[0] & 0x3F; - Temp2 = ((Aptr[0] >> 6) & 0x3) | ((Aptr[1] & 0xF) << 2); - Temp3 = ((Aptr[1] >> 4) & 0xF) | ((Aptr[2] & 0x3) << 4); - Temp4 = ((Aptr[2] >> 2) & 0x3F); - Temp5 = Aptr[3] & 0x3F; - Temp6 = ((Aptr[3] >> 6) & 0x3) | ((Aptr[4] & 0xF) << 2); - Temp7 = ((Aptr[4] >> 4) & 0xF) | ((Aptr[5] & 0x3) << 4); - Temp8 = ((Aptr[5] >> 2) & 0x3F); - - Result = Temp1 ^ Temp2 ^ Temp3 ^ Temp4 ^ Temp5 ^ Temp6 ^ Temp7 ^ Temp8; - - if (Result >= XEMACPS_MAX_HASH_BITS) { - return (XST_INVALID_PARAM); - } - - if (Result < 32) { - HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_HASHL_OFFSET); - HashAddr &= (~(1 << Result)); - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_HASHL_OFFSET, HashAddr); - } else { - HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_HASHH_OFFSET); - HashAddr &= (~(1 << (Result - 32))); - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_HASHH_OFFSET, HashAddr); - } - - return (XST_SUCCESS); -} - - -/*****************************************************************************/ -/** - * Clear the Hash registers for the mac address pointed by AddressPtr. - * - * @param InstancePtr is a pointer to the instance to be worked on. - * - *****************************************************************************/ -void XEmacPs_ClearHash(XEmacPs *InstancePtr) -{ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_HASHL_OFFSET, 0x0); - - /* write bits [63:32] in TOP */ - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_HASHH_OFFSET, 0x0); -} - - -/*****************************************************************************/ -/** - * Get the Hash address for this driver/device. - * - * @param InstancePtr is a pointer to the instance to be worked on. - * @param AddressPtr is an output parameter, and is a pointer to a buffer into - * which the current HASH MAC address will be copied. - * - *****************************************************************************/ -void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr) -{ - u32 *Aptr = (u32 *) AddressPtr; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(AddressPtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - Aptr[0] = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_HASHL_OFFSET); - - /* Read Hash bits [63:32] in TOP */ - Aptr[1] = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_HASHH_OFFSET); -} - - -/*****************************************************************************/ -/** - * Set the Type ID match for this driver/device. The register is a 32-bit - * value. The device must be stopped before calling this function. - * - * @param InstancePtr is a pointer to the instance to be worked on. - * @param Id_Check is type ID to be configured. - * @param Index is a index to which Type ID (1-4). - * - * @return - * - XST_SUCCESS if the MAC address was set successfully - * - XST_DEVICE_IS_STARTED if the device has not yet been stopped - * - *****************************************************************************/ -int XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index) -{ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid((Index <= XEMACPS_MAX_TYPE_ID) && (Index > 0)); - - /* Be sure device has been stopped */ - if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) { - return (XST_DEVICE_IS_STARTED); - } - - /* Index ranges 1 to 4, for offset calculation is 0 to 3. */ - Index--; - - /* Set the ID bits in MATCHx register */ - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - (XEMACPS_MATCH1_OFFSET + (Index * 4)), Id_Check); - - return (XST_SUCCESS); -} - -/*****************************************************************************/ -/** - * Set options for the driver/device. The driver should be stopped with - * XEmacPs_Stop() before changing options. - * - * @param InstancePtr is a pointer to the instance to be worked on. - * @param Options are the options to set. Multiple options can be set by OR'ing - * XTE_*_OPTIONS constants together. Options not specified are not - * affected. - * - * @return - * - XST_SUCCESS if the options were set successfully - * - XST_DEVICE_IS_STARTED if the device has not yet been stopped - * - * @note - * See xemacps.h for a description of the available options. - * - *****************************************************************************/ -int XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options) -{ - u32 Reg; /* Generic register contents */ - u32 RegNetCfg; /* Reflects original contents of NET_CONFIG */ - u32 RegNewNetCfg; /* Reflects new contents of NET_CONFIG */ - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* Be sure device has been stopped */ - if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) { - return (XST_DEVICE_IS_STARTED); - } - - /* Many of these options will change the NET_CONFIG registers. - * To reduce the amount of IO to the device, group these options here - * and change them all at once. - */ - - /* Grab current register contents */ - RegNetCfg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCFG_OFFSET); - RegNewNetCfg = RegNetCfg; - - /* - * It is configured to max 1536. - */ - if (Options & XEMACPS_FRAME1536_OPTION) { - RegNewNetCfg |= (XEMACPS_NWCFG_1536RXEN_MASK); - } - - /* Turn on VLAN packet only, only VLAN tagged will be accepted */ - if (Options & XEMACPS_VLAN_OPTION) { - RegNewNetCfg |= XEMACPS_NWCFG_NVLANDISC_MASK; - } - - /* Turn on FCS stripping on receive packets */ - if (Options & XEMACPS_FCS_STRIP_OPTION) { - RegNewNetCfg |= XEMACPS_NWCFG_FCSREM_MASK; - } - - /* Turn on length/type field checking on receive packets */ - if (Options & XEMACPS_LENTYPE_ERR_OPTION) { - RegNewNetCfg |= XEMACPS_NWCFG_LENGTHERRDSCRD_MASK; - } - - /* Turn on flow control */ - if (Options & XEMACPS_FLOW_CONTROL_OPTION) { - RegNewNetCfg |= XEMACPS_NWCFG_PAUSEEN_MASK; - } - - /* Turn on promiscuous frame filtering (all frames are received) */ - if (Options & XEMACPS_PROMISC_OPTION) { - RegNewNetCfg |= XEMACPS_NWCFG_COPYALLEN_MASK; - } - - /* Allow broadcast address reception */ - if (Options & XEMACPS_BROADCAST_OPTION) { - RegNewNetCfg &= ~XEMACPS_NWCFG_BCASTDI_MASK; - } - - /* Allow multicast address filtering */ - if (Options & XEMACPS_MULTICAST_OPTION) { - RegNewNetCfg |= XEMACPS_NWCFG_MCASTHASHEN_MASK; - } - - /* enable RX checksum offload */ - if (Options & XEMACPS_RX_CHKSUM_ENABLE_OPTION) { - RegNewNetCfg |= XEMACPS_NWCFG_RXCHKSUMEN_MASK; - } - - /* Officially change the NET_CONFIG registers if it needs to be - * modified. - */ - if (RegNetCfg != RegNewNetCfg) { - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCFG_OFFSET, RegNewNetCfg); - } - - /* Enable TX checksum offload */ - if (Options & XEMACPS_TX_CHKSUM_ENABLE_OPTION) { - Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_DMACR_OFFSET); - Reg |= XEMACPS_DMACR_TCPCKSUM_MASK; - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_DMACR_OFFSET, Reg); - } - - /* Enable transmitter */ - if (Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) { - Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCTRL_OFFSET); - Reg |= XEMACPS_NWCTRL_TXEN_MASK; - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCTRL_OFFSET, Reg); - } - - /* Enable receiver */ - if (Options & XEMACPS_RECEIVER_ENABLE_OPTION) { - Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCTRL_OFFSET); - Reg |= XEMACPS_NWCTRL_RXEN_MASK; - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCTRL_OFFSET, Reg); - } - - /* The remaining options not handled here are managed elsewhere in the - * driver. No register modifications are needed at this time. Reflecting - * the option in InstancePtr->Options is good enough for now. - */ - - /* Set options word to its new value */ - InstancePtr->Options |= Options; - - return (XST_SUCCESS); -} - - -/*****************************************************************************/ -/** - * Clear options for the driver/device - * - * @param InstancePtr is a pointer to the instance to be worked on. - * @param Options are the options to clear. Multiple options can be cleared by - * OR'ing XEMACPS_*_OPTIONS constants together. Options not specified - * are not affected. - * - * @return - * - XST_SUCCESS if the options were set successfully - * - XST_DEVICE_IS_STARTED if the device has not yet been stopped - * - * @note - * See xemacps.h for a description of the available options. - * - *****************************************************************************/ -int XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options) -{ - u32 Reg; /* Generic */ - u32 RegNetCfg; /* Reflects original contents of NET_CONFIG */ - u32 RegNewNetCfg; /* Reflects new contents of NET_CONFIG */ - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* Be sure device has been stopped */ - if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) { - return (XST_DEVICE_IS_STARTED); - } - - /* Many of these options will change the NET_CONFIG registers. - * To reduce the amount of IO to the device, group these options here - * and change them all at once. - */ - - /* Grab current register contents */ - RegNetCfg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCFG_OFFSET); - RegNewNetCfg = RegNetCfg; - - /* There is only RX configuration!? - * It is configured in two different length, upto 1536 and 10240 bytes - */ - if (Options & XEMACPS_FRAME1536_OPTION) { - RegNewNetCfg &= ~XEMACPS_NWCFG_1536RXEN_MASK; - } - - /* Turn off VLAN packet only */ - if (Options & XEMACPS_VLAN_OPTION) { - RegNewNetCfg &= ~XEMACPS_NWCFG_NVLANDISC_MASK; - } - - /* Turn off FCS stripping on receive packets */ - if (Options & XEMACPS_FCS_STRIP_OPTION) { - RegNewNetCfg &= ~XEMACPS_NWCFG_FCSREM_MASK; - } - - /* Turn off length/type field checking on receive packets */ - if (Options & XEMACPS_LENTYPE_ERR_OPTION) { - RegNewNetCfg &= ~XEMACPS_NWCFG_LENGTHERRDSCRD_MASK; - } - - /* Turn off flow control */ - if (Options & XEMACPS_FLOW_CONTROL_OPTION) { - RegNewNetCfg &= ~XEMACPS_NWCFG_PAUSEEN_MASK; - } - - /* Turn off promiscuous frame filtering (all frames are received) */ - if (Options & XEMACPS_PROMISC_OPTION) { - RegNewNetCfg &= ~XEMACPS_NWCFG_COPYALLEN_MASK; - } - - /* Disallow broadcast address filtering => broadcast reception */ - if (Options & XEMACPS_BROADCAST_OPTION) { - RegNewNetCfg |= XEMACPS_NWCFG_BCASTDI_MASK; - } - - /* Disallow multicast address filtering */ - if (Options & XEMACPS_MULTICAST_OPTION) { - RegNewNetCfg &= ~XEMACPS_NWCFG_MCASTHASHEN_MASK; - } - - /* Disable RX checksum offload */ - if (Options & XEMACPS_RX_CHKSUM_ENABLE_OPTION) { - RegNewNetCfg &= ~XEMACPS_NWCFG_RXCHKSUMEN_MASK; - } - - /* Officially change the NET_CONFIG registers if it needs to be - * modified. - */ - if (RegNetCfg != RegNewNetCfg) { - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCFG_OFFSET, RegNewNetCfg); - } - - /* Disable TX checksum offload */ - if (Options & XEMACPS_TX_CHKSUM_ENABLE_OPTION) { - Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_DMACR_OFFSET); - Reg &= ~XEMACPS_DMACR_TCPCKSUM_MASK; - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_DMACR_OFFSET, Reg); - } - - /* Disable transmitter */ - if (Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) { - Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCTRL_OFFSET); - Reg &= ~XEMACPS_NWCTRL_TXEN_MASK; - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCTRL_OFFSET, Reg); - } - - /* Disable receiver */ - if (Options & XEMACPS_RECEIVER_ENABLE_OPTION) { - Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCTRL_OFFSET); - Reg &= ~XEMACPS_NWCTRL_RXEN_MASK; - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCTRL_OFFSET, Reg); - } - - /* The remaining options not handled here are managed elsewhere in the - * driver. No register modifications are needed at this time. Reflecting - * option in InstancePtr->Options is good enough for now. - */ - - /* Set options word to its new value */ - InstancePtr->Options &= ~Options; - - return (XST_SUCCESS); -} - - -/*****************************************************************************/ -/** - * Get current option settings - * - * @param InstancePtr is a pointer to the instance to be worked on. - * - * @return - * A bitmask of XTE_*_OPTION constants. Any bit set to 1 is to be interpreted - * as a set opion. - * - * @note - * See xemacps.h for a description of the available options. - * - *****************************************************************************/ -u32 XEmacPs_GetOptions(XEmacPs *InstancePtr) -{ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - return (InstancePtr->Options); -} - - -/*****************************************************************************/ -/** - * Send a pause packet - * - * @param InstancePtr is a pointer to the instance to be worked on. - * - * @return - * - XST_SUCCESS if pause frame transmission was initiated - * - XST_DEVICE_IS_STOPPED if the device has not been started. - * - *****************************************************************************/ -int XEmacPs_SendPausePacket(XEmacPs *InstancePtr) -{ - u32 Reg; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* Make sure device is ready for this operation */ - if (InstancePtr->IsStarted != XIL_COMPONENT_IS_STARTED) { - return (XST_DEVICE_IS_STOPPED); - } - - /* Send flow control frame */ - Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCTRL_OFFSET); - Reg |= XEMACPS_NWCTRL_PAUSETX_MASK; - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCTRL_OFFSET, Reg); - return (XST_SUCCESS); -} - -/*****************************************************************************/ -/** - * XEmacPs_GetOperatingSpeed gets the current operating link speed. This may - * be the value set by XEmacPs_SetOperatingSpeed() or a hardware default. - * - * @param InstancePtr references the TEMAC channel on which to operate. - * - * @return XEmacPs_GetOperatingSpeed returns the link speed in units of - * megabits per second. - * - * @note - * - *****************************************************************************/ -u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr) -{ - u32 Reg; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCFG_OFFSET); - - if (Reg & XEMACPS_NWCFG_1000_MASK) { - return (1000); - } else { - if (Reg & XEMACPS_NWCFG_100_MASK) { - return (100); - } else { - return (10); - } - } -} - - -/*****************************************************************************/ -/** - * XEmacPs_SetOperatingSpeed sets the current operating link speed. For any - * traffic to be passed, this speed must match the current MII/GMII/SGMII/RGMII - * link speed. - * - * @param InstancePtr references the TEMAC channel on which to operate. - * @param Speed is the speed to set in units of Mbps. Valid values are 10, 100, - * or 1000. XEmacPs_SetOperatingSpeed ignores invalid values. - * - * @note - * - *****************************************************************************/ -void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed) -{ - u32 Reg; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid((Speed == 10) || (Speed == 100) || (Speed == 1000)); - - Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCFG_OFFSET); - Reg &= ~(XEMACPS_NWCFG_1000_MASK | XEMACPS_NWCFG_100_MASK); - - switch (Speed) { - case 10: - break; - - case 100: - Reg |= XEMACPS_NWCFG_100_MASK; - break; - - case 1000: - Reg |= XEMACPS_NWCFG_1000_MASK; - break; - - default: - return; - } - - /* Set register and return */ - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCFG_OFFSET, Reg); -} - - -/*****************************************************************************/ -/** - * Set the MDIO clock divisor. - * - * Calculating the divisor: - * - * <pre> - * f[HOSTCLK] - * f[MDC] = ----------------- - * (1 + Divisor) * 2 - * </pre> - * - * where f[HOSTCLK] is the bus clock frequency in MHz, and f[MDC] is the - * MDIO clock frequency in MHz to the PHY. Typically, f[MDC] should not - * exceed 2.5 MHz. Some PHYs can tolerate faster speeds which means faster - * access. Here is the table to show values to generate MDC, - * - * <pre> - * 000 : divide pclk by 8 (pclk up to 20 MHz) - * 001 : divide pclk by 16 (pclk up to 40 MHz) - * 010 : divide pclk by 32 (pclk up to 80 MHz) - * 011 : divide pclk by 48 (pclk up to 120 MHz) - * 100 : divide pclk by 64 (pclk up to 160 MHz) - * 101 : divide pclk by 96 (pclk up to 240 MHz) - * 110 : divide pclk by 128 (pclk up to 320 MHz) - * 111 : divide pclk by 224 (pclk up to 540 MHz) - * </pre> - * - * @param InstancePtr is a pointer to the instance to be worked on. - * @param Divisor is the divisor to set. Range is 0b000 to 0b111. - * - *****************************************************************************/ -void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, XEmacPs_MdcDiv Divisor) -{ - u32 Reg; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Divisor <= 0x7); /* only last three bits are valid */ - - Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCFG_OFFSET); - /* clear these three bits, could be done with mask */ - Reg &= ~XEMACPS_NWCFG_MDCCLKDIV_MASK; - - Reg |= (Divisor << XEMACPS_NWCFG_MDC_SHIFT_MASK); - - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCFG_OFFSET, Reg); - -} - - -/*****************************************************************************/ -/** -* Read the current value of the PHY register indicated by the PhyAddress and -* the RegisterNum parameters. The MAC provides the driver with the ability to -* talk to a PHY that adheres to the Media Independent Interface (MII) as -* defined in the IEEE 802.3 standard. -* -* Prior to PHY access with this function, the user should have setup the MDIO -* clock with XEmacPs_SetMdioDivisor(). -* -* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. -* @param PhyAddress is the address of the PHY to be read (supports multiple -* PHYs) -* @param RegisterNum is the register number, 0-31, of the specific PHY register -* to read -* @param PhyDataPtr is an output parameter, and points to a 16-bit buffer into -* which the current value of the register will be copied. -* -* @return -* -* - XST_SUCCESS if the PHY was read from successfully -* - XST_EMAC_MII_BUSY if there is another PHY operation in progress -* -* @note -* -* This function is not thread-safe. The user must provide mutually exclusive -* access to this function if there are to be multiple threads that can call it. -* -* There is the possibility that this function will not return if the hardware -* is broken (i.e., it never sets the status bit indicating that the read is -* done). If this is of concern to the user, the user should provide a mechanism -* suitable to their needs for recovery. -* -* For the duration of this function, all host interface reads and writes are -* blocked to the current XEmacPs instance. -* -******************************************************************************/ -int XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress, - u32 RegisterNum, u16 *PhyDataPtr) -{ - u32 Mgtcr; - volatile u32 Ipisr; - - Xil_AssertNonvoid(InstancePtr != NULL); - - /* Make sure no other PHY operation is currently in progress */ - if (!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWSR_OFFSET) & - XEMACPS_NWSR_MDIOIDLE_MASK)) { - return (XST_EMAC_MII_BUSY); - } - - /* Construct Mgtcr mask for the operation */ - Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_R_MASK | - (PhyAddress << XEMACPS_PHYMNTNC_PHYAD_SHIFT_MASK) | - (RegisterNum << XEMACPS_PHYMNTNC_PHREG_SHIFT_MASK); - - /* Write Mgtcr and wait for completion */ - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_PHYMNTNC_OFFSET, Mgtcr); - - do { - Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWSR_OFFSET); - } while ((Ipisr & XEMACPS_NWSR_MDIOIDLE_MASK) == 0); - - /* Read data */ - *PhyDataPtr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_PHYMNTNC_OFFSET); - - return (XST_SUCCESS); -} - - -/*****************************************************************************/ -/** -* Write data to the specified PHY register. The Ethernet driver does not -* require the device to be stopped before writing to the PHY. Although it is -* probably a good idea to stop the device, it is the responsibility of the -* application to deem this necessary. The MAC provides the driver with the -* ability to talk to a PHY that adheres to the Media Independent Interface -* (MII) as defined in the IEEE 802.3 standard. -* -* Prior to PHY access with this function, the user should have setup the MDIO -* clock with XEmacPs_SetMdioDivisor(). -* -* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. -* @param PhyAddress is the address of the PHY to be written (supports multiple -* PHYs) -* @param RegisterNum is the register number, 0-31, of the specific PHY register -* to write -* @param PhyData is the 16-bit value that will be written to the register -* -* @return -* -* - XST_SUCCESS if the PHY was written to successfully. Since there is no error -* status from the MAC on a write, the user should read the PHY to verify the -* write was successful. -* - XST_EMAC_MII_BUSY if there is another PHY operation in progress -* -* @note -* -* This function is not thread-safe. The user must provide mutually exclusive -* access to this function if there are to be multiple threads that can call it. -* -* There is the possibility that this function will not return if the hardware -* is broken (i.e., it never sets the status bit indicating that the write is -* done). If this is of concern to the user, the user should provide a mechanism -* suitable to their needs for recovery. -* -* For the duration of this function, all host interface reads and writes are -* blocked to the current XEmacPs instance. -* -******************************************************************************/ -int XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress, - u32 RegisterNum, u16 PhyData) -{ - u32 Mgtcr; - volatile u32 Ipisr; - - Xil_AssertNonvoid(InstancePtr != NULL); - - /* Make sure no other PHY operation is currently in progress */ - if (!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWSR_OFFSET) & - XEMACPS_NWSR_MDIOIDLE_MASK)) { - return (XST_EMAC_MII_BUSY); - } - - /* Construct Mgtcr mask for the operation */ - Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_W_MASK | - (PhyAddress << XEMACPS_PHYMNTNC_PHYAD_SHIFT_MASK) | - (RegisterNum << XEMACPS_PHYMNTNC_PHREG_SHIFT_MASK) | PhyData; - - /* Write Mgtcr and wait for completion */ - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_PHYMNTNC_OFFSET, Mgtcr); - - do { - Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWSR_OFFSET); - } while ((Ipisr & XEMACPS_NWSR_MDIOIDLE_MASK) == 0); - - return (XST_SUCCESS); -} - -/*****************************************************************************/ -/** -* API to update the Burst length in the DMACR register. -* -* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. -* @param BLength is the length in bytes for the dma burst. -* -* @return None -* -******************************************************************************/ -void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, int BLength) -{ - u32 Reg; - u32 RegUpdateVal = 0; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid((BLength == XEMACPS_SINGLE_BURST) || - (BLength == XEMACPS_4BYTE_BURST) || - (BLength == XEMACPS_8BYTE_BURST) || - (BLength == XEMACPS_16BYTE_BURST)); - - switch (BLength) { - case XEMACPS_SINGLE_BURST: - RegUpdateVal = XEMACPS_DMACR_SINGLE_AHB_BURST; - break; - - case XEMACPS_4BYTE_BURST: - RegUpdateVal = XEMACPS_DMACR_INCR4_AHB_BURST; - break; - - case XEMACPS_8BYTE_BURST: - RegUpdateVal = XEMACPS_DMACR_INCR8_AHB_BURST; - break; - - case XEMACPS_16BYTE_BURST: - RegUpdateVal = XEMACPS_DMACR_INCR16_AHB_BURST; - break; - - default: - break; - } - Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_DMACR_OFFSET); - - Reg &= (~XEMACPS_DMACR_BLENGTH_MASK); - Reg |= RegUpdateVal; - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET, - Reg); -} \ No newline at end of file diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps_g.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps_g.c deleted file mode 100644 index f06875cb11790d36ab814642cf9aa638ce83c42b..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps_g.c +++ /dev/null @@ -1,30 +0,0 @@ - -/******************************************************************* -* -* CAUTION: This file is automatically generated by libgen. -* Version: Xilinx EDK 14.7 EDK_P.20131013 -* DO NOT EDIT. -* -* Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. - -* -* Description: Driver configuration -* -*******************************************************************/ - -#include "xparameters.h" -#include "xemacps.h" - -/* -* The configuration table for devices -*/ - -XEmacPs_Config XEmacPs_ConfigTable[] = -{ - { - XPAR_PS7_ETHERNET_0_DEVICE_ID, - XPAR_PS7_ETHERNET_0_BASEADDR - } -}; - - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps_hw.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps_hw.c deleted file mode 100644 index 0b6f4715497c1ae522ee90bc2d0a9b9298a4666f..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps_hw.c +++ /dev/null @@ -1,132 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xemacps_hw.c -* -* This file contains the implementation of the ethernet interface reset sequence -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.05a kpc 28/06/13 First release -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xparameters.h" -#include "xemacps_hw.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - -/*****************************************************************************/ -/** -* This function perform the reset sequence to the given emacps interface by -* configuring the appropriate control bits in the emacps specifc registers. -* the emacps reset squence involves the following steps -* Disable all the interuupts -* Clear the status registers -* Disable Rx and Tx engines -* Update the Tx and Rx descriptor queue registers with reset values -* Update the other relevant control registers with reset value -* -* @param BaseAddress of the interface -* -* @return N/A -* -* @note -* This function will not modify the slcr registers that are relavant for -* emacps controller -******************************************************************************/ -void XEmacPs_ResetHw(u32 BaseAddr) -{ - u32 RegVal = 0; - - /* Disable the interrupts */ - XEmacPs_WriteReg(BaseAddr,XEMACPS_IDR_OFFSET,0x0); - - /* Stop transmission,disable loopback and Stop tx and Rx engines */ - RegVal = XEmacPs_ReadReg(BaseAddr,XEMACPS_NWCTRL_OFFSET); - RegVal &= ~(XEMACPS_NWCTRL_TXEN_MASK| - XEMACPS_NWCTRL_RXEN_MASK| - XEMACPS_NWCTRL_HALTTX_MASK| - XEMACPS_NWCTRL_LOOPEN_MASK); - /* Clear the statistic registers, flush the packets in DPRAM*/ - RegVal |= (XEMACPS_NWCTRL_STATCLR_MASK| - XEMACPS_NWCTRL_FLUSH_DPRAM_MASK); - XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCTRL_OFFSET,RegVal); - /* Clear the interrupt status */ - XEmacPs_WriteReg(BaseAddr,XEMACPS_ISR_OFFSET,XEMACPS_IXR_ALL_MASK); - /* Clear the tx status */ - XEmacPs_WriteReg(BaseAddr,XEMACPS_TXSR_OFFSET,XEMACPS_TXSR_ERROR_MASK| - XEMACPS_TXSR_TXCOMPL_MASK| - XEMACPS_TXSR_TXGO_MASK); - /* Clear the rx status */ - XEmacPs_WriteReg(BaseAddr,XEMACPS_RXSR_OFFSET, - XEMACPS_RXSR_FRAMERX_MASK); - /* Clear the tx base address */ - XEmacPs_WriteReg(BaseAddr,XEMACPS_TXQBASE_OFFSET,0x0); - /* Clear the rx base address */ - XEmacPs_WriteReg(BaseAddr,XEMACPS_RXQBASE_OFFSET,0x0); - /* Update the network config register with reset value */ - XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCFG_OFFSET,XEMACPS_NWCFG_RESET_MASK); - /* Update the hash address registers with reset value */ - XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHL_OFFSET,0x0); - XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHH_OFFSET,0x0); -} - - - - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps_hw.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps_hw.h deleted file mode 100644 index 4f81fc1a7dcd0a4069bbc25a0aad244c81115b2c..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps_hw.h +++ /dev/null @@ -1,603 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xemacps_hw.h -* -* This header file contains identifiers and low-level driver functions (or -* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device. -* High-level driver functions are defined in xemacps.h. -* -* @note -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.00a wsy 01/10/10 First release. -* 1.02a asa 11/05/12 Added hash defines for DMACR burst length configuration. -* 1.05a kpc 28/06/13 Added XEmacPs_ResetHw function prototype -* </pre> -* -******************************************************************************/ - -#ifndef XEMACPS_HW_H /* prevent circular inclusions */ -#define XEMACPS_HW_H /* by using protection macros */ - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xil_io.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/************************** Constant Definitions *****************************/ - -#define XEMACPS_MAX_MAC_ADDR 4 /**< Maxmum number of mac address - supported */ -#define XEMACPS_MAX_TYPE_ID 4 /**< Maxmum number of type id supported */ -#define XEMACPS_BD_ALIGNMENT 4 /**< Minimum buffer descriptor alignment - on the local bus */ -#define XEMACPS_RX_BUF_ALIGNMENT 4 /**< Minimum buffer alignment when using - options that impose alignment - restrictions on the buffer data on - the local bus */ - -/** @name Direction identifiers - * - * These are used by several functions and callbacks that need - * to specify whether an operation specifies a send or receive channel. - * @{ - */ -#define XEMACPS_SEND 1 /**< send direction */ -#define XEMACPS_RECV 2 /**< receive direction */ -/*@}*/ - -/** @name MDC clock division - * currently supporting 8, 16, 32, 48, 64, 96, 128, 224. - * @{ - */ -typedef enum { MDC_DIV_8 = 0, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48, - MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224 -} XEmacPs_MdcDiv; - -/*@}*/ - -#define XEMACPS_RX_BUF_SIZE 1536 /**< Specify the receive buffer size in - bytes, 64, 128, ... 10240 */ -#define XEMACPS_RX_BUF_UNIT 64 /**< Number of receive buffer bytes as a - unit, this is HW setup */ - -#define XEMACPS_MAX_RXBD 128 /**< Size of RX buffer descriptor queues */ -#define XEMACPS_MAX_TXBD 128 /**< Size of TX buffer descriptor queues */ - -#define XEMACPS_MAX_HASH_BITS 64 /**< Maximum value for hash bits. 2**6 */ - -/* Register offset definitions. Unless otherwise noted, register access is - * 32 bit. Names are self explained here. - */ - -#define XEMACPS_NWCTRL_OFFSET 0x00000000 /**< Network Control reg */ -#define XEMACPS_NWCFG_OFFSET 0x00000004 /**< Network Config reg */ -#define XEMACPS_NWSR_OFFSET 0x00000008 /**< Network Status reg */ - -#define XEMACPS_DMACR_OFFSET 0x00000010 /**< DMA Control reg */ -#define XEMACPS_TXSR_OFFSET 0x00000014 /**< TX Status reg */ -#define XEMACPS_RXQBASE_OFFSET 0x00000018 /**< RX Q Base address reg */ -#define XEMACPS_TXQBASE_OFFSET 0x0000001C /**< TX Q Base address reg */ -#define XEMACPS_RXSR_OFFSET 0x00000020 /**< RX Status reg */ - -#define XEMACPS_ISR_OFFSET 0x00000024 /**< Interrupt Status reg */ -#define XEMACPS_IER_OFFSET 0x00000028 /**< Interrupt Enable reg */ -#define XEMACPS_IDR_OFFSET 0x0000002C /**< Interrupt Disable reg */ -#define XEMACPS_IMR_OFFSET 0x00000030 /**< Interrupt Mask reg */ - -#define XEMACPS_PHYMNTNC_OFFSET 0x00000034 /**< Phy Maintaince reg */ -#define XEMACPS_RXPAUSE_OFFSET 0x00000038 /**< RX Pause Time reg */ -#define XEMACPS_TXPAUSE_OFFSET 0x0000003C /**< TX Pause Time reg */ - -#define XEMACPS_HASHL_OFFSET 0x00000080 /**< Hash Low address reg */ -#define XEMACPS_HASHH_OFFSET 0x00000084 /**< Hash High address reg */ - -#define XEMACPS_LADDR1L_OFFSET 0x00000088 /**< Specific1 addr low reg */ -#define XEMACPS_LADDR1H_OFFSET 0x0000008C /**< Specific1 addr high reg */ -#define XEMACPS_LADDR2L_OFFSET 0x00000090 /**< Specific2 addr low reg */ -#define XEMACPS_LADDR2H_OFFSET 0x00000094 /**< Specific2 addr high reg */ -#define XEMACPS_LADDR3L_OFFSET 0x00000098 /**< Specific3 addr low reg */ -#define XEMACPS_LADDR3H_OFFSET 0x0000009C /**< Specific3 addr high reg */ -#define XEMACPS_LADDR4L_OFFSET 0x000000A0 /**< Specific4 addr low reg */ -#define XEMACPS_LADDR4H_OFFSET 0x000000A4 /**< Specific4 addr high reg */ - -#define XEMACPS_MATCH1_OFFSET 0x000000A8 /**< Type ID1 Match reg */ -#define XEMACPS_MATCH2_OFFSET 0x000000AC /**< Type ID2 Match reg */ -#define XEMACPS_MATCH3_OFFSET 0x000000B0 /**< Type ID3 Match reg */ -#define XEMACPS_MATCH4_OFFSET 0x000000B4 /**< Type ID4 Match reg */ - -#define XEMACPS_STRETCH_OFFSET 0x000000BC /**< IPG Stretch reg */ - -#define XEMACPS_OCTTXL_OFFSET 0x00000100 /**< Octects transmitted Low - reg */ -#define XEMACPS_OCTTXH_OFFSET 0x00000104 /**< Octects transmitted High - reg */ - -#define XEMACPS_TXCNT_OFFSET 0x00000108 /**< Error-free Frmaes - transmitted counter */ -#define XEMACPS_TXBCCNT_OFFSET 0x0000010C /**< Error-free Broadcast - Frames counter*/ -#define XEMACPS_TXMCCNT_OFFSET 0x00000110 /**< Error-free Multicast - Frame counter */ -#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114 /**< Pause Frames Transmitted - Counter */ -#define XEMACPS_TX64CNT_OFFSET 0x00000118 /**< Error-free 64 byte Frames - Transmitted counter */ -#define XEMACPS_TX65CNT_OFFSET 0x0000011C /**< Error-free 65-127 byte - Frames Transmitted - counter */ -#define XEMACPS_TX128CNT_OFFSET 0x00000120 /**< Error-free 128-255 byte - Frames Transmitted - counter*/ -#define XEMACPS_TX256CNT_OFFSET 0x00000124 /**< Error-free 256-511 byte - Frames transmitted - counter */ -#define XEMACPS_TX512CNT_OFFSET 0x00000128 /**< Error-free 512-1023 byte - Frames transmitted - counter */ -#define XEMACPS_TX1024CNT_OFFSET 0x0000012C /**< Error-free 1024-1518 byte - Frames transmitted - counter */ -#define XEMACPS_TX1519CNT_OFFSET 0x00000130 /**< Error-free larger than - 1519 byte Frames - transmitted counter */ -#define XEMACPS_TXURUNCNT_OFFSET 0x00000134 /**< TX under run error - counter */ - -#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138 /**< Single Collision Frame - Counter */ -#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013C /**< Multiple Collision Frame - Counter */ -#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140 /**< Excessive Collision Frame - Counter */ -#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144 /**< Late Collision Frame - Counter */ -#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148 /**< Deferred Transmission - Frame Counter */ -#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014C /**< Transmit Carrier Sense - Error Counter */ - -#define XEMACPS_OCTRXL_OFFSET 0x00000150 /**< Octects Received register - Low */ -#define XEMACPS_OCTRXH_OFFSET 0x00000154 /**< Octects Received register - High */ - -#define XEMACPS_RXCNT_OFFSET 0x00000158 /**< Error-free Frames - Received Counter */ -#define XEMACPS_RXBROADCNT_OFFSET 0x0000015C /**< Error-free Broadcast - Frames Received Counter */ -#define XEMACPS_RXMULTICNT_OFFSET 0x00000160 /**< Error-free Multicast - Frames Received Counter */ -#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164 /**< Pause Frames - Received Counter */ -#define XEMACPS_RX64CNT_OFFSET 0x00000168 /**< Error-free 64 byte Frames - Received Counter */ -#define XEMACPS_RX65CNT_OFFSET 0x0000016C /**< Error-free 65-127 byte - Frames Received Counter */ -#define XEMACPS_RX128CNT_OFFSET 0x00000170 /**< Error-free 128-255 byte - Frames Received Counter */ -#define XEMACPS_RX256CNT_OFFSET 0x00000174 /**< Error-free 256-512 byte - Frames Received Counter */ -#define XEMACPS_RX512CNT_OFFSET 0x00000178 /**< Error-free 512-1023 byte - Frames Received Counter */ -#define XEMACPS_RX1024CNT_OFFSET 0x0000017C /**< Error-free 1024-1518 byte - Frames Received Counter */ -#define XEMACPS_RX1519CNT_OFFSET 0x00000180 /**< Error-free 1519-max byte - Frames Received Counter */ -#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184 /**< Undersize Frames Received - Counter */ -#define XEMACPS_RXOVRCNT_OFFSET 0x00000188 /**< Oversize Frames Received - Counter */ -#define XEMACPS_RXJABCNT_OFFSET 0x0000018C /**< Jabbers Received - Counter */ -#define XEMACPS_RXFCSCNT_OFFSET 0x00000190 /**< Frame Check Sequence - Error Counter */ -#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194 /**< Length Field Error - Counter */ -#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198 /**< Symbol Error Counter */ -#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019C /**< Alignment Error Counter */ -#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0 /**< Receive Resource Error - Counter */ -#define XEMACPS_RXORCNT_OFFSET 0x000001A4 /**< Receive Overrun Counter */ -#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8 /**< IP header Checksum Error - Counter */ -#define XEMACPS_RXTCPCCNT_OFFSET 0x000001AC /**< TCP Checksum Error - Counter */ -#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0 /**< UDP Checksum Error - Counter */ -#define XEMACPS_LAST_OFFSET 0x000001B4 /**< Last statistic counter - offset, for clearing */ - -#define XEMACPS_1588_SEC_OFFSET 0x000001D0 /**< 1588 second counter */ -#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4 /**< 1588 nanosecond counter */ -#define XEMACPS_1588_ADJ_OFFSET 0x000001D8 /**< 1588 nanosecond - adjustment counter */ -#define XEMACPS_1588_INC_OFFSET 0x000001DC /**< 1588 nanosecond - increment counter */ -#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0 /**< 1588 PTP transmit second - counter */ -#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4 /**< 1588 PTP transmit - nanosecond counter */ -#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8 /**< 1588 PTP receive second - counter */ -#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001EC /**< 1588 PTP receive - nanosecond counter */ -#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0 /**< 1588 PTP peer transmit - second counter */ -#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4 /**< 1588 PTP peer transmit - nanosecond counter */ -#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8 /**< 1588 PTP peer receive - second counter */ -#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FC /**< 1588 PTP peer receive - nanosecond counter */ - -/* Define some bit positions for registers. */ - -/** @name network control register bit definitions - * @{ - */ -#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000 /**< Flush a packet from - Rx SRAM */ -#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800 /**< Transmit zero quantum - pause frame */ -#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800 /**< Transmit pause frame */ -#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400 /**< Halt transmission - after current frame */ -#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200 /**< Start tx (tx_go) */ - -#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080 /**< Enable writing to - stat counters */ -#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040 /**< Increment statistic - registers */ -#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020 /**< Clear statistic - registers */ -#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010 /**< Enable MDIO port */ -#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008 /**< Enable transmit */ -#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004 /**< Enable receive */ -#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002 /**< local loopback */ -/*@}*/ - -/** @name network configuration register bit definitions - * @{ - */ -#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000 /**< disable rejection of - non-standard preamble */ -#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000 /**< enable transmit IPG */ -#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000 /**< disable rejection of - FCS error */ -#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000 /**< RX half duplex */ -#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000 /**< enable RX checksum - offload */ -#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000 /**< Do not copy pause - Frames to memory */ -#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18 /**< shift bits for MDC */ -#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000 /**< MDC Mask PCLK divisor */ -#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000 /**< Discard FCS from - received frames */ -#define XEMACPS_NWCFG_LENGTHERRDSCRD_MASK 0x00010000 -/**< RX length error discard */ -#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000 /**< RX buffer offset */ -#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000 /**< Enable pause RX */ -#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000 /**< Retry test */ -#define XEMACPS_NWCFG_EXTADDRMATCHEN_MASK 0x00000200 -/**< External address match enable */ -#define XEMACPS_NWCFG_1000_MASK 0x00000400 /**< 1000 Mbps */ -#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100 /**< Enable 1536 byte - frames reception */ -#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080 /**< Receive unicast hash - frames */ -#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040 /**< Receive multicast hash - frames */ -#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020 /**< Do not receive - broadcast frames */ -#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010 /**< Copy all frames */ -#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008 /**< Jumbo frames */ -#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004 /**< Receive only VLAN - frames */ -#define XEMACPS_NWCFG_FDEN_MASK 0x00000002 /**< full duplex */ -#define XEMACPS_NWCFG_100_MASK 0x00000001 /**< 100 Mbps */ -#define XEMACPS_NWCFG_RESET_MASK 0x00080000 /**< reset value */ -/*@}*/ - -/** @name network status register bit definitaions - * @{ - */ -#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004 /**< PHY management idle */ -#define XEMACPS_NWSR_MDIO_MASK 0x00000002 /**< Status of mdio_in */ -/*@}*/ - - -/** @name MAC address register word 1 mask - * @{ - */ -#define XEMACPS_LADDR_MACH_MASK 0x0000FFFF /**< Address bits[47:32] - bit[31:0] are in BOTTOM */ -/*@}*/ - - -/** @name DMA control register bit definitions - * @{ - */ -#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000 /**< Mask bit for RX buffer - size */ -#define XEMACPS_DMACR_RXBUF_SHIFT 16 /**< Shift bit for RX buffer - size */ -#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800 /**< enable/disable TX - checksum offload */ -#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400 /**< TX buffer memory size */ -#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300 /**< RX buffer memory size */ -#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080 /**< endian configuration */ -#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001F /**< buffer burst length */ -#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001 /**< single AHB bursts */ -#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004 /**< 4 bytes AHB bursts */ -#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008 /**< 8 bytes AHB bursts */ -#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010 /**< 16 bytes AHB bursts */ -/*@}*/ - -/** @name transmit status register bit definitions - * @{ - */ -#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100 /**< Transmit hresp not OK */ -#define XEMACPS_TXSR_URUN_MASK 0x00000040 /**< Transmit underrun */ -#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020 /**< Transmit completed OK */ -#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010 /**< Transmit buffs exhausted - mid frame */ -#define XEMACPS_TXSR_TXGO_MASK 0x00000008 /**< Status of go flag */ -#define XEMACPS_TXSR_RXOVR_MASK 0x00000004 /**< Retry limit exceeded */ -#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002 /**< Collision tx frame */ -#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001 /**< TX buffer used bit set */ - -#define XEMACPS_TXSR_ERROR_MASK (XEMACPS_TXSR_HRESPNOK_MASK | \ - XEMACPS_TXSR_URUN_MASK | \ - XEMACPS_TXSR_BUFEXH_MASK | \ - XEMACPS_TXSR_RXOVR_MASK | \ - XEMACPS_TXSR_FRAMERX_MASK | \ - XEMACPS_TXSR_USEDREAD_MASK) -/*@}*/ - -/** - * @name receive status register bit definitions - * @{ - */ -#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008 /**< Receive hresp not OK */ -#define XEMACPS_RXSR_RXOVR_MASK 0x00000004 /**< Receive overrun */ -#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002 /**< Frame received OK */ -#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001 /**< RX buffer used bit set */ - -#define XEMACPS_RXSR_ERROR_MASK (XEMACPS_RXSR_HRESPNOK_MASK | \ - XEMACPS_RXSR_RXOVR_MASK | \ - XEMACPS_RXSR_BUFFNA_MASK) -/*@}*/ - -/** - * @name interrupts bit definitions - * Bits definitions are same in XEMACPS_ISR_OFFSET, - * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET - * @{ - */ -#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000 /**< PTP Psync transmitted */ -#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000 /**< PTP Pdelay_req - transmitted */ -#define XEMACPS_IXR_PTPSTX_MASK 0x00800000 /**< PTP Sync transmitted */ -#define XEMACPS_IXR_PTPDRTX_MASK 0x00400000 /**< PTP Delay_req transmitted - */ -#define XEMACPS_IXR_PTPPSRX_MASK 0x00200000 /**< PTP Psync received */ -#define XEMACPS_IXR_PTPPDRRX_MASK 0x00100000 /**< PTP Pdelay_req received */ -#define XEMACPS_IXR_PTPSRX_MASK 0x00080000 /**< PTP Sync received */ -#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000 /**< PTP Delay_req received */ -#define XEMACPS_IXR_PAUSETX_MASK 0x00004000 /**< Pause frame transmitted */ -#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000 /**< Pause time has reached - zero */ -#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000 /**< Pause frame received */ -#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800 /**< hresp not ok */ -#define XEMACPS_IXR_RXOVR_MASK 0x00000400 /**< Receive overrun occurred */ -#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080 /**< Frame transmitted ok */ -#define XEMACPS_IXR_TXEXH_MASK 0x00000040 /**< Transmit err occurred or - no buffers*/ -#define XEMACPS_IXR_RETRY_MASK 0x00000020 /**< Retry limit exceeded */ -#define XEMACPS_IXR_URUN_MASK 0x00000010 /**< Transmit underrun */ -#define XEMACPS_IXR_TXUSED_MASK 0x00000008 /**< Tx buffer used bit read */ -#define XEMACPS_IXR_RXUSED_MASK 0x00000004 /**< Rx buffer used bit read */ -#define XEMACPS_IXR_FRAMERX_MASK 0x00000002 /**< Frame received ok */ -#define XEMACPS_IXR_MGMNT_MASK 0x00000001 /**< PHY management complete */ -#define XEMACPS_IXR_ALL_MASK 0x00007FFF /**< Everything! */ - -#define XEMACPS_IXR_TX_ERR_MASK (XEMACPS_IXR_TXEXH_MASK | \ - XEMACPS_IXR_RETRY_MASK | \ - XEMACPS_IXR_URUN_MASK | \ - XEMACPS_IXR_TXUSED_MASK) - - -#define XEMACPS_IXR_RX_ERR_MASK (XEMACPS_IXR_HRESPNOK_MASK | \ - XEMACPS_IXR_RXUSED_MASK | \ - XEMACPS_IXR_RXOVR_MASK) - -/*@}*/ - -/** @name PHY Maintenance bit definitions - * @{ - */ -#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000 /**< operation mask bits */ -#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000 /**< read operation */ -#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000 /**< write operation */ -#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000 /**< Address bits */ -#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000 /**< register bits */ -#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFF /**< data bits */ -#define XEMACPS_PHYMNTNC_PHYAD_SHIFT_MASK 23 /**< Shift bits for PHYAD */ -#define XEMACPS_PHYMNTNC_PHREG_SHIFT_MASK 18 /**< Shift bits for PHREG */ -/*@}*/ - -/* Transmit buffer descriptor status words offset - * @{ - */ -#define XEMACPS_BD_ADDR_OFFSET 0x00000000 /**< word 0/addr of BDs */ -#define XEMACPS_BD_STAT_OFFSET 0x00000004 /**< word 1/status of BDs */ -/* - * @} - */ - -/* Transmit buffer descriptor status words bit positions. - * Transmit buffer descriptor consists of two 32-bit registers, - * the first - word0 contains a 32-bit address pointing to the location of - * the transmit data. - * The following register - word1, consists of various information to control - * the XEmacPs transmit process. After transmit, this is updated with status - * information, whether the frame was transmitted OK or why it had failed. - * @{ - */ -#define XEMACPS_TXBUF_USED_MASK 0x80000000 /**< Used bit. */ -#define XEMACPS_TXBUF_WRAP_MASK 0x40000000 /**< Wrap bit, last descriptor */ -#define XEMACPS_TXBUF_RETRY_MASK 0x20000000 /**< Retry limit exceeded */ -#define XEMACPS_TXBUF_URUN_MASK 0x10000000 /**< Transmit underrun occurred */ -#define XEMACPS_TXBUF_EXH_MASK 0x08000000 /**< Buffers exhausted */ -#define XEMACPS_TXBUF_TCP_MASK 0x04000000 /**< Late collision. */ -#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000 /**< No CRC */ -#define XEMACPS_TXBUF_LAST_MASK 0x00008000 /**< Last buffer */ -#define XEMACPS_TXBUF_LEN_MASK 0x00003FFF /**< Mask for length field */ -/* - * @} - */ - -/* Receive buffer descriptor status words bit positions. - * Receive buffer descriptor consists of two 32-bit registers, - * the first - word0 contains a 32-bit word aligned address pointing to the - * address of the buffer. The lower two bits make up the wrap bit indicating - * the last descriptor and the ownership bit to indicate it has been used by - * the XEmacPs. - * The following register - word1, contains status information regarding why - * the frame was received (the filter match condition) as well as other - * useful info. - * @{ - */ -#define XEMACPS_RXBUF_BCAST_MASK 0x80000000 /**< Broadcast frame */ -#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000 /**< Multicast hashed frame */ -#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000 /**< Unicast hashed frame */ -#define XEMACPS_RXBUF_EXH_MASK 0x08000000 /**< buffer exhausted */ -#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000 /**< Specific address - matched */ -#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000 /**< Type ID matched */ -#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000 /**< ID matched mask */ -#define XEMACPS_RXBUF_VLAN_MASK 0x00200000 /**< VLAN tagged */ -#define XEMACPS_RXBUF_PRI_MASK 0x00100000 /**< Priority tagged */ -#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000 /**< Vlan priority */ -#define XEMACPS_RXBUF_CFI_MASK 0x00010000 /**< CFI frame */ -#define XEMACPS_RXBUF_EOF_MASK 0x00008000 /**< End of frame. */ -#define XEMACPS_RXBUF_SOF_MASK 0x00004000 /**< Start of frame. */ -#define XEMACPS_RXBUF_LEN_MASK 0x00003FFF /**< Mask for length field */ - -#define XEMACPS_RXBUF_WRAP_MASK 0x00000002 /**< Wrap bit, last BD */ -#define XEMACPS_RXBUF_NEW_MASK 0x00000001 /**< Used bit.. */ -#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFC /**< Mask for address */ -/* - * @} - */ - -/* - * Define appropriate I/O access method to mempry mapped I/O or other - * intarfce if necessary. - */ - -#define XEmacPs_In32 Xil_In32 -#define XEmacPs_Out32 Xil_Out32 - - -/****************************************************************************/ -/** -* -* Read the given register. -* -* @param BaseAddress is the base address of the device -* @param RegOffset is the register offset to be read -* -* @return The 32-bit value of the register -* -* @note -* C-style signature: -* u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset) -* -*****************************************************************************/ -#define XEmacPs_ReadReg(BaseAddress, RegOffset) \ - XEmacPs_In32((BaseAddress) + (RegOffset)) - - -/****************************************************************************/ -/** -* -* Write the given register. -* -* @param BaseAddress is the base address of the device -* @param RegOffset is the register offset to be written -* @param Data is the 32-bit value to write to the register -* -* @return None. -* -* @note -* C-style signature: -* void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset, -* u32 Data) -* -*****************************************************************************/ -#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \ - XEmacPs_Out32((BaseAddress) + (RegOffset), (Data)) - -/************************** Function Prototypes *****************************/ -/* - * Perform reset operation to the emacps interface - */ -void XEmacPs_ResetHw(u32 BaseAddr); - -#ifdef __cplusplus - } -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps_intr.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps_intr.c deleted file mode 100644 index a3b92084834525a456629c848639a5f15f1861a9..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps_intr.c +++ /dev/null @@ -1,229 +0,0 @@ -/* $Id: xemacps_intr.c,v 1.1.2.1 2011/01/20 03:39:02 sadanan Exp $ */ -/****************************************************************************** -* -* (c) Copyright 2010 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xemacps_intr.c -* -* Functions in this file implement general purpose interrupt processing related -* functionality. See xemacps.h for a detailed description of the driver. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.00a wsy 01/10/10 First release -* 1.03a asa 01/24/13 Fix for CR #692702 which updates error handling for -* Rx errors. Under heavy Rx traffic, there will be a large -* number of errors related to receive buffer not available. -* Because of a HW bug (SI #692601), under such heavy errors, -* the Rx data path can become unresponsive. To reduce the -* probabilities for hitting this HW bug, the SW writes to -* bit 18 to flush a packet from Rx DPRAM immediately. The -* changes for it are done in the function -* XEmacPs_IntrHandler. -* </pre> -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xemacps.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - - -/************************** Variable Definitions *****************************/ - - -/*****************************************************************************/ -/** - * Install an asynchronious handler function for the given HandlerType: - * - * @param InstancePtr is a pointer to the instance to be worked on. - * @param HandlerType indicates what interrupt handler type is. - * XEMACPS_HANDLER_DMASEND, XEMACPS_HANDLER_DMARECV and - * XEMACPS_HANDLER_ERROR. - * @param FuncPtr is the pointer to the callback function - * @param CallBackRef is the upper layer callback reference passed back when - * when the callback function is invoked. - * - * @return - * - * None. - * - * @note - * There is no assert on the CallBackRef since the driver doesn't know what - * it is. - * - *****************************************************************************/ -int XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType, - void *FuncPtr, void *CallBackRef) -{ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(FuncPtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - switch (HandlerType) { - case XEMACPS_HANDLER_DMASEND: - InstancePtr->SendHandler = (XEmacPs_Handler) FuncPtr; - InstancePtr->SendRef = CallBackRef; - break; - case XEMACPS_HANDLER_DMARECV: - InstancePtr->RecvHandler = (XEmacPs_Handler) FuncPtr; - InstancePtr->RecvRef = CallBackRef; - break; - case XEMACPS_HANDLER_ERROR: - InstancePtr->ErrorHandler = (XEmacPs_ErrHandler) FuncPtr; - InstancePtr->ErrorRef = CallBackRef; - break; - default: - return (XST_INVALID_PARAM); - } - return (XST_SUCCESS); -} - -/*****************************************************************************/ -/** -* Master interrupt handler for EMAC driver. This routine will query the -* status of the device, bump statistics, and invoke user callbacks. -* -* This routine must be connected to an interrupt controller using OS/BSP -* specific methods. -* -* @param XEmacPsPtr is a pointer to the XEMACPS instance that has caused the -* interrupt. -* -******************************************************************************/ -void XEmacPs_IntrHandler(void *XEmacPsPtr) -{ - u32 RegISR; - u32 RegSR; - u32 RegCtrl; - XEmacPs *InstancePtr = (XEmacPs *) XEmacPsPtr; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* This ISR will try to handle as many interrupts as it can in a single - * call. However, in most of the places where the user's error handler - * is called, this ISR exits because it is expected that the user will - * reset the device in nearly all instances. - */ - RegISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_ISR_OFFSET); - - /* Clear the interrupt status register */ - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET, - RegISR); - - /* Receive complete interrupt */ - if (RegISR & (XEMACPS_IXR_FRAMERX_MASK)) { - /* Clear RX status register RX complete indication but preserve - * error bits if there is any */ - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_RXSR_OFFSET, - XEMACPS_RXSR_FRAMERX_MASK | - XEMACPS_RXSR_BUFFNA_MASK); - InstancePtr->RecvHandler(InstancePtr->RecvRef); - } - - /* Transmit complete interrupt */ - if (RegISR & (XEMACPS_IXR_TXCOMPL_MASK)) { - /* Clear TX status register TX complete indication but preserve - * error bits if there is any */ - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_TXSR_OFFSET, - XEMACPS_TXSR_TXCOMPL_MASK | - XEMACPS_TXSR_USEDREAD_MASK); - InstancePtr->SendHandler(InstancePtr->SendRef); - } - - /* Receive error conditions interrupt */ - if (RegISR & (XEMACPS_IXR_RX_ERR_MASK)) { - /* Clear RX status register */ - RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_RXSR_OFFSET); - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_RXSR_OFFSET, RegSR); - - /* Fix for CR # 692702. Write to bit 18 of net_ctrl - * register to flush a packet out of Rx SRAM upon - * an error for receive buffer not available. */ - if (RegISR & XEMACPS_IXR_RXUSED_MASK) { - RegCtrl = - XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCTRL_OFFSET); - RegCtrl |= XEMACPS_NWCTRL_FLUSH_DPRAM_MASK; - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_NWCTRL_OFFSET, RegCtrl); - } - InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_RECV, - RegSR); - } - - /* When XEMACPS_IXR_TXCOMPL_MASK is flaged, XEMACPS_IXR_TXUSED_MASK - * will be asserted the same time. - * Have to distinguish this bit to handle the real error condition. - */ - /* Transmit error conditions interrupt */ - if (RegISR & (XEMACPS_IXR_TX_ERR_MASK) && - !(RegISR & (XEMACPS_IXR_TXCOMPL_MASK))) { - /* Clear TX status register */ - RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, - XEMACPS_TXSR_OFFSET); - XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, - XEMACPS_TXSR_OFFSET, RegSR); - InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND, - RegSR); - } - -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps_sinit.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps_sinit.c deleted file mode 100644 index 6472342ebb887930609991181b49203f2e757f23..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/emacps_v1_05_a/src/xemacps_sinit.c +++ /dev/null @@ -1,102 +0,0 @@ -/* $Id: xemacps_sinit.c,v 1.1.2.1 2011/01/20 03:39:02 sadanan Exp $ */ -/****************************************************************************** -* -* (c) Copyright 2010 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xemacps_sinit.c -* -* This file contains lookup method by device ID when success, it returns -* pointer to config table to be used to initialize the device. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.00a wsy 01/10/10 New -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xparameters.h" -#include "xemacps.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - -/*****************************************************************************/ -/** -* Lookup the device configuration based on the unique device ID. The table -* contains the configuration info for each device in the system. -* -* @param DeviceId is the unique device ID of the device being looked up. -* -* @return -* A pointer to the configuration table entry corresponding to the given -* device ID, or NULL if no match is found. -* -******************************************************************************/ -XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId) -{ - extern XEmacPs_Config XEmacPs_ConfigTable[]; - XEmacPs_Config *CfgPtr = NULL; - int i; - - for (i = 0; i < XPAR_XEMACPS_NUM_INSTANCES; i++) { - if (XEmacPs_ConfigTable[i].DeviceId == DeviceId) { - CfgPtr = &XEmacPs_ConfigTable[i]; - break; - } - } - - return (CfgPtr); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/Makefile b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/Makefile deleted file mode 100644 index 5f8a635728d8a0f668697e23acb35e6c7c63975b..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -COMPILER= -ARCHIVER= -CP=cp -COMPILER_FLAGS= -EXTRA_COMPILER_FLAGS= -LIB=libxil.a - -RELEASEDIR=../../../lib -INCLUDEDIR=../../../include -INCLUDES=-I./. -I${INCLUDEDIR} - -INCLUDEFILES=xgpio_l.h xgpio.h - -LIBSOURCES=*.c -OUTS = *.o - - -libs: - echo "Compiling gpio" - $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) - $(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS) - make clean - -include: - ${CP} ${INCLUDEFILES} ${INCLUDEDIR} - -clean: - rm -rf ${OUTS} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/xgpio.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/xgpio.c deleted file mode 100644 index a2039840158f9f2fe687fb0841dd3e3990bb6b15..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/xgpio.c +++ /dev/null @@ -1,264 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2002-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ - -/** -* @file xgpio.c -* -* The implementation of the XGpio driver's basic functionality. See xgpio.h -* for more information about the driver. -* -* @note -* -* None -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a rmm 02/04/02 First release -* 2.00a jhl 12/16/02 Update for dual channel and interrupt support -* 2.01a jvb 12/13/05 Changed Initialize() into CfgInitialize(), and made -* CfgInitialize() take a pointer to a config structure -* instead of a device id. Moved Initialize() into -* xgpio_sinit.c, and had Initialize() call CfgInitialize() -* after it retrieved the config structure using the device -* id. Removed include of xparameters.h along with any -* dependencies on xparameters.h and the _g.c config table. -* 2.11a mta 03/21/07 Updated to new coding style, added GetDataDirection -* 2.12a sv 11/21/07 Updated driver to support access through DCR bus -* 3.00a sv 11/21/09 Updated to use HAL Processor APIs. Renamed the -* macros to remove _m from the name. -* </pre> -* -*****************************************************************************/ - -/***************************** Include Files ********************************/ - -#include "xgpio.h" -#include "xstatus.h" - -/************************** Constant Definitions ****************************/ - -/**************************** Type Definitions ******************************/ - -/***************** Macros (Inline Functions) Definitions ********************/ - -/************************** Variable Definitions ****************************/ - - -/************************** Function Prototypes *****************************/ - - -/****************************************************************************/ -/** -* Initialize the XGpio instance provided by the caller based on the -* given configuration data. -* -* Nothing is done except to initialize the InstancePtr. -* -* @param InstancePtr is a pointer to an XGpio instance. The memory the -* pointer references must be pre-allocated by the caller. Further -* calls to manipulate the driver through the XGpio API must be -* made with this pointer. -* @param Config is a reference to a structure containing information -* about a specific GPIO device. This function initializes an -* InstancePtr object for a specific device specified by the -* contents of Config. This function can initialize multiple -* instance objects with the use of multiple calls giving different -* Config information on each call. -* @param EffectiveAddr is the device base address in the virtual memory -* address space. The caller is responsible for keeping the address -* mapping from EffectiveAddr to the device physical base address -* unchanged once this function is invoked. Unexpected errors may -* occur if the address mapping changes after this function is -* called. If address translation is not used, use -* Config->BaseAddress for this parameters, passing the physical -* address instead. -* -* @return -* - XST_SUCCESS Initialization was successfull. -* -* @note None. -* -*****************************************************************************/ -int XGpio_CfgInitialize(XGpio * InstancePtr, XGpio_Config * Config, - u32 EffectiveAddr) -{ - /* - * Assert arguments - */ - Xil_AssertNonvoid(InstancePtr != NULL); - - /* - * Set some default values. - */ -#if (XPAR_XGPIO_USE_DCR_BRIDGE != 0) - InstancePtr->BaseAddress = ((EffectiveAddr >> 2)) & 0xFFF; -#else - InstancePtr->BaseAddress = EffectiveAddr; -#endif - - InstancePtr->InterruptPresent = Config->InterruptPresent; - InstancePtr->IsDual = Config->IsDual; - - /* - * Indicate the instance is now ready to use, initialized without error - */ - InstancePtr->IsReady = XIL_COMPONENT_IS_READY; - return (XST_SUCCESS); -} - - -/****************************************************************************/ -/** -* Set the input/output direction of all discrete signals for the specified -* GPIO channel. -* -* @param InstancePtr is a pointer to an XGpio instance to be worked on. -* @param Channel contains the channel of the GPIO (1 or 2) to operate on. -* @param DirectionMask is a bitmask specifying which discretes are input -* and which are output. Bits set to 0 are output and bits set to 1 -* are input. -* -* @return None. -* -* @note The hardware must be built for dual channels if this function -* is used with any channel other than 1. If it is not, this -* function will assert. -* -*****************************************************************************/ -void XGpio_SetDataDirection(XGpio * InstancePtr, unsigned Channel, - u32 DirectionMask) -{ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid((Channel == 1) || - ((Channel == 2) && (InstancePtr->IsDual == TRUE))); - - XGpio_WriteReg(InstancePtr->BaseAddress, - ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_TRI_OFFSET, - DirectionMask); -} - -/****************************************************************************/ -/** -* Get the input/output direction of all discrete signals for the specified -* GPIO channel. -* -* @param InstancePtr is a pointer to an XGpio instance to be worked on. -* @param Channel contains the channel of the GPIO (1 or 2) to operate on. -* -* @return Bitmask specifying which discretes are input and -* which are output. Bits set to 0 are output and bits set to 1 are -* input. -* -* @note -* -* The hardware must be built for dual channels if this function is used -* with any channel other than 1. If it is not, this function will assert. -* -*****************************************************************************/ -u32 XGpio_GetDataDirection(XGpio *InstancePtr, unsigned Channel) -{ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid((Channel == 1) || - ((Channel == 2) && - (InstancePtr->IsDual == TRUE))); - - return XGpio_ReadReg(InstancePtr->BaseAddress, - ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_TRI_OFFSET); -} - -/****************************************************************************/ -/** -* Read state of discretes for the specified GPIO channnel. -* -* @param InstancePtr is a pointer to an XGpio instance to be worked on. -* @param Channel contains the channel of the GPIO (1 or 2) to operate on. -* -* @return Current copy of the discretes register. -* -* @note The hardware must be built for dual channels if this function -* is used with any channel other than 1. If it is not, this -* function will assert. -* -*****************************************************************************/ -u32 XGpio_DiscreteRead(XGpio * InstancePtr, unsigned Channel) -{ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid((Channel == 1) || - ((Channel == 2) && (InstancePtr->IsDual == TRUE))); - - return XGpio_ReadReg(InstancePtr->BaseAddress, - ((Channel - 1) * XGPIO_CHAN_OFFSET) + - XGPIO_DATA_OFFSET); -} - -/****************************************************************************/ -/** -* Write to discretes register for the specified GPIO channel. -* -* @param InstancePtr is a pointer to an XGpio instance to be worked on. -* @param Channel contains the channel of the GPIO (1 or 2) to operate on. -* @param Data is the value to be written to the discretes register. -* -* @return None. -* -* @note The hardware must be built for dual channels if this function -* is used with any channel other than 1. If it is not, this -* function will assert. See also XGpio_DiscreteSet() and -* XGpio_DiscreteClear(). -* -*****************************************************************************/ -void XGpio_DiscreteWrite(XGpio * InstancePtr, unsigned Channel, u32 Data) -{ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid((Channel == 1) || - ((Channel == 2) && (InstancePtr->IsDual == TRUE))); - - XGpio_WriteReg(InstancePtr->BaseAddress, - ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET, - Data); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/xgpio.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/xgpio.h deleted file mode 100644 index bd77b92044c866518ed2ba3a0cc2b578445da1ac..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/xgpio.h +++ /dev/null @@ -1,203 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2002-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* @file xgpio.h -* -* This file contains the software API definition of the Xilinx General Purpose -* I/O (XGpio) device driver. -* -* The Xilinx GPIO controller is a soft IP core designed for Xilinx FPGAs and -* contains the following general features: -* - Support for up to 32 I/O discretes for each channel (64 bits total). -* - Each of the discretes can be configured for input or output. -* - Configurable support for dual channels and interrupt generation. -* -* The driver provides interrupt management functions. Implementation of -* interrupt handlers is left to the user. Refer to the provided interrupt -* example in the examples directory for details. -* -* This driver is intended to be RTOS and processor independent. Any needs for -* dynamic memory management, threads or thread mutual exclusion, virtual -* memory, or cache control must be satisfied by the layer above this driver. -* -* <b>Initialization & Configuration</b> -* -* The XGpio_Config structure is used by the driver to configure itself. This -* configuration structure is typically created by the tool-chain based on HW -* build properties. -* -* To support multiple runtime loading and initialization strategies employed -* by various operating systems, the driver instance can be initialized in one -* of the following ways: -* -* - XGpio_Initialize(InstancePtr, DeviceId) - The driver looks up its own -* configuration structure created by the tool-chain based on an ID provided -* by the tool-chain. -* -* - XGpio_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a -* configuration structure provided by the caller. If running in a system -* with address translation, the provided virtual memory base address -* replaces the physical address present in the configuration structure. -* -* @note -* -* This API utilizes 32 bit I/O to the GPIO registers. With less than 32 bits, -* the unused bits from registers are read as zero and written as don't cares. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a rmm 03/13/02 First release -* 2.00a jhl 11/26/03 Added support for dual channels and interrupts -* 2.01a jvb 12/14/05 I separated dependency on the static config table and -* xparameters.h from the driver initialization by moving -* _Initialize and _LookupConfig to _sinit.c. I also added -* the new _CfgInitialize routine. -* 2.11a mta 03/21/07 Updated to new coding style, added GetDataDirection -* 2.12a sv 11/21/07 Updated driver to support access through DCR bus -* 2.12a sv 06/05/08 Updated driver to fix the XGpio_InterruptDisable function -* to properly update the Interrupt Enable register -* 2.13a sdm 08/22/08 Removed support for static interrupt handlers from the MDD -* file -* 3.00a sv 11/21/09 Updated to use HAL Processor APIs. -* Renamed the macros XGpio_mWriteReg to XGpio_WriteReg and -* XGpio_mReadReg to XGpio_ReadReg. Removed the macros -* XGpio_mSetDataDirection, XGpio_mGetDataReg and -* XGpio_mSetDataReg. Users should use XGpio_WriteReg and -* XGpio_ReadReg to achieve the same functionality. -* 3.01a bss 04/18/13 Updated driver tcl to generate Canonical params in -* xparameters.h. CR#698589 -* </pre> -*****************************************************************************/ - -#ifndef XGPIO_H /* prevent circular inclusions */ -#define XGPIO_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files ********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xstatus.h" -#include "xgpio_l.h" - -/************************** Constant Definitions ****************************/ - -/**************************** Type Definitions ******************************/ - -/** - * This typedef contains configuration information for the device. - */ -typedef struct { - u16 DeviceId; /* Unique ID of device */ - u32 BaseAddress; /* Device base address */ - int InterruptPresent; /* Are interrupts supported in h/w */ - int IsDual; /* Are 2 channels supported in h/w */ -} XGpio_Config; - -/** - * The XGpio driver instance data. The user is required to allocate a - * variable of this type for every GPIO device in the system. A pointer - * to a variable of this type is then passed to the driver API functions. - */ -typedef struct { - u32 BaseAddress; /* Device base address */ - u32 IsReady; /* Device is initialized and ready */ - int InterruptPresent; /* Are interrupts supported in h/w */ - int IsDual; /* Are 2 channels supported in h/w */ -} XGpio; - -/***************** Macros (Inline Functions) Definitions ********************/ - - -/************************** Function Prototypes *****************************/ - -/* - * Initialization functions in xgpio_sinit.c - */ -int XGpio_Initialize(XGpio *InstancePtr, u16 DeviceId); -XGpio_Config *XGpio_LookupConfig(u16 DeviceId); - -/* - * API Basic functions implemented in xgpio.c - */ -int XGpio_CfgInitialize(XGpio *InstancePtr, XGpio_Config * Config, - u32 EffectiveAddr); -void XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel, - u32 DirectionMask); -u32 XGpio_GetDataDirection(XGpio *InstancePtr, unsigned Channel); -u32 XGpio_DiscreteRead(XGpio *InstancePtr, unsigned Channel); -void XGpio_DiscreteWrite(XGpio *InstancePtr, unsigned Channel, u32 Mask); - - -/* - * API Functions implemented in xgpio_extra.c - */ -void XGpio_DiscreteSet(XGpio *InstancePtr, unsigned Channel, u32 Mask); -void XGpio_DiscreteClear(XGpio *InstancePtr, unsigned Channel, u32 Mask); - -/* - * API Functions implemented in xgpio_selftest.c - */ -int XGpio_SelfTest(XGpio *InstancePtr); - -/* - * API Functions implemented in xgpio_intr.c - */ -void XGpio_InterruptGlobalEnable(XGpio *InstancePtr); -void XGpio_InterruptGlobalDisable(XGpio *InstancePtr); -void XGpio_InterruptEnable(XGpio *InstancePtr, u32 Mask); -void XGpio_InterruptDisable(XGpio *InstancePtr, u32 Mask); -void XGpio_InterruptClear(XGpio *InstancePtr, u32 Mask); -u32 XGpio_InterruptGetEnabled(XGpio *InstancePtr); -u32 XGpio_InterruptGetStatus(XGpio *InstancePtr); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/xgpio_extra.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/xgpio_extra.c deleted file mode 100644 index 3a4df60845e6540c9f631ec4e0e10fa28b2b28ec..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/xgpio_extra.c +++ /dev/null @@ -1,174 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2002-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ - -/** -* @file xgpio_extra.c -* -* The implementation of the XGpio driver's advanced discrete functions. -* See xgpio.h for more information about the driver. -* -* @note -* -* These APIs can only be used if the GPIO_IO ports in the IP are used for -* connecting to the external output ports. -* -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a rmm 02/04/02 First release -* 2.00a jhl 12/16/02 Update for dual channel and interrupt support -* 2.11a mta 03/21/07 Updated to new coding style -* 3.00a sv 11/21/09 Updated to use HAL Processor APIs. Renamed the macros -* XGpio_mWriteReg to XGpio_WriteReg, and XGpio_mReadReg -* to XGpio_ReadReg. -* </pre> -* -*****************************************************************************/ - -/***************************** Include Files ********************************/ - -#include "xgpio.h" -#include "xgpio_i.h" - -/************************** Constant Definitions ****************************/ - -/**************************** Type Definitions ******************************/ - -/***************** Macros (Inline Functions) Definitions ********************/ - -/************************** Variable Definitions ****************************/ - -/************************** Function Prototypes *****************************/ - - -/****************************************************************************/ -/** -* Set output discrete(s) to logic 1 for the specified GPIO channel. -* -* @param InstancePtr is a pointer to an XGpio instance to be worked on. -* @param Channel contains the channel of the GPIO (1 or 2) to operate on. -* @param Mask is the set of bits that will be set to 1 in the discrete -* data register. All other bits in the data register are -* unaffected. -* -* @return None. -* -* @note -* -* The hardware must be built for dual channels if this function is used -* with any channel other than 1. If it is not, this function will assert. -* -* This API can only be used if the GPIO_IO ports in the IP are used for -* connecting to the external output ports. -* -*****************************************************************************/ -void XGpio_DiscreteSet(XGpio * InstancePtr, unsigned Channel, u32 Mask) -{ - u32 Current; - unsigned DataOffset; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid((Channel == 1) || - ((Channel == 2) && (InstancePtr->IsDual == TRUE))); - - /* - * Calculate the offset to the data register of the GPIO once - */ - DataOffset = ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET; - - /* - * Read the contents of the data register, merge in Mask and write - * back results - */ - Current = XGpio_ReadReg(InstancePtr->BaseAddress, DataOffset); - Current |= Mask; - XGpio_WriteReg(InstancePtr->BaseAddress, DataOffset, Current); -} - - -/****************************************************************************/ -/** -* Set output discrete(s) to logic 0 for the specified GPIO channel. -* -* @param InstancePtr is a pointer to an XGpio instance to be worked on. -* @param Channel contains the channel of the GPIO (1 or 2) to operate on. -* @param Mask is the set of bits that will be set to 0 in the discrete -* data register. All other bits in the data register are -* unaffected. -* -* @return None. -* -* @note -* -* The hardware must be built for dual channels if this function is used -* with any channel other than 1. If it is not, this function will assert. -* -* This API can only be used if the GPIO_IO ports in the IP are used for -* connecting to the external output ports. -* -*****************************************************************************/ -void XGpio_DiscreteClear(XGpio * InstancePtr, unsigned Channel, u32 Mask) -{ - u32 Current; - unsigned DataOffset; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid((Channel == 1) || - ((Channel == 2) && (InstancePtr->IsDual == TRUE))); - - /* - * Calculate the offset to the data register of the GPIO once - */ - DataOffset = ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET; - - /* - * Read the contents of the data register, merge in Mask and write - * back results - */ - Current = XGpio_ReadReg(InstancePtr->BaseAddress, DataOffset); - Current &= ~Mask; - XGpio_WriteReg(InstancePtr->BaseAddress, DataOffset, Current); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/xgpio_g.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/xgpio_g.c deleted file mode 100644 index 2bd5f4865a3ec54caeedf1fb6abd42a1b0a7e246..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/xgpio_g.c +++ /dev/null @@ -1,32 +0,0 @@ - -/******************************************************************* -* -* CAUTION: This file is automatically generated by libgen. -* Version: Xilinx EDK 14.7 EDK_P.20131013 -* DO NOT EDIT. -* -* Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. - -* -* Description: Driver configuration -* -*******************************************************************/ - -#include "xparameters.h" -#include "xgpio.h" - -/* -* The configuration table for devices -*/ - -XGpio_Config XGpio_ConfigTable[] = -{ - { - XPAR_BTNS_4BITS_TRI_IO_DEVICE_ID, - XPAR_BTNS_4BITS_TRI_IO_BASEADDR, - XPAR_BTNS_4BITS_TRI_IO_INTERRUPT_PRESENT, - XPAR_BTNS_4BITS_TRI_IO_IS_DUAL - } -}; - - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/xgpio_i.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/xgpio_i.h deleted file mode 100644 index 327ee540a95f5cd85b143c063cad8d83631c79f6..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/xgpio_i.h +++ /dev/null @@ -1,93 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2002-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/******************************************************************************/ -/** -* @file xgpio_i.h -* -* This header file contains internal identifiers, which are those shared -* between the files of the driver. It is intended for internal use only. -* -* NOTES: -* -* None. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a rmm 03/13/02 First release -* 2.11a mta 03/21/07 Updated to new coding style -* </pre> -******************************************************************************/ - -#ifndef XGPIO_I_H /* prevent circular inclusions */ -#define XGPIO_I_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xgpio.h" - -/************************** Constant Definitions ****************************/ - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - - -/************************** Variable Definitions ****************************/ - -extern XGpio_Config XGpio_ConfigTable[]; - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/xgpio_intr.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/xgpio_intr.c deleted file mode 100644 index 3aea00ece8307a5f39a3bf6b54cc8058fb588541..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/xgpio_intr.c +++ /dev/null @@ -1,301 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2002-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ - -/*****************************************************************************/ -/** -* @file xgpio_intr.c -* -* Implements GPIO interrupt processing functions for the XGpio driver. -* See xgpio.h for more information about the driver. -* -* The functions in this file require the hardware device to be built with -* interrupt capabilities. The functions will assert if called using hardware -* that does not have interrupt capabilities. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 2.00a jhl 11/26/03 Initial release -* 2.11a mta 03/21/07 Updated to new coding style -* 2.12a sv 06/05/08 Updated driver to fix the XGpio_InterruptDisable function -* to properly update the Interrupt Enable register -* 3.00a sv 11/21/09 Updated to use HAL Processor APIs. Renamed the macros -* XGpio_mWriteReg to XGpio_WriteReg, and XGpio_mReadReg -* to XGpio_ReadReg. - -* </pre> -* -*****************************************************************************/ - -/***************************** Include Files ********************************/ -#include "xgpio.h" - - -/************************** Constant Definitions ****************************/ - -/**************************** Type Definitions ******************************/ - -/***************** Macros (Inline Functions) Definitions ********************/ - -/************************** Variable Definitions ****************************/ - -/************************** Function Prototypes *****************************/ - - -/****************************************************************************/ -/** -* Enable the interrupt output signal. Interrupts enabled through -* XGpio_InterruptEnable() will not be passed through until the global enable -* bit is set by this function. This function is designed to allow all -* interrupts (both channels) to be enabled easily for exiting a critical -* section. This function will assert if the hardware device has not been -* built with interrupt capabilities. -* -* @param InstancePtr is the GPIO instance to operate on. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XGpio_InterruptGlobalEnable(XGpio * InstancePtr) -{ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE); - - XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_GIE_OFFSET, - XGPIO_GIE_GINTR_ENABLE_MASK); -} - - -/****************************************************************************/ -/** -* Disable the interrupt output signal. Interrupts enabled through -* XGpio_InterruptEnable() will no longer be passed through until the global -* enable bit is set by XGpio_InterruptGlobalEnable(). This function is -* designed to allow all interrupts (both channels) to be disabled easily for -* entering a critical section. This function will assert if the hardware -* device has not been built with interrupt capabilities. -* -* @param InstancePtr is the GPIO instance to operate on. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XGpio_InterruptGlobalDisable(XGpio * InstancePtr) -{ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE); - - - XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_GIE_OFFSET, 0x0); - -} - - -/****************************************************************************/ -/** -* Enable interrupts. The global interrupt must also be enabled by calling -* XGpio_InterruptGlobalEnable() for interrupts to occur. This function will -* assert if the hardware device has not been built with interrupt capabilities. -* -* @param InstancePtr is the GPIO instance to operate on. -* @param Mask is the mask to enable. Bit positions of 1 are enabled. -* This mask is formed by OR'ing bits from XGPIO_IR* bits which -* are contained in xgpio_l.h. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XGpio_InterruptEnable(XGpio * InstancePtr, u32 Mask) -{ - u32 Register; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE); - - /* - * Read the interrupt enable register and only enable the specified - * interrupts without disabling or enabling any others. - */ - - Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET); - XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET, - Register | Mask); - -} - - -/****************************************************************************/ -/** -* Disable interrupts. This function allows specific interrupts for each -* channel to be disabled. This function will assert if the hardware device -* has not been built with interrupt capabilities. -* -* @param InstancePtr is the GPIO instance to operate on. -* @param Mask is the mask to disable. Bits set to 1 are disabled. This -* mask is formed by OR'ing bits from XGPIO_IR* bits which are -* contained in xgpio_l.h. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XGpio_InterruptDisable(XGpio * InstancePtr, u32 Mask) -{ - u32 Register; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE); - - /* - * Read the interrupt enable register and only disable the specified - * interrupts without enabling or disabling any others. - */ - Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET); - XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET, - Register & (~Mask)); - -} - -/****************************************************************************/ -/** -* Clear pending interrupts with the provided mask. This function should be -* called after the software has serviced the interrupts that are pending. -* This function will assert if the hardware device has not been built with -* interrupt capabilities. -* -* @param InstancePtr is the GPIO instance to operate on. -* @param Mask is the mask to clear pending interrupts for. Bit positions -* of 1 are cleared. This mask is formed by OR'ing bits from -* XGPIO_IR* bits which are contained in xgpio_l.h. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XGpio_InterruptClear(XGpio * InstancePtr, u32 Mask) -{ - u32 Register; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE); - - /* - * Read the interrupt status register and only clear the interrupts - * that are specified without affecting any others. Since the register - * is a toggle on write, make sure any bits to be written are already - * set. - */ - Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET); - XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET, - Register & Mask); - - -} - - -/****************************************************************************/ -/** -* Returns the interrupt enable mask. This function will assert if the -* hardware device has not been built with interrupt capabilities. -* -* @param InstancePtr is the GPIO instance to operate on. -* -* @return A mask of bits made from XGPIO_IR* bits which are contained in -* xgpio_l.h. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -u32 XGpio_InterruptGetEnabled(XGpio * InstancePtr) -{ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(InstancePtr->InterruptPresent == TRUE); - - return XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET); -} - - -/****************************************************************************/ -/** -* Returns the status of interrupt signals. Any bit in the mask set to 1 -* indicates that the channel associated with the bit has asserted an interrupt -* condition. This function will assert if the hardware device has not been -* built with interrupt capabilities. -* -* @param InstancePtr is the GPIO instance to operate on. -* -* @return A pointer to a mask of bits made from XGPIO_IR* bits which are -* contained in xgpio_l.h. -* -* @note -* -* The interrupt status indicates the status of the device irregardless if -* the interrupts from the devices have been enabled or not through -* XGpio_InterruptEnable(). -* -*****************************************************************************/ -u32 XGpio_InterruptGetStatus(XGpio * InstancePtr) -{ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(InstancePtr->InterruptPresent == TRUE); - - - return XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/xgpio_l.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/xgpio_l.h deleted file mode 100644 index 5b3480706f8dffa08c7a080af2af1709f57be955..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/xgpio_l.h +++ /dev/null @@ -1,235 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2002-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xgpio_l.h -* -* This header file contains identifiers and driver functions (or -* macros) that can be used to access the device. The user should refer to the -* hardware device specification for more details of the device operation. -* -* The macros that are available in this file use a multiply to calculate the -* addresses of registers. The user can control whether that multiply is done -* at run time or at compile time. A constant passed as the channel parameter -* will cause the multiply to be done at compile time. A variable passed as the -* channel parameter will cause it to occur at run time. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a jhl 04/24/02 First release of low level driver -* 2.00a jhl 11/26/03 Added support for dual channels and interrupts. This -* change required the functions to be changed such that -* the interface is not compatible with previous versions. -* See the examples in the example directory for macros -* to help compile an application that was designed for -* previous versions of the driver. The interrupt registers -* are accessible using the ReadReg and WriteReg macros and -* a channel parameter was added to the other macros. -* 2.11a mta 03/21/07 Updated to new coding style -* 2.12a sv 11/21/07 Updated driver to support access through DCR bus. -* 3.00a sv 11/21/09 Renamed the macros XGpio_mWriteReg to XGpio_WriteReg -* XGpio_mReadReg to XGpio_ReadReg. -* Removed the macros XGpio_mSetDataDirection, -* XGpio_mGetDataReg and XGpio_mSetDataReg. Users -* should use XGpio_WriteReg/XGpio_ReadReg to achieve the -* same functionality. -* </pre> -* -******************************************************************************/ - -#ifndef XGPIO_L_H /* prevent circular inclusions */ -#define XGPIO_L_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xil_io.h" - -/* - * XPAR_XGPIO_USE_DCR_BRIDGE has to be set to 1 if the GPIO device is - * accessed through a DCR bus connected to a bridge - */ -#define XPAR_XGPIO_USE_DCR_BRIDGE 0 - - -#if (XPAR_XGPIO_USE_DCR_BRIDGE != 0) -#include "xio_dcr.h" -#endif - -/************************** Constant Definitions *****************************/ - -/** @name Registers - * - * Register offsets for this device. - * @{ - */ -#if (XPAR_XGPIO_USE_DCR_BRIDGE != 0) - -#define XGPIO_DATA_OFFSET 0x0 /**< Data register for 1st channel */ -#define XGPIO_TRI_OFFSET 0x1 /**< I/O direction reg for 1st channel */ -#define XGPIO_DATA2_OFFSET 0x2 /**< Data register for 2nd channel */ -#define XGPIO_TRI2_OFFSET 0x3 /**< I/O direction reg for 2nd channel */ - -#define XGPIO_GIE_OFFSET 0x47 /**< Global interrupt enable register */ -#define XGPIO_ISR_OFFSET 0x48 /**< Interrupt status register */ -#define XGPIO_IER_OFFSET 0x4A /**< Interrupt enable register */ - -#else - -#define XGPIO_DATA_OFFSET 0x0 /**< Data register for 1st channel */ -#define XGPIO_TRI_OFFSET 0x4 /**< I/O direction reg for 1st channel */ -#define XGPIO_DATA2_OFFSET 0x8 /**< Data register for 2nd channel */ -#define XGPIO_TRI2_OFFSET 0xC /**< I/O direction reg for 2nd channel */ - -#define XGPIO_GIE_OFFSET 0x11C /**< Glogal interrupt enable register */ -#define XGPIO_ISR_OFFSET 0x120 /**< Interrupt status register */ -#define XGPIO_IER_OFFSET 0x128 /**< Interrupt enable register */ - -#endif - -/* @} */ - -/* The following constant describes the offset of each channels data and - * tristate register from the base address. - */ -#define XGPIO_CHAN_OFFSET 8 - -/** @name Interrupt Status and Enable Register bitmaps and masks - * - * Bit definitions for the interrupt status register and interrupt enable - * registers. - * @{ - */ -#define XGPIO_IR_MASK 0x3 /**< Mask of all bits */ -#define XGPIO_IR_CH1_MASK 0x1 /**< Mask for the 1st channel */ -#define XGPIO_IR_CH2_MASK 0x2 /**< Mask for the 2nd channel */ -/*@}*/ - - -/** @name Global Interrupt Enable Register bitmaps and masks - * - * Bit definitions for the Global Interrupt Enable register - * @{ - */ -#define XGPIO_GIE_GINTR_ENABLE_MASK 0x80000000 -/*@}*/ - - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - /* - * Define the appropriate I/O access method to memory mapped I/O or DCR. - */ -#if (XPAR_XGPIO_USE_DCR_BRIDGE != 0) - -#define XGpio_In32 XIo_DcrIn -#define XGpio_Out32 XIo_DcrOut - -#else - -#define XGpio_In32 Xil_In32 -#define XGpio_Out32 Xil_Out32 - -#endif - - -/****************************************************************************/ -/** -* -* Write a value to a GPIO register. A 32 bit write is performed. If the -* GPIO core is implemented in a smaller width, only the least significant data -* is written. -* -* @param BaseAddress is the base address of the GPIO device. -* @param RegOffset is the register offset from the base to write to. -* @param Data is the data written to the register. -* -* @return None. -* -* @note C-style signature: -* void XGpio_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) -* -****************************************************************************/ -#define XGpio_WriteReg(BaseAddress, RegOffset, Data) \ - XGpio_Out32((BaseAddress) + (RegOffset), (u32)(Data)) - -/****************************************************************************/ -/** -* -* Read a value from a GPIO register. A 32 bit read is performed. If the -* GPIO core is implemented in a smaller width, only the least -* significant data is read from the register. The most significant data -* will be read as 0. -* -* @param BaseAddress is the base address of the GPIO device. -* @param RegOffset is the register offset from the base to read from. -* -* @return Data read from the register. -* -* @note C-style signature: -* u32 XGpio_ReadReg(u32 BaseAddress, u32 RegOffset) -* -****************************************************************************/ -#define XGpio_ReadReg(BaseAddress, RegOffset) \ - XGpio_In32((BaseAddress) + (RegOffset)) - -/************************** Function Prototypes ******************************/ - -/************************** Variable Definitions *****************************/ - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/xgpio_selftest.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/xgpio_selftest.c deleted file mode 100644 index ef94226457fd6995fcdb4cc0efce469d78536cbe..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/xgpio_selftest.c +++ /dev/null @@ -1,116 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2003-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* @file xgpio_selftest.c -* -* The implementation of the XGpio driver's self test function. -* See xgpio.h for more information about the driver. -* -* @note -* -* None -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a rmm 02/04/02 First release -* 2.00a jhl 01/13/04 Addition of dual channels and interrupts. -* 2.11a mta 03/21/07 Updated to new coding style -* 3.00a sv 11/21/09 Updated to use HAL Processor APIs. -* </pre> -* -*****************************************************************************/ - -/***************************** Include Files ********************************/ -#include "xgpio.h" - -/************************** Constant Definitions ****************************/ - -/**************************** Type Definitions ******************************/ - -/***************** Macros (Inline Functions) Definitions ********************/ - -/************************** Variable Definitions ****************************/ - -/************************** Function Prototypes *****************************/ - - -/******************************************************************************/ -/** -* Run a self-test on the driver/device. This function does a minimal test -* in which the data register is read. It only does a read without any kind -* of test because the hardware has been parameterized such that it may be only -* an input such that the state of the inputs won't be known. -* -* All other hardware features of the device are not guaranteed to be in the -* hardware since they are parameterizable. -* -* -* @param InstancePtr is a pointer to the XGpio instance to be worked on. -* This parameter must have been previously initialized with -* XGpio_Initialize(). -* -* @return XST_SUCCESS always. If the GPIO device was not present in the -* hardware a bus error could be generated. Other indicators of a -* bus error, such as registers in bridges or buses, may be -* necessary to determine if this function caused a bus error. -* -* @note None. -* -******************************************************************************/ -int XGpio_SelfTest(XGpio * InstancePtr) -{ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read from the data register of channel 1 which is always guaranteed - * to be in the hardware device. Since the data may be configured as - * all inputs, there is not way to guarantee the value read so don't - * test it. - */ - (void) XGpio_DiscreteRead(InstancePtr, 1); - - return (XST_SUCCESS); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/xgpio_sinit.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/xgpio_sinit.c deleted file mode 100644 index b9995614bcae0e67fdc3c7a08a563ab403d21f75..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpio_v3_01_a/src/xgpio_sinit.c +++ /dev/null @@ -1,159 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2003-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* @file xgpio_sinit.c -* -* The implementation of the XGpio driver's static initialzation -* functionality. -* -* @note -* -* None -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 2.01a jvb 10/13/05 First release -* 2.11a mta 03/21/07 Updated to new coding style -* </pre> -* -*****************************************************************************/ - -/***************************** Include Files ********************************/ - -#include "xstatus.h" -#include "xparameters.h" -#include "xgpio_i.h" - -/************************** Constant Definitions ****************************/ - -/**************************** Type Definitions ******************************/ - -/***************** Macros (Inline Functions) Definitions ********************/ - -/************************** Variable Definitions ****************************/ - - -/************************** Function Prototypes *****************************/ - - -/******************************************************************************/ -/** -* Lookup the device configuration based on the unique device ID. The table -* ConfigTable contains the configuration info for each device in the system. -* -* @param DeviceId is the device identifier to lookup. -* -* @return -* - A pointer of data type XGpio_Config which points to the -* device configuration if DeviceID is found. -* - NULL if DeviceID is not found. -* -* @note None. -* -******************************************************************************/ -XGpio_Config *XGpio_LookupConfig(u16 DeviceId) -{ - XGpio_Config *CfgPtr = NULL; - - int Index; - - for (Index = 0; Index < XPAR_XGPIO_NUM_INSTANCES; Index++) { - if (XGpio_ConfigTable[Index].DeviceId == DeviceId) { - CfgPtr = &XGpio_ConfigTable[Index]; - break; - } - } - - return CfgPtr; -} - - -/****************************************************************************/ -/** -* Initialize the XGpio instance provided by the caller based on the -* given DeviceID. -* -* Nothing is done except to initialize the InstancePtr. -* -* @param InstancePtr is a pointer to an XGpio instance. The memory the -* pointer references must be pre-allocated by the caller. Further -* calls to manipulate the instance/driver through the XGpio API -* must be made with this pointer. -* @param DeviceId is the unique id of the device controlled by this XGpio -* instance. Passing in a device id associates the generic XGpio -* instance to a specific device, as chosen by the caller or -* application developer. -* -* @return -* - XST_SUCCESS if the initialization was successfull. -* - XST_DEVICE_NOT_FOUND if the device configuration data was not -* found for a device with the supplied device ID. -* -* @note None. -* -*****************************************************************************/ -int XGpio_Initialize(XGpio * InstancePtr, u16 DeviceId) -{ - XGpio_Config *ConfigPtr; - - /* - * Assert arguments - */ - Xil_AssertNonvoid(InstancePtr != NULL); - - /* - * Lookup configuration data in the device configuration table. - * Use this configuration info down below when initializing this - * driver. - */ - ConfigPtr = XGpio_LookupConfig(DeviceId); - if (ConfigPtr == (XGpio_Config *) NULL) { - InstancePtr->IsReady = 0; - return (XST_DEVICE_NOT_FOUND); - } - - return XGpio_CfgInitialize(InstancePtr, ConfigPtr, - ConfigPtr->BaseAddress); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v1_02_a/src/Makefile b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v1_02_a/src/Makefile deleted file mode 100644 index f7eb27bf1e44fdc5a8ada275cefcc89f77a3416d..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v1_02_a/src/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -COMPILER= -ARCHIVER= -CP=cp -COMPILER_FLAGS= -EXTRA_COMPILER_FLAGS= -LIB=libxil.a - -CC_FLAGS = $(COMPILER_FLAGS) -ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) - -RELEASEDIR=../../../lib -INCLUDEDIR=../../../include -INCLUDES=-I./. -I${INCLUDEDIR} - -OUTS = *.o - -LIBSOURCES:=*.c -INCLUDEFILES:=*.h - -OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) - -libs: banner xgpiops_libs clean - -%.o: %.c - ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< - -banner: - echo "Compiling gpiops" - -xgpiops_libs: ${OBJECTS} - $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} - -.PHONY: include -include: xgpiops_includes - -xgpiops_includes: - ${CP} ${INCLUDEFILES} ${INCLUDEDIR} - -clean: - rm -rf ${OBJECTS} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v1_02_a/src/xgpiops.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v1_02_a/src/xgpiops.c deleted file mode 100644 index 4bfb203b2e63b2b2d6da533e906353390cb7c1ed..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v1_02_a/src/xgpiops.c +++ /dev/null @@ -1,604 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xgpiops.c -* -* The XGpioPs driver. Functions in this file are the minimum required functions -* for this driver. See xgpiops.h for a detailed description of the driver. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a sv 01/15/10 First Release -* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin -* XGpioPs_GetMode, XGpioPs_GetModePin as they are not -* relevant to Zynq device. The interrupts are disabled -* for output pins on all banks during initialization. -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xgpiops.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Variable Definitions *****************************/ - -/* - * This structure defines the mapping of the pin numbers to the banks when - * the driver APIs are used for working on the individual pins. - */ -unsigned int XGpioPsPinTable[] = { - 31, /* 0 - 31, Bank 0 */ - 53, /* 32 - 53, Bank 1 */ - 85, /* 54 - 85, Bank 2 */ - 117 /* 86 - 117 Bank 3 */ -}; - -/************************** Function Prototypes ******************************/ - -extern void StubHandler(void *CallBackRef, int Bank, u32 Status); - -/*****************************************************************************/ -/* -* -* This function initializes a XGpioPs instance/driver. -* All members of the XGpioPs instance structure are initialized and -* StubHandlers are assigned to the Bank Status Handlers. -* -* @param InstancePtr is a pointer to the XGpioPs instance. -* @param ConfigPtr points to the XGpioPs device configuration structure. -* @param EffectiveAddr is the device base address in the virtual memory -* address space. If the address translation is not used then the -* physical address should be passed. -* Unexpected errors may occur if the address mapping is changed -* after this function is invoked. -* -* @return XST_SUCCESS always. -* -* @note None. -* -******************************************************************************/ -int XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr, - u32 EffectiveAddr) -{ - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(ConfigPtr != NULL); - - /* - * Set some default values for instance data, don't indicate the device - * is ready to use until everything has been initialized successfully. - */ - InstancePtr->IsReady = 0; - InstancePtr->GpioConfig.BaseAddr = EffectiveAddr; - InstancePtr->GpioConfig.DeviceId = ConfigPtr->DeviceId; - InstancePtr->Handler = StubHandler; - - /* - * By default, interrupts are not masked in GPIO. Disable - * interrupts for all pins in all the 4 banks. - */ - XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, - XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFF); - - XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, - ((1) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFF); - - XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, - ((2) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFF); - - XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, - ((3) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFF); - - /* - * Indicate the component is now ready to use. - */ - InstancePtr->IsReady = XIL_COMPONENT_IS_READY; - - return XST_SUCCESS; -} - -/****************************************************************************/ -/** -* -* Read the Data register of the specified GPIO bank. -* -* @param InstancePtr is a pointer to the XGpioPs instance. -* @param Bank is the bank number of the GPIO to operate on. -* Valid values are 0 to XGPIOPS_MAX_BANKS - 1. -* -* @return Current value of the Data register. -* -* @note This function is used for reading the state of all the GPIO pins -* of specified bank. -* -*****************************************************************************/ -u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank) -{ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS); - - return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_DATA_BANK_OFFSET) + - XGPIOPS_DATA_OFFSET); -} - -/****************************************************************************/ -/** -* -* Read Data from the specified pin. -* -* @param InstancePtr is a pointer to the XGpioPs instance. -* @param Pin is the pin number for which the data has to be read. -* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1. -* See xgpiops.h for the mapping of the pin numbers in the banks. -* -* @return Current value of the Pin (0 or 1). -* -* @note This function is used for reading the state of the specified -* GPIO pin. -* -*****************************************************************************/ -int XGpioPs_ReadPin(XGpioPs *InstancePtr, int Pin) -{ - u8 Bank; - u8 PinNumber; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM); - - /* - * Get the Bank number and Pin number within the bank. - */ - XGpioPs_GetBankPin(Pin, &Bank, &PinNumber); - - return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_DATA_BANK_OFFSET) + - XGPIOPS_DATA_OFFSET) >> PinNumber) & 1; - -} - -/****************************************************************************/ -/** -* -* Write to the Data register of the specified GPIO bank. -* -* @param InstancePtr is a pointer to the XGpioPs instance. -* @param Bank is the bank number of the GPIO to operate on. -* Valid values are 0 to XGPIOPS_MAX_BANKS - 1. -* @param Data is the value to be written to the Data register. -* -* @return None. -* -* @note This function is used for writing to all the GPIO pins of -* the bank. The previous state of the pins is not maintained. -* -*****************************************************************************/ -void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data) -{ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS); - - XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_DATA_BANK_OFFSET) + - XGPIOPS_DATA_OFFSET, Data); -} - -/****************************************************************************/ -/** -* -* Write data to the specified pin. -* -* @param InstancePtr is a pointer to the XGpioPs instance. -* @param Pin is the pin number to which the Data is to be written. -* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1. -* @param Data is the data to be written to the specified pin (0 or 1). -* -* @return None. -* -* @note This function does a masked write to the specified pin of -* the specified GPIO bank. The previous state of other pins -* is maintained. -* -*****************************************************************************/ -void XGpioPs_WritePin(XGpioPs *InstancePtr, int Pin, int Data) -{ - u32 RegOffset; - u32 Value; - u8 Bank; - u8 PinNumber; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM); - - /* - * Get the Bank number and Pin number within the bank. - */ - XGpioPs_GetBankPin(Pin, &Bank, &PinNumber); - - if (PinNumber > 15) { - /* - * There are only 16 data bits in bit maskable register. - */ - PinNumber -= 16; - RegOffset = XGPIOPS_DATA_MSW_OFFSET; - } else { - RegOffset = XGPIOPS_DATA_LSW_OFFSET; - } - - /* - * Get the 32 bit value to be written to the Mask/Data register where - * the upper 16 bits is the mask and lower 16 bits is the data. - */ - Data &= 0x01; - Value = ~(1 << (PinNumber + 16)) & ((Data << PinNumber) | 0xFFFF0000); - XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_DATA_MASK_OFFSET) + - RegOffset, Value); -} - - - -/****************************************************************************/ -/** -* -* Set the Direction of the pins of the specified GPIO Bank. -* -* @param InstancePtr is a pointer to the XGpioPs instance. -* @param Bank is the bank number of the GPIO to operate on. -* Valid values are 0 to XGPIOPS_MAX_BANKS - 1. -* @param Direction is the 32 bit mask of the Pin direction to be set for -* all the pins in the Bank. Bits with 0 are set to Input mode, -* bits with 1 are set to Output Mode. -* -* @return None. -* -* @note This function is used for setting the direction of all the pins -* in the specified bank. The previous state of the pins is -* not maintained. -* -*****************************************************************************/ -void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction) -{ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS); - - XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_DIRM_OFFSET, Direction); -} - -/****************************************************************************/ -/** -* -* Set the Direction of the specified pin. -* -* @param InstancePtr is a pointer to the XGpioPs instance. -* @param Pin is the pin number to which the Data is to be written. -* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1. -* @param Direction is the direction to be set for the specified pin. -* Valid values are 0 for Input Direction, 1 for Output Direction. -* -* @return None. -* -*****************************************************************************/ -void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, int Pin, int Direction) -{ - u8 Bank; - u8 PinNumber; - u32 DirModeReg; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM); - Xil_AssertVoid((Direction == 0) || (Direction == 1)); - - /* - * Get the Bank number and Pin number within the bank. - */ - XGpioPs_GetBankPin(Pin, &Bank, &PinNumber); - - DirModeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_DIRM_OFFSET); - - if (Direction) { /* Output Direction */ - DirModeReg |= (1 << PinNumber); - } else { /* Input Direction */ - DirModeReg &= ~ (1 << PinNumber); - } - - XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_DIRM_OFFSET, DirModeReg); -} - -/****************************************************************************/ -/** -* -* Get the Direction of the pins of the specified GPIO Bank. -* -* @param InstancePtr is a pointer to the XGpioPs instance. -* @param Bank is the bank number of the GPIO to operate on. -* Valid values are 0 to XGPIOPS_MAX_BANKS - 1. -* -* return Returns a 32 bit mask of the Direction register. Bits with 0 are -* in Input mode, bits with 1 are in Output Mode. -* -* @note None. -* -*****************************************************************************/ -u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank) -{ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS); - - return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_DIRM_OFFSET); -} - -/****************************************************************************/ -/** -* -* Get the Direction of the specified pin. -* -* @param InstancePtr is a pointer to the XGpioPs instance. -* @param Pin is the pin number for which the Direction is to be -* retrieved. -* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1. -* -* @return Direction of the specified pin. -* - 0 for Input Direction -* - 1 for Output Direction -* -* @note None. -* -*****************************************************************************/ -int XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, int Pin) -{ - u8 Bank; - u8 PinNumber; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM); - - /* - * Get the Bank number and Pin number within the bank. - */ - XGpioPs_GetBankPin(Pin, &Bank, &PinNumber); - - return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_DIRM_OFFSET) >> PinNumber) & 1; -} - -/****************************************************************************/ -/** -* -* Set the Output Enable of the pins of the specified GPIO Bank. -* -* @param InstancePtr is a pointer to the XGpioPs instance. -* @param Bank is the bank number of the GPIO to operate on. -* Valid values are 0 to XGPIOPS_MAX_BANKS - 1. -* @param OpEnable is the 32 bit mask of the Output Enables to be set for -* all the pins in the Bank. The Output Enable of bits with 0 are -* disabled, the Output Enable of bits with 1 are enabled. -* -* @return None. -* -* @note This function is used for setting the Output Enables of all the -* pins in the specified bank. The previous state of the Output -* Enables is not maintained. -* -*****************************************************************************/ -void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable) -{ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS); - - XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_OUTEN_OFFSET, OpEnable); -} - -/****************************************************************************/ -/** -* -* Set the Output Enable of the specified pin. -* -* @param InstancePtr is a pointer to the XGpioPs instance. -* @param Pin is the pin number to which the Data is to be written. -* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1. -* @param OpEnable specifies whether the Output Enable for the specified -* pin should be enabled. -* Valid values are 0 for Disabling Output Enable, -* 1 for Enabling Output Enable. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, int Pin, int OpEnable) -{ - u8 Bank; - u8 PinNumber; - u32 OpEnableReg; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM); - Xil_AssertVoid((OpEnable == 0) || (OpEnable == 1)); - - /* - * Get the Bank number and Pin number within the bank. - */ - XGpioPs_GetBankPin(Pin, &Bank, &PinNumber); - - OpEnableReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_OUTEN_OFFSET); - - if (OpEnable) { /* Enable Output Enable */ - OpEnableReg |= (1 << PinNumber); - } else { /* Disable Output Enable */ - OpEnableReg &= ~ (1 << PinNumber); - } - - XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_OUTEN_OFFSET, OpEnableReg); -} -/****************************************************************************/ -/** -* -* Get the Output Enable status of the pins of the specified GPIO Bank. -* -* @param InstancePtr is a pointer to the XGpioPs instance. -* @param Bank is the bank number of the GPIO to operate on. -* Valid values are 0 to XGPIOPS_MAX_BANKS - 1. -* -* return Returns a a 32 bit mask of the Output Enable register. -* Bits with 0 are in Disabled state, bits with 1 are in -* Enabled State. -* -* @note None. -* -*****************************************************************************/ -u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank) -{ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS); - - return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_OUTEN_OFFSET); -} - -/****************************************************************************/ -/** -* -* Get the Output Enable status of the specified pin. -* -* @param InstancePtr is a pointer to the XGpioPs instance. -* @param Pin is the pin number for which the Output Enable status is to -* be retrieved. -* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1. -* -* @return Output Enable of the specified pin. -* - 0 if Output Enable is disabled for this pin -* - 1 if Output Enable is enabled for this pin -* -* @note None. -* -*****************************************************************************/ -int XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, int Pin) -{ - u8 Bank; - u8 PinNumber; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM); - - /* - * Get the Bank number and Pin number within the bank. - */ - XGpioPs_GetBankPin(Pin, &Bank, &PinNumber); - - return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_OUTEN_OFFSET) >> PinNumber) & 1; -} - -/****************************************************************************/ -/* -* -* Get the Bank number and the Pin number in the Bank, for the given PinNumber -* in the GPIO device. -* -* @param PinNumber is the Pin number in the GPIO device. -* @param BankNumber returns the Bank in which this GPIO pin is present. -* Valid values are 0 to XGPIOPS_MAX_BANKS - 1. -* @param PinNumberInBank returns the Pin Number within the Bank. -* -* return None; -* -* @note None. -* -*****************************************************************************/ -void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank) -{ - for (*BankNumber = 0; *BankNumber < 4; (*BankNumber)++) - if (PinNumber <= XGpioPsPinTable[*BankNumber]) - break; - - if (*BankNumber == 0) { - *PinNumberInBank = PinNumber; - } else { - *PinNumberInBank = PinNumber % - (XGpioPsPinTable[*BankNumber - 1] + 1); - } -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v1_02_a/src/xgpiops.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v1_02_a/src/xgpiops.h deleted file mode 100644 index 1b8eb4ff27eaa05ebcc1ce84c43a71f3b8fd4a5e..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v1_02_a/src/xgpiops.h +++ /dev/null @@ -1,262 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xgpiops.h -* -* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO -* Controller. -* -* The GPIO Controller supports the following features: -* - 4 banks -* - Masked writes (There are no masked reads) -* - Bypass mode -* - Configurable Interrupts (Level/Edge) -* -* This driver is intended to be RTOS and processor independent. Any needs for -* dynamic memory management, threads or thread mutual exclusion, virtual -* memory, or cache control must be satisfied by the layer above this driver. - -* This driver supports all the features listed above, if applicable. -* -* <b>Driver Description</b> -* -* The device driver enables higher layer software (e.g., an application) to -* communicate to the GPIO. -* -* <b>Interrupts</b> -* -* The driver provides interrupt management functions and an interrupt handler. -* Users of this driver need to provide callback functions. An interrupt handler -* example is available with the driver. -* -* <b>Threads</b> -* -* This driver is not thread safe. Any needs for threads or thread mutual -* exclusion must be satisfied by the layer above this driver. -* -* <b>Asserts</b> -* -* Asserts are used within all Xilinx drivers to enforce constraints on argument -* values. Asserts can be turned off on a system-wide basis by defining, at -* compile time, the NDEBUG identifier. By default, asserts are turned on and it -* is recommended that users leave asserts on during development. -* -* <b>Building the driver</b> -* -* The XGpioPs driver is composed of several source files. This allows the user -* to build and link only those parts of the driver that are necessary. -* <br><br> -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a sv 01/15/10 First Release -* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin -* XGpioPs_GetMode, XGpioPs_GetModePin as they are not -* relevant to Zynq device.The interrupts are disabled -* for output pins on all banks during initialization. -* 1.02a hk 08/22/13 Added low level reset API -* </pre> -* -******************************************************************************/ -#ifndef XGPIOPS_H /* prevent circular inclusions */ -#define XGPIOPS_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xstatus.h" -#include "xgpiops_hw.h" - -/************************** Constant Definitions *****************************/ - -/** @name Interrupt types - * @{ - * The following constants define the interrupt types that can be set for each - * GPIO pin. - */ -#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0 /**< Interrupt on Rising edge */ -#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 1 /**< Interrupt Falling edge */ -#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 2 /**< Interrupt on both edges */ -#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 3 /**< Interrupt on high level */ -#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 4 /**< Interrupt on low level */ -/*@}*/ - -#define XGPIOPS_BANK0 0 /**< GPIO Bank 0 */ -#define XGPIOPS_BANK1 1 /**< GPIO Bank 1 */ -#define XGPIOPS_BANK2 2 /**< GPIO Bank 2 */ -#define XGPIOPS_BANK3 3 /**< GPIO Bank 3 */ - -#define XGPIOPS_MAX_BANKS 4 /**< Max banks in a GPIO device */ -#define XGPIOPS_BANK_MAX_PINS 32 /**< Max pins in a GPIO bank */ - -#define XGPIOPS_DEVICE_MAX_PIN_NUM 118 /*< Max pins in the GPIO device - * 0 - 31, Bank 0 - * 32 - 53, Bank 1 - * 54 - 85, Bank 2 - * 86 - 117, Bank 3 - */ - -/**************************** Type Definitions *******************************/ - -/****************************************************************************/ -/** - * This handler data type allows the user to define a callback function to - * handle the interrupts for the GPIO device. The application using this - * driver is expected to define a handler of this type, to support interrupt - * driven mode. The handler executes in an interrupt context such that minimal - * processing should be performed. - * - * @param CallBackRef is a callback reference passed in by the upper layer - * when setting the callback functions for a GPIO bank. It is - * passed back to the upper layer when the callback is invoked. Its - * type is not important to the driver component, so it is a void - * pointer. - * @param Bank is the bank for which the interrupt status has changed. - * @param Status is the Interrupt status of the GPIO bank. - * - *****************************************************************************/ -typedef void (*XGpioPs_Handler) (void *CallBackRef, int Bank, u32 Status); - -/** - * This typedef contains configuration information for a device. - */ -typedef struct { - u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddr; /**< Register base address */ -} XGpioPs_Config; - -/** - * The XGpioPs driver instance data. The user is required to allocate a - * variable of this type for the GPIO device in the system. A pointer - * to a variable of this type is then passed to the driver API functions. - */ -typedef struct { - XGpioPs_Config GpioConfig; /**< Device configuration */ - u32 IsReady; /**< Device is initialized and ready */ - XGpioPs_Handler Handler; /**< Status handlers for all banks */ - void *CallBackRef; /**< Callback ref for bank handlers */ -} XGpioPs; - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/* - * Functions in xgpiops.c - */ -int XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr, - u32 EffectiveAddr); - -/* - * Bank APIs in xgpiops.c - */ -u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank); -void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data); -void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction); -u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank); -void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 Enable); -u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank); -void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank); - -/* - * Pin APIs in xgpiops.c - */ -int XGpioPs_ReadPin(XGpioPs *InstancePtr, int Pin); -void XGpioPs_WritePin(XGpioPs *InstancePtr, int Pin, int Data); -void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, int Pin, int Direction); -int XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, int Pin); -void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, int Pin, int Enable); -int XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, int Pin); - -/* - * Diagnostic functions in xgpiops_selftest.c - */ -int XGpioPs_SelfTest(XGpioPs *InstancePtr); - -/* - * Functions in xgpiops_intr.c - */ -/* - * Bank APIs in xgpiops_intr.c - */ -void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask); -void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask); -u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank); -u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank); -void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask); -void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType, - u32 IntrPolarity, u32 IntrOnAny); -void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType, - u32 *IntrPolarity, u32 *IntrOnAny); -void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef, - XGpioPs_Handler FuncPtr); -void XGpioPs_IntrHandler(XGpioPs *InstancePtr); - -/* - * Pin APIs in xgpiops_intr.c - */ -void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, int Pin, u8 IrqType); -u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, int Pin); - -void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, int Pin); -void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, int Pin); -int XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, int Pin); -int XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, int Pin); -void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, int Pin); - -/* - * Functions in xgpiops_sinit.c - */ -XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v1_02_a/src/xgpiops_g.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v1_02_a/src/xgpiops_g.c deleted file mode 100644 index 23af564f8497d1ece8934d8e6969acf957474ba9..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v1_02_a/src/xgpiops_g.c +++ /dev/null @@ -1,30 +0,0 @@ - -/******************************************************************* -* -* CAUTION: This file is automatically generated by libgen. -* Version: Xilinx EDK 14.7 EDK_P.20131013 -* DO NOT EDIT. -* -* Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. - -* -* Description: Driver configuration -* -*******************************************************************/ - -#include "xparameters.h" -#include "xgpiops.h" - -/* -* The configuration table for devices -*/ - -XGpioPs_Config XGpioPs_ConfigTable[] = -{ - { - XPAR_PS7_GPIO_0_DEVICE_ID, - XPAR_PS7_GPIO_0_BASEADDR - } -}; - - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v1_02_a/src/xgpiops_hw.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v1_02_a/src/xgpiops_hw.c deleted file mode 100644 index 0bd51df9cbd986fbc54b42d890f0545aa3459e30..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v1_02_a/src/xgpiops_hw.c +++ /dev/null @@ -1,171 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xgpiops_hw.c -* -* This file contains low level GPIO functions. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.02a hk 08/22/13 First Release -* -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xgpiops_hw.h" -#include "xgpiops.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Variable Definitions *****************************/ - -/************************** Function Prototypes ******************************/ - - -/*****************************************************************************/ -/* -* -* This function resets the GPIO module by writing reset values to -* all registers -* -* @param Base address of GPIO module -* -* @return None -* -* @note None. -* -******************************************************************************/ -void XGpioPs_ResetHw(u32 BaseAddress) -{ - u32 BankCount; - - /* - * Write reset values to all mask data registers - */ - for(BankCount = 2; BankCount < XGPIOPS_MAX_BANKS; BankCount++) { - - XGpioPs_WriteReg(BaseAddress, - ((BankCount * XGPIOPS_DATA_MASK_OFFSET) + - XGPIOPS_DATA_LSW_OFFSET), 0x0); - XGpioPs_WriteReg(BaseAddress, - ((BankCount * XGPIOPS_DATA_MASK_OFFSET) + - XGPIOPS_DATA_MSW_OFFSET), 0x0); - } - /* - * Write reset values to all output data registers - */ - for(BankCount = 2; BankCount < XGPIOPS_MAX_BANKS; BankCount++) { - - XGpioPs_WriteReg(BaseAddress, - ((BankCount * XGPIOPS_DATA_BANK_OFFSET) + - XGPIOPS_DATA_OFFSET), 0x0); - } - - /* - * Reset all registers of all 4 banks - */ - for(BankCount = 0; BankCount < XGPIOPS_MAX_BANKS; BankCount++) { - - XGpioPs_WriteReg(BaseAddress, - ((BankCount * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_DIRM_OFFSET), 0x0); - XGpioPs_WriteReg(BaseAddress, - ((BankCount * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_OUTEN_OFFSET), 0x0); - XGpioPs_WriteReg(BaseAddress, - ((BankCount * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTMASK_OFFSET), 0x0); - XGpioPs_WriteReg(BaseAddress, - ((BankCount * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTEN_OFFSET), 0x0); - XGpioPs_WriteReg(BaseAddress, - ((BankCount * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTDIS_OFFSET), 0x0); - XGpioPs_WriteReg(BaseAddress, - ((BankCount * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTSTS_OFFSET), 0x0); - XGpioPs_WriteReg(BaseAddress, - ((BankCount * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTPOL_OFFSET), 0x0); - XGpioPs_WriteReg(BaseAddress, - ((BankCount * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTANY_OFFSET), 0x0); - } - - /* - * Bank 0 Int type - */ - XGpioPs_WriteReg(BaseAddress, XGPIOPS_INTTYPE_OFFSET, - XGPIOPS_INTTYPE_BANK0_RESET); - /* - * Bank 1 Int type - */ - XGpioPs_WriteReg(BaseAddress, - (XGPIOPS_REG_MASK_OFFSET + XGPIOPS_INTTYPE_OFFSET), - XGPIOPS_INTTYPE_BANK1_RESET); - /* - * Bank 2 Int type - */ - XGpioPs_WriteReg(BaseAddress, - ((2*XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET), - XGPIOPS_INTTYPE_BANK2_RESET); - /* - * Bank 3 Int type - */ - XGpioPs_WriteReg(BaseAddress, - ((3*XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET), - XGPIOPS_INTTYPE_BANK3_RESET); - -} - - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v1_02_a/src/xgpiops_hw.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v1_02_a/src/xgpiops_hw.h deleted file mode 100644 index 28c4993fa4d352ac1fecba11a2ed31e81f17c7f0..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v1_02_a/src/xgpiops_hw.h +++ /dev/null @@ -1,158 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xgpiops_hw.h -* -* This header file contains the identifiers and basic driver functions (or -* macros) that can be used to access the device. Other driver functions -* are defined in xgpiops.h. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------- -* 1.00a sv 01/15/10 First Release -* 1.02a hk 08/22/13 Added low level reset API function prototype and -* related constant definitions -* </pre> -* -******************************************************************************/ -#ifndef XGPIOPS_HW_H /* prevent circular inclusions */ -#define XGPIOPS_HW_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xil_io.h" - -/************************** Constant Definitions *****************************/ - -/** @name Register offsets for the GPIO. Each register is 32 bits. - * @{ - */ -#define XGPIOPS_DATA_LSW_OFFSET 0x000 /* Mask and Data Register LSW, WO */ -#define XGPIOPS_DATA_MSW_OFFSET 0x004 /* Mask and Data Register MSW, WO */ -#define XGPIOPS_DATA_OFFSET 0x040 /* Data Register, RW */ -#define XGPIOPS_DIRM_OFFSET 0x204 /* Direction Mode Register, RW */ -#define XGPIOPS_OUTEN_OFFSET 0x208 /* Output Enable Register, RW */ -#define XGPIOPS_INTMASK_OFFSET 0x20C /* Interrupt Mask Register, RO */ -#define XGPIOPS_INTEN_OFFSET 0x210 /* Interrupt Enable Register, WO */ -#define XGPIOPS_INTDIS_OFFSET 0x214 /* Interrupt Disable Register, WO*/ -#define XGPIOPS_INTSTS_OFFSET 0x218 /* Interrupt Status Register, RO */ -#define XGPIOPS_INTTYPE_OFFSET 0x21C /* Interrupt Type Register, RW */ -#define XGPIOPS_INTPOL_OFFSET 0x220 /* Interrupt Polarity Register, RW */ -#define XGPIOPS_INTANY_OFFSET 0x224 /* Interrupt On Any Register, RW */ -/* @} */ - -/** @name Register offsets for each Bank. - * @{ - */ -#define XGPIOPS_DATA_MASK_OFFSET 0x8 /* Data/Mask Registers offset */ -#define XGPIOPS_DATA_BANK_OFFSET 0x4 /* Data Registers offset */ -#define XGPIOPS_REG_MASK_OFFSET 0x40 /* Registers offset */ -/* @} */ - -/* For backwards compatibility */ -#define XGPIOPS_BYPM_MASK_OFFSET XGPIOPS_REG_MASK_OFFSET - -/** @name Interrupt type reset values for each bank - * @{ - */ -#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFF -#define XGPIOPS_INTTYPE_BANK1_RESET 0x3FFFFFFF -#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFF -#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFF -/* @} */ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/****************************************************************************/ -/** -* -* This macro reads the given register. -* -* @param BaseAddr is the base address of the device. -* @param RegOffset is the register offset to be read. -* -* @return The 32-bit value of the register -* -* @note None. -* -*****************************************************************************/ -#define XGpioPs_ReadReg(BaseAddr, RegOffset) \ - Xil_In32((BaseAddr) + (RegOffset)) - -/****************************************************************************/ -/** -* -* This macro writes to the given register. -* -* @param BaseAddr is the base address of the device. -* @param RegOffset is the offset of the register to be written. -* @param Data is the 32-bit value to write to the register. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \ - Xil_Out32((BaseAddr) + (RegOffset), (Data)) - -/************************** Function Prototypes ******************************/ - -void XGpioPs_ResetHw(u32 BaseAddress); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* XGPIOPS_HW_H */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v1_02_a/src/xgpiops_intr.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v1_02_a/src/xgpiops_intr.c deleted file mode 100644 index 4dd2c970fd04cbc0cbe0e22f66646304ebb0191a..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v1_02_a/src/xgpiops_intr.c +++ /dev/null @@ -1,741 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xgpiops_intr.c -* -* This file contains functions related to GPIO interrupt handling. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a sv 01/18/10 First Release -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xgpiops.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Variable Definitions *****************************/ - -/************************** Function Prototypes ******************************/ - -void StubHandler(void *CallBackRef, int Bank, u32 Status); - -/****************************************************************************/ -/** -* -* This function enables the interrupts for the specified pins in the specified -* bank. -* -* @param InstancePtr is a pointer to the XGpioPs instance. -* @param Bank is the bank number of the GPIO to operate on. -* Valid values are 0 to XGPIOPS_MAX_BANKS - 1. -* @param Mask is the bit mask of the pins for which interrupts are to -* be enabled. Bit positions of 1 will be enabled. Bit positions -* of 0 will keep the previous setting. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask) -{ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS); - - XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTEN_OFFSET, Mask); -} - -/****************************************************************************/ -/** -* -* This function enables the interrupt for the specified pin. -* -* @param InstancePtr is a pointer to the XGpioPs instance. -* @param Pin is the pin number for which the interrupt is to be enabled. -* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, int Pin) -{ - u8 Bank; - u8 PinNumber; - u32 IntrReg = 0; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM); - - /* - * Get the Bank number and Pin number within the bank. - */ - XGpioPs_GetBankPin(Pin, &Bank, &PinNumber); - - IntrReg = 1 << PinNumber; - XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTEN_OFFSET, IntrReg); -} - -/****************************************************************************/ -/** -* -* This function disables the interrupts for the specified pins in the specified -* bank. -* -* @param InstancePtr is a pointer to the XGpioPs instance. -* @param Bank is the bank number of the GPIO to operate on. -* Valid values are 0 to XGPIOPS_MAX_BANKS - 1. -* @param Mask is the bit mask of the pins for which interrupts are -* to be disabled. Bit positions of 1 will be disabled. Bit -* positions of 0 will keep the previous setting. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask) -{ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS); - - XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTDIS_OFFSET, Mask); -} - -/****************************************************************************/ -/** -* -* This function disables the interrupts for the specified pin. -* -* @param InstancePtr is a pointer to the XGpioPs instance. -* @param Pin is the pin number for which the interrupt is to be disabled. -* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, int Pin) -{ - u8 Bank; - u8 PinNumber; - u32 IntrReg = 0; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM); - - /* - * Get the Bank number and Pin number within the bank. - */ - XGpioPs_GetBankPin(Pin, &Bank, &PinNumber); - - IntrReg = 1 << PinNumber; - XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTDIS_OFFSET, IntrReg); -} - -/****************************************************************************/ -/** -* -* This function returns the interrupt enable status for a bank. -* -* @param InstancePtr is a pointer to the XGpioPs instance. -* @param Bank is the bank number of the GPIO to operate on. -* Valid values are 0 to XGPIOPS_MAX_BANKS - 1. -* -* @return Enabled interrupt(s) in a 32-bit format. Bit positions with 1 -* indicate that the interrupt for that pin is enabled, bit -* positions with 0 indicate that the interrupt for that pin is -* disabled. -* -* @note None. -* -*****************************************************************************/ -u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank) -{ - u32 IntrMask; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS); - - IntrMask = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTMASK_OFFSET); - return ~IntrMask; -} - -/****************************************************************************/ -/** -* -* This function returns whether interrupts are enabled for the specified pin. -* -* @param InstancePtr is a pointer to the XGpioPs instance. -* @param Pin is the pin number for which the interrupt enable status -* is to be known. -* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1. -* -* @return -* - TRUE if the interrupt is enabled. -* - FALSE if the interrupt is disabled. -* -* @note None. -* -*****************************************************************************/ -int XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, int Pin) -{ - u8 Bank; - u8 PinNumber; - u32 IntrReg; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM); - - /* - * Get the Bank number and Pin number within the bank. - */ - XGpioPs_GetBankPin(Pin, &Bank, &PinNumber); - - IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTMASK_OFFSET); - - return (IntrReg & (1 << Pin)) ? TRUE : FALSE; -} - -/****************************************************************************/ -/** -* -* This function returns interrupt status read from Interrupt Status Register. -* -* @param InstancePtr is a pointer to the XGpioPs instance. -* @param Bank is the bank number of the GPIO to operate on. -* Valid values are 0 to XGPIOPS_MAX_BANKS - 1. -* -* @return The value read from Interrupt Status Register. -* -* @note None. -* -*****************************************************************************/ -u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank) -{ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS); - - return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTSTS_OFFSET); -} - -/****************************************************************************/ -/** -* -* This function returns interrupt enable status of the specified pin. -* -* @param InstancePtr is a pointer to the XGpioPs instance. -* @param Pin is the pin number for which the interrupt enable status -* is to be known. -* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1. -* -* @return -* - TRUE if the interrupt has occurred. -* - FALSE if the interrupt has not occurred. -* -* @note None. -* -*****************************************************************************/ -int XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, int Pin) -{ - u8 Bank; - u8 PinNumber; - u32 IntrReg; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM); - - /* - * Get the Bank number and Pin number within the bank. - */ - XGpioPs_GetBankPin(Pin, &Bank, &PinNumber); - - IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTSTS_OFFSET); - - return (IntrReg & (1 << Pin)) ? TRUE : FALSE; -} - -/****************************************************************************/ -/** -* -* This function clears pending interrupt(s) with the provided mask. This -* function should be called after the software has serviced the interrupts -* that are pending. -* -* @param InstancePtr is a pointer to the XGpioPs instance. -* @param Bank is the bank number of the GPIO to operate on. -* Valid values are 0 to XGPIOPS_MAX_BANKS - 1. -* @param Mask is the mask of the interrupts to be cleared. Bit positions -* of 1 will be cleared. Bit positions of 0 will not change the -* previous interrupt status. -* -* @note None. -* -*****************************************************************************/ -void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask) -{ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS); - - /* - * Clear the currently pending interrupts. - */ - XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTSTS_OFFSET, Mask); -} - -/****************************************************************************/ -/** -* -* This function clears the specified pending interrupt. This function should be -* called after the software has serviced the interrupts that are pending. -* -* @param InstancePtr is a pointer to the XGpioPs instance. -* @param Pin is the pin number for which the interrupt status is to be -* cleared. Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1. -* -* @note None. -* -*****************************************************************************/ -void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, int Pin) -{ - u8 Bank; - u8 PinNumber; - u32 IntrReg; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM); - - /* - * Get the Bank number and Pin number within the bank. - */ - XGpioPs_GetBankPin(Pin, &Bank, &PinNumber); - - /* - * Clear the specified pending interrupts. - */ - IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTSTS_OFFSET); - - IntrReg &= (1 << Pin); - XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTSTS_OFFSET, IntrReg); -} - -/****************************************************************************/ -/** -* -* This function is used for setting the Interrupt Type, Interrupt Polarity and -* Interrupt On Any for the specified GPIO Bank pins. -* -* @param InstancePtr is a pointer to an XGpioPs instance. -* @param Bank is the bank number of the GPIO to operate on. -* Valid values are 0 to XGPIOPS_MAX_BANKS - 1. -* @param IntrType is the 32 bit mask of the interrupt type. -* 0 means Level Sensitive and 1 means Edge Sensitive. -* @param IntrPolarity is the 32 bit mask of the interrupt polarity. -* 0 means Active Low or Falling Edge and 1 means Active High or -* Rising Edge. -* @param IntrOnAny is the 32 bit mask of the interrupt trigger for -* edge triggered interrupts. 0 means trigger on single edge using -* the configured interrupt polarity and 1 means trigger on both -* edges. -* -* @return None. -* -* @note This function is used for setting the interrupt related -* properties of all the pins in the specified bank. The previous -* state of the pins is not maintained. -* To change the Interrupt properties of a single GPIO pin, use the -* function XGpioPs_SetPinIntrType(). -* -*****************************************************************************/ -void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType, - u32 IntrPolarity, u32 IntrOnAny) -{ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS); - - XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTTYPE_OFFSET, IntrType); - - XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTPOL_OFFSET, IntrPolarity); - - XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTANY_OFFSET, IntrOnAny); -} - -/****************************************************************************/ -/** -* -* This function is used for getting the Interrupt Type, Interrupt Polarity and -* Interrupt On Any for the specified GPIO Bank pins. -* -* @param InstancePtr is a pointer to an XGpioPs instance. -* @param Bank is the bank number of the GPIO to operate on. -* Valid values are 0 to XGPIOPS_MAX_BANKS - 1. -* @param IntrType returns the 32 bit mask of the interrupt type. -* 0 means Level Sensitive and 1 means Edge Sensitive. -* @param IntrPolarity returns the 32 bit mask of the interrupt -* polarity. 0 means Active Low or Falling Edge and 1 means -* Active High or Rising Edge. -* @param IntrOnAny returns the 32 bit mask of the interrupt trigger for -* edge triggered interrupts. 0 means trigger on single edge using -* the configured interrupt polarity and 1 means trigger on both -* edges. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType, - u32 *IntrPolarity, u32 *IntrOnAny) - -{ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS); - - *IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTTYPE_OFFSET); - - *IntrPolarity = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTPOL_OFFSET); - - *IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTANY_OFFSET); -} - -/****************************************************************************/ -/** -* -* This function is used for setting the IRQ Type of a single GPIO pin. -* -* @param InstancePtr is a pointer to an XGpioPs instance. -* @param Pin is the pin number whose IRQ type is to be set. -* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1. -* @param IrqType is the IRQ type for GPIO Pin. Use XGPIOPS_IRQ_TYPE_* -* defined in xgpiops.h to specify the IRQ type. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, int Pin, u8 IrqType) -{ - u32 IntrTypeReg; - u32 IntrPolReg; - u32 IntrOnAnyReg; - u8 Bank; - u8 PinNumber; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM); - Xil_AssertVoid(IrqType <= XGPIOPS_IRQ_TYPE_LEVEL_LOW); - - /* - * Get the Bank number and Pin number within the bank. - */ - XGpioPs_GetBankPin(Pin, &Bank, &PinNumber); - - IntrTypeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTTYPE_OFFSET); - - IntrPolReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTPOL_OFFSET); - - IntrOnAnyReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTANY_OFFSET); - - switch (IrqType) { - case XGPIOPS_IRQ_TYPE_EDGE_RISING: - IntrTypeReg |= (1 << PinNumber); - IntrPolReg |= (1 << PinNumber); - IntrOnAnyReg &= ~(1 << PinNumber); - break; - case XGPIOPS_IRQ_TYPE_EDGE_FALLING: - IntrTypeReg |= (1 << PinNumber); - IntrPolReg &= ~(1 << PinNumber); - IntrOnAnyReg &= ~(1 << PinNumber); - break; - case XGPIOPS_IRQ_TYPE_EDGE_BOTH: - IntrTypeReg |= (1 << PinNumber); - IntrOnAnyReg |= (1 << PinNumber); - break; - case XGPIOPS_IRQ_TYPE_LEVEL_HIGH: - IntrTypeReg &= ~(1 << PinNumber); - IntrPolReg |= (1 << PinNumber); - break; - case XGPIOPS_IRQ_TYPE_LEVEL_LOW: - IntrTypeReg &= ~(1 << PinNumber); - IntrPolReg &= ~(1 << PinNumber); - break; - } - - XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTTYPE_OFFSET, IntrTypeReg); - - XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTPOL_OFFSET, IntrPolReg); - - XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTANY_OFFSET, IntrOnAnyReg); -} - -/****************************************************************************/ -/** -* -* This function returns the IRQ Type of a given GPIO pin. -* -* @param InstancePtr is a pointer to an XGpioPs instance. -* @param Pin is the pin number whose IRQ type is to be obtained. -* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1. -* -* @return None. -* -* @note Use XGPIOPS_IRQ_TYPE_* defined in xgpiops.h for the IRQ type -* returned by this function. -* -*****************************************************************************/ -u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, int Pin) -{ - u32 IntrType; - u32 IntrPol; - u32 IntrOnAny; - u8 Bank; - u8 PinNumber; - u8 IrqType; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM); - - /* - * Get the Bank number and Pin number within the bank. - */ - XGpioPs_GetBankPin(Pin, &Bank, &PinNumber); - - IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTTYPE_OFFSET) & PinNumber; - - IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTPOL_OFFSET) & PinNumber; - - IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr, - ((Bank) * XGPIOPS_REG_MASK_OFFSET) + - XGPIOPS_INTANY_OFFSET) & PinNumber; - - if (IntrType == 1) { - if (IntrOnAny == 1) { - IrqType = XGPIOPS_IRQ_TYPE_EDGE_BOTH; - } else if (IntrPol == 1) { - IrqType = XGPIOPS_IRQ_TYPE_EDGE_RISING; - } else { - IrqType = XGPIOPS_IRQ_TYPE_EDGE_FALLING; - } - } else { - if (IntrPol == 1) { - IrqType = XGPIOPS_IRQ_TYPE_LEVEL_HIGH; - } else { - IrqType = XGPIOPS_IRQ_TYPE_LEVEL_LOW; - } - } - - return IrqType; -} - -/*****************************************************************************/ -/** -* -* This function sets the status callback function. The callback function is -* called by the XGpioPs_IntrHandler when an interrupt occurs. -* -* @param InstancePtr is a pointer to the XGpioPs instance. -* @param CallBackRef is the upper layer callback reference passed back -* when the callback function is invoked. -* @param FuncPtr is the pointer to the callback function. -* -* -* @return None. -* -* @note The handler is called within interrupt context, so it should do -* its work quickly and queue potentially time-consuming work to a -* task-level thread. -* -******************************************************************************/ -void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef, - XGpioPs_Handler FuncPtr) -{ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(FuncPtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - InstancePtr->Handler = FuncPtr; - InstancePtr->CallBackRef = CallBackRef; -} - -/*****************************************************************************/ -/** -* -* This function is the interrupt handler for GPIO interrupts.It checks the -* interrupt status registers of all the banks to determine the actual bank in -* which an interrupt has been triggered. It then calls the upper layer callback -* handler set by the function XGpioPs_SetBankHandler(). The callback is called -* when an interrupt -* -* @param InstancePtr is a pointer to the XGpioPs instance. -* -* @return None. -* -* @note This function does not save and restore the processor context -* such that the user must provide this processing. -* -******************************************************************************/ -void XGpioPs_IntrHandler(XGpioPs *InstancePtr) -{ - u8 Bank; - u32 IntrStatus; - u32 IntrEnabled; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - for (Bank = 0; Bank < XGPIOPS_MAX_BANKS; Bank++) { - IntrStatus = XGpioPs_IntrGetStatus(InstancePtr, Bank); - if (IntrStatus != 0) { - IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr, - Bank); - XGpioPs_IntrClear(InstancePtr, Bank, - IntrStatus & IntrEnabled); - InstancePtr->Handler((void *)InstancePtr-> - CallBackRef, Bank, - (IntrStatus & IntrEnabled)); - } - } -} - -/*****************************************************************************/ -/** -* -* This is a stub for the status callback. The stub is here in case the upper -* layers do not set the handler. -* -* @param CallBackRef is a pointer to the upper layer callback reference -* @param Bank is the GPIO Bank in which an interrupt occurred. -* @param Status is the Interrupt status of the GPIO bank. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void StubHandler(void *CallBackRef, int Bank, u32 Status) -{ - (void) CallBackRef; - (void) Bank; - (void) Status; - - Xil_AssertVoidAlways(); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v1_02_a/src/xgpiops_selftest.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v1_02_a/src/xgpiops_selftest.c deleted file mode 100644 index f55e9dab276d53286c1172e9ec347e92947e1a60..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v1_02_a/src/xgpiops_selftest.c +++ /dev/null @@ -1,140 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xgpiops_selftest.c -* -* This file contains a diagnostic self-test function for the XGpioPs driver. -* -* Read xgpiops.h file for more information. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a sv 01/18/10 First Release -* </pre> -* -*****************************************************************************/ - -/***************************** Include Files ********************************/ - -#include "xstatus.h" -#include "xgpiops.h" - -/************************** Constant Definitions ****************************/ - - -/**************************** Type Definitions ******************************/ - -/***************** Macros (Inline Functions) Definitions ********************/ - -/************************** Variable Definitions ****************************/ - -/************************** Function Prototypes *****************************/ - -/*****************************************************************************/ -/** -* -* This function runs a self-test on the GPIO driver/device. This function -* does a register read/write test on some of the Interrupt Registers. -* -* @param InstancePtr is a pointer to the XGpioPs instance. -* -* @return -* - XST_SUCCESS if the self-test passed. -* - XST_FAILURE otherwise. -* -* -******************************************************************************/ -int XGpioPs_SelfTest(XGpioPs *InstancePtr) -{ - int Status = XST_SUCCESS; - u32 IntrEnabled; - u32 CurrentIntrType; - u32 CurrentIntrPolarity; - u32 CurrentIntrOnAny; - u32 IntrType; - u32 IntrPolarity; - u32 IntrOnAny; - u32 IntrTestValue = 0x22; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Disable the Interrupts for Bank 0 . - */ - IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr, XGPIOPS_BANK0); - XGpioPs_IntrDisable(InstancePtr, XGPIOPS_BANK0, IntrEnabled); - - /* - * Get the Current Interrupt properties for Bank 0. - * Set them to a known value, read it back and compare. - */ - XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &CurrentIntrType, - &CurrentIntrPolarity, &CurrentIntrOnAny); - - XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, IntrTestValue, - IntrTestValue, IntrTestValue); - - XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &IntrType, - &IntrPolarity, &IntrOnAny); - - if ((IntrType != IntrTestValue) && (IntrPolarity != IntrTestValue) && - (IntrOnAny != IntrTestValue)) { - - Status = XST_FAILURE; - } - - /* - * Restore the contents of all the interrupt registers modified in this - * test. - */ - XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, CurrentIntrType, - CurrentIntrPolarity, CurrentIntrOnAny); - - XGpioPs_IntrEnable(InstancePtr, XGPIOPS_BANK0, IntrEnabled); - - return Status; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v1_02_a/src/xgpiops_sinit.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v1_02_a/src/xgpiops_sinit.c deleted file mode 100644 index 9a01883a0494c02c9c5f0e76ec547e5a5c00a93e..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/gpiops_v1_02_a/src/xgpiops_sinit.c +++ /dev/null @@ -1,106 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xgpiops_sinit.c -* -* This file contains the implementation of the XGpioPs driver's static -* initialization functionality. -* -* @note None. -* -* <pre> -* -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a sv 01/15/10 First Release -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xparameters.h" -#include "xgpiops.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/************************** Variable Definitions *****************************/ -extern XGpioPs_Config XGpioPs_ConfigTable[]; - -/*****************************************************************************/ -/** -* -* This function looks for the device configuration based on the unique device -* ID. The table XGpioPs_ConfigTable[] contains the configuration information -* for each device in the system. -* -* @param DeviceId is the unique device ID of the device being looked up. -* -* @return A pointer to the configuration table entry corresponding to the -* given device ID, or NULL if no match is found. -* -* @note None. -* -******************************************************************************/ -XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId) -{ - XGpioPs_Config *CfgPtr = NULL; - u32 Index; - - for (Index = 0; Index < XPAR_XGPIOPS_NUM_INSTANCES; Index++) { - if (XGpioPs_ConfigTable[Index].DeviceId == DeviceId) { - CfgPtr = &XGpioPs_ConfigTable[Index]; - break; - } - } - - return CfgPtr; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/Makefile b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/Makefile deleted file mode 100644 index c506c25d5ec4f10386abd803cefa7601b6ee6adf..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -COMPILER= -ARCHIVER= -CP=cp -COMPILER_FLAGS= -EXTRA_COMPILER_FLAGS= -LIB=libxil.a - -CC_FLAGS = $(COMPILER_FLAGS) -ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) - -RELEASEDIR=../../../lib -INCLUDEDIR=../../../include -INCLUDES=-I./. -I${INCLUDEDIR} - -OUTS = *.o - -LIBSOURCES:=*.c -INCLUDEFILES:=*.h - -OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) - -libs: banner xiicps_libs clean - -%.o: %.c - ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< - -banner: - echo "Compiling iicps" - -xiicps_libs: ${OBJECTS} - $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} - -.PHONY: include -include: xiicps_includes - -xiicps_includes: - ${CP} ${INCLUDEFILES} ${INCLUDEDIR} - -clean: - rm -rf ${OBJECTS} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps.c deleted file mode 100644 index f96780d5b1593d76930660395bdb530f9e6c5ddd..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps.c +++ /dev/null @@ -1,326 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xiicps.c -* -* Contains implementation of required functions for the XIicPs driver. -* See xiicps.h for detailed description of the device and driver. -* -* <pre> MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------ -------- -------------------------------------------- -* 1.00a drg/jz 01/30/10 First release -* 1.00a sdm 09/21/11 Updated the InstancePtr->Options in the -* XIicPs_CfgInitialize by calling XIicPs_GetOptions. -* -* -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xiicps.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -static void StubHandler(void *CallBackRef, u32 StatusEvent); - -/************************** Variable Definitions *****************************/ - - -/*****************************************************************************/ -/** -* -* Initializes a specific XIicPs instance such that the driver is ready to use. -* -* The state of the device after initialization is: -* - Device is disabled -* - Slave mode -* -* @param InstancePtr is a pointer to the XIicPs instance. -* @param ConfigPtr is a reference to a structure containing information -* about a specific IIC device. This function initializes an -* InstancePtr object for a specific device specified by the -* contents of Config. -* @param EffectiveAddr is the device base address in the virtual memory -* address space. The caller is responsible for keeping the address -* mapping from EffectiveAddr to the device physical base address -* unchanged once this function is invoked. Unexpected errors may -* occur if the address mapping changes after this function is -* called. If address translation is not used, use -* ConfigPtr->BaseAddress for this parameter, passing the physical -* address instead. -* -* @return The return value is XST_SUCCESS if successful. -* -* @note None. -* -******************************************************************************/ -int XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config *ConfigPtr, - u32 EffectiveAddr) -{ - /* - * Assert validates the input arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(ConfigPtr != NULL); - - /* - * Set some default values. - */ - InstancePtr->Config.DeviceId = ConfigPtr->DeviceId; - InstancePtr->Config.BaseAddress = EffectiveAddr; - InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz; - InstancePtr->StatusHandler = StubHandler; - InstancePtr->CallBackRef = NULL; - - InstancePtr->IsReady = XIL_COMPONENT_IS_READY; - - /* - * Reset the IIC device to get it into its initial state. It is expected - * that device configuration will take place after this initialization - * is done, but before the device is started. - */ - XIicPs_Reset(InstancePtr); - - /* - * Keep a copy of what options this instance has. - */ - InstancePtr->Options = XIicPs_GetOptions(InstancePtr); - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* Check whether the I2C bus is busy -* -* @param InstancePtr is a pointer to the XIicPs instance. -* -* @return -* - TRUE if the bus is busy. -* - FALSE if the bus is not busy. -* -* @note None. -* -******************************************************************************/ -int XIicPs_BusIsBusy(XIicPs *InstancePtr) -{ - u32 StatusReg; - - StatusReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress, - XIICPS_SR_OFFSET); - if (StatusReg & XIICPS_SR_BA_MASK) { - return TRUE; - }else { - return FALSE; - } -} - -/*****************************************************************************/ -/** -* -* This is a stub for the status callback. The stub is here in case the upper -* layers forget to set the handler. -* -* @param CallBackRef is a pointer to the upper layer callback reference. -* @param StatusEvent is the event that just occurred. -* @param ByteCount is the number of bytes transferred up until the event -* occurred. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -static void StubHandler(void *CallBackRef, u32 StatusEvent) -{ - (void) CallBackRef; - (void) StatusEvent; - Xil_AssertVoidAlways(); -} - - -/*****************************************************************************/ -/** -* -* Aborts a transfer in progress by resetting the FIFOs. The byte counts are -* cleared. -* -* @param InstancePtr is a pointer to the XIicPs instance. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XIicPs_Abort(XIicPs *InstancePtr) -{ - u32 IntrMaskReg; - u32 IntrStatusReg; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Enter a critical section, so disable the interrupts while we clear - * the FIFO and the status register. - */ - IntrMaskReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress, - XIICPS_IMR_OFFSET); - XIicPs_WriteReg(InstancePtr->Config.BaseAddress, - XIICPS_IDR_OFFSET, XIICPS_IXR_ALL_INTR_MASK); - - /* - * Clear the FIFOs. - */ - XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET, - XIICPS_CR_CLR_FIFO_MASK); - - /* - * Read, then write the interrupt status to make sure there are no - * pending interrupts. - */ - IntrStatusReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress, - XIICPS_ISR_OFFSET); - XIicPs_WriteReg(InstancePtr->Config.BaseAddress, - XIICPS_ISR_OFFSET, IntrStatusReg); - - /* - * Restore the interrupt state. - */ - IntrMaskReg = XIICPS_IXR_ALL_INTR_MASK & (~IntrMaskReg); - XIicPs_WriteReg(InstancePtr->Config.BaseAddress, - XIICPS_IER_OFFSET, IntrMaskReg); - -} - -/*****************************************************************************/ -/** -* -* Resets the IIC device. Reset must only be called after the driver has been -* initialized. The configuration of the device after reset is the same as its -* configuration after initialization. Any data transfer that is in progress is -* aborted. -* -* The upper layer software is responsible for re-configuring (if necessary) -* and reenabling interrupts for the IIC device after the reset. -* -* @param InstancePtr is a pointer to the XIicPs instance. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XIicPs_Reset(XIicPs *InstancePtr) -{ - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Abort any transfer that is in progress. - */ - XIicPs_Abort(InstancePtr); - - /* - * Reset any values so the software state matches the hardware device. - */ - XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET, - XIICPS_CR_RESET_VALUE); - XIicPs_WriteReg(InstancePtr->Config.BaseAddress, - XIICPS_TIME_OUT_OFFSET, XIICPS_TO_RESET_VALUE); - XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_IDR_OFFSET, - XIICPS_IXR_ALL_INTR_MASK); - -} -/*****************************************************************************/ -/** -* Put more data into the transmit FIFO, number of bytes is ether expected -* number of bytes for this transfer or available space in FIFO, which ever -* is less. -* -* @param InstancePtr is a pointer to the XIicPs instance. -* -* @return Number of bytes left for this instance. -* -* @note This is function is shared by master and slave. -* -******************************************************************************/ -int TransmitFifoFill(XIicPs *InstancePtr) -{ - u8 AvailBytes; - int LoopCnt; - int NumBytesToSend; - - /* - * Determine number of bytes to write to FIFO. - */ - AvailBytes = XIICPS_FIFO_DEPTH - - XIicPs_ReadReg(InstancePtr->Config.BaseAddress, - XIICPS_TRANS_SIZE_OFFSET); - - if (InstancePtr->SendByteCount > AvailBytes) { - NumBytesToSend = AvailBytes; - } else { - NumBytesToSend = InstancePtr->SendByteCount; - } - - /* - * Fill FIFO with amount determined above. - */ - for (LoopCnt = 0; LoopCnt < NumBytesToSend; LoopCnt++) { - XIicPs_SendByte(InstancePtr); - } - - return InstancePtr->SendByteCount; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps.h deleted file mode 100644 index de89a99018a598d245faa47e42bfe8a715068c72..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps.h +++ /dev/null @@ -1,394 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xiicps.h -* -* This is an implementation of IIC driver in the PS block. The device can -* be either a master or a slave on the IIC bus. This implementation supports -* both interrupt mode transfer and polled mode transfer. Only 7-bit address -* is used in the driver, although the hardware also supports 10-bit address. -* -* IIC is a 2-wire serial interface. The master controls the clock, so it can -* regulate when it wants to send or receive data. The slave is under control of -* the master, it must respond quickly since it has no control of the clock and -* must send/receive data as fast or as slow as the master does. -* -* The higher level software must implement a higher layer protocol to inform -* the slave what to send to the master. -* -* <b>Initialization & Configuration</b> -* -* The XIicPs_Config structure is used by the driver to configure itself. This -* configuration structure is typically created by the tool-chain based on HW -* build properties. -* -* To support multiple runtime loading and initialization strategies employed by -* various operating systems, the driver instance can be initialized in the -* following way: -* -* - XIicPs_LookupConfig(DeviceId) - Use the device identifier to find -* the static configuration structure defined in xiicps_g.c. This is -* setup by the tools. For some operating systems the config structure -* will be initialized by the software and this call is not needed. -* -* - XIicPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a -* configuration structure provided by the caller. If running in a -* system with address translation, the provided virtual memory base -* address replaces the physical address in the configuration -* structure. -* -* <b>Multiple Masters</b> -* -* More than one master can exist, bus arbitration is defined in the IIC -* standard. Lost of arbitration causes arbitration loss interrupt on the device. -* -* <b>Multiple Slaves</b> -* -* Multiple slaves are supported by selecting them with unique addresses. It is -* up to the system designer to be sure all devices on the IIC bus have -* unique addresses. -* -* <b>Addressing</b> -* -* The IIC hardware can use 7 or 10 bit addresses. The driver provides the -* ability to control which address size is sent in messages as a master to a -* slave device. -* -* <b>FIFO Size </b> -* The hardware FIFO is 32 bytes deep. The user must know the limitations of -* other IIC devices on the bus. Some are only able to receive a limited number -* of bytes in a single transfer. -* -* <b>Data Rates</b> -* -* The data rate is set by values in the control register. The formula for -* determining the correct register values is: -* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1)) -* -* When the device is configured as a slave, the slck setting controls the -* sample rate and so must be set to be at least as fast as the fastest scl -* expected to be seen in the system. -* -* <b>Polled Mode Operation</b> -* -* This driver supports polled mode transfers. -* -* <b>Interrupts</b> -* -* The user must connect the interrupt handler of the driver, -* XIicPs_InterruptHandler to an interrupt system such that it will be called -* when an interrupt occurs. This function does not save and restore the -* processor context such that the user must provide this processing. -* -* The driver handles the following interrupts: -* - Transfer complete -* - More Data -* - Transfer not Acknowledged -* - Transfer Time out -* - Monitored slave ready - master mode only -* - Receive Overflow -* - Transmit FIFO overflow -* - Receive FIFO underflow -* - Arbitration lost -* -* <b>Bus Busy</b> -* -* Bus busy is checked before the setup of a master mode device, to avoid -* unnecessary arbitration loss interrupt. -* -* <b>RTOS Independence</b> -* -* This driver is intended to be RTOS and processor independent. It works with -* physical addresses only. Any needs for dynamic memory management, threads or -* thread mutual exclusion, virtual memory, or cache control must be satisfied by -* the layer above this driver. -* -* @note -* . Less than FIFO size transfers work for both 100 KHz and 400 KHz. -* . Larger than FIFO size interrupt-driven transfers are not reliable on -* busy systems where interrupt latency is high. -* . Larger than FIFO size interrupt-driven transfers are not reliable for -* data rate of 400 KHz. -* . Larger than FIFO size polled mode transfers work reliably. -* -* <pre> MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------ -------- ----------------------------------------------- -* 1.00a drg/jz 01/30/08 First release -* 1.00a sdm 09/21/11 Fixed an issue in the XIicPs_SetOptions and -* XIicPs_ClearOptions where the InstancePtr->Options -* was not updated correctly. -* Updated the InstancePtr->Options in the -* XIicPs_CfgInitialize by calling XIicPs_GetOptions. -* Updated the XIicPs_SetupMaster to not check for -* Bus Busy condition when the Hold Bit is set. -* Removed some unused variables. -* 1.01a sg 03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a -* check for transfer completion is added, which indicates -* the completion of current transfer. -* 1.02a sg 08/29/12 Updated the logic to arrive at the best divisors -* to achieve I2C clock with minimum error for -* CR #674195 -* 1.03a hk 05/04/13 Initialized BestDivA and BestDivB to 0. -* This is fix for CR#704398 to remove warning. -* -* </pre> -* -******************************************************************************/ - -#ifndef XIICPS_H /* prevent circular inclusions */ -#define XIICPS_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xstatus.h" -#include "xiicps_hw.h" - -/************************** Constant Definitions *****************************/ - -/** @name Configuration options - * - * The following options may be specified or retrieved for the device and - * enable/disable additional features of the IIC. Each of the options - * are bit fields, so more than one may be specified. - * - * @{ - */ -#define XIICPS_7_BIT_ADDR_OPTION 0x01 /**< 7-bit address mode */ -#define XIICPS_10_BIT_ADDR_OPTION 0x02 /**< 10-bit address mode */ -#define XIICPS_SLAVE_MON_OPTION 0x04 /**< Slave monitor mode */ -#define XIICPS_REP_START_OPTION 0x08 /**< Repeated Start */ -/*@}*/ - -/** @name Callback events - * - * These constants specify the handler events that are passed to an application - * event handler from the driver. These constants are bit masks such that - * more than one event can be passed to the handler. - * - * @{ - */ -#define XIICPS_EVENT_COMPLETE_SEND 0x0001 /**< Transmit Complete Event*/ -#define XIICPS_EVENT_COMPLETE_RECV 0x0002 /**< Receive Complete Event*/ -#define XIICPS_EVENT_TIME_OUT 0x0004 /**< Transfer timed out */ -#define XIICPS_EVENT_ERROR 0x0008 /**< Receive error */ -#define XIICPS_EVENT_ARB_LOST 0x0010 /**< Arbitration lost */ -#define XIICPS_EVENT_NACK 0x0020 /**< NACK Received */ -#define XIICPS_EVENT_SLAVE_RDY 0x0040 /**< Slave ready */ -#define XIICPS_EVENT_RX_OVR 0x0080 /**< RX overflow */ -#define XIICPS_EVENT_TX_OVR 0x0100 /**< TX overflow */ -#define XIICPS_EVENT_RX_UNF 0x0200 /**< RX underflow */ -/*@}*/ - -/** @name Role constants - * - * These constants are used to pass into the device setup routines to - * set up the device according to transfer direction. - */ -#define SENDING_ROLE 1 /**< Transfer direction is sending */ -#define RECVING_ROLE 0 /**< Transfer direction is receiving */ - - -/**************************** Type Definitions *******************************/ - -/** -* The handler data type allows the user to define a callback function to -* respond to interrupt events in the system. This function is executed -* in interrupt context, so amount of processing should be minimized. -* -* @param CallBackRef is the callback reference passed in by the upper -* layer when setting the callback functions, and passed back to -* the upper layer when the callback is invoked. Its type is -* not important to the driver, so it is a void pointer. -* @param StatusEvent indicates one or more status events that occurred. -*/ -typedef void (*XIicPs_IntrHandler) (void *CallBackRef, u32 StatusEvent); - -/** - * This typedef contains configuration information for the device. - */ -typedef struct { - u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddress; /**< Base address of the device */ - u32 InputClockHz; /**< Input clock frequency */ -} XIicPs_Config; - -/** - * The XIicPs driver instance data. The user is required to allocate a - * variable of this type for each IIC device in the system. A pointer - * to a variable of this type is then passed to the driver API functions. - */ -typedef struct { - XIicPs_Config Config; /* Configuration structure */ - u32 IsReady; /* Device is initialized and ready */ - u32 Options; /* Options set in the device */ - - u8 *SendBufferPtr; /* Pointer to send buffer */ - u8 *RecvBufferPtr; /* Pointer to recv buffer */ - int SendByteCount; /* Number of bytes still expected to send */ - int RecvByteCount; /* Number of bytes still expected to receive */ - - XIicPs_IntrHandler StatusHandler; /* Event handler function */ - void *CallBackRef; /* Callback reference for event handler */ -} XIicPs; - -/***************** Macros (Inline Functions) Definitions *********************/ -/****************************************************************************/ -/* -* -* Place one byte into the transmit FIFO. -* -* @param InstancePtr is the instance of IIC -* -* @return None. -* -* @note C-Style signature: -* void XIicPs_SendByte(XIicPs *InstancePtr) -* -*****************************************************************************/ -#define XIicPs_SendByte(InstancePtr) \ -{ \ - XIicPs_Out32((InstancePtr)->Config.BaseAddress \ - + XIICPS_DATA_OFFSET, \ - *(InstancePtr)->SendBufferPtr ++); \ - (InstancePtr)->SendByteCount --; \ -} - -/****************************************************************************/ -/* -* -* Receive one byte from FIFO. -* -* @param InstancePtr is the instance of IIC -* -* @return None. -* -* @note C-Style signature: -* u8 XIicPs_RecvByte(XIicPs *InstancePtr) -* -*****************************************************************************/ -#define XIicPs_RecvByte(InstancePtr) \ -{ \ - *(InstancePtr)->RecvBufferPtr ++ = \ - (u8)XIicPs_In32((InstancePtr)->Config.BaseAddress \ - + XIICPS_DATA_OFFSET); \ - (InstancePtr)->RecvByteCount --; \ -} - -/************************** Function Prototypes ******************************/ - -/* - * Function for configuration lookup, in xiicps_sinit.c - */ -XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId); - -/* - * Functions for general setup, in xiicps.c - */ -int XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config * Config, - u32 EffectiveAddr); - -void XIicPs_Abort(XIicPs *InstancePtr); -void XIicPs_Reset(XIicPs *InstancePtr); - -int XIicPs_BusIsBusy(XIicPs *InstancePtr); - -/* - * Functions for interrupts, in xiicps_intr.c - */ -void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef, - XIicPs_IntrHandler FuncPtr); - -/* - * Functions for device as master, in xiicps_master.c - */ -void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount, - u16 SlaveAddr); -void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount, - u16 SlaveAddr); -int XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount, - u16 SlaveAddr); -int XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount, - u16 SlaveAddr); -void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr); -void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr); -void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr); - -/* - * Functions for device as slave, in xiicps_slave.c - */ -void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr); -void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount); -void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount); -int XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount); -int XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount); -void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr); - -/* - * Functions for selftest, in xiicps_selftest.c - */ -int XIicPs_SelfTest(XIicPs *InstancePtr); - -/* - * Functions for setting and getting data rate, in xiicps_options.c - */ -int XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options); -int XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options); -u32 XIicPs_GetOptions(XIicPs *InstancePtr); - -int XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz); -u32 XIicPs_GetSClk(XIicPs *InstancePtr); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps_g.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps_g.c deleted file mode 100644 index 0f7edcfd69a30adedb9e802894a300cb468d4b6b..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps_g.c +++ /dev/null @@ -1,31 +0,0 @@ - -/******************************************************************* -* -* CAUTION: This file is automatically generated by libgen. -* Version: Xilinx EDK 14.7 EDK_P.20131013 -* DO NOT EDIT. -* -* Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. - -* -* Description: Driver configuration -* -*******************************************************************/ - -#include "xparameters.h" -#include "xiicps.h" - -/* -* The configuration table for devices -*/ - -XIicPs_Config XIicPs_ConfigTable[] = -{ - { - XPAR_PS7_I2C_0_DEVICE_ID, - XPAR_PS7_I2C_0_BASEADDR, - XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ - } -}; - - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps_hw.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps_hw.c deleted file mode 100644 index 03c9bffb43b905dd3c27513c7c981f5f3c63f5f4..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps_hw.c +++ /dev/null @@ -1,116 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xiicps_hw.c -* -* Contains implementation of required functions for providing the reset sequence -* to the i2c interface -* -* <pre> MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------ -------- -------------------------------------------- -* 1.04a kpc 11/07/13 First release -* -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xiicps_hw.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/************************** Variable Definitions *****************************/ -/*****************************************************************************/ -/** -* This function perform the reset sequence to the given I2c interface by -* configuring the appropriate control bits in the I2c specifc registers -* the i2cps reset squence involves the following steps -* Disable all the interuupts -* Clear the status -* Clear FIFO's and disable hold bit -* Clear the line status -* Update relevant config registers with reset values -* -* @param BaseAddress of the interface -* -* @return N/A -* -* @note -* This function will not modify the slcr registers that are relavant for -* I2c controller -******************************************************************************/ -void XIicPs_ResetHw(u32 BaseAddress) -{ - u32 RegVal; - - /* Disable all the interrupts */ - XIicPs_WriteReg(BaseAddress, XIICPS_IDR_OFFSET, XIICPS_IXR_ALL_INTR_MASK); - /* Clear the interrupt status */ - RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_ISR_OFFSET); - XIicPs_WriteReg(BaseAddress, XIICPS_ISR_OFFSET, RegVal); - /* Clear the hold bit,master enable bit and ack bit */ - RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_CR_OFFSET); - RegVal &= ~(XIICPS_CR_HOLD_MASK|XIICPS_CR_MS_MASK|XIICPS_CR_ACKEN_MASK); - /* Clear the fifos */ - RegVal |= XIICPS_CR_CLR_FIFO_MASK; - XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, RegVal); - /* Clear the timeout register */ - XIicPs_WriteReg(BaseAddress, XIICPS_TIME_OUT_OFFSET, 0x0); - /* Clear the transfer size register */ - XIicPs_WriteReg(BaseAddress, XIICPS_TRANS_SIZE_OFFSET, 0x0); - /* Clear the status register */ - RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_SR_OFFSET); - XIicPs_WriteReg(BaseAddress, XIICPS_SR_OFFSET, RegVal); - /* Update the configuraqtion register with reset value */ - XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, 0x0); -} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps_hw.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps_hw.h deleted file mode 100644 index 69b71ce09c70dc9e5c0c4ba3147b2f9a5db45523..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps_hw.h +++ /dev/null @@ -1,388 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xiicps_hw.h -* -* This header file contains the hardware definition for an IIC device. -* It includes register definitions and interface functions to read/write -* the registers. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------ -------- ----------------------------------------------- -* 1.00a drg/jz 01/30/10 First release -* 1.04a kpc 11/07/13 Added function prototype. -* </pre> -* -******************************************************************************/ -#ifndef XIICPS_HW_H /* prevent circular inclusions */ -#define XIICPS_HW_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xil_io.h" - -/************************** Constant Definitions *****************************/ - -/** @name Register Map - * - * Register offsets for the IIC. - * @{ - */ -#define XIICPS_CR_OFFSET 0x00 /**< 32-bit Control */ -#define XIICPS_SR_OFFSET 0x04 /**< Status */ -#define XIICPS_ADDR_OFFSET 0x08 /**< IIC Address */ -#define XIICPS_DATA_OFFSET 0x0C /**< IIC FIFO Data */ -#define XIICPS_ISR_OFFSET 0x10 /**< Interrupt Status */ -#define XIICPS_TRANS_SIZE_OFFSET 0x14 /**< Transfer Size */ -#define XIICPS_SLV_PAUSE_OFFSET 0x18 /**< Slave monitor pause */ -#define XIICPS_TIME_OUT_OFFSET 0x1C /**< Time Out */ -#define XIICPS_IMR_OFFSET 0x20 /**< Interrupt Enabled Mask */ -#define XIICPS_IER_OFFSET 0x24 /**< Interrupt Enable */ -#define XIICPS_IDR_OFFSET 0x28 /**< Interrupt Disable */ -/* @} */ - -/** @name Control Register - * - * This register contains various control bits that - * affects the operation of the IIC controller. Read/Write. - * @{ - */ - -#define XIICPS_CR_DIV_A_MASK 0x0000C000 /**< Clock Divisor A */ -#define XIICPS_CR_DIV_A_SHIFT 14 /**< Clock Divisor A shift */ -#define XIICPS_DIV_A_MAX 4 /**< Maximum value of Divisor A */ -#define XIICPS_CR_DIV_B_MASK 0x00003F00 /**< Clock Divisor B */ -#define XIICPS_CR_DIV_B_SHIFT 8 /**< Clock Divisor B shift */ -#define XIICPS_CR_CLR_FIFO_MASK 0x00000040 /**< Clear FIFO, auto clears*/ -#define XIICPS_CR_SLVMON_MASK 0x00000020 /**< Slave monitor mode */ -#define XIICPS_CR_HOLD_MASK 0x00000010 /**< Hold bus 1=Hold scl, - 0=terminate transfer */ -#define XIICPS_CR_ACKEN_MASK 0x00000008 /**< Enable TX of ACK when - Master receiver*/ -#define XIICPS_CR_NEA_MASK 0x00000004 /**< Addressing Mode 1=7 bit, - 0=10 bit */ -#define XIICPS_CR_MS_MASK 0x00000002 /**< Master mode bit 1=Master, - 0=Slave */ -#define XIICPS_CR_RD_WR_MASK 0x00000001 /**< Read or Write Master - transfer 0=Transmitter, - 1=Receiver*/ -#define XIICPS_CR_RESET_VALUE 0 /**< Reset value of the Control - register */ -/* @} */ - -/** @name IIC Status Register - * - * This register is used to indicate status of the IIC controller. Read only - * @{ - */ -#define XIICPS_SR_BA_MASK 0x00000100 /**< Bus Active Mask */ -#define XIICPS_SR_RXOVF_MASK 0x00000080 /**< Receiver Overflow Mask */ -#define XIICPS_SR_TXDV_MASK 0x00000040 /**< Transmit Data Valid Mask */ -#define XIICPS_SR_RXDV_MASK 0x00000020 /**< Receiver Data Valid Mask */ -#define XIICPS_SR_RXRW_MASK 0x00000008 /**< Receive read/write Mask */ -/* @} */ - -/** @name IIC Address Register - * - * Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0]. - * A write access to this register always initiates a transfer if the IIC is in - * master mode. Read/Write - * @{ - */ -#define XIICPS_ADDR_MASK 0x000003FF /**< IIC Address Mask */ -/* @} */ - -/** @name IIC Data Register - * - * When written to, the data register sets data to transmit. When read from, the - * data register reads the last received byte of data. Read/Write - * @{ - */ -#define XIICPS_DATA_MASK 0x000000FF /**< IIC Data Mask */ -/* @} */ - -/** @name IIC Interrupt Registers - * - * <b>IIC Interrupt Status Register</b> - * - * This register holds the interrupt status flags for the IIC controller. Some - * of the flags are level triggered - * - i.e. are set as long as the interrupt condition exists. Other flags are - * edge triggered, which means they are set one the interrupt condition occurs - * then remain set until they are cleared by software. - * The interrupts are cleared by writing a one to the interrupt bit position - * in the Interrupt Status Register. Read/Write. - * - * <b>IIC Interrupt Enable Register</b> - * - * This register is used to enable interrupt sources for the IIC controller. - * Writing a '1' to a bit in this register clears the corresponding bit in the - * IIC Interrupt Mask register. Write only. - * - * <b>IIC Interrupt Disable Register </b> - * - * This register is used to disable interrupt sources for the IIC controller. - * Writing a '1' to a bit in this register sets the corresponding bit in the - * IIC Interrupt Mask register. Write only. - * - * <b>IIC Interrupt Mask Register</b> - * - * This register shows the enabled/disabled status of each IIC controller - * interrupt source. A bit set to 1 will ignore the corresponding interrupt in - * the status register. A bit set to 0 means the interrupt is enabled. - * All mask bits are set and all interrupts are disabled after reset. Read only. - * - * All four registers have the same bit definitions. They are only defined once - * for each of the Interrupt Enable Register, Interrupt Disable Register, - * Interrupt Mask Register, and Interrupt Status Register - * @{ - */ - -#define XIICPS_IXR_ARB_LOST_MASK 0x00000200 /**< Arbitration Lost Interrupt - mask */ -#define XIICPS_IXR_RX_UNF_MASK 0x00000080 /**< FIFO Recieve Underflow - Interrupt mask */ -#define XIICPS_IXR_TX_OVR_MASK 0x00000040 /**< Transmit Overflow - Interrupt mask */ -#define XIICPS_IXR_RX_OVR_MASK 0x00000020 /**< Receive Overflow Interrupt - mask */ -#define XIICPS_IXR_SLV_RDY_MASK 0x00000010 /**< Monitored Slave Ready - Interrupt mask */ -#define XIICPS_IXR_TO_MASK 0x00000008 /**< Transfer Time Out - Interrupt mask */ -#define XIICPS_IXR_NACK_MASK 0x00000004 /**< NACK Interrupt mask */ -#define XIICPS_IXR_DATA_MASK 0x00000002 /**< Data Interrupt mask */ -#define XIICPS_IXR_COMP_MASK 0x00000001 /**< Transfer Complete - Interrupt mask */ -#define XIICPS_IXR_DEFAULT_MASK 0x000002FF /**< Default ISR Mask */ -#define XIICPS_IXR_ALL_INTR_MASK 0x000002FF /**< All ISR Mask */ -/* @} */ - - -/** @name IIC Transfer Size Register -* -* The register's meaning varies according to the operating mode as follows: -* - Master transmitter mode: number of data bytes still not transmitted minus -* one -* - Master receiver mode: number of data bytes that are still expected to be -* received -* - Slave transmitter mode: number of bytes remaining in the FIFO after the -* master terminates the transfer -* - Slave receiver mode: number of valid data bytes in the FIFO -* -* This register is cleared if CLR_FIFO bit in the control register is set. -* Read/Write -* @{ -*/ -#define XIICPS_TRANS_SIZE_MASK 0x0000003F /**< IIC Transfer Size Mask */ -#define XIICPS_FIFO_DEPTH 16 /**< Number of bytes in the FIFO */ -#define XIICPS_DATA_INTR_DEPTH 14 /**< Number of bytes at DATA intr */ -/* @} */ - - -/** @name IIC Slave Monitor Pause Register -* -* This register is associated with the slave monitor mode of the I2C interface. -* It is meaningful only when the module is in master mode and bit SLVMON in the -* control register is set. -* -* This register defines the pause interval between consecutive attempts to -* address the slave once a write to an I2C address register is done by the -* host. It represents the number of sclk cycles minus one between two attempts. -* -* The reset value of the register is 0, which results in the master repeatedly -* trying to access the slave immediately after unsuccessful attempt. -* Read/Write -* @{ -*/ -#define XIICPS_SLV_PAUSE_MASK 0x0000000F /**< Slave monitor pause mask */ -/* @} */ - - -/** @name IIC Time Out Register -* -* The value of time out register represents the time out interval in number of -* sclk cycles minus one. -* -* When the accessed slave holds the sclk line low for longer than the time out -* period, thus prohibiting the I2C interface in master mode to complete the -* current transfer, an interrupt is generated and TO interrupt flag is set. -* -* The reset value of the register is 0x1f. -* Read/Write -* @{ - */ -#define XIICPS_TIME_OUT_MASK 0x000000FF /**< IIC Time Out mask */ -#define XIICPS_TO_RESET_VALUE 0x0000001F /**< IIC Time Out reset value */ -/* @} */ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -#define XIicPs_In32 Xil_In32 -#define XIicPs_Out32 Xil_Out32 - -/****************************************************************************/ -/** -* Read an IIC register. -* -* @param BaseAddress contains the base address of the device. -* @param RegOffset contains the offset from the 1st register of the -* device to select the specific register. -* -* @return The value read from the register. -* -* @note C-Style signature: -* u32 XIicPs_ReadReg(u32 BaseAddress. int RegOffset) -* -******************************************************************************/ -#define XIicPs_ReadReg(BaseAddress, RegOffset) \ - XIicPs_In32((BaseAddress) + (RegOffset)) - -/***************************************************************************/ -/** -* Write an IIC register. -* -* @param BaseAddress contains the base address of the device. -* @param RegOffset contains the offset from the 1st register of the -* device to select the specific register. -* @param RegisterValue is the value to be written to the register. -* -* @return None. -* -* @note C-Style signature: -* void XIicPs_WriteReg(u32 BaseAddress, int RegOffset, u32 RegisterValue) -* -******************************************************************************/ -#define XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ - XIicPs_Out32((BaseAddress) + (RegOffset), (RegisterValue)) - -/***************************************************************************/ -/** -* Read the interrupt enable register. -* -* @param BaseAddress contains the base address of the device. -* -* @return Current bit mask that represents currently enabled interrupts. -* -* @note C-Style signature: -* u32 XIicPs_ReadIER(u32 BaseAddress) -* -******************************************************************************/ -#define XIicPs_ReadIER(BaseAddress) \ - XIicPs_ReadReg((BaseAddress), XIICPS_IER_OFFSET) - -/***************************************************************************/ -/** -* Write to the interrupt enable register. -* -* @param BaseAddress contains the base address of the device. -* -* @param IntrMask is the interrupts to be enabled. -* -* @return None. -* -* @note C-Style signature: -* void XIicPs_EnabledInterrupts(u32 BaseAddress, u32 IntrMask) -* -******************************************************************************/ -#define XIicPs_EnableInterrupts(BaseAddress, IntrMask) \ - XIicPs_WriteReg((BaseAddress), XIICPS_IER_OFFSET, (IntrMask)) - -/***************************************************************************/ -/** -* Disable all interrupts. -* -* @param BaseAddress contains the base address of the device. -* -* @return None. -* -* @note C-Style signature: -* void XIicPs_DisableAllInterrupts(u32 BaseAddress) -* -******************************************************************************/ -#define XIicPs_DisableAllInterrupts(BaseAddress) \ - XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \ - XIICPS_IXR_ALL_INTR_MASK) - -/***************************************************************************/ -/** -* Disable selected interrupts. -* -* @param BaseAddress contains the base address of the device. -* -* @param IntrMask is the interrupts to be disabled. -* -* @return None. -* -* @note C-Style signature: -* void XIicPs_DisableInterrupts(u32 BaseAddress, u32 IntrMask) -* -******************************************************************************/ -#define XIicPs_DisableInterrupts(BaseAddress, IntrMask) \ - XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \ - (IntrMask)) - -/************************** Variable Definitions *****************************/ - -/************************** Function Prototypes ******************************/ -/* - * Perform reset operation to the I2c interface - */ -void XIicPs_ResetHw(u32 BaseAddr); -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps_intr.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps_intr.c deleted file mode 100644 index 1dfeb9aba2aa16719686f2effc3eb377f88325be..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps_intr.c +++ /dev/null @@ -1,106 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xiicps_intr.c -* -* Contains functions of the XIicPs driver for interrupt-driven transfers. -* See xiicps.h for a detailed description of the device and driver. -* -* <pre> MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------ -------- ----------------------------------------------- -* 1.00a drg/jz 01/30/10 First release -* -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xiicps.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/************************* Variable Definitions *****************************/ - -/*****************************************************************************/ -/** -* -* This function sets the status callback function, the status handler, which the -* driver calls when it encounters conditions that should be reported to the -* higher layer software. The handler executes in an interrupt context, so -* the amount of processing should be minimized -* -* Refer to the xiicps.h file for a list of the Callback events. The events are -* defined to start with XIICPS_EVENT_*. -* -* @param InstancePtr is a pointer to the XIicPs instance. -* @param CallBackRef is the upper layer callback reference passed back -* when the callback function is invoked. -* @param FuncPtr is the pointer to the callback function. -* -* @return None. -* -* @note -* -* The handler is called within interrupt context, so it should finish its -* work quickly. -* -******************************************************************************/ -void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef, - XIicPs_IntrHandler FuncPtr) -{ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(FuncPtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - InstancePtr->StatusHandler = FuncPtr; - InstancePtr->CallBackRef = CallBackRef; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps_master.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps_master.c deleted file mode 100644 index 50da8752ec013eabc971b98a8a9a9f4e30761b02..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps_master.c +++ /dev/null @@ -1,876 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xiicps_master.c -* -* Handles master mode transfers. -* -* <pre> MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- --------------------------------------------- -* 1.00a jz 01/30/10 First release -* 1.00a sdm 09/21/11 Updated the XIicPs_SetupMaster to not check for -* Bus Busy condition when the Hold Bit is set. -* 1.01a sg 03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a -* check for transfer completion is added, which indicates - the completion of current transfer. -* -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xiicps.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ -int TransmitFifoFill(XIicPs *InstancePtr); - -static int XIicPs_SetupMaster(XIicPs *InstancePtr, int Role); -static void MasterSendData(XIicPs *InstancePtr); - -/************************* Variable Definitions *****************************/ - -/*****************************************************************************/ -/** -* This function initiates an interrupt-driven send in master mode. -* -* It tries to send the first FIFO-full of data, then lets the interrupt -* handler to handle the rest of the data if there is any. -* -* @param InstancePtr is a pointer to the XIicPs instance. -* @param MsgPtr is the pointer to the send buffer. -* @param ByteCount is the number of bytes to be sent. -* @param SlaveAddr is the address of the slave we are sending to. -* -* @return None. -* -* @note This send routine is for interrupt-driven transfer only. -* - ****************************************************************************/ -void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount, - u16 SlaveAddr) -{ - u32 BaseAddr; - - /* - * Assert validates the input arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(MsgPtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr); - - - BaseAddr = InstancePtr->Config.BaseAddress; - InstancePtr->SendBufferPtr = MsgPtr; - InstancePtr->SendByteCount = ByteCount; - InstancePtr->RecvBufferPtr = NULL; - - /* - * Setup as a master sending role. - */ - XIicPs_SetupMaster(InstancePtr, SENDING_ROLE); - - /* - * Set repeated start if sending more than FIFO of data. - */ - if (ByteCount > XIICPS_FIFO_DEPTH) { - XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, - XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) | - XIICPS_CR_HOLD_MASK); - } - - /* - * Do the address transfer to notify the slave. - */ - XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr); - - TransmitFifoFill(InstancePtr); - - XIicPs_EnableInterrupts(BaseAddr, - XIICPS_IXR_NACK_MASK | XIICPS_IXR_TO_MASK | - XIICPS_IXR_COMP_MASK | XIICPS_IXR_ARB_LOST_MASK); -} - -/*****************************************************************************/ -/** -* This function initiates an interrupt-driven receive in master mode. -* -* It sets the transfer size register so the slave can send data to us. -* The rest of the work is managed by interrupt handler. -* -* @param InstancePtr is a pointer to the XIicPs instance. -* @param MsgPtr is the pointer to the receive buffer. -* @param ByteCount is the number of bytes to be received. -* @param SlaveAddr is the address of the slave we are receiving from. -* -* @return None. -* -* @note This receive routine is for interrupt-driven transfer only. -* -****************************************************************************/ -void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount, - u16 SlaveAddr) -{ - u32 BaseAddr; - - /* - * Assert validates the input arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(MsgPtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr); - - BaseAddr = InstancePtr->Config.BaseAddress; - InstancePtr->RecvBufferPtr = MsgPtr; - InstancePtr->RecvByteCount = ByteCount; - InstancePtr->SendBufferPtr = NULL; - - /* - * Initialize for a master receiving role. - */ - XIicPs_SetupMaster(InstancePtr, RECVING_ROLE); - - XIicPs_EnableInterrupts(BaseAddr, - XIICPS_IXR_NACK_MASK | XIICPS_IXR_TO_MASK | - XIICPS_IXR_DATA_MASK |XIICPS_IXR_RX_OVR_MASK | - XIICPS_IXR_COMP_MASK | XIICPS_IXR_ARB_LOST_MASK); - - /* - * Do the address transfer to signal the slave. - */ - XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr); - - /* - * Setup the transfer size register so the slave knows how much - * to send to us. - */ - if (ByteCount > XIICPS_FIFO_DEPTH) { - XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET, - XIICPS_FIFO_DEPTH); - } else { - XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET, - ByteCount); - } -} - -/*****************************************************************************/ -/** -* This function initiates a polled mode send in master mode. -* -* It sends data to the FIFO and waits for the slave to pick them up. -* If slave fails to remove data from FIFO, the send fails with -* time out. -* -* @param InstancePtr is a pointer to the XIicPs instance. -* @param MsgPtr is the pointer to the send buffer. -* @param ByteCount is the number of bytes to be sent. -* @param SlaveAddr is the address of the slave we are sending to. -* -* @return -* - XST_SUCCESS if everything went well. -* - XST_FAILURE if timed out. -* -* @note This send routine is for polled mode transfer only. -* -****************************************************************************/ -int XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, - int ByteCount, u16 SlaveAddr) -{ - u32 IntrStatusReg; - u32 StatusReg; - u32 BaseAddr; - u32 Intrs; - - /* - * Assert validates the input arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(MsgPtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr); - - BaseAddr = InstancePtr->Config.BaseAddress; - InstancePtr->SendBufferPtr = MsgPtr; - InstancePtr->SendByteCount = ByteCount; - - XIicPs_SetupMaster(InstancePtr, SENDING_ROLE); - - XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr); - - /* - * Intrs keeps all the error-related interrupts. - */ - Intrs = XIICPS_IXR_ARB_LOST_MASK | XIICPS_IXR_TX_OVR_MASK | - XIICPS_IXR_TO_MASK | XIICPS_IXR_NACK_MASK; - - /* - * Clear the interrupt status register before use it to monitor. - */ - IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET); - XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg); - - /* - * Transmit first FIFO full of data. - */ - TransmitFifoFill(InstancePtr); - - IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET); - - /* - * Continue sending as long as there is more data and - * there are no errors. - */ - while ((InstancePtr->SendByteCount > 0) && - ((IntrStatusReg & Intrs) == 0)) { - StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET); - - /* - * Wait until transmit FIFO is empty. - */ - if ((StatusReg & XIICPS_SR_TXDV_MASK) != 0) { - IntrStatusReg = XIicPs_ReadReg(BaseAddr, - XIICPS_ISR_OFFSET); - continue; - } - - /* - * Send more data out through transmit FIFO. - */ - TransmitFifoFill(InstancePtr); - } - - /* - * Check for completion of transfer. - */ - while ((XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET) & - XIICPS_IXR_COMP_MASK) != XIICPS_IXR_COMP_MASK); - - /* - * If there is an error, tell the caller. - */ - if (IntrStatusReg & Intrs) { - return XST_FAILURE; - } - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* This function initiates a polled mode receive in master mode. -* -* It repeatedly sets the transfer size register so the slave can -* send data to us. It polls the data register for data to come in. -* If slave fails to send us data, it fails with time out. -* -* @param InstancePtr is a pointer to the XIicPs instance. -* @param MsgPtr is the pointer to the receive buffer. -* @param ByteCount is the number of bytes to be received. -* @param SlaveAddr is the address of the slave we are receiving from. -* -* @return -* - XST_SUCCESS if everything went well. -* - XST_FAILURE if timed out. -* -* @note This receive routine is for polled mode transfer only. -* -****************************************************************************/ -int XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, - int ByteCount, u16 SlaveAddr) -{ - u32 IntrStatusReg; - u32 Intrs; - u32 StatusReg; - u32 BaseAddr; - int BytesToRecv; - int BytesToRead; - int TransSize; - int Tmp; - - /* - * Assert validates the input arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(MsgPtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr); - - BaseAddr = InstancePtr->Config.BaseAddress; - InstancePtr->RecvBufferPtr = MsgPtr; - InstancePtr->RecvByteCount = ByteCount; - - XIicPs_SetupMaster(InstancePtr, RECVING_ROLE); - - XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr); - - /* - * Intrs keeps all the error-related interrupts. - */ - Intrs = XIICPS_IXR_ARB_LOST_MASK | XIICPS_IXR_RX_OVR_MASK | - XIICPS_IXR_RX_UNF_MASK | XIICPS_IXR_TO_MASK | - XIICPS_IXR_NACK_MASK; - - /* - * Clear the interrupt status register before use it to monitor. - */ - IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET); - XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg); - - /* - * Set up the transfer size register so the slave knows how much - * to send to us. - */ - if (ByteCount > XIICPS_FIFO_DEPTH) { - XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET, - XIICPS_FIFO_DEPTH); - }else { - XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET, - ByteCount); - } - - /* - * Pull the interrupt status register to find the errors. - */ - IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET); - while ((InstancePtr->RecvByteCount > 0) && - ((IntrStatusReg & Intrs) == 0)) { - StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET); - - /* - * If there is no data in the FIFO, check the interrupt - * status register for error, and continue. - */ - if ((StatusReg & XIICPS_SR_RXDV_MASK) == 0) { - IntrStatusReg = XIicPs_ReadReg(BaseAddr, - XIICPS_ISR_OFFSET); - continue; - } - - /* - * The transfer size register shows how much more data slave - * needs to send to us. - */ - TransSize = XIicPs_ReadReg(BaseAddr, - XIICPS_TRANS_SIZE_OFFSET); - - BytesToRead = InstancePtr->RecvByteCount; - - /* - * If expected number of bytes is greater than FIFO size, - * the master needs to wait for data comes in and set the - * transfer size register for slave to send more. - */ - if (InstancePtr->RecvByteCount > XIICPS_FIFO_DEPTH) { - /* wait slave to send data */ - while ((TransSize > 2) && - ((IntrStatusReg & Intrs) == 0)) { - TransSize = XIicPs_ReadReg(BaseAddr, - XIICPS_TRANS_SIZE_OFFSET); - IntrStatusReg = XIicPs_ReadReg(BaseAddr, - XIICPS_ISR_OFFSET); - } - - /* - * If timeout happened, it is an error. - */ - if (IntrStatusReg & XIICPS_IXR_TO_MASK) { - return XST_FAILURE; - } - TransSize = XIicPs_ReadReg(BaseAddr, - XIICPS_TRANS_SIZE_OFFSET); - - /* - * Take trans size into account of how many more should - * be received. - */ - BytesToRecv = InstancePtr->RecvByteCount - - XIICPS_FIFO_DEPTH + TransSize; - - /* Tell slave to send more to us */ - if (BytesToRecv > XIICPS_FIFO_DEPTH) { - XIicPs_WriteReg(BaseAddr, - XIICPS_TRANS_SIZE_OFFSET, - XIICPS_FIFO_DEPTH); - } else{ - XIicPs_WriteReg(BaseAddr, - XIICPS_TRANS_SIZE_OFFSET, BytesToRecv); - } - - BytesToRead = XIICPS_FIFO_DEPTH - TransSize; - } - - Tmp = 0; - IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET); - while ((Tmp < BytesToRead) && - ((IntrStatusReg & Intrs) == 0)) { - StatusReg = XIicPs_ReadReg(BaseAddr, - XIICPS_SR_OFFSET); - IntrStatusReg = XIicPs_ReadReg(BaseAddr, - XIICPS_ISR_OFFSET); - - if ((StatusReg & XIICPS_SR_RXDV_MASK) == 0) { - /* No data in fifo */ - continue; - } - XIicPs_RecvByte(InstancePtr); - Tmp ++; - } - } - - if (IntrStatusReg & Intrs) { - return XST_FAILURE; - } - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* This function enables the slave monitor mode. -* -* It enables slave monitor in the control register and enables -* slave ready interrupt. It then does an address transfer to slave. -* Interrupt handler will signal the caller if slave responds to -* the address transfer. -* -* @param InstancePtr is a pointer to the XIicPs instance. -* @param SlaveAddr is the address of the slave we want to contact. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr) -{ - u32 BaseAddr; - - Xil_AssertVoid(InstancePtr != NULL); - - BaseAddr = InstancePtr->Config.BaseAddress; - - /* - * Enable slave monitor mode in control register. - */ - XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, - XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) | - XIICPS_CR_MS_MASK | - XIICPS_CR_NEA_MASK | - XIICPS_CR_SLVMON_MASK ); - - /* - * Set up interrupt flag for slave monitor interrupt. - */ - XIicPs_EnableInterrupts(BaseAddr, XIICPS_IXR_TO_MASK | - XIICPS_IXR_NACK_MASK | XIICPS_IXR_SLV_RDY_MASK); - - /* - * Initialize the slave monitor register. - */ - XIicPs_WriteReg(BaseAddr, XIICPS_SLV_PAUSE_OFFSET, 0xF); - - /* - * Set the slave address to start the slave address transmission. - */ - XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr); - - return; -} - -/*****************************************************************************/ -/** -* This function disables slave monitor mode. -* -* @param InstancePtr is a pointer to the XIicPs instance. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr) -{ - u32 BaseAddr; - - Xil_AssertVoid(InstancePtr != NULL); - - BaseAddr = InstancePtr->Config.BaseAddress; - - /* - * Clear slave monitor control bit. - */ - XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, - XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) - & (~XIICPS_CR_SLVMON_MASK)); - - /* - * Clear interrupt flag for slave monitor interrupt. - */ - XIicPs_DisableInterrupts(BaseAddr, XIICPS_IXR_SLV_RDY_MASK); - - return; -} - -/*****************************************************************************/ -/** -* The interrupt handler for the master mode. It does the protocol handling for -* the interrupt-driven transfers. -* -* Completion events and errors are signaled to upper layer for proper handling. -* -* <pre> -* The interrupts that are handled are: -* - DATA -* This case is handled only for master receive data. -* The master has to request for more data (if there is more data to -* receive) and read the data from the FIFO . -* -* - COMP -* If the Master is transmitting data and there is more data to be -* sent then the data is written to the FIFO. If there is no more data to -* be transmitted then a completion event is signalled to the upper layer -* by calling the callback handler. -* -* If the Master is receiving data then the data is read from the FIFO and -* the Master has to request for more data (if there is more data to -* receive). If all the data has been received then a completion event -* is signalled to the upper layer by calling the callback handler. -* It is an error if the amount of received data is more than expected. -* -* - NAK and SLAVE_RDY -* This is signalled to the upper layer by calling the callback handler. -* -* - All Other interrupts -* These interrupts are marked as error. This is signalled to the upper -* layer by calling the callback handler. -* -* </pre> -* -* @param InstancePtr is a pointer to the XIicPs instance. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr) -{ - u32 IntrStatusReg; - u32 IsSend = 0; - u32 StatusEvent = 0; - u32 BaseAddr; - int Tmp; - int BytesToRecv; - - /* - * Assert validates the input arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - BaseAddr = InstancePtr->Config.BaseAddress; - - /* - * Read the Interrupt status register. - */ - IntrStatusReg = XIicPs_ReadReg(BaseAddr, - XIICPS_ISR_OFFSET); - - /* - * Write the status back to clear the interrupts so no events are missed - * while processing this interrupt. - */ - XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg); - - /* - * Use the Mask register AND with the Interrupt Status register so - * disabled interrupts are not processed. - */ - IntrStatusReg &= ~(XIicPs_ReadReg(BaseAddr, XIICPS_IMR_OFFSET)); - - /* - * Data interrupt. - * - * In master mode, this means master receiving needs to put more data - * into the FIFO. In order to avoid slave times out waiting for ack, - * transfer size register must be set before data is processed. - * - */ - if (0 != (IntrStatusReg & XIICPS_IXR_DATA_MASK)) { - - /* - * Only greater than FIFO size is handled here, otherwise, the - * COMP interrupt will be triggered shortly, and we will handle - * those receives there. - */ - if ((InstancePtr->RecvByteCount) > XIICPS_FIFO_DEPTH){ - /* First find out how many bytes slave has sent us */ - BytesToRecv = XIICPS_FIFO_DEPTH - - XIicPs_ReadReg(BaseAddr, - XIICPS_TRANS_SIZE_OFFSET); - - if ((InstancePtr->RecvByteCount - BytesToRecv) - > XIICPS_FIFO_DEPTH) { - XIicPs_WriteReg(BaseAddr, - XIICPS_TRANS_SIZE_OFFSET, - XIICPS_FIFO_DEPTH); - } else { - XIicPs_WriteReg(BaseAddr, - XIICPS_TRANS_SIZE_OFFSET, - (InstancePtr->RecvByteCount - - BytesToRecv)); - } - - /* - * Receive the data out of the FIFO. - */ - for(Tmp = 0; Tmp < BytesToRecv; Tmp ++) { - XIicPs_RecvByte(InstancePtr); - } - - /* - * For receiving of larger than FIFO size, this is all - * the handling we need to do. - */ - return; - } - } - - /* - * Determine whether the device is sending. - */ - if (InstancePtr->RecvBufferPtr == NULL) { - IsSend = 1; - } - - /* - * Complete flag. - */ - if (0 != (IntrStatusReg & XIICPS_IXR_COMP_MASK)) { - if (IsSend) { - if (InstancePtr->SendByteCount > 0) { - MasterSendData(InstancePtr); - } else { - StatusEvent |= XIICPS_EVENT_COMPLETE_SEND; - } - } else { - /* - * Get the data out of FIFO first, if not done, - * tell the slave to send more. - */ - while (XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET) & - XIICPS_SR_RXDV_MASK) { - XIicPs_RecvByte(InstancePtr); - } - - /* - * Continue to tell slave to send data if not done. - */ - if (InstancePtr->RecvByteCount > XIICPS_FIFO_DEPTH) { - - XIicPs_WriteReg( - InstancePtr->Config.BaseAddress, - XIICPS_TRANS_SIZE_OFFSET, - XIICPS_FIFO_DEPTH); - - } else if (InstancePtr->RecvByteCount > 0) { - - XIicPs_WriteReg( - InstancePtr->Config.BaseAddress, - XIICPS_TRANS_SIZE_OFFSET, - InstancePtr->RecvByteCount); - } - - /* - * If all done, tell the application. - */ - if (InstancePtr->RecvByteCount == 0){ - StatusEvent |= XIICPS_EVENT_COMPLETE_RECV; - } - - /* - * If received more than expected, it is an error. - */ - if (InstancePtr->RecvByteCount < 0){ - StatusEvent |= XIICPS_EVENT_ERROR; - } - } - } - - /* - * Slave ready interrupt, it is only meaningful for master mode. - */ - if (0 != (IntrStatusReg & XIICPS_IXR_SLV_RDY_MASK)) { - StatusEvent |= XIICPS_EVENT_SLAVE_RDY; - } - - if (0 != (IntrStatusReg & XIICPS_IXR_NACK_MASK)) { - StatusEvent |= XIICPS_EVENT_NACK; - } - - /* - * All other interrupts are treated as error. - */ - if (0 != (IntrStatusReg & (XIICPS_IXR_TO_MASK | XIICPS_IXR_NACK_MASK | - XIICPS_IXR_ARB_LOST_MASK | XIICPS_IXR_RX_UNF_MASK | - XIICPS_IXR_TX_OVR_MASK | XIICPS_IXR_RX_OVR_MASK))) { - StatusEvent |= XIICPS_EVENT_ERROR; - } - - /* - * Signal application if there are any events. - */ - if (0 != StatusEvent) { - InstancePtr->StatusHandler(InstancePtr->CallBackRef, - StatusEvent); - } - -} - -/*****************************************************************************/ -/* -* This function prepares a device to transfers as a master. -* -* @param InstancePtr is a pointer to the XIicPs instance. -* -* @param Role specifies whether the device is sending or receiving. -* -* @return -* - XST_SUCCESS if everything went well. -* - XST_FAILURE if bus is busy. -* -* @note Interrupts are always disabled, device which needs to use -* interrupts needs to setup interrupts after this call. -* -****************************************************************************/ -static int XIicPs_SetupMaster(XIicPs *InstancePtr, int Role) -{ - u32 ControlReg; - u32 BaseAddr; - u32 EnabledIntr = 0x0; - - Xil_AssertNonvoid(InstancePtr != NULL); - - BaseAddr = InstancePtr->Config.BaseAddress; - ControlReg = XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET); - - - /* - * Only check if bus is busy when repeated start option is not set. - */ - if ((ControlReg & XIICPS_CR_HOLD_MASK) == 0) { - if (XIicPs_BusIsBusy(InstancePtr)) { - return XST_FAILURE; - } - } - - /* - * Set up master, AckEn, nea and also clear fifo. - */ - ControlReg |= XIICPS_CR_ACKEN_MASK | XIICPS_CR_CLR_FIFO_MASK | - XIICPS_CR_NEA_MASK | XIICPS_CR_MS_MASK; - - if (Role == RECVING_ROLE) { - ControlReg |= XIICPS_CR_RD_WR_MASK; - EnabledIntr = XIICPS_IXR_DATA_MASK |XIICPS_IXR_RX_OVR_MASK; - }else { - ControlReg &= ~XIICPS_CR_RD_WR_MASK; - } - EnabledIntr |= XIICPS_IXR_COMP_MASK | XIICPS_IXR_ARB_LOST_MASK; - - XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, ControlReg); - - XIicPs_DisableAllInterrupts(BaseAddr); - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/* -* This function handles continuation of sending data. It is invoked -* from interrupt handler. -* -* @param InstancePtr is a pointer to the XIicPs instance. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -static void MasterSendData(XIicPs *InstancePtr) -{ - TransmitFifoFill(InstancePtr); - - /* - * Clear repeated start if done, so stop can be sent out. - */ - if (InstancePtr->SendByteCount == 0) { - - /* - * If user has enabled repeated start as an option, - * do not disable it. - */ - if ((InstancePtr->Options & XIICPS_REP_START_OPTION) == 0) { - - XIicPs_WriteReg(InstancePtr->Config.BaseAddress, - XIICPS_CR_OFFSET, - XIicPs_ReadReg(InstancePtr->Config.BaseAddress, - XIICPS_CR_OFFSET) & ~ XIICPS_CR_HOLD_MASK); - } - } - - return; -} - - - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps_options.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps_options.c deleted file mode 100644 index 4d30b914351f8832a4a9e151da0c8e83cc9c45e3..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps_options.c +++ /dev/null @@ -1,455 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xiicps_options.c -* -* Contains functions for the configuration of the XIccPs driver. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------ -------- ----------------------------------------------- -* 1.00a drg/jz 01/30/10 First release -* 1.02a sg 08/29/12 Updated the logic to arrive at the best divisors -* to achieve I2C clock with minimum error. -* This is a fix for CR #674195 -* 1.03a hk 05/04/13 Initialized BestDivA and BestDivB to 0. - This is fix for CR#704398 to remove warning. -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xiicps.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - - -/************************** Variable Definitions *****************************/ -/* - * Create the table of options which are processed to get/set the device - * options. These options are table driven to allow easy maintenance and - * expansion of the options. - */ -typedef struct { - u32 Option; - u32 Mask; -} OptionsMap; - -static OptionsMap OptionsTable[] = { - {XIICPS_7_BIT_ADDR_OPTION, XIICPS_CR_NEA_MASK}, - {XIICPS_10_BIT_ADDR_OPTION, XIICPS_CR_NEA_MASK}, - {XIICPS_SLAVE_MON_OPTION, XIICPS_CR_SLVMON_MASK}, - {XIICPS_REP_START_OPTION, XIICPS_CR_HOLD_MASK}, -}; - -#define XIICPS_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(OptionsMap)) - -/*****************************************************************************/ -/** -* -* This function sets the options for the IIC device driver. The options control -* how the device behaves relative to the IIC bus. The device must be idle -* rather than busy transferring data before setting these device options. -* -* @param InstancePtr is a pointer to the XIicPs instance. -* @param Options contains the specified options to be set. This is a bit -* mask where a 1 means to turn the option on. One or more bit -* values may be contained in the mask. See the bit definitions -* named XIICPS_*_OPTION in xiicps.h. -* -* @return -* - XST_SUCCESS if options are successfully set. -* - XST_DEVICE_IS_STARTED if the device is currently transferring -* data. The transfer must complete or be aborted before setting -* options. -* -* @note None. -* -******************************************************************************/ -int XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options) -{ - u32 ControlReg; - unsigned int Index; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress, - XIICPS_CR_OFFSET); - - /* - * Loop through the options table, turning the option on. - */ - for (Index = 0; Index < XIICPS_NUM_OPTIONS; Index++) { - if (Options & OptionsTable[Index].Option) { - /* - * 10-bit option is specially treated, because it is - * using the 7-bit option, so turning it on means - * turning 7-bit option off. - */ - if (OptionsTable[Index].Option & - XIICPS_10_BIT_ADDR_OPTION) { - /* Turn 7-bit off */ - ControlReg &= ~OptionsTable[Index].Mask; - } else { - /* Turn 7-bit on */ - ControlReg |= OptionsTable[Index].Mask; - } - } - } - - /* - * Now write to the control register. Leave it to the upper layers - * to restart the device. - */ - XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET, - ControlReg); - - /* - * Keep a copy of what options this instance has. - */ - InstancePtr->Options = XIicPs_GetOptions(InstancePtr); - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* This function clears the options for the IIC device driver. The options -* control how the device behaves relative to the IIC bus. The device must be -* idle rather than busy transferring data before setting these device options. -* -* @param InstancePtr is a pointer to the XIicPs instance. -* @param Options contains the specified options to be cleared. This is a -* bit mask where a 1 means to turn the option off. One or more bit -* values may be contained in the mask. See the bit definitions -* named XIICPS_*_OPTION in xiicps.h. -* -* @return -* - XST_SUCCESS if options are successfully set. -* - XST_DEVICE_IS_STARTED if the device is currently transferring -* data. The transfer must complete or be aborted before setting -* options. -* -* @note None -* -******************************************************************************/ -int XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options) -{ - u32 ControlReg; - unsigned int Index; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress, - XIICPS_CR_OFFSET); - - /* - * Loop through the options table and clear the specified options. - */ - for (Index = 0; Index < XIICPS_NUM_OPTIONS; Index++) { - if (Options & OptionsTable[Index].Option) { - - /* - * 10-bit option is specially treated, because it is - * using the 7-bit option, so clearing it means turning - * 7-bit option on. - */ - if (OptionsTable[Index].Option & - XIICPS_10_BIT_ADDR_OPTION) { - - /* Turn 7-bit on */ - ControlReg |= OptionsTable[Index].Mask; - } else { - - /* Turn 7-bit off */ - ControlReg &= ~OptionsTable[Index].Mask; - } - } - } - - - /* - * Now write the control register. Leave it to the upper layers - * to restart the device. - */ - XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET, - ControlReg); - - /* - * Keep a copy of what options this instance has. - */ - InstancePtr->Options = XIicPs_GetOptions(InstancePtr); - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* This function gets the options for the IIC device. The options control how -* the device behaves relative to the IIC bus. -* -* @param InstancePtr is a pointer to the XIicPs instance. -* -* @return 32 bit mask of the options, where a 1 means the option is on, -* and a 0 means to the option is off. One or more bit values may -* be contained in the mask. See the bit definitions named -* XIICPS_*_OPTION in the file xiicps.h. -* -* @note None. -* -******************************************************************************/ -u32 XIicPs_GetOptions(XIicPs *InstancePtr) -{ - u32 OptionsFlag = 0; - u32 ControlReg; - unsigned int Index; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read control register to find which options are currently set. - */ - ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress, - XIICPS_CR_OFFSET); - - /* - * Loop through the options table to determine which options are set. - */ - for (Index = 0; Index < XIICPS_NUM_OPTIONS; Index++) { - if (ControlReg & OptionsTable[Index].Mask) { - OptionsFlag |= OptionsTable[Index].Option; - } - if ((ControlReg & XIICPS_CR_NEA_MASK) == 0) { - OptionsFlag |= XIICPS_10_BIT_ADDR_OPTION; - } - } - - return OptionsFlag; -} - -/*****************************************************************************/ -/** -* -* This function sets the serial clock rate for the IIC device. The device -* must be idle rather than busy transferring data before setting these device -* options. -* -* The data rate is set by values in the control register. The formula for -* determining the correct register values is: -* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1)) -* See the hardware data sheet for a full explanation of setting the serial -* clock rate. -* -* @param InstancePtr is a pointer to the XIicPs instance. -* @param FsclHz is the clock frequency in Hz. The two most common clock -* rates are 100KHz and 400KHz. -* -* @return -* - XST_SUCCESS if options are successfully set. -* - XST_DEVICE_IS_STARTED if the device is currently transferring -* data. The transfer must complete or be aborted before setting -* options. -* - XST_FAILURE if the Fscl frequency can not be set. -* -* @note The clock can not be faster than the input clock divide by 22. -* -******************************************************************************/ -int XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz) -{ - u32 Div_a; - u32 Div_b; - u32 ActualFscl; - u32 Temp; - u32 TempLimit; - u32 LastError; - u32 BestError; - u32 CurrentError; - u32 ControlReg; - u32 CalcDivA; - u32 CalcDivB; - u32 BestDivA = 0; - u32 BestDivB = 0; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(FsclHz > 0); - - if (0 != XIicPs_In32((InstancePtr->Config.BaseAddress) + - XIICPS_TRANS_SIZE_OFFSET)) { - return XST_DEVICE_IS_STARTED; - } - - /* - * Assume Div_a is 0 and calculate (divisor_a+1) x (divisor_b+1). - */ - Temp = (InstancePtr->Config.InputClockHz) / (22 * FsclHz); - - /* - * If the answer is negative or 0, the Fscl input is out of range. - */ - if (0 == Temp) { - return XST_FAILURE; - } - - /* - * TempLimit helps in iterating over the consecutive value of Temp to - * find the closest clock rate achievable with divisors. - * Iterate over the next value only if fractional part is involved. - */ - TempLimit = ((InstancePtr->Config.InputClockHz) % (22 * FsclHz)) ? - Temp + 1 : Temp; - BestError = FsclHz; - - for ( ; Temp <= TempLimit ; Temp++) - { - LastError = FsclHz; - CalcDivA = 0; - CalcDivB = 0; - CurrentError = 0; - - for (Div_b = 0; Div_b < 64; Div_b++) { - - Div_a = Temp / (Div_b + 1); - - if (Div_a != 0) - Div_a = Div_a - 1; - - if (Div_a > 3) - continue; - - ActualFscl = (InstancePtr->Config.InputClockHz) / - (22 * (Div_a + 1) * (Div_b + 1)); - - if (ActualFscl > FsclHz) - CurrentError = (ActualFscl - FsclHz); - else - CurrentError = (FsclHz - ActualFscl); - - if (LastError > CurrentError) { - CalcDivA = Div_a; - CalcDivB = Div_b; - LastError = CurrentError; - } - } - - /* - * Used to capture the best divisors. - */ - if (LastError < BestError) { - BestError = LastError; - BestDivA = CalcDivA; - BestDivB = CalcDivB; - } - } - - - /* - * Read the control register and mask the Divisors. - */ - ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress, - XIICPS_CR_OFFSET); - ControlReg &= ~(XIICPS_CR_DIV_A_MASK | XIICPS_CR_DIV_B_MASK); - ControlReg |= (BestDivA << XIICPS_CR_DIV_A_SHIFT) | - (BestDivB << XIICPS_CR_DIV_B_SHIFT); - - XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET, - ControlReg); - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* This function gets the serial clock rate for the IIC device. The device -* must be idle rather than busy transferring data before setting these device -* options. -* -* @param InstancePtr is a pointer to the XIicPs instance. -* -* @return The value of the IIC clock to the nearest Hz based on the -* control register settings. The actual value may not be exact to -* to integer math rounding errors. -* -* @note None. -* -******************************************************************************/ -u32 XIicPs_GetSClk(XIicPs *InstancePtr) -{ - u32 ControlReg; - u32 ActualFscl; - u32 Div_a; - u32 Div_b; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress, - XIICPS_CR_OFFSET); - - Div_a = (ControlReg & XIICPS_CR_DIV_A_MASK) >> XIICPS_CR_DIV_A_SHIFT; - Div_b = (ControlReg & XIICPS_CR_DIV_B_MASK) >> XIICPS_CR_DIV_B_SHIFT; - - ActualFscl = (InstancePtr->Config.InputClockHz) / - (22 * (Div_a + 1) * (Div_b + 1)); - - return ActualFscl; -} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps_selftest.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps_selftest.c deleted file mode 100644 index aa2bca1ccc4b206a97c6a4c47434a95217470394..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps_selftest.c +++ /dev/null @@ -1,140 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xiicps_selftest.c -* -* This component contains the implementation of selftest functions for the -* XIicPs driver component. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------ -------- --------------------------------------------- -* 1.00a drg/jz 01/30/10 First release -* 1.00a sdm 09/22/11 Removed unused code -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xiicps.h" - -/************************** Constant Definitions *****************************/ - -#define REG_TEST_VALUE 0x00000005 - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - - -/************************** Variable Definitions *****************************/ - - -/*****************************************************************************/ -/** -* -* Runs a self-test on the driver/device. The self-test is destructive in that -* a reset of the device is performed in order to check the reset values of -* the registers and to get the device into a known state. -* -* Upon successful return from the self-test, the device is reset. -* -* @param InstancePtr is a pointer to the XIicPs instance. -* -* @return -* - XST_SUCCESS if successful. -* - XST_REGISTER_ERROR indicates a register did not read or write -* correctly -* -* @note None. -* -******************************************************************************/ -int XIicPs_SelfTest(XIicPs *InstancePtr) -{ - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * All the IIC registers should be in their default state right now. - */ - if ((XIICPS_CR_RESET_VALUE != - XIicPs_ReadReg(InstancePtr->Config.BaseAddress, - XIICPS_CR_OFFSET)) || - (XIICPS_TO_RESET_VALUE != - XIicPs_ReadReg(InstancePtr->Config.BaseAddress, - XIICPS_TIME_OUT_OFFSET)) || - (XIICPS_IXR_ALL_INTR_MASK != - XIicPs_ReadReg(InstancePtr->Config.BaseAddress, - XIICPS_IMR_OFFSET))) { - return XST_FAILURE; - } - - XIicPs_Reset(InstancePtr); - - /* - * Write, Read then write a register - */ - XIicPs_WriteReg(InstancePtr->Config.BaseAddress, - XIICPS_SLV_PAUSE_OFFSET, REG_TEST_VALUE); - - if (REG_TEST_VALUE != XIicPs_ReadReg(InstancePtr->Config.BaseAddress, - XIICPS_SLV_PAUSE_OFFSET)) { - return XST_FAILURE; - } - - XIicPs_WriteReg(InstancePtr->Config.BaseAddress, - XIICPS_SLV_PAUSE_OFFSET, 0); - - XIicPs_Reset(InstancePtr); - - return XST_SUCCESS; -} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps_sinit.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps_sinit.c deleted file mode 100644 index fcf30b63d35c68f83744b49658e7480dfdbd2214..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps_sinit.c +++ /dev/null @@ -1,107 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xiicps_sinit.c -* -* The implementation of the XIicPs component's static initialization -* functionality. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------ -------- -------------------------------------------- -* 1.00a drg/jz 01/30/10 First release -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xstatus.h" -#include "xparameters.h" -#include "xiicps.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - -/************************** Variable Definitions *****************************/ -extern XIicPs_Config XIicPs_ConfigTable[]; - -/*****************************************************************************/ -/** -* -* Looks up the device configuration based on the unique device ID. A table -* contains the configuration info for each device in the system. -* -* @param DeviceId contains the ID of the device to look up the -* configuration for. -* -* @return A pointer to the configuration found or NULL if the specified -* device ID was not found. See xiicps.h for the definition of -* XIicPs_Config. -* -* @note None. -* -******************************************************************************/ -XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId) -{ - XIicPs_Config *CfgPtr = NULL; - int Index; - - for (Index = 0; Index < XPAR_XIICPS_NUM_INSTANCES; Index++) { - if (XIicPs_ConfigTable[Index].DeviceId == DeviceId) { - CfgPtr = &XIicPs_ConfigTable[Index]; - break; - } - } - - return CfgPtr; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps_slave.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps_slave.c deleted file mode 100644 index f9170aaaf6a03e6b3d8c80f468b3e931592d20f7..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/iicps_v1_04_a/src/xiicps_slave.c +++ /dev/null @@ -1,585 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* @file xiicps_slave.c -* -* Handles slave transfers -* -* <pre> MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- -- -------- --------------------------------------------- -* 1.00a jz 01/30/10 First release -* 1.04a kpc 08/30/13 Avoid buffer overwrite in SlaveRecvData function -* -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ -#include "xiicps.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ -extern int TransmitFifoFill(XIicPs *InstancePtr); - -static int SlaveRecvData(XIicPs *InstancePtr); - -/************************* Variable Definitions *****************************/ - -/*****************************************************************************/ -/** -* This function sets up the device to be a slave. -* -* @param InstancePtr is a pointer to the XIicPs instance. -* @param SlaveAddr is the address of the slave we are receiving from. -* -* @return None. -* -* @note -* Interrupt is always enabled no matter the tranfer is interrupt- -* driven or polled mode. Whether device will be interrupted or not -* depends on whether the device is connected to an interrupt -* controller and interrupt for the device is enabled. -* -****************************************************************************/ -void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr) -{ - volatile u32 ControlReg; - u32 BaseAddr; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr); - - BaseAddr = InstancePtr->Config.BaseAddress; - - ControlReg = XIicPs_In32(BaseAddr + XIICPS_CR_OFFSET); - - /* - * Set up master, AckEn, nea and also clear fifo. - */ - ControlReg |= XIICPS_CR_ACKEN_MASK | XIICPS_CR_CLR_FIFO_MASK; - ControlReg |= XIICPS_CR_NEA_MASK; - ControlReg &= ~XIICPS_CR_MS_MASK; - - XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, - ControlReg); - - XIicPs_DisableAllInterrupts(BaseAddr); - - XIicPs_WriteReg(InstancePtr->Config.BaseAddress, - XIICPS_ADDR_OFFSET, SlaveAddr); - - return; -} - -/*****************************************************************************/ -/** -* This function setup a slave interrupt-driven send. It set the repeated -* start for the device is the tranfer size is larger than FIFO depth. -* Data processing for the send is initiated by the interrupt handler. -* -* @param InstancePtr is a pointer to the XIicPs instance. -* @param MsgPtr is the pointer to the send buffer. -* @param ByteCount is the number of bytes to be sent. -* -* @return None. -* -* @note This send routine is for interrupt-driven transfer only. -* -****************************************************************************/ -void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount) -{ - u32 BaseAddr; - - /* - * Assert validates the input arguments - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(MsgPtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - - BaseAddr = InstancePtr->Config.BaseAddress; - InstancePtr->SendBufferPtr = MsgPtr; - InstancePtr->SendByteCount = ByteCount; - InstancePtr->RecvBufferPtr = NULL; - - XIicPs_EnableInterrupts(BaseAddr, - XIICPS_IXR_DATA_MASK | XIICPS_IXR_COMP_MASK | - XIICPS_IXR_TO_MASK | XIICPS_IXR_NACK_MASK | - XIICPS_IXR_TX_OVR_MASK); -} - -/*****************************************************************************/ -/** -* This function setup a slave interrupt-driven receive. -* Data processing for the receive is handled by the interrupt handler. -* -* @param InstancePtr is a pointer to the XIicPs instance. -* @param MsgPtr is the pointer to the receive buffer. -* @param ByteCount is the number of bytes to be received. -* -* @return None. -* -* @note This routine is for interrupt-driven transfer only. -* -****************************************************************************/ -void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount) -{ - /* - * Assert validates the input arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(MsgPtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - - InstancePtr->RecvBufferPtr = MsgPtr; - InstancePtr->RecvByteCount = ByteCount; - InstancePtr->SendBufferPtr = NULL; - - XIicPs_EnableInterrupts(InstancePtr->Config.BaseAddress, - XIICPS_IXR_DATA_MASK | XIICPS_IXR_COMP_MASK | - XIICPS_IXR_NACK_MASK | XIICPS_IXR_TO_MASK | - XIICPS_IXR_RX_OVR_MASK | XIICPS_IXR_RX_UNF_MASK); - -} - -/*****************************************************************************/ -/** -* This function sends a buffer in polled mode as a slave. -* -* @param InstancePtr is a pointer to the XIicPs instance. -* @param MsgPtr is the pointer to the send buffer. -* @param ByteCount is the number of bytes to be sent. -* -* @return -* - XST_SUCCESS if everything went well. -* - XST_FAILURE if master sends us data or master terminates the -* transfer before all data has sent out. -* -* @note This send routine is for polled mode transfer only. -* -****************************************************************************/ -int XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount) -{ - volatile u32 IntrStatusReg; - volatile u32 StatusReg; - u32 BaseAddr; - int Tmp; - int BytesToSend; - int Error = 0; - - /* - * Assert validates the input arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(MsgPtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - BaseAddr = InstancePtr->Config.BaseAddress; - InstancePtr->SendBufferPtr = MsgPtr; - InstancePtr->SendByteCount = ByteCount; - - /* - * Use RXRW bit in status register to wait master to start a read. - */ - StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET); - while (((StatusReg & XIICPS_SR_RXRW_MASK) == 0) && (!Error)) { - - /* - * If master tries to send us data, it is an error. - */ - if (StatusReg & XIICPS_SR_RXDV_MASK) { - Error = 1; - } - - StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET); - } - - if (Error) { - return XST_FAILURE; - } - - /* - * Clear the interrupt status register. - */ - IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET); - XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg); - - /* - * Send data as long as there is more data to send and - * there are no errors. - */ - while ((InstancePtr->SendByteCount > 0) && (!Error)){ - - /* - * Find out how many can be sent. - */ - BytesToSend = InstancePtr->SendByteCount; - if (BytesToSend > XIICPS_FIFO_DEPTH) { - BytesToSend = XIICPS_FIFO_DEPTH; - } - - for(Tmp = 0; Tmp < BytesToSend; Tmp ++) { - XIicPs_SendByte(InstancePtr); - } - - StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET); - - /* - * Wait for master to read the data out of fifo. - */ - while (((StatusReg & XIICPS_SR_TXDV_MASK) != 0) && (!Error)) { - - /* - * If master terminates the transfer before all data is - * sent, it is an error. - */ - IntrStatusReg = XIicPs_ReadReg(BaseAddr, - XIICPS_ISR_OFFSET); - if (IntrStatusReg & XIICPS_IXR_NACK_MASK) { - Error = 1; - } - - /* Clear ISR. - */ - XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, - IntrStatusReg); - - StatusReg = XIicPs_ReadReg(BaseAddr, - XIICPS_SR_OFFSET); - } - } - - if (Error) { - return XST_FAILURE; - } - - return XST_SUCCESS; -} -/*****************************************************************************/ -/** -* This function receives a buffer in polled mode as a slave. -* -* @param InstancePtr is a pointer to the XIicPs instance. -* @param MsgPtr is the pointer to the receive buffer. -* @param ByteCount is the number of bytes to be received. -* -* @return -* - XST_SUCCESS if everything went well. -* - XST_FAILURE if timed out. -* -* @note This receive routine is for polled mode transfer only. -* -****************************************************************************/ -int XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount) -{ - volatile u32 IntrStatusReg; - volatile u32 StatusReg; - u32 BaseAddr; - - /* - * Assert validates the input arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(MsgPtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - BaseAddr = InstancePtr->Config.BaseAddress; - InstancePtr->RecvBufferPtr = MsgPtr; - InstancePtr->RecvByteCount = ByteCount; - - StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET); - - /* - * Clear the interrupt status register. - */ - IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET); - XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg); - - /* - * Clear the status register. - */ - StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET); - XIicPs_WriteReg(BaseAddr, XIICPS_SR_OFFSET, StatusReg); - - StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET); - while (InstancePtr->RecvByteCount > 0) { - - /* Wait for master to put data */ - while ((StatusReg & XIICPS_SR_RXDV_MASK) == 0) { - StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET); - - /* - * If master terminates the transfer before we get all - * the data or the master tries to read from us, - * it is an error. - */ - IntrStatusReg = XIicPs_ReadReg(BaseAddr, - XIICPS_ISR_OFFSET); - if ((IntrStatusReg & (XIICPS_IXR_DATA_MASK | - XIICPS_IXR_COMP_MASK)) && - ((StatusReg & XIICPS_SR_RXDV_MASK) == 0) && - (InstancePtr->RecvByteCount > 0)) { - - return XST_FAILURE; - } - - /* - * Clear the interrupt status register. - */ - XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, - IntrStatusReg); - } - - /* - * Read all data from FIFO. - */ - while ((StatusReg & XIICPS_SR_RXDV_MASK) && - (InstancePtr->RecvByteCount > 0)){ - - XIicPs_RecvByte(InstancePtr); - - StatusReg = XIicPs_ReadReg(BaseAddr, - XIICPS_SR_OFFSET); - } - } - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* The interrupt handler for slave mode. It does the protocol handling for -* the interrupt-driven transfers. -* -* Completion events and errors are signaled to upper layer for proper -* handling. -* -* <pre> -* -* The interrupts that are handled are: -* - DATA -* If the instance is sending, it means that the master wants to read more -* data from us. Send more data, and check whether we are done with this -* send. -* -* If the instance is receiving, it means that the master has writen -* more data to us. Receive more data, and check whether we are done with -* with this receive. -* -* - COMP -* This marks that stop sequence has been sent from the master, transfer -* is about to terminate. However, for receiving, the master may have -* written us some data, so receive that first. -* -* It is an error if the amount of transfered data is less than expected. -* -* - NAK -* This marks that master does not want our data. It is for send only. -* -* - Other interrupts -* These interrupts are marked as error. -* -* </pre> -* -* @param InstancePtr is a pointer to the XIicPs instance. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr) -{ - volatile u32 IntrStatusReg; - u32 IsSend = 0; - u32 StatusEvent = 0; - int LeftOver; - u32 BaseAddr; - - /* - * Assert validates the input arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - BaseAddr = InstancePtr->Config.BaseAddress; - - /* - * Read the Interrupt status register. - */ - IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET); - - /* - * Write the status back to clear the interrupts so no events are missed - * while processing this interrupt. - */ - XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg); - - /* - * Use the Mask register AND with the Interrupt Status register so - * disabled interrupts are not processed. - */ - IntrStatusReg &= ~(XIicPs_ReadReg(BaseAddr, XIICPS_IMR_OFFSET)); - - /* - * Determine whether the device is sending. - */ - if (InstancePtr->RecvBufferPtr == NULL) { - IsSend = 1; - } - - /* Data interrupt - * - * This means master wants to do more data transfers. - * Also check for completion of transfer, signal upper layer if done. - */ - if (0 != (IntrStatusReg & XIICPS_IXR_DATA_MASK)) { - if (IsSend) { - LeftOver = TransmitFifoFill(InstancePtr); - /* - * We may finish send here - */ - if (LeftOver == 0) { - StatusEvent |= - XIICPS_EVENT_COMPLETE_SEND; - } - } else { - LeftOver = SlaveRecvData(InstancePtr); - - /* We may finish the receive here */ - if (LeftOver == 0) { - StatusEvent |= XIICPS_EVENT_COMPLETE_RECV; - } - } - } - - /* - * Complete interrupt. - * - * In slave mode, it means the master has done with this transfer, so - * we signal the application using completion event. - */ - if (0 != (IntrStatusReg & XIICPS_IXR_COMP_MASK)) { - if (IsSend) { - if (InstancePtr->SendByteCount > 0) { - StatusEvent |= XIICPS_EVENT_ERROR; - }else { - StatusEvent |= XIICPS_EVENT_COMPLETE_SEND; - } - } else { - LeftOver = SlaveRecvData(InstancePtr); - if (LeftOver > 0) { - StatusEvent |= XIICPS_EVENT_ERROR; - } else { - StatusEvent |= XIICPS_EVENT_COMPLETE_RECV; - } - } - } - - /* - * Nack interrupt, pass this information to application. - */ - if (0 != (IntrStatusReg & XIICPS_IXR_NACK_MASK)) { - StatusEvent |= XIICPS_EVENT_NACK; - } - - /* - * All other interrupts are treated as error. - */ - if (0 != (IntrStatusReg & (XIICPS_IXR_TO_MASK | - XIICPS_IXR_RX_UNF_MASK | - XIICPS_IXR_TX_OVR_MASK | - XIICPS_IXR_RX_OVR_MASK))){ - - StatusEvent |= XIICPS_EVENT_ERROR; - } - - /* - * Signal application if there are any events. - */ - if (0 != StatusEvent) { - InstancePtr->StatusHandler(InstancePtr->CallBackRef, - StatusEvent); - } -} - -/*****************************************************************************/ -/* -* -* This function handles continuation of receiving data. It is invoked -* from interrupt handler. -* -* @param InstancePtr is a pointer to the XIicPs instance. -* -* @return Number of bytes still expected by the instance. -* -* @note None. -* -****************************************************************************/ -static int SlaveRecvData(XIicPs *InstancePtr) -{ - volatile u32 StatusReg; - u32 BaseAddr; - - BaseAddr = InstancePtr->Config.BaseAddress; - - StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET); - - while ((StatusReg & XIICPS_SR_RXDV_MASK) && - (InstancePtr->RecvByteCount > 0)) { - XIicPs_RecvByte(InstancePtr); - StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET); - } - - return InstancePtr->RecvByteCount; -} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/qspips_v2_03_a/src/Makefile b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/qspips_v2_03_a/src/Makefile deleted file mode 100644 index c05a30d97b9afea4fe520865ca6e465b6b8fbd27..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/qspips_v2_03_a/src/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -COMPILER= -ARCHIVER= -CP=cp -COMPILER_FLAGS= -EXTRA_COMPILER_FLAGS= -LIB=libxil.a - -CC_FLAGS = $(COMPILER_FLAGS) -ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) - -RELEASEDIR=../../../lib -INCLUDEDIR=../../../include -INCLUDES=-I./. -I${INCLUDEDIR} - -OUTS = *.o - -LIBSOURCES:=*.c -INCLUDEFILES:=*.h - -OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) - -libs: banner xqspips_libs clean - -%.o: %.c - ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< - -banner: - echo "Compiling qspips" - -xqspips_libs: ${OBJECTS} - $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} - -.PHONY: include -include: xqspips_includes - -xqspips_includes: - ${CP} ${INCLUDEFILES} ${INCLUDEDIR} - -clean: - rm -rf ${OBJECTS} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/qspips_v2_03_a/src/xqspips.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/qspips_v2_03_a/src/xqspips.c deleted file mode 100644 index a017dbcd06df6438e7071a31b1e71cdd5fd9ee89..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/qspips_v2_03_a/src/xqspips.c +++ /dev/null @@ -1,1558 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xqspips.c -* -* Contains implements the interface functions of the XQspiPs driver. -* See xqspips.h for a detailed description of the device and driver. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- ----------------------------------------------- -* 1.00 sdm 11/25/10 First release -* 2.00a kka 07/25/12 Removed XQspiPs_GetWriteData API. -* The XQspiPs_SetSlaveSelect has been modified to remove -* the argument of the slave select as the QSPI controller -* only supports one slave. -* XQspiPs_GetSlaveSelect API has been removed -* Added logic to XQspiPs_GetReadData to handle data -* shift for normal data reads and instruction/status -* reads differently based on the ShiftReadData flag. -* Removed the selection for the following options: -* Master mode (XQSPIPS_MASTER_OPTION) and -* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option -* as the QSPI driver supports the Master mode -* and Flash Interface mode and doesnot support -* Slave mode or the legacy mode. -* Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer -* APIs so that the last argument (IsInst) specifying whether -* it is instruction or data has been removed. The first byte -* in the SendBufPtr argument of these APIs specify the -* instruction to be sent to the Flash Device. -* The XQspiPs_PolledTransfer function has been updated -* to fill the data to fifo depth. -* This version of the driver fixes CRs 670197/663787. -* 2.01a sg 02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ. -* Created macros XQspiPs_IsManualStart and -* XQspiPs_IsManualChipSelect. -* Changed QSPI transfer logic for polled and interrupt -* modes to be based on filled tx fifo count and receive -* based on it. RXNEMPTY interrupt is not used. -* Added assertions to XQspiPs_LqspiRead function. -* -* 2.02a hk 05/14/13 Added enable and disable to the XQspiPs_LqspiRead() -* function -* Added instructions for bank selection, die erase and -* flag status register to the flash instruction table -* Handling for instructions not in flash instruction -* table added. Checking for Tx FIFO empty when switching from -* TXD1/2/3 to TXD0 added. If WRSR instruction is sent with -* byte count 3 (spansion), instruction size and TXD register -* changed accordingly. CR# 712502 and 703869. -* Added (#ifdef linear base address) in the Linear read function. -* Changed XPAR_XQSPIPS_0_LINEAR_BASEADDR to -* XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in -* XQspiPs_LqspiRead function. Fix for CR#718141 -* -* 2.03a hk 09/05/13 Modified polled and interrupt transfers to make use of -* thresholds. This is to improve performance. -* Added RX and TX threshold reset to one in XQspiPs_Abort. -* Added RX threshold reset(1) after transfer in polled and -* interrupt transfers. Made changes to make sure threshold -* change is done only when no transfer is in progress. -* -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xqspips.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - -/** - * This typedef defines qspi flash instruction format - */ -typedef struct { - u8 OpCode; /**< Operational code of the instruction */ - u8 InstSize; /**< Size of the instruction including address bytes */ - u8 TxOffset; /**< Register address where instruction has to be - written */ -} XQspiPsInstFormat; - -/***************** Macros (Inline Functions) Definitions *********************/ - -#define ARRAY_SIZE(Array) (sizeof(Array) / sizeof((Array)[0])) - -/************************** Function Prototypes ******************************/ -static void XQspiPs_GetReadData(XQspiPs *InstancePtr, u32 Data, u8 Size); -static void StubStatusHandler(void *CallBackRef, u32 StatusEvent, - unsigned ByteCount); - -/************************** Variable Definitions *****************************/ - -/* - * List of all the QSPI instructions and its format - */ -static XQspiPsInstFormat FlashInst[] = { - { XQSPIPS_FLASH_OPCODE_WREN, 1, XQSPIPS_TXD_01_OFFSET }, - { XQSPIPS_FLASH_OPCODE_WRDS, 1, XQSPIPS_TXD_01_OFFSET }, - { XQSPIPS_FLASH_OPCODE_RDSR1, 2, XQSPIPS_TXD_10_OFFSET }, - { XQSPIPS_FLASH_OPCODE_RDSR2, 2, XQSPIPS_TXD_10_OFFSET }, - { XQSPIPS_FLASH_OPCODE_WRSR, 2, XQSPIPS_TXD_10_OFFSET }, - { XQSPIPS_FLASH_OPCODE_PP, 4, XQSPIPS_TXD_00_OFFSET }, - { XQSPIPS_FLASH_OPCODE_SE, 4, XQSPIPS_TXD_00_OFFSET }, - { XQSPIPS_FLASH_OPCODE_BE_32K, 4, XQSPIPS_TXD_00_OFFSET }, - { XQSPIPS_FLASH_OPCODE_BE_4K, 4, XQSPIPS_TXD_00_OFFSET }, - { XQSPIPS_FLASH_OPCODE_BE, 1, XQSPIPS_TXD_01_OFFSET }, - { XQSPIPS_FLASH_OPCODE_ERASE_SUS, 1, XQSPIPS_TXD_01_OFFSET }, - { XQSPIPS_FLASH_OPCODE_ERASE_RES, 1, XQSPIPS_TXD_01_OFFSET }, - { XQSPIPS_FLASH_OPCODE_RDID, 4, XQSPIPS_TXD_00_OFFSET }, - { XQSPIPS_FLASH_OPCODE_NORM_READ, 4, XQSPIPS_TXD_00_OFFSET }, - { XQSPIPS_FLASH_OPCODE_FAST_READ, 4, XQSPIPS_TXD_00_OFFSET }, - { XQSPIPS_FLASH_OPCODE_DUAL_READ, 4, XQSPIPS_TXD_00_OFFSET }, - { XQSPIPS_FLASH_OPCODE_QUAD_READ, 4, XQSPIPS_TXD_00_OFFSET }, - { XQSPIPS_FLASH_OPCODE_DUAL_IO_READ, 4, XQSPIPS_TXD_00_OFFSET }, - { XQSPIPS_FLASH_OPCODE_QUAD_IO_READ, 4, XQSPIPS_TXD_00_OFFSET }, - { XQSPIPS_FLASH_OPCODE_BRWR, 2, XQSPIPS_TXD_10_OFFSET }, - { XQSPIPS_FLASH_OPCODE_BRRD, 2, XQSPIPS_TXD_10_OFFSET }, - { XQSPIPS_FLASH_OPCODE_EARWR, 2, XQSPIPS_TXD_10_OFFSET }, - { XQSPIPS_FLASH_OPCODE_EARRD, 2, XQSPIPS_TXD_10_OFFSET }, - { XQSPIPS_FLASH_OPCODE_DIE_ERASE, 4, XQSPIPS_TXD_00_OFFSET }, - { XQSPIPS_FLASH_OPCODE_READ_FLAG_SR, 2, XQSPIPS_TXD_10_OFFSET }, - { XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR, 1, XQSPIPS_TXD_01_OFFSET }, - /* Add all the instructions supported by the flash device */ -}; - -/*****************************************************************************/ -/** -* -* Initializes a specific XQspiPs instance such that the driver is ready to use. -* -* The state of the device after initialization is: -* - Master mode -* - Active high clock polarity -* - Clock phase 0 -* - Baud rate divisor 2 -* - Transfer width 32 -* - Master reference clock = pclk -* - No chip select active -* - Manual CS and Manual Start disabled -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* @param ConfigPtr is a reference to a structure containing information -* about a specific QSPI device. This function initializes an -* InstancePtr object for a specific device specified by the -* contents of Config. -* @param EffectiveAddr is the device base address in the virtual memory -* address space. The caller is responsible for keeping the address -* mapping from EffectiveAddr to the device physical base address -* unchanged once this function is invoked. Unexpected errors may -* occur if the address mapping changes after this function is -* called. If address translation is not used, use -* ConfigPtr->Config.BaseAddress for this device. -* -* @return -* - XST_SUCCESS if successful. -* - XST_DEVICE_IS_STARTED if the device is already started. -* It must be stopped to re-initialize. -* -* @note None. -* -******************************************************************************/ -int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *ConfigPtr, - u32 EffectiveAddr) -{ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(ConfigPtr != NULL); - - /* - * If the device is busy, disallow the initialize and return a status - * indicating it is already started. This allows the user to stop the - * device and re-initialize, but prevents a user from inadvertently - * initializing. This assumes the busy flag is cleared at startup. - */ - if (InstancePtr->IsBusy == TRUE) { - return XST_DEVICE_IS_STARTED; - } - - /* - * Set some default values. - */ - InstancePtr->IsBusy = FALSE; - - InstancePtr->Config.BaseAddress = EffectiveAddr; - InstancePtr->StatusHandler = StubStatusHandler; - - InstancePtr->SendBufferPtr = NULL; - InstancePtr->RecvBufferPtr = NULL; - InstancePtr->RequestedBytes = 0; - InstancePtr->RemainingBytes = 0; - InstancePtr->IsReady = XIL_COMPONENT_IS_READY; - - InstancePtr->Config.ConnectionMode = ConfigPtr->ConnectionMode; - - /* - * Reset the QSPI device to get it into its initial state. It is - * expected that device configuration will take place after this - * initialization is done, but before the device is started. - */ - XQspiPs_Reset(InstancePtr); - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* Resets the QSPI device. Reset must only be called after the driver has been -* initialized. Any data transfer that is in progress is aborted. -* -* The upper layer software is responsible for re-configuring (if necessary) -* and restarting the QSPI device after the reset. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XQspiPs_Reset(XQspiPs *InstancePtr) -{ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Abort any transfer that is in progress - */ - XQspiPs_Abort(InstancePtr); - - /* - * Reset any values that are not reset by the hardware reset such that - * the software state matches the hardware device - */ - XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET, - XQSPIPS_CR_RESET_STATE); -} - -/*****************************************************************************/ -/** -* -* Aborts a transfer in progress by disabling the device and flush the RxFIFO. -* The byte counts are cleared, the busy flag is cleared. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* -* @return None. -* -* @note -* -* This function does a read/modify/write of the config register. The user of -* this function needs to take care of critical sections. -* -******************************************************************************/ -void XQspiPs_Abort(XQspiPs *InstancePtr) -{ - u32 ConfigReg; - - XQspiPs_Disable(InstancePtr); - - /* - * De-assert slave select lines. - */ - ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); - ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK); - XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET, ConfigReg); - - /* - * Set the RX and TX FIFO threshold to reset value (one) - */ - XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE); - - XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_TXWR_OFFSET, XQSPIPS_TXWR_RESET_VALUE); - - /* - * Clear the RX FIFO and drop any data. - */ - while ((XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_SR_OFFSET) & XQSPIPS_IXR_RXNEMPTY_MASK) != 0) { - XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_RXD_OFFSET); - } - - InstancePtr->RemainingBytes = 0; - InstancePtr->RequestedBytes = 0; - InstancePtr->IsBusy = FALSE; -} - -/*****************************************************************************/ -/** -* -* Transfers specified data on the QSPI bus. Initiates bus communication and -* sends/receives data to/from the selected QSPI slave. For every byte sent, -* a byte is received. -* -* The caller has the option of providing two different buffers for send and -* receive, or one buffer for both send and receive, or no buffer for receive. -* The receive buffer must be at least as big as the send buffer to prevent -* unwanted memory writes. This implies that the byte count passed in as an -* argument must be the smaller of the two buffers if they differ in size. -* Here are some sample usages: -* <pre> -* XQspiPs_Transfer(InstancePtr, SendBuf, RecvBuf, ByteCount) -* The caller wishes to send and receive, and provides two different -* buffers for send and receive. -* -* XQspiPs_Transfer(InstancePtr, SendBuf, NULL, ByteCount) -* The caller wishes only to send and does not care about the received -* data. The driver ignores the received data in this case. -* -* XQspiPs_Transfer(InstancePtr, SendBuf, SendBuf, ByteCount) -* The caller wishes to send and receive, but provides the same buffer -* for doing both. The driver sends the data and overwrites the send -* buffer with received data as it transfers the data. -* -* XQspiPs_Transfer(InstancePtr, RecvBuf, RecvBuf, ByteCount) -* The caller wishes to only receive and does not care about sending -* data. In this case, the caller must still provide a send buffer, but -* it can be the same as the receive buffer if the caller does not care -* what it sends. The device must send N bytes of data if it wishes to -* receive N bytes of data. -* </pre> -* Although this function takes entire buffers as arguments, the driver can only -* transfer a limited number of bytes at a time, limited by the size of the -* FIFO. A call to this function only starts the transfer, then subsequent -* transfers of the data is performed by the interrupt service routine until -* the entire buffer has been transferred. The status callback function is -* called when the entire buffer has been sent/received. -* -* This function is non-blocking. The SetSlaveSelect function must be called -* prior to this function. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* @param SendBufPtr is a pointer to a data buffer that needs to be -* transmitted. This buffer must not be NULL. -* @param RecvBufPtr is a pointer to a buffer for received data. -* This argument can be NULL if do not care about receiving. -* @param ByteCount contains the number of bytes to send/receive. -* The number of bytes received always equals the number of bytes -* sent. -* -* @return -* - XST_SUCCESS if the buffers are successfully handed off to the -* device for transfer. -* - XST_DEVICE_BUSY indicates that a data transfer is already in -* progress. This is determined by the driver. -* -* @note -* -* This function is not thread-safe. The higher layer software must ensure that -* no two threads are transferring data on the QSPI bus at the same time. -* -******************************************************************************/ -int XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr, - unsigned ByteCount) -{ - u32 StatusReg; - u32 ConfigReg; - u8 Instruction; - u32 Data; - unsigned int Index; - u8 TransCount = 0; - XQspiPsInstFormat *CurrInst; - XQspiPsInstFormat NewInst[2]; - u8 SwitchFlag = 0; - - CurrInst = &NewInst[0]; - - /* - * The RecvBufPtr argument can be null - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(SendBufPtr != NULL); - Xil_AssertNonvoid(ByteCount > 0); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Check whether there is another transfer in progress. Not thread-safe. - */ - if (InstancePtr->IsBusy) { - return XST_DEVICE_BUSY; - } - - /* - * Set the busy flag, which will be cleared in the ISR when the - * transfer is entirely done. - */ - InstancePtr->IsBusy = TRUE; - - /* - * Set up buffer pointers. - */ - InstancePtr->SendBufferPtr = SendBufPtr; - InstancePtr->RecvBufferPtr = RecvBufPtr; - - InstancePtr->RequestedBytes = ByteCount; - InstancePtr->RemainingBytes = ByteCount; - - /* - * The first byte with every chip-select assertion is always - * expected to be an instruction for flash interface mode - */ - Instruction = *InstancePtr->SendBufferPtr; - - for (Index = 0 ; Index < ARRAY_SIZE(FlashInst); Index++) { - if (Instruction == FlashInst[Index].OpCode) { - break; - } - } - - /* - * Set the RX FIFO threshold - */ - XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT); - - /* - * If the slave select is "Forced" or under manual control, - * set the slave select now, before beginning the transfer. - */ - if (XQspiPs_IsManualChipSelect(InstancePtr)) { - ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); - ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK; - XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET, - ConfigReg); - } - - /* - * Enable the device. - */ - XQspiPs_Enable(InstancePtr); - - /* - * Clear all the interrrupts. - */ - XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_SR_OFFSET, - XQSPIPS_IXR_WR_TO_CLR_MASK); - - if (Index < ARRAY_SIZE(FlashInst)) { - CurrInst = &FlashInst[Index]; - /* - * Check for WRSR instruction which has different size for - * Spansion (3 bytes) and Micron (2 bytes) - */ - if( (CurrInst->OpCode == XQSPIPS_FLASH_OPCODE_WRSR) && - (ByteCount == 3) ) { - CurrInst->InstSize = 3; - CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET; - } - } - - /* - * If instruction not present in table - */ - if (Index == ARRAY_SIZE(FlashInst)) { - /* - * Assign current instruction, size and TXD register to be used - * The InstSize mentioned in case of instructions greater than - * 4 bytes is not the actual size, but is indicative of - * the TXD register used. - * The remaining bytes of the instruction will be transmitted - * through TXD0 below. - */ - switch(ByteCount%4) - { - case XQSPIPS_SIZE_ONE: - CurrInst->OpCode = Instruction; - CurrInst->InstSize = XQSPIPS_SIZE_ONE; - CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET; - if(ByteCount > 4) { - SwitchFlag = 1; - } - break; - case XQSPIPS_SIZE_TWO: - CurrInst->OpCode = Instruction; - CurrInst->InstSize = XQSPIPS_SIZE_TWO; - CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET; - if(ByteCount > 4) { - SwitchFlag = 1; - } - break; - case XQSPIPS_SIZE_THREE: - CurrInst->OpCode = Instruction; - CurrInst->InstSize = XQSPIPS_SIZE_THREE; - CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET; - if(ByteCount > 4) { - SwitchFlag = 1; - } - break; - default: - CurrInst->OpCode = Instruction; - CurrInst->InstSize = XQSPIPS_SIZE_FOUR; - CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET; - break; - } - } - - /* - * If the instruction size in not 4 bytes then the data received needs - * to be shifted - */ - if( CurrInst->InstSize != 4 ) { - InstancePtr->ShiftReadData = 1; - } else { - InstancePtr->ShiftReadData = 0; - } - - /* Get the complete command (flash inst + address/data) */ - Data = *((u32 *)InstancePtr->SendBufferPtr); - InstancePtr->SendBufferPtr += CurrInst->InstSize; - InstancePtr->RemainingBytes -= CurrInst->InstSize; - if (InstancePtr->RemainingBytes < 0) { - InstancePtr->RemainingBytes = 0; - } - - /* Write the command to the FIFO */ - XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - CurrInst->TxOffset, Data); - TransCount++; - - /* - * If switching from TXD1/2/3 to TXD0, then start transfer and - * check for FIFO empty - */ - if(SwitchFlag == 1) { - SwitchFlag = 0; - /* - * If, in Manual Start mode, start the transfer. - */ - if (XQspiPs_IsManualStart(InstancePtr)) { - ConfigReg = XQspiPs_ReadReg( - InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); - ConfigReg |= XQSPIPS_CR_MANSTRT_MASK; - XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET, ConfigReg); - } - /* - * Wait for the transfer to finish by polling Tx fifo status. - */ - do { - StatusReg = XQspiPs_ReadReg( - InstancePtr->Config.BaseAddress, - XQSPIPS_SR_OFFSET); - } while ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0); - - } - - /* - * Fill the Tx FIFO with as many bytes as it takes (or as many as - * we have to send). - */ - while ((InstancePtr->RemainingBytes > 0) && - (TransCount < XQSPIPS_FIFO_DEPTH)) { - XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_TXD_00_OFFSET, - *((u32 *)InstancePtr->SendBufferPtr)); - InstancePtr->SendBufferPtr += 4; - InstancePtr->RemainingBytes -= 4; - if (InstancePtr->RemainingBytes < 0) { - InstancePtr->RemainingBytes = 0; - } - TransCount++; - } - - /* - * Enable QSPI interrupts (connecting to the interrupt controller and - * enabling interrupts should have been done by the caller). - */ - XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_IER_OFFSET, XQSPIPS_IXR_RXNEMPTY_MASK | - XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXOVR_MASK | - XQSPIPS_IXR_TXUF_MASK); - - /* - * If, in Manual Start mode, Start the transfer. - */ - if (XQspiPs_IsManualStart(InstancePtr)) { - ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); - ConfigReg |= XQSPIPS_CR_MANSTRT_MASK; - XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET, ConfigReg); - } - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* Transfers specified data on the QSPI bus in polled mode. -* -* The caller has the option of providing two different buffers for send and -* receive, or one buffer for both send and receive, or no buffer for receive. -* The receive buffer must be at least as big as the send buffer to prevent -* unwanted memory writes. This implies that the byte count passed in as an -* argument must be the smaller of the two buffers if they differ in size. -* Here are some sample usages: -* <pre> -* XQspiPs_PolledTransfer(InstancePtr, SendBuf, RecvBuf, ByteCount) -* The caller wishes to send and receive, and provides two different -* buffers for send and receive. -* -* XQspiPs_PolledTransfer(InstancePtr, SendBuf, NULL, ByteCount) -* The caller wishes only to send and does not care about the received -* data. The driver ignores the received data in this case. -* -* XQspiPs_PolledTransfer(InstancePtr, SendBuf, SendBuf, ByteCount) -* The caller wishes to send and receive, but provides the same buffer -* for doing both. The driver sends the data and overwrites the send -* buffer with received data as it transfers the data. -* -* XQspiPs_PolledTransfer(InstancePtr, RecvBuf, RecvBuf, ByteCount) -* The caller wishes to only receive and does not care about sending -* data. In this case, the caller must still provide a send buffer, but -* it can be the same as the receive buffer if the caller does not care -* what it sends. The device must send N bytes of data if it wishes to -* receive N bytes of data. -* -* </pre> -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* @param SendBufPtr is a pointer to a data buffer that needs to be -* transmitted. This buffer must not be NULL. -* @param RecvBufPtr is a pointer to a buffer for received data. -* This argument can be NULL if do not care about receiving. -* @param ByteCount contains the number of bytes to send/receive. -* The number of bytes received always equals the number of bytes -* sent. -* @return -* - XST_SUCCESS if the buffers are successfully handed off to the -* device for transfer. -* - XST_DEVICE_BUSY indicates that a data transfer is already in -* progress. This is determined by the driver. -* -* @note -* -* This function is not thread-safe. The higher layer software must ensure that -* no two threads are transferring data on the QSPI bus at the same time. -* -******************************************************************************/ -int XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr, - u8 *RecvBufPtr, unsigned ByteCount) -{ - u32 StatusReg; - u32 ConfigReg; - u8 Instruction; - u32 Data; - u8 TransCount; - unsigned int Index; - XQspiPsInstFormat *CurrInst; - XQspiPsInstFormat NewInst[2]; - u8 SwitchFlag = 0; - u8 IsManualStart = FALSE; - u32 RxCount = 0; - - CurrInst = &NewInst[0]; - /* - * The RecvBufPtr argument can be NULL. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(SendBufPtr != NULL); - Xil_AssertNonvoid(ByteCount > 0); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Check whether there is another transfer in progress. Not thread-safe. - */ - if (InstancePtr->IsBusy) { - return XST_DEVICE_BUSY; - } - - /* - * Set the busy flag, which will be cleared when the transfer is - * entirely done. - */ - InstancePtr->IsBusy = TRUE; - - /* - * Set up buffer pointers. - */ - InstancePtr->SendBufferPtr = SendBufPtr; - InstancePtr->RecvBufferPtr = RecvBufPtr; - - InstancePtr->RequestedBytes = ByteCount; - InstancePtr->RemainingBytes = ByteCount; - - /* - * The first byte with every chip-select assertion is always - * expected to be an instruction for flash interface mode - */ - Instruction = *InstancePtr->SendBufferPtr; - - for (Index = 0 ; Index < ARRAY_SIZE(FlashInst); Index++) { - if (Instruction == FlashInst[Index].OpCode) { - break; - } - } - - /* - * Set the RX FIFO threshold - */ - XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT); - - /* - * If the slave select is "Forced" or under manual control, - * set the slave select now, before beginning the transfer. - */ - if (XQspiPs_IsManualChipSelect(InstancePtr)) { - ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); - ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK; - XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET, - ConfigReg); - } - - /* - * Enable the device. - */ - XQspiPs_Enable(InstancePtr); - - if (Index < ARRAY_SIZE(FlashInst)) { - - CurrInst = &FlashInst[Index]; - /* - * Check for WRSR instruction which has different size for - * Spansion (3 bytes) and Micron (2 bytes) - */ - if( (CurrInst->OpCode == XQSPIPS_FLASH_OPCODE_WRSR) && - (ByteCount == 3) ) { - CurrInst->InstSize = 3; - CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET; - } - } - - /* - * If instruction not present in table - */ - if (Index == ARRAY_SIZE(FlashInst)) { - /* - * Assign current instruction, size and TXD register to be used. - * The InstSize mentioned in case of instructions greater than 4 bytes - * is not the actual size, but is indicative of the TXD register used. - * The remaining bytes of the instruction will be transmitted - * through TXD0 below. - */ - switch(ByteCount%4) - { - case XQSPIPS_SIZE_ONE: - CurrInst->OpCode = Instruction; - CurrInst->InstSize = XQSPIPS_SIZE_ONE; - CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET; - if(ByteCount > 4) { - SwitchFlag = 1; - } - break; - case XQSPIPS_SIZE_TWO: - CurrInst->OpCode = Instruction; - CurrInst->InstSize = XQSPIPS_SIZE_TWO; - CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET; - if(ByteCount > 4) { - SwitchFlag = 1; - } - break; - case XQSPIPS_SIZE_THREE: - CurrInst->OpCode = Instruction; - CurrInst->InstSize = XQSPIPS_SIZE_THREE; - CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET; - if(ByteCount > 4) { - SwitchFlag = 1; - } - break; - default: - CurrInst->OpCode = Instruction; - CurrInst->InstSize = XQSPIPS_SIZE_FOUR; - CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET; - break; - } - } - - /* - * If the instruction size in not 4 bytes then the data received needs - * to be shifted - */ - if( CurrInst->InstSize != 4 ) { - InstancePtr->ShiftReadData = 1; - } else { - InstancePtr->ShiftReadData = 0; - } - TransCount = 0; - /* Get the complete command (flash inst + address/data) */ - Data = *((u32 *)InstancePtr->SendBufferPtr); - InstancePtr->SendBufferPtr += CurrInst->InstSize; - InstancePtr->RemainingBytes -= CurrInst->InstSize; - if (InstancePtr->RemainingBytes < 0) { - InstancePtr->RemainingBytes = 0; - } - - /* Write the command to the FIFO */ - XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - CurrInst->TxOffset, Data); - ++TransCount; - - /* - * If switching from TXD1/2/3 to TXD0, then start transfer and - * check for FIFO empty - */ - if(SwitchFlag == 1) { - SwitchFlag = 0; - /* - * If, in Manual Start mode, start the transfer. - */ - if (XQspiPs_IsManualStart(InstancePtr)) { - ConfigReg = XQspiPs_ReadReg( - InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); - ConfigReg |= XQSPIPS_CR_MANSTRT_MASK; - XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET, ConfigReg); - } - /* - * Wait for the transfer to finish by polling Tx fifo status. - */ - do { - StatusReg = XQspiPs_ReadReg( - InstancePtr->Config.BaseAddress, - XQSPIPS_SR_OFFSET); - } while ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0); - - } - - /* - * Check if manual start is selected and store it in a - * local varibale for reference. This is to avoid reading - * the config register everytime. - */ - IsManualStart = XQspiPs_IsManualStart(InstancePtr); - - /* - * Fill the DTR/FIFO with as many bytes as it will take (or as - * many as we have to send). - */ - while ((InstancePtr->RemainingBytes > 0) && - (TransCount < XQSPIPS_FIFO_DEPTH)) { - XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_TXD_00_OFFSET, - *((u32 *)InstancePtr->SendBufferPtr)); - InstancePtr->SendBufferPtr += 4; - InstancePtr->RemainingBytes -= 4; - if (InstancePtr->RemainingBytes < 0) { - InstancePtr->RemainingBytes = 0; - } - ++TransCount; - } - - while((InstancePtr->RemainingBytes > 0) || - (InstancePtr->RequestedBytes > 0)) { - - /* - * Fill the TX FIFO with RX threshold no. of entries (or as - * many as we have to send, in case that's less). - */ - while ((InstancePtr->RemainingBytes > 0) && - (TransCount < XQSPIPS_RXFIFO_THRESHOLD_OPT)) { - XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_TXD_00_OFFSET, - *((u32 *)InstancePtr->SendBufferPtr)); - InstancePtr->SendBufferPtr += 4; - InstancePtr->RemainingBytes -= 4; - if (InstancePtr->RemainingBytes < 0) { - InstancePtr->RemainingBytes = 0; - } - ++TransCount; - } - - /* - * If, in Manual Start mode, start the transfer. - */ - if (IsManualStart == TRUE) { - ConfigReg = XQspiPs_ReadReg( - InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); - ConfigReg |= XQSPIPS_CR_MANSTRT_MASK; - XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET, ConfigReg); - } - - /* - * Reset TransCount - this is only used to fill TX FIFO - * in the above loop; - * RxCount is used to keep track of data received - */ - TransCount = 0; - - /* - * Wait for RX FIFO to reach threshold (or) - * TX FIFO to become empty. - * The latter check is required for - * small transfers (<32 words) and - * when the last chunk in a large data transfer is < 32 words. - */ - - do { - StatusReg = XQspiPs_ReadReg( - InstancePtr->Config.BaseAddress, - XQSPIPS_SR_OFFSET); - } while ( ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0) && - ((StatusReg & XQSPIPS_IXR_RXNEMPTY_MASK) == 0) ); - - /* - * A transmit has just completed. Process received data - * and check for more data to transmit. - * First get the data received as a result of the - * transmit that just completed. Receive data based on the - * count obtained while filling tx fifo. Always get - * the received data, but only fill the receive - * buffer if it points to something (the upper layer - * software may not care to receive data). - */ - while ((InstancePtr->RequestedBytes > 0) && - (RxCount < XQSPIPS_RXFIFO_THRESHOLD_OPT )) { - u32 Data; - - RxCount++; - - if (InstancePtr->RecvBufferPtr != NULL) { - if (InstancePtr->RequestedBytes < 4) { - Data = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_RXD_OFFSET); - XQspiPs_GetReadData(InstancePtr, Data, - InstancePtr->RequestedBytes); - } else { - (*(u32 *)InstancePtr->RecvBufferPtr) = - XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_RXD_OFFSET); - InstancePtr->RecvBufferPtr += 4; - InstancePtr->RequestedBytes -= 4; - if (InstancePtr->RequestedBytes < 0) { - InstancePtr->RequestedBytes = 0; - } - } - } else { - Data = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_RXD_OFFSET); - InstancePtr->RequestedBytes -= 4; - } - } - RxCount = 0; - } - - /* - * If the Slave select lines are being manually controlled, disable - * them because the transfer is complete. - */ - if (XQspiPs_IsManualChipSelect(InstancePtr)) { - ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); - ConfigReg |= XQSPIPS_CR_SSCTRL_MASK; - XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET, ConfigReg); - } - - /* - * Clear the busy flag. - */ - InstancePtr->IsBusy = FALSE; - - /* - * Disable the device. - */ - XQspiPs_Disable(InstancePtr); - - /* - * Reset the RX FIFO threshold to one - */ - XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE); - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* Read the flash in Linear QSPI mode. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* @param RecvBufPtr is a pointer to a buffer for received data. -* @param Address is the starting address within the flash from -* from where data needs to be read. -* @param ByteCount contains the number of bytes to receive. -* -* @return -* - XST_SUCCESS if read is performed -* - XST_FAILURE if Linear mode is not set -* -* @note None. -* -* -******************************************************************************/ -int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr, - u32 Address, unsigned ByteCount) -{ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(RecvBufPtr != NULL); - Xil_AssertNonvoid(ByteCount > 0); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - -#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR - /* - * Enable the controller - */ - XQspiPs_Enable(InstancePtr); - - if (XQspiPs_GetLqspiConfigReg(InstancePtr) & - XQSPIPS_LQSPI_CR_LINEAR_MASK) { - memcpy((void*)RecvBufPtr, - (const void*)(XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR + - Address), - (size_t)ByteCount); - return XST_SUCCESS; - } else { - return XST_FAILURE; - } - - /* - * Disable the controller - */ - XQspiPs_Disable(InstancePtr); - -#else - return XST_FAILURE; -#endif - -} - -/*****************************************************************************/ -/** -* -* Selects the slave with which the master communicates. -* -* The user is not allowed to select the slave while a transfer is in progress. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* -* @return -* - XST_SUCCESS if the slave is selected or deselected -* successfully. -* - XST_DEVICE_BUSY if a transfer is in progress, slave cannot be -* changed. -* -* @note -* -* This function only sets the slave which will be selected when a transfer -* occurs. The slave is not selected when the QSPI is idle. -* -******************************************************************************/ -int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr) -{ - u32 ConfigReg; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Do not allow the slave select to change while a transfer is in - * progress. Not thread-safe. - */ - if (InstancePtr->IsBusy) { - return XST_DEVICE_BUSY; - } - - /* - * Select the slave - */ - ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); - ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK; - XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET, ConfigReg); - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* Sets the status callback function, the status handler, which the driver -* calls when it encounters conditions that should be reported to upper -* layer software. The handler executes in an interrupt context, so it must -* minimize the amount of processing performed. One of the following status -* events is passed to the status handler. -* -* <pre> -* -* XST_SPI_TRANSFER_DONE The requested data transfer is done -* -* XST_SPI_TRANSMIT_UNDERRUN As a slave device, the master clocked data -* but there were none available in the transmit -* register/FIFO. This typically means the slave -* application did not issue a transfer request -* fast enough, or the processor/driver could not -* fill the transmit register/FIFO fast enough. -* -* XST_SPI_RECEIVE_OVERRUN The QSPI device lost data. Data was received -* but the receive data register/FIFO was full. -* -* </pre> -* @param InstancePtr is a pointer to the XQspiPs instance. -* @param CallBackRef is the upper layer callback reference passed back -* when the callback function is invoked. -* @param FuncPtr is the pointer to the callback function. -* -* @return None. -* -* @note -* -* The handler is called within interrupt context, so it should do its work -* quickly and queue potentially time-consuming work to a task-level thread. -* -******************************************************************************/ -void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef, - XQspiPs_StatusHandler FuncPtr) -{ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(FuncPtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - InstancePtr->StatusHandler = FuncPtr; - InstancePtr->StatusRef = CallBackRef; -} - -/*****************************************************************************/ -/** -* -* This is a stub for the status callback. The stub is here in case the upper -* layers forget to set the handler. -* -* @param CallBackRef is a pointer to the upper layer callback reference -* @param StatusEvent is the event that just occurred. -* @param ByteCount is the number of bytes transferred up until the event -* occurred. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -static void StubStatusHandler(void *CallBackRef, u32 StatusEvent, - unsigned ByteCount) -{ - (void) CallBackRef; - (void) StatusEvent; - (void) ByteCount; - - Xil_AssertVoidAlways(); -} - -/*****************************************************************************/ -/** -* -* The interrupt handler for QSPI interrupts. This function must be connected -* by the user to an interrupt controller. -* -* The interrupts that are handled are: -* -* -* - Data Transmit Register (FIFO) Empty. This interrupt is generated when the -* transmit register or FIFO is empty. The driver uses this interrupt during a -* transmission to continually send/receive data until the transfer is done. -* -* - Data Transmit Register (FIFO) Underflow. This interrupt is generated when -* the QSPI device, when configured as a slave, attempts to read an empty -* DTR/FIFO. An empty DTR/FIFO usually means that software is not giving the -* device data in a timely manner. No action is taken by the driver other than -* to inform the upper layer software of the error. -* -* - Data Receive Register (FIFO) Overflow. This interrupt is generated when the -* QSPI device attempts to write a received byte to an already full DRR/FIFO. -* A full DRR/FIFO usually means software is not emptying the data in a timely -* manner. No action is taken by the driver other than to inform the upper -* layer software of the error. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* -* @return None. -* -* @note -* -* The slave select register is being set to deselect the slave when a transfer -* is complete. -* -******************************************************************************/ -void XQspiPs_InterruptHandler(void *InstancePtr) -{ - XQspiPs *QspiPtr = (XQspiPs *)InstancePtr; - u32 IntrStatus; - u32 ConfigReg; - u32 Data; - u32 TransCount; - u32 Count = 0; - unsigned BytesDone; /* Number of bytes done so far. */ - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(QspiPtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Immediately clear the interrupts in case the ISR causes another - * interrupt to be generated. If we clear at the end of the ISR, - * we may miss newly generated interrupts. This occurs because we - * transmit from within the ISR, which could potentially cause another - * TX_EMPTY interrupt. - */ - IntrStatus = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress, - XQSPIPS_SR_OFFSET); - XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_SR_OFFSET, - (IntrStatus & XQSPIPS_IXR_WR_TO_CLR_MASK)); - XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_IDR_OFFSET, - XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXNEMPTY_MASK | - XQSPIPS_IXR_RXOVR_MASK | XQSPIPS_IXR_TXUF_MASK); - - if ((IntrStatus & XQSPIPS_IXR_TXOW_MASK) || - (IntrStatus & XQSPIPS_IXR_RXNEMPTY_MASK)) { - - /* - * Rx FIFO has just reached threshold no. of entries. - * Read threshold no. of entries from RX FIFO - * Another possiblity of entering this loop is when - * the last byte has been transmitted and TX FIFO is empty, - * in which case, read all the data from RX FIFO. - * Always get the received data, but only fill the - * receive buffer if it is not null (it can be null when - * the device does not care to receive data). - */ - TransCount = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes; - if (TransCount % 4) { - TransCount = TransCount/4 + 1; - } else { - TransCount = TransCount/4; - } - - while ((Count < TransCount) && - (Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) { - - if (QspiPtr->RecvBufferPtr != NULL) { - if (QspiPtr->RequestedBytes < 4) { - Data = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress, - XQSPIPS_RXD_OFFSET); - XQspiPs_GetReadData(QspiPtr, Data, - QspiPtr->RequestedBytes); - } else { - (*(u32 *)QspiPtr->RecvBufferPtr) = - XQspiPs_ReadReg(QspiPtr->Config.BaseAddress, - XQSPIPS_RXD_OFFSET); - QspiPtr->RecvBufferPtr += 4; - QspiPtr->RequestedBytes -= 4; - if (QspiPtr->RequestedBytes < 0) { - QspiPtr->RequestedBytes = 0; - } - } - } else { - XQspiPs_ReadReg(QspiPtr->Config.BaseAddress, - XQSPIPS_RXD_OFFSET); - QspiPtr->RequestedBytes -= 4; - if (QspiPtr->RequestedBytes < 0) { - QspiPtr->RequestedBytes = 0; - } - - } - Count++; - } - Count = 0; - /* - * Interrupt asserted as TX_OW got asserted - * See if there is more data to send. - * Fill TX FIFO with RX threshold no. of entries or - * remaining entries (in case that is less than threshold) - */ - while ((QspiPtr->RemainingBytes > 0) && - (Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) { - /* - * Send more data. - */ - XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, - XQSPIPS_TXD_00_OFFSET, - *((u32 *)QspiPtr->SendBufferPtr)); - QspiPtr->SendBufferPtr += 4; - QspiPtr->RemainingBytes -= 4; - if (QspiPtr->RemainingBytes < 0) { - QspiPtr->RemainingBytes = 0; - } - - Count++; - } - - if ((QspiPtr->RemainingBytes == 0) && - (QspiPtr->RequestedBytes == 0)) { - /* - * No more data to send. Disable the interrupt - * and inform the upper layer software that the - * transfer is done. The interrupt will be re-enabled - * when another transfer is initiated. - */ - XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, - XQSPIPS_IDR_OFFSET, - XQSPIPS_IXR_RXNEMPTY_MASK | - XQSPIPS_IXR_TXOW_MASK | - XQSPIPS_IXR_RXOVR_MASK | - XQSPIPS_IXR_TXUF_MASK); - - /* - * If the Slave select is being manually controlled, - * disable it because the transfer is complete. - */ - if (XQspiPs_IsManualChipSelect(InstancePtr)) { - ConfigReg = XQspiPs_ReadReg( - QspiPtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); - ConfigReg |= XQSPIPS_CR_SSCTRL_MASK; - XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET, - ConfigReg); - } - - /* - * Clear the busy flag. - */ - QspiPtr->IsBusy = FALSE; - - /* - * Disable the device. - */ - XQspiPs_Disable(QspiPtr); - - /* - * Reset the RX FIFO threshold to one - */ - XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, - XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE); - - QspiPtr->StatusHandler(QspiPtr->StatusRef, - XST_SPI_TRANSFER_DONE, - QspiPtr->RequestedBytes); - } else { - /* - * Enable the TXOW interrupt. - */ - XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, - XQSPIPS_IER_OFFSET, - XQSPIPS_IXR_RXNEMPTY_MASK | - XQSPIPS_IXR_TXOW_MASK | - XQSPIPS_IXR_RXOVR_MASK | - XQSPIPS_IXR_TXUF_MASK); - /* - * If, in Manual Start mode, start the transfer. - */ - if (XQspiPs_IsManualStart(QspiPtr)) { - ConfigReg = XQspiPs_ReadReg( - QspiPtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); - ConfigReg |= XQSPIPS_CR_MANSTRT_MASK; - XQspiPs_WriteReg( - QspiPtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET, ConfigReg); - } - } - } - - /* - * Check for overflow and underflow errors. - */ - if (IntrStatus & XQSPIPS_IXR_RXOVR_MASK) { - BytesDone = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes; - QspiPtr->IsBusy = FALSE; - - /* - * If the Slave select lines is being manually controlled, - * disable it because the transfer is complete. - */ - if (XQspiPs_IsManualChipSelect(InstancePtr)) { - ConfigReg = XQspiPs_ReadReg( - QspiPtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); - ConfigReg |= XQSPIPS_CR_SSCTRL_MASK; - XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET, ConfigReg); - } - - /* - * Disable the device. - */ - XQspiPs_Disable(QspiPtr); - - /* - * Reset the RX FIFO threshold to one - */ - XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, - XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE); - - QspiPtr->StatusHandler(QspiPtr->StatusRef, - XST_SPI_RECEIVE_OVERRUN, BytesDone); - } - - if (IntrStatus & XQSPIPS_IXR_TXUF_MASK) { - BytesDone = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes; - - QspiPtr->IsBusy = FALSE; - /* - * If the Slave select lines is being manually controlled, - * disable it because the transfer is complete. - */ - if (XQspiPs_IsManualChipSelect(InstancePtr)) { - ConfigReg = XQspiPs_ReadReg( - QspiPtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); - ConfigReg |= XQSPIPS_CR_SSCTRL_MASK; - XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET, ConfigReg); - } - - /* - * Disable the device. - */ - XQspiPs_Disable(QspiPtr); - - /* - * Reset the RX FIFO threshold to one - */ - XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, - XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE); - - QspiPtr->StatusHandler(QspiPtr->StatusRef, - XST_SPI_TRANSMIT_UNDERRUN, BytesDone); - } -} - - -/*****************************************************************************/ -/** -* -* Copies data from Data to the Receive buffer. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* @param Data is the data which needs to be copied to the Rx buffer. -* @param Size is the number of bytes to be copied to the Receive buffer. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -static void XQspiPs_GetReadData(XQspiPs *InstancePtr, u32 Data, u8 Size) -{ - u8 DataByte3; - - if (InstancePtr->RecvBufferPtr) { - switch (Size) { - case 1: - if (InstancePtr->ShiftReadData == 1) { - *((u8 *)InstancePtr->RecvBufferPtr) = - ((Data & 0xFF000000) >> 24); - } else { - *((u8 *)InstancePtr->RecvBufferPtr) = - (Data & 0xFF); - } - InstancePtr->RecvBufferPtr += 1; - break; - case 2: - if (InstancePtr->ShiftReadData == 1) { - *((u16 *)InstancePtr->RecvBufferPtr) = - ((Data & 0xFFFF0000) >> 16); - } else { - *((u16 *)InstancePtr->RecvBufferPtr) = - (Data & 0xFFFF); - } - InstancePtr->RecvBufferPtr += 2; - break; - case 3: - if (InstancePtr->ShiftReadData == 1) { - *((u16 *)InstancePtr->RecvBufferPtr) = - ((Data & 0x00FFFF00) >> 8); - InstancePtr->RecvBufferPtr += 2; - DataByte3 = ((Data & 0xFF000000) >> 24); - *((u8 *)InstancePtr->RecvBufferPtr) = DataByte3; - } else { - *((u16 *)InstancePtr->RecvBufferPtr) = - (Data & 0xFFFF); - InstancePtr->RecvBufferPtr += 2; - DataByte3 = ((Data & 0x00FF0000) >> 16); - *((u8 *)InstancePtr->RecvBufferPtr) = DataByte3; - } - InstancePtr->RecvBufferPtr += 1; - break; - default: - /* This will never execute */ - break; - } - } - InstancePtr->ShiftReadData = 0; - InstancePtr->RequestedBytes -= Size; - if (InstancePtr->RequestedBytes < 0) { - InstancePtr->RequestedBytes = 0; - } -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/qspips_v2_03_a/src/xqspips.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/qspips_v2_03_a/src/xqspips.h deleted file mode 100644 index 3114f5b57e3900496af6933b9e276b3b11179c00..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/qspips_v2_03_a/src/xqspips.h +++ /dev/null @@ -1,790 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xqspips.h -* -* This file contains the implementation of the XQspiPs driver. It supports only -* master mode. User documentation for the driver functions is contained in this -* file in the form of comment blocks at the front of each function. -* -* A QSPI device connects to an QSPI bus through a 4-wire serial interface. -* The QSPI bus is a full-duplex, synchronous bus that facilitates communication -* between one master and one slave. The device is always full-duplex, -* which means that for every byte sent, one is received, and vice-versa. -* The master controls the clock, so it can regulate when it wants to -* send or receive data. The slave is under control of the master, it must -* respond quickly since it has no control of the clock and must send/receive -* data as fast or as slow as the master does. -* -* <b> Linear Mode </b> -* The Linear Quad-SPI Controller extends the existing Quad-SPI Controller’s -* functionality by adding a linear addressing scheme that allows the SPI flash -* memory subsystem to behave like a typical ROM device. The new feature hides -* the normal SPI protocol from a master reading from the SPI flash memory. The -* feature improves both the user friendliness and the overall read memory -* throughput over that of the current Quad-SPI Controller by lessening the -* amount of software overheads required and by the use of the faster AXI -* interface. -* -* <b>Initialization & Configuration</b> -* -* The XQspiPs_Config structure is used by the driver to configure itself. This -* configuration structure is typically created by the tool-chain based on HW -* build properties. -* -* To support multiple runtime loading and initialization strategies employed by -* various operating systems, the driver instance can be initialized in the -* following way: -* - XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find -* static configuration structure defined in xqspips_g.c. This is setup -* by the tools. For some operating systems the config structure will be -* initialized by the software and this call is not needed. -* - XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a -* configuration structure provided by the caller. If running in a system -* with address translation, the provided virtual memory base address -* replaces the physical address present in the configuration structure. -* -* <b>Multiple Masters</b> -* -* More than one master can exist, but arbitration is the responsibility of -* the higher layer software. The device driver does not perform any type of -* arbitration. -* -* <b>Modes of Operation</b> -* -* There are four modes to perform a data transfer and the selection of a mode -* is based on Chip Select(CS) and Start. These two options individually, can -* be controlled either by software(Manual) or hardware(Auto). -* - Auto CS: Chip select is automatically asserted as soon as the first word -* is written into the TXFIFO and de asserted when the TXFIFO becomes -* empty -* - Manual CS: Software must assert and de assert CS. -* - Auto Start: Data transmission starts as soon as there is data in the -* TXFIFO and stalls when the TXFIFO is empty -* - Manual Start: Software must start data transmission at the beginning of -* the transaction or whenever the TXFIFO has become empty -* -* The preferred combination is Manual CS and Auto Start. -* In this combination, the software asserts CS before loading any data into -* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it -* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the -* data is available. If no further data, software disables CS. -* -* Risks/challenges of other combinations: -* - Manual CS and Manual Start: Manual Start bit should be set after each -* TXFIFO write otherwise there could be a race condition where the TXFIFO -* becomes empty before the new word is written. In that case the -* transmission stops. -* - Auto CS with Manual or Auto Start: It is very difficult for software to -* keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted. -* This results in a single transaction to be split into multiple pieces each -* with its own chip select. This will result in garbage data to be sent. -* -* <b>Interrupts</b> -* -* The user must connect the interrupt handler of the driver, -* XQspiPs_InterruptHandler, to an interrupt system such that it will be -* called when an interrupt occurs. This function does not save and restore -* the processor context such that the user must provide this processing. -* -* The driver handles the following interrupts: -* - Data Transmit Register/FIFO Underflow -* - Data Receive Register/FIFO Not Empty -* - Data Transmit Register/FIFO Overwater -* - Data Receive Register/FIFO Overrun -* -* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the -* QSPI device has transmitted the data available to transmit, and now its data -* register and FIFO is ready to accept more data. The driver uses this -* interrupt to indicate progress while sending data. The driver may have -* more data to send, in which case the data transmit register and FIFO is -* filled for subsequent transmission. When this interrupt arrives and all -* the data has been sent, the driver invokes the status callback with a -* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that -* all data has been sent. -* -* The Data Transmit Register/FIFO Underflow interrupt -- indicates that, -* as slave, the QSPI device was required to transmit but there was no data -* available to transmit in the transmit register (or FIFO). This may not -* be an error if the master is not expecting data. But in the case where -* the master is expecting data, this serves as a notification of such a -* condition. The driver reports this condition to the upper layer -* software through the status handler. -* -* The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI -* device received data and subsequently dropped the data because the data -* receive register and FIFO was full. The driver reports this condition to the -* upper layer software through the status handler. This likely indicates a -* problem with the higher layer protocol, or a problem with the slave -* performance. -* -* -* <b>Polled Operation</b> -* -* Transfer in polled mode is supported through a separate interface function -* XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode, -* this function blocks until all data has been sent/received. -* -* <b>Device Busy</b> -* -* Some operations are disallowed when the device is busy. The driver tracks -* whether a device is busy. The device is considered busy when a data transfer -* request is outstanding, and is considered not busy only when that transfer -* completes (or is aborted with a mode fault error). -* -* <b>Device Configuration</b> -* -* The device can be configured in various ways during the FPGA implementation -* process. Configuration parameters are stored in the xqspips_g.c file or -* passed in via XQspiPs_CfgInitialize(). A table is defined where each entry -* contains configuration information for an QSPI device, including the base -* address for the device. -* -* <b>RTOS Independence</b> -* -* This driver is intended to be RTOS and processor independent. It works with -* physical addresses only. Any needs for dynamic memory management, threads or -* thread mutual exclusion, virtual memory, or cache control must be satisfied -* by the layer above this driver. -* -* NOTE: This driver was always tested with endianess set to little-endian. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- ----------------------------------------------- -* 1.00a sdm 11/25/10 First release, based on the PS SPI driver. -* 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters -* in xparameters.h -* 2.00a kka 07/25/12 Added a few register defines for CR 670297 -* Removed code related to mode fault for CR 671468 -* The XQspiPs_SetSlaveSelect has been modified to remove -* the argument of the slave select as the QSPI controller -* only supports one slave. -* XQspiPs_GetSlaveSelect API has been removed -* Added a flag ShiftReadData to the instance structure -*. and is used in the XQspiPs_GetReadData API. -* The ShiftReadData Flag indicates whether the data -* read from the Rx FIFO needs to be shifted -* in cases where the data is less than 4 bytes -* Removed the selection for the following options: -* Master mode (XQSPIPS_MASTER_OPTION) and -* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option -* as the QSPI driver supports the Master mode -* and Flash Interface mode and doesnot support -* Slave mode or the legacy mode. -* Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer -* APIs so that the last argument (IsInst) specifying whether -* it is instruction or data has been removed. The first byte -* in the SendBufPtr argument of these APIs specify the -* instruction to be sent to the Flash Device. -* This version of the driver fixes CRs 670197/663787/ -* 670297/671468. -* Added the option for setting the Holdb_dr bit in the -* configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION -* is the option to be used for setting this bit in the -* configuration register. -* The XQspiPs_PolledTransfer function has been updated -* to fill the data to fifo depth. -* 2.01a sg 02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ. -* Added macros for Set/Get Rx Watermark. Changed QSPI -* Enable/Disable macro argument from BaseAddress to -* Instance Pointer. Added DelayNss argument to SetDelays -* and GetDelays API's. -* Created macros XQspiPs_IsManualStart and -* XQspiPs_IsManualChipSelect. -* Changed QSPI transfer logic for polled and interrupt -* modes to be based on filled tx fifo count and receive -* based on it. RXNEMPTY interrupt is not used. -* Added assertions to XQspiPs_LqspiRead function. -* SetDelays and GetDelays API's include DelayNss parameter. -* Added defines for DelayNss,Rx Watermark,Interrupts -* which need write to clear. Removed Read zeros mask from -* LQSPI Config register. Renamed Fixed burst error to -* data FSM error in LQSPI Status register. -* -* 2.02a hk 05/07/13 Added ConnectionMode to config structure. -* Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel -* Added enable and disable to the XQspiPs_LqspiRead() function -* Removed XQspi_Reset() in Set_Options() function when -* LQSPI_MODE_OPTION is set. -* Added instructions for bank selection, die erase and -* flag status register to the flash instruction table -* Handling for instructions not in flash instruction -* table added. Checking for Tx FIFO empty when switching from -* TXD1/2/3 to TXD0 added. If WRSR instruction is sent with -* byte count 3 (spansion), instruction size and TXD register -* changed accordingly. CR# 712502 and 703869. -* Added prefix to constant definitions for ConnectionMode -* Added (#ifdef linear base address) in the Linear read function. -* Changed XPAR_XQSPIPS_0_LINEAR_BASEADDR to -* XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in -* XQspiPs_LqspiRead function. Fix for CR#718141. -* -* 2.03a hk 09/17/13 Modified polled and interrupt transfers to make use of -* thresholds. This is to improve performance. -* Added API's for QSPI reset and -* linear mode initialization for boot. -* Added RX and TX threshold reset to one in XQspiPs_Abort. -* Added RX threshold reset(1) after transfer in polled and -* interrupt transfers. Made changes to make sure threshold -* change is done only when no transfer is in progress. -* Updated linear init API for parallel and stacked modes. -* CR#737760. -* -* </pre> -* -******************************************************************************/ -#ifndef XQSPIPS_H /* prevent circular inclusions */ -#define XQSPIPS_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xstatus.h" -#include "xqspips_hw.h" -#include <string.h> - -/************************** Constant Definitions *****************************/ - -/** @name Configuration options - * - * The following options are supported to enable/disable certain features of - * an QSPI device. Each of the options is a bit mask, so more than one may be - * specified. - * - * - * The <b>Active Low Clock option</b> configures the device's clock polarity. - * Setting this option means the clock is active low and the SCK signal idles - * high. By default, the clock is active high and SCK idles low. - * - * The <b>Clock Phase option</b> configures the QSPI device for one of two - * transfer formats. A clock phase of 0, the default, means data is valid on - * the first SCK edge (rising or falling) after the slave select (SS) signal - * has been asserted. A clock phase of 1 means data is valid on the second SCK - * edge (rising or falling) after SS has been asserted. - * - * - * The <b>QSPI Force Slave Select option</b> is used to enable manual control of - * the slave select signal. - * 0: The SPI_SS signal is controlled by the QSPI controller during - * transfers. (Default) - * 1: The SPI_SS signal is forced active (driven low) regardless of any - * transfers in progress. - * - * NOTE: The driver will handle setting and clearing the Slave Select when - * the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the - * QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the - * processor cannot empty and refill the FIFOs before the TX FIFO is empty - * When the QSPI hardware is controlling the Slave Select signals, this - * will cause slave to be de-selected and terminate the transfer. - * - * The <b>Manual Start option</b> is used to enable manual control of - * the Start command to perform data transfer. - * 0: The Start command is controlled by the QSPI controller during - * transfers(Default). Data transmission starts as soon as there is data in - * the TXFIFO and stalls when the TXFIFO is empty - * 1: The Start command must be issued by software to perform data transfer. - * Bit 15 of Configuration register is used to issue Start command. This bit - * must be set whenever TXFIFO is filled with new data. - * - * NOTE: The driver will set the Manual Start Enable bit in Configuration - * Register, if Manual Start option is selected. Software will issue - * Manual Start command whenever TXFIFO is filled with data. When there is - * no further data, driver will clear the Manual Start Enable bit. - * - * @{ - */ -#define XQSPIPS_CLK_ACTIVE_LOW_OPTION 0x2 /**< Active Low Clock option */ -#define XQSPIPS_CLK_PHASE_1_OPTION 0x4 /**< Clock Phase one option */ -#define XQSPIPS_FORCE_SSELECT_OPTION 0x10 /**< Force Slave Select */ -#define XQSPIPS_MANUAL_START_OPTION 0x20 /**< Manual Start enable */ -#define XQSPIPS_LQSPI_MODE_OPTION 0x80 /**< Linear QPSI mode */ -#define XQSPIPS_HOLD_B_DRIVE_OPTION 0x100 /**< Drive HOLD_B Pin */ -/*@}*/ - - -/** @name QSPI Clock Prescaler options - * The QSPI Clock Prescaler Configuration bits are used to program master mode - * bit rate. The bit rate can be programmed in divide-by-two decrements from - * pclk/2 to pclk/256. - * - * @{ - */ -#define XQSPIPS_CLK_PRESCALE_2 0x00 /**< PCLK/2 Prescaler */ -#define XQSPIPS_CLK_PRESCALE_4 0x01 /**< PCLK/4 Prescaler */ -#define XQSPIPS_CLK_PRESCALE_8 0x02 /**< PCLK/8 Prescaler */ -#define XQSPIPS_CLK_PRESCALE_16 0x03 /**< PCLK/16 Prescaler */ -#define XQSPIPS_CLK_PRESCALE_32 0x04 /**< PCLK/32 Prescaler */ -#define XQSPIPS_CLK_PRESCALE_64 0x05 /**< PCLK/64 Prescaler */ -#define XQSPIPS_CLK_PRESCALE_128 0x06 /**< PCLK/128 Prescaler */ -#define XQSPIPS_CLK_PRESCALE_256 0x07 /**< PCLK/256 Prescaler */ - -/*@}*/ - - -/** @name Callback events - * - * These constants specify the handler events that are passed to - * a handler from the driver. These constants are not bit masks such that - * only one will be passed at a time to the handler. - * - * @{ - */ -#define XQSPIPS_EVENT_TRANSFER_DONE 2 /**< Transfer done */ -#define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */ -#define XQSPIPS_EVENT_RECEIVE_OVERRUN 4 /**< Receive data loss because - RX FIFO full */ -/*@}*/ - -/** @name Flash commands - * - * The following constants define most of the commands supported by flash - * devices. Users can add more commands supported by the flash devices - * - * @{ - */ -#define XQSPIPS_FLASH_OPCODE_WRSR 0x01 /* Write status register */ -#define XQSPIPS_FLASH_OPCODE_PP 0x02 /* Page program */ -#define XQSPIPS_FLASH_OPCODE_NORM_READ 0x03 /* Normal read data bytes */ -#define XQSPIPS_FLASH_OPCODE_WRDS 0x04 /* Write disable */ -#define XQSPIPS_FLASH_OPCODE_RDSR1 0x05 /* Read status register 1 */ -#define XQSPIPS_FLASH_OPCODE_WREN 0x06 /* Write enable */ -#define XQSPIPS_FLASH_OPCODE_FAST_READ 0x0B /* Fast read data bytes */ -#define XQSPIPS_FLASH_OPCODE_BE_4K 0x20 /* Erase 4KiB block */ -#define XQSPIPS_FLASH_OPCODE_RDSR2 0x35 /* Read status register 2 */ -#define XQSPIPS_FLASH_OPCODE_DUAL_READ 0x3B /* Dual read data bytes */ -#define XQSPIPS_FLASH_OPCODE_BE_32K 0x52 /* Erase 32KiB block */ -#define XQSPIPS_FLASH_OPCODE_QUAD_READ 0x6B /* Quad read data bytes */ -#define XQSPIPS_FLASH_OPCODE_ERASE_SUS 0x75 /* Erase suspend */ -#define XQSPIPS_FLASH_OPCODE_ERASE_RES 0x7A /* Erase resume */ -#define XQSPIPS_FLASH_OPCODE_RDID 0x9F /* Read JEDEC ID */ -#define XQSPIPS_FLASH_OPCODE_BE 0xC7 /* Erase whole flash block */ -#define XQSPIPS_FLASH_OPCODE_SE 0xD8 /* Sector erase (usually 64KB)*/ -#define XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */ -#define XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */ -#define XQSPIPS_FLASH_OPCODE_BRWR 0x17 /* Bank Register Write */ -#define XQSPIPS_FLASH_OPCODE_BRRD 0x16 /* Bank Register Read */ -/* Extende Address Register Write - Micron's equivalent of Bank Register */ -#define XQSPIPS_FLASH_OPCODE_EARWR 0xC5 -/* Extende Address Register Read - Micron's equivalent of Bank Register */ -#define XQSPIPS_FLASH_OPCODE_EARRD 0xC8 -#define XQSPIPS_FLASH_OPCODE_DIE_ERASE 0xC4 -#define XQSPIPS_FLASH_OPCODE_READ_FLAG_SR 0x70 -#define XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR 0x50 -#define XQSPIPS_FLASH_OPCODE_READ_LOCK_REG 0xE8 /* Lock register Read */ -#define XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG 0xE5 /* Lock Register Write */ - -/*@}*/ - -/** @name Instruction size - * - * The following constants define numbers 1 to 4. - * Used to identify whether TXD0,1,2 or 3 is to be used. - * - * @{ - */ -#define XQSPIPS_SIZE_ONE 1 -#define XQSPIPS_SIZE_TWO 2 -#define XQSPIPS_SIZE_THREE 3 -#define XQSPIPS_SIZE_FOUR 4 - -/*@}*/ - -/** @name ConnectionMode - * - * The following constants are the possible values of ConnectionMode in - * Config structure. - * - * @{ - */ -#define XQSPIPS_CONNECTION_MODE_SINGLE 0 -#define XQSPIPS_CONNECTION_MODE_STACKED 1 -#define XQSPIPS_CONNECTION_MODE_PARALLEL 2 - -/*@}*/ - -/** @name FIFO threshold value - * - * This is the Rx FIFO threshold (in words) that was found to be most - * optimal in terms of performance - * - * @{ - */ -#define XQSPIPS_RXFIFO_THRESHOLD_OPT 32 - -/*@}*/ - -/**************************** Type Definitions *******************************/ -/** - * The handler data type allows the user to define a callback function to - * handle the asynchronous processing for the QSPI device. The application - * using this driver is expected to define a handler of this type to support - * interrupt driven mode. The handler executes in an interrupt context, so - * only minimal processing should be performed. - * - * @param CallBackRef is the callback reference passed in by the upper - * layer when setting the callback functions, and passed back to - * the upper layer when the callback is invoked. Its type is - * not important to the driver, so it is a void pointer. - * @param StatusEvent holds one or more status events that have occurred. - * See the XQspiPs_SetStatusHandler() for details on the status - * events that can be passed in the callback. - * @param ByteCount indicates how many bytes of data were successfully - * transferred. This may be less than the number of bytes - * requested if the status event indicates an error. - */ -typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent, - unsigned ByteCount); - -/** - * This typedef contains configuration information for the device. - */ -typedef struct { - u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddress; /**< Base address of the device */ - u32 InputClockHz; /**< Input clock frequency */ - u8 ConnectionMode; /**< Single, Stacked and Parallel mode */ -} XQspiPs_Config; - -/** - * The XQspiPs driver instance data. The user is required to allocate a - * variable of this type for every QSPI device in the system. A pointer - * to a variable of this type is then passed to the driver API functions. - */ -typedef struct { - XQspiPs_Config Config; /**< Configuration structure */ - u32 IsReady; /**< Device is initialized and ready */ - - u8 *SendBufferPtr; /**< Buffer to send (state) */ - u8 *RecvBufferPtr; /**< Buffer to receive (state) */ - int RequestedBytes; /**< Number of bytes to transfer (state) */ - int RemainingBytes; /**< Number of bytes left to transfer(state) */ - u32 IsBusy; /**< A transfer is in progress (state) */ - XQspiPs_StatusHandler StatusHandler; - void *StatusRef; /**< Callback reference for status handler */ - u32 ShiftReadData; /**< Flag to indicate whether the data - * read from the Rx FIFO needs to be shifted - * in cases where the data is less than 4 - * bytes - */ -} XQspiPs; - -/***************** Macros (Inline Functions) Definitions *********************/ - -/****************************************************************************/ -/* -* -* Check in OptionsTable if Manual Start Option is enabled or disabled. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* -* @return -* - TRUE if option is set -* - FALSE if option is not set -* -* @note C-Style signature: -* u8 XQspiPs_IsManualStart(XQspiPs *InstancePtr); -* -*****************************************************************************/ -#define XQspiPs_IsManualStart(InstancePtr) \ - ((XQspiPs_GetOptions(InstancePtr) & \ - XQSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE) - -/****************************************************************************/ -/* -* -* Check in OptionsTable if Manual Chip Select Option is enabled or disabled. -* -* @param InstancePtr is a pointer to the XSpiPs instance. -* -* @return -* - TRUE if option is set -* - FALSE if option is not set -* -* @note C-Style signature: -* u8 XQspiPs_IsManualChipSelect(XQspiPs *InstancePtr); -* -*****************************************************************************/ -#define XQspiPs_IsManualChipSelect(InstancePtr) \ - ((XQspiPs_GetOptions(InstancePtr) & \ - XQSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE) - -/****************************************************************************/ -/** -* -* Set the contents of the slave idle count register. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* @param RegisterValue is the value to be written, valid values are -* 0-255. -* -* @return None -* -* @note -* C-Style signature: -* void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr, u32 RegisterValue) -* -*****************************************************************************/ -#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue) \ - XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ - XQSPIPS_SICR_OFFSET, (RegisterValue)) - -/****************************************************************************/ -/** -* -* Get the contents of the slave idle count register. Use the XQSPIPS_SICR_* -* constants defined in xqspips_hw.h to interpret the bit-mask returned. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* -* @return An 8-bit value representing Slave Idle Count. -* -* @note C-Style signature: -* u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr) -* -*****************************************************************************/ -#define XQspiPs_GetSlaveIdle(InstancePtr) \ - XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \ - XQSPIPS_SICR_OFFSET) - -/****************************************************************************/ -/** -* -* Set the contents of the transmit FIFO watermark register. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* @param RegisterValue is the value to be written, valid values are 1-63. -* -* @return None. -* -* @note -* C-Style signature: -* void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr, u32 RegisterValue) -* -*****************************************************************************/ -#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue) \ - XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ - XQSPIPS_TXWR_OFFSET, (RegisterValue)) - -/****************************************************************************/ -/** -* -* Get the contents of the transmit FIFO watermark register. -* Valid values are in the range 1-63. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* -* @return A 6-bit value representing Tx Watermark level. -* -* @note C-Style signature: -* u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr) -* -*****************************************************************************/ -#define XQspiPs_GetTXWatermark(InstancePtr) \ - XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET) - -/****************************************************************************/ -/** -* -* Set the contents of the receive FIFO watermark register. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* @param RegisterValue is the value to be written, valid values are 1-63. -* -* @return None. -* -* @note -* C-Style signature: -* void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr, u32 RegisterValue) -* -*****************************************************************************/ -#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue) \ - XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ - XQSPIPS_RXWR_OFFSET, (RegisterValue)) - -/****************************************************************************/ -/** -* -* Get the contents of the receive FIFO watermark register. -* Valid values are in the range 1-63. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* -* @return A 6-bit value representing Rx Watermark level. -* -* @note C-Style signature: -* u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr) -* -*****************************************************************************/ -#define XQspiPs_GetRXWatermark(InstancePtr) \ - XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET) - -/****************************************************************************/ -/** -* -* Enable the device and uninhibit master transactions. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* -* @return None. -* -* @note C-Style signature: -* void XQspiPs_Enable(XQspiPs *InstancePtr) -* -*****************************************************************************/ -#define XQspiPs_Enable(InstancePtr) \ - XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \ - XQSPIPS_ER_ENABLE_MASK) - -/****************************************************************************/ -/** -* -* Disable the device. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* -* @return None. -* -* @note C-Style signature: -* void XQspiPs_Disable(XQspiPs *InstancePtr) -* -*****************************************************************************/ -#define XQspiPs_Disable(InstancePtr) \ - XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0) - -/****************************************************************************/ -/** -* -* Set the contents of the Linear QSPI Configuration register. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* @param RegisterValue is the value to be written to the Linear QSPI -* configuration register. -* -* @return None. -* -* @note -* C-Style signature: -* void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr, -* u32 RegisterValue) -* -*****************************************************************************/ -#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue) \ - XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ - XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue)) - -/****************************************************************************/ -/** -* -* Get the contents of the Linear QSPI Configuration register. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* -* @return A 32-bit value representing the contents of the LQSPI Config -* register. -* -* @note C-Style signature: -* u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr) -* -*****************************************************************************/ -#define XQspiPs_GetLqspiConfigReg(InstancePtr) \ - XQspiPs_In32((InstancePtr->Config.BaseAddress) + \ - XQSPIPS_LQSPI_CR_OFFSET) - -/************************** Function Prototypes ******************************/ - -/* - * Initialization function, implemented in xqspips_sinit.c - */ -XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId); - -/* - * Functions implemented in xqspips.c - */ -int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config * Config, - u32 EffectiveAddr); -void XQspiPs_Reset(XQspiPs *InstancePtr); -void XQspiPs_Abort(XQspiPs *InstancePtr); - -int XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr, - unsigned ByteCount); -int XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr, - u8 *RecvBufPtr, unsigned ByteCount); -int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr, - u32 Address, unsigned ByteCount); - -int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr); - -void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef, - XQspiPs_StatusHandler FuncPtr); -void XQspiPs_InterruptHandler(void *InstancePtr); - -/* - * Functions for selftest, in xqspips_selftest.c - */ -int XQspiPs_SelfTest(XQspiPs *InstancePtr); - -/* - * Functions for options, in xqspips_options.c - */ -int XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options); -u32 XQspiPs_GetOptions(XQspiPs *InstancePtr); - -int XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler); -u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr); - -int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn, - u8 DelayAfter, u8 DelayInit); -void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn, - u8 *DelayAfter, u8 *DelayInit); -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/qspips_v2_03_a/src/xqspips_g.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/qspips_v2_03_a/src/xqspips_g.c deleted file mode 100644 index cc154213682889c3858431358db3c581d8a7e0ee..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/qspips_v2_03_a/src/xqspips_g.c +++ /dev/null @@ -1,32 +0,0 @@ - -/******************************************************************* -* -* CAUTION: This file is automatically generated by libgen. -* Version: Xilinx EDK 14.7 EDK_P.20131013 -* DO NOT EDIT. -* -* Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. - -* -* Description: Driver configuration -* -*******************************************************************/ - -#include "xparameters.h" -#include "xqspips.h" - -/* -* The configuration table for devices -*/ - -XQspiPs_Config XQspiPs_ConfigTable[] = -{ - { - XPAR_PS7_QSPI_0_DEVICE_ID, - XPAR_PS7_QSPI_0_BASEADDR, - XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ, - XPAR_PS7_QSPI_0_QSPI_MODE - } -}; - - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/qspips_v2_03_a/src/xqspips_hw.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/qspips_v2_03_a/src/xqspips_hw.c deleted file mode 100644 index db8657053c665fe49ef9dfe0b6bfd58c47a8b015..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/qspips_v2_03_a/src/xqspips_hw.c +++ /dev/null @@ -1,228 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xqspips_hw.c -* -* Contains low level functions, primarily reset related. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- ----------------------------------------------- -* 2.03a hk 09/17/13 First release -* -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xqspips_hw.h" -#include "xqspips.h" - -/************************** Constant Definitions *****************************/ - -/** @name Pre-scaler value for divided by 4 - * - * Pre-scaler value for divided by 4 - * - * @{ - */ -#define XQSPIPS_CR_PRESC_DIV_BY_4 0x01 -/* @} */ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/************************** Variable Definitions *****************************/ - - -/*****************************************************************************/ -/** -* -* Resets QSPI by disabling the device and bringing it to reset state through -* register writes. -* -* @param None -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XQspiPs_ResetHw(u32 BaseAddress) -{ - u32 ConfigReg; - - /* - * Disable interrupts - */ - XQspiPs_WriteReg(BaseAddress, XQSPIPS_IDR_OFFSET, - XQSPIPS_IXR_DISABLE_ALL); - - /* - * Disable device - */ - XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET, - 0); - - /* - * De-assert slave select lines. - */ - ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET); - ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK); - XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg); - - /* - * Write default value to RX and TX threshold registers - * RX threshold should be set to 1 here because the corresponding - * status bit is used next to clear the RXFIFO - */ - XQspiPs_WriteReg(BaseAddress, XQSPIPS_TXWR_OFFSET, - (XQSPIPS_TXWR_RESET_VALUE & XQSPIPS_TXWR_MASK)); - XQspiPs_WriteReg(BaseAddress, XQSPIPS_RXWR_OFFSET, - (XQSPIPS_RXWR_RESET_VALUE & XQSPIPS_RXWR_MASK)); - - /* - * Clear RXFIFO - */ - while ((XQspiPs_ReadReg(BaseAddress,XQSPIPS_SR_OFFSET) & - XQSPIPS_IXR_RXNEMPTY_MASK) != 0) { - XQspiPs_ReadReg(BaseAddress, XQSPIPS_RXD_OFFSET); - } - - /* - * Clear status register by reading register and - * writing 1 to clear the write to clear bits - */ - XQspiPs_ReadReg(BaseAddress, XQSPIPS_SR_OFFSET); - XQspiPs_WriteReg(BaseAddress, XQSPIPS_SR_OFFSET, - XQSPIPS_IXR_WR_TO_CLR_MASK); - - /* - * Write default value to configuration register - */ - XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, - XQSPIPS_CR_RESET_STATE); - - - /* - * De-select linear mode - */ - XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET, - 0x0); - -} - -/*****************************************************************************/ -/** -* -* Initializes QSPI to Linear mode with default QSPI boot settings. -* -* @param None -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XQspiPs_LinearInit(u32 BaseAddress) -{ - u32 BaudRateDiv; - u32 LinearCfg; - - /* - * Baud rate divisor for dividing by 4. Value of CR bits [5:3] - * should be set to 0x001; hence shift the value and use the mask. - */ - BaudRateDiv = ( (XQSPIPS_CR_PRESC_DIV_BY_4) << - XQSPIPS_CR_PRESC_SHIFT) & XQSPIPS_CR_PRESC_MASK; - /* - * Write configuration register with default values, slave selected & - * pre-scaler value for divide by 4 - */ - XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, - ((XQSPIPS_CR_RESET_STATE | - XQSPIPS_CR_HOLD_B_MASK | BaudRateDiv) & - (~XQSPIPS_CR_SSCTRL_MASK) )); - - /* - * Write linear configuration register with default value - - * enable linear mode and use fast read. - */ - - if(XPAR_PS7_QSPI_0_QSPI_MODE == XQSPIPS_CONNECTION_MODE_SINGLE){ - - LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE; - - }else if(XPAR_PS7_QSPI_0_QSPI_MODE == - XQSPIPS_CONNECTION_MODE_STACKED){ - - LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE | - XQSPIPS_LQSPI_CR_TWO_MEM_MASK; - - }else if(XPAR_PS7_QSPI_0_QSPI_MODE == - XQSPIPS_CONNECTION_MODE_PARALLEL){ - - LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE | - XQSPIPS_LQSPI_CR_TWO_MEM_MASK | - XQSPIPS_LQSPI_CR_SEP_BUS_MASK; - - } - - XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET, - LinearCfg); - - /* - * Enable device - */ - XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET, - XQSPIPS_ER_ENABLE_MASK); - -} - - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/qspips_v2_03_a/src/xqspips_hw.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/qspips_v2_03_a/src/xqspips_hw.h deleted file mode 100644 index 8e77c75abcf174a3a3f59fa46b7dcda03659db6e..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/qspips_v2_03_a/src/xqspips_hw.h +++ /dev/null @@ -1,381 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xqspips_hw.h -* -* This header file contains the identifiers and basic HW access driver -* functions (or macros) that can be used to access the device. Other driver -* functions are defined in xqspips.h. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- ----------------------------------------------- -* 1.00 sdm 11/25/10 First release -* 2.00a ka 07/25/12 Added a few register defines for CR 670297 -* and removed some defines of reserved fields for -* CR 671468 -* Added define XQSPIPS_CR_HOLD_B_MASK for Holdb_dr -* bit in Configuration register. -* 2.01a sg 02/03/13 Added defines for DelayNss,Rx Watermark,Interrupts -* which need write to clear. Removed Read zeros mask from -* LQSPI Config register. -* 2.03a hk 08/22/13 Added prototypes of API's for QSPI reset and -* linear mode initialization for boot. Added related -* constant definitions. -* -* </pre> -* -******************************************************************************/ -#ifndef XQSPIPS_HW_H /* prevent circular inclusions */ -#define XQSPIPS_HW_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xil_io.h" -#include "xparameters.h" - -/************************** Constant Definitions *****************************/ - -/** @name Register Map - * - * Register offsets from the base address of an QSPI device. - * @{ - */ -#define XQSPIPS_CR_OFFSET 0x00 /**< Configuration Register */ -#define XQSPIPS_SR_OFFSET 0x04 /**< Interrupt Status */ -#define XQSPIPS_IER_OFFSET 0x08 /**< Interrupt Enable */ -#define XQSPIPS_IDR_OFFSET 0x0c /**< Interrupt Disable */ -#define XQSPIPS_IMR_OFFSET 0x10 /**< Interrupt Enabled Mask */ -#define XQSPIPS_ER_OFFSET 0x14 /**< Enable/Disable Register */ -#define XQSPIPS_DR_OFFSET 0x18 /**< Delay Register */ -#define XQSPIPS_TXD_00_OFFSET 0x1C /**< Transmit 4-byte inst/data */ -#define XQSPIPS_RXD_OFFSET 0x20 /**< Data Receive Register */ -#define XQSPIPS_SICR_OFFSET 0x24 /**< Slave Idle Count */ -#define XQSPIPS_TXWR_OFFSET 0x28 /**< Transmit FIFO Watermark */ -#define XQSPIPS_RXWR_OFFSET 0x2C /**< Receive FIFO Watermark */ -#define XQSPIPS_GPIO_OFFSET 0x30 /**< GPIO Register */ -#define XQSPIPS_LPBK_DLY_ADJ_OFFSET 0x38 /**< Loopback Delay Adjust Reg */ -#define XQSPIPS_TXD_01_OFFSET 0x80 /**< Transmit 1-byte inst */ -#define XQSPIPS_TXD_10_OFFSET 0x84 /**< Transmit 2-byte inst */ -#define XQSPIPS_TXD_11_OFFSET 0x88 /**< Transmit 3-byte inst */ -#define XQSPIPS_LQSPI_CR_OFFSET 0xA0 /**< Linear QSPI config register */ -#define XQSPIPS_LQSPI_SR_OFFSET 0xA4 /**< Linear QSPI status register */ -#define XQSPIPS_MOD_ID_OFFSET 0xFC /**< Module ID register */ - -/* @} */ - -/** @name Configuration Register - * - * This register contains various control bits that - * affect the operation of the QSPI device. Read/Write. - * @{ - */ - -#define XQSPIPS_CR_IFMODE_MASK 0x80000000 /**< Flash mem interface mode */ -#define XQSPIPS_CR_ENDIAN_MASK 0x04000000 /**< Tx/Rx FIFO endianness */ -#define XQSPIPS_CR_MANSTRT_MASK 0x00010000 /**< Manual Transmission Start */ -#define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start - Enable */ -#define XQSPIPS_CR_SSFORCE_MASK 0x00004000 /**< Force Slave Select */ -#define XQSPIPS_CR_SSCTRL_MASK 0x00000400 /**< Slave Select Decode */ -#define XQSPIPS_CR_SSCTRL_SHIFT 10 /**< Slave Select Decode shift */ -#define XQSPIPS_CR_DATA_SZ_MASK 0x000000C0 /**< Size of word to be - transferred */ -#define XQSPIPS_CR_PRESC_MASK 0x00000038 /**< Prescaler Setting */ -#define XQSPIPS_CR_PRESC_SHIFT 3 /**< Prescaler shift */ -#define XQSPIPS_CR_PRESC_MAXIMUM 0x07 /**< Prescaler maximum value */ - -#define XQSPIPS_CR_CPHA_MASK 0x00000004 /**< Phase Configuration */ -#define XQSPIPS_CR_CPOL_MASK 0x00000002 /**< Polarity Configuration */ - -#define XQSPIPS_CR_MSTREN_MASK 0x00000001 /**< Master Mode Enable */ - -#define XQSPIPS_CR_HOLD_B_MASK 0x00080000 /**< HOLD_B Pin Drive Enable */ - -/* Deselect the Slave select line and set the transfer size to 32 at reset */ -#define XQSPIPS_CR_RESET_STATE (XQSPIPS_CR_IFMODE_MASK | \ - XQSPIPS_CR_SSCTRL_MASK | \ - XQSPIPS_CR_DATA_SZ_MASK | \ - XQSPIPS_CR_MSTREN_MASK) -/* @} */ - - -/** @name QSPI Interrupt Registers - * - * <b>QSPI Status Register</b> - * - * This register holds the interrupt status flags for an QSPI device. Some - * of the flags are level triggered, which means that they are set as long - * as the interrupt condition exists. Other flags are edge triggered, - * which means they are set once the interrupt condition occurs and remain - * set until they are cleared by software. The interrupts are cleared by - * writing a '1' to the interrupt bit position in the Status Register. - * Read/Write. - * - * <b>QSPI Interrupt Enable Register</b> - * - * This register is used to enable chosen interrupts for an QSPI device. - * Writing a '1' to a bit in this register sets the corresponding bit in the - * QSPI Interrupt Mask register. Write only. - * - * <b>QSPI Interrupt Disable Register </b> - * - * This register is used to disable chosen interrupts for an QSPI device. - * Writing a '1' to a bit in this register clears the corresponding bit in the - * QSPI Interrupt Mask register. Write only. - * - * <b>QSPI Interrupt Mask Register</b> - * - * This register shows the enabled/disabled interrupts of an QSPI device. - * Read only. - * - * All four registers have the same bit definitions. They are only defined once - * for each of the Interrupt Enable Register, Interrupt Disable Register, - * Interrupt Mask Register, and Channel Interrupt Status Register - * @{ - */ - -#define XQSPIPS_IXR_TXUF_MASK 0x00000040 /**< QSPI Tx FIFO Underflow */ -#define XQSPIPS_IXR_RXFULL_MASK 0x00000020 /**< QSPI Rx FIFO Full */ -#define XQSPIPS_IXR_RXNEMPTY_MASK 0x00000010 /**< QSPI Rx FIFO Not Empty */ -#define XQSPIPS_IXR_TXFULL_MASK 0x00000008 /**< QSPI Tx FIFO Full */ -#define XQSPIPS_IXR_TXOW_MASK 0x00000004 /**< QSPI Tx FIFO Overwater */ -#define XQSPIPS_IXR_RXOVR_MASK 0x00000001 /**< QSPI Rx FIFO Overrun */ -#define XQSPIPS_IXR_DFLT_MASK 0x00000025 /**< QSPI default interrupts - mask */ -#define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041 /**< Interrupts which - need write to clear */ -#define XQSPIPS_ISR_RESET_STATE 0x00000004 /**< Default to tx/rx empty */ -#define XQSPIPS_IXR_DISABLE_ALL 0x0000007D /**< Disable all interrupts */ -/* @} */ - - -/** @name Enable Register - * - * This register is used to enable or disable an QSPI device. - * Read/Write - * @{ - */ -#define XQSPIPS_ER_ENABLE_MASK 0x00000001 /**< QSPI Enable Bit Mask */ -/* @} */ - - -/** @name Delay Register - * - * This register is used to program timing delays in - * slave mode. Read/Write - * @{ - */ -#define XQSPIPS_DR_NSS_MASK 0xFF000000 /**< Delay to de-assert slave select - between two words mask */ -#define XQSPIPS_DR_NSS_SHIFT 24 /**< Delay to de-assert slave select - between two words shift */ -#define XQSPIPS_DR_BTWN_MASK 0x00FF0000 /**< Delay Between Transfers - mask */ -#define XQSPIPS_DR_BTWN_SHIFT 16 /**< Delay Between Transfers shift */ -#define XQSPIPS_DR_AFTER_MASK 0x0000FF00 /**< Delay After Transfers mask */ -#define XQSPIPS_DR_AFTER_SHIFT 8 /**< Delay After Transfers shift */ -#define XQSPIPS_DR_INIT_MASK 0x000000FF /**< Delay Initially mask */ -/* @} */ - -/** @name Slave Idle Count Registers - * - * This register defines the number of pclk cycles the slave waits for a the - * QSPI clock to become stable in quiescent state before it can detect the start - * of the next transfer in CPHA = 1 mode. - * Read/Write - * - * @{ - */ -#define XQSPIPS_SICR_MASK 0x000000FF /**< Slave Idle Count Mask */ -/* @} */ - - -/** @name Transmit FIFO Watermark Register - * - * This register defines the watermark setting for the Transmit FIFO. - * - * @{ - */ -#define XQSPIPS_TXWR_MASK 0x0000003F /**< Transmit Watermark Mask */ -#define XQSPIPS_TXWR_RESET_VALUE 0x00000001 /**< Transmit Watermark - * register reset value */ - -/* @} */ - -/** @name Receive FIFO Watermark Register - * - * This register defines the watermark setting for the Receive FIFO. - * - * @{ - */ -#define XQSPIPS_RXWR_MASK 0x0000003F /**< Receive Watermark Mask */ -#define XQSPIPS_RXWR_RESET_VALUE 0x00000001 /**< Receive Watermark - * register reset value */ - -/* @} */ - -/** @name FIFO Depth - * - * This macro provides the depth of transmit FIFO and receive FIFO. - * - * @{ - */ -#define XQSPIPS_FIFO_DEPTH 63 /**< FIFO depth (words) */ -/* @} */ - - -/** @name Linear QSPI Configuration Register - * - * This register contains various control bits that - * affect the operation of the Linear QSPI controller. Read/Write. - * - * @{ - */ -#define XQSPIPS_LQSPI_CR_LINEAR_MASK 0x80000000 /**< LQSPI mode enable */ -#define XQSPIPS_LQSPI_CR_TWO_MEM_MASK 0x40000000 /**< Both memories or one */ -#define XQSPIPS_LQSPI_CR_SEP_BUS_MASK 0x20000000 /**< Seperate memory bus */ -#define XQSPIPS_LQSPI_CR_U_PAGE_MASK 0x10000000 /**< Upper memory page */ -#define XQSPIPS_LQSPI_CR_MODE_EN_MASK 0x02000000 /**< Enable mode bits */ -#define XQSPIPS_LQSPI_CR_MODE_ON_MASK 0x01000000 /**< Mode on */ -#define XQSPIPS_LQSPI_CR_MODE_BITS_MASK 0x00FF0000 /**< Mode value for dual I/O - or quad I/O */ -#define XQSPIPS_LQSPI_CR_DUMMY_MASK 0x00000700 /**< Number of dummy bytes - between addr and return - read data */ -#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF /**< Read instr code */ -#define XQSPIPS_LQSPI_CR_RST_STATE 0x8000016B /**< Default CR value */ -/* @} */ - -/** @name Linear QSPI Status Register - * - * This register contains various status bits of the Linear QSPI controller. - * Read/Write. - * - * @{ - */ -#define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK 0x00000004 /**< AXI Data FSM Error - received */ -#define XQSPIPS_LQSPI_SR_WR_RECVD_MASK 0x00000002 /**< AXI write command - received */ -/* @} */ - - -/** @name Loopback Delay Adjust Register - * - * This register contains various bit masks of Loopback Delay Adjust Register. - * - * @{ - */ - -#define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 /**< Loopback Bit */ - -/* @} */ - - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -#define XQspiPs_In32 Xil_In32 -#define XQspiPs_Out32 Xil_Out32 - -/****************************************************************************/ -/** -* Read a register. -* -* @param BaseAddress contains the base address of the device. -* @param RegOffset contains the offset from the 1st register of the -* device to the target register. -* -* @return The value read from the register. -* -* @note C-Style signature: -* u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset) -* -******************************************************************************/ -#define XQspiPs_ReadReg(BaseAddress, RegOffset) \ - XQspiPs_In32((BaseAddress) + (RegOffset)) - -/***************************************************************************/ -/** -* Write to a register. -* -* @param BaseAddress contains the base address of the device. -* @param RegOffset contains the offset from the 1st register of the -* device to target register. -* @param RegisterValue is the value to be written to the register. -* -* @return None. -* -* @note C-Style signature: -* void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset, -* u32 RegisterValue) -* -******************************************************************************/ -#define XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ - XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue)) - -/************************** Function Prototypes ******************************/ - -/* - * Functions implemented in xqspips_hw.c - */ -void XQspiPs_ResetHw(u32 BaseAddress); -void XQspiPs_LinearInit(u32 BaseAddress); - -/************************** Variable Definitions *****************************/ - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/qspips_v2_03_a/src/xqspips_options.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/qspips_v2_03_a/src/xqspips_options.c deleted file mode 100644 index f3cbe8b48eed1c2f59dcf080377e6a8a7d2f102a..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/qspips_v2_03_a/src/xqspips_options.c +++ /dev/null @@ -1,434 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xqspips_options.c -* -* Contains functions for the configuration of the XQspiPs driver component. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- ----------------------------------------------- -* 1.00 sdm 11/25/10 First release -* 2.00a kka 07/25/12 Removed the selection for the following options: -* Master mode (XQSPIPS_MASTER_OPTION) and -* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option -* as the QSPI driver supports the Master mode -* and Flash Interface mode. The driver doesnot support -* Slave mode or the legacy mode. -* Added the option for setting the Holdb_dr bit in the -* configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION -* is the option to be used for setting this bit in the -* configuration register. -* 2.01a sg 02/03/13 SetDelays and GetDelays API's include DelayNss parameter. -* -* 2.02a hk 26/03/13 Removed XQspi_Reset() in Set_Options() function when -* LQSPI_MODE_OPTION is set. Moved Enable() to XQpsiPs_LqspiRead(). -*</pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xqspips.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/************************** Variable Definitions *****************************/ - -/* - * Create the table of options which are processed to get/set the device - * options. These options are table driven to allow easy maintenance and - * expansion of the options. - */ -typedef struct { - u32 Option; - u32 Mask; -} OptionsMap; - -static OptionsMap OptionsTable[] = { - {XQSPIPS_CLK_ACTIVE_LOW_OPTION, XQSPIPS_CR_CPOL_MASK}, - {XQSPIPS_CLK_PHASE_1_OPTION, XQSPIPS_CR_CPHA_MASK}, - {XQSPIPS_FORCE_SSELECT_OPTION, XQSPIPS_CR_SSFORCE_MASK}, - {XQSPIPS_MANUAL_START_OPTION, XQSPIPS_CR_MANSTRTEN_MASK}, - {XQSPIPS_HOLD_B_DRIVE_OPTION, XQSPIPS_CR_HOLD_B_MASK}, -}; - -#define XQSPIPS_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(OptionsMap)) - -/*****************************************************************************/ -/** -* -* This function sets the options for the QSPI device driver. The options control -* how the device behaves relative to the QSPI bus. The device must be idle -* rather than busy transferring data before setting these device options. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* @param Options contains the specified options to be set. This is a bit -* mask where a 1 means to turn the option on, and a 0 means to -* turn the option off. One or more bit values may be contained in -* the mask. See the bit definitions named XQSPIPS_*_OPTIONS in -* the file xqspips.h. -* -* @return -* - XST_SUCCESS if options are successfully set. -* - XST_DEVICE_BUSY if the device is currently transferring data. -* The transfer must complete or be aborted before setting options. -* -* @note -* This function is not thread-safe. -* -******************************************************************************/ -int XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options) -{ - u32 ConfigReg; - unsigned int Index; - u32 QspiOptions; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Do not allow to modify the Control Register while a transfer is in - * progress. Not thread-safe. - */ - if (InstancePtr->IsBusy) { - return XST_DEVICE_BUSY; - } - - QspiOptions = Options & XQSPIPS_LQSPI_MODE_OPTION; - Options &= ~XQSPIPS_LQSPI_MODE_OPTION; - - ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); - - /* - * Loop through the options table, turning the option on or off - * depending on whether the bit is set in the incoming options flag. - */ - for (Index = 0; Index < XQSPIPS_NUM_OPTIONS; Index++) { - if (Options & OptionsTable[Index].Option) { - /* Turn it on */ - ConfigReg |= OptionsTable[Index].Mask; - } else { - /* Turn it off */ - ConfigReg &= ~(OptionsTable[Index].Mask); - } - } - - /* - * Now write the control register. Leave it to the upper layers - * to restart the device. - */ - XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET, - ConfigReg); - - /* - * Check for the LQSPI configuration options. - */ - ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_LQSPI_CR_OFFSET); - - - if (QspiOptions & XQSPIPS_LQSPI_MODE_OPTION) { - XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_LQSPI_CR_OFFSET, - XQSPIPS_LQSPI_CR_RST_STATE); - XQspiPs_SetSlaveSelect(InstancePtr); - } else { - ConfigReg &= ~XQSPIPS_LQSPI_CR_LINEAR_MASK; - XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_LQSPI_CR_OFFSET, ConfigReg); - } - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* This function gets the options for the QSPI device. The options control how -* the device behaves relative to the QSPI bus. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* -* @return -* -* Options contains the specified options currently set. This is a bit value -* where a 1 means the option is on, and a 0 means the option is off. -* See the bit definitions named XQSPIPS_*_OPTIONS in file xqspips.h. -* -* @note None. -* -******************************************************************************/ -u32 XQspiPs_GetOptions(XQspiPs *InstancePtr) -{ - u32 OptionsFlag = 0; - u32 ConfigReg; - unsigned int Index; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Get the current options from QSPI configuration register. - */ - ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); - - /* - * Loop through the options table to grab options - */ - for (Index = 0; Index < XQSPIPS_NUM_OPTIONS; Index++) { - if (ConfigReg & OptionsTable[Index].Mask) { - OptionsFlag |= OptionsTable[Index].Option; - } - } - - /* - * Check for the LQSPI configuration options. - */ - ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_LQSPI_CR_OFFSET); - - if ((ConfigReg & XQSPIPS_LQSPI_CR_LINEAR_MASK) != 0) { - OptionsFlag |= XQSPIPS_LQSPI_MODE_OPTION; - } - - return OptionsFlag; -} - -/*****************************************************************************/ -/** -* -* This function sets the clock prescaler for an QSPI device. The device -* must be idle rather than busy transferring data before setting these device -* options. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* @param Prescaler is the value that determine how much the clock should -* be divided by. Use the XQSPIPS_CLK_PRESCALE_* constants defined -* in xqspips.h for this setting. -* -* @return -* - XST_SUCCESS if options are successfully set. -* - XST_DEVICE_BUSY if the device is currently transferring data. -* The transfer must complete or be aborted before setting options. -* -* @note -* This function is not thread-safe. -* -******************************************************************************/ -int XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler) -{ - u32 ConfigReg; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(Prescaler <= XQSPIPS_CR_PRESC_MAXIMUM); - - /* - * Do not allow the slave select to change while a transfer is in - * progress. Not thread-safe. - */ - if (InstancePtr->IsBusy) { - return XST_DEVICE_BUSY; - } - - /* - * Read the configuration register, mask out the interesting bits, and set - * them with the shifted value passed into the function. Write the - * results back to the configuration register. - */ - ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); - - ConfigReg &= ~XQSPIPS_CR_PRESC_MASK; - ConfigReg |= (u32) (Prescaler & XQSPIPS_CR_PRESC_MAXIMUM) << - XQSPIPS_CR_PRESC_SHIFT; - - XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET, - ConfigReg); - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* This function gets the clock prescaler of an QSPI device. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* -* @return The prescaler value. -* -* @note None. -* -* -******************************************************************************/ -u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr) -{ - u32 ConfigReg; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); - - ConfigReg &= XQSPIPS_CR_PRESC_MASK; - - return (u8)(ConfigReg >> XQSPIPS_CR_PRESC_SHIFT); -} - -/*****************************************************************************/ -/** -* -* This function sets the delay register for the QSPI device driver. -* The delay register controls the Delay Between Transfers, Delay After -* Transfers, and the Delay Initially. The default value is 0x0. The range of -* each delay value is 0-255. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* @param DelayNss is the delay to de-assert slave select between -* two word transfers. -* @param DelayBtwn is the delay between one Slave Select being -* de-activated and the activation of another slave. The delay is -* the number of master clock periods given by DelayBtwn + 2. -* @param DelayAfter define the delay between the last bit of the current -* byte transfer and the first bit of the next byte transfer. -* The delay in number of master clock periods is given as: -* CHPA=0:DelayInit+DelayAfter+3 -* CHPA=1:DelayAfter+1 -* @param DelayInit is the delay between asserting the slave select signal -* and the first bit transfer. The delay int number of master clock -* periods is DelayInit+1. -* -* @return -* - XST_SUCCESS if delays are successfully set. -* - XST_DEVICE_BUSY if the device is currently transferring data. -* The transfer must complete or be aborted before setting options. -* -* @note None. -* -******************************************************************************/ -int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn, - u8 DelayAfter, u8 DelayInit) -{ - u32 DelayRegister; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Do not allow the delays to change while a transfer is in - * progress. Not thread-safe. - */ - if (InstancePtr->IsBusy) { - return XST_DEVICE_BUSY; - } - - /* Shift, Mask and OR the values to build the register settings */ - DelayRegister = (u32) DelayNss << XQSPIPS_DR_NSS_SHIFT; - DelayRegister |= (u32) DelayBtwn << XQSPIPS_DR_BTWN_SHIFT; - DelayRegister |= (u32) DelayAfter << XQSPIPS_DR_AFTER_SHIFT; - DelayRegister |= (u32) DelayInit; - - XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPS_DR_OFFSET, DelayRegister); - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* This function gets the delay settings for an QSPI device. -* The delay register controls the Delay Between Transfers, Delay After -* Transfers, and the Delay Initially. The default value is 0x0. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* @param DelayNss is a pointer to the Delay to de-assert slave select -* between two word transfers. -* @param DelayBtwn is a pointer to the Delay Between transfers value. -* This is a return parameter. -* @param DelayAfter is a pointer to the Delay After transfer value. -* This is a return parameter. -* @param DelayInit is a pointer to the Delay Initially value. This is -* a return parameter. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn, - u8 *DelayAfter, u8 *DelayInit) -{ - u32 DelayRegister; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - DelayRegister = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_DR_OFFSET); - - *DelayInit = (u8)(DelayRegister & XQSPIPS_DR_INIT_MASK); - - *DelayAfter = (u8)((DelayRegister & XQSPIPS_DR_AFTER_MASK) >> - XQSPIPS_DR_AFTER_SHIFT); - - *DelayBtwn = (u8)((DelayRegister & XQSPIPS_DR_BTWN_MASK) >> - XQSPIPS_DR_BTWN_SHIFT); - - *DelayNss = (u8)((DelayRegister & XQSPIPS_DR_NSS_MASK) >> - XQSPIPS_DR_NSS_SHIFT); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/qspips_v2_03_a/src/xqspips_selftest.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/qspips_v2_03_a/src/xqspips_selftest.c deleted file mode 100644 index 9ad32eaa2235f4bbb299e92f17485475eabe3f77..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/qspips_v2_03_a/src/xqspips_selftest.c +++ /dev/null @@ -1,159 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xqspips_selftest.c -* -* This file contains the implementation of selftest function for the QSPI -* device. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- ----------------------------------------------- -* 1.00 sdm 11/25/10 First release -* 2.01a sg 02/03/13 Delay Register test is added with DelayNss parameter. -* -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xqspips.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/************************** Variable Definitions *****************************/ - -/*****************************************************************************/ -/** -* -* Runs a self-test on the driver/device. The self-test is destructive in that -* a reset of the device is performed in order to check the reset values of -* the registers and to get the device into a known state. -* -* Upon successful return from the self-test, the device is reset. -* -* @param InstancePtr is a pointer to the XQspiPs instance. -* -* @return -* - XST_SUCCESS if successful -* - XST_REGISTER_ERROR indicates a register did not read or write -* correctly. -* -* @note None. -* -******************************************************************************/ -int XQspiPs_SelfTest(XQspiPs *InstancePtr) -{ - int Status; - u32 Register; - u8 DelayTestNss; - u8 DelayTestBtwn; - u8 DelayTestAfter; - u8 DelayTestInit; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Reset the QSPI device to leave it in a known good state - */ - XQspiPs_Reset(InstancePtr); - - /* - * All the QSPI registers should be in their default state right now. - */ - Register = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_CR_OFFSET); - if (Register != XQSPIPS_CR_RESET_STATE) { - return XST_REGISTER_ERROR; - } - - Register = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, - XQSPIPS_SR_OFFSET); - if (Register != XQSPIPS_ISR_RESET_STATE) { - return XST_REGISTER_ERROR; - } - - DelayTestNss = 0x5A; - DelayTestBtwn = 0xA5; - DelayTestAfter = 0xAA; - DelayTestInit = 0x55; - - /* - * Write and read the delay register, just to be sure there is some - * hardware out there. - */ - Status = XQspiPs_SetDelays(InstancePtr, DelayTestNss, DelayTestBtwn, - DelayTestAfter, DelayTestInit); - if (Status != XST_SUCCESS) { - return Status; - } - - XQspiPs_GetDelays(InstancePtr, &DelayTestNss, &DelayTestBtwn, - &DelayTestAfter, &DelayTestInit); - if ((0x5A != DelayTestNss) || (0xA5 != DelayTestBtwn) || - (0xAA != DelayTestAfter) || (0x55 != DelayTestInit)) { - return XST_REGISTER_ERROR; - } - - Status = XQspiPs_SetDelays(InstancePtr, 0, 0, 0, 0); - if (Status != XST_SUCCESS) { - return Status; - } - - /* - * Reset the QSPI device to leave it in a known good state - */ - XQspiPs_Reset(InstancePtr); - - return XST_SUCCESS; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/qspips_v2_03_a/src/xqspips_sinit.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/qspips_v2_03_a/src/xqspips_sinit.c deleted file mode 100644 index 27ba3750bb512d6829467e3256321e2c497c7f74..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/qspips_v2_03_a/src/xqspips_sinit.c +++ /dev/null @@ -1,106 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xqspips_sinit.c -* -* The implementation of the XQspiPs component's static initialization -* functionality. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- ----------------------------------------------- -* 1.00 sdm 11/25/10 First release -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xstatus.h" -#include "xqspips.h" -#include "xparameters.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/************************** Variable Definitions *****************************/ - -extern XQspiPs_Config XQspiPs_ConfigTable[]; - -/*****************************************************************************/ -/** -* -* Looks up the device configuration based on the unique device ID. A table -* contains the configuration info for each device in the system. -* -* @param DeviceId contains the ID of the device to look up the -* configuration for. -* -* @return -* -* A pointer to the configuration found or NULL if the specified device ID was -* not found. See xqspips.h for the definition of XQspiPs_Config. -* -* @note None. -* -******************************************************************************/ -XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId) -{ - XQspiPs_Config *CfgPtr = NULL; - int Index; - - for (Index = 0; Index < XPAR_XQSPIPS_NUM_INSTANCES; Index++) { - if (XQspiPs_ConfigTable[Index].DeviceId == DeviceId) { - CfgPtr = &XQspiPs_ConfigTable[Index]; - break; - } - } - return CfgPtr; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scugic_v1_05_a/src/Makefile b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scugic_v1_05_a/src/Makefile deleted file mode 100644 index f32ad9b52cb441b1d261cc6d8bfe41a55fab986a..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scugic_v1_05_a/src/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -COMPILER= -ARCHIVER= -CP=cp -COMPILER_FLAGS= -EXTRA_COMPILER_FLAGS= -LIB=libxil.a - -CC_FLAGS = $(COMPILER_FLAGS) -ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) - -RELEASEDIR=../../../lib -INCLUDEDIR=../../../include -INCLUDES=-I./. -I${INCLUDEDIR} - -OUTS = *.o - -LIBSOURCES:=*.c -INCLUDEFILES:=*.h - -OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) - -libs: banner scugic_libs clean - -%.o: %.c - ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< - -banner: - echo "Compiling scugic" - -scugic_libs: ${OBJECTS} - $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} - -.PHONY: include -include: scugic_includes - -scugic_includes: - ${CP} ${INCLUDEFILES} ${INCLUDEDIR} - -clean: - rm -rf ${OBJECTS} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scugic_v1_05_a/src/xscugic.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scugic_v1_05_a/src/xscugic.c deleted file mode 100644 index 8847646a03d9aa0512561baf26e2570815be9e1c..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scugic_v1_05_a/src/xscugic.c +++ /dev/null @@ -1,716 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xscugic.c -* -* Contains required functions for the XScuGic driver for the Interrupt -* Controller. See xscugic.h for a detailed description of the driver. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- -------------------------------------------------------- -* 1.00a drg 01/19/10 First release -* 1.01a sdm 11/09/11 Changes are made in function XScuGic_CfgInitialize. Since -* "Config" entry is now made as pointer in the XScuGic -* structure, necessary changes are made. -* The HandlerTable can now be populated through the low -* level routine XScuGic_RegisterHandler added in this -* release. Hence necessary checks are added not to -* overwrite the HandlerTable entriesin function -* XScuGic_CfgInitialize. -* 1.03a srt 02/27/13 Added APIs -* - XScuGic_SetPriTrigTypeByDistAddr() -* - XScuGic_GetPriTrigTypeByDistAddr() -* Removed Offset calculation macros, defined in _hw.h -* (CR 702687) -* Added support to direct interrupts to the appropriate CPU. Earlier -* interrupts were directed to CPU1 (hard coded). Now depending -* upon the CPU selected by the user (xparameters.h), interrupts -* will be directed to the relevant CPU. This fixes CR 699688. -* -* 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in -* XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings. -* Moved functions XScuGic_SetPriTrigTypeByDistAddr and -* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c. -* This is fix for CR#705621. -* -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ -#include "xparameters.h" -#include "xil_types.h" -#include "xil_assert.h" -#include "xscugic.h" - - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Variable Definitions *****************************/ - -/************************** Function Prototypes ******************************/ - -static void StubHandler(void *CallBackRef); - -/*****************************************************************************/ -/** -* -* DistInit initializes the distributor of the GIC. The -* initialization entails: -* -* - Write the trigger mode, priority and target CPU -* - All interrupt sources are disabled -* - Enable the distributor -* -* @param InstancePtr is a pointer to the XScuGic instance. -* @param CpuID is the Cpu ID to be initialized. -* -* @return None -* -* @note None. -* -******************************************************************************/ -static void DistInit(XScuGic *InstancePtr, u32 CpuID) -{ - u32 Int_Id; - -#if USE_AMP==1 - #warning "Building GIC for AMP" - - /* - * The distrubutor should not be initialized by FreeRTOS in the case of - * AMP -- it is assumed that Linux is the master of this device in that - * case. - */ - return; -#endif - - XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0UL); - - /* - * Set the security domains in the int_security registers for - * non-secure interrupts - * All are secure, so leave at the default. Set to 1 for non-secure - * interrupts. - */ - - /* - * For the Shared Peripheral Interrupts INT_ID[MAX..32], set: - */ - - /* - * 1. The trigger mode in the int_config register - * Only write to the SPI interrupts, so start at 32 - */ - for (Int_Id = 32; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id+=16) { - /* - * Each INT_ID uses two bits, or 16 INT_ID per register - * Set them all to be level sensitive, active HIGH. - */ - XScuGic_DistWriteReg(InstancePtr, - XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id), - 0UL); - } - - -#define DEFAULT_PRIORITY 0xa0a0a0a0UL - for (Int_Id = 0; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id+=4) { - /* - * 2. The priority using int the priority_level register - * The priority_level and spi_target registers use one byte per - * INT_ID. - * Write a default value that can be changed elsewhere. - */ - XScuGic_DistWriteReg(InstancePtr, - XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id), - DEFAULT_PRIORITY); - } - - for (Int_Id = 32; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id+=4) { - /* - * 3. The CPU interface in the spi_target register - * Only write to the SPI interrupts, so start at 32 - */ - CpuID |= CpuID << 8; - CpuID |= CpuID << 16; - - XScuGic_DistWriteReg(InstancePtr, - XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), - CpuID); - } - - for (Int_Id = 0; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id+=32) { - /* - * 4. Enable the SPI using the enable_set register. Leave all - * disabled for now. - */ - XScuGic_DistWriteReg(InstancePtr, - XSCUGIC_ENABLE_DISABLE_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET, Int_Id), - 0xFFFFFFFFUL); - - } - - XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, - XSCUGIC_EN_INT_MASK); - -} - -/*****************************************************************************/ -/** -* -* CPUInit initializes the CPU Interface of the GIC. The initialization entails: -* -* - Set the priority of the CPU -* - Enable the CPU interface -* -* @param InstancePtr is a pointer to the XScuGic instance. -* -* @return None -* -* @note None. -* -******************************************************************************/ -static void CPUInit(XScuGic *InstancePtr) -{ - /* - * Program the priority mask of the CPU using the Priority mask register - */ - XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_CPU_PRIOR_OFFSET, 0xF0); - - - /* - * If the CPU operates in both security domains, set parameters in the - * control_s register. - * 1. Set FIQen=1 to use FIQ for secure interrupts, - * 2. Program the AckCtl bit - * 3. Program the SBPR bit to select the binary pointer behavior - * 4. Set EnableS = 1 to enable secure interrupts - * 5. Set EnbleNS = 1 to enable non secure interrupts - */ - - /* - * If the CPU operates only in the secure domain, setup the - * control_s register. - * 1. Set FIQen=1, - * 2. Set EnableS=1, to enable the CPU interface to signal secure interrupts. - * Only enable the IRQ output unless secure interrupts are needed. - */ - XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_CONTROL_OFFSET, 0x07); - -} - -/*****************************************************************************/ -/** -* -* CfgInitialize a specific interrupt controller instance/driver. The -* initialization entails: -* -* - Initialize fields of the XScuGic structure -* - Initial vector table with stub function calls -* - All interrupt sources are disabled -* -* @param InstancePtr is a pointer to the XScuGic instance. -* @param ConfigPtr is a pointer to a config table for the particular -* device this driver is associated with. -* @param EffectiveAddr is the device base address in the virtual memory -* address space. The caller is responsible for keeping the address -* mapping from EffectiveAddr to the device physical base address -* unchanged once this function is invoked. Unexpected errors may -* occur if the address mapping changes after this function is -* called. If address translation is not used, use -* Config->BaseAddress for this parameters, passing the physical -* address instead. -* -* @return -* - XST_SUCCESS if initialization was successful -* -* @note None. -* -******************************************************************************/ -int XScuGic_CfgInitialize(XScuGic *InstancePtr, - XScuGic_Config *ConfigPtr, - u32 EffectiveAddr) -{ - u32 Int_Id; - u8 Cpu_Id = XPAR_CPU_ID + 1; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(ConfigPtr != NULL); - - /* - * Set some default values - */ - InstancePtr->Config->CpuBaseAddress = EffectiveAddr; - InstancePtr->IsReady = 0; - InstancePtr->Config = ConfigPtr; - - - for (Int_Id = 0; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id++) { - /* - * Initalize the handler to point to a stub to handle an - * interrupt which has not been connected to a handler. Only - * initialize it if the handler is 0 which means it was not - * initialized statically by the tools/user. Set the callback - * reference to this instance so that unhandled interrupts - * can be tracked. - */ - if ((InstancePtr->Config->HandlerTable[Int_Id].Handler == 0)) { - InstancePtr->Config->HandlerTable[Int_Id].Handler = - StubHandler; - } - InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = - InstancePtr; - } - - DistInit(InstancePtr, Cpu_Id); - CPUInit(InstancePtr); - - InstancePtr->IsReady = XIL_COMPONENT_IS_READY; - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* Makes the connection between the Int_Id of the interrupt source and the -* associated handler that is to run when the interrupt is recognized. The -* argument provided in this call as the Callbackref is used as the argument -* for the handler when it is called. -* -* @param InstancePtr is a pointer to the XScuGic instance. -* @param Int_Id contains the ID of the interrupt source and should be -* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1 -* @param Handler to the handler for that interrupt. -* @param CallBackRef is the callback reference, usually the instance -* pointer of the connecting driver. -* -* @return -* -* - XST_SUCCESS if the handler was connected correctly. -* -* @note -* -* WARNING: The handler provided as an argument will overwrite any handler -* that was previously connected. -* -****************************************************************************/ -int XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id, - Xil_InterruptHandler Handler, void *CallBackRef) -{ - /* - * Assert the arguments - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS); - Xil_AssertNonvoid(Handler != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * The Int_Id is used as an index into the table to select the proper - * handler - */ - InstancePtr->Config->HandlerTable[Int_Id].Handler = Handler; - InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = CallBackRef; - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* Updates the interrupt table with the Null Handler and NULL arguments at the -* location pointed at by the Int_Id. This effectively disconnects that interrupt -* source from any handler. The interrupt is disabled also. -* -* @param InstancePtr is a pointer to the XScuGic instance to be worked on. -* @param Int_Id contains the ID of the interrupt source and should -* be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1 -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id) -{ - u32 Mask; - - /* - * Assert the arguments - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * The Int_Id is used to create the appropriate mask for the - * desired bit position. Int_Id currently limited to 0 - 31 - */ - Mask = 0x00000001 << (Int_Id % 32); - - /* - * Disable the interrupt such that it won't occur while disconnecting - * the handler, only disable the specified interrupt id without modifying - * the other interrupt ids - */ - XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DISABLE_OFFSET + - ((Int_Id / 32) * 4), Mask); - - /* - * Disconnect the handler and connect a stub, the callback reference - * must be set to this instance to allow unhandled interrupts to be - * tracked - */ - InstancePtr->Config->HandlerTable[Int_Id].Handler = StubHandler; - InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = InstancePtr; -} - -/*****************************************************************************/ -/** -* -* Enables the interrupt source provided as the argument Int_Id. Any pending -* interrupt condition for the specified Int_Id will occur after this function is -* called. -* -* @param InstancePtr is a pointer to the XScuGic instance. -* @param Int_Id contains the ID of the interrupt source and should be -* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1 -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id) -{ - u32 Mask; - - /* - * Assert the arguments - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * The Int_Id is used to create the appropriate mask for the - * desired bit position. Int_Id currently limited to 0 - 31 - */ - Mask = 0x00000001 << (Int_Id % 32); - - /* - * Enable the selected interrupt source by setting the - * corresponding bit in the Enable Set register. - */ - XScuGic_DistWriteReg(InstancePtr, XSCUGIC_ENABLE_SET_OFFSET + - ((Int_Id / 32) * 4), Mask); -} - -/*****************************************************************************/ -/** -* -* Disables the interrupt source provided as the argument Int_Id such that the -* interrupt controller will not cause interrupts for the specified Int_Id. The -* interrupt controller will continue to hold an interrupt condition for the -* Int_Id, but will not cause an interrupt. -* -* @param InstancePtr is a pointer to the XScuGic instance. -* @param Int_Id contains the ID of the interrupt source and should be -* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1 -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id) -{ - u32 Mask; - - /* - * Assert the arguments - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * The Int_Id is used to create the appropriate mask for the - * desired bit position. Int_Id currently limited to 0 - 31 - */ - Mask = 0x00000001 << (Int_Id % 32); - - /* - * Disable the selected interrupt source by setting the - * corresponding bit in the IDR. - */ - XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DISABLE_OFFSET + - ((Int_Id / 32) * 4), Mask); -} - -/*****************************************************************************/ -/** -* -* Allows software to simulate an interrupt in the interrupt controller. This -* function will only be successful when the interrupt controller has been -* started in simulation mode. A simulated interrupt allows the interrupt -* controller to be tested without any device to drive an interrupt input -* signal into it. -* -* @param InstancePtr is a pointer to the XScuGic instance. -* @param Int_Id is the software interrupt ID to simulate an interrupt. -* @param Cpu_Id is the list of CPUs to send the interrupt. -* -* @return -* -* XST_SUCCESS if successful, or XST_FAILURE if the interrupt could not be -* simulated -* -* @note None. -* -******************************************************************************/ -int XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id) -{ - u32 Mask; - - /* - * Assert the arguments - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(Int_Id <= 15) ; - Xil_AssertNonvoid(Cpu_Id <= 255) ; - - - /* - * The Int_Id is used to create the appropriate mask for the - * desired interrupt. Int_Id currently limited to 0 - 15 - * Use the target list for the Cpu ID. - */ - Mask = ((Cpu_Id << 16) | Int_Id) & - (XSCUGIC_SFI_TRIG_CPU_MASK | XSCUGIC_SFI_TRIG_INTID_MASK); - - /* - * Write to the Software interrupt trigger register. Use the appropriate - * CPU Int_Id. - */ - XScuGic_DistWriteReg(InstancePtr, XSCUGIC_SFI_TRIG_OFFSET, Mask); - - /* Indicate the interrupt was successfully simulated */ - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* A stub for the asynchronous callback. The stub is here in case the upper -* layers forget to set the handler. -* -* @param CallBackRef is a pointer to the upper layer callback reference -* -* @return None. -* -* @note None. -* -******************************************************************************/ -static void StubHandler(void *CallBackRef) { - /* - * verify that the inputs are valid - */ - Xil_AssertVoid(CallBackRef != NULL); - - /* - * Indicate another unhandled interrupt for stats - */ - ((XScuGic *)CallBackRef)->UnhandledInterrupts++; -} - -/****************************************************************************/ -/** -* Sets the interrupt priority and trigger type for the specificd IRQ source. -* -* @param InstancePtr is a pointer to the instance to be worked on. -* @param Int_Id is the IRQ source number to modify -* @param Priority is the new priority for the IRQ source. 0 is highest -* priority, 0xF8 (248) is lowest. There are 32 priority levels -* supported with a step of 8. Hence the supported priorities are -* 0, 8, 16, 32, 40 ..., 248. -* @param Trigger is the new trigger type for the IRQ source. -* Each bit pair describes the configuration for an INT_ID. -* SFI Read Only b10 always -* PPI Read Only depending on how the PPIs are configured. -* b01 Active HIGH level sensitive -* b11 Rising edge sensitive -* SPI LSB is read only. -* b01 Active HIGH level sensitive -* b11 Rising edge sensitive/ -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, - u8 Priority, u8 Trigger) -{ - u32 RegValue; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS); - Xil_AssertVoid(Trigger <= XSCUGIC_INT_CFG_MASK); - Xil_AssertVoid(Priority <= XSCUGIC_MAX_INTR_PRIO_VAL); - - /* - * Determine the register to write to using the Int_Id. - */ - RegValue = XScuGic_DistReadReg(InstancePtr, - XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id)); - - /* - * The priority bits are Bits 7 to 3 in GIC Priority Register. This - * means the number of priority levels supported are 32 and they are - * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc. - * The lower order 3 bits are masked before putting it in the register. - */ - Priority = Priority & XSCUGIC_INTR_PRIO_MASK; - /* - * Shift and Mask the correct bits for the priority and trigger in the - * register - */ - RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4)*8)); - RegValue |= Priority << ((Int_Id%4)*8); - - /* - * Write the value back to the register. - */ - XScuGic_DistWriteReg(InstancePtr, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id), - RegValue); - - /* - * Determine the register to write to using the Int_Id. - */ - RegValue = XScuGic_DistReadReg(InstancePtr, - XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id)); - - /* - * Shift and Mask the correct bits for the priority and trigger in the - * register - */ - RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16)*2)); - RegValue |= Trigger << ((Int_Id%16)*2); - - /* - * Write the value back to the register. - */ - XScuGic_DistWriteReg(InstancePtr, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id), - RegValue); - -} - -/****************************************************************************/ -/** -* Gets the interrupt priority and trigger type for the specificd IRQ source. -* -* @param InstancePtr is a pointer to the instance to be worked on. -* @param Int_Id is the IRQ source number to modify -* @param Priority is a pointer to the value of the priority of the IRQ -* source. This is a return value. -* @param Trigger is pointer to the value of the trigger of the IRQ -* source. This is a return value. -* -* @return None. -* -* @note None -* -*****************************************************************************/ -void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, - u8 *Priority, u8 *Trigger) -{ - u32 RegValue; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS); - Xil_AssertVoid(Priority != NULL); - Xil_AssertVoid(Trigger != NULL); - - /* - * Determine the register to read to using the Int_Id. - */ - RegValue = XScuGic_DistReadReg(InstancePtr, - XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id)); - - /* - * Shift and Mask the correct bits for the priority and trigger in the - * register - */ - RegValue = RegValue >> ((Int_Id%4)*8); - *Priority = RegValue & XSCUGIC_PRIORITY_MASK; - - /* - * Determine the register to read to using the Int_Id. - */ - RegValue = XScuGic_DistReadReg(InstancePtr, - XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id)); - - /* - * Shift and Mask the correct bits for the priority and trigger in the - * register - */ - RegValue = RegValue >> ((Int_Id%16)*2); - - *Trigger = RegValue & XSCUGIC_INT_CFG_MASK; -} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scugic_v1_05_a/src/xscugic.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scugic_v1_05_a/src/xscugic.h deleted file mode 100644 index d119872e93163065757770548eb75316b6674052..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scugic_v1_05_a/src/xscugic.h +++ /dev/null @@ -1,318 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xscugic.h -* -* The generic interrupt controller driver component. -* -* The interrupt controller driver uses the idea of priority for the various -* handlers. Priority is an integer within the range of 1 and 31 inclusive with -* default of 1 being the highest priority interrupt source. The priorities -* of the various sources can be dynamically altered as needed through -* hardware configuration. -* -* The generic interrupt controller supports the following -* features: -* -* - specific individual interrupt enabling/disabling -* - specific individual interrupt acknowledging -* - attaching specific callback function to handle interrupt source -* - assigning desired priority to interrupt source if default is not -* acceptable. -* -* Details about connecting the interrupt handler of the driver are contained -* in the source file specific to interrupt processing, xscugic_intr.c. -* -* This driver is intended to be RTOS and processor independent. It works with -* physical addresses only. Any needs for dynamic memory management, threads -* or thread mutual exclusion, virtual memory, or cache control must be -* satisfied by the layer above this driver. -* -* <b>Interrupt Vector Tables</b> -* -* The device ID of the interrupt controller device is used by the driver as a -* direct index into the configuration data table. The user should populate the -* vector table with handlers and callbacks at run-time using the -* XScuGic_Connect() and XScuGic_Disconnect() functions. -* -* Each vector table entry corresponds to a device that can generate an -* interrupt. Each entry contains an interrupt handler function and an -* argument to be passed to the handler when an interrupt occurs. The -* user must use XScuGic_Connect() when the interrupt handler takes an -* argument other than the base address. -* -* <b>Nested Interrupts Processing</b> -* -* Nested interrupts are not supported by this driver. -* -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- --------------------------------------------------------- -* 1.00a drg 01/19/00 First release -* 1.01a sdm 11/09/11 The XScuGic and XScuGic_Config structures have changed. -* The HandlerTable (of type XScuGic_VectorTableEntry) is -* moved to XScuGic_Config structure from XScuGic structure. -* -* The "Config" entry in XScuGic structure is made as -* pointer for better efficiency. -* -* A new file named as xscugic_hw.c is now added. It is -* to implement low level driver routines without using -* any xscugic instance pointer. They are useful when the -* user wants to use xscugic through device id or -* base address. The driver routines provided are explained -* below. -* XScuGic_DeviceInitialize that takes device id as -* argument and initializes the device (without calling -* XScuGic_CfgInitialize). -* XScuGic_DeviceInterruptHandler that takes device id -* as argument and calls appropriate handlers from the -* HandlerTable. -* XScuGic_RegisterHandler that registers a new handler -* by taking xscugic hardware base address as argument. -* LookupConfigByBaseAddress is used to return the -* corresponding config structure from XScuGic_ConfigTable -* based on the scugic base address passed. -* 1.02a sdm 12/20/11 Removed AckBeforeService from the XScuGic_Config -* structure. -* 1.03a srt 02/27/13 Moved Offset calculation macros from *.c and *_hw.c to -* *_hw.h -* Added APIs -* - XScuGic_SetPriTrigTypeByDistAddr() -* - XScuGic_GetPriTrigTypeByDistAddr() -* (CR 702687) -* Added support to direct interrupts to the appropriate CPU. Earlier -* interrupts were directed to CPU1 (hard coded). Now depending -* upon the CPU selected by the user (xparameters.h), interrupts -* will be directed to the relevant CPU. This fixes CR 699688. -* 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in -* XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings. -* Moved functions XScuGic_SetPriTrigTypeByDistAddr and -* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c. -* This is fix for CR#705621. -* 1.05a hk 06/26/13 Modified tcl to export external interrupts correctly to -* xparameters.h. Fix for CR's 690505, 708928 & 719359. -* -* </pre> -* -******************************************************************************/ - -#ifndef XSCUGIC_H /* prevent circular inclusions */ -#define XSCUGIC_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - - -/***************************** Include Files *********************************/ - -#include "xstatus.h" -#include "xil_io.h" -#include "xscugic_hw.h" -#include "xil_exception.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - -/* The following data type defines each entry in an interrupt vector table. - * The callback reference is the base address of the interrupting device - * for the low level driver and an instance pointer for the high level driver. - */ -typedef struct -{ - Xil_InterruptHandler Handler; - void *CallBackRef; -} XScuGic_VectorTableEntry; - -/** - * This typedef contains configuration information for the device. - */ -typedef struct -{ - u16 DeviceId; /**< Unique ID of device */ - u32 CpuBaseAddress; /**< CPU Interface Register base address */ - u32 DistBaseAddress; /**< Distributor Register base address */ - XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**< - Vector table of interrupt handlers */ -} XScuGic_Config; - -/** - * The XScuGic driver instance data. The user is required to allocate a - * variable of this type for every intc device in the system. A pointer - * to a variable of this type is then passed to the driver API functions. - */ -typedef struct -{ - XScuGic_Config *Config; /**< Configuration table entry */ - u32 IsReady; /**< Device is initialized and ready */ - u32 UnhandledInterrupts; /**< Intc Statistics */ -} XScuGic; - -/***************** Macros (Inline Functions) Definitions *********************/ - -/****************************************************************************/ -/** -* -* Write the given CPU Interface register -* -* @param InstancePtr is a pointer to the instance to be worked on. -* @param RegOffset is the register offset to be written -* @param Data is the 32-bit value to write to the register -* -* @return None. -* -* @note -* C-style signature: -* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) -* -*****************************************************************************/ -#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \ -(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \ - ((u32)Data))) - -/****************************************************************************/ -/** -* -* Read the given CPU Interface register -* -* @param InstancePtr is a pointer to the instance to be worked on. -* @param RegOffset is the register offset to be read -* -* @return The 32-bit value of the register -* -* @note -* C-style signature: -* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset) -* -*****************************************************************************/ -#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \ - (XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset))) - -/****************************************************************************/ -/** -* -* Write the given Distributor Interface register -* -* @param InstancePtr is a pointer to the instance to be worked on. -* @param RegOffset is the register offset to be written -* @param Data is the 32-bit value to write to the register -* -* @return None. -* -* @note -* C-style signature: -* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) -* -*****************************************************************************/ -#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \ -(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \ - ((u32)Data))) - -/****************************************************************************/ -/** -* -* Read the given Distributor Interface register -* -* @param InstancePtr is a pointer to the instance to be worked on. -* @param RegOffset is the register offset to be read -* -* @return The 32-bit value of the register -* -* @note -* C-style signature: -* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset) -* -*****************************************************************************/ -#define XScuGic_DistReadReg(InstancePtr, RegOffset) \ -(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset))) - -/************************** Function Prototypes ******************************/ - -/* - * Required functions in xscugic.c - */ - -int XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id, - Xil_InterruptHandler Handler, void *CallBackRef); -void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id); - -void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id); -void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id); - -int XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr, - u32 EffectiveAddr); - -int XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id); - -void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, - u8 *Priority, u8 *Trigger); -void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, - u8 Priority, u8 Trigger); - -/* - * Initialization functions in xscugic_sinit.c - */ -XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId); - -/* - * Interrupt functions in xscugic_intr.c - */ -void XScuGic_InterruptHandler(XScuGic *InstancePtr); - -/* - * Self-test functions in xscugic_selftest.c - */ -int XScuGic_SelfTest(XScuGic *InstancePtr); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scugic_v1_05_a/src/xscugic_g.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scugic_v1_05_a/src/xscugic_g.c deleted file mode 100644 index 60986e6b416ef849001b0684765a916844777408..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scugic_v1_05_a/src/xscugic_g.c +++ /dev/null @@ -1,31 +0,0 @@ - -/******************************************************************* -* -* CAUTION: This file is automatically generated by libgen. -* Version: Xilinx EDK 14.7 EDK_P.20131013 -* DO NOT EDIT. -* -* Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. - -* -* Description: Driver configuration -* -*******************************************************************/ - -#include "xparameters.h" -#include "xscugic.h" - -/* -* The configuration table for devices -*/ - -XScuGic_Config XScuGic_ConfigTable[] = -{ - { - XPAR_PS7_SCUGIC_0_DEVICE_ID, - XPAR_PS7_SCUGIC_0_BASEADDR, - XPAR_PS7_SCUGIC_0_DIST_BASEADDR - } -}; - - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scugic_v1_05_a/src/xscugic_hw.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scugic_v1_05_a/src/xscugic_hw.c deleted file mode 100644 index 488428ecf8c05be3fc6db579a6d26d9f15fb9d11..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scugic_v1_05_a/src/xscugic_hw.c +++ /dev/null @@ -1,567 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xscugic_hw.c -* -* This file contains low-level driver functions that can be used to access the -* device. The user should refer to the hardware device specification for more -* details of the device operation. -* These routines are used when the user does not want to create an instance of -* XScuGic structure but still wants to use the ScuGic device. Hence the -* routines provided here take device id or scugic base address as arguments. -* Separate static versions of DistInit and CPUInit are provided to implement -* the low level driver routines. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.01a sdm 07/18/11 First release -* 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR -* 702687). -* Added support to direct interrupts to the appropriate CPU. -* Earlier interrupts were directed to CPU1 (hard coded). Now -* depending upon the CPU selected by the user (xparameters.h), -* interrupts will be directed to the relevant CPU. -* This fixes CR 699688. -* 1.04a hk 05/04/13 Fix for CR#705621. Moved functions -* XScuGic_SetPriTrigTypeByDistAddr and -* XScuGic_GetPriTrigTypeByDistAddr here from xscugic.c -* -* </pre> -* -******************************************************************************/ - - -/***************************** Include Files *********************************/ - -#include "xparameters.h" -#include "xil_types.h" -#include "xil_assert.h" -#include "xscugic.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -static void DistInit(XScuGic_Config *Config, u32 CpuID); -static void CPUInit(XScuGic_Config *Config); -static XScuGic_Config *LookupConfigByBaseAddress(u32 BaseAddress); - -/************************** Variable Definitions *****************************/ - -extern XScuGic_Config XScuGic_ConfigTable[]; - -/*****************************************************************************/ -/** -* -* DistInit initializes the distributor of the GIC. The -* initialization entails: -* -* - Write the trigger mode, priority and target CPU -* - All interrupt sources are disabled -* - Enable the distributor -* -* @param InstancePtr is a pointer to the XScuGic instance. -* @param CpuID is the Cpu ID to be initialized. -* -* @return None -* -* @note None. -* -******************************************************************************/ -static void DistInit(XScuGic_Config *Config, u32 CpuID) -{ - u32 Int_Id; - -#if USE_AMP==1 - #warning "Building GIC for AMP" - - /* - * The distrubutor should not be initialized by FreeRTOS in the case of - * AMP -- it is assumed that Linux is the master of this device in that - * case. - */ - return; -#endif - - XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, 0UL); - - /* - * Set the security domains in the int_security registers for non-secure - * interrupts. All are secure, so leave at the default. Set to 1 for - * non-secure interrupts. - */ - - - /* - * For the Shared Peripheral Interrupts INT_ID[MAX..32], set: - */ - - /* - * 1. The trigger mode in the int_config register - * Only write to the SPI interrupts, so start at 32 - */ - for (Int_Id = 32; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id+=16) { - /* - * Each INT_ID uses two bits, or 16 INT_ID per register - * Set them all to be level sensitive, active HIGH. - */ - XScuGic_WriteReg(Config->DistBaseAddress, - XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id), 0UL); - } - - -#define DEFAULT_PRIORITY 0xa0a0a0a0UL - for (Int_Id = 0; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id+=4) { - /* - * 2. The priority using int the priority_level register - * The priority_level and spi_target registers use one byte per - * INT_ID. - * Write a default value that can be changed elsewhere. - */ - XScuGic_WriteReg(Config->DistBaseAddress, - XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id), - DEFAULT_PRIORITY); - } - - for (Int_Id = 32; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id+=4) { - /* - * 3. The CPU interface in the spi_target register - * Only write to the SPI interrupts, so start at 32 - */ - CpuID |= CpuID << 8; - CpuID |= CpuID << 16; - - XScuGic_WriteReg(Config->DistBaseAddress, - XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), CpuID); - } - - for (Int_Id = 0; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id+=32) { - /* - * 4. Enable the SPI using the enable_set register. Leave all disabled - * for now. - */ - XScuGic_WriteReg(Config->DistBaseAddress, - XSCUGIC_ENABLE_DISABLE_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET, - Int_Id), - 0xFFFFFFFFUL); - - } - - XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, - XSCUGIC_EN_INT_MASK); - -} - -/*****************************************************************************/ -/** -* -* CPUInit initializes the CPU Interface of the GIC. The initialization entails: -* -* - Set the priority of the CPU. -* - Enable the CPU interface -* -* @param ConfigPtr is a pointer to a config table for the particular -* device this driver is associated with. -* -* @return None -* -* @note None. -* -******************************************************************************/ -static void CPUInit(XScuGic_Config *Config) -{ - /* - * Program the priority mask of the CPU using the Priority mask - * register - */ - XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CPU_PRIOR_OFFSET, - 0xF0); - - /* - * If the CPU operates in both security domains, set parameters in the - * control_s register. - * 1. Set FIQen=1 to use FIQ for secure interrupts, - * 2. Program the AckCtl bit - * 3. Program the SBPR bit to select the binary pointer behavior - * 4. Set EnableS = 1 to enable secure interrupts - * 5. Set EnbleNS = 1 to enable non secure interrupts - */ - - /* - * If the CPU operates only in the secure domain, setup the - * control_s register. - * 1. Set FIQen=1, - * 2. Set EnableS=1, to enable the CPU interface to signal secure . - * interrupts Only enable the IRQ output unless secure interrupts - * are needed. - */ - XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CONTROL_OFFSET, 0x07); - -} - -/*****************************************************************************/ -/** -* -* CfgInitialize a specific interrupt controller instance/driver. The -* initialization entails: -* -* - Initialize fields of the XScuGic structure -* - Initial vector table with stub function calls -* - All interrupt sources are disabled -* -* @param InstancePtr is a pointer to the XScuGic instance to be worked on. -* @param ConfigPtr is a pointer to a config table for the particular device -* this driver is associated with. -* @param EffectiveAddr is the device base address in the virtual memory address -* space. The caller is responsible for keeping the address mapping -* from EffectiveAddr to the device physical base address unchanged -* once this function is invoked. Unexpected errors may occur if the -* address mapping changes after this function is called. If address -* translation is not used, use Config->BaseAddress for this parameters, -* passing the physical address instead. -* -* @return -* -* - XST_SUCCESS if initialization was successful -* -* @note -* -* None. -* -******************************************************************************/ -int XScuGic_DeviceInitialize(u32 DeviceId) -{ - XScuGic_Config *Config; - u8 Cpu_Id = XPAR_CPU_ID + 1; - - Config = &XScuGic_ConfigTable[(u32 )DeviceId]; - - DistInit(Config, Cpu_Id); - - CPUInit(Config); - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* This function is the primary interrupt handler for the driver. It must be -* connected to the interrupt source such that it is called when an interrupt of -* the interrupt controller is active. It will resolve which interrupts are -* active and enabled and call the appropriate interrupt handler. It uses -* the Interrupt Type information to determine when to acknowledge the -* interrupt.Highest priority interrupts are serviced first. -* -* This function assumes that an interrupt vector table has been previously -* initialized. It does not verify that entries in the table are valid before -* calling an interrupt handler. -* -* @param DeviceId is the unique identifier for the ScuGic device. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XScuGic_DeviceInterruptHandler(void *DeviceId) -{ - - u32 IntID; - XScuGic_VectorTableEntry *TablePtr; - XScuGic_Config *CfgPtr; - - CfgPtr = &XScuGic_ConfigTable[(u32 )DeviceId]; - - /* - * Read the int_ack register to identify the highest priority - * interrupt ID and make sure it is valid. Reading Int_Ack will - * clear the interrupt in the GIC. - */ - IntID = XScuGic_ReadReg(CfgPtr->CpuBaseAddress, XSCUGIC_INT_ACK_OFFSET) - & XSCUGIC_ACK_INTID_MASK; - if(XSCUGIC_MAX_NUM_INTR_INPUTS < IntID){ - goto IntrExit; - } - - /* - * If the interrupt is shared, do some locking here if there are - * multiple processors. - */ - /* - * If pre-eption is required: - * Re-enable pre-emption by setting the CPSR I bit for non-secure , - * interrupts or the F bit for secure interrupts - */ - - /* - * If we need to change security domains, issue a SMC instruction here. - */ - - /* - * Execute the ISR. Jump into the Interrupt service routine based on - * the IRQSource. A software trigger is cleared by the ACK. - */ - TablePtr = &(CfgPtr->HandlerTable[IntID]); - TablePtr->Handler(TablePtr->CallBackRef); - -IntrExit: - /* - * Write to the EOI register, we are all done here. - * Let this function return, the boot code will restore the stack. - */ - XScuGic_WriteReg(CfgPtr->CpuBaseAddress, XSCUGIC_EOI_OFFSET, IntID); - - /* - * Return from the interrupt. Change security domains could happen - * here. - */ -} - -/*****************************************************************************/ -/** -* -* Register a handler function for a specific interrupt ID. The vector table -* of the interrupt controller is updated, overwriting any previous handler. -* The handler function will be called when an interrupt occurs for the given -* interrupt ID. -* -* @param BaseAddress is the CPU Interface Register base address of the -* interrupt controller whose vector table will be modified. -* @param InterruptId is the interrupt ID to be associated with the input -* handler. -* @param Handler is the function pointer that will be added to -* the vector table for the given interrupt ID. -* @param CallBackRef is the argument that will be passed to the new -* handler function when it is called. This is user-specific. -* -* @return None. -* -* @note -* -* Note that this function has no effect if the input base address is invalid. -* -******************************************************************************/ -void XScuGic_RegisterHandler(u32 BaseAddress, int InterruptId, - Xil_InterruptHandler Handler, void *CallBackRef) -{ - XScuGic_Config *CfgPtr; - - CfgPtr = LookupConfigByBaseAddress(BaseAddress); - if (CfgPtr != NULL) { - CfgPtr->HandlerTable[InterruptId].Handler = Handler; - CfgPtr->HandlerTable[InterruptId].CallBackRef = CallBackRef; - } -} - -/*****************************************************************************/ -/** -* -* Looks up the device configuration based on the CPU interface base address of -* the device. A table contains the configuration info for each device in the -* system. -* -* @param CpuBaseAddress is the CPU Interface Register base address. -* -* @return A pointer to the configuration structure for the specified -* device, or NULL if the device was not found. -* -* @note None. -* -******************************************************************************/ -static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress) -{ - XScuGic_Config *CfgPtr = NULL; - int Index; - - for (Index = 0; Index < XPAR_SCUGIC_NUM_INSTANCES; Index++) { - if (XScuGic_ConfigTable[Index].CpuBaseAddress == - CpuBaseAddress) { - CfgPtr = &XScuGic_ConfigTable[Index]; - break; - } - } - - return CfgPtr; -} - -/****************************************************************************/ -/** -* Sets the interrupt priority and trigger type for the specificd IRQ source. -* -* @param BaseAddr is the device base address -* @param Int_Id is the IRQ source number to modify -* @param Priority is the new priority for the IRQ source. 0 is highest -* priority, 0xF8 (248) is lowest. There are 32 priority levels -* supported with a step of 8. Hence the supported priorities are -* 0, 8, 16, 32, 40 ..., 248. -* @param Trigger is the new trigger type for the IRQ source. -* Each bit pair describes the configuration for an INT_ID. -* SFI Read Only b10 always -* PPI Read Only depending on how the PPIs are configured. -* b01 Active HIGH level sensitive -* b11 Rising edge sensitive -* SPI LSB is read only. -* b01 Active HIGH level sensitive -* b11 Rising edge sensitive/ -* -* @return None. -* -* @note This API has the similar functionality of XScuGic_SetPriority -* TriggerType() and should be used when there is no InstancePtr. -* -*****************************************************************************/ -void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, - u8 Priority, u8 Trigger) -{ - u32 RegValue; - - Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS); - Xil_AssertVoid(Trigger <= XSCUGIC_INT_CFG_MASK); - Xil_AssertVoid(Priority <= XSCUGIC_MAX_INTR_PRIO_VAL); - - /* - * Determine the register to write to using the Int_Id. - */ - RegValue = XScuGic_ReadReg(DistBaseAddress, - XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id)); - - /* - * The priority bits are Bits 7 to 3 in GIC Priority Register. This - * means the number of priority levels supported are 32 and they are - * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc. - * The lower order 3 bits are masked before putting it in the register. - */ - Priority = Priority & XSCUGIC_INTR_PRIO_MASK; - /* - * Shift and Mask the correct bits for the priority and trigger in the - * register - */ - RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4)*8)); - RegValue |= Priority << ((Int_Id%4)*8); - - /* - * Write the value back to the register. - */ - XScuGic_WriteReg(DistBaseAddress, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id), - RegValue); - /* - * Determine the register to write to using the Int_Id. - */ - RegValue = XScuGic_ReadReg(DistBaseAddress, - XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id)); - - /* - * Shift and Mask the correct bits for the priority and trigger in the - * register - */ - RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16)*2)); - RegValue |= Trigger << ((Int_Id%16)*2); - - /* - * Write the value back to the register. - */ - XScuGic_WriteReg(DistBaseAddress, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id), - RegValue); -} - -/****************************************************************************/ -/** -* Gets the interrupt priority and trigger type for the specificd IRQ source. -* -* @param BaseAddr is the device base address -* @param Int_Id is the IRQ source number to modify -* @param Priority is a pointer to the value of the priority of the IRQ -* source. This is a return value. -* @param Trigger is pointer to the value of the trigger of the IRQ -* source. This is a return value. -* -* @return None. -* -* @note This API has the similar functionality of XScuGic_GetPriority -* TriggerType() and should be used when there is no InstancePtr. -* -*****************************************************************************/ -void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, - u8 *Priority, u8 *Trigger) -{ - u32 RegValue; - - Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS); - Xil_AssertVoid(Priority != NULL); - Xil_AssertVoid(Trigger != NULL); - - /* - * Determine the register to read to using the Int_Id. - */ - RegValue = XScuGic_ReadReg(DistBaseAddress, - XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id)); - - /* - * Shift and Mask the correct bits for the priority and trigger in the - * register - */ - RegValue = RegValue >> ((Int_Id%4)*8); - *Priority = RegValue & XSCUGIC_PRIORITY_MASK; - - /* - * Determine the register to read to using the Int_Id. - */ - RegValue = XScuGic_ReadReg(DistBaseAddress, - XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id)); - - /* - * Shift and Mask the correct bits for the priority and trigger in the - * register - */ - RegValue = RegValue >> ((Int_Id%16)*2); - - *Trigger = RegValue & XSCUGIC_INT_CFG_MASK; -} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scugic_v1_05_a/src/xscugic_hw.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scugic_v1_05_a/src/xscugic_hw.h deleted file mode 100644 index 4f8354fe9afcb6aa32092c31a57c4c65d8aee2ce..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scugic_v1_05_a/src/xscugic_hw.h +++ /dev/null @@ -1,641 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xscugic_hw.h -* -* This header file contains identifiers and HW access functions (or -* macros) that can be used to access the device. The user should refer to the -* hardware device specification for more details of the device operation. -* The driver functions/APIs are defined in xscugic.h. -* -* This GIC device has two parts, a distributor and CPU interface(s). Each part -* has separate register definition sections. -* -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------------- -* 1.00a drg 01/19/10 First release -* 1.01a sdm 11/09/11 "xil_exception.h" added as include. -* Macros XScuGic_EnableIntr and XScuGic_DisableIntr are -* added to enable or disable interrupts based on -* Distributor Register base address. Normally users use -* XScuGic instance and call XScuGic_Enable or -* XScuGic_Disable to enable/disable interrupts. These -* new macros are provided when user does not want to -* use an instance pointer but still wants to enable or -* disable interrupts. -* Function prototypes for functions (present in newly -* added file xscugic_hw.c) are added. -* 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR -* 702687). -* 1.04a hk 05/04/13 Fix for CR#705621. Moved function prototypes -* XScuGic_SetPriTrigTypeByDistAddr and -* XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h -* -* </pre> -* -******************************************************************************/ - -#ifndef XSCUGIC_HW_H /* prevent circular inclusions */ -#define XSCUGIC_HW_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xil_io.h" -#include "xil_exception.h" - -/************************** Constant Definitions *****************************/ - -/* - * The maximum number of interrupts supported by the hardware. - */ -#define XSCUGIC_MAX_NUM_INTR_INPUTS 95 - -/* - * The maximum priority value that can be used in the GIC. - */ -#define XSCUGIC_MAX_INTR_PRIO_VAL 248 -#define XSCUGIC_INTR_PRIO_MASK 0xF8 - -/** @name Distributor Interface Register Map - * - * Define the offsets from the base address for all Distributor registers of - * the interrupt controller, some registers may be reserved in the hardware - * device. - * @{ - */ -#define XSCUGIC_DIST_EN_OFFSET 0x00000000 /**< Distributor Enable - Register */ -#define XSCUGIC_IC_TYPE_OFFSET 0x00000004 /**< Interrupt Controller - Type Register */ -#define XSCUGIC_DIST_IDENT_OFFSET 0x00000008 /**< Implementor ID - Register */ -#define XSCUGIC_SECURITY_OFFSET 0x00000080 /**< Interrupt Security - Register */ -#define XSCUGIC_ENABLE_SET_OFFSET 0x00000100 /**< Enable Set - Register */ -#define XSCUGIC_DISABLE_OFFSET 0x00000180 /**< Enable Clear Register */ -#define XSCUGIC_PENDING_SET_OFFSET 0x00000200 /**< Pending Set - Register */ -#define XSCUGIC_PENDING_CLR_OFFSET 0x00000280 /**< Pending Clear - Register */ -#define XSCUGIC_ACTIVE_OFFSET 0x00000300 /**< Active Status Register */ -#define XSCUGIC_PRIORITY_OFFSET 0x00000400 /**< Priority Level Register */ -#define XSCUGIC_SPI_TARGET_OFFSET 0x00000800 /**< SPI Target - Register 0x800-0x8FB */ -#define XSCUGIC_INT_CFG_OFFSET 0x00000C00 /**< Interrupt Configuration - Register 0xC00-0xCFC */ -#define XSCUGIC_PPI_STAT_OFFSET 0x00000D00 /**< PPI Status Register */ -#define XSCUGIC_SPI_STAT_OFFSET 0x00000D04 /**< SPI Status Register - 0xd04-0xd7C */ -#define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80 /**< AHB Configuration - Register */ -#define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00 /**< Software Triggered - Interrupt Register */ -#define XSCUGIC_PERPHID_OFFSET 0x00000FD0 /**< Peripheral ID Reg */ -#define XSCUGIC_PCELLID_OFFSET 0x00000FF0 /**< Pcell ID Register */ -/* @} */ - -/** @name Distributor Enable Register - * Controls if the distributor response to external interrupt inputs. - * @{ - */ -#define XSCUGIC_EN_INT_MASK 0x00000001 /**< Interrupt In Enable */ -/* @} */ - -/** @name Interrupt Controller Type Register - * @{ - */ -#define XSCUGIC_LSPI_MASK 0x0000F800 /**< Number of Lockable - Shared Peripheral - Interrupts*/ -#define XSCUGIC_DOMAIN_MASK 0x00000400 /**< Number os Security domains*/ -#define XSCUGIC_CPU_NUM_MASK 0x000000E0 /**< Number of CPU Interfaces */ -#define XSCUGIC_NUM_INT_MASK 0x0000001F /**< Number of Interrupt IDs */ -/* @} */ - -/** @name Implementor ID Register - * Implementor and revision information. - * @{ - */ -#define XSCUGIC_REV_MASK 0x00FFF000 /**< Revision Number */ -#define XSCUGIC_IMPL_MASK 0x00000FFF /**< Implementor */ -/* @} */ - -/** @name Interrupt Security Registers - * Each bit controls the security level of an interrupt, either secure or non - * secure. These registers can only be accessed using secure read and write. - * There are registers for each of the CPU interfaces at offset 0x080. A - * register set for the SPI interrupts is available to all CPU interfaces. - * There are up to 32 of these registers staring at location 0x084. - * @{ - */ -#define XSCUGIC_INT_NS_MASK 0x00000001 /**< Each bit corresponds to an - INT_ID */ -/* @} */ - -/** @name Enable Set Register - * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is - * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a - * bit to 0. - * There are registers for each of the CPU interfaces at offset 0x100. With up - * to 8 registers aliased to the same address. A register set for the SPI - * interrupts is available to all CPU interfaces. - * There are up to 32 of these registers staring at location 0x104. - * @{ - */ -#define XSCUGIC_INT_EN_MASK 0x00000001 /**< Each bit corresponds to an - INT_ID */ -/* @} */ - -/** @name Enable Clear Register - * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is - * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and - * sets the corresponding bit to 0. - * There are registers for each of the CPU interfaces at offset 0x180. With up - * to 8 registers aliased to the same address. - * A register set for the SPI interrupts is available to all CPU interfaces. - * There are up to 32 of these registers staring at location 0x184. - * @{ - */ -#define XSCUGIC_INT_CLR_MASK 0x00000001 /**< Each bit corresponds to an - INT_ID */ -/* @} */ - -/** @name Pending Set Register - * Each bit controls the Pending or Active and Pending state of an interrupt, a - * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets - * an interrupt to the pending state. - * There are registers for each of the CPU interfaces at offset 0x200. With up - * to 8 registers aliased to the same address. - * A register set for the SPI interrupts is available to all CPU interfaces. - * There are up to 32 of these registers staring at location 0x204. - * @{ - */ -#define XSCUGIC_PEND_SET_MASK 0x00000001 /**< Each bit corresponds to an - INT_ID */ -/* @} */ - -/** @name Pending Clear Register - * Each bit can clear the Pending or Active and Pending state of an interrupt, a - * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 - * clears the pending state of an interrupt. - * There are registers for each of the CPU interfaces at offset 0x280. With up - * to 8 registers aliased to the same address. - * A register set for the SPI interrupts is available to all CPU interfaces. - * There are up to 32 of these registers staring at location 0x284. - * @{ - */ -#define XSCUGIC_PEND_CLR_MASK 0x00000001 /**< Each bit corresponds to an - INT_ID */ -/* @} */ - -/** @name Active Status Register - * Each bit provides the Active status of an interrupt, a - * 0 is not Active, a 1 is Active. This is a read only register. - * There are registers for each of the CPU interfaces at offset 0x300. With up - * to 8 registers aliased to each address. - * A register set for the SPI interrupts is available to all CPU interfaces. - * There are up to 32 of these registers staring at location 0x380. - * @{ - */ -#define XSCUGIC_ACTIVE_MASK 0x00000001 /**< Each bit corresponds to an - INT_ID */ -/* @} */ - -/** @name Priority Level Register - * Each byte in a Priority Level Register sets the priority level of an - * interrupt. Reading the register provides the priority level of an interrupt. - * There are registers for each of the CPU interfaces at offset 0x400 through - * 0x41C. With up to 8 registers aliased to each address. - * 0 is highest priority, 0xFF is lowest. - * A register set for the SPI interrupts is available to all CPU interfaces. - * There are up to 255 of these registers staring at location 0x420. - * @{ - */ -#define XSCUGIC_PRIORITY_MASK 0x000000FF /**< Each Byte corresponds to an - INT_ID */ -#define XSCUGIC_PRIORITY_MAX 0x000000FF /**< Highest value of a priority - actually the lowest priority*/ -/* @} */ - -/** @name SPI Target Register 0x800-0x8FB - * Each byte references a separate SPI and programs which of the up to 8 CPU - * interfaces are sent a Pending interrupt. - * There are registers for each of the CPU interfaces at offset 0x800 through - * 0x81C. With up to 8 registers aliased to each address. - * A register set for the SPI interrupts is available to all CPU interfaces. - * There are up to 255 of these registers staring at location 0x820. - * - * This driver does not support multiple CPU interfaces. These are included - * for complete documentation. - * @{ - */ -#define XSCUGIC_SPI_CPU7_MASK 0x00000080 /**< CPU 7 Mask*/ -#define XSCUGIC_SPI_CPU6_MASK 0x00000040 /**< CPU 6 Mask*/ -#define XSCUGIC_SPI_CPU5_MASK 0x00000020 /**< CPU 5 Mask*/ -#define XSCUGIC_SPI_CPU4_MASK 0x00000010 /**< CPU 4 Mask*/ -#define XSCUGIC_SPI_CPU3_MASK 0x00000008 /**< CPU 3 Mask*/ -#define XSCUGIC_SPI_CPU2_MASK 0x00000003 /**< CPU 2 Mask*/ -#define XSCUGIC_SPI_CPU1_MASK 0x00000002 /**< CPU 1 Mask*/ -#define XSCUGIC_SPI_CPU0_MASK 0x00000001 /**< CPU 0 Mask*/ -/* @} */ - -/** @name Interrupt Configuration Register 0xC00-0xCFC - * The interrupt configuration registers program an SFI to be active HIGH level - * sensitive or rising edge sensitive. - * Each bit pair describes the configuration for an INT_ID. - * SFI Read Only b10 always - * PPI Read Only depending on how the PPIs are configured. - * b01 Active HIGH level sensitive - * b11 Rising edge sensitive - * SPI LSB is read only. - * b01 Active HIGH level sensitive - * b11 Rising edge sensitive/ - * There are registers for each of the CPU interfaces at offset 0xC00 through - * 0xC04. With up to 8 registers aliased to each address. - * A register set for the SPI interrupts is available to all CPU interfaces. - * There are up to 255 of these registers staring at location 0xC08. - * @{ - */ -#define XSCUGIC_INT_CFG_MASK 0x00000003 /**< */ -/* @} */ - -/** @name PPI Status Register - * Enables an external AMBA master to access the status of the PPI inputs. - * A CPU can only read the status of its local PPI signals and cannot read the - * status for other CPUs. - * This register is aliased for each CPU interface. - * @{ - */ -#define XSCUGIC_PPI_C15_MASK 0x00008000 /**< PPI Status */ -#define XSCUGIC_PPI_C14_MASK 0x00004000 /**< PPI Status */ -#define XSCUGIC_PPI_C13_MASK 0x00002000 /**< PPI Status */ -#define XSCUGIC_PPI_C12_MASK 0x00001000 /**< PPI Status */ -#define XSCUGIC_PPI_C11_MASK 0x00000800 /**< PPI Status */ -#define XSCUGIC_PPI_C10_MASK 0x00000400 /**< PPI Status */ -#define XSCUGIC_PPI_C09_MASK 0x00000200 /**< PPI Status */ -#define XSCUGIC_PPI_C08_MASK 0x00000100 /**< PPI Status */ -#define XSCUGIC_PPI_C07_MASK 0x00000080 /**< PPI Status */ -#define XSCUGIC_PPI_C06_MASK 0x00000040 /**< PPI Status */ -#define XSCUGIC_PPI_C05_MASK 0x00000020 /**< PPI Status */ -#define XSCUGIC_PPI_C04_MASK 0x00000010 /**< PPI Status */ -#define XSCUGIC_PPI_C03_MASK 0x00000008 /**< PPI Status */ -#define XSCUGIC_PPI_C02_MASK 0x00000004 /**< PPI Status */ -#define XSCUGIC_PPI_C01_MASK 0x00000002 /**< PPI Status */ -#define XSCUGIC_PPI_C00_MASK 0x00000001 /**< PPI Status */ -/* @} */ - -/** @name SPI Status Register 0xd04-0xd7C - * Enables an external AMBA master to access the status of the SPI inputs. - * There are up to 63 registers if the maximum number of SPI inputs are - * configured. - * @{ - */ -#define XSCUGIC_SPI_N_MASK 0x00000001 /**< Each bit corresponds to an SPI - input */ -/* @} */ - -/** @name AHB Configuration Register - * Provides the status of the CFGBIGEND input signal and allows the endianess - * of the GIC to be set. - * @{ - */ -#define XSCUGIC_AHB_END_MASK 0x00000004 /**< 0-GIC uses little Endian, - 1-GIC uses Big Endian */ -#define XSCUGIC_AHB_ENDOVR_MASK 0x00000002 /**< 0-Uses CFGBIGEND control, - 1-use the AHB_END bit */ -#define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001 /**< State of CFGBIGEND */ - -/* @} */ - -/** @name Software Triggered Interrupt Register - * Controls issueing of software interrupts. - * @{ - */ -#define XSCUGIC_SFI_SELFTRIG_MASK 0x02010000 -#define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000 /**< Target List filter - b00-Use the target List - b01-All CPUs except requester - b10-To Requester - b11-reserved */ -#define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000 /**< CPU Target list */ -#define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000 /**< 0= Use a secure interrupt */ -#define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000F /**< Set to the INTID - signaled to the CPU*/ -/* @} */ - -/** @name CPU Interface Register Map - * - * Define the offsets from the base address for all CPU registers of the - * interrupt controller, some registers may be reserved in the hardware device. - * @{ - */ -#define XSCUGIC_CONTROL_OFFSET 0x00000000 /**< CPU Interface Control - Register */ -#define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004 /**< Priority Mask Reg */ -#define XSCUGIC_BIN_PT_OFFSET 0x00000008 /**< Binary Point Register */ -#define XSCUGIC_INT_ACK_OFFSET 0x0000000C /**< Interrupt ACK Reg */ -#define XSCUGIC_EOI_OFFSET 0x00000010 /**< End of Interrupt Reg */ -#define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014 /**< Running Priority Reg */ -#define XSCUGIC_HI_PEND_OFFSET 0x00000018 /**< Highest Pending Interrupt - Register */ -#define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001C /**< Aliased non-Secure - Binary Point Register */ - -/**< 0x00000020 to 0x00000FBC are reserved and should not be read or written - * to. */ -/* @} */ - - -/** @name Control Register - * CPU Interface Control register definitions - * All bits are defined here although some are not available in the non-secure - * mode. - * @{ - */ -#define XSCUGIC_CNTR_SBPR_MASK 0x00000010 /**< Secure Binary Pointer, - 0=separate registers, - 1=both use bin_pt_s */ -#define XSCUGIC_CNTR_FIQEN_MASK 0x00000008 /**< Use nFIQ_C for secure - interrupts, - 0= use IRQ for both, - 1=Use FIQ for secure, IRQ for non*/ -#define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004 /**< Ack control for secure or non secure */ -#define XSCUGIC_CNTR_EN_NS_MASK 0x00000002 /**< Non Secure enable */ -#define XSCUGIC_CNTR_EN_S_MASK 0x00000001 /**< Secure enable, 0=Disabled, 1=Enabled */ -/* @} */ - -/** @name Priority Mask Register - * Priority Mask register definitions - * The CPU interface does not send interrupt if the level of the interrupt is - * lower than the level of the register. - * @{ - */ -#define XSCUGIC_PRIORITY_MASK 0x000000FF /**< All interrupts */ -/* @} */ - -/** @name Binary Point Register - * Binary Point register definitions - * @{ - */ - -#define XSCUGIC_BIN_PT_MASK 0x00000007 /**< Binary point mask value - Value Secure Non-secure - b000 0xFE 0xFF - b001 0xFC 0xFE - b010 0xF8 0xFC - b011 0xF0 0xF8 - b100 0xE0 0xF0 - b101 0xC0 0xE0 - b110 0x80 0xC0 - b111 0x00 0x80 - */ -/*@}*/ - -/** @name Interrupt Acknowledge Register - * Interrupt Acknowledge register definitions - * Identifies the current Pending interrupt, and the CPU ID for software - * interrupts. - */ -#define XSCUGIC_ACK_INTID_MASK 0x000003FF /**< Interrupt ID */ -#define XSCUGIC_CPUID_MASK 0x00000C00 /**< CPU ID */ -/* @} */ - -/** @name End of Interrupt Register - * End of Interrupt register definitions - * Allows the CPU to signal the GIC when it completes an interrupt service - * routine. - */ -#define XSCUGIC_EOI_INTID_MASK 0x000003FF /**< Interrupt ID */ - -/* @} */ - -/** @name Running Priority Register - * Running Priority register definitions - * Identifies the interrupt priority level of the highest priority active - * interrupt. - */ -#define XSCUGIC_RUN_PRIORITY_MASK 0x00000FF /**< Interrupt Priority */ -/* @} */ - -/* - * Highest Pending Interrupt register definitions - * Identifies the interrupt priority of the highest priority pending interupt - */ -#define XSCUGIC_PEND_INTID_MASK 0x000003FF /**< Pending Interrupt ID */ -#define XSCUGIC_CPUID_MASK 0x00000C00 /**< CPU ID */ -/* @} */ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/****************************************************************************/ -/** -* -* Read the Interrupt Configuration Register offset for an interrupt id. -* -* @param InterruptID is the interrupt number. -* -* @return The 32-bit value of the offset -* -* @note -* -*****************************************************************************/ -#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \ - (XSCUGIC_INT_CFG_OFFSET + ((InterruptID/16) * 4)) - -/****************************************************************************/ -/** -* -* Read the Interrupt Priority Register offset for an interrupt id. -* -* @param InterruptID is the interrupt number. -* -* @return The 32-bit value of the offset -* -* @note -* -*****************************************************************************/ -#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \ - (XSCUGIC_PRIORITY_OFFSET + ((InterruptID/4) * 4)) - -/****************************************************************************/ -/** -* -* Read the SPI Target Register offset for an interrupt id. -* -* @param InterruptID is the interrupt number. -* -* @return The 32-bit value of the offset -* -* @note -* -*****************************************************************************/ -#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \ - (XSCUGIC_SPI_TARGET_OFFSET + ((InterruptID/4) * 4)) - -/****************************************************************************/ -/** -* -* Read the Interrupt Clear-Enable Register offset for an interrupt ID -* -* @param Register is the register offset for the clear/enable bank. -* @param InterruptID is the interrupt number. -* -* @return The 32-bit value of the offset -* -* @note -* -*****************************************************************************/ -#define XSCUGIC_ENABLE_DISABLE_OFFSET_CALC(Register, InterruptID) \ - (Register + ((InterruptID/32) * 4)) - -/****************************************************************************/ -/** -* -* Read the given Intc register. -* -* @param BaseAddress is the base address of the device. -* @param RegOffset is the register offset to be read -* -* @return The 32-bit value of the register -* -* @note -* C-style signature: -* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset) -* -*****************************************************************************/ -#define XScuGic_ReadReg(BaseAddress, RegOffset) \ - (Xil_In32((BaseAddress) + (RegOffset))) - - -/****************************************************************************/ -/** -* -* Write the given Intc register. -* -* @param BaseAddress is the base address of the device. -* @param RegOffset is the register offset to be written -* @param Data is the 32-bit value to write to the register -* -* @return None. -* -* @note -* C-style signature: -* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) -* -*****************************************************************************/ -#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \ - (Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)Data))) - - -/****************************************************************************/ -/** -* -* Enable specific interrupt(s) in the interrupt controller. -* -* @param DistBaseAddress is the Distributor Register base address of the -* device -* @param Int_Id is the ID of the interrupt source and should be in the -* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1 -* -* @return None. -* -* @note C-style signature: -* void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id); -* -*****************************************************************************/ -#define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \ - XScuGic_WriteReg((DistBaseAddress), \ - XSCUGIC_ENABLE_SET_OFFSET + ((Int_Id / 32) * 4), \ - (1 << (Int_Id % 32))) - -/****************************************************************************/ -/** -* -* Disable specific interrupt(s) in the interrupt controller. -* -* @param DistBaseAddress is the Distributor Register base address of the -* device -* @param Int_Id is the ID of the interrupt source and should be in the -* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1 -* -* -* @return None. -* -* @note C-style signature: -* void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id); -* -*****************************************************************************/ -#define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \ - XScuGic_WriteReg((DistBaseAddress), \ - XSCUGIC_DISABLE_OFFSET + ((Int_Id / 32) * 4), \ - (1 << (Int_Id % 32))) - - -/************************** Function Prototypes ******************************/ - -void XScuGic_DeviceInterruptHandler(void *DeviceId); -int XScuGic_DeviceInitialize(u32 DeviceId); -void XScuGic_RegisterHandler(u32 BaseAddress, int InterruptId, - Xil_InterruptHandler Handler, void *CallBackRef); -void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, - u8 Priority, u8 Trigger); -void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, - u8 *Priority, u8 *Trigger); -/************************** Variable Definitions *****************************/ -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scugic_v1_05_a/src/xscugic_intr.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scugic_v1_05_a/src/xscugic_intr.c deleted file mode 100644 index 05415c086e46bdd62f9d5dc50977c69a54785d0a..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scugic_v1_05_a/src/xscugic_intr.c +++ /dev/null @@ -1,174 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xscugic_intr.c -* -* This file contains the interrupt processing for the driver for the Xilinx -* Interrupt Controller. The interrupt processing is partitioned separately such -* that users are not required to use the provided interrupt processing. This -* file requires other files of the driver to be linked in also. -* -* The interrupt handler, XScuGic_InterruptHandler, uses an input argument which -* is an instance pointer to an interrupt controller driver such that multiple -* interrupt controllers can be supported. This handler requires the calling -* function to pass it the appropriate argument, so another level of indirection -* may be required. -* -* The interrupt processing may be used by connecting the interrupt handler to -* the interrupt system. The handler does not save and restore the processor -* context but only handles the processing of the Interrupt Controller. The user -* is encouraged to supply their own interrupt handler when performance tuning is -* deemed necessary. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- --------------------------------------------------------- -* 1.00a drg 01/19/10 First release -* 1.01a sdm 11/09/11 XScuGic_InterruptHandler has changed correspondingly -* since the HandlerTable has now moved to XScuGic_Config. -* -* </pre> -* -* @internal -* -* This driver assumes that the context of the processor has been saved prior to -* the calling of the Interrupt Controller interrupt handler and then restored -* after the handler returns. This requires either the running RTOS to save the -* state of the machine or that a wrapper be used as the destination of the -* interrupt vector to save the state of the processor and restore the state -* after the interrupt handler returns. -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xscugic.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/************************** Variable Definitions *****************************/ - -/*****************************************************************************/ -/** -* This function is the primary interrupt handler for the driver. It must be -* connected to the interrupt source such that it is called when an interrupt of -* the interrupt controller is active. It will resolve which interrupts are -* active and enabled and call the appropriate interrupt handler. It uses -* the Interrupt Type information to determine when to acknowledge the interrupt. -* Highest priority interrupts are serviced first. -* -* This function assumes that an interrupt vector table has been previously -* initialized. It does not verify that entries in the table are valid before -* calling an interrupt handler. -* -* -* @param InstancePtr is a pointer to the XScuGic instance. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XScuGic_InterruptHandler(XScuGic *InstancePtr) -{ - - u32 IntID; - XScuGic_VectorTableEntry *TablePtr; - - /* Assert that the pointer to the instance is valid - */ - Xil_AssertVoid(InstancePtr != NULL); - - /* - * Read the int_ack register to identify the highest priority interrupt ID - * and make sure it is valid. Reading Int_Ack will clear the interrupt - * in the GIC. - */ - IntID = XScuGic_CPUReadReg(InstancePtr, XSCUGIC_INT_ACK_OFFSET) & - XSCUGIC_ACK_INTID_MASK; - if(XSCUGIC_MAX_NUM_INTR_INPUTS < IntID){ - goto IntrExit; - } - - /* - * If the interrupt is shared, do some locking here if there are multiple - * processors. - */ - /* - * If pre-eption is required: - * Re-enable pre-emption by setting the CPSR I bit for non-secure , - * interrupts or the F bit for secure interrupts - */ - - /* - * If we need to change security domains, issue a SMC instruction here. - */ - - /* - * Execute the ISR. Jump into the Interrupt service routine based on the - * IRQSource. A software trigger is cleared by the ACK. - */ - TablePtr = &(InstancePtr->Config->HandlerTable[IntID]); - TablePtr->Handler(TablePtr->CallBackRef); - -IntrExit: - /* - * Write to the EOI register, we are all done here. - * Let this function return, the boot code will restore the stack. - */ - XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_EOI_OFFSET, IntID); - - /* - * Return from the interrupt. Change security domains could happen here. - */ -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scugic_v1_05_a/src/xscugic_selftest.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scugic_v1_05_a/src/xscugic_selftest.c deleted file mode 100644 index 3c0d42a5b0e360dea58d142ae8a945923010c279..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scugic_v1_05_a/src/xscugic_selftest.c +++ /dev/null @@ -1,119 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xscugic_selftest.c -* -* Contains diagnostic self-test functions for the XScuGic driver. -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a drg 01/19/10 First release -* -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xscugic.h" - -/************************** Constant Definitions *****************************/ - -#define XSCUGIC_PCELL_ID 0xB105F00D - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - -/************************** Variable Definitions *****************************/ - -/*****************************************************************************/ -/** -* -* Run a self-test on the driver/device. This test reads the ID registers and -* compares them. -* -* @param InstancePtr is a pointer to the XScuGic instance. -* -* @return -* -* - XST_SUCCESS if self-test is successful. -* - XST_FAILURE if the self-test is not successful. -* -* @note None. -* -******************************************************************************/ -int XScuGic_SelfTest(XScuGic *InstancePtr) -{ - u32 RegValue1 =0; - int Index; - - /* - * Assert the arguments - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the ID registers. - */ - for(Index=0; Index<=3; Index++) { - RegValue1 |= XScuGic_DistReadReg(InstancePtr, - (XSCUGIC_PCELLID_OFFSET + (Index * 4))) << (Index * 8); - } - - if(XSCUGIC_PCELL_ID != RegValue1){ - return XST_FAILURE; - } - - return XST_SUCCESS; -} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scugic_v1_05_a/src/xscugic_sinit.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scugic_v1_05_a/src/xscugic_sinit.c deleted file mode 100644 index c1e635adbdedfcd76e1cfda9cb081b7b65049300..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scugic_v1_05_a/src/xscugic_sinit.c +++ /dev/null @@ -1,109 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xscugic_sinit.c -* -* Contains static init functions for the XScuGic driver for the Interrupt -* Controller. See xscugic.h for a detailed description of the driver. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- -------------------------------------------------------- -* 1.00a drg 01/19/10 First release -* -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xparameters.h" -#include "xscugic.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Variable Definitions *****************************/ - -extern XScuGic_Config XScuGic_ConfigTable[]; - -/************************** Function Prototypes ******************************/ - -/*****************************************************************************/ -/** -* -* Looks up the device configuration based on the unique device ID. A table -* contains the configuration info for each device in the system. -* -* @param DeviceId is the unique identifier for a device. -* -* @return A pointer to the XScuGic configuration structure for the -* specified device, or NULL if the device was not found. -* -* @note None. -* -******************************************************************************/ -XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId) -{ - XScuGic_Config *CfgPtr = NULL; - int Index; - - for (Index=0; Index < XPAR_SCUGIC_NUM_INSTANCES; Index++) { - if (XScuGic_ConfigTable[Index].DeviceId == DeviceId) { - CfgPtr = &XScuGic_ConfigTable[Index]; - break; - } - } - - return CfgPtr; -} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v1_02_a/src/Makefile b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v1_02_a/src/Makefile deleted file mode 100644 index f50acb48de89400a2b0b6c4d0baf093d078e8bad..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v1_02_a/src/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -COMPILER= -ARCHIVER= -CP=cp -COMPILER_FLAGS= -EXTRA_COMPILER_FLAGS= -LIB=libxil.a - -CC_FLAGS = $(COMPILER_FLAGS) -ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) - -RELEASEDIR=../../../lib -INCLUDEDIR=../../../include -INCLUDES=-I./. -I${INCLUDEDIR} - -OUTS = *.o - -LIBSOURCES:=*.c -INCLUDEFILES:=*.h - -OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) - -libs: banner scutimer_libs clean - -%.o: %.c - ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< - -banner: - echo "Compiling scutimer" - -scutimer_libs: ${OBJECTS} - $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} - -.PHONY: include -include: scutimer_includes - -scutimer_includes: - ${CP} ${INCLUDEFILES} ${INCLUDEDIR} - -clean: - rm -rf ${OBJECTS} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v1_02_a/src/xscutimer.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v1_02_a/src/xscutimer.c deleted file mode 100644 index c3b4b72eb0df1fbd55020bfe5fb83f2bba1282e0..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v1_02_a/src/xscutimer.c +++ /dev/null @@ -1,289 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ - -/****************************************************************************/ -/** -* -* @file xscutimer.c -* -* Contains the implementation of interface functions of the SCU Timer driver. -* See xscutimer.h for a description of the driver. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- --------------------------------------------- -* 1.00a nm 03/10/10 First release -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xscutimer.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/************************** Variable Definitions *****************************/ - -/****************************************************************************/ -/** -* -* Initialize a specific timer instance/driver. This function must be called -* before other functions of the driver are called. -* -* @param InstancePtr is a pointer to the XScuTimer instance. -* @param ConfigPtr points to the XScuTimer configuration structure. -* @param EffectiveAddress is the base address for the device. It could be -* a virtual address if address translation is supported in the -* system, otherwise it is the physical address. -* -* @return -* - XST_SUCCESS if initialization was successful. -* - XST_DEVICE_IS_STARTED if the device has already been started. -* -* @note None. -* -******************************************************************************/ -int XScuTimer_CfgInitialize(XScuTimer *InstancePtr, - XScuTimer_Config *ConfigPtr, u32 EffectiveAddress) -{ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(ConfigPtr != NULL); - - /* - * If the device is started, disallow the initialize and return a - * status indicating it is started. This allows the user to stop the - * device and reinitialize, but prevents a user from inadvertently - * initializing. - */ - if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) { - return XST_DEVICE_IS_STARTED; - } - - /* - * Copy configuration into the instance structure. - */ - InstancePtr->Config.DeviceId = ConfigPtr->DeviceId; - - /* - * Save the base address pointer such that the registers of the block - * can be accessed and indicate it has not been started yet. - */ - InstancePtr->Config.BaseAddr = EffectiveAddress; - - InstancePtr->IsStarted = 0; - - /* - * Indicate the instance is ready to use, successfully initialized. - */ - InstancePtr->IsReady = XIL_COMPONENT_IS_READY; - - return XST_SUCCESS; -} - -/****************************************************************************/ -/** -* -* Start the timer. -* -* @param InstancePtr is a pointer to the XScuTimer instance. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XScuTimer_Start(XScuTimer *InstancePtr) -{ - u32 Register; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the contents of the Control register. - */ - Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr, - XSCUTIMER_CONTROL_OFFSET); - - /* - * Set the 'timer enable' bit in the register. - */ - Register |= XSCUTIMER_CONTROL_ENABLE_MASK; - - /* - * Update the Control register with the new value. - */ - XScuTimer_WriteReg(InstancePtr->Config.BaseAddr, - XSCUTIMER_CONTROL_OFFSET, Register); - - /* - * Indicate that the device is started. - */ - InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED; -} - -/****************************************************************************/ -/** -* -* Stop the timer. -* -* @param InstancePtr is a pointer to the XScuTimer instance. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XScuTimer_Stop(XScuTimer *InstancePtr) -{ - u32 Register; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the contents of the Control register. - */ - Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr, - XSCUTIMER_CONTROL_OFFSET); - - /* - * Clear the 'timer enable' bit in the register. - */ - Register &= ~XSCUTIMER_CONTROL_ENABLE_MASK; - - /* - * Update the Control register with the new value. - */ - XScuTimer_WriteReg(InstancePtr->Config.BaseAddr, - XSCUTIMER_CONTROL_OFFSET, Register); - - /* - * Indicate that the device is stopped. - */ - InstancePtr->IsStarted = 0; -} - -/*****************************************************************************/ -/** -* -* This function sets the prescaler bits in the timer control register. -* -* @param InstancePtr is a pointer to the XScuTimer instance. -* @param PrescalerValue is a 8 bit value that sets the prescaler to use. -* -* @return None -* -* @note None -* -****************************************************************************/ -void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue) -{ - u32 ControlReg; - - /* - * Assert to validate input arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - /* - * Read the Timer control register. - */ - ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr, - XSCUTIMER_CONTROL_OFFSET); - - /* - * Clear all of the prescaler control bits in the register. - */ - ControlReg &= ~XSCUTIMER_CONTROL_PRESCALER_MASK; - - /* - * Set the prescaler value. - */ - ControlReg |= (PrescalerValue << XSCUTIMER_CONTROL_PRESCALER_SHIFT); - - /* - * Write the register with the new values. - */ - XScuTimer_WriteReg(InstancePtr->Config.BaseAddr, - XSCUTIMER_CONTROL_OFFSET, ControlReg); -} - -/*****************************************************************************/ -/** -* -* This function returns the current prescaler value. -* -* @param InstancePtr is a pointer to the XScuTimer instance. -* -* @return The prescaler value. -* -* @note None. -* -****************************************************************************/ -u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr) -{ - u32 ControlReg; - - /* - * Assert to validate input arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the Timer control register. - */ - ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr, - XSCUTIMER_CONTROL_OFFSET); - ControlReg &= XSCUTIMER_CONTROL_PRESCALER_MASK; - - return (ControlReg >> XSCUTIMER_CONTROL_PRESCALER_SHIFT); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v1_02_a/src/xscutimer.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v1_02_a/src/xscutimer.h deleted file mode 100644 index 464cf22a15505972c9a91be2f8d66b82838a221a..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v1_02_a/src/xscutimer.h +++ /dev/null @@ -1,365 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file xscutimer.h -* -* The timer driver supports the Cortex A9 private timer. -* -* The timer driver supports the following features: -* - Normal mode and Auto reload mode -* - Interrupts (Interrupt handler is not provided in this driver. Application -* has to register it's own handler) -* -* <b> Initialization and Configuration </b> -* -* The device driver enables higher layer software (e.g., an application) to -* communicate with the Timer. -* -* XScuTimer_CfgInitialize() API is used to initialize the Timer. The -* user needs to first call the XScuTimer_LookupConfig() API which returns -* the Configuration structure pointer which is passed as a parameter to -* the XScuTimer_CfgInitialize() API. -* -* <b> Interrupts </b> -* -* The Timer hardware supports interrupts. -* -* This driver does not provide a Interrupt Service Routine (ISR) for the device. -* It is the responsibility of the application to provide one if needed. Refer to -* the interrupt example provided with this driver for details on using the -* Timer in interrupt mode. -* -* <b> Virtual Memory </b> -* -* This driver supports Virtual Memory. The RTOS is responsible for calculating -* the correct device base address in Virtual Memory space. -* -* <b> Threads </b> -* -* This driver is not thread safe. Any needs for threads or thread mutual -* exclusion must be satisfied by the layer above this driver. -* -* <b> Asserts </b> -* -* Asserts are used within all Xilinx drivers to enforce constraints on argument -* values. Asserts can be turned off on a system-wide basis by defining, at -* compile time, the NDEBUG identifier. By default, asserts are turned on and it -* is recommended that users leave asserts on during development. -* -* <b> Building the driver </b> -* -* The XScuTimer driver is composed of several source files. This allows the user -* to build and link only those parts of the driver that are necessary. -* -* <br><br> -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- --------------------------------------------- -* 1.00a nm 03/10/10 First release -* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue -* when the xstatus.h in the common driver overwrites -* the xstatus.h of the standalone BSP during the -* libgen. -* </pre> -* -******************************************************************************/ -#ifndef XSCUTIMER_H /* prevent circular inclusions */ -#define XSCUTIMER_H /* by using protection macros */ - -/***************************** Include Files *********************************/ - -#include "xstatus.h" -#include "xscutimer_hw.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/** - * This typedef contains configuration information for the device. - */ -typedef struct { - u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddr; /**< Base address of the device */ -} XScuTimer_Config; - -/** - * The XScuTimer driver instance data. The user is required to allocate a - * variable of this type for every timer device in the system. - * A pointer to a variable of this type is then passed to the driver API - * functions. - */ -typedef struct { - XScuTimer_Config Config; /**< Hardware Configuration */ - u32 IsReady; /**< Device is initialized and ready */ - u32 IsStarted; /**< Device timer is running */ -} XScuTimer; - -/***************** Macros (Inline Functions) Definitions *********************/ - -/****************************************************************************/ -/** -* -* Check if the timer has expired. -* -* @param InstancePtr is a pointer to the XScuTimer instance. -* -* @return -* - TRUE if the timer has expired. -* - FALSE if the timer has not expired. -* -* @note C-style signature: -* int XScuTimer_IsExpired(XScuTimer *InstancePtr) -* -******************************************************************************/ -#define XScuTimer_IsExpired(InstancePtr) \ - ((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_ISR_OFFSET) & \ - XSCUTIMER_ISR_EVENT_FLAG_MASK) == \ - XSCUTIMER_ISR_EVENT_FLAG_MASK) - -/****************************************************************************/ -/** -* -* Re-start the timer. This macro will read the timer load register -* and writes the same value to load register to update the counter register. -* -* @param InstancePtr is a pointer to the XScuTimer instance. -* -* @return None. -* -* @note C-style signature: -* void XScuTimer_RestartTimer(XScuTimer *InstancePtr) -* -******************************************************************************/ -#define XScuTimer_RestartTimer(InstancePtr) \ - XScuTimer_LoadTimer(InstancePtr, \ - XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_LOAD_OFFSET)) - -/****************************************************************************/ -/** -* -* Write to the timer load register. This will also update the -* timer counter register with the new value. This macro can be used to -* change the time-out value. -* -* @param InstancePtr is a pointer to the XScuTimer instance. -* @param Value is the count to be loaded in to the load register. -* -* @return None. -* -* @note C-style signature: -* void XScuTimer_LoadTimer(XScuTimer *InstancePtr, u32 Value) -* -******************************************************************************/ -#define XScuTimer_LoadTimer(InstancePtr, Value) \ - XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_LOAD_OFFSET, Value) - -/****************************************************************************/ -/** -* -* Returns the current timer counter register value. It can be called at any -* time. -* -* @param InstancePtr is a pointer to the XScuTimer instance. -* -* @return Contents of the timer counter register. -* -* @note C-style signature: - u32 XScuTimer_GetCounterValue(XScuTimer *InstancePtr) -* -******************************************************************************/ -#define XScuTimer_GetCounterValue(InstancePtr) \ - XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_COUNTER_OFFSET) - -/****************************************************************************/ -/** -* -* Enable auto-reload mode. -* -* @param InstancePtr is a pointer to the XScuTimer instance. -* -* @return None. -* -* @note C-style signature: -* void XScuTimer_EnableAutoReload(XScuTimer *InstancePtr) -* -******************************************************************************/ -#define XScuTimer_EnableAutoReload(InstancePtr) \ - XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET, \ - (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET) | \ - XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)) - -/****************************************************************************/ -/** -* -* Disable auto-reload mode. -* -* @param InstancePtr is a pointer to the XScuTimer instance. -* -* @return None. -* -* @note C-style signature: -* void XScuTimer_DisableAutoReload(XScuTimer *InstancePtr) -* -******************************************************************************/ -#define XScuTimer_DisableAutoReload(InstancePtr) \ - XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET, \ - (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET) & \ - ~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))) - -/****************************************************************************/ -/** -* -* Enable the Timer interrupt. -* -* @param InstancePtr is a pointer to the XScuTimer instance. -* -* @return None. -* -* @note C-style signature: -* void XScuTimer_EnableInterrupt(XScuTimer *InstancePtr) -* -******************************************************************************/ -#define XScuTimer_EnableInterrupt(InstancePtr) \ - XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET, \ - (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET) | \ - XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)) - -/****************************************************************************/ -/** -* -* Disable the Timer interrupt. -* -* @param InstancePtr is a pointer to the XScuTimer instance. -* -* @return None. -* -* @note C-style signature: -* void XScuTimer_DisableInterrupt(XScuTimer *InstancePtr) -* -******************************************************************************/ -#define XScuTimer_DisableInterrupt(InstancePtr) \ - XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET, \ - (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_CONTROL_OFFSET) & \ - ~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))) - -/*****************************************************************************/ -/** -* -* This function reads the interrupt status. -* -* @param InstancePtr is a pointer to the XScuTimer instance. -* -* @return None. -* -* @note C-style signature: -* void XScuTimer_GetInterruptStatus(XScuTimer *InstancePtr) -* -******************************************************************************/ -#define XScuTimer_GetInterruptStatus(InstancePtr) \ - XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_ISR_OFFSET) - -/*****************************************************************************/ -/** -* -* This function clears the interrupt status. -* -* @param InstancePtr is a pointer to the XScuTimer instance. -* -* @return None. -* -* @note C-style signature: -* void XScuTimer_ClearInterruptStatus(XScuTimer *InstancePtr) -* -******************************************************************************/ -#define XScuTimer_ClearInterruptStatus(InstancePtr) \ - XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK) - -/************************** Function Prototypes ******************************/ - -/* - * Lookup configuration in xscutimer_sinit.c - */ -XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId); - -/* - * Selftest function in xscutimer_selftest.c - */ -int XScuTimer_SelfTest(XScuTimer *InstancePtr); - -/* - * Interface functions in xscutimer.c - */ -int XScuTimer_CfgInitialize(XScuTimer *InstancePtr, - XScuTimer_Config *ConfigPtr, u32 EffectiveAddress); -void XScuTimer_Start(XScuTimer *InstancePtr); -void XScuTimer_Stop(XScuTimer *InstancePtr); -void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue); -u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v1_02_a/src/xscutimer_g.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v1_02_a/src/xscutimer_g.c deleted file mode 100644 index e03cf4631024f475c4ccfd180452e90b569a5123..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v1_02_a/src/xscutimer_g.c +++ /dev/null @@ -1,30 +0,0 @@ - -/******************************************************************* -* -* CAUTION: This file is automatically generated by libgen. -* Version: Xilinx EDK 14.7 EDK_P.20131013 -* DO NOT EDIT. -* -* Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. - -* -* Description: Driver configuration -* -*******************************************************************/ - -#include "xparameters.h" -#include "xscutimer.h" - -/* -* The configuration table for devices -*/ - -XScuTimer_Config XScuTimer_ConfigTable[] = -{ - { - XPAR_PS7_SCUTIMER_0_DEVICE_ID, - XPAR_PS7_SCUTIMER_0_BASEADDR - } -}; - - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v1_02_a/src/xscutimer_hw.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v1_02_a/src/xscutimer_hw.h deleted file mode 100644 index d18cf6366254e6e83ef4ea7d76b7baa9993b2810..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v1_02_a/src/xscutimer_hw.h +++ /dev/null @@ -1,292 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file xscutimer_hw.h -* -* This file contains the hardware interface to the Timer. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- --------------------------------------------- -* 1.00a nm 03/10/10 First release -* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control -* and interrupt registers -* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue -* when the xstatus.h in the common driver overwrites -* the xstatus.h of the standalone BSP during the -* libgen. -* </pre> -* -******************************************************************************/ -#ifndef XSCUTIMER_HW_H /* prevent circular inclusions */ -#define XSCUTIMER_HW_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ -#include "xil_types.h" -#include "xil_io.h" -#include "xil_assert.h" -/************************** Constant Definitions *****************************/ - -/** @name Register Map - * Offsets of registers from the start of the device - * @{ - */ - -#define XSCUTIMER_LOAD_OFFSET 0x00 /**< Timer Load Register */ -#define XSCUTIMER_COUNTER_OFFSET 0x04 /**< Timer Counter Register */ -#define XSCUTIMER_CONTROL_OFFSET 0x08 /**< Timer Control Register */ -#define XSCUTIMER_ISR_OFFSET 0x0C /**< Timer Interrupt - Status Register */ -/* @} */ - -/** @name Timer Control register - * This register bits control the prescaler, Intr enable, - * auto-reload and timer enable. - * @{ - */ - -#define XSCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00 /**< Prescaler */ -#define XSCUTIMER_CONTROL_PRESCALER_SHIFT 8 -#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004 /**< Intr enable */ -#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002 /**< Auto-reload */ -#define XSCUTIMER_CONTROL_ENABLE_MASK 0x00000001 /**< Timer enable */ -/* @} */ - -/** @name Interrupt Status register - * This register indicates the Timer counter register has reached zero. - * @{ - */ - -#define XSCUTIMER_ISR_EVENT_FLAG_MASK 0x00000001 /**< Event flag */ -/*@}*/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/****************************************************************************/ -/** -* -* Write to the timer load register. This will also update the -* timer counter register with the new value. This macro can be used to -* change the time-out value. -* -* @param BaseAddr is the base address of the scu timer. -* @param Value is the count to be loaded in to the load register. -* -* @return None. -* -* @note C-style signature: -* void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value) -* -******************************************************************************/ -#define XScuTimer_SetLoadReg(BaseAddr, Value) \ - XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, Value) - -/****************************************************************************/ -/** -* -* Returns the current timer load register value. -* -* @param BaseAddr is the base address of the scu timer. -* -* @return Contents of the timer load register. -* -* @note C-style signature: -* u32 XScuTimer_GetLoadReg(u32 BaseAddr) -* -******************************************************************************/ -#define XScuTimer_GetLoadReg(BaseAddr) \ - XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET) - -/****************************************************************************/ -/** -* -* Write to the timer counter register. -* -* @param BaseAddr is the base address of the scu timer. -* @param Value is the count to be loaded in to the counter register. -* -* @return None. -* -* @note C-style signature: -* void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value) -* -******************************************************************************/ -#define XScuTimer_SetCounterReg(BaseAddr, Value) \ - XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, Value) - -/****************************************************************************/ -/** -* -* Returns the current timer counter register value. -* -* @param BaseAddr is the base address of the scu timer. -* -* @return Contents of the timer counter register. -* -* @note C-style signature: - u32 XScuTimer_GetCounterReg(u32 BaseAddr) -* -******************************************************************************/ -#define XScuTimer_GetCounterReg(BaseAddr) \ - XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET) - -/****************************************************************************/ -/** -* -* Write to the timer load register. This will also update the -* timer counter register with the new value. This macro can be used to -* change the time-out value. -* -* @param BaseAddr is the base address of the scu timer. -* @param Value is the count to be loaded in to the load register. -* -* @return None. -* -* @note C-style signature: -* void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value) -* -******************************************************************************/ -#define XScuTimer_SetControlReg(BaseAddr, Value) \ - XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, Value) - -/****************************************************************************/ -/** -* -* Returns the current timer load register value. -* -* @param BaseAddr is the base address of the scu timer. -* -* @return Contents of the timer load register. -* -* @note C-style signature: - u32 XScuTimer_GetControlReg(u32 BaseAddr) -* -******************************************************************************/ -#define XScuTimer_GetControlReg(BaseAddr) \ - XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET) - -/****************************************************************************/ -/** -* -* Write to the timer counter register. -* -* @param BaseAddr is the base address of the scu timer. -* @param Value is the count to be loaded in to the counter register. -* -* @return None. -* -* @note C-style signature: -* void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value) -* -******************************************************************************/ -#define XScuTimer_SetIntrReg(BaseAddr, Value) \ - XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, Value) - -/****************************************************************************/ -/** -* -* Returns the current timer counter register value. -* -* @param BaseAddr is the base address of the scu timer. -* -* @return Contents of the timer counter register. -* -* @note C-style signature: - u32 XScuTimer_GetIntrReg(u32 BaseAddr) -* -******************************************************************************/ -#define XScuTimer_GetIntrReg(BaseAddr) \ - XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET) - -/****************************************************************************/ -/** -* -* Read from the given Timer register. -* -* @param BaseAddr is the base address of the device -* @param RegOffset is the register offset to be read -* -* @return The 32-bit value of the register -* -* @note C-style signature: -* u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset) -* -*****************************************************************************/ -#define XScuTimer_ReadReg(BaseAddr, RegOffset) \ - Xil_In32((BaseAddr) + (RegOffset)) - -/****************************************************************************/ -/** -* -* Write to the given Timer register. -* -* @param BaseAddr is the base address of the device -* @param RegOffset is the register offset to be written -* @param Data is the 32-bit value to write to the register -* -* @return None. -* -* @note C-style signature: -* void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data) -* -*****************************************************************************/ -#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data) \ - Xil_Out32((BaseAddr) + (RegOffset), (Data)) - -/************************** Function Prototypes ******************************/ - -/************************** Variable Definitions *****************************/ - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v1_02_a/src/xscutimer_selftest.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v1_02_a/src/xscutimer_selftest.c deleted file mode 100644 index 8aedc229504bec8effce8f39eafeba8e518f0ef2..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v1_02_a/src/xscutimer_selftest.c +++ /dev/null @@ -1,140 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file xscutimer_selftest.c -* -* Contains diagnostic self-test functions for the XScuTimer driver. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- --------------------------------------------- -* 1.00a nm 03/10/10 First release -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xscutimer.h" - -/************************** Constant Definitions *****************************/ - -#define XSCUTIMER_SELFTEST_VALUE 0xA55AF00F - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/************************** Variable Definitions *****************************/ - -/****************************************************************************/ -/** -* -* Run a self-test on the timer. This test clears the timer enable bit in -* the control register, writes to the timer load register and verifies the -* value read back matches the value written and restores the control register -* and the timer load register. -* -* @param InstancePtr is a pointer to the XScuTimer instance. -* -* @return -* - XST_SUCCESS if self-test was successful. -* - XST_FAILURE if self test was not successful. -* -* @note None. -* -******************************************************************************/ -int XScuTimer_SelfTest(XScuTimer *InstancePtr) -{ - u32 Register; - u32 CtrlOrig; - u32 LoadOrig; - - /* - * Assert to ensure the inputs are valid and the instance has been - * initialized. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Save the contents of the Control Register and stop the timer. - */ - CtrlOrig = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr, - XSCUTIMER_CONTROL_OFFSET); - Register = CtrlOrig & ~XSCUTIMER_CONTROL_ENABLE_MASK; - XScuTimer_WriteReg(InstancePtr->Config.BaseAddr, - XSCUTIMER_CONTROL_OFFSET, Register); - - /* - * Save the contents of the Load Register. - * Load a new test value in the Load Register, read it back and - * compare it with the written value. - */ - LoadOrig = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, - XSCUTIMER_LOAD_OFFSET); - XScuTimer_LoadTimer(InstancePtr, XSCUTIMER_SELFTEST_VALUE); - Register = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, - XSCUTIMER_LOAD_OFFSET); - - /* - * Restore the contents of the Load Register and Control Register. - */ - XScuTimer_LoadTimer(InstancePtr, LoadOrig); - XScuTimer_WriteReg(InstancePtr->Config.BaseAddr, - XSCUTIMER_CONTROL_OFFSET, CtrlOrig); - - /* - * Return a Failure if the contents of the Load Register do not - * match with the value written to it. - */ - if (Register != XSCUTIMER_SELFTEST_VALUE) { - return XST_FAILURE; - } - - return XST_SUCCESS; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v1_02_a/src/xscutimer_sinit.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v1_02_a/src/xscutimer_sinit.c deleted file mode 100644 index 65652897e29e388bace10bd81d5cc9b3ad2b8b49..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scutimer_v1_02_a/src/xscutimer_sinit.c +++ /dev/null @@ -1,99 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xscutimer_sinit.c -* -* This file contains method for static initialization (compile-time) of the -* driver. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- --------------------------------------------- -* 1.00a nm 03/10/10 First release -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xscutimer.h" -#include "xparameters.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/*****************************************************************************/ -/** -* Lookup the device configuration based on the unique device ID. The table -* contains the configuration info for each device in the system. -* -* @param DeviceId is the unique device ID of the device being looked up. -* -* @return A pointer to the configuration table entry corresponding to the -* given device ID, or NULL if no match is found. -* -* @note None. -* -******************************************************************************/ -XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId) -{ - extern XScuTimer_Config XScuTimer_ConfigTable[]; - XScuTimer_Config *CfgPtr = NULL; - int Index; - - for (Index = 0; Index < XPAR_XSCUTIMER_NUM_INSTANCES; Index++) { - if (XScuTimer_ConfigTable[Index].DeviceId == DeviceId) { - CfgPtr = &XScuTimer_ConfigTable[Index]; - break; - } - } - - return (CfgPtr); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v1_02_a/src/Makefile b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v1_02_a/src/Makefile deleted file mode 100644 index 2c783d4a703e19a7fa18fe49873b2b0dea88db7f..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v1_02_a/src/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -COMPILER= -ARCHIVER= -CP=cp -COMPILER_FLAGS= -EXTRA_COMPILER_FLAGS= -LIB=libxil.a - -CC_FLAGS = $(COMPILER_FLAGS) -ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) - -RELEASEDIR=../../../lib -INCLUDEDIR=../../../include -INCLUDES=-I./. -I${INCLUDEDIR} - -OUTS = *.o - -LIBSOURCES:=*.c -INCLUDEFILES:=*.h - -OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) - -libs: banner scuwdt_libs clean - -%.o: %.c - ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< - -banner: - echo "Compiling scuwdt" - -scuwdt_libs: ${OBJECTS} - $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} - -.PHONY: include -include: scuwdt_includes - -scuwdt_includes: - ${CP} ${INCLUDEFILES} ${INCLUDEDIR} - -clean: - rm -rf ${OBJECTS} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v1_02_a/src/xscuwdt.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v1_02_a/src/xscuwdt.c deleted file mode 100644 index f561d8d7f387ba6ed0bbec914893ac4f249ec7ab..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v1_02_a/src/xscuwdt.c +++ /dev/null @@ -1,219 +0,0 @@ -/* $Id: xscuwdt.c,v 1.1.2.1 2011/01/20 04:04:40 sadanan Exp $ */ -/****************************************************************************** -* -* (c) Copyright 2010 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file xscuwdt.c -* -* Contains the implementation of interface functions of the XScuWdt driver. -* See xscuwdt.h for a description of the driver. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- --------------------------------------------- -* 1.00a sdm 01/15/10 First release -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xscuwdt.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/************************** Variable Definitions *****************************/ - -/****************************************************************************/ -/** -* -* Initialize a specific watchdog timer instance/driver. This function -* must be called before other functions of the driver are called. -* -* @param InstancePtr is a pointer to the XScuWdt instance. -* @param ConfigPtr is the config structure. -* @param EffectiveAddress is the base address for the device. It could be -* a virtual address if address translation is supported in the -* system, otherwise it is the physical address. -* -* @return -* - XST_SUCCESS if initialization was successful. -* - XST_DEVICE_IS_STARTED if the device has already been started. -* -* @note This function enables the watchdog mode. -* -******************************************************************************/ -int XScuWdt_CfgInitialize(XScuWdt *InstancePtr, - XScuWdt_Config *ConfigPtr, u32 EffectiveAddress) -{ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(ConfigPtr != NULL); - - /* - * If the device is started, disallow the initialize and return a - * status indicating it is started. This allows the user to stop the - * device and reinitialize, but prevents a user from inadvertently - * initializing. - */ - if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) { - return XST_DEVICE_IS_STARTED; - } - - /* - * Copy configuration into instance. - */ - InstancePtr->Config.DeviceId = ConfigPtr->DeviceId; - - /* - * Save the base address pointer such that the registers of the block - * can be accessed and indicate it has not been started yet. - */ - InstancePtr->Config.BaseAddr = EffectiveAddress; - InstancePtr->IsStarted = 0; - - /* - * Put the watchdog timer in Watchdog mode. - */ - XScuWdt_SetWdMode(InstancePtr); - - /* - * Indicate the instance is ready to use, successfully initialized. - */ - InstancePtr->IsReady = XIL_COMPONENT_IS_READY; - - return XST_SUCCESS; -} - -/****************************************************************************/ -/** -* -* Start the watchdog counter of the device. -* -* @param InstancePtr is a pointer to the XScuWdt instance. -* -* @return None. -* -* @note User needs to select the appropriate mode (watchdog/timer) -* before using this API. -* See XScuWdt_SetWdMode/XScuWdt_SetTimerMode macros in -* xscuwdt.h. -* -******************************************************************************/ -void XScuWdt_Start(XScuWdt *InstancePtr) -{ - u32 Register; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the contents of the Control register. - */ - Register = XScuWdt_ReadReg(InstancePtr->Config.BaseAddr, - XSCUWDT_CONTROL_OFFSET); - - /* - * Set the 'watchdog enable' bit in the register. - */ - Register |= XSCUWDT_CONTROL_WD_ENABLE_MASK; - - /* - * Update the Control register with the new value. - */ - XScuWdt_WriteReg(InstancePtr->Config.BaseAddr, - XSCUWDT_CONTROL_OFFSET, Register); - - /* - * Indicate that the device is started. - */ - InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED; -} - -/****************************************************************************/ -/** -* -* Stop the watchdog timer. -* -* @param InstancePtr is a pointer to the XScuWdt instance. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XScuWdt_Stop(XScuWdt *InstancePtr) -{ - u32 Register; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the contents of the Control register. - */ - Register = XScuWdt_ReadReg(InstancePtr->Config.BaseAddr, - XSCUWDT_CONTROL_OFFSET); - - /* - * Clear the 'watchdog enable' bit in the register. - */ - Register &= ~XSCUWDT_CONTROL_WD_ENABLE_MASK; - - /* - * Update the Control register with the new value. - */ - XScuWdt_WriteReg(InstancePtr->Config.BaseAddr, - XSCUWDT_CONTROL_OFFSET, Register); - - /* - * Indicate that the device is stopped. - */ - InstancePtr->IsStarted = 0; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v1_02_a/src/xscuwdt.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v1_02_a/src/xscuwdt.h deleted file mode 100644 index 39ecd7d18b9bbf5e32810c3672533457ccfed790..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v1_02_a/src/xscuwdt.h +++ /dev/null @@ -1,384 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file xscuwdt.h -* -* The Xilinx SCU watchdog timer driver (XScuWdt) supports the Xilinx SCU private -* watchdog timer hardware. -* -* The XScuWdt driver supports the following features: -* - Watchdog mode -* - Timer mode -* - Auto reload (timer mode only) -* -* The watchdog counter register is a down counter and starts decrementing when -* the watchdog is started. -* In watchdog mode, when the counter reaches 0, the Reset flag is set in the -* Reset status register and the WDRESETREQ pin is asserted, causing a system -* reset. The Reset flag is not reset by normal processor reset and is cleared -* when written with a value of 1. This enables the user to differentiate a -* normal reset and a reset caused by watchdog time-out. The user needs to call -* XScuWdt_RestartWdt() periodically, to avoid the watchdog from being timed-out. -* -* The IsWdtExpired function can be used to check if the watchdog was the cause -* of the last reset. In this situation, call Initialize then call IsWdtExpired. -* If the result is true, watchdog timeout caused the last system reset. The -* application then needs to clear the Reset flag. -* -* In timer mode, when the counter reaches 0, the Event flag is set in the -* Interrupt status register and if interrupts are enabled, interrupt ID 30 is -* set as pending in the interrupt distributor. The IsTimerExpired function -* is used to check if the watchdog counter has decremented to 0 in timer mode. -* If auto-reload mode is enabled, the Counter register is automatically reloaded -* from the Load register. -* -* <b> Initialization and Configuration </b> -* -* The device driver enables higher layer software (e.g., an application) to -* communicate with the Watchdog Timer. -* -* XScuWdt_CfgInitialize() API is used to initialize the Watchdog Timer. The -* user needs to first call the XScuWdt_LookupConfig() API which returns -* the Configuration structure pointer which is passed as a parameter to -* the XScuWdt_CfgInitialize() API. -* -* <b>Interrupts</b> -* -* The SCU Watchdog Timer supports interrupts in Timer mode. -* -* This driver does not provide a Interrupt Service Routine (ISR) for the device. -* It is the responsibility of the application to provide one if needed. Refer to -* the interrupt example provided with this driver for details on using the -* Timer in interrupt mode. -* -* <b> Virtual Memory </b> -* -* This driver supports Virtual Memory. The RTOS is responsible for calculating -* the correct device base address in Virtual Memory space. -* -* <b> Threads </b> -* -* This driver is not thread safe. Any needs for threads or thread mutual -* exclusion must be satisfied by the layer above this driver. -* -* <b> Asserts </b> -* -* Asserts are used within all Xilinx drivers to enforce constraints on argument -* values. Asserts can be turned off on a system-wide basis by defining, at -* compile time, the NDEBUG identifier. By default, asserts are turned on and it -* is recommended that users leave asserts on during development. -* -* <b> Building the driver </b> -* -* The XScuWdt driver is composed of several source files. This allows the user -* to build and link only those parts of the driver that are necessary. -* -* <br><br> -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- --------------------------------------------- -* 1.00a sdm 01/15/10 First release -* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue -* when the xstatus.h in the common driver overwrites -* the xstatus.h of the standalone BSP during the -* libgen. -* </pre> -* -******************************************************************************/ -#ifndef XSCUWDT_H /* prevent circular inclusions */ -#define XSCUWDT_H /* by using protection macros */ - -/***************************** Include Files *********************************/ - -#include "xstatus.h" -#include "xscuwdt_hw.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/** - * This typedef contains configuration information for the device. - */ -typedef struct { - u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddr; /**< Base address of the device */ -} XScuWdt_Config; - -/** - * The XScuWdt driver instance data. The user is required to allocate a - * variable of this type for every watchdog/timer device in the system. - * A pointer to a variable of this type is then passed to the driver API - * functions. - */ -typedef struct { - XScuWdt_Config Config;/**< Hardware Configuration */ - u32 IsReady; /**< Device is initialized and ready */ - u32 IsStarted; /**< Device watchdog timer is running */ -} XScuWdt; - -/***************** Macros (Inline Functions) Definitions *********************/ -/****************************************************************************/ -/** -* -* This function is used to check if the watchdog has timed-out and the last -* reset was caused by the watchdog reset. -* -* @param InstancePtr is a pointer to the XScuWdt instance. -* -* @return -* - TRUE if the watchdog has expired. -* - FALSE if the watchdog has not expired. -* -* @note C-style signature: -* int XScuWdt_IsWdtExpired(XScuWdt *InstancePtr) -* -******************************************************************************/ -#define XScuWdt_IsWdtExpired(InstancePtr) \ - ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUWDT_RST_STS_OFFSET) & \ - XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK) - -/****************************************************************************/ -/** -* -* This function is used to check if the watchdog counter has reached 0 in timer -* mode. -* -* @param InstancePtr is a pointer to the XScuWdt instance. -* -* @return -* - TRUE if the watchdog has expired. -* - FALSE if the watchdog has not expired. -* -* @note C-style signature: -* int XScuWdt_IsTimerExpired(XScuWdt *InstancePtr) -* -******************************************************************************/ -#define XScuWdt_IsTimerExpired(InstancePtr) \ - ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUWDT_ISR_OFFSET) & \ - XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK) - -/****************************************************************************/ -/** -* -* Re-start the watchdog timer. This macro will read the watchdog load register -* and write the same value to load register to update the counter register. -* An application needs to call this function periodically to keep the watchdog -* from asserting the WDRESETREQ reset request output pin. -* -* @param InstancePtr is a pointer to the XScuWdt instance. -* -* @return None. -* -* @note C-style signature: -* void XScuWdt_RestartWdt(XScuWdt *InstancePtr) -* -******************************************************************************/ -#define XScuWdt_RestartWdt(InstancePtr) \ - XScuWdt_LoadWdt(InstancePtr, \ - (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUWDT_LOAD_OFFSET))) - -/****************************************************************************/ -/** -* -* Write to the watchdog timer load register. This will also update the -* watchdog counter register with the new value. This macro can be used to -* change the time-out value. -* -* @param InstancePtr is a pointer to the XScuWdt instance. -* @param Value is the value to be written to the Watchdog Load register. -* -* @return None. -* -* @note C-style signature: -* void XScuWdt_LoadWdt(XScuWdt *InstancePtr, u32 Value) -* -******************************************************************************/ -#define XScuWdt_LoadWdt(InstancePtr, Value) \ - XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUWDT_LOAD_OFFSET, Value) - -/****************************************************************************/ -/** -* -* Put the watchdog timer in Watchdog mode by setting the WD mode bit of the -* Watchdog control register. -* -* @param InstancePtr is a pointer to the XScuWdt instance. -* -* @return None. -* -* @note C-style signature: -* void XScuWdt_SetWdMode(XScuWdt *InstancePtr) -* -******************************************************************************/ -#define XScuWdt_SetWdMode(InstancePtr) \ - XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUWDT_CONTROL_OFFSET, \ - (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUWDT_CONTROL_OFFSET) | \ - XSCUWDT_CONTROL_WD_MODE_MASK)) - -/****************************************************************************/ -/** -* -* Put the watchdog timer in Timer mode by writing 0x12345678 and 0x87654321 -* successively to the Watchdog Disable Register. -* The software must write 0x12345678 and 0x87654321 successively to the -* Watchdog Disable Register so that the watchdog mode bit in the Watchdog -* Control Register is set to zero. -* -* @param InstancePtr is a pointer to the XScuWdt instance. -* -* @return None. -* -* @note C-style signature: -* void XScuWdt_SetTimerMode(XScuWdt *InstancePtr) -* -******************************************************************************/ -#define XScuWdt_SetTimerMode(InstancePtr) \ -{ \ - XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUWDT_DISABLE_OFFSET, \ - XSCUWDT_DISABLE_VALUE1); \ - XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUWDT_DISABLE_OFFSET, \ - XSCUWDT_DISABLE_VALUE2); \ -} - -/****************************************************************************/ -/** -* -* Get the contents of the watchdog control register. -* -* @param InstancePtr is a pointer to the XScuWdt instance. -* -* @return Contents of the watchdog control register. -* -* @note C-style signature: - u32 XScuWdt_GetControlReg(XScuWdt *InstancePtr) -* -******************************************************************************/ -#define XScuWdt_GetControlReg(InstancePtr) \ - XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ - XSCUWDT_CONTROL_OFFSET) - -/****************************************************************************/ -/** -* -* Write to the watchdog control register. -* -* @param InstancePtr is a pointer to the XScuWdt instance. -* @param ControlReg is the value to be written to the watchdog control -* register. -* -* @return None. -* -* @note C-style signature: - void XScuWdt_SetControlReg(XScuWdt *InstancePtr, u32 ControlReg) -* -******************************************************************************/ -#define XScuWdt_SetControlReg(InstancePtr, ControlReg) \ - XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ - XSCUWDT_CONTROL_OFFSET, ControlReg) - -/****************************************************************************/ -/** -* -* Enable auto-reload mode. -* -* @param InstancePtr is a pointer to the XScuWdt instance. -* -* @return None. -* -* @note C-style signature: -* void XScuWdt_EnableAutoReload(XScuWdt *InstancePtr) -* -******************************************************************************/ -#define XScuWdt_EnableAutoReload(InstancePtr) \ - XScuWdt_SetControlReg((InstancePtr), \ - (XScuWdt_GetControlReg(InstancePtr) | \ - XSCUWDT_CONTROL_AUTO_RELOAD_MASK)) - -/************************** Function Prototypes ******************************/ - -/* - * Lookup configuration in xscuwdt_sinit.c. - */ -XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId); - -/* - * Selftest function in xscuwdt_selftest.c - */ -int XScuWdt_SelfTest(XScuWdt *InstancePtr); - -/* - * Interface functions in xscuwdt.c - */ -int XScuWdt_CfgInitialize(XScuWdt *InstancePtr, - XScuWdt_Config *ConfigPtr, u32 EffectiveAddress); - -void XScuWdt_Start(XScuWdt *InstancePtr); - -void XScuWdt_Stop(XScuWdt *InstancePtr); - -/* - * Self-test function in xwdttb_selftest.c. - */ -int XScuWdt_SelfTest(XScuWdt *InstancePtr); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v1_02_a/src/xscuwdt_g.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v1_02_a/src/xscuwdt_g.c deleted file mode 100644 index ed1ead33b6c1043f664b9751e39c03803f415410..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v1_02_a/src/xscuwdt_g.c +++ /dev/null @@ -1,30 +0,0 @@ - -/******************************************************************* -* -* CAUTION: This file is automatically generated by libgen. -* Version: Xilinx EDK 14.7 EDK_P.20131013 -* DO NOT EDIT. -* -* Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. - -* -* Description: Driver configuration -* -*******************************************************************/ - -#include "xparameters.h" -#include "xscuwdt.h" - -/* -* The configuration table for devices -*/ - -XScuWdt_Config XScuWdt_ConfigTable[] = -{ - { - XPAR_PS7_SCUWDT_0_DEVICE_ID, - XPAR_PS7_SCUWDT_0_BASEADDR - } -}; - - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v1_02_a/src/xscuwdt_hw.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v1_02_a/src/xscuwdt_hw.h deleted file mode 100644 index 9bf23046d9fda0868c4233acf5a1a29f1f773b85..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v1_02_a/src/xscuwdt_hw.h +++ /dev/null @@ -1,187 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file xscuwdt_hw.h -* -* This file contains the hardware interface to the Xilinx SCU private Watch Dog -* Timer (XSCUWDT). -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- --------------------------------------------- -* 1.00a sdm 01/15/10 First release -* 1.01a bss 02/27/12 Updated the register offsets to start at 0x0 instead -* of 0x20 as the base address obtained from the tools -* starts at 0x20. -* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue -* when the xstatus.h in the common driver overwrites -* the xstatus.h of the standalone BSP during the -* libgen. -* </pre> -* -******************************************************************************/ -#ifndef XSCUWDT_HW_H /* prevent circular inclusions */ -#define XSCUWDT_HW_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_io.h" -#include "xil_assert.h" -/************************** Constant Definitions *****************************/ - -/** @name Register Map - * Offsets of registers from the start of the device. The WDT registers start at - * an offset 0x20 - * @{ - */ - -#define XSCUWDT_LOAD_OFFSET 0x00 /**< Watchdog Load Register */ -#define XSCUWDT_COUNTER_OFFSET 0x04 /**< Watchdog Counter Register */ -#define XSCUWDT_CONTROL_OFFSET 0x08 /**< Watchdog Control Register */ -#define XSCUWDT_ISR_OFFSET 0x0C /**< Watchdog Interrupt Status Register */ -#define XSCUWDT_RST_STS_OFFSET 0x10 /**< Watchdog Reset Status Register */ -#define XSCUWDT_DISABLE_OFFSET 0x14 /**< Watchdog Disable Register */ -/* @} */ - -/** @name Watchdog Control register - * This register bits control the prescaler, WD/Timer mode, Intr enable, - * auto-reload, watchdog enable. - * @{ - */ - -#define XSCUWDT_CONTROL_PRESCALER_MASK 0x0000FF00 /**< Prescaler */ -#define XSCUWDT_CONTROL_PRESCALER_SHIFT 8 -#define XSCUWDT_CONTROL_WD_MODE_MASK 0x00000008 /**< Watchdog/Timer mode */ -#define XSCUWDT_CONTROL_IT_ENABLE_MASK 0x00000004 /**< Intr enable (in - timer mode) */ -#define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002 /**< Auto-reload (in - timer mode) */ -#define XSCUWDT_CONTROL_WD_ENABLE_MASK 0x00000001 /**< Watchdog enable */ -/* @} */ - -/** @name Interrupt Status register - * This register indicates the Counter register has reached zero in Counter - * mode. - * @{ - */ - -#define XSCUWDT_ISR_EVENT_FLAG_MASK 0x00000001 /**< Event flag */ -/*@}*/ - -/** @name Reset Status register - * This register indicates the Counter register has reached zero in Watchdog - * mode and a reset request is sent. - * @{ - */ - -#define XSCUWDT_RST_STS_RESET_FLAG_MASK 0x00000001 /**< Time out occured */ -/*@}*/ - -/** @name Disable register - * This register is used to switch from watchdog mode to timer mode. - * The software must write 0x12345678 and 0x87654321 successively to the - * Watchdog Disable Register so that the watchdog mode bit in the Watchdog - * Control Register is set to zero. - * @{ - */ -#define XSCUWDT_DISABLE_VALUE1 0x12345678 /**< Watchdog mode disable - value 1 */ -#define XSCUWDT_DISABLE_VALUE2 0x87654321 /**< Watchdog mode disable - value 2 */ -/*@}*/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/****************************************************************************/ -/** -* -* Read the given register. -* -* @param BaseAddr is the base address of the device -* @param RegOffset is the register offset to be read -* -* @return The 32-bit value of the register -* -* @note C-style signature: -* u32 XScuWdt_ReadReg(u32 BaseAddr, u32 RegOffset) -* -*****************************************************************************/ -#define XScuWdt_ReadReg(BaseAddr, RegOffset) \ - Xil_In32((BaseAddr) + (RegOffset)) - -/****************************************************************************/ -/** -* -* Write the given register. -* -* @param BaseAddr is the base address of the device -* @param RegOffset is the register offset to be written -* @param Data is the 32-bit value to write to the register -* -* @return None. -* -* @note C-style signature: -* void XScuWdt_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data) -* -*****************************************************************************/ -#define XScuWdt_WriteReg(BaseAddr, RegOffset, Data) \ - Xil_Out32((BaseAddr) + (RegOffset), (Data)) - -/************************** Function Prototypes ******************************/ - -/************************** Variable Definitions *****************************/ - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v1_02_a/src/xscuwdt_selftest.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v1_02_a/src/xscuwdt_selftest.c deleted file mode 100644 index 8afd5a975865298f365cc5b777bddee588383381..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v1_02_a/src/xscuwdt_selftest.c +++ /dev/null @@ -1,132 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file xscuwdt_selftest.c -* -* Contains diagnostic self-test functions for the XScuWdt driver. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- --------------------------------------------- -* 1.00a sdm 01/15/10 First release -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xscuwdt.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/************************** Variable Definitions *****************************/ - -/****************************************************************************/ -/** -* -* Run a self-test on the WDT. This test stops the watchdog, writes a value to -* the watchdog load register, starts the watchdog and verifies that the value -* read from the counter register is less that the value written to the load -* register. It then restores the control register and the watchdog load -* register. -* -* @param InstancePtr is a pointer to the XScuWdt instance. -* -* @return -* - XST_SUCCESS if self-test was successful. -* - XST_FAILURE if the WDT is not decrementing. -* -* @note None. -* -******************************************************************************/ -int XScuWdt_SelfTest(XScuWdt *InstancePtr) -{ - u32 Register; - u32 CtrlOrig; - u32 LoadOrig; - - /* - * Assert to ensure the inputs are valid and the instance has been - * initialized. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Stop the watchdog timer. - */ - CtrlOrig = XScuWdt_GetControlReg(InstancePtr); - XScuWdt_SetControlReg(InstancePtr, - CtrlOrig & ~XSCUWDT_CONTROL_WD_ENABLE_MASK); - - LoadOrig = XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, - XSCUWDT_LOAD_OFFSET); - XScuWdt_LoadWdt(InstancePtr, 0xFFFFFFFF); - - /* - * Start the watchdog timer and check if the watchdog counter is - * decrementing. - */ - XScuWdt_SetControlReg(InstancePtr, - CtrlOrig | XSCUWDT_CONTROL_WD_ENABLE_MASK); - - Register = XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, - XSCUWDT_COUNTER_OFFSET); - - XScuWdt_LoadWdt(InstancePtr, LoadOrig); - XScuWdt_SetControlReg(InstancePtr, CtrlOrig); - - if (Register == 0xFFFFFFFF) { - return XST_FAILURE; - } - - return XST_SUCCESS; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v1_02_a/src/xscuwdt_sinit.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v1_02_a/src/xscuwdt_sinit.c deleted file mode 100644 index c286994cddbdc5cea2517a8b9f91fc9d0c5691e9..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/scuwdt_v1_02_a/src/xscuwdt_sinit.c +++ /dev/null @@ -1,99 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xscuwdt_sinit.c -* -* This file contains method for static initialization (compile-time) of the -* driver. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- --- -------- --------------------------------------------- -* 1.00a sdm 01/15/10 First release -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xscuwdt.h" -#include "xparameters.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/*****************************************************************************/ -/** -* Lookup the device configuration based on the unique device ID. The table -* contains the configuration info for each device in the system. -* -* @param DeviceId is the unique device ID of the device being looked up. -* -* @return A pointer to the configuration table entry corresponding to the -* given device ID, or NULL if no match is found. -* -* @note None. -* -******************************************************************************/ -XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId) -{ - extern XScuWdt_Config XScuWdt_ConfigTable[]; - XScuWdt_Config *CfgPtr = NULL; - int Index; - - for (Index = 0; Index < XPAR_XSCUWDT_NUM_INSTANCES; Index++) { - if (XScuWdt_ConfigTable[Index].DeviceId == DeviceId) { - CfgPtr = &XScuWdt_ConfigTable[Index]; - break; - } - } - - return (CfgPtr); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/Makefile b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/Makefile deleted file mode 100644 index f7bba6f6b2f23dd640860014437b2235b7e0b075..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/Makefile +++ /dev/null @@ -1,72 +0,0 @@ -###################################################################### -# Copyright (c) 2011-13 Xilinx, Inc. All rights reserved. -# -# Xilinx, Inc. -# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR -# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION -# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE -# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO -# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY -# AND FITNESS FOR A PARTICULAR PURPOSE. -###################################################################### - -include config.make - -AS=arm-xilinx-eabi-as -CC=arm-xilinx-eabi-gcc -AR=arm-xilinx-eabi-ar -CP=cp -COMPILER_FLAGS= -EXTRA_COMPILER_FLAGS= -LIB=libxil.a - -LIB=libxil.a - -CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS)) -ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS)) - -ifeq ($(COMPILER) , arm-eabi-gcc) - ECC_FLAGS = += -nostartfiles -endif - -#The following flags are required for PEEP. We can remove them later -ECC_FLAGS += -march=armv7-a \ - -mfloat-abi=soft \ - -mfpu=neon - -RELEASEDIR=../../../lib -INCLUDEDIR=../../../include -INCLUDES=-I./. -I${INCLUDEDIR} - -OUTS = *.o - -INCLUDEFILES=*.h - -libs: $(LIBS) - -standalone_libs: $(LIBSOURCES) - echo "Compiling standalone" - $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^ - $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} - -profile_libs: - $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(ARCHIVER)" AS="$(AS)" libs - -.PHONY: include -include: standalone_includes profile_includes - -standalone_includes: - ${CP} ${INCLUDEFILES} ${INCLUDEDIR} - -profile_includes: - $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(ARCHIVER)" AS="$(AS)" include - -clean: - rm -rf ${OUTS} - $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(ARCHIVER)" AS="$(AS)" clean - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/_exit.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/_exit.c deleted file mode 100644 index 20df10bc3fe14642b9dfb0244bb3adc972d7c83a..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/_exit.c +++ /dev/null @@ -1,50 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ - -#include <unistd.h> - -/* _exit - Simple implementation. Does not return. -*/ -void _exit (int status) -{ - (void)status; - while (1); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/_exit.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/_exit.o deleted file mode 100644 index df3a83e4607af928a7de8b1f38b22313a7cc2e67..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/_exit.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/_open.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/_open.c deleted file mode 100644 index 95ad8c503a16f1907a5624ab736e47324db20ee5..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/_open.c +++ /dev/null @@ -1,62 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ - -#include <errno.h> - -#ifdef __cplusplus -extern "C" { - int _open(const char *buf, int flags, int mode); -} -#endif - -/* - * _open -- open a file descriptor. We don't have a filesystem, so - * we return an error. - */ -int _open(const char *buf, int flags, int mode) -{ - (void)buf; - (void)flags; - (void)mode; - errno = EIO; - return (-1); -} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/_open.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/_open.o deleted file mode 100644 index 3b2782853a966e80c6801afcea9d547f1a255d22..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/_open.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/_sbrk.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/_sbrk.c deleted file mode 100644 index b26195e50ca16bf09a3d168ddc312df5f36f8d7b..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/_sbrk.c +++ /dev/null @@ -1,71 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ - -#include <sys/types.h> - -extern int _heap_start; -extern int _heap_end; - -#ifdef __cplusplus -extern "C" { - caddr_t _sbrk ( int incr ); -} -#endif - -caddr_t _sbrk ( int incr ) -{ - static unsigned char *heap = NULL; - unsigned char *prev_heap; - - if (heap == NULL) { - heap = (unsigned char *)&_heap_start; - } - prev_heap = heap; - - heap += incr; - -/* if ((unsigned)heap > (unsigned)_heap_end){ - return (caddr_t) -1; - }*/ - - return (caddr_t) prev_heap; -} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/_sbrk.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/_sbrk.o deleted file mode 100644 index 00bf7acca275b54658b3f61dce5a50143107a7be..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/_sbrk.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/abort.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/abort.c deleted file mode 100644 index e8f17bb5d3d8b15f52be1df7153bec721cb13ddd..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/abort.c +++ /dev/null @@ -1,51 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ - -#include <stdlib.h> -#include <unistd.h> - -/* - * abort -- go out via exit... - */ -void abort(void) -{ - _exit(1); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/abort.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/abort.o deleted file mode 100644 index 73438ea3740d57ec98217ef7698408db888ee731..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/abort.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/asm_vectors.S b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/asm_vectors.S deleted file mode 100644 index 94b8ab0c0ec629a1b5c3498ee8bfd563258db309..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/asm_vectors.S +++ /dev/null @@ -1,205 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* @file asm_vectors.s -* -* This file contains the initial vector table for the Cortex A9 processor -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------- -------- --------------------------------------------------- -* 1.00a ecm/sdm 10/20/09 Initial version -* 3.05a sdm 02/02/12 Save lr when profiling is enabled -* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file -* 'xil_errata.h' for errata description -* </pre> -* -* @note -* -* None. -* -******************************************************************************/ -#include "xil_errata.h" - -#define __ARM_NEON__ 1 - -.org 0 -.text - -.globl _boot -.globl _vector_table - -.globl FIQInterrupt -.globl IRQInterrupt -.globl SWInterrupt -.globl DataAbortInterrupt -.globl PrefetchAbortInterrupt - -.globl IRQHandler -.globl prof_pc - -.section .vectors -_vector_table: - B _boot - B Undefined - B SVCHandler - B PrefetchAbortHandler - B DataAbortHandler - NOP /* Placeholder for address exception vector*/ - B IRQHandler - B FIQHandler - - -IRQHandler: /* IRQ vector handler */ - - stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code*/ -#ifdef __ARM_NEON__ - vpush {d0-d7} - vpush {d16-d31} - vmrs r1, FPSCR - push {r1} - vmrs r1, FPEXC - push {r1} -#endif - -#ifdef PROFILING - ldr r2, =prof_pc - subs r3, lr, #0 - str r3, [r2] -#endif - - bl IRQInterrupt /* IRQ vector */ - -#ifdef __ARM_NEON__ - pop {r1} - vmsr FPEXC, r1 - pop {r1} - vmsr FPSCR, r1 - vpop {d16-d31} - vpop {d0-d7} -#endif - ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ - - - subs pc, lr, #4 /* adjust return */ - - -FIQHandler: /* FIQ vector handler */ - stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ -#ifdef __ARM_NEON__ - vpush {d0-d7} - vpush {d16-d31} - vmrs r1, FPSCR - push {r1} - vmrs r1, FPEXC - push {r1} -#endif - -FIQLoop: - bl FIQInterrupt /* FIQ vector */ - -#ifdef __ARM_NEON__ - pop {r1} - vmsr FPEXC, r1 - pop {r1} - vmsr FPSCR, r1 - vpop {d16-d31} - vpop {d0-d7} -#endif - ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ - subs pc, lr, #4 /* adjust return */ - - -Undefined: /* Undefined handler */ - stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ - - ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ - - b _prestart - - movs pc, lr - - -SVCHandler: /* SWI handler */ - stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ - - tst r0, #0x20 /* check the T bit */ - ldrneh r0, [lr,#-2] /* Thumb mode */ - bicne r0, r0, #0xff00 /* Thumb mode */ - ldreq r0, [lr,#-4] /* ARM mode */ - biceq r0, r0, #0xff000000 /* ARM mode */ - - bl SWInterrupt /* SWInterrupt: call C function here */ - - ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ - - subs pc, lr, #4 /* adjust return */ - - -DataAbortHandler: /* Data Abort handler */ -#ifdef CONFIG_ARM_ERRATA_775420 - dsb -#endif - stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ - - bl DataAbortInterrupt /*DataAbortInterrupt :call C function here */ - - ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ - - subs pc, lr, #4 /* adjust return */ - -PrefetchAbortHandler: /* Prefetch Abort handler */ -#ifdef CONFIG_ARM_ERRATA_775420 - dsb -#endif - stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ - - bl PrefetchAbortInterrupt /* PrefetchAbortInterrupt: call C function here */ - - ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ - - subs pc, lr, #4 /* adjust return */ - - -.end diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/asm_vectors.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/asm_vectors.o deleted file mode 100644 index a9f8dc0745cf6b29c1233f789e1ae4e0fc3b9818..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/asm_vectors.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/boot.S b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/boot.S deleted file mode 100644 index e07b421933d6f3da53c98be441f036020bb95039..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/boot.S +++ /dev/null @@ -1,448 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* @file boot.S -* -* This file contains the initial startup code for the Cortex A9 processor -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------- -------- --------------------------------------------------- -* 1.00a ecm/sdm 10/20/09 Initial version -* 3.06a sgd 05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control -* register settings. -* 3.06a asa 06/17/12 Modified the TTBR settings and L2 Cache auxiliary -* register settings. -* 3.07a asa 07/16/12 Modified the L2 Cache controller settings to improve -* performance. Changed the property of the ".boot" -* section. -* 3.07a sgd 08/21/12 Modified the L2 Cache controller and cp15 Aux Control -* Register settings -* 3.09a sgd 02/06/13 Updated SLCR l2c Ram Control register to a -* value of 0x00020202. Fix for CR 697094 (SI#687034). -* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file -* 'xil_errata.h' for errata description -* </pre> -* -* @note -* -* None. -* -******************************************************************************/ - -#include "xparameters.h" -#include "xil_errata.h" - -.globl MMUTable -.global _prestart -.global _boot -.global __stack -.global __irq_stack -.global __supervisor_stack -.global __abort_stack -.global __fiq_stack -.global __undef_stack -.global _vector_table - -.set PSS_L2CC_BASE_ADDR, 0xF8F02000 -.set PSS_SLCR_BASE_ADDR, 0xF8000000 - -.set RESERVED, 0x0fffff00 -.set TblBase , MMUTable -.set LRemap, 0xFE00000F /* set the base address of the peripheral block as not shared */ -.set L2CCWay, (PSS_L2CC_BASE_ADDR + 0x077C) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_INVLD_WAY_OFFSET)*/ -.set L2CCSync, (PSS_L2CC_BASE_ADDR + 0x0730) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_SYNC_OFFSET)*/ -.set L2CCCrtl, (PSS_L2CC_BASE_ADDR + 0x0100) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CNTRL_OFFSET)*/ -.set L2CCAuxCrtl, (PSS_L2CC_BASE_ADDR + 0x0104) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_AUX_CNTRL_OFFSET)*/ -.set L2CCTAGLatReg, (PSS_L2CC_BASE_ADDR + 0x0108) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_TAG_RAM_CNTRL_OFFSET)*/ -.set L2CCDataLatReg, (PSS_L2CC_BASE_ADDR + 0x010C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_DATA_RAM_CNTRL_OFFSET)*/ -.set L2CCIntClear, (PSS_L2CC_BASE_ADDR + 0x0220) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_IAR_OFFSET)*/ -.set L2CCIntRaw, (PSS_L2CC_BASE_ADDR + 0x021C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_ISR_OFFSET)*/ - -.set SLCRlockReg, (PSS_SLCR_BASE_ADDR + 0x04) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_LOCK_OFFSET)*/ -.set SLCRUnlockReg, (PSS_SLCR_BASE_ADDR + 0x08) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_UNLOCK_OFFSET)*/ -.set SLCRL2cRamReg, (PSS_SLCR_BASE_ADDR + 0xA1C) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_L2C_RAM_OFFSET)*/ - -/* workaround for simulation not working when L1 D and I caches,MMU and L2 cache enabled - DT568997 */ -.if SIM_MODE == 1 -.set CRValMmuCac, 0b00000000000000 /* Disable IDC, and MMU */ -.else -.set CRValMmuCac, 0b01000000000101 /* Enable IDC, and MMU */ -.endif - -.set CRValHiVectorAddr, 0b10000000000000 /* Set the Vector address to high, 0xFFFF0000 */ - -.set L2CCAuxControl, 0x72360000 /* Enable all prefetching, Cache replacement policy, Parity enable, - Event monitor bus enable and Way Size (64 KB) */ -.set L2CCControl, 0x01 /* Enable L2CC */ -.set L2CCTAGLatency, 0x0111 /* latency for TAG RAM */ -.set L2CCDataLatency, 0x0121 /* latency for DATA RAM */ - -.set SLCRlockKey, 0x767B /* SLCR lock key */ -.set SLCRUnlockKey, 0xDF0D /* SLCR unlock key */ -.set SLCRL2cRamConfig, 0x00020202 /* SLCR L2C ram configuration */ - -/* Stack Pointer locations for boot code */ -.set Undef_stack, __undef_stack -.set FIQ_stack, __fiq_stack -.set Abort_stack, __abort_stack -.set SPV_stack, __supervisor_stack -.set IRQ_stack, __irq_stack -.set SYS_stack, __stack - -.set vector_base, _vector_table - -.set FPEXC_EN, 0x40000000 /* FPU enable bit, (1 << 30) */ - -.section .boot,"ax" - - -/* this initializes the various processor modes */ - -_prestart: -_boot: - -#if XPAR_CPU_ID==0 -/* only allow cpu0 through */ - mrc p15,0,r1,c0,c0,5 - and r1, r1, #0xf - cmp r1, #0 - beq OKToRun -EndlessLoop0: - wfe - b EndlessLoop0 - -#elif XPAR_CPU_ID==1 -/* only allow cpu1 through */ - mrc p15,0,r1,c0,c0,5 - and r1, r1, #0xf - cmp r1, #1 - beq OKToRun -EndlessLoop1: - wfe - b EndlessLoop1 -#endif - -OKToRun: - mrc p15, 0, r0, c0, c0, 0 /* Get the revision */ - and r5, r0, #0x00f00000 - and r6, r0, #0x0000000f - orr r6, r6, r5, lsr #20-4 - -#ifdef CONFIG_ARM_ERRATA_742230 - cmp r6, #0x22 /* only present up to r2p2 */ - mrcle p15, 0, r10, c15, c0, 1 /* read diagnostic register */ - orrle r10, r10, #1 << 4 /* set bit #4 */ - mcrle p15, 0, r10, c15, c0, 1 /* write diagnostic register */ -#endif - -#ifdef CONFIG_ARM_ERRATA_743622 - teq r5, #0x00200000 /* only present in r2p* */ - mrceq p15, 0, r10, c15, c0, 1 /* read diagnostic register */ - orreq r10, r10, #1 << 6 /* set bit #6 */ - mcreq p15, 0, r10, c15, c0, 1 /* write diagnostic register */ -#endif - - /* set VBAR to the _vector_table address in linker script */ - ldr r0, =vector_base - mcr p15, 0, r0, c12, c0, 0 - - /*set scu enable bit in scu*/ - ldr r7, =0xf8f00000 - ldr r0, [r7] - orr r0, r0, #0x1 - str r0, [r7] - - /*invalidate scu*/ - ldr r7, =0xf8f0000c - ldr r6, =0xffff - str r6, [r7] - - /* Write to ACTLR */ - mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/ - orr r0, r0, #(0x01 << 6) /* set SMP bit */ - orr r0, r0, #(0x01 ) /* */ - mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/ - -/* Invalidate caches and TLBs */ - mov r0,#0 /* r0 = 0 */ - mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */ - mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */ - mcr p15, 0, r0, c7, c5, 6 /* Invalidate branch predictor array */ - bl invalidate_dcache /* invalidate dcache */ - -/* Invalidate L2c Cache */ -/* For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux) */ -#if USE_AMP!=1 - ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */ - mov r1, #0 /* force the disable bit */ - str r1, [r0] /* disable the L2 Caches */ - - ldr r0,=L2CCAuxCrtl /* Load L2CC base address base + Aux control register */ - ldr r1,[r0] /* read the register */ - ldr r2,=L2CCAuxControl /* set the default bits */ - orr r1,r1,r2 - str r1, [r0] /* store the Aux Control Register */ - - ldr r0,=L2CCTAGLatReg /* Load L2CC base address base + TAG Latency address */ - ldr r1,=L2CCTAGLatency /* set the latencies for the TAG*/ - str r1, [r0] /* store the TAG Latency register Register */ - - ldr r0,=L2CCDataLatReg /* Load L2CC base address base + Data Latency address */ - ldr r1,=L2CCDataLatency /* set the latencies for the Data*/ - str r1, [r0] /* store the Data Latency register Register */ - - ldr r0,=L2CCWay /* Load L2CC base address base + way register*/ - ldr r2, =0xFFFF - str r2, [r0] /* force invalidate */ - - ldr r0,=L2CCSync /* need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET */ - /* Load L2CC base address base + sync register*/ - /* poll for completion */ -Sync: ldr r1, [r0] - cmp r1, #0 - bne Sync - - ldr r0,=L2CCIntRaw /* clear pending interrupts */ - ldr r1,[r0] - ldr r0,=L2CCIntClear - str r1,[r0] -#endif - - /* Disable MMU, if enabled */ - mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 */ - bic r0, r0, #0x1 /* clear bit 0 */ - mcr p15, 0, r0, c1, c0, 0 /* write value back */ - -#ifdef SHAREABLE_DDR - /* Mark the entire DDR memory as shareable */ - ldr r3, =0x3ff /* 1024 entries to cover 1G DDR */ - ldr r0, =TblBase /* MMU Table address in memory */ - ldr r2, =0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */ -shareable_loop: - str r2, [r0] /* write the entry to MMU table */ - add r0, r0, #0x4 /* next entry in the table */ - add r2, r2, #0x100000 /* next section */ - subs r3, r3, #1 - bge shareable_loop /* loop till 1G is covered */ -#endif - - /* In case of AMP, map virtual address 0x20000000 to 0x00000000 and mark it as non-cacheable */ -#if USE_AMP==1 - ldr r3, =0x1ff /* 512 entries to cover 512MB DDR */ - ldr r0, =TblBase /* MMU Table address in memory */ - add r0, r0, #0x800 /* Address of entry in MMU table, for 0x20000000 */ - ldr r2, =0x0c02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */ -mmu_loop: - str r2, [r0] /* write the entry to MMU table */ - add r0, r0, #0x4 /* next entry in the table */ - add r2, r2, #0x100000 /* next section */ - subs r3, r3, #1 - bge mmu_loop /* loop till 512MB is covered */ -#endif - - mrs r0, cpsr /* get the current PSR */ - mvn r1, #0x1f /* set up the irq stack pointer */ - and r2, r1, r0 - orr r2, r2, #0x12 /* IRQ mode */ - msr cpsr, r2 - ldr r13,=IRQ_stack /* IRQ stack pointer */ - - mrs r0, cpsr /* get the current PSR */ - mvn r1, #0x1f /* set up the supervisor stack pointer */ - and r2, r1, r0 - orr r2, r2, #0x13 /* supervisor mode */ - msr cpsr, r2 - ldr r13,=SPV_stack /* Supervisor stack pointer */ - - mrs r0, cpsr /* get the current PSR */ - mvn r1, #0x1f /* set up the Abort stack pointer */ - and r2, r1, r0 - orr r2, r2, #0x17 /* Abort mode */ - msr cpsr, r2 - ldr r13,=Abort_stack /* Abort stack pointer */ - - mrs r0, cpsr /* get the current PSR */ - mvn r1, #0x1f /* set up the FIQ stack pointer */ - and r2, r1, r0 - orr r2, r2, #0x11 /* FIQ mode */ - msr cpsr, r2 - ldr r13,=FIQ_stack /* FIQ stack pointer */ - - mrs r0, cpsr /* get the current PSR */ - mvn r1, #0x1f /* set up the Undefine stack pointer */ - and r2, r1, r0 - orr r2, r2, #0x1b /* Undefine mode */ - msr cpsr, r2 - ldr r13,=Undef_stack /* Undefine stack pointer */ - - mrs r0, cpsr /* get the current PSR */ - mvn r1, #0x1f /* set up the system stack pointer */ - and r2, r1, r0 - orr r2, r2, #0x1F /* SYS mode */ - msr cpsr, r2 - ldr r13,=SYS_stack /* SYS stack pointer */ - - /* enable MMU and cache */ - - ldr r0,=TblBase /* Load MMU translation table base */ - orr r0, r0, #0x5B /* Outer-cacheable, WB */ - mcr 15, 0, r0, c2, c0, 0 /* TTB0 */ - - - mvn r0,#0 /* Load MMU domains -- all ones=manager */ - mcr p15,0,r0,c3,c0,0 - - /* Enable mmu, icahce and dcache */ - ldr r0,=CRValMmuCac - - mcr p15,0,r0,c1,c0,0 /* Enable cache and MMU */ - dsb /* dsb allow the MMU to start up */ - - isb /* isb flush prefetch buffer */ - -/* For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux) */ -#if USE_AMP!=1 - ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */ - ldr r1,=SLCRUnlockKey /* set unlock key */ - str r1, [r0] /* Unlock SLCR */ - - ldr r0,=SLCRL2cRamReg /* Load SLCR base address base + l2c Ram Control register */ - ldr r1,=SLCRL2cRamConfig /* set the configuration value */ - str r1, [r0] /* store the L2c Ram Control Register */ - - ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */ - ldr r1,=SLCRlockKey /* set lock key */ - str r1, [r0] /* lock SLCR */ - - ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */ - ldr r1,[r0] /* read the register */ - mov r2, #L2CCControl /* set the enable bit */ - orr r1,r1,r2 - str r1, [r0] /* enable the L2 Caches */ -#endif - - mov r0, r0 - mrc p15, 0, r1, c1, c0, 2 /* read cp access control register (CACR) into r1 */ - orr r1, r1, #(0xf << 20) /* enable full access for p10 & p11 */ - mcr p15, 0, r1, c1, c0, 2 /* write back into CACR */ - - /* enable vfp */ - fmrx r1, FPEXC /* read the exception register */ - orr r1,r1, #FPEXC_EN /* set VFP enable bit, leave the others in orig state */ - fmxr FPEXC, r1 /* write back the exception register */ - - mrc p15,0,r0,c1,c0,0 /* flow prediction enable */ - orr r0, r0, #(0x01 << 11) /* #0x8000 */ - mcr p15,0,r0,c1,c0,0 - - mrc p15,0,r0,c1,c0,1 /* read Auxiliary Control Register */ - orr r0, r0, #(0x1 << 2) /* enable Dside prefetch */ - orr r0, r0, #(0x1 << 1) /* enable L2 Prefetch hint */ - mcr p15,0,r0,c1,c0,1 /* write Auxiliary Control Register */ - - b _start /* jump to C startup code */ - and r0, r0, r0 /* no op */ - -.Ldone: b .Ldone /* Paranoia: we should never get here */ - - -/* - ************************************************************************* - * - * invalidate_dcache - invalidate the entire d-cache by set/way - * - * Note: for Cortex-A9, there is no cp instruction for invalidating - * the whole D-cache. Need to invalidate each line. - * - ************************************************************************* - */ -invalidate_dcache: - mrc p15, 1, r0, c0, c0, 1 /* read CLIDR */ - ands r3, r0, #0x7000000 - mov r3, r3, lsr #23 /* cache level value (naturally aligned) */ - beq finished - mov r10, #0 /* start with level 0 */ -loop1: - add r2, r10, r10, lsr #1 /* work out 3xcachelevel */ - mov r1, r0, lsr r2 /* bottom 3 bits are the Cache type for this level */ - and r1, r1, #7 /* get those 3 bits alone */ - cmp r1, #2 - blt skip /* no cache or only instruction cache at this level */ - mcr p15, 2, r10, c0, c0, 0 /* write the Cache Size selection register */ - isb /* isb to sync the change to the CacheSizeID reg */ - mrc p15, 1, r1, c0, c0, 0 /* reads current Cache Size ID register */ - and r2, r1, #7 /* extract the line length field */ - add r2, r2, #4 /* add 4 for the line length offset (log2 16 bytes) */ - ldr r4, =0x3ff - ands r4, r4, r1, lsr #3 /* r4 is the max number on the way size (right aligned) */ - clz r5, r4 /* r5 is the bit position of the way size increment */ - ldr r7, =0x7fff - ands r7, r7, r1, lsr #13 /* r7 is the max number of the index size (right aligned) */ -loop2: - mov r9, r4 /* r9 working copy of the max way size (right aligned) */ -loop3: - orr r11, r10, r9, lsl r5 /* factor in the way number and cache number into r11 */ - orr r11, r11, r7, lsl r2 /* factor in the index number */ - mcr p15, 0, r11, c7, c6, 2 /* invalidate by set/way */ - subs r9, r9, #1 /* decrement the way number */ - bge loop3 - subs r7, r7, #1 /* decrement the index */ - bge loop2 -skip: - add r10, r10, #2 /* increment the cache number */ - cmp r3, r10 - bgt loop1 - -finished: - mov r10, #0 /* swith back to cache level 0 */ - mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */ - dsb - isb - - bx lr - -.end - - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/boot.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/boot.o deleted file mode 100644 index 5fcf3b4d6a6fe82a9b7a89268d3277cb3acefda6..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/boot.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/bspconfig.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/bspconfig.h deleted file mode 100644 index a7fdebbc69da581bcb2a49e2875b35e0c66d64f3..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/bspconfig.h +++ /dev/null @@ -1,15 +0,0 @@ - -/******************************************************************* -* -* CAUTION: This file is automatically generated by libgen. -* Version: Xilinx EDK 14.7 EDK_P.20131013 -* DO NOT EDIT. -* -* Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. - -* -* Description: Configurations for Standalone BSP -* -*******************************************************************/ - -#define MICROBLAZE_PVR_NONE diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/changelog.txt b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/changelog.txt deleted file mode 100644 index eb111f868a479f1500d688dcc1724bc6a776bc7c..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/changelog.txt +++ /dev/null @@ -1,147 +0,0 @@ -/***************************************************************************** - * MODIFICATION HISTORY: - * - * Ver Who Date Changes - * ----- ---- -------- --------------------------------------------------- - * 3.02a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros - * 3.02a sdm 06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs - * 3.02a sdm 07/07/11 Updated ppc440 boot.S to set guarded bit for all but - * cacheable regions - * Update ppc440/xil_cache.c to use CACHEABLE_REGION_MASK - * generated by the cpu driver, for enabling caches - * 3.02a sdm 07/08/11 Updated microblaze cache flush APIs based on write-back/ - * write-thru caches - * 3.03a sdm 08/20/11 Updated the tag/data RAM latency values for L2CC - * Updated the MMU table to mark OCM in high address space - * as inner cacheable and reserved space as Invalid - * 3.03a sdm 08/20/11 Changes to support FreeRTOS - * Updated the MMU table to mark upper half of the DDR as - * non-cacheable - * Setup supervisor and abort mode stacks - * Do not initialize/enable L2CC in case of AMP - * Initialize UART1 for 9600bps in case of AMP - * 3.03a sdm 08/27/11 Setup abort and supervisor mode stacks and don't init SMC - * in case of AMP - * 3.03a sdm 09/14/11 Added code for performance monitor and L2CC event - * counters - * 3.03a sdm 11/08/11 Updated microblaze xil_cache.h file to include - * xparameters.h file for CR630532 - Xil_DCacheFlush()/ - * Xil_DCacheFlushRange() functions in standalone BSP v3_02a - * for MicroBlaze will invalidate data in the cache instead - * of flushing it for writeback caches - * 3.04a sdm 11/21/11 Updated to initialize stdio device for 115200bps, for PS7 - * 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values - * Remove redundant dsb/dmb instructions in cache maintenance - * APIs - * Remove redundant dsb in mcr instruction - * 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable - * 3.05a sdm 02/02/12 Removed some of the defines as they are being generated through - * driver tcl in xparameters.h. Update the gcc/translationtable.s - * for the QSPI complete address range - DT644567 - * Removed profile directory for armcc compiler and changed - * profiling setting to false in standalone_v2_1_0.tcl file - * Deleting boot.S file after preprocessing for armcc compiler - * 3.05a asa 03/11/12 Updated the function Xil_EnableMMU in file xil_mmu.c to - * invalidate the caches before enabling back the MMU and - * D cache. - * 3.05a asa 04/15/12 Updated the function Xil_SetTlbAttributes in file - * xil_mmu.c. Now we invalidate UTLB, Branch predictor - * array, flush the D-cache before changing the attributes - * in translation table. The user need not call Xil_DisableMMU - * before calling Xil_SetTlbAttributes. - * 3.06a asa/ 06/17/12 Removed the UART initialization for Zynq. For PEEP, the UART - * sgd initialization is present. Changes for this were done in - * uart.c and xil-crt0.s. - * Made changes in xil_io.c to use volatile pointers. - * Made changes in xil_mmu.c to correct the function - * Xil_SetTlbAttributes. - * Changes are made xil-crt0.s to initialize the static - * C++ constructors. - * Changes are made in boot.s, to fix the TTBR settings, - * correct the L2 Cache Auxiliary register settings, L2 cache - * latency settings. - * 3.07a asa/ 07/16/12 Made changes in cortexa9/xtime_l.c, xtime_l.h, sleep.c - * sgd usleep.c to use global timer intstead of CP15. - * Made changes in cortexa9/gcc/translation_table.s to map - * the peripheral devices as shareable device memory. - * Made changes in cortexa9/gcc/xil-crt0.s to initialize - * the global timer. - * Made changes in cortexa9/armcc/boot.S to initialize - * the global timer. - * Made changes in cortexa9/armcc/translation_table.s to - * map the peripheral devices as shareable device memory. - * Made changes in cortexa9/gcc/boot.S to optimize the - * L2 cache settings. Changes the section properties for - * ".mmu_tbl" and ".boot" sections in cortexa9/gcc/boot.S - * and cortexa9/gcc/translation_table.S. - * Made changes in cortexa9/xil_cache.c to change the - * cache invalidation order. - * 3.07a asa 08/17/12 Made changes across files for Cortexa9 to remove - * compilation/linking issues for C++ compiler. - * Made changes in mb_interface.h to remove compilation/ - * linking issues for C++ compiler. - * Added macros for swapb and swaph microblaze instructions - * mb_interface.h - * Remove barrier usage (SYNCHRONIZE_IO) from xil_io.c - * for CortexA9. - * 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address - * 3.07a asa 08/31/12 Added xil_printf.h include - * 3.07a sgd 09/18/12 Corrected the L2 cache enable settings - * Corrected L2 cache sequence disable sequence - * 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with compiler option - * 3.09a asa 01/25/13 Updated to push and pop neon registers into stack for - * irq/fiq handling. - * Relocated COUNTS_PER_SECOND from sleep.c to xtime_l.h. This - * fixes the CR #692094. - * 3.09a sgd 02/14/13 Fix for CRs 697094 (SI#687034) and 675552. - * 3.10a srt 04/18/13 Implemented ARM Erratas. - * Cortex A9 Errata - 742230, 743622, 775420, 794073 - * L2Cache PL310 Errata - 588369, 727915, 759370 - * Please refer to file 'xil_errata.h' for errata - * description. - * 3.10a asa 05/04/13 Added support for L2 cache in MicroBlaze BSP. The older - * cache APIs were corresponding to only Layer 1 cache - * memories. New APIs were now added and the existing cache - * related APIs were changed to provide a uniform interface - * to flush/invalidate/enable/disable the complete cache - * system which includes both L1 and L2 caches. The changes - * for these were done in: - * src/microblaze/xil_cache.c and src/microblaze/xil_cache.h - * files. - * Four new files were added for supporting L2 cache. They are: - * microblaze_flush_cache_ext.S-> Flushes L2 cache - * microblaze_flush_cache_ext_range.S -> Flushes a range of - * memory in L2 cache. - * microblaze_invalidate_cache_ext.S-> Invalidates L2 cache - * microblaze_invalidate_cache_ext_range -> Invalidates a - * range of memory in L2 cache. - * These changes are done to implement PR #697214. - * 3.10a asa 05/13/13 Modified cache disable APIs at src/cortexa9/xil_cache.c to - * fix the CR #706464. L2 cache disabling happens independent - * of L1 data cache disable operation. Changes are done in the - * same file in cache handling APIs to do a L2 cache sync - * (poll reg7_?cache_?sync). This fixes CR #700542. - * 3.10a asa 05/20/13 Added API/Macros for enabling and disabling nested - * interrupts for ARM. These are done to fix the CR#699680. - * 3.10a srt 05/20/13 Made changes in cache maintenance APIs to do a proper cach - * sync operation. This fixes the CR# 716781. - * 3.11a asa 09/07/13 Added support for iccarm toolchain. A new folder "iccarm" - * is added that contains iccarm (iar arm compiler) specific - * BSP initialization code. Changes are done in other source - * files with inline assembly code to add support for armcc. - * Modified BSP tcl to add support for iccarm. - * Updated armcc specific BSP files to have proper support - * for armcc toolchain. - * Modified asm_vectors.S (gcc) and asm_vectors.s (armcc) to - * fix issues related to NEON context saving. The assembly - * routines for IRQ and FIQ handling are modified. - * Deprecated the older BSP (3.10a). - * 3.11a asa 09/22/13 Fix for CR#732704. Cache APIs are modified to avoid - * various potential issues. Made changes in the function - * Xil_SetAttributes in file xil_mmu.c. - * 3.11a asa 09/23/13 Added files xil_misc_psreset_api.c and xil_misc_psreset_api.h - * in src\cortexa9 and src\microblaze folders. - * 3.11a asa 09/28/13 Modified the cache APIs (src\cortexa9) to fix handling of - * L2 cache sync operation and to fix issues around complete - * L2 cache flush/invalidation by ways. - ********************************************************************************/ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/close.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/close.c deleted file mode 100644 index 173b55dc288231b7f929b80912f0632890cebe98..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/close.c +++ /dev/null @@ -1,55 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -#ifdef __cplusplus -extern "C" { - int _close(int fd); -} -#endif - -/* - * close -- We don't need to do anything, but pretend we did. - */ - -int _close(int fd) -{ - (void)fd; - return (0); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/close.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/close.o deleted file mode 100644 index 303d4af8510d5c8aa9d39d936759bc33f6f74052..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/close.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/config.make b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/config.make deleted file mode 100644 index 618f1f343f91bcfa17046fa53f5833ffcaa8a549..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/config.make +++ /dev/null @@ -1,3 +0,0 @@ -LIBSOURCES = *.c *.s *.S -PROFILE_ARCH_OBJS = profile_mcount_arm.o -LIBS = standalone_libs diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/cpu_init.S b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/cpu_init.S deleted file mode 100644 index a4b1a6564600ebcb8b64b86222855b0dad26eeff..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/cpu_init.S +++ /dev/null @@ -1,88 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* @file cpu_init.s -* -* This file contains CPU specific initialization. Invoked from main CRT -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------- -------- --------------------------------------------------- -* 1.00a ecm/sdm 10/20/09 Initial version -* 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values -* </pre> -* -* @note -* -* None. -* -******************************************************************************/ - - .text - .global __cpu_init - .align 2 -__cpu_init: - -/* Clear cp15 regs with unknown reset values */ - mov r0, #0x0 - mcr p15, 0, r0, c5, c0, 0 /* DFSR */ - mcr p15, 0, r0, c5, c0, 1 /* IFSR */ - mcr p15, 0, r0, c6, c0, 0 /* DFAR */ - mcr p15, 0, r0, c6, c0, 2 /* IFAR */ - mcr p15, 0, r0, c9, c13, 2 /* PMXEVCNTR */ - mcr p15, 0, r0, c13, c0, 2 /* TPIDRURW */ - mcr p15, 0, r0, c13, c0, 3 /* TPIDRURO */ - mcr p15, 5, r0, c15, c5, 2 /* Write Lockdown TLB VA */ - -/* Reset and start Cycle Counter */ - mov r2, #0x80000000 /* clear overflow */ - mcr p15, 0, r2, c9, c12, 3 - mov r2, #0xd /* D, C, E */ - mcr p15, 0, r2, c9, c12, 0 - mov r2, #0x80000000 /* enable cycle counter */ - mcr p15, 0, r2, c9, c12, 1 - - bx lr - -.end diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/cpu_init.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/cpu_init.o deleted file mode 100644 index 7b4caeed76943d1db11fa7316e113148fefda845..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/cpu_init.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/errno.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/errno.c deleted file mode 100644 index 78a61a3457fb6e67c417d12548c2306a29b4c4d7..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/errno.c +++ /dev/null @@ -1,59 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ - -/* The errno variable is stored in the reentrancy structure. This - function returns its address for use by the macro errno defined in - errno.h. */ - -#include <errno.h> -#include <reent.h> - -#ifdef __cplusplus -extern "C" { - int * __errno (); -} -#endif - -int * -__errno () -{ - return &_REENT->_errno; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/errno.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/errno.o deleted file mode 100644 index 2afee2e1fbaddd8da04c2dc80cf1d0bfd7acd4c2..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/errno.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/fcntl.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/fcntl.c deleted file mode 100644 index be641813a3634c04cf9aa547f739fa532f0b2461..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/fcntl.c +++ /dev/null @@ -1,54 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ - -#include <stdio.h> - -/* - * fcntl -- Manipulate a file descriptor. - * We don't have a filesystem, so we do nothing. - */ -int fcntl (int fd, int cmd, long arg) -{ - (void)fd; - (void)cmd; - (void)arg; - return 0; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/fcntl.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/fcntl.o deleted file mode 100644 index 4aacb01056d42ea2d3ca8735cd90479f8d083b34..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/fcntl.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/fstat.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/fstat.c deleted file mode 100644 index 2f647c70ad1d56e80964b37cefcc51fb8a03110a..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/fstat.c +++ /dev/null @@ -1,58 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ - -#include <sys/stat.h> - -#ifdef __cplusplus -extern "C" { - int _fstat(int fd, struct stat *buf); -} -#endif -/* - * fstat -- Since we have no file system, we just return an error. - */ -int _fstat(int fd, struct stat *buf) -{ - (void)fd; - buf->st_mode = S_IFCHR; /* Always pretend to be a tty */ - - return (0); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/fstat.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/fstat.o deleted file mode 100644 index de5fffaf9468035fc91efa1cf3519eb6ae17a15e..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/fstat.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/getpid.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/getpid.c deleted file mode 100644 index 6f5fb55deec2df26a4966463665f4eab0cb53f53..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/getpid.c +++ /dev/null @@ -1,59 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ - -/* - * getpid -- only one process, so just return 1. - */ -#ifdef __cplusplus -extern "C" { - int _getpid(); -} -#endif - -int getpid() -{ - return 1; -} - -int _getpid() -{ - return 1; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/getpid.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/getpid.o deleted file mode 100644 index 6ad81a314940580bc9af870b1a7f463f252fa487..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/getpid.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/inbyte.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/inbyte.c deleted file mode 100644 index 0036459e40288e21e8d2017d9d8aee0e43a40a76..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/inbyte.c +++ /dev/null @@ -1,14 +0,0 @@ -#include "xparameters.h" -#include "xuartps_hw.h" - -#ifdef __cplusplus -extern "C" { -#endif -char inbyte(void); -#ifdef __cplusplus -} -#endif - -char inbyte(void) { - return XUartPs_RecvByte(STDIN_BASEADDRESS); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/inbyte.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/inbyte.o deleted file mode 100644 index a24f1f220d87041c55f7ca509c9990e4a95c54f8..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/inbyte.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/isatty.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/isatty.c deleted file mode 100644 index a42edfa3ba695755d859860c1e4f8f13d929c16e..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/isatty.c +++ /dev/null @@ -1,64 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -#include <unistd.h> - -#ifdef __cplusplus -extern "C" { - int _isatty(int fd); -} -#endif - -/* - * isatty -- returns 1 if connected to a terminal device, - * returns 0 if not. Since we're hooked up to a - * serial port, we'll say yes _AND return a 1. - */ -int isatty(int fd) -{ - (void)fd; - return (1); -} - -int _isatty(int fd) -{ - (void)fd; - return (1); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/isatty.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/isatty.o deleted file mode 100644 index df0fdb5f8ee9dfc67ae10f080a03d6f19ba76c57..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/isatty.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/kill.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/kill.c deleted file mode 100644 index 6b7df0c89cab55281d8b7ca8cad2b8381f4911f8..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/kill.c +++ /dev/null @@ -1,67 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -#include <signal.h> -#include <unistd.h> - -#ifdef __cplusplus -extern "C" { - int _kill(int pid, int sig); -} -#endif - -/* - * kill -- go out via exit... - */ - -int kill(int pid, int sig) -{ - if(pid == 1) - _exit(sig); - return 0; -} - -int _kill(int pid, int sig) -{ - if(pid == 1) - _exit(sig); - return 0; -} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/kill.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/kill.o deleted file mode 100644 index 51ceda7815fb015be5cea53eaa7bca8936fc3a3b..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/kill.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/lseek.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/lseek.c deleted file mode 100644 index 45e7ec3f920db32d7da0b39d0447692bdce888c3..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/lseek.c +++ /dev/null @@ -1,69 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ - -#include <sys/types.h> -#include <errno.h> - -#ifdef __cplusplus -extern "C" { - off_t _lseek(int fd, off_t offset, int whence); -} -#endif -/* - * lseek -- Since a serial port is non-seekable, we return an error. - */ -off_t lseek(int fd, off_t offset, int whence) -{ - (void)fd; - (void)offset; - (void)whence; - errno = ESPIPE; - return ((off_t)-1); -} - -off_t _lseek(int fd, off_t offset, int whence) -{ - (void)fd; - (void)offset; - (void)whence; - errno = ESPIPE; - return ((off_t)-1); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/lseek.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/lseek.o deleted file mode 100644 index 920c4101b64a060c986965f79fb023b056013371..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/lseek.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/open.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/open.c deleted file mode 100644 index 0a5b553a67fab51bc2f3941a74670197c3a618b5..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/open.c +++ /dev/null @@ -1,61 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ - -#include <errno.h> - -#ifdef __cplusplus -extern "C" { - int open(const char *buf, int flags, int mode); -} -#endif -/* - * open -- open a file descriptor. We don't have a filesystem, so - * we return an error. - */ -int open(const char *buf, int flags, int mode) -{ - (void)buf; - (void)flags; - (void)mode; - errno = EIO; - return (-1); -} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/open.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/open.o deleted file mode 100644 index cf51b82737c4e37286cb8c47bc3e77ec3ba1cbf6..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/open.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/outbyte.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/outbyte.c deleted file mode 100644 index 8b56036b7677518b290df22d590cdad568fbdad4..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/outbyte.c +++ /dev/null @@ -1,15 +0,0 @@ -#include "xparameters.h" -#include "xuartps_hw.h" - -#ifdef __cplusplus -extern "C" { -#endif -void outbyte(char c); - -#ifdef __cplusplus -} -#endif - -void outbyte(char c) { - XUartPs_SendByte(STDOUT_BASEADDRESS, c); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/outbyte.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/outbyte.o deleted file mode 100644 index dc3563daa10ff8fd3797914f22051c7bb6ebcf90..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/outbyte.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/print.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/print.c deleted file mode 100644 index be29280ca16e8d7105651b9f58fa39dab2669897..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/print.c +++ /dev/null @@ -1,31 +0,0 @@ -/* print.c -- print a string on the output device. - * - * Copyright (c) 1995 Cygnus Support - * - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. - * - */ - -/* - * print -- do a raw print of a string - */ -#include "xil_printf.h" - -void print(const char *ptr) -{ -#ifdef STDOUT_BASEADDRESS - while (*ptr) { - outbyte (*ptr++); - } -#else -(void)ptr; -#endif -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/print.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/print.o deleted file mode 100644 index 989d08e635ccd700d639f57870f206673087e182..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/print.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/Makefile b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/Makefile deleted file mode 100644 index 9a33fda027614ac6ce27e471c5e7065c5ea69ce9..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/Makefile +++ /dev/null @@ -1,65 +0,0 @@ -####################################################################### -# -# Copyright (c) 2002 Xilinx, Inc. All rights reserved. -# Xilinx, Inc. -# -# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR -# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION -# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE -# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO -# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY -# AND FITNESS FOR A PARTICULAR PURPOSE. -# -# $Id: Makefile,v 1.1.2.1 2011/05/17 04:37:55 sadanan Exp $ -# -# Makefile for profiler -# -####################################################################### - -# PROFILE_ARCH_OBJS - Processor Architecture Dependent files defined here -include ../config.make - -AS=mb-as -COMPILER = mb-gcc -ARCHIVER = mb-ar -CP = cp -COMPILER_FLAGS=-O2 -EXTRA_COMPILER_FLAGS= -LIB = libxil.a -DUMMYLIB = libxilprofile.a - -CC_FLAGS = $(subst -pg, , $(COMPILER_FLAGS)) -ECC_FLAGS = $(subst -pg, , $(EXTRA_COMPILER_FLAGS)) - -RELEASEDIR = ../../../../lib -INCLUDEDIR = ../../../../include -INCLUDES = -I./. -I${INCLUDEDIR} - -OBJS = _profile_init.o _profile_clean.o _profile_timer_hw.o profile_hist.o profile_cg.o -DUMMYOBJ = dummy.o -INCLUDEFILES = profile.h mblaze_nt_types.h _profile_timer_hw.h - -libs : reallibs dummylibs - -reallibs : $(OBJS) $(PROFILE_ARCH_OBJS) - $(ARCHIVER) -r $(RELEASEDIR)/$(LIB) $(OBJS) $(PROFILE_ARCH_OBJS) - -dummylibs : $(DUMMYOBJ) - $(ARCHIVER) -r $(RELEASEDIR)/$(DUMMYLIB) $(DUMMYOBJ) - -%.o:%.c - $(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES) - -%.o:%.S - $(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES) - -include: - $(CP) -rf $(INCLUDEFILES) $(INCLUDEDIR) - -clean: - rm -f $(OBJS) $(PROFILE_ARCH_OBJS) $(LIB) diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/_profile_clean.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/_profile_clean.c deleted file mode 100644 index b4e3e33475deccd6575029a8d1b826a5366a1554..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/_profile_clean.c +++ /dev/null @@ -1,33 +0,0 @@ -// -// Copyright (c) 2002 Xilinx, Inc. All rights reserved. -// Xilinx, Inc. -// -// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR -// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION -// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE -// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO -// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY -// AND FITNESS FOR A PARTICULAR PURPOSE. -// -// $Id: _profile_clean.c,v 1.1.2.1 2011/05/17 04:37:55 sadanan Exp $ -// - -#include "profile.h" -#include "_profile_timer_hw.h" -#include "xil_exception.h" - -/* - * This function is the exit routine and is called by the crtinit, when the - * program terminates. The name needs to be changed later.. - */ -void _profile_clean( void ) -{ - Xil_ExceptionDisable(); - disable_timer(); -} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/_profile_init.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/_profile_init.c deleted file mode 100644 index e3a8a0143a9df79d08c56bda12b24dffd734012a..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/_profile_init.c +++ /dev/null @@ -1,80 +0,0 @@ -////////////////////////////////////////////////////////////////////// -// -// Copyright (c) 2002-2011 Xilinx, Inc. All rights reserved. -// Xilinx, Inc. -// -// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR -// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION -// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE -// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO -// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY -// AND FITNESS FOR A PARTICULAR PURPOSE. -// -// $Id: _profile_init.c,v 1.1.2.1 2011/05/17 04:37:56 sadanan Exp $ -// -// _program_init.c: -// Initialize the Profiling Structures. -// -////////////////////////////////////////////////////////////////////// - -#include "profile.h" - -// XMD Initializes the following Global Variables Value during Program -// Download with appropriate values. - -#ifdef PROC_MICROBLAZE - -extern int microblaze_init(void); - -#elif defined PROC_PPC - -extern int powerpc405_init(void); - -#else - -extern int cortexa9_init(void); - -#endif - - - -int profile_version = 1; // Version of S/W Intrusive Profiling library - -int binsize = BINSIZE; // Histogram Bin Size -unsigned int cpu_clk_freq = CPU_FREQ_HZ ; // CPU Clock Frequency -unsigned int sample_freq_hz = SAMPLE_FREQ_HZ ; // Histogram Sampling Frequency -unsigned int timer_clk_ticks = TIMER_CLK_TICKS ;// Timer Clock Ticks for the Timer - -// Structure for Storing the Profiling Data -struct gmonparam *_gmonparam = (struct gmonparam *)0xffffffff; -int n_gmon_sections = 1; - -// This is the initialization code, which is called from the crtinit. -// -void _profile_init( void ) -{ -/* print("Gmon Init called....\r\n") ; */ -/* putnum(n_gmon_sections) ; print("\r\n") ; */ -/* if( _gmonparam == 0xffffffff ) */ -/* printf("Gmonparam is NULL !!\r\n"); */ -/* for( i = 0; i < n_gmon_sections; i++ ){ */ -/* putnum(_gmonparam[i].lowpc) ; print("\t") ; */ -/* putnum(_gmonparam[i].highpc) ; print("\r\n") ; */ -/* putnum( _gmonparam[i].textsize ); print("\r\n") ; */ -/* putnum( _gmonparam[i].kcountsize * sizeof(unsigned short));print("\r\n"); */ -/* } */ - -#ifdef PROC_MICROBLAZE - microblaze_init(); -#elif defined PROC_PPC - powerpc405_init(); -#else - cortexa9_init (); -#endif -} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/_profile_timer_hw.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/_profile_timer_hw.c deleted file mode 100644 index 7f95483369132afa2dca11553921445cc0443484..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/_profile_timer_hw.c +++ /dev/null @@ -1,346 +0,0 @@ -////////////////////////////////////////////////////////////////////// -// -// Copyright (c) 2004-2010 Xilinx, Inc. All rights reserved. -// Xilinx, Inc. -// -// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR -// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION -// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE -// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO -// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY -// AND FITNESS FOR A PARTICULAR PURPOSE. -// -// $Id: _profile_timer_hw.c,v 1.1.2.1 2011/05/17 04:37:56 sadanan Exp $ -// -// _program_timer_hw.c: -// Timer related functions -// -////////////////////////////////////////////////////////////////////// - -#include "profile.h" -#include "_profile_timer_hw.h" - -#include "xil_exception.h" - -#ifdef PROC_PPC -#include "xtime_l.h" -#include "xpseudo_asm.h" -#endif - -#ifdef TIMER_CONNECT_INTC -#include "xintc_l.h" -#include "xintc.h" -#endif // TIMER_CONNECT_INTC - -//#ifndef PPC_PIT_INTERRUPT -#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9) -#include "xtmrctr_l.h" -#endif - -extern unsigned int timer_clk_ticks ; - -//-------------------------------------------------------------------- -// PowerPC Target - Timer related functions -//-------------------------------------------------------------------- -#ifdef PROC_PPC405 - - -//-------------------------------------------------------------------- -// PowerPC PIT Timer Init. -// Defined only if PIT Timer is used for Profiling -// -//-------------------------------------------------------------------- -#ifdef PPC_PIT_INTERRUPT -int ppc_pit_init( void ) -{ - // 1. Register Profile_intr_handler as Interrupt handler - // 2. Set PIT Timer Interrupt and Enable it. - Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_PIT_INT, - (Xil_ExceptionHandler)profile_intr_handler,(void *)0); - XTime_PITSetInterval( timer_clk_ticks ) ; - XTime_PITEnableAutoReload() ; - return 0; -} -#endif - - -//-------------------------------------------------------------------- -// PowerPC Timer Initialization functions. -// For PowerPC, PIT and opb_timer can be used for Profiling. This -// is selected by the user in standalone BSP -// -//-------------------------------------------------------------------- -int powerpc405_init() -{ - Xil_ExceptionInit() ; - Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ; - - // Initialize the Timer. - // 1. If PowerPC PIT Timer has to be used, initialize PIT timer. - // 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC -#ifdef PPC_PIT_INTERRUPT - ppc_pit_init(); -#else -#ifdef TIMER_CONNECT_INTC - Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT, - (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0); - XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID, - (XInterruptHandler)profile_intr_handler,(void*)0); -#else - Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT, - (Xil_ExceptionHandler)profile_intr_handler,(void *)0); -#endif - // Initialize the timer with Timer Ticks - opb_timer_init() ; -#endif - - // Enable Interrupts in the System, if Profile Timer is the only Interrupt - // in the System. -#ifdef ENABLE_SYS_INTR -#ifdef PPC_PIT_INTERRUPT - XTime_PITEnableInterrupt() ; -#elif TIMER_CONNECT_INTC - XIntc_MasterEnable( INTC_BASEADDR ); - XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION); - XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK ); -#endif - Xil_ExceptionEnableMask( XIL_EXCEPTION_NON_CRITICAL ) ; -#endif - return 0; -} - -#endif // PROC_PPC - - - -//-------------------------------------------------------------------- -// PowerPC440 Target - Timer related functions -//-------------------------------------------------------------------- -#ifdef PROC_PPC440 - - -//-------------------------------------------------------------------- -// PowerPC DEC Timer Init. -// Defined only if DEC Timer is used for Profiling -// -//-------------------------------------------------------------------- -#ifdef PPC_PIT_INTERRUPT -int ppc_dec_init( void ) -{ - // 1. Register Profile_intr_handler as Interrupt handler - // 2. Set DEC Timer Interrupt and Enable it. - Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_DEC_INT, - (Xil_ExceptionHandler)profile_intr_handler,(void *)0); - XTime_DECSetInterval( timer_clk_ticks ) ; - XTime_DECEnableAutoReload() ; - return 0; -} -#endif - - -//-------------------------------------------------------------------- -// PowerPC Timer Initialization functions. -// For PowerPC, DEC and opb_timer can be used for Profiling. This -// is selected by the user in standalone BSP -// -//-------------------------------------------------------------------- -int powerpc405_init(void) -{ - Xil_ExceptionInit(); - Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ; - - // Initialize the Timer. - // 1. If PowerPC DEC Timer has to be used, initialize DEC timer. - // 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC -#ifdef PPC_PIT_INTERRUPT - ppc_dec_init(); -#else -#ifdef TIMER_CONNECT_INTC - Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_NON_CRITICAL_INT, - (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0); - - XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID, - (XInterruptHandler)profile_intr_handler,(void*)0); -#else - Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT, - (Xil_ExceptionHandler)profile_intr_handler,(void *)0); - Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT, - (Xil_ExceptionHandler)profile_intr_handler,(void *)0); -#endif - // Initialize the timer with Timer Ticks - opb_timer_init() ; -#endif - - // Enable Interrupts in the System, if Profile Timer is the only Interrupt - // in the System. -#ifdef ENABLE_SYS_INTR -#ifdef PPC_PIT_INTERRUPT - XTime_DECEnableInterrupt() ; -#elif TIMER_CONNECT_INTC - XIntc_MasterEnable( INTC_BASEADDR ); - XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION); - XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK ); -#endif - Xil_ExceptionEnableMask( XEXC_NON_CRITICAL ) ; -#endif - return 0; -} - -#endif // PROC_PPC440 - -//-------------------------------------------------------------------- -// opb_timer Initialization for PowerPC and MicroBlaze. This function -// is not needed if DEC timer is used in PowerPC -// -//-------------------------------------------------------------------- -//#ifndef PPC_PIT_INTERRUPT -#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9) -int opb_timer_init( void ) -{ - // set the number of cycles the timer counts before interrupting - XTmrCtr_SetLoadReg(PROFILE_TIMER_BASEADDR, 0, timer_clk_ticks); - - // reset the timers, and clear interrupts - XTmrCtr_SetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, - XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK ); - - // start the timers - XTmrCtr_SetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, XTC_CSR_ENABLE_TMR_MASK - | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK); - return 0; -} -#endif - - -//-------------------------------------------------------------------- -// MicroBlaze Target - Timer related functions -//-------------------------------------------------------------------- -#ifdef PROC_MICROBLAZE - -//-------------------------------------------------------------------- -// Initialize the Profile Timer for MicroBlaze Target. -// For MicroBlaze, opb_timer is used. The opb_timer can be directly -// connected to MicroBlaze or connected through Interrupt Controller. -// -//-------------------------------------------------------------------- -int microblaze_init(void) -{ - // Register profile_intr_handler - // 1. If timer is connected to Interrupt Controller, register the handler - // to Interrupt Controllers vector table. - // 2. If timer is directly connected to MicroBlaze, register the handler - // as Interrupt handler - Xil_ExceptionInit(); - -#ifdef TIMER_CONNECT_INTC - XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID, - (XInterruptHandler)profile_intr_handler,(void*)0); -#else - Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, - (Xil_ExceptionHandler)profile_intr_handler, - (void *)0) ; -#endif - - // Initialize the timer with Timer Ticks - opb_timer_init() ; - - // Enable Interrupts in the System, if Profile Timer is the only Interrupt - // in the System. -#ifdef ENABLE_SYS_INTR -#ifdef TIMER_CONNECT_INTC - XIntc_MasterEnable( INTC_BASEADDR ); - XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION); - XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK ); - Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, - (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0); -#endif - -#endif - - Xil_ExceptionEnable(); - - return 0; - -} - -#endif // PROC_MICROBLAZE - - - -//-------------------------------------------------------------------- -// Cortex A9 Target - Timer related functions -//-------------------------------------------------------------------- -#ifdef PROC_CORTEXA9 - -//-------------------------------------------------------------------- -// Initialize the Profile Timer for Cortex A9 Target. -// The scu private timer is connected to the Scu GIC controller. -// -//-------------------------------------------------------------------- -int scu_timer_init( void ) -{ - // set the number of cycles the timer counts before interrupting - // scu timer runs at half the cpu clock - XScuTimer_SetLoadReg(PROFILE_TIMER_BASEADDR, timer_clk_ticks/2); - - // clear any pending interrupts - XScuTimer_SetIntrReg(PROFILE_TIMER_BASEADDR, 1); - - // enable interrupts, auto-reload mode and start the timer - XScuTimer_SetControlReg(PROFILE_TIMER_BASEADDR, XSCUTIMER_CONTROL_IRQ_ENABLE_MASK | - XSCUTIMER_CONTROL_AUTO_RELOAD_MASK | XSCUTIMER_CONTROL_ENABLE_MASK); - - return 0; -} - -int cortexa9_init(void) -{ - - Xil_ExceptionInit(); - - XScuGic_DeviceInitialize(0); - - /* - * Connect the interrupt controller interrupt handler to the hardware - * interrupt handling logic in the processor. - */ - Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT, - (Xil_ExceptionHandler)XScuGic_DeviceInterruptHandler, - (void *)0); - - /* - * Connect the device driver handler that will be called when an - * interrupt for the device occurs, the handler defined above performs - * the specific interrupt processing for the device. - */ - XScuGic_RegisterHandler(SCUGIC_CPU_BASEADDR, - PROFILE_TIMER_INTR_ID, - (Xil_ExceptionHandler)profile_intr_handler, - (void *)0); - - /* - * Enable the interrupt for scu timer. - */ - XScuGic_EnableIntr(SCUGIC_DIST_BASEADDR, PROFILE_TIMER_INTR_ID); - - /* - * Enable interrupts in the Processor. - */ - Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ); - - /* - * Initialize the timer with Timer Ticks - */ - scu_timer_init() ; - - Xil_ExceptionEnable(); - - return 0; -} - -#endif // PROC_CORTEXA9 diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/_profile_timer_hw.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/_profile_timer_hw.h deleted file mode 100644 index 19499f7c5b33e404a6548723db1e165b8bd8db31..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/_profile_timer_hw.h +++ /dev/null @@ -1,292 +0,0 @@ -////////////////////////////////////////////////////////////////////// -// -// Copyright (c) 2004-11 Xilinx, Inc. All rights reserved. -// Xilinx, Inc. -// -// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR -// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION -// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE -// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO -// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY -// AND FITNESS FOR A PARTICULAR PURPOSE. -// -// $Id: _profile_timer_hw.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $ -// -// _program_timer_hw.h: -// Timer related functions -// -////////////////////////////////////////////////////////////////////// - -#ifndef _PROFILE_TIMER_HW_H -#define _PROFILE_TIMER_HW_H - -#include "profile.h" - -#ifdef PROC_PPC -#if defined __GNUC__ -# define SYNCHRONIZE_IO __asm__ volatile ("eieio") -#elif defined __DCC__ -# define SYNCHRONIZE_IO __asm volatile(" eieio") -#else -# define SYNCHRONIZE_IO -#endif -#endif - -#ifdef PROC_PPC -#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; -#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; } -#else -#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr)); -#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); } -#endif - -#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\ - ProfIo_Out32(((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \ - (RegOffset)), (ValueToWrite)) - -#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \ - ProfIo_In32((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + (RegOffset)) - -#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\ - ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \ - (RegisterValue)) - -#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \ - ProfTimerCtr_mReadReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET) - - - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef PROC_PPC -#include "xexception_l.h" -#include "xtime_l.h" -#include "xpseudo_asm.h" -#endif - -#ifdef TIMER_CONNECT_INTC -#include "xintc_l.h" -#include "xintc.h" -#endif // TIMER_CONNECT_INTC - -#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9) -#include "xtmrctr_l.h" -#endif - -#ifdef PROC_CORTEXA9 -#include "xscutimer_hw.h" -#include "xscugic.h" -#endif - -extern unsigned int timer_clk_ticks ; - -//-------------------------------------------------------------------- -// PowerPC Target - Timer related functions -//-------------------------------------------------------------------- -#ifdef PROC_PPC - -#ifdef PPC_PIT_INTERRUPT -unsigned long timer_lo_clk_ticks ; // Clk ticks when Timer is disabled in CG -#endif - -#ifdef PROC_PPC440 -#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE -#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS -#define XREG_SPR_PIT XREG_SPR_DEC -#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT -#endif - -//-------------------------------------------------------------------- -// Disable the Timer - During Profiling -// -// For PIT Timer - -// 1. XTime_PITDisableInterrupt() ; -// 2. Store the remaining timer clk tick -// 3. Stop the PIT Timer -//-------------------------------------------------------------------- - -#ifdef PPC_PIT_INTERRUPT -#define disable_timer() \ - { \ - unsigned long val; \ - val=mfspr(XREG_SPR_TCR); \ - mtspr(XREG_SPR_TCR, val & ~XREG_TCR_PIT_INTERRUPT_ENABLE); \ - timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \ - mtspr(XREG_SPR_PIT, 0); \ - } -#else -#define disable_timer() \ - { \ - u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \ - u32 tmp_v = ProfIo_In32(addr); \ - tmp_v = tmp_v & ~XTC_CSR_ENABLE_TMR_MASK; \ - ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \ - } -#endif - - - -//-------------------------------------------------------------------- -// Enable the Timer -// -// For PIT Timer - -// 1. Load the remaining timer clk ticks -// 2. XTime_PITEnableInterrupt() ; -//-------------------------------------------------------------------- -#ifdef PPC_PIT_INTERRUPT -#define enable_timer() \ - { \ - unsigned long val; \ - val=mfspr(XREG_SPR_TCR); \ - mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \ - mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \ - } -#else -#define enable_timer() \ - { \ - u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \ - u32 tmp_v = ProfIo_In32(addr); \ - tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \ - ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \ - } -#endif - - - -//-------------------------------------------------------------------- -// Send Ack to Timer Interrupt -// -// For PIT Timer - -// 1. Load the timer clk ticks -// 2. Enable AutoReload and Interrupt -// 3. Clear PIT Timer Status bits -//-------------------------------------------------------------------- -#ifdef PPC_PIT_INTERRUPT -#define timer_ack() \ - { \ - unsigned long val; \ - mtspr(XREG_SPR_PIT, timer_clk_ticks); \ - mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \ - val=mfspr(XREG_SPR_TCR); \ - mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \ - } -#else -#define timer_ack() \ - { \ - unsigned int csr; \ - csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \ - ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \ - } -#endif - -//-------------------------------------------------------------------- -#endif // PROC_PPC -//-------------------------------------------------------------------- - - - - -//-------------------------------------------------------------------- -// MicroBlaze Target - Timer related functions -//-------------------------------------------------------------------- -#ifdef PROC_MICROBLAZE - -//-------------------------------------------------------------------- -// Disable the Timer during Call-Graph Data collection -// -//-------------------------------------------------------------------- -#define disable_timer() \ - { \ - u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \ - u32 tmp_v = ProfIo_In32(addr); \ - tmp_v = tmp_v & ~XTC_CSR_ENABLE_TMR_MASK; \ - ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \ - } - - -//-------------------------------------------------------------------- -// Enable the Timer after Call-Graph Data collection -// -//-------------------------------------------------------------------- -#define enable_timer() \ - { \ - u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \ - u32 tmp_v = ProfIo_In32(addr); \ - tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \ - ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \ - } - - -//-------------------------------------------------------------------- -// Send Ack to Timer Interrupt -// -//-------------------------------------------------------------------- -#define timer_ack() \ - { \ - unsigned int csr; \ - csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \ - ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \ - } - -//-------------------------------------------------------------------- -#endif // PROC_MICROBLAZE -//-------------------------------------------------------------------- - -//-------------------------------------------------------------------- -// Cortex A9 Target - Timer related functions -//-------------------------------------------------------------------- -#ifdef PROC_CORTEXA9 - -//-------------------------------------------------------------------- -// Disable the Timer during Call-Graph Data collection -// -//-------------------------------------------------------------------- -#define disable_timer() \ -{ \ - u32 Reg; \ - Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \ - Reg &= ~XSCUTIMER_CONTROL_ENABLE_MASK;\ - Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\ -} \ - - -//-------------------------------------------------------------------- -// Enable the Timer after Call-Graph Data collection -// -//-------------------------------------------------------------------- -#define enable_timer() \ -{ \ - u32 Reg; \ - Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \ - Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \ - Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\ -} \ - - -//-------------------------------------------------------------------- -// Send Ack to Timer Interrupt -// -//-------------------------------------------------------------------- -#define timer_ack() \ -{ \ - Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_ISR_OFFSET, \ - XSCUTIMER_ISR_EVENT_FLAG_MASK);\ -} - -//-------------------------------------------------------------------- -#endif // PROC_CORTEXA9 -//-------------------------------------------------------------------- - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/dummy.S b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/dummy.S deleted file mode 100644 index 98c5fa86ec99336e7b3acd8e4962dbcf78145778..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/dummy.S +++ /dev/null @@ -1,50 +0,0 @@ -// -// Copyright (c) 2002 Xilinx, Inc. All rights reserved. -// Xilinx, Inc. -// -// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR -// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION -// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE -// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO -// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY -// AND FITNESS FOR A PARTICULAR PURPOSE. -// -// $Id: dummy.S,v 1.1.2.1 2011/05/17 04:37:56 sadanan Exp $ -// - .globl dummy_f - -#ifdef PROC_MICROBLAZE - .text - .align 2 - .ent dummy_f - -dummy_f: - nop - - .end dummy_f -#endif - -#ifdef PROC_PPC - .section .text - .align 2 - .type dummy_f@function - -dummy_f: - b dummy_f - -#endif - -#ifdef PROC_CORTEXA9 - .section .text - .align 2 - .type dummy_f, %function - -dummy_f: - b dummy_f - -#endif diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/mblaze_nt_types.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/mblaze_nt_types.h deleted file mode 100644 index 2cf77fe837c322816705985c52c53d8c49c97fb1..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/mblaze_nt_types.h +++ /dev/null @@ -1,51 +0,0 @@ -////////////////////////////////////////////////////////////////////// -// -// Copyright (c) 2002-11 Xilinx, Inc. All rights reserved. -// Xilinx, Inc. -// -// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR -// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION -// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE -// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO -// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY -// AND FITNESS FOR A PARTICULAR PURPOSE. -// -// $Id: mblaze_nt_types.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $ -// -////////////////////////////////////////////////////////////////////// - -#ifndef _MBLAZE_NT_TYPES_H -#define _MBLAZE_NT_TYPES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef char byte; -typedef short half; -typedef int word; -typedef unsigned char ubyte; -typedef unsigned short uhalf; -typedef unsigned int uword; -typedef ubyte boolean; - -//typedef unsigned char u_char; -//typedef unsigned short u_short; -//typedef unsigned int u_int; -//typedef unsigned long u_long; - -typedef short int16_t; -typedef unsigned short uint16_t; -typedef int int32_t; -typedef unsigned int uint32_t; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/profile.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/profile.h deleted file mode 100644 index 0657e6f9959fab9deee68f749e63ebfae6c4d336..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/profile.h +++ /dev/null @@ -1,127 +0,0 @@ -////////////////////////////////////////////////////////////////////// -// -// Copyright (c) 2002-11 Xilinx, Inc. All rights reserved. -// Xilinx, Inc. -// -// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR -// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION -// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE -// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO -// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY -// AND FITNESS FOR A PARTICULAR PURPOSE. -// -// $Id: profile.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $ -// -////////////////////////////////////////////////////////////////////// - -#ifndef _PROFILE_H -#define _PROFILE_H 1 - -#include <stdio.h> -#include "mblaze_nt_types.h" -#include "profile_config.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void _system_init( void ) ; -void _system_clean( void ) ; -void mcount(unsigned long frompc, unsigned long selfpc); -void profile_intr_handler( void ) ; - - - -/**************************************************************************** - * Profiling on hardware - Hash table maintained on hardware and data sent - * to xmd for gmon.out generation. - ****************************************************************************/ -/* - * histogram counters are unsigned shorts (according to the kernel). - */ -#define HISTCOUNTER unsigned short - -struct tostruct { - unsigned long selfpc; - long count; - short link; - unsigned short pad; -}; - -struct fromstruct { - unsigned long frompc ; - short link ; - unsigned short pad ; -} ; - -/* - * general rounding functions. - */ -#define ROUNDDOWN(x,y) (((x)/(y))*(y)) -#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y)) - -/* - * The profiling data structures are housed in this structure. - */ -struct gmonparam { - long int state; - - // Histogram Information - unsigned short *kcount; /* No. of bins in histogram */ - unsigned long kcountsize; /* Histogram samples */ - - // Call-graph Information - struct fromstruct *froms; - unsigned long fromssize; - struct tostruct *tos; - unsigned long tossize; - - // Initialization I/Ps - unsigned long lowpc; - unsigned long highpc; - unsigned long textsize; - //unsigned long cg_froms; - //unsigned long cg_tos; -}; -extern struct gmonparam *_gmonparam; -extern int n_gmon_sections; - -/* - * Possible states of profiling. - */ -#define GMON_PROF_ON 0 -#define GMON_PROF_BUSY 1 -#define GMON_PROF_ERROR 2 -#define GMON_PROF_OFF 3 - -/* - * Sysctl definitions for extracting profiling information from the kernel. - */ -#define GPROF_STATE 0 /* int: profiling enabling variable */ -#define GPROF_COUNT 1 /* struct: profile tick count buffer */ -#define GPROF_FROMS 2 /* struct: from location hash bucket */ -#define GPROF_TOS 3 /* struct: destination/count structure */ -#define GPROF_GMONPARAM 4 /* struct: profiling parameters (see above) */ - -#ifdef __cplusplus -} -#endif - -#endif /* _PROFILE_H */ - - - - - - - - - - - - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/profile_cg.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/profile_cg.c deleted file mode 100644 index 1c1e08fd6c3ae0a69c7bc9b8620b0cf0538c30af..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/profile_cg.c +++ /dev/null @@ -1,146 +0,0 @@ -// -// Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. -// Xilinx, Inc. -// -// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR -// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION -// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE -// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO -// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY -// AND FITNESS FOR A PARTICULAR PURPOSE. -// -// $Id: profile_cg.c,v 1.1.2.1 2011/05/17 04:37:57 sadanan Exp $ -// - -#include "mblaze_nt_types.h" -#include "profile.h" -#include "_profile_timer_hw.h" - -/* - * The mcount fucntion is excluded from the library, if the user defines - * PROFILE_NO_GRAPH. - */ -#ifndef PROFILE_NO_GRAPH - -#include <stdio.h> -#include <stdlib.h> -#include <string.h> - -extern struct gmonparam *_gmonparam; - -#ifdef PROFILE_NO_FUNCPTR -int searchpc( struct fromto_struct *cgtable, int cgtable_size, unsigned long frompc ) -{ - int index = 0 ; - - while( (index < cgtable_size) && (cgtable[index].frompc != frompc) ){ - index++ ; - } - if( index == cgtable_size ) - return -1 ; - else - return index ; -} -#else -int searchpc( struct fromstruct *froms, int fromssize, unsigned long frompc ) -{ - int index = 0 ; - - while( (index < fromssize) && (froms[index].frompc != frompc) ){ - index++ ; - } - if( index == fromssize ) - return -1 ; - else - return index ; -} -#endif /* PROFILE_NO_FUNCPTR */ - - -void mcount( unsigned long frompc, unsigned long selfpc ) -{ - register struct gmonparam *p = NULL; - register long toindex, fromindex; - int j; - - disable_timer(); - - //print("CG: "); putnum(frompc); print("->"); putnum(selfpc); print("\r\n"); - // check that frompcindex is a reasonable pc value. - // for example: signal catchers get called from the stack, - // not from text space. too bad. - // - for(j = 0; j < n_gmon_sections; j++ ){ - if((frompc >= _gmonparam[j].lowpc) && (frompc < _gmonparam[j].highpc)) { - p = &_gmonparam[j]; - break; - } - } - if( j == n_gmon_sections ) - goto done; - -#ifdef PROFILE_NO_FUNCPTR - fromindex = searchpc( p->cgtable, p->cgtable_size, frompc ) ; - if( fromindex == -1 ) { - fromindex = p->cgtable_size ; - p->cgtable_size++ ; - p->cgtable[fromindex].frompc = frompc ; - p->cgtable[fromindex].selfpc = selfpc ; - p->cgtable[fromindex].count = 1 ; - goto done ; - } - p->cgtable[fromindex].count++ ; -#else - fromindex = searchpc( p->froms, p->fromssize, frompc ) ; - if( fromindex == -1 ) { - fromindex = p->fromssize ; - p->fromssize++ ; - //if( fromindex >= N_FROMS ) { - //print("Error : From PC table overflow\r\n") ; - //goto overflow ; - //} - p->froms[fromindex].frompc = frompc ; - p->froms[fromindex].link = -1 ; - }else { - toindex = p->froms[fromindex].link ; - while(toindex != -1) { - toindex = (p->tossize - toindex)-1 ; - if( p->tos[toindex].selfpc == selfpc ) { - p->tos[toindex].count++ ; - goto done ; - } - toindex = p->tos[toindex].link ; - } - } - - //if( toindex == -1 ) { - p->tos-- ; - p->tossize++ ; - //if( toindex >= N_TOS ) { - //print("Error : To PC table overflow\r\n") ; - //goto overflow ; - //} - p->tos[0].selfpc = selfpc ; - p->tos[0].count = 1 ; - p->tos[0].link = p->froms[fromindex].link ; - p->froms[fromindex].link = p->tossize-1 ; -#endif - - done: - p->state = GMON_PROF_ON; - goto enable_timer ; - //overflow: - p->state = GMON_PROF_ERROR; - enable_timer: - enable_timer(); - return ; -} - - -#endif /* PROFILE_NO_GRAPH */ - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/profile_config.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/profile_config.h deleted file mode 100644 index 76ddbe80c0ebbfe85a567ee1da7a9595a773d73d..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/profile_config.h +++ /dev/null @@ -1,36 +0,0 @@ -////////////////////////////////////////////////////////////////////// -// -// Copyright (c) 2002-11 Xilinx, Inc. All rights reserved. -// Xilinx, Inc. -// -// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR -// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION -// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE -// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO -// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY -// AND FITNESS FOR A PARTICULAR PURPOSE. -// -// $Id: profile_config.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $ -// -////////////////////////////////////////////////////////////////////// - -#ifndef _PROFILE_CONFIG_H -#define _PROFILE_CONFIG_H - -#define BINSIZE 4 -#define SAMPLE_FREQ_HZ 100000 -#define TIMER_CLK_TICKS 1000 - -#define PROFILE_NO_FUNCPTR_FLAG 0 - -#define PROFILE_TIMER_BASEADDR 0x00608000 -#define PROFILE_TIMER_INTR_ID 0 - -#define TIMER_CONNECT_INTC - -#endif diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/profile_hist.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/profile_hist.c deleted file mode 100644 index a726670c0a22ed38c6892fd4144b0443b51cccc1..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/profile_hist.c +++ /dev/null @@ -1,53 +0,0 @@ -// -// Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. -// Xilinx, Inc. -// -// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR -// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION -// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE -// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO -// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY -// AND FITNESS FOR A PARTICULAR PURPOSE. -// -// $Id: profile_hist.c,v 1.1.2.1 2011/05/17 04:37:57 sadanan Exp $ -// -#include "profile.h" -#include "mblaze_nt_types.h" -#include "_profile_timer_hw.h" - -#ifdef PROC_PPC -#include "xpseudo_asm.h" -#define SPR_SRR0 0x01A -#endif - -extern int binsize ; -uint32_t prof_pc ; - -void profile_intr_handler( void ) -{ - - int j; - -#ifdef PROC_MICROBLAZE - asm( "swi r14, r0, prof_pc" ) ; -#elif defined PROC_PPC - prof_pc = mfspr(SPR_SRR0); -#else - // for cortexa9, lr is saved in asm interrupt handler -#endif - //print("PC: "); putnum(prof_pc); print("\r\n"); - for(j = 0; j < n_gmon_sections; j++ ){ - if((prof_pc >= _gmonparam[j].lowpc) && (prof_pc < _gmonparam[j].highpc)) { - _gmonparam[j].kcount[(prof_pc-_gmonparam[j].lowpc)/(4 * binsize)]++; - break; - } - } - // Ack the Timer Interrupt - timer_ack(); -} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/profile_mcount_arm.S b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/profile_mcount_arm.S deleted file mode 100644 index fef9ad8613e9e53c2d235c831f726d099cfbb7b5..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/profile_mcount_arm.S +++ /dev/null @@ -1,33 +0,0 @@ -// -// Copyright (c) 2012 Xilinx, Inc. All rights reserved. -// Xilinx, Inc. -// -// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR -// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION -// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE -// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO -// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY -// AND FITNESS FOR A PARTICULAR PURPOSE. -// -// $Id: profile_mcount_arm.S,v 1.1.2.1 2011/05/17 04:37:57 sadanan Exp $ -// - -// based on "ARM Profiling Implementation" from Sourcery G++ Lite for ARM EABI - -.globl __gnu_mcount_nc -.type __gnu_mcount_nc, %function - -__gnu_mcount_nc: - push {r0, r1, r2, r3, lr} - subs r1, lr, #0 /* callee - current lr */ - ldr r0, [sp, #20] /* caller - at the top of the stack */ - bl mcount /* when __gnu_mcount_nc is called */ - pop {r0, r1, r2, r3, ip, lr} - bx ip - - .end __gnu_mcount_nc diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/profile_mcount_mb.S b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/profile_mcount_mb.S deleted file mode 100644 index de93730759a1694dc75565f9bf2775b49f714b8c..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/profile_mcount_mb.S +++ /dev/null @@ -1,55 +0,0 @@ -// -// Copyright (c) 2002 Xilinx, Inc. All rights reserved. -// Xilinx, Inc. -// -// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR -// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION -// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE -// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO -// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY -// AND FITNESS FOR A PARTICULAR PURPOSE. -// -// $Id: profile_mcount_mb.S,v 1.1.2.1 2011/05/17 04:37:58 sadanan Exp $ -// - .globl _mcount - .text - .align 2 - .ent _mcount - - #ifndef PROFILE_NO_GRAPH - -_mcount: - addi r1, r1, -48 - swi r11, r1, 44 - swi r12, r1, 40 - swi r5, r1, 36 - swi r6, r1, 32 - swi r7, r1, 28 - swi r8, r1, 24 - swi r9, r1, 20 - swi r10, r1, 16 - swi r16, r1, 12 - add r5, r0, r15 - brlid r15, mcount - add r6, r0, r16 - - lwi r11, r1, 44 - lwi r12, r1, 40 - lwi r5, r1, 36 - lwi r6, r1, 32 - lwi r7, r1, 28 - lwi r8, r1, 24 - lwi r9, r1, 20 - lwi r10, r1, 16 - lwi r16, r1, 12 - rtbd r16, 4 - addi r1, r1, 48 - - #endif /* PROFILE_NO_GRAPH */ - - .end _mcount diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/profile_mcount_ppc.S b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/profile_mcount_ppc.S deleted file mode 100644 index 73e1dc69832c280cae6efdacc1f29fe9be750e5a..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/profile/profile_mcount_ppc.S +++ /dev/null @@ -1,58 +0,0 @@ -// -// Copyright (c) 2002 Xilinx, Inc. All rights reserved. -// Xilinx, Inc. -// -// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR -// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION -// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE -// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO -// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE -// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY -// AND FITNESS FOR A PARTICULAR PURPOSE. -// -// $Id: profile_mcount_ppc.S,v 1.1.2.1 2011/05/17 04:37:58 sadanan Exp $ -// - .globl _mcount - - #define _MCOUNT_STACK_FRAME 48 - .section .text - .align 2 - .type _mcount@function - - -_mcount: - stwu 1, -_MCOUNT_STACK_FRAME(1) - stw 3, 8(1) - stw 4, 12(1) - stw 5, 16(1) - stw 6, 20(1) - stw 7, 24(1) - stw 8, 28(1) - stw 9, 32(1) - stw 10, 36(1) - stw 11, 40(1) - stw 12, 44(1) - mflr 4 - stw 4, (_MCOUNT_STACK_FRAME+4)(1) - lwz 3, (_MCOUNT_STACK_FRAME)(1) - lwz 3, 4(3) - bl mcount - lwz 4, (_MCOUNT_STACK_FRAME+4)(1) - mtlr 4 - lwz 12, 44(1) - lwz 11, 40(1) - lwz 10, 36(1) - lwz 9, 32(1) - lwz 8, 28(1) - lwz 7, 24(1) - lwz 6, 20(1) - lwz 5, 16(1) - lwz 4, 12(1) - lwz 3, 8(1) - addi 1,1, _MCOUNT_STACK_FRAME - blr - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/putnum.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/putnum.c deleted file mode 100644 index f2af0ae270b662b0afbf4ac7b590ee9f4d23eb9d..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/putnum.c +++ /dev/null @@ -1,41 +0,0 @@ -/* putnum.c -- put a hex number on the output device. - * - * Copyright (c) 1995 Cygnus Support - * - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. - */ - -/* - * putnum -- print a 32 bit number in hex - */ - -extern void print (char* ); - -void putnum(unsigned int num) -{ - char buf[9]; - int cnt; - char *ptr; - int digit; - - ptr = buf; - for (cnt = 7 ; cnt >= 0 ; cnt--) { - digit = (num >> (cnt * 4)) & 0xf; - - if (digit <= 9) - *ptr++ = (char) ('0' + digit); - else - *ptr++ = (char) ('a' - 10 + digit); - } - - *ptr = (char) 0; - print (buf); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/putnum.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/putnum.o deleted file mode 100644 index 2364acf55600c485620d9e7f54c7abc8d1d4efd2..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/putnum.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/read.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/read.c deleted file mode 100644 index 609aa681bc2c31f10ae7d7dc1bb8f3abc9a72cc0..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/read.c +++ /dev/null @@ -1,100 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ - -/* read.c -- read bytes from a input device. - */ - -#include "xparameters.h" -#include "xil_printf.h" - -#ifdef __cplusplus -extern "C" { - int _read (int fd, char* buf, int nbytes); -} -#endif - -/* - * read -- read bytes from the serial port. Ignore fd, since - * we only have stdin. - */ -int -read (int fd, char* buf, int nbytes) -{ -#ifdef STDIN_BASEADDRESS - int i = 0; - - (void)fd; - for (i = 0; i < nbytes; i++) { - *(buf + i) = inbyte(); - if ((*(buf + i) == '\n' || *(buf + i) == '\r')) - break; - } - - return (i + 1); -#else - (void)fd; - (void)buf; - (void)nbytes; - return 0; -#endif -} - -int -_read (int fd, char* buf, int nbytes) -{ -#ifdef STDIN_BASEADDRESS - int i = 0; - - (void)fd; - for (i = 0; i < nbytes; i++) { - *(buf + i) = inbyte(); - if ((*(buf + i) == '\n' || *(buf + i) == '\r')) - break; - } - - return (i + 1); -#else - (void)fd; - (void)buf; - (void)nbytes; - return 0; -#endif -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/read.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/read.o deleted file mode 100644 index 7c1f5cdcc68f3c3e1b1854286b17d35b3d9d4296..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/read.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/sbrk.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/sbrk.c deleted file mode 100644 index a6fc4e34900b0a30206504456c6678fab2794aeb..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/sbrk.c +++ /dev/null @@ -1,76 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ - -#include <errno.h> -#ifdef __cplusplus -extern "C" { - char *sbrk (int nbytes); -} -#endif - -extern char _heap_start[]; -extern char _heap_end[]; -extern char HeapBase[]; -extern char HeapLimit[]; - -static char *heap_ptr; - -char *sbrk (int nbytes) -{ - char *base; - - if (!heap_ptr) - /*heap_ptr = (char *)&_heap_start;*/ - heap_ptr = (char *)&HeapBase; - - base = heap_ptr; - heap_ptr += nbytes; - -/* if (heap_ptr <= ((char *)&_heap_end + 1))*/ - if (heap_ptr <= ((char *)&HeapLimit + 1)) - return base; - - else - { - errno = ENOMEM; - return ((char *)-1); - } -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/sbrk.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/sbrk.o deleted file mode 100644 index 9131bcf30e517b976ce7591b1fa0eaafd8042f7b..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/sbrk.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/sleep.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/sleep.c deleted file mode 100644 index 64c9625e409f827d8ecdef2390160a3d9eb73967..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/sleep.c +++ /dev/null @@ -1,89 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/***************************************************************************** -* -* @file sleep.c -* -* This function provides a second delay using the Global Timer register in -* the ARM Cortex A9 MP core. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- -------- -------- ----------------------------------------------- -* 1.00a ecm/sdm 11/11/09 First release -* 3.07a sgd 07/05/12 Updated sleep function to make use Global Timer -* </pre> -* -******************************************************************************/ -/***************************** Include Files *********************************/ - -#include "sleep.h" -#include "xtime_l.h" -#include "xparameters.h" - -/*****************************************************************************/ -/* -* -* This API is used to provide delays in seconds -* -* @param seconds requested -* -* @return 0 always -* -* @note None. -* -****************************************************************************/ -int sleep(unsigned int seconds) -{ - XTime tEnd, tCur; - - XTime_GetTime(&tCur); - tEnd = tCur + ((XTime) seconds) * COUNTS_PER_SECOND; - do - { - XTime_GetTime(&tCur); - } while (tCur < tEnd); - - return 0; -} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/sleep.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/sleep.h deleted file mode 100644 index 4d9dd5abde56a317894d979c67bb6cc20fa4f1eb..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/sleep.h +++ /dev/null @@ -1,58 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ - -#ifndef SLEEP_H -#define SLEEP_H - -#ifdef __cplusplus -extern "C" { -#endif - -void nanosleep(unsigned int nanoseconds); -int usleep(unsigned int useconds); -int sleep(unsigned int seconds); - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/sleep.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/sleep.o deleted file mode 100644 index 23baceac931e01bcfd722ebffa598463fd332fd7..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/sleep.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/smc.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/smc.c deleted file mode 100644 index c6490285e6154551848458f76839c6097259784b..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/smc.c +++ /dev/null @@ -1,146 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -******************************************************************************/ -/*****************************************************************************/ -/** -* @file smc.c -* -* This file contains APIs for configuring the PL353 Static Memory Controller -* interfaces for NAND flash, SRAM and NOR flash. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- --------------------------------------------------- -* 1.00a sdm 08/02/10 Initial version -* </pre> -* -* @note -* -* None. -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "smc.h" - -/***************** Macros (Inline Functions) Definitions *********************/ - -/**************************** Type Definitions *******************************/ - -/************************** Constant Definitions *****************************/ - -/* - * Register values for using NOR interface of SMC Controller - */ -#define NOR_SET_CYCLES ((0x0 << 20) | /* set_t6 or we_time from sram_cycles */ \ - (0x1 << 17) | /* set_t5 or t_tr from sram_cycles */ \ - (0x2 << 14) | /* set_t4 or t_pc from sram_cycles */ \ - (0x5 << 11) | /* set_t3 or t_wp from sram_cycles */ \ - (0x2 << 8) | /* set_t2 t_ceoe from sram_cycles */ \ - (0x7 << 4) | /* set_t1 t_wc from sram_cycles */ \ - (0x7)) /* set_t0 t_rc from sram_cycles */ - -#define NOR_SET_OPMODE ((0x1 << 13) | /* set_burst_align,set to 32 beats */ \ - (0x1 << 12) | /* set_bls,set to default */ \ - (0x0 << 11) | /* set_adv bit, set to default */ \ - (0x0 << 10) | /* set_baa, we don't use baa_n */ \ - (0x0 << 7) | /* set_wr_bl,write brust len,set to 0 */ \ - (0x0 << 6) | /* set_wr_sync, set to 0 */ \ - (0x0 << 3) | /* set_rd_bl,read brust len,set to 0 */ \ - (0x0 << 2) | /* set_rd_sync, set to 0 */ \ - (0x0)) /* set_mw, memory width, 16bits width*/ - /* 0x00002000 */ -#define NOR_DIRECT_CMD ((0x0 << 23) | /* Chip 0 from interface 0 */ \ - (0x2 << 21) | /* UpdateRegs operation */ \ - (0x0 << 20) | /* No ModeReg write */ \ - (0x0)) /* Addr, not used in UpdateRegs */ - -/* Register values for using SRAM interface of SMC Controller */ -#define SRAM_SET_CYCLES (0x00125155) -#define SRAM_SET_OPMODE (0x00003000) -#define SRAM_DIRECT_CMD (0x00C00000) /* Chip 1 */ - -/************************** Variable Definitions *****************************/ - -/************************** Function Prototypes ******************************/ - -/**************************************************************************** -* -* Configure the SMC interface for SRAM. -* -* @param None. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void XSmc_SramInit (void) -{ - Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_SET_CYCLES, - SRAM_SET_CYCLES); - Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_SET_OPMODE, - SRAM_SET_OPMODE); - Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_DIRECT_CMD, - SRAM_DIRECT_CMD); -} - -/**************************************************************************** -* -* Configure the SMC interface for NOR flash. -* -* @param None. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void XSmc_NorInit(void) -{ - Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_SET_CYCLES, - NOR_SET_CYCLES); - Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_SET_OPMODE, - NOR_SET_OPMODE); - Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_DIRECT_CMD, - NOR_DIRECT_CMD); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/smc.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/smc.h deleted file mode 100644 index fcfccebaa6c02fe0dbd282304e0eace4ce037b4b..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/smc.h +++ /dev/null @@ -1,124 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* @file smc.h -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- --------------------------------------------------- -* 1.00a sdm 11/03/09 Initial release. -* </pre> -* -* @note None. -* -******************************************************************************/ - -#ifndef SMC_H /* prevent circular inclusions */ -#define SMC_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xparameters.h" -#include "xil_io.h" - -/***************** Macros (Inline Functions) Definitions *********************/ - -/**************************** Type Definitions *******************************/ - -/************************** Constant Definitions *****************************/ - -/* Memory controller configuration register offset */ -#define XSMCPSS_MC_STATUS 0x000 /* Controller status reg, RO */ -#define XSMCPSS_MC_INTERFACE_CONFIG 0x004 /* Interface config reg, RO */ -#define XSMCPSS_MC_SET_CONFIG 0x008 /* Set configuration reg, WO */ -#define XSMCPSS_MC_CLR_CONFIG 0x00C /* Clear config reg, WO */ -#define XSMCPSS_MC_DIRECT_CMD 0x010 /* Direct command reg, WO */ -#define XSMCPSS_MC_SET_CYCLES 0x014 /* Set cycles register, WO */ -#define XSMCPSS_MC_SET_OPMODE 0x018 /* Set opmode register, WO */ -#define XSMCPSS_MC_REFRESH_PERIOD_0 0x020 /* Refresh period_0 reg, RW */ -#define XSMCPSS_MC_REFRESH_PERIOD_1 0x024 /* Refresh period_1 reg, RW */ - -/* Chip select configuration register offset */ -#define XSMCPSS_CS_IF0_CHIP_0_OFFSET 0x100 /* Interface 0 chip 0 config */ -#define XSMCPSS_CS_IF0_CHIP_1_OFFSET 0x120 /* Interface 0 chip 1 config */ -#define XSMCPSS_CS_IF0_CHIP_2_OFFSET 0x140 /* Interface 0 chip 2 config */ -#define XSMCPSS_CS_IF0_CHIP_3_OFFSET 0x160 /* Interface 0 chip 3 config */ -#define XSMCPSS_CS_IF1_CHIP_0_OFFSET 0x180 /* Interface 1 chip 0 config */ -#define XSMCPSS_CS_IF1_CHIP_1_OFFSET 0x1A0 /* Interface 1 chip 1 config */ -#define XSMCPSS_CS_IF1_CHIP_2_OFFSET 0x1C0 /* Interface 1 chip 2 config */ -#define XSMCPSS_CS_IF1_CHIP_3_OFFSET 0x1E0 /* Interface 1 chip 3 config */ - -/* User configuration register offset */ -#define XSMCPSS_UC_STATUS_OFFSET 0x200 /* User status reg, RO */ -#define XSMCPSS_UC_CONFIG_OFFSET 0x204 /* User config reg, WO */ - -/* Integration test register offset */ -#define XSMCPSS_IT_OFFSET 0xE00 - -/* ID configuration register offset */ -#define XSMCPSS_ID_PERIP_0_OFFSET 0xFE0 -#define XSMCPSS_ID_PERIP_1_OFFSET 0xFE4 -#define XSMCPSS_ID_PERIP_2_OFFSET 0xFE8 -#define XSMCPSS_ID_PERIP_3_OFFSET 0xFEC -#define XSMCPSS_ID_PCELL_0_OFFSET 0xFF0 -#define XSMCPSS_ID_PCELL_1_OFFSET 0xFF4 -#define XSMCPSS_ID_PCELL_2_OFFSET 0xFF8 -#define XSMCPSS_ID_PCELL_3_OFFSET 0xFFC - -/************************** Variable Definitions *****************************/ - -/************************** Function Prototypes ******************************/ - -void XSmc_SramInit (void); -void XSmc_NorInit(void); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* SMC_H */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/smc.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/smc.o deleted file mode 100644 index 733a1535eea9317c27256a4e26b2954bc22654ed..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/smc.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/translation_table.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/translation_table.o deleted file mode 100644 index 32ad058fbe256a5d24aa40d6ac9b2328202d17fb..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/translation_table.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/translation_table.s b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/translation_table.s deleted file mode 100644 index c842ee9d45fe0bccf6fbc6c2e256d5de763f255b..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/translation_table.s +++ /dev/null @@ -1,141 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* @file translation_table.s -* -* This file contains the initialization for the MMU table in RAM -* needed by the Cortex A9 processor -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- --------------------------------------------------- -* 1.00a ecm 10/20/09 Initial version -* 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable -* 3.07a sgd 07/05/2012 Configuring device address spaces as shareable device -* instead of strongly-ordered. -* 3.07a asa 07/17/2012 Changed the property of the ".mmu_tbl" section. -* </pre> -* -* @note -* -* None. -* -******************************************************************************/ - .globl MMUTable - - .section .mmu_tbl,"a" - -MMUTable: - /* Each table entry occupies one 32-bit word and there are - * 4096 entries, so the entire table takes up 16KB. - * Each entry covers a 1MB section. - */ - -.set SECT, 0 - -.rept 0x0400 /* 0x00000000 - 0x3fffffff (DDR Cacheable) */ -.word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */ -.set SECT, SECT+0x100000 -.endr - -.rept 0x0400 /* 0x40000000 - 0x7fffffff (FPGA slave0) */ -.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */ -.set SECT, SECT+0x100000 -.endr - -.rept 0x0400 /* 0x80000000 - 0xbfffffff (FPGA slave1) */ -.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */ -.set SECT, SECT+0x100000 -.endr - -.rept 0x0200 /* 0xc0000000 - 0xdfffffff (unassigned/reserved). - * Generates a translation fault if accessed */ -.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */ -.set SECT, SECT+0x100000 -.endr - -.rept 0x0020 /* 0xe0000000 - 0xe1ffffff (Memory mapped devices) - * UART/USB/IIC/SPI/CAN/GEM/GPIO/QSPI/SD/NAND */ -.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */ -.set SECT, SECT+0x100000 -.endr - -.rept 0x0020 /* 0xe2000000 - 0xe3ffffff (NOR) */ -.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */ -.set SECT, SECT+0x100000 -.endr - -.rept 0x0020 /* 0xe4000000 - 0xe5ffffff (SRAM) */ -.word SECT + 0xc0e /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 */ -.set SECT, SECT+0x100000 -.endr - -.rept 0x0120 /* 0xe6000000 - 0xf7ffffff (unassigned/reserved). - * Generates a translation fault if accessed */ -.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */ -.set SECT, SECT+0x100000 -.endr - -.rept 0x0010 /* 0xf8000000 - 0xf8ffffff (AMBA APB Peripherals) */ -.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */ -.set SECT, SECT+0x100000 -.endr - -.rept 0x0030 /* 0xf9000000 - 0xfbffffff (unassigned/reserved). - * Generates a translation fault if accessed */ -.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */ -.set SECT, SECT+0x100000 -.endr - -.rept 0x003f /* 0xfc000000 - 0xffefffff (Linear QSPI - XIP) */ -.word SECT + 0xc0a /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 */ -.set SECT, SECT+0x100000 -.endr - - /* 256K OCM when mapped to high address space - * inner-cacheable */ -.word SECT + 0x4c0e /* S=b0 TEX=b100 AP=b11, Domain=b0, C=b1, B=b1 */ -.set SECT, SECT+0x100000 - -.end diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/uart.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/uart.c deleted file mode 100644 index ba7240ed2fd4b3ffb0bb2e8afb7e056ae3ed17c8..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/uart.c +++ /dev/null @@ -1,159 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -******************************************************************************/ -/*****************************************************************************/ -/** -* @file uart.c -* -* This file contains APIs for configuring the UART. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- --------------------------------------------------- -* 1.00a sdm 08/02/10 Initial version -* </pre> -* -* @note -* -* None. -* -******************************************************************************/ - -#include "xparameters.h" -#include "xil_types.h" -#include "xil_assert.h" -#include "xil_io.h" - -/* Register offsets */ -#define UART_CR_OFFSET 0x00 -#define UART_MR_OFFSET 0x04 -#define UART_BAUDGEN_OFFSET 0x18 -#define UART_BAUDDIV_OFFSET 0x34 - -#define MAX_BAUD_ERROR_RATE 3 /* max % error allowed */ -#define UART_BAUDRATE 115200 - -void Init_Uart(void); - -void Init_Uart(void) -{ -#ifdef STDOUT_BASEADDRESS - u8 IterBAUDDIV; /* Iterator for available baud divisor values */ - u32 BRGR_Value; /* Calculated value for baud rate generator */ - u32 CalcBaudRate; /* Calculated baud rate */ - u32 BaudError; /* Diff between calculated and requested baud - * rate */ - u32 Best_BRGR = 0; /* Best value for baud rate generator */ - u8 Best_BAUDDIV = 0; /* Best value for baud divisor */ - u32 Best_Error = 0xFFFFFFFF; - u32 PercentError; - u32 InputClk; - u32 BaudRate = UART_BAUDRATE; - -#if (STDOUT_BASEADDRESS == XPAR_XUARTPS_0_BASEADDR) - InputClk = XPAR_XUARTPS_0_UART_CLK_FREQ_HZ; -#elif (STDOUT_BASEADDRESS == XPAR_XUARTPS_1_BASEADDR) - InputClk = XPAR_XUARTPS_1_UART_CLK_FREQ_HZ; -#else - /* STDIO is not set or axi_uart is being used for STDIO */ - return; -#endif - - /* - * Determine the Baud divider. It can be 4to 254. - * Loop through all possible combinations - */ - for (IterBAUDDIV = 4; IterBAUDDIV < 255; IterBAUDDIV++) { - - /* - * Calculate the value for BRGR register - */ - BRGR_Value = InputClk / (BaudRate * (IterBAUDDIV + 1)); - - /* - * Calculate the baud rate from the BRGR value - */ - CalcBaudRate = InputClk/ (BRGR_Value * (IterBAUDDIV + 1)); - - /* - * Avoid unsigned integer underflow - */ - if (BaudRate > CalcBaudRate) { - BaudError = BaudRate - CalcBaudRate; - } else { - BaudError = CalcBaudRate - BaudRate; - } - - /* - * Find the calculated baud rate closest to requested baud rate. - */ - if (Best_Error > BaudError) { - - Best_BRGR = BRGR_Value; - Best_BAUDDIV = IterBAUDDIV; - Best_Error = BaudError; - } - } - - /* - * Make sure the best error is not too large. - */ - PercentError = (Best_Error * 100) / BaudRate; - if (MAX_BAUD_ERROR_RATE < PercentError) { - return; - } - - /* set CD and BDIV */ - Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, Best_BRGR); - Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, Best_BAUDDIV); - - /* - * 8 data, 1 stop, 0 parity bits - * sel_clk=uart_clk=APB clock - */ - Xil_Out32(STDOUT_BASEADDRESS + UART_MR_OFFSET, 0x20); - - /* enable Tx/Rx and reset Tx/Rx data path */ - Xil_Out32((STDOUT_BASEADDRESS + UART_CR_OFFSET), 0x17); - - return; -#endif -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/uart.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/uart.o deleted file mode 100644 index 9a3981f8028a43608d928ed39c6d92c56f80b807..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/uart.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/unlink.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/unlink.c deleted file mode 100644 index 908457004347b3ba4284f9d854630c05639b8962..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/unlink.c +++ /dev/null @@ -1,58 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ - -#include <errno.h> - -#ifdef __cplusplus -extern "C" { - int unlink(char *path); -} -#endif -/* - * unlink -- since we have no file system, - * we just return an error. - */ -int unlink(char *path) -{ - (void)path; - errno = EIO; - return (-1); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/unlink.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/unlink.o deleted file mode 100644 index bdc147170625b50039fb4a695453d94135c41fde..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/unlink.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/usleep.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/usleep.c deleted file mode 100644 index 84c0f20e39ac55cc41ac0e8d2b23324fa2015b68..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/usleep.c +++ /dev/null @@ -1,113 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file usleep.c -* -* This function provides a microsecond delay using the Global Timer register in -* the ARM Cortex A9 MP core. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- -------- -------- ----------------------------------------------- -* 1.00a ecm/sdm 11/11/09 First release -* 3.07a sgd 07/05/12 Upadted micro sleep function to make use Global Timer -* </pre> -* -******************************************************************************/ -/***************************** Include Files *********************************/ - -#include "sleep.h" -#include "xtime_l.h" -#include "xparameters.h" -#include "xpseudo_asm.h" -#include "xreg_cortexa9.h" - -/* Global Timer is always clocked at half of the CPU frequency */ -#define COUNTS_PER_USECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ / (2*1000000)) - -/*****************************************************************************/ -/** -* -* This is not implemented . -* -* @param nanoseconds -* -* @return None -* -* @note None. -* -****************************************************************************/ -void nanosleep(unsigned int nanoseconds){ - /* not implemented */ - (void)nanoseconds; -} - -/*****************************************************************************/ -/** -* -* This API gives a delay in microseconds -* -* @param useconds requested -* -* @return 0 if the delay can be achieved, -1 if the requested delay -* is out of range -* -* @note None. -* -****************************************************************************/ -int usleep(unsigned int useconds) -{ - XTime tEnd, tCur; - - XTime_GetTime(&tCur); - tEnd = tCur + ((XTime) useconds) * COUNTS_PER_USECOND; - do - { - XTime_GetTime(&tCur); - } while (tCur < tEnd); - - return 0; -} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/usleep.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/usleep.o deleted file mode 100644 index ea8bb1d46c949a99d46f409dfab9d799eb9a93a1..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/usleep.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/vectors.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/vectors.c deleted file mode 100644 index dd010d7ef92d992a5e59219e4d17f2adf9c32fd1..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/vectors.c +++ /dev/null @@ -1,177 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* @file vectors.c -* -* This file contains the C level vectors for the ARM Cortex A9 core. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- --------------------------------------------------- -* 1.00a ecm 10/20/09 Initial version, moved over from bsp area -* </pre> -* -* @note -* -* None. -* -******************************************************************************/ -/***************************** Include Files *********************************/ - -#include "xil_exception.h" -#include "vectors.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -typedef struct { - Xil_ExceptionHandler Handler; - void *Data; -} XExc_VectorTableEntry; - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Variable Definitions *****************************/ - -extern XExc_VectorTableEntry XExc_VectorTable[]; - -/************************** Function Prototypes ******************************/ - - - -/*****************************************************************************/ -/** -* -* This is the C level wrapper for the FIQ interrupt called from the vectors.s -* file. -* -* @param None. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void FIQInterrupt(void) -{ - XExc_VectorTable[XIL_EXCEPTION_ID_FIQ_INT].Handler(XExc_VectorTable[ - XIL_EXCEPTION_ID_FIQ_INT].Data); -} - -/*****************************************************************************/ -/** -* -* This is the C level wrapper for the IRQ interrupt called from the vectors.s -* file. -* -* @param None. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void IRQInterrupt(void) -{ - XExc_VectorTable[XIL_EXCEPTION_ID_IRQ_INT].Handler(XExc_VectorTable[ - XIL_EXCEPTION_ID_IRQ_INT].Data); -} - -/*****************************************************************************/ -/** -* -* This is the C level wrapper for the SW Interrupt called from the vectors.s -* file. -* -* @param None. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void SWInterrupt(void) -{ - XExc_VectorTable[XIL_EXCEPTION_ID_SWI_INT].Handler(XExc_VectorTable[ - XIL_EXCEPTION_ID_SWI_INT].Data); -} - -/*****************************************************************************/ -/** -* -* This is the C level wrapper for the DataAbort Interrupt called from the -* vectors.s file. -* -* @param None. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void DataAbortInterrupt(void) -{ - XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Handler( - XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Data); -} - -/*****************************************************************************/ -/** -* -* This is the C level wrapper for the PrefetchAbort Interrupt called from the -* vectors.s file. -* -* @param None. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void PrefetchAbortInterrupt(void) -{ - XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Handler( - XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Data); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/vectors.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/vectors.h deleted file mode 100644 index 1b094cd177f030e4eabc8413da1a3584955da49f..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/vectors.h +++ /dev/null @@ -1,90 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* @file vectors.h -* -* This file contains the C level vector prototypes for the ARM Cortex A9 core. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- --------------------------------------------------- -* 1.00a ecm 10/20/10 Initial version, moved over from bsp area -* </pre> -* -* @note -* -* None. -* -******************************************************************************/ - -#ifndef _VECTORS_H_ -#define _VECTORS_H_ - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif -/***************** Macros (Inline Functions) Definitions *********************/ - -/**************************** Type Definitions *******************************/ - -/************************** Constant Definitions *****************************/ - -/************************** Function Prototypes ******************************/ -void FIQInterrupt(void); -void IRQInterrupt(void); -void SWInterrupt(void); -void DataAbortInterrupt(void); -void PrefetchAbortInterrupt(void); - - -#ifdef __cplusplus -} -#endif - -#endif /* protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/vectors.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/vectors.o deleted file mode 100644 index bd9cae0e543000f4bf0764baca2538119867e72d..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/vectors.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/write.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/write.c deleted file mode 100644 index fff2882ad3440cb7dd5380077a7cf9bf4f6e3d4e..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/write.c +++ /dev/null @@ -1,103 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ - -/* write.c -- write bytes to an output device. - */ - -#include "xparameters.h" -#include "xil_printf.h" - -#ifdef __cplusplus -extern "C" { - int _write (int fd, char* buf, int nbytes); -} -#endif - -/* - * write -- write bytes to the serial port. Ignore fd, since - * stdout and stderr are the same. Since we have no filesystem, - * open will only return an error. - */ -int -write (int fd, char* buf, int nbytes) - -{ -#ifdef STDOUT_BASEADDRESS - int i; - - (void)fd; - for (i = 0; i < nbytes; i++) { - if (*(buf + i) == '\n') { - outbyte ('\r'); - } - outbyte (*(buf + i)); - } - return (nbytes); -#else - (void)fd; - (void)buf; - (void)nbytes; - return 0; -#endif -} - -int -_write (int fd, char* buf, int nbytes) -{ -#ifdef STDOUT_BASEADDRESS - int i; - - (void)fd; - for (i = 0; i < nbytes; i++) { - if (*(buf + i) == '\n') { - outbyte ('\r'); - } - outbyte (*(buf + i)); - } - return (nbytes); -#else - (void)fd; - (void)buf; - (void)nbytes; - return 0; -#endif -} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/write.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/write.o deleted file mode 100644 index cdfc1514011387d0f0ff34cc0034cc75633ccafa..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/write.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil-crt0.S b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil-crt0.S deleted file mode 100644 index d5409c29d8a5f2ba670ba14e7de34d863527025f..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil-crt0.S +++ /dev/null @@ -1,166 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* @file xil-crt0.S -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- --------------------------------------------------- -* 1.00a ecm 10/20/09 Initial version -* 3.05a sdm 02/02/12 Added code for profiling -* 3.06a sgd 05/16/12 Added global constructors and cleanup code -* Uart initialization based on compiler flag -* 3.07a sgd 07/05/12 Updated with reset and start Global Timer -* 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with build option -* </pre> -* -* @note -* -* None. -* -******************************************************************************/ - -.extern XSmc_NorInit -.extern XSmc_SramInit - - .file "xil-crt0.S" - .section ".got2","aw" - .align 2 - - .text -.Lsbss_start: - .long __sbss_start - -.Lsbss_end: - .long __sbss_end - -.Lbss_start: - .long __bss_start - -.Lbss_end: - .long __bss_end - -.Lstack: - .long __stack - - - .globl _start -_start: - bl __cpu_init /* Initialize the CPU first (BSP provides this) */ - - mov r0, #0 - - /* clear sbss */ - ldr r1,.Lsbss_start /* calculate beginning of the SBSS */ - ldr r2,.Lsbss_end /* calculate end of the SBSS */ - -.Lloop_sbss: - cmp r1,r2 - bge .Lenclsbss /* If no SBSS, no clearing required */ - str r0, [r1], #4 - b .Lloop_sbss - -.Lenclsbss: - /* clear bss */ - ldr r1,.Lbss_start /* calculate beginning of the BSS */ - ldr r2,.Lbss_end /* calculate end of the BSS */ - -.Lloop_bss: - cmp r1,r2 - bge .Lenclbss /* If no BSS, no clearing required */ - str r0, [r1], #4 - b .Lloop_bss - -.Lenclbss: - - /* set stack pointer */ - ldr r13,.Lstack /* stack address */ - - /* Reset and start Global Timer */ - mov r0, #0x0 - mov r1, #0x0 - bl XTime_SetTime - -#ifdef PEEP - /* Initialize STDOUT */ - bl Init_Uart - - /* Initialize the SMC interfaces for NOR */ - bl XSmc_NorInit - - /* Initialize the SMC interfaces for SRAM */ - bl XSmc_SramInit -#endif - -#ifdef PROFILING /* defined in Makefile */ - /* Setup profiling stuff */ - bl _profile_init -#endif /* PROFILING */ - - /* run global constructors */ - bl __libc_init_array - - /* make sure argc and argv are valid */ - mov r0, #0 - mov r1, #0 - - /* Let her rip */ - bl main - - /* Cleanup global constructors */ - bl __libc_fini_array - -#ifdef PROFILING - /* Cleanup profiling stuff */ - bl _profile_clean -#endif /* PROFILING */ - - /* All done */ - bl exit - -.Lexit: /* should never get here */ - b .Lexit - -.Lstart: - .size _start,.Lstart-_start diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil-crt0.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil-crt0.o deleted file mode 100644 index 047bcee914538137f0fa8b625ab9c07855a8e8fb..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil-crt0.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_assert.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_assert.c deleted file mode 100644 index 5ef2eee453516bf3c5e8843f204ceffc8cde9c8b..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_assert.c +++ /dev/null @@ -1,139 +0,0 @@ -/****************************************************************************** -* -* -* (c) Copyright 2009 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_assert.c -* -* This file contains basic assert related functions for Xilinx software IP. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.00a hbm 07/14/09 Initial release -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Variable Definitions *****************************/ - -/** - * This variable allows testing to be done easier with asserts. An assert - * sets this variable such that a driver can evaluate this variable - * to determine if an assert occurred. - */ -unsigned int Xil_AssertStatus; - -/** - * This variable allows the assert functionality to be changed for testing - * such that it does not wait infinitely. Use the debugger to disable the - * waiting during testing of asserts. - */ -int Xil_AssertWait = TRUE; - -/* The callback function to be invoked when an assert is taken */ -static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL; - -/************************** Function Prototypes ******************************/ - -/*****************************************************************************/ -/** -* -* Implement assert. Currently, it calls a user-defined callback function -* if one has been set. Then, it potentially enters an infinite loop depending -* on the value of the Xil_AssertWait variable. -* -* @param file is the name of the filename of the source -* @param line is the linenumber within File -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void Xil_Assert(const char *File, int Line) -{ - /* if the callback has been set then invoke it */ - if (Xil_AssertCallbackRoutine != 0) { - (*Xil_AssertCallbackRoutine)(File, Line); - } - - /* if specified, wait indefinitely such that the assert will show up - * in testing - */ - while (Xil_AssertWait) { - } -} - -/*****************************************************************************/ -/** -* -* Set up a callback function to be invoked when an assert occurs. If there -* was already a callback installed, then it is replaced. -* -* @param routine is the callback to be invoked when an assert is taken -* -* @return None. -* -* @note This function has no effect if NDEBUG is set -* -******************************************************************************/ -void Xil_AssertSetCallback(Xil_AssertCallback Routine) -{ - Xil_AssertCallbackRoutine = Routine; -} - - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_assert.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_assert.h deleted file mode 100644 index 419492f94d45d6e03122ba361f986222901cbada..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_assert.h +++ /dev/null @@ -1,195 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_assert.h -* -* This file contains assert related functions. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.00a hbm 07/14/09 First release -* </pre> -* -******************************************************************************/ - -#ifndef XIL_ASSERT_H /* prevent circular inclusions */ -#define XIL_ASSERT_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - - -/***************************** Include Files *********************************/ - - -/************************** Constant Definitions *****************************/ - -#define XIL_ASSERT_NONE 0 -#define XIL_ASSERT_OCCURRED 1 - -extern unsigned int Xil_AssertStatus; -extern void Xil_Assert(const char *, int); - - -/** - * This data type defines a callback to be invoked when an - * assert occurs. The callback is invoked only when asserts are enabled - */ -typedef void (*Xil_AssertCallback) (const char *File, int Line); - -/***************** Macros (Inline Functions) Definitions *********************/ - -#ifndef NDEBUG - -/*****************************************************************************/ -/** -* This assert macro is to be used for functions that do not return anything -* (void). This in conjunction with the Xil_AssertWait boolean can be used to -* accomodate tests so that asserts which fail allow execution to continue. -* -* @param expression is the expression to evaluate. If it evaluates to -* false, the assert occurs. -* -* @return Returns void unless the Xil_AssertWait variable is true, in which -* case no return is made and an infinite loop is entered. -* -* @note None. -* -******************************************************************************/ -#define Xil_AssertVoid(Expression) \ -{ \ - if (Expression) { \ - Xil_AssertStatus = XIL_ASSERT_NONE; \ - } else { \ - Xil_Assert(__FILE__, __LINE__); \ - Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ - return; \ - } \ -} - -/*****************************************************************************/ -/** -* This assert macro is to be used for functions that do return a value. This in -* conjunction with the Xil_AssertWait boolean can be used to accomodate tests -* so that asserts which fail allow execution to continue. -* -* @param expression is the expression to evaluate. If it evaluates to false, -* the assert occurs. -* -* @return Returns 0 unless the Xil_AssertWait variable is true, in which -* case no return is made and an infinite loop is entered. -* -* @note None. -* -******************************************************************************/ -#define Xil_AssertNonvoid(Expression) \ -{ \ - if (Expression) { \ - Xil_AssertStatus = XIL_ASSERT_NONE; \ - } else { \ - Xil_Assert(__FILE__, __LINE__); \ - Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ - return 0; \ - } \ -} - -/*****************************************************************************/ -/** -* Always assert. This assert macro is to be used for functions that do not -* return anything (void). Use for instances where an assert should always -* occur. -* -* @return Returns void unless the Xil_AssertWait variable is true, in which -* case no return is made and an infinite loop is entered. -* -* @note None. -* -******************************************************************************/ -#define Xil_AssertVoidAlways() \ -{ \ - Xil_Assert(__FILE__, __LINE__); \ - Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ - return; \ -} - -/*****************************************************************************/ -/** -* Always assert. This assert macro is to be used for functions that do return -* a value. Use for instances where an assert should always occur. -* -* @return Returns void unless the Xil_AssertWait variable is true, in which -* case no return is made and an infinite loop is entered. -* -* @note None. -* -******************************************************************************/ -#define Xil_AssertNonvoidAlways() \ -{ \ - Xil_Assert(__FILE__, __LINE__); \ - Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ - return 0; \ -} - - -#else - -#define Xil_AssertVoid(Expression) -#define Xil_AssertVoidAlways() -#define Xil_AssertNonvoid(Expression) -#define Xil_AssertNonvoidAlways() - -#endif - -/************************** Function Prototypes ******************************/ - -void Xil_AssertSetCallback(Xil_AssertCallback Routine); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_assert.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_assert.o deleted file mode 100644 index f815362b9aceb51a83daefd67bbd8100c3a89478..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_assert.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_cache.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_cache.c deleted file mode 100644 index 0d33b8be0b0909a482c7d37b1bb66fb71dc760c5..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_cache.c +++ /dev/null @@ -1,1499 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_cache.c -* -* Contains required functions for the ARM cache functionality. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a ecm 01/29/10 First release -* 1.00a ecm 06/24/10 Moved the L1 and L2 specific function prototypes -* to xil_cache_mach.h to give access to sophisticated users -* 3.02a sdm 04/07/11 Updated Flush/InvalidateRange APIs to flush/invalidate -* L1 and L2 caches in a single loop and used dsb, L2 sync -* at the end of the loop. -* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance -* APIs. -* 3.07a asa 07/16/12 Corrected the L1 and L2 cache invalidation order. -* 3.07a sgd 09/18/12 Corrected the L2 cache enable and disable sequence. -* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file -* 'xil_errata.h' for errata description -* 3.10a asa 05/13/13 Modified cache disable APIs. The L2 cache disable -* operation was being done with L1 Data cache disabled. This is -* fixed so that L2 cache disable operation happens independent of -* L1 cache disable operation. This fixes CR #706464. -* Changes are done to do a L2 cache sync (poll reg7_?cache_?sync). -* This is done to fix the CR #700542. -* 3.11a asa 09/23/13 Modified the Xil_DCacheFlushRange and -* Xil_DCacheInvalidateRange to fix potential issues. Fixed other -* relevant cache APIs to disable and enable back the interrupts. -* This fixes CR #663885. -* 3.11a asa 09/28/13 Made changes for L2 cache sync operation. It is found -* out that for L2 cache flush/clean/invalidation by cache lines -* does not need a cache sync as these are atomic nature. Similarly -* figured out that for complete L2 cache flush/invalidation by way -* we need to wait for some more time in a loop till the status -* shows that the cache operation is completed. -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xil_cache.h" -#include "xil_cache_l.h" -#include "xil_io.h" -#include "xpseudo_asm.h" -#include "xparameters.h" -#include "xreg_cortexa9.h" -#include "xl2cc.h" -#include "xil_errata.h" -#include "xil_exception.h" - -/************************** Function Prototypes ******************************/ - -/**************************************************************************** -* -* Access L2 Debug Control Register. -* -* @param Value, value to be written to Debug Control Register. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -#ifdef __GNUC__ -static inline Xil_L2WriteDebugCtrl(u32 Value) -#else -static void Xil_L2WriteDebugCtrl(u32 Value) -#endif -{ -#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) - Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DEBUG_CTRL_OFFSET, Value); -#else - (void)(Value); -#endif -} - -/**************************************************************************** -* -* Perform L2 Cache Sync Operation. -* -* @param None. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -#ifdef __GNUC__ -static inline Xil_L2CacheSync(void) -#else -static void Xil_L2CacheSync(void) -#endif -{ -#ifdef CONFIG_PL310_ERRATA_753970 - Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET, 0x0); -#else - Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_SYNC_OFFSET, 0x0); -#endif -} - -/**************************************************************************** -* -* Enable the Data cache. -* -* @param None. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void Xil_DCacheEnable(void) -{ - Xil_L1DCacheEnable(); - Xil_L2CacheEnable(); -} - -/**************************************************************************** -* -* Disable the Data cache. -* -* @param None. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void Xil_DCacheDisable(void) -{ - Xil_L2CacheDisable(); - Xil_L1DCacheDisable(); -} - -/**************************************************************************** -* -* Invalidate the entire Data cache. -* -* @param None. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void Xil_DCacheInvalidate(void) -{ - unsigned int currmask; - - currmask = mfcpsr(); - mtcpsr(currmask | 0xC0); - - Xil_L2CacheInvalidate(); - Xil_L1DCacheInvalidate(); - - mtcpsr(currmask); -} - -/**************************************************************************** -* -* Invalidate a Data cache line. If the byte specified by the address (adr) -* is cached by the Data cache, the cacheline containing that byte is -* invalidated. If the cacheline is modified (dirty), the modified contents -* are lost and are NOT written to system memory before the line is -* invalidated. -* -* @param Address to be flushed. -* -* @return None. -* -* @note The bottom 4 bits are set to 0, forced by architecture. -* -****************************************************************************/ -void Xil_DCacheInvalidateLine(unsigned int adr) -{ - unsigned int currmask; - - currmask = mfcpsr(); - mtcpsr(currmask | 0xC0); - - Xil_L2CacheInvalidateLine(adr); - Xil_L1DCacheInvalidateLine(adr); - - mtcpsr(currmask); -} - -/**************************************************************************** -* -* Invalidate the Data cache for the given address range. -* If the bytes specified by the address (adr) are cached by the Data cache, -* the cacheline containing that byte is invalidated. If the cacheline -* is modified (dirty), the modified contents are lost and are NOT -* written to system memory before the line is invalidated. -* -* @param Start address of range to be invalidated. -* @param Length of range to be invalidated in bytes. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void Xil_DCacheInvalidateRange(unsigned int adr, unsigned len) -{ - const unsigned cacheline = 32; - unsigned int end; - unsigned int tempadr = adr; - unsigned int tempend; - unsigned int currmask; - volatile u32 *L2CCOffset = (volatile u32 *) (XPS_L2CC_BASEADDR + - XPS_L2CC_CACHE_INVLD_PA_OFFSET); - - currmask = mfcpsr(); - mtcpsr(currmask | 0xC0); - - if (len != 0) { - end = tempadr + len; - tempend = end; - /* Select L1 Data cache in CSSR */ - mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); - - if (tempadr & (cacheline-1)) { - tempadr &= ~(cacheline - 1); - - /* Disable Write-back and line fills */ - Xil_L2WriteDebugCtrl(0x3); - Xil_L2CacheFlushLine(tempadr); - /* Enable Write-back and line fills */ - Xil_L2WriteDebugCtrl(0x0); - Xil_L1DCacheFlushLine(tempadr); - tempadr += cacheline; - } - if (tempend & (cacheline-1)) { - tempend &= ~(cacheline - 1); - - /* Disable Write-back and line fills */ - Xil_L2WriteDebugCtrl(0x3); - Xil_L2CacheFlushLine(tempend); - /* Enable Write-back and line fills */ - Xil_L2WriteDebugCtrl(0x0); - Xil_L1DCacheFlushLine(tempadr); - } - - while (tempadr < tempend) { - /* Invalidate L2 cache line */ - *L2CCOffset = tempadr; - dsb(); -#ifdef __GNUC__ - /* Invalidate L1 Data cache line */ - __asm__ __volatile__("mcr " \ - XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (tempadr)); -#elif defined (__ICCARM__) - __asm volatile ("mcr " \ - XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (tempadr)); -#else - { volatile register unsigned int Reg - __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC); - Reg = tempadr; } -#endif - tempadr += cacheline; - } - } - - dsb(); - mtcpsr(currmask); -} - -/**************************************************************************** -* -* Flush the entire Data cache. -* -* @param None. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void Xil_DCacheFlush(void) -{ - unsigned int currmask; - - currmask = mfcpsr(); - mtcpsr(currmask | 0xC0); - Xil_L1DCacheFlush(); - Xil_L2CacheFlush(); - - mtcpsr(currmask); -} - -/**************************************************************************** -* -* Flush a Data cache line. If the byte specified by the address (adr) -* is cached by the Data cache, the cacheline containing that byte is -* invalidated. If the cacheline is modified (dirty), the entire -* contents of the cacheline are written to system memory before the -* line is invalidated. -* -* @param Address to be flushed. -* -* @return None. -* -* @note The bottom 4 bits are set to 0, forced by architecture. -* -****************************************************************************/ -void Xil_DCacheFlushLine(unsigned int adr) -{ - unsigned int currmask; - - currmask = mfcpsr(); - mtcpsr(currmask | 0xC0); - Xil_L1DCacheFlushLine(adr); - - /* Disable Write-back and line fills */ - Xil_L2WriteDebugCtrl(0x3); - - Xil_L2CacheFlushLine(adr); - - /* Enable Write-back and line fills */ - Xil_L2WriteDebugCtrl(0x0); - mtcpsr(currmask); -} - -/**************************************************************************** -* Flush the Data cache for the given address range. -* If the bytes specified by the address (adr) are cached by the Data cache, -* the cacheline containing that byte is invalidated. If the cacheline -* is modified (dirty), the written to system memory first before the -* before the line is invalidated. -* -* @param Start address of range to be flushed. -* @param Length of range to be flushed in bytes. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void Xil_DCacheFlushRange(unsigned int adr, unsigned len) -{ - const unsigned cacheline = 32; - unsigned int end; - unsigned int currmask; - volatile u32 *L2CCOffset = (volatile u32 *) (XPS_L2CC_BASEADDR + - XPS_L2CC_CACHE_INV_CLN_PA_OFFSET); - - currmask = mfcpsr(); - mtcpsr(currmask | 0xC0); - - if (len != 0) { - /* Back the starting address up to the start of a cache line - * perform cache operations until adr+len - */ - end = adr + len; - adr &= ~(cacheline - 1); - - while (adr < end) { -#ifdef __GNUC__ - /* Flush L1 Data cache line */ - __asm__ __volatile__("mcr " \ - XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (adr)); -#elif defined (__ICCARM__) - __asm volatile ("mcr " \ - XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (adr)); -#else - { volatile register unsigned int Reg - __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC); - Reg = adr; } -#endif - /* Flush L2 cache line */ - *L2CCOffset = adr; - dsb(); - adr += cacheline; - } - } - dsb(); - mtcpsr(currmask); -} -/**************************************************************************** -* -* Store a Data cache line. If the byte specified by the address (adr) -* is cached by the Data cache and the cacheline is modified (dirty), -* the entire contents of the cacheline are written to system memory. -* After the store completes, the cacheline is marked as unmodified -* (not dirty). -* -* @param Address to be stored. -* -* @return None. -* -* @note The bottom 4 bits are set to 0, forced by architecture. -* -****************************************************************************/ -void Xil_DCacheStoreLine(unsigned int adr) -{ - unsigned int currmask; - - currmask = mfcpsr(); - mtcpsr(currmask | 0xC0); - - Xil_L1DCacheStoreLine(adr); - Xil_L2CacheStoreLine(adr); - mtcpsr(currmask); -} - -/**************************************************************************** -* -* Enable the instruction cache. -* -* @param None. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void Xil_ICacheEnable(void) -{ - Xil_L1ICacheEnable(); - Xil_L2CacheEnable(); -} - -/**************************************************************************** -* -* Disable the instruction cache. -* -* @param None. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void Xil_ICacheDisable(void) -{ - Xil_L2CacheDisable(); - Xil_L1ICacheDisable(); -} - -/**************************************************************************** -* -* Invalidate the entire instruction cache. -* -* @param None. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void Xil_ICacheInvalidate(void) -{ - unsigned int currmask; - - currmask = mfcpsr(); - mtcpsr(currmask | 0xC0); - - Xil_L2CacheInvalidate(); - Xil_L1ICacheInvalidate(); - - mtcpsr(currmask); -} - -/**************************************************************************** -* -* Invalidate an instruction cache line. If the instruction specified by the -* parameter adr is cached by the instruction cache, the cacheline containing -* that instruction is invalidated. -* -* @param None. -* -* @return None. -* -* @note The bottom 4 bits are set to 0, forced by architecture. -* -****************************************************************************/ -void Xil_ICacheInvalidateLine(unsigned int adr) -{ - unsigned int currmask; - - currmask = mfcpsr(); - mtcpsr(currmask | 0xC0); - Xil_L2CacheInvalidateLine(adr); - Xil_L1ICacheInvalidateLine(adr); - mtcpsr(currmask); -} - -/**************************************************************************** -* -* Invalidate the instruction cache for the given address range. -* If the bytes specified by the address (adr) are cached by the Data cache, -* the cacheline containing that byte is invalidated. If the cacheline -* is modified (dirty), the modified contents are lost and are NOT -* written to system memory before the line is invalidated. -* -* @param Start address of range to be invalidated. -* @param Length of range to be invalidated in bytes. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void Xil_ICacheInvalidateRange(unsigned int adr, unsigned len) -{ - const unsigned cacheline = 32; - unsigned int end; - volatile u32 *L2CCOffset = (volatile u32 *) (XPS_L2CC_BASEADDR + - XPS_L2CC_CACHE_INVLD_PA_OFFSET); - - unsigned int currmask; - - currmask = mfcpsr(); - mtcpsr(currmask | 0xC0); - if (len != 0) { - /* Back the starting address up to the start of a cache line - * perform cache operations until adr+len - */ - end = adr + len; - adr = adr & ~(cacheline - 1); - - /* Select cache L0 I-cache in CSSR */ - mtcp(XREG_CP15_CACHE_SIZE_SEL, 1); - - while (adr < end) { - /* Invalidate L2 cache line */ - *L2CCOffset = adr; - dsb(); -#ifdef __GNUC__ - /* Invalidate L1 I-cache line */ - __asm__ __volatile__("mcr " \ - XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (adr)); -#elif defined (__ICCARM__) - __asm volatile ("mcr " \ - XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (adr)); -#else - { volatile register unsigned int Reg - __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU); - Reg = adr; } -#endif - - adr += cacheline; - } - } - - /* Wait for L1 and L2 invalidate to complete */ - dsb(); - mtcpsr(currmask); -} - -/**************************************************************************** -* -* Enable the level 1 Data cache. -* -* @param None. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void Xil_L1DCacheEnable(void) -{ - register unsigned int CtrlReg; - - /* enable caches only if they are disabled */ -#ifdef __GNUC__ - CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); -#elif defined (__ICCARM__) - mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); -#else - { volatile register unsigned int Reg __asm(XREG_CP15_SYS_CONTROL); - CtrlReg = Reg; } -#endif - if (CtrlReg & XREG_CP15_CONTROL_C_BIT) { - return; - } - - /* clean and invalidate the Data cache */ - Xil_L1DCacheInvalidate(); - - /* enable the Data cache */ - CtrlReg |= (XREG_CP15_CONTROL_C_BIT); - - mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); -} - -/**************************************************************************** -* -* Disable the level 1 Data cache. -* -* @param None. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void Xil_L1DCacheDisable(void) -{ - register unsigned int CtrlReg; - - /* clean and invalidate the Data cache */ - Xil_L1DCacheFlush(); - -#ifdef __GNUC__ - /* disable the Data cache */ - CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); -#elif defined (__ICCARM__) - mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); -#else - { volatile register unsigned int Reg __asm(XREG_CP15_SYS_CONTROL); - CtrlReg = Reg; } -#endif - - CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); - - mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); -} - -/**************************************************************************** -* -* Invalidate the level 1 Data cache. -* -* @param None. -* -* @return None. -* -* @note In Cortex A9, there is no cp instruction for invalidating -* the whole D-cache. This function invalidates each line by -* set/way. -* -****************************************************************************/ -void Xil_L1DCacheInvalidate(void) -{ - register unsigned int CsidReg, C7Reg; - unsigned int CacheSize, LineSize, NumWays; - unsigned int Way, WayIndex, Set, SetIndex, NumSet; - unsigned int currmask; - - currmask = mfcpsr(); - mtcpsr(currmask | 0xC0); - - /* Select cache level 0 and D cache in CSSR */ - mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); - -#ifdef __GNUC__ - CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID); -#elif defined (__ICCARM__) - mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg); -#else - { volatile register unsigned int Reg __asm(XREG_CP15_CACHE_SIZE_ID); - CsidReg = Reg; } -#endif - /* Determine Cache Size */ - CacheSize = (CsidReg >> 13) & 0x1FF; - CacheSize +=1; - CacheSize *=128; /* to get number of bytes */ - - /* Number of Ways */ - NumWays = (CsidReg & 0x3ff) >> 3; - NumWays += 1; - - /* Get the cacheline size, way size, index size from csidr */ - LineSize = (CsidReg & 0x07) + 4; - - NumSet = CacheSize/NumWays; - NumSet /= (1 << LineSize); - - Way = 0UL; - Set = 0UL; - - /* Invalidate all the cachelines */ - for (WayIndex =0; WayIndex < NumWays; WayIndex++) { - for (SetIndex =0; SetIndex < NumSet; SetIndex++) { - C7Reg = Way | Set; -#ifdef __GNUC__ - /* Invalidate by Set/Way */ - __asm__ __volatile__("mcr " \ - XREG_CP15_INVAL_DC_LINE_SW :: "r" (C7Reg)); -#elif defined (__ICCARM__) - __asm volatile ("mcr " \ - XREG_CP15_INVAL_DC_LINE_SW :: "r" (C7Reg)); -#else - //mtcp(XREG_CP15_INVAL_DC_LINE_SW, C7Reg); - { volatile register unsigned int Reg - __asm(XREG_CP15_INVAL_DC_LINE_SW); - Reg = C7Reg; } -#endif - Set += (1 << LineSize); - } - Way += 0x40000000; - } - - /* Wait for L1 invalidate to complete */ - dsb(); - mtcpsr(currmask); -} - -/**************************************************************************** -* -* Invalidate a level 1 Data cache line. If the byte specified by the address -* (Addr) is cached by the Data cache, the cacheline containing that byte is -* invalidated. If the cacheline is modified (dirty), the modified contents -* are lost and are NOT written to system memory before the line is -* invalidated. -* -* @param Address to be flushed. -* -* @return None. -* -* @note The bottom 5 bits are set to 0, forced by architecture. -* -****************************************************************************/ -void Xil_L1DCacheInvalidateLine(unsigned int adr) -{ - mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); - mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F))); - - /* Wait for L1 invalidate to complete */ - dsb(); -} - -/**************************************************************************** -* -* Invalidate the level 1 Data cache for the given address range. -* If the bytes specified by the address (adr) are cached by the Data cache, -* the cacheline containing that byte is invalidated. If the cacheline -* is modified (dirty), the modified contents are lost and are NOT -* written to system memory before the line is invalidated. -* -* @param Start address of range to be invalidated. -* @param Length of range to be invalidated in bytes. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void Xil_L1DCacheInvalidateRange(unsigned int adr, unsigned len) -{ - const unsigned cacheline = 32; - unsigned int end; - unsigned int currmask; - - currmask = mfcpsr(); - mtcpsr(currmask | 0xC0); - - if (len != 0) { - /* Back the starting address up to the start of a cache line - * perform cache operations until adr+len - */ - end = adr + len; - adr = adr & ~(cacheline - 1); - - /* Select cache L0 D-cache in CSSR */ - mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); - - while (adr < end) { -#ifdef __GNUC__ - __asm__ __volatile__("mcr " \ - XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (adr)); -#elif defined (__ICCARM__) - __asm volatile ("mcr " \ - XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (adr)); -#else - { volatile register unsigned int Reg - __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC); - Reg = adr; } -#endif - adr += cacheline; - } - } - - /* Wait for L1 invalidate to complete */ - dsb(); - mtcpsr(currmask); -} - -/**************************************************************************** -* -* Flush the level 1 Data cache. -* -* @param None. -* -* @return None. -* -* @note In Cortex A9, there is no cp instruction for flushing -* the whole D-cache. Need to flush each line. -* -****************************************************************************/ -void Xil_L1DCacheFlush(void) -{ - register unsigned int CsidReg, C7Reg; - unsigned int CacheSize, LineSize, NumWays; - unsigned int Way, WayIndex, Set, SetIndex, NumSet; - unsigned int currmask; - - currmask = mfcpsr(); - mtcpsr(currmask | 0xC0); - - /* Select cache level 0 and D cache in CSSR */ - mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); - -#ifdef __GNUC__ - CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID); -#elif defined (__ICCARM__) - mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg); -#else - { volatile register unsigned int Reg __asm(XREG_CP15_CACHE_SIZE_ID); - CsidReg = Reg; } -#endif - - /* Determine Cache Size */ - - CacheSize = (CsidReg >> 13) & 0x1FF; - CacheSize +=1; - CacheSize *=128; /* to get number of bytes */ - - /* Number of Ways */ - NumWays = (CsidReg & 0x3ff) >> 3; - NumWays += 1; - - /* Get the cacheline size, way size, index size from csidr */ - LineSize = (CsidReg & 0x07) + 4; - - NumSet = CacheSize/NumWays; - NumSet /= (1 << LineSize); - - Way = 0UL; - Set = 0UL; - - /* Invalidate all the cachelines */ - for (WayIndex =0; WayIndex < NumWays; WayIndex++) { - for (SetIndex =0; SetIndex < NumSet; SetIndex++) { - C7Reg = Way | Set; - /* Flush by Set/Way */ -#ifdef __GNUC__ - __asm__ __volatile__("mcr " \ - XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (C7Reg)); -#elif defined (__ICCARM__) - __asm volatile ("mcr " \ - XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (C7Reg)); -#else - { volatile register unsigned int Reg - __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_SW); - Reg = C7Reg; } -#endif - Set += (1 << LineSize); - } - Way += 0x40000000; - } - - /* Wait for L1 flush to complete */ - dsb(); - mtcpsr(currmask); -} - -/**************************************************************************** -* -* Flush a level 1 Data cache line. If the byte specified by the address (adr) -* is cached by the Data cache, the cacheline containing that byte is -* invalidated. If the cacheline is modified (dirty), the entire -* contents of the cacheline are written to system memory before the -* line is invalidated. -* -* @param Address to be flushed. -* -* @return None. -* -* @note The bottom 5 bits are set to 0, forced by architecture. -* -****************************************************************************/ -void Xil_L1DCacheFlushLine(unsigned int adr) -{ - mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); - mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F))); - - /* Wait for L1 flush to complete */ - dsb(); -} - -/**************************************************************************** -* Flush the level 1 Data cache for the given address range. -* If the bytes specified by the address (adr) are cached by the Data cache, -* the cacheline containing that byte is invalidated. If the cacheline -* is modified (dirty), the written to system memory first before the -* before the line is invalidated. -* -* @param Start address of range to be flushed. -* @param Length of range to be flushed in bytes. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void Xil_L1DCacheFlushRange(unsigned int adr, unsigned len) -{ - const unsigned cacheline = 32; - unsigned int end; - unsigned int currmask; - - currmask = mfcpsr(); - mtcpsr(currmask | 0xC0); - - if (len != 0) { - /* Back the starting address up to the start of a cache line - * perform cache operations until adr+len - */ - end = adr + len; - adr = adr & ~(cacheline - 1); - - /* Select cache L0 D-cache in CSSR */ - mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); - - while (adr < end) { -#ifdef __GNUC__ - __asm__ __volatile__("mcr " \ - XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (adr)); -#elif defined (__ICCARM__) - __asm volatile ("mcr " \ - XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (adr)); -#else - { volatile register unsigned int Reg - __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC); - Reg = adr; } -#endif - adr += cacheline; - } - } - - /* Wait for L1 flush to complete */ - dsb(); - mtcpsr(currmask); -} - -/**************************************************************************** -* -* Store a level 1 Data cache line. If the byte specified by the address (adr) -* is cached by the Data cache and the cacheline is modified (dirty), -* the entire contents of the cacheline are written to system memory. -* After the store completes, the cacheline is marked as unmodified -* (not dirty). -* -* @param Address to be stored. -* -* @return None. -* -* @note The bottom 5 bits are set to 0, forced by architecture. -* -****************************************************************************/ -void Xil_L1DCacheStoreLine(unsigned int adr) -{ - mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); - mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1F))); - - /* Wait for L1 store to complete */ - dsb(); -} - -/**************************************************************************** -* -* Enable the level 1 instruction cache. -* -* @param None. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void Xil_L1ICacheEnable(void) -{ - register unsigned int CtrlReg; - - /* enable caches only if they are disabled */ -#ifdef __GNUC__ - CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); -#elif defined (__ICCARM__) - mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); -#else - { volatile register unsigned int Reg __asm(XREG_CP15_SYS_CONTROL); - CtrlReg = Reg; } -#endif - if (CtrlReg & XREG_CP15_CONTROL_I_BIT) { - return; - } - - /* invalidate the instruction cache */ - mtcp(XREG_CP15_INVAL_IC_POU, 0); - - /* enable the instruction cache */ - CtrlReg |= (XREG_CP15_CONTROL_I_BIT); - - mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); -} - -/**************************************************************************** -* -* Disable level 1 the instruction cache. -* -* @param None. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void Xil_L1ICacheDisable(void) -{ - register unsigned int CtrlReg; - - dsb(); - - /* invalidate the instruction cache */ - mtcp(XREG_CP15_INVAL_IC_POU, 0); - - /* disable the instruction cache */ -#ifdef __GNUC__ - CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); -#elif defined (__ICCARM__) - mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); -#else - { volatile register unsigned int Reg __asm(XREG_CP15_SYS_CONTROL); - CtrlReg = Reg; } -#endif - CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT); - - mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); -} - -/**************************************************************************** -* -* Invalidate the entire level 1 instruction cache. -* -* @param None. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void Xil_L1ICacheInvalidate(void) -{ - mtcp(XREG_CP15_CACHE_SIZE_SEL, 1); - /* invalidate the instruction cache */ - mtcp(XREG_CP15_INVAL_IC_POU, 0); - - /* Wait for L1 invalidate to complete */ - dsb(); -} - -/**************************************************************************** -* -* Invalidate a level 1 instruction cache line. If the instruction specified by -* the parameter adr is cached by the instruction cache, the cacheline containing -* that instruction is invalidated. -* -* @param None. -* -* @return None. -* -* @note The bottom 5 bits are set to 0, forced by architecture. -* -****************************************************************************/ -void Xil_L1ICacheInvalidateLine(unsigned int adr) -{ - mtcp(XREG_CP15_CACHE_SIZE_SEL, 1); - mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1F))); - - /* Wait for L1 invalidate to complete */ - dsb(); -} - -/**************************************************************************** -* -* Invalidate the level 1 instruction cache for the given address range. -* If the bytes specified by the address (adr) are cached by the Data cache, -* the cacheline containing that byte is invalidated. If the cacheline -* is modified (dirty), the modified contents are lost and are NOT -* written to system memory before the line is invalidated. -* -* @param Start address of range to be invalidated. -* @param Length of range to be invalidated in bytes. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void Xil_L1ICacheInvalidateRange(unsigned int adr, unsigned len) -{ - const unsigned cacheline = 32; - unsigned int end; - unsigned int currmask; - - currmask = mfcpsr(); - mtcpsr(currmask | 0xC0); - - if (len != 0) { - /* Back the starting address up to the start of a cache line - * perform cache operations until adr+len - */ - end = adr + len; - adr = adr & ~(cacheline - 1); - - /* Select cache L0 I-cache in CSSR */ - mtcp(XREG_CP15_CACHE_SIZE_SEL, 1); - - while (adr < end) { -#ifdef __GNUC__ - __asm__ __volatile__("mcr " \ - XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (adr)); -#elif defined (__ICCARM__) - __asm volatile ("mcr " \ - XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (adr)); -#else - { volatile register unsigned int Reg - __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU); - Reg = adr; } -#endif - adr += cacheline; - } - } - - /* Wait for L1 invalidate to complete */ - dsb(); - mtcpsr(currmask); -} - -/**************************************************************************** -* -* Enable the L2 cache. -* -* @param None. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void Xil_L2CacheEnable(void) -{ - register unsigned int L2CCReg; - - L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET); - - /* only enable if L2CC is currently disabled */ - if ((L2CCReg & 0x01) == 0) { - /* set up the way size and latencies */ - L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + - XPS_L2CC_AUX_CNTRL_OFFSET); - L2CCReg &= XPS_L2CC_AUX_REG_ZERO_MASK; - L2CCReg |= XPS_L2CC_AUX_REG_DEFAULT_MASK; - Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_AUX_CNTRL_OFFSET, - L2CCReg); - Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_TAG_RAM_CNTRL_OFFSET, - XPS_L2CC_TAG_RAM_DEFAULT_MASK); - Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DATA_RAM_CNTRL_OFFSET, - XPS_L2CC_DATA_RAM_DEFAULT_MASK); - - /* Clear the pending interrupts */ - L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + - XPS_L2CC_ISR_OFFSET); - Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_IAR_OFFSET, L2CCReg); - - Xil_L2CacheInvalidate(); - /* Enable the L2CC */ - L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + - XPS_L2CC_CNTRL_OFFSET); - Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET, - (L2CCReg | (0x01))); - - Xil_L2CacheSync(); - /* synchronize the processor */ - dsb(); - - } -} - -/**************************************************************************** -* -* Disable the L2 cache. -* -* @param None. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void Xil_L2CacheDisable(void) -{ - register unsigned int L2CCReg; - - L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET); - - if(L2CCReg & 0x1) { - - /* Clean and Invalidate L2 Cache */ - Xil_L2CacheFlush(); - - /* Disable the L2CC */ - L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET); - Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET, - (L2CCReg & (~0x01))); - /* Wait for the cache operations to complete */ - - dsb(); - } -} - -/**************************************************************************** -* -* Invalidate the L2 cache. If the byte specified by the address (adr) -* is cached by the Data cache, the cacheline containing that byte is -* invalidated. If the cacheline is modified (dirty), the modified contents -* are lost and are NOT written to system memory before the line is -* invalidated. -* -* @param Address to be flushed. -* -* @return None. -* -* @note The bottom 4 bits are set to 0, forced by architecture. -* -****************************************************************************/ -void Xil_L2CacheInvalidate(void) -{ - /* Invalidate the caches */ - Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET, - 0x0000FFFF); - while((Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET)) - & 0x0000FFFF); - - /* Wait for the invalidate to complete */ - Xil_L2CacheSync(); - - /* synchronize the processor */ - dsb(); -} - -/**************************************************************************** -* -* Invalidate a level 2 cache line. If the byte specified by the address (adr) -* is cached by the Data cache, the cacheline containing that byte is -* invalidated. If the cacheline is modified (dirty), the modified contents -* are lost and are NOT written to system memory before the line is -* invalidated. -* -* @param Address to be flushed. -* -* @return None. -* -* @note The bottom 4 bits are set to 0, forced by architecture. -* -****************************************************************************/ -void Xil_L2CacheInvalidateLine(unsigned int adr) -{ - Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, adr); - /* synchronize the processor */ - dsb(); -} - -/**************************************************************************** -* -* Invalidate the level 2 cache for the given address range. -* If the bytes specified by the address (adr) are cached by the Data cache, -* the cacheline containing that byte is invalidated. If the cacheline -* is modified (dirty), the modified contents are lost and are NOT -* written to system memory before the line is invalidated. -* -* @param Start address of range to be invalidated. -* @param Length of range to be invalidated in bytes. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void Xil_L2CacheInvalidateRange(unsigned int adr, unsigned len) -{ - const unsigned cacheline = 32; - unsigned int end; - volatile u32 *L2CCOffset = (volatile u32 *) (XPS_L2CC_BASEADDR + - XPS_L2CC_CACHE_INVLD_PA_OFFSET); - - unsigned int currmask; - - currmask = mfcpsr(); - mtcpsr(currmask | 0xC0); - - if (len != 0) { - /* Back the starting address up to the start of a cache line - * perform cache operations until adr+len - */ - end = adr + len; - adr = adr & ~(cacheline - 1); - - /* Disable Write-back and line fills */ - Xil_L2WriteDebugCtrl(0x3); - - while (adr < end) { - *L2CCOffset = adr; - adr += cacheline; - } - - /* Enable Write-back and line fills */ - Xil_L2WriteDebugCtrl(0x0); - } - - /* synchronize the processor */ - dsb(); - mtcpsr(currmask); -} - -/**************************************************************************** -* -* Flush the L2 cache. If the byte specified by the address (adr) -* is cached by the Data cache, the cacheline containing that byte is -* invalidated. If the cacheline is modified (dirty), the entire -* contents of the cacheline are written to system memory before the -* line is invalidated. -* -* @param Address to be flushed. -* -* @return None. -* -* @note The bottom 4 bits are set to 0, forced by architecture. -* -****************************************************************************/ -void Xil_L2CacheFlush(void) -{ - unsigned int L2CCReg; - - /* Flush the caches */ - - /* Disable Write-back and line fills */ - Xil_L2WriteDebugCtrl(0x3); - - Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET, - 0x0000FFFF); - - while((Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET)) - & 0x0000FFFF); - - Xil_L2CacheSync(); - /* Enable Write-back and line fills */ - Xil_L2WriteDebugCtrl(0x0); - - /* synchronize the processor */ - dsb(); -} - -/**************************************************************************** -* -* Flush a level 2 cache line. If the byte specified by the address (adr) -* is cached by the Data cache, the cacheline containing that byte is -* invalidated. If the cacheline is modified (dirty), the entire -* contents of the cacheline are written to system memory before the -* line is invalidated. -* -* @param Address to be flushed. -* -* @return None. -* -* @note The bottom 4 bits are set to 0, forced by architecture. -* -****************************************************************************/ -void Xil_L2CacheFlushLine(unsigned int adr) -{ -#ifdef CONFIG_PL310_ERRATA_588369 - Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr); - Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, adr); -#else - Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_PA_OFFSET, adr); -#endif - /* synchronize the processor */ - dsb(); -} - -/**************************************************************************** -* Flush the level 2 cache for the given address range. -* If the bytes specified by the address (adr) are cached by the Data cache, -* the cacheline containing that byte is invalidated. If the cacheline -* is modified (dirty), the written to system memory first before the -* before the line is invalidated. -* -* @param Start address of range to be flushed. -* @param Length of range to be flushed in bytes. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void Xil_L2CacheFlushRange(unsigned int adr, unsigned len) -{ - const unsigned cacheline = 32; - unsigned int end; - volatile u32 *L2CCOffset = (volatile u32 *) (XPS_L2CC_BASEADDR + - XPS_L2CC_CACHE_INV_CLN_PA_OFFSET); - - unsigned int currmask; - - currmask = mfcpsr(); - mtcpsr(currmask | 0xC0); - if (len != 0) { - /* Back the starting address up to the start of a cache line - * perform cache operations until adr+len - */ - end = adr + len; - adr = adr & ~(cacheline - 1); - - /* Disable Write-back and line fills */ - Xil_L2WriteDebugCtrl(0x3); - - while (adr < end) { - *L2CCOffset = adr; - Xil_L2CacheSync(); - adr += cacheline; - } - - /* Enable Write-back and line fills */ - Xil_L2WriteDebugCtrl(0x0); - } - /* synchronize the processor */ - dsb(); - mtcpsr(currmask); -} - -/**************************************************************************** -* -* Store a level 2 cache line. If the byte specified by the address (adr) -* is cached by the Data cache and the cacheline is modified (dirty), -* the entire contents of the cacheline are written to system memory. -* After the store completes, the cacheline is marked as unmodified -* (not dirty). -* -* @param Address to be stored. -* -* @return None. -* -* @note The bottom 4 bits are set to 0, forced by architecture. -* -****************************************************************************/ -void Xil_L2CacheStoreLine(unsigned int adr) -{ - Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr); - /* synchronize the processor */ - dsb(); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_cache.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_cache.h deleted file mode 100644 index e1e0adaacd90a7ad1ce8326ddfaa330b493a549d..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_cache.h +++ /dev/null @@ -1,84 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_cache.h -* -* Contains required functions for the ARM cache functionality -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a ecm 01/29/10 First release -* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance -* APIs. -* </pre> -* -******************************************************************************/ -#ifndef XIL_CACHE_H -#define XIL_CACHE_H - -#include "xil_types.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void Xil_DCacheEnable(void); -void Xil_DCacheDisable(void); -void Xil_DCacheInvalidate(void); -void Xil_DCacheInvalidateRange(unsigned int adr, unsigned len); -void Xil_DCacheFlush(void); -void Xil_DCacheFlushRange(unsigned int adr, unsigned len); - -void Xil_ICacheEnable(void); -void Xil_ICacheDisable(void); -void Xil_ICacheInvalidate(void); -void Xil_ICacheInvalidateRange(unsigned int adr, unsigned len); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_cache.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_cache.o deleted file mode 100644 index 25338eccf721af37925bfc5d4caf6638bd556b9f..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_cache.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_cache_l.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_cache_l.h deleted file mode 100644 index d0c3f40e6793ca07a354b32cc0cf9a2657b3428f..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_cache_l.h +++ /dev/null @@ -1,103 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_cache_l.h -* -* Contains L1 and L2 specific functions for the ARM cache functionality -* used by xcache.c. This functionality is being made available here for -* more sophisticated users. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a ecm 01/24/10 First release -* </pre> -* -******************************************************************************/ -#ifndef XIL_CACHE_MACH_H -#define XIL_CACHE_MACH_H - -#ifdef __cplusplus -extern "C" { -#endif - -/************************** Function Prototypes ******************************/ - -void Xil_DCacheInvalidateLine(unsigned int adr); -void Xil_DCacheFlushLine(unsigned int adr); -void Xil_DCacheStoreLine(unsigned int adr); -void Xil_ICacheInvalidateLine(unsigned int adr); - -void Xil_L1DCacheEnable(void); -void Xil_L1DCacheDisable(void); -void Xil_L1DCacheInvalidate(void); -void Xil_L1DCacheInvalidateLine(unsigned int adr); -void Xil_L1DCacheInvalidateRange(unsigned int adr, unsigned len); -void Xil_L1DCacheFlush(void); -void Xil_L1DCacheFlushLine(unsigned int adr); -void Xil_L1DCacheFlushRange(unsigned int adr, unsigned len); -void Xil_L1DCacheStoreLine(unsigned int adr); - -void Xil_L1ICacheEnable(void); -void Xil_L1ICacheDisable(void); -void Xil_L1ICacheInvalidate(void); -void Xil_L1ICacheInvalidateLine(unsigned int adr); -void Xil_L1ICacheInvalidateRange(unsigned int adr, unsigned len); - -void Xil_L2CacheEnable(void); -void Xil_L2CacheDisable(void); -void Xil_L2CacheInvalidate(void); -void Xil_L2CacheInvalidateLine(unsigned int adr); -void Xil_L2CacheInvalidateRange(unsigned int adr, unsigned len); -void Xil_L2CacheFlush(void); -void Xil_L2CacheFlushLine(unsigned int adr); -void Xil_L2CacheFlushRange(unsigned int adr, unsigned len); -void Xil_L2CacheStoreLine(unsigned int adr); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_cache_vxworks.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_cache_vxworks.h deleted file mode 100644 index 3ad8965dfc8eba8a24f5f9f7cd1a03375eaaca0e..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_cache_vxworks.h +++ /dev/null @@ -1,103 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_cache_vxworks.h -* -* Contains the cache related functions for VxWorks that is wrapped by -* xil_cache. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.00a hbm 12/11/09 Initial release -* -* </pre> -* -* @note -* -******************************************************************************/ - -#ifndef XIL_CACHE_VXWORKS_H -#define XIL_CACHE_VXWORKS_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "vxWorks.h" -#include "vxLib.h" -#include "sysLibExtra.h" -#include "cacheLib.h" - -#if (CPU_FAMILY==PPC) - -#define Xil_DCacheEnable() cacheEnable(DATA_CACHE) - -#define Xil_DCacheDisable() cacheDisable(DATA_CACHE) - -#define Xil_DCacheInvalidateRange(Addr, Len) \ - cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len)) - -#define Xil_DCacheFlushRange(Addr, Len) \ - cacheFlush(DATA_CACHE, (void *)(Addr), (Len)) - -#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE) - -#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE) - -#define Xil_ICacheInvalidateRange(Addr, Len) \ - cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len)) - - -#else -#error "Unknown processor / architecture. Must be PPC for VxWorks." -#endif - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_errata.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_errata.h deleted file mode 100644 index bb09eef3fe4c23dfe9206faf56690245dd104c11..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_errata.h +++ /dev/null @@ -1,117 +0,0 @@ -/******************************************************************************* -* -* (c) Copyright 2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -*******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_errata.h -* -* This header file contains Cortex A9 and PL310 Errata definitions. -* -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a srt 04/18/13 First release -* </pre> -* -******************************************************************************/ -#ifndef XIL_ERRATA_H -#define XIL_ERRATA_H - -#define ENABLE_ARM_ERRATA 1 - -#ifdef ENABLE_ARM_ERRATA -/* Cortex A9 ARM Errata */ - -/* - * Errata No: 742230 - * Description: DMB operation may be faulty - */ -#define CONFIG_ARM_ERRATA_742230 1 - -/* - * Errata No: 743622 - * Description: Faulty hazard checking in the Store Buffer may lead - * to data corruption. - */ -#define CONFIG_ARM_ERRATA_743622 1 - -/* - * Errata No: 775420 - * Description: A data cache maintenance operation which aborts, - * might lead to deadlock - */ -#define CONFIG_ARM_ERRATA_775420 1 - -/* - * Errata No: 794073 - * Description: Speculative instruction fetches with MMU disabled - * might not comply with architectural requirements - */ -#define CONFIG_ARM_ERRATA_794073 1 - - -/* PL310 L2 Cache Errata */ - -/* - * Errata No: 588369 - * Description: Clean & Invalidate maintenance operations do not - * invalidate clean lines - */ -#define CONFIG_PL310_ERRATA_588369 1 - -/* - * Errata No: 727915 - * Description: Background Clean and Invalidate by Way operation - * can cause data corruption - */ -#define CONFIG_PL310_ERRATA_727915 1 - -/* - * Errata No: 753970 - * Description: Cache sync operation may be faulty - */ -#define CONFIG_PL310_ERRATA_753970 1 - -#endif /* ENABLE_ARM_ERRATA */ - -#endif /* XIL_ERRATA_H */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_exception.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_exception.c deleted file mode 100644 index 77ab9986df71087ac92b6031f679013e68ae1a0b..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_exception.c +++ /dev/null @@ -1,188 +0,0 @@ -/***************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file xil_exception.c -* -* This file contains low-level driver functions for the Cortex A9 exception -* Handler. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- -------- -------- ----------------------------------------------- -* 1.00a ecm/sdm 11/04/09 First release -* 3.05a sdm 02/02/12 Updated to resiter a null handler only if a handler -* is not already registered -* </pre> -* -*****************************************************************************/ - -/***************************** Include Files ********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xil_exception.h" -#include "xpseudo_asm.h" - -/************************** Constant Definitions ****************************/ - -/**************************** Type Definitions ******************************/ - -typedef struct { - Xil_ExceptionHandler Handler; - void *Data; -} XExc_VectorTableEntry; - -/***************** Macros (Inline Functions) Definitions ********************/ - -/************************** Function Prototypes *****************************/ - -/************************** Variable Definitions *****************************/ -/* - * Exception vector table to store handlers for each exception vector. - */ -XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1]; - -/*****************************************************************************/ - -/****************************************************************************/ -/** -* -* This function is a stub Handler that is the default Handler that gets called -* if the application has not setup a Handler for a specific exception. The -* function interface has to match the interface specified for a Handler even -* though none of the arguments are used. -* -* @param Data is unused by this function. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -static void Xil_ExceptionNullHandler(void *Data) -{ - (void)Data; -DieLoop: goto DieLoop; -} - -/****************************************************************************/ -/** -* -* Initialize exception handling for the Processor. The exception vector table -* is setup with the stub Handler for all exceptions. -* -* @param None. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void Xil_ExceptionInit(void) -{ - unsigned long index; - - /* - * Initialize the vector table. Register the stub Handler for each - * exception. - */ - for(index = XIL_EXCEPTION_ID_FIRST; index < XIL_EXCEPTION_ID_LAST + 1; - index++) { - if (XExc_VectorTable[index].Handler == NULL) { - Xil_ExceptionRegisterHandler(index, - Xil_ExceptionNullHandler, - NULL); - } - } -} - -/*****************************************************************************/ -/** -* -* Makes the connection between the Id of the exception source and the -* associated Handler that is to run when the exception is recognized. The -* argument provided in this call as the Data is used as the argument -* for the Handler when it is called. -* -* @param exception_id contains the ID of the exception source and should -* be in the range of 0 to XIL_EXCEPTION_ID_LAST. - See xil_exception_l.h for further information. -* @param Handler to the Handler for that exception. -* @param Data is a reference to Data that will be passed to the -* Handler when it gets called. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void Xil_ExceptionRegisterHandler(u32 exception_id, - Xil_ExceptionHandler Handler, - void *Data) -{ - XExc_VectorTable[exception_id].Handler = Handler; - XExc_VectorTable[exception_id].Data = Data; -} - -/*****************************************************************************/ -/** -* -* Removes the Handler for a specific exception Id. The stub Handler is then -* registered for this exception Id. -* -* @param exception_id contains the ID of the exception source and should -* be in the range of 0 to XIL_EXCEPTION_ID_LAST. -* See xil_exception_l.h for further information. - -* @return None. -* -* @note None. -* -****************************************************************************/ -void Xil_ExceptionRemoveHandler(u32 exception_id) -{ - Xil_ExceptionRegisterHandler(exception_id, - Xil_ExceptionNullHandler, - NULL); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_exception.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_exception.h deleted file mode 100644 index dfa50d7fafc5cf8c1a393dd550638b721981b904..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_exception.h +++ /dev/null @@ -1,241 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_exception.h -* -* This header file contains ARM Cortex A9 specific exception related APIs. -* For exception related functions that can be used across all Xilinx supported -* processors, please use xil_exception.h. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- -------- -------- ----------------------------------------------- -* 1.00a ecm/sdm 11/04/09 First release -* </pre> -* -******************************************************************************/ - -#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */ -#define XIL_EXCEPTION_H /* by using protection macros */ - -/***************************** Include Files ********************************/ - -#include "xil_types.h" -#include "xpseudo_asm.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/************************** Constant Definitions ****************************/ - -#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE -#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE -#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE) - -#define XIL_EXCEPTION_ID_FIRST 0 -#define XIL_EXCEPTION_ID_RESET 0 -#define XIL_EXCEPTION_ID_UNDEFINED_INT 1 -#define XIL_EXCEPTION_ID_SWI_INT 2 -#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3 -#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4 -#define XIL_EXCEPTION_ID_IRQ_INT 5 -#define XIL_EXCEPTION_ID_FIQ_INT 6 -#define XIL_EXCEPTION_ID_LAST 6 - -/* - * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors. - */ -#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT - -/**************************** Type Definitions ******************************/ - -/** - * This typedef is the exception handler function. - */ -typedef void (*Xil_ExceptionHandler)(void *data); -typedef void (*Xil_InterruptHandler)(void *data); - -/***************** Macros (Inline Functions) Definitions ********************/ - -/****************************************************************************/ -/** -* Enable Exceptions. -* -* @param Mask for exceptions to be enabled. -* -* @return None. -* -* @note If bit is 0, exception is enabled. -* C-Style signature: void Xil_ExceptionEnableMask(Mask); -* -******************************************************************************/ -#ifdef __GNUC__ -#define Xil_ExceptionEnableMask(Mask) \ - mtcpsr(mfcpsr() & ~ (Mask & XIL_EXCEPTION_ALL)) -#elif defined (__ICCARM__) -#define Xil_ExceptionEnableMask(Mask) \ - { register unsigned int rval; \ - mfcpsr(rval); \ - mtcpsr(rval & ~ (Mask & XIL_EXCEPTION_ALL)) ;} -#else -#define Xil_ExceptionEnableMask(Mask) \ - { register unsigned int Reg __asm("cpsr"); \ - mtcpsr(Reg & ~ (Mask & XIL_EXCEPTION_ALL)) } -#endif - -/****************************************************************************/ -/** -* Enable the IRQ exception. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -#define Xil_ExceptionEnable() \ - Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ) - -/****************************************************************************/ -/** -* Disable Exceptions. -* -* @param Mask for exceptions to be enabled. -* -* @return None. -* -* @note If bit is 1, exception is disabled. -* C-Style signature: Xil_ExceptionDisableMask(Mask); -* -******************************************************************************/ -#ifdef __GNUC__ -#define Xil_ExceptionDisableMask(Mask) \ - mtcpsr(mfcpsr() | (Mask & XIL_EXCEPTION_ALL)) -#elif defined (__ICCARM__) -#define Xil_ExceptionDisableMask(Mask) \ - { register unsigned int rval; \ - mfcpsr(rval); \ - mtcpsr(rval | (Mask & XIL_EXCEPTION_ALL)) ;} -#else -#define Xil_ExceptionDisableMask(Mask) \ - { register unsigned int Reg __asm("cpsr"); \ - mtcpsr(Reg | (Mask & XIL_EXCEPTION_ALL)) } -#endif - -/****************************************************************************/ -/** -* Disable the IRQ exception. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -#define Xil_ExceptionDisable() \ - Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ) - -/****************************************************************************/ -/** -* Enable nested interrupts by clearing the I and F bits it CPSR -* -* @return None. -* -* @note This macro is supposed to be used from interrupt handlers. In the -* interrupt handler the interrupts are disabled by default (I and F -* are 1). To allow nesting of interrupts, this macro should be -* used. It clears the I and F bits by changing the ARM mode to -* system mode. Once these bits are cleared and provided the -* preemption of interrupt conditions are met in the GIC, nesting of -* interrupts will start happening. -* Caution: This macro must be used with caution. Before calling this -* macro, the user must ensure that the source of the current IRQ -* is appropriately cleared. Otherwise, as soon as we clear the I and -* F bits, there can be an infinite loop of interrupts with an -* eventual crash (all the stack space getting consumed). -******************************************************************************/ -#define Xil_EnableNestedInterrupts() \ - __asm__ __volatile__ ("mrs lr, spsr"); \ - __asm__ __volatile__ ("stmfd sp!, {lr}"); \ - __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \ - __asm__ __volatile__ ("stmfd sp!, {lr}"); - -/****************************************************************************/ -/** -* Disable the nested interrupts by setting the I and F bits. -* -* @return None. -* -* @note This macro is meant to be called in the interrupt service routines. -* This macro cannot be used independently. It can only be used when -* nesting of interrupts have been enabled by using the macro -* Xil_EnableNestedInterrupts(). In a typical flow, the user first -* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate -* point. The user then must call this macro before exiting the interrupt -* service routine. This macro puts the ARM back in IRQ/FIQ mode and -* hence sets back the I and F bits. -******************************************************************************/ -#define Xil_DisableNestedInterrupts() \ - __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ - __asm__ __volatile__ ("msr cpsr_c, #0x92"); \ - __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ - __asm__ __volatile__ ("msr spsr_cxsf, lr"); - -/************************** Variable Definitions ****************************/ - -/************************** Function Prototypes *****************************/ - -extern void Xil_ExceptionRegisterHandler(u32 id, - Xil_ExceptionHandler handler, - void *data); - -extern void Xil_ExceptionRemoveHandler(u32 id); - -extern void Xil_ExceptionInit(void); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* XIL_EXCEPTION_H */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_exception.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_exception.o deleted file mode 100644 index c2faebaf6cde063570bd818023cdd4f49c551270..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_exception.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_hal.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_hal.h deleted file mode 100644 index b58c7eb8af67a90dc3e8a81648537aa9b12014df..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_hal.h +++ /dev/null @@ -1,71 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_hal.h -* -* Contains all the HAL header files. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.00a hbm 07/28/09 Initial release -* -* </pre> -* -* @note -* -******************************************************************************/ - -#ifndef XIL_HAL_H -#define XIL_HAL_H - -#include "xil_cache.h" -#include "xil_io.h" -#include "xil_assert.h" -#include "xil_exception.h" -#include "xil_types.h" - -#endif - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_io.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_io.c deleted file mode 100644 index a091b232e10b78815cdc8c8168afabac4d0c4e6f..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_io.c +++ /dev/null @@ -1,350 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -*******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_io.c -* -* Contains I/O functions for memory-mapped or non-memory-mapped I/O -* architectures. These functions encapsulate Cortex A9 architecture-specific -* I/O requirements. -* -* @note -* -* This file contains architecture-dependent code. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- -------- -------- ----------------------------------------------- -* 1.00a ecm/sdm 10/24/09 First release -* 3.06a sgd 05/15/12 Pointer volatile used for the all read functions -* 3.07a sgd 08/17/12 Removed barriers (SYNCHRONIZE_IO) calls. -* 3.09a sgd 02/05/13 Comments cleanup -* </pre> -******************************************************************************/ - - -/***************************** Include Files *********************************/ -#include "xil_io.h" -#include "xil_types.h" -#include "xil_assert.h" -#include "xpseudo_asm.h" -#include "xreg_cortexa9.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/*****************************************************************************/ -/** -* -* Performs an input operation for an 8-bit memory location by reading from the -* specified address and returning the Value read from that address. -* -* @param Addr contains the address to perform the input operation -* at. -* -* @return The Value read from the specified input address. -* -* @note None. -* -******************************************************************************/ -u8 Xil_In8(u32 Addr) -{ - return *(volatile u8 *) Addr; -} - -/*****************************************************************************/ -/** -* -* Performs an input operation for a 16-bit memory location by reading from the -* specified address and returning the Value read from that address. -* -* @param Addr contains the address to perform the input operation -* at. -* -* @return The Value read from the specified input address. -* -* @note None. -* -******************************************************************************/ -u16 Xil_In16(u32 Addr) -{ - return *(volatile u16 *) Addr; -} - -/*****************************************************************************/ -/** -* -* Performs an input operation for a 32-bit memory location by reading from the -* specified address and returning the Value read from that address. -* -* @param Addr contains the address to perform the input operation -* at. -* -* @return The Value read from the specified input address. -* -* @note None. -* -******************************************************************************/ -u32 Xil_In32(u32 Addr) -{ - return *(volatile u32 *) Addr; -} - -/*****************************************************************************/ -/** -* -* Performs an output operation for an 8-bit memory location by writing the -* specified Value to the the specified address. -* -* @param OutAddress contains the address to perform the output operation -* at. -* @param Value contains the Value to be output at the specified address. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void Xil_Out8(u32 OutAddress, u8 Value) -{ - *(volatile u8 *) OutAddress = Value; -} - -/*****************************************************************************/ -/** -* -* Performs an output operation for a 16-bit memory location by writing the -* specified Value to the the specified address. -* -* @param OutAddress contains the address to perform the output operation -* at. -* @param Value contains the Value to be output at the specified address. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void Xil_Out16(u32 OutAddress, u16 Value) -{ - *(volatile u16 *) OutAddress = Value; -} - -/*****************************************************************************/ -/** -* -* Performs an output operation for a 32-bit memory location by writing the -* specified Value to the the specified address. -* -* @param OutAddress contains the address to perform the output operation -* at. -* @param Value contains the Value to be output at the specified address. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void Xil_Out32(u32 OutAddress, u32 Value) -{ - *(volatile u32 *) OutAddress = Value; -} - -/*****************************************************************************/ -/** -* -* Performs an input operation for a 16-bit memory location by reading from the -* specified address and returning the byte-swapped Value read from that -* address. -* -* @param Addr contains the address to perform the input operation -* at. -* -* @return The byte-swapped Value read from the specified input address. -* -* @note None. -* -******************************************************************************/ -u16 Xil_In16BE(u32 Addr) -{ - u16 temp; - u16 result; - - temp = Xil_In16(Addr); - - result = Xil_EndianSwap16(temp); - - return result; -} - -/*****************************************************************************/ -/** -* -* Performs an input operation for a 32-bit memory location by reading from the -* specified address and returning the byte-swapped Value read from that -* address. -* -* @param Addr contains the address to perform the input operation -* at. -* -* @return The byte-swapped Value read from the specified input address. -* -* @note None. -* -******************************************************************************/ -u32 Xil_In32BE(u32 Addr) -{ - u32 temp; - u32 result; - - temp = Xil_In32(Addr); - - result = Xil_EndianSwap32(temp); - - return result; -} - -/*****************************************************************************/ -/** -* -* Performs an output operation for a 16-bit memory location by writing the -* specified Value to the the specified address. The Value is byte-swapped -* before being written. -* -* @param OutAddress contains the address to perform the output operation -* at. -* @param Value contains the Value to be output at the specified address. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void Xil_Out16BE(u32 OutAddress, u16 Value) -{ - u16 temp; - - temp = Xil_EndianSwap16(Value); - - Xil_Out16(OutAddress, temp); -} - -/*****************************************************************************/ -/** -* -* Performs an output operation for a 32-bit memory location by writing the -* specified Value to the the specified address. The Value is byte-swapped -* before being written. -* -* @param OutAddress contains the address to perform the output operation -* at. -* @param Value contains the Value to be output at the specified address. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void Xil_Out32BE(u32 OutAddress, u32 Value) -{ - u32 temp; - - temp = Xil_EndianSwap32(Value); - - Xil_Out32(OutAddress, temp); -} - -/*****************************************************************************/ -/** -* -* Perform a 16-bit endian converion. -* -* @param Data contains the value to be converted. -* -* @return converted value. -* -* @note None. -* -******************************************************************************/ -u16 Xil_EndianSwap16(u16 Data) -{ - return (u16) (((Data & 0xFF00) >> 8) | ((Data & 0x00FF) << 8)); -} - -/*****************************************************************************/ -/** -* -* Perform a 32-bit endian converion. -* -* @param Data contains the value to be converted. -* -* @return converted value. -* -* @note None. -* -******************************************************************************/ -u32 Xil_EndianSwap32(u32 Data) -{ - u16 LoWord; - u16 HiWord; - - /* get each of the half words from the 32 bit word */ - - LoWord = (u16) (Data & 0x0000FFFF); - HiWord = (u16) ((Data & 0xFFFF0000) >> 16); - - /* byte swap each of the 16 bit half words */ - - LoWord = (((LoWord & 0xFF00) >> 8) | ((LoWord & 0x00FF) << 8)); - HiWord = (((HiWord & 0xFF00) >> 8) | ((HiWord & 0x00FF) << 8)); - - /* swap the half words before returning the value */ - - return (u32) ((LoWord << 16) | HiWord); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_io.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_io.h deleted file mode 100644 index 06e83bfa8f7988b01fbd9b3ed787e383a16a0dc3..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_io.h +++ /dev/null @@ -1,254 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_io.h -* -* This file contains the interface for the general IO component, which -* encapsulates the Input/Output functions for processors that do not -* require any special I/O handling. -* -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- -------- -------- ----------------------------------------------- -* 1.00a ecm/sdm 10/24/09 First release -* 1.00a sdm 07/21/10 Added Xil_Htonl/s, Xil_Ntohl/s -* 3.07a asa 08/31/12 Added xil_printf.h include -* 3.08a sgd 11/05/12 Reverted SYNC macros definitions -* </pre> -******************************************************************************/ - -#ifndef XIL_IO_H /* prevent circular inclusions */ -#define XIL_IO_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xpseudo_asm.h" -#include "xil_printf.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -#if defined __GNUC__ -# define SYNCHRONIZE_IO dmb() -# define INST_SYNC isb() -# define DATA_SYNC dsb() -#else -# define SYNCHRONIZE_IO -# define INST_SYNC -# define DATA_SYNC -#endif /* __GNUC__ */ - -/*****************************************************************************/ -/** -* -* Perform an big-endian input operation for a 16-bit memory location -* by reading from the specified address and returning the Value read from -* that address. -* -* @param Addr contains the address to perform the input operation at. -* -* @return The Value read from the specified input address with the -* proper endianness. The return Value has the same endianness -* as that of the processor, i.e. if the processor is -* little-engian, the return Value is the byte-swapped Value read -* from the address. -* -* @note None. -* -******************************************************************************/ -#define Xil_In16LE(Addr) Xil_In16(Addr) - -/*****************************************************************************/ -/** -* -* Perform a big-endian input operation for a 32-bit memory location -* by reading from the specified address and returning the Value read from -* that address. -* -* @param Addr contains the address to perform the input operation at. -* -* @return The Value read from the specified input address with the -* proper endianness. The return Value has the same endianness -* as that of the processor, i.e. if the processor is -* little-engian, the return Value is the byte-swapped Value read -* from the address. -* -* -* @note None. -* -******************************************************************************/ -#define Xil_In32LE(Addr) Xil_In32(Addr) - -/*****************************************************************************/ -/** -* -* Perform a big-endian output operation for a 16-bit memory location -* by writing the specified Value to the specified address. -* -* @param Addr contains the address to perform the output operation at. -* @param Value contains the Value to be output at the specified address. -* The Value has the same endianness as that of the processor. -* If the processor is little-endian, the byte-swapped Value is -* written to the address. -* -* -* @return None -* -* @note None. -* -******************************************************************************/ -#define Xil_Out16LE(Addr, Value) Xil_Out16(Addr, Value) - -/*****************************************************************************/ -/** -* -* Perform a big-endian output operation for a 32-bit memory location -* by writing the specified Value to the specified address. -* -* @param Addr contains the address to perform the output operation at. -* @param Value contains the Value to be output at the specified address. -* The Value has the same endianness as that of the processor. -* If the processor is little-endian, the byte-swapped Value is -* written to the address. -* -* @return None -* -* @note None. -* -******************************************************************************/ -#define Xil_Out32LE(Addr, Value) Xil_Out32(Addr, Value) - -/*****************************************************************************/ -/** -* -* Convert a 32-bit number from host byte order to network byte order. -* -* @param Data the 32-bit number to be converted. -* -* @return The converted 32-bit number in network byte order. -* -* @note None. -* -******************************************************************************/ -#define Xil_Htonl(Data) Xil_EndianSwap32(Data) - -/*****************************************************************************/ -/** -* -* Convert a 16-bit number from host byte order to network byte order. -* -* @param Data the 16-bit number to be converted. -* -* @return The converted 16-bit number in network byte order. -* -* @note None. -* -******************************************************************************/ -#define Xil_Htons(Data) Xil_EndianSwap16(Data) - -/*****************************************************************************/ -/** -* -* Convert a 32-bit number from network byte order to host byte order. -* -* @param Data the 32-bit number to be converted. -* -* @return The converted 32-bit number in host byte order. -* -* @note None. -* -******************************************************************************/ -#define Xil_Ntohl(Data) Xil_EndianSwap32(Data) - -/*****************************************************************************/ -/** -* -* Convert a 16-bit number from network byte order to host byte order. -* -* @param Data the 16-bit number to be converted. -* -* @return The converted 16-bit number in host byte order. -* -* @note None. -* -******************************************************************************/ -#define Xil_Ntohs(Data) Xil_EndianSwap16(Data) - -/************************** Function Prototypes ******************************/ - -/* The following functions allow the software to be transportable across - * processors which may use memory mapped I/O or I/O which is mapped into a - * seperate address space. - */ -u8 Xil_In8(u32 Addr); -u16 Xil_In16(u32 Addr); -u32 Xil_In32(u32 Addr); - -void Xil_Out8(u32 Addr, u8 Value); -void Xil_Out16(u32 Addr, u16 Value); -void Xil_Out32(u32 Addr, u32 Value); - -u16 Xil_In16BE(u32 Addr); -u32 Xil_In32BE(u32 Addr); -void Xil_Out16BE(u32 Addr, u16 Value); -void Xil_Out32BE(u32 Addr, u32 Value); - -u16 Xil_EndianSwap16(u16 Data); -u32 Xil_EndianSwap32(u32 Data); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_io.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_io.o deleted file mode 100644 index 3e99f45763724d540d9f1167d467719b90766594..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_io.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_macroback.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_macroback.h deleted file mode 100644 index c614daaf5ec1ec506ee5fa8f6aab2b2d95f2bc97..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_macroback.h +++ /dev/null @@ -1,1069 +0,0 @@ -/*********************************************************************/ -/** - * (c) Copyright 2010 Xilinx, Inc. All rights reserved. - * - * This file contains confidential and proprietary information - * of Xilinx, Inc. and is protected under U.S. and - * international copyright and other intellectual property - * laws. - * - * DISCLAIMER - * This disclaimer is not a license and does not grant any - * rights to the materials distributed herewith. Except as - * otherwise provided in a valid license issued to you by - * Xilinx, and to the maximum extent permitted by applicable - * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND - * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES - * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING - * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- - * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and - * (2) Xilinx shall not be liable (whether in contract or tort, - * including negligence, or under any other theory of - * liability) for any loss or damage of any kind or nature - * related to, arising under or in connection with these - * materials, including for any direct, or any indirect, - * special, incidental, or consequential loss or damage - * (including loss of data, profits, goodwill, or any type of - * loss or damage suffered as a result of any action brought - * by a third party) even if such damage or loss was - * reasonably foreseeable or Xilinx had been advised of the - * possibility of the same. - * - * CRITICAL APPLICATIONS - * Xilinx products are not designed or intended to be fail- - * safe, or for use in any application requiring fail-safe - * performance, such as life-support or safety devices or - * systems, Class III medical devices, nuclear facilities, - * applications related to the deployment of airbags, or any - * other applications that could lead to death, personal - * injury, or severe property or environmental damage - * (individually and collectively, "Critical - * Applications"). Customer assumes the sole risk and - * liability of any use of Xilinx products in Critical - * Applications, subject only to applicable laws and - * regulations governing limitations on product liability. - * - * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS - * PART OF THIS FILE AT ALL TIMES. - *********************************************************************/ - -/*********************************************************************/ -/** - * @file xil_macroback.h - * - * This header file is meant to bring back the removed _m macros. - * This header file must be included last. - * The following macros are not defined here due to the driver change: - * XGpio_mSetDataDirection - * XGpio_mGetDataReg - * XGpio_mSetDataReg - * XIIC_RESET - * XIIC_CLEAR_STATS - * XSpi_mReset - * XSysAce_mSetCfgAddr - * XSysAce_mIsCfgDone - * XTft_mSetPixel - * XTft_mGetPixel - * XWdtTb_mEnableWdt - * XWdtTb_mDisbleWdt - * XWdtTb_mRestartWdt - * XWdtTb_mGetTimebaseReg - * XWdtTb_mHasReset - * - * Please refer the corresonding driver document for replacement. - * - *********************************************************************/ - -#ifndef XIL_MACROBACK_H -#define XIL_MACROBACK_H - -/*********************************************************************/ -/** - * Macros for Driver XCan - * - *********************************************************************/ -#ifndef XCan_mReadReg -#define XCan_mReadReg XCan_ReadReg -#endif - -#ifndef XCan_mWriteReg -#define XCan_mWriteReg XCan_WriteReg -#endif - -#ifndef XCan_mIsTxDone -#define XCan_mIsTxDone XCan_IsTxDone -#endif - -#ifndef XCan_mIsTxFifoFull -#define XCan_mIsTxFifoFull XCan_IsTxFifoFull -#endif - -#ifndef XCan_mIsHighPriorityBufFull -#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull -#endif - -#ifndef XCan_mIsRxEmpty -#define XCan_mIsRxEmpty XCan_IsRxEmpty -#endif - -#ifndef XCan_mIsAcceptFilterBusy -#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy -#endif - -#ifndef XCan_mCreateIdValue -#define XCan_mCreateIdValue XCan_CreateIdValue -#endif - -#ifndef XCan_mCreateDlcValue -#define XCan_mCreateDlcValue XCan_CreateDlcValue -#endif - -/*********************************************************************/ -/** - * Macros for Driver XDmaCentral - * - *********************************************************************/ -#ifndef XDmaCentral_mWriteReg -#define XDmaCentral_mWriteReg XDmaCentral_WriteReg -#endif - -#ifndef XDmaCentral_mReadReg -#define XDmaCentral_mReadReg XDmaCentral_ReadReg -#endif - -/*********************************************************************/ -/** - * Macros for Driver XDsAdc - * - *********************************************************************/ -#ifndef XDsAdc_mWriteReg -#define XDsAdc_mWriteReg XDsAdc_WriteReg -#endif - -#ifndef XDsAdc_mReadReg -#define XDsAdc_mReadReg XDsAdc_ReadReg -#endif - -#ifndef XDsAdc_mIsEmpty -#define XDsAdc_mIsEmpty XDsAdc_IsEmpty -#endif - -#ifndef XDsAdc_mSetFstmReg -#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg -#endif - -#ifndef XDsAdc_mGetFstmReg -#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg -#endif - -#ifndef XDsAdc_mEnableConversion -#define XDsAdc_mEnableConversion XDsAdc_EnableConversion -#endif - -#ifndef XDsAdc_mDisableConversion -#define XDsAdc_mDisableConversion XDsAdc_DisableConversion -#endif - -#ifndef XDsAdc_mGetFifoOccyReg -#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg -#endif - -/*********************************************************************/ -/** - * Macros for Driver XDsDac - * - *********************************************************************/ -#ifndef XDsDac_mWriteReg -#define XDsDac_mWriteReg XDsDac_WriteReg -#endif - -#ifndef XDsDac_mReadReg -#define XDsDac_mReadReg XDsDac_ReadReg -#endif - -#ifndef XDsDac_mIsEmpty -#define XDsDac_mIsEmpty XDsDac_IsEmpty -#endif - -#ifndef XDsDac_mFifoIsFull -#define XDsDac_mFifoIsFull XDsDac_FifoIsFull -#endif - -#ifndef XDsDac_mGetVacancy -#define XDsDac_mGetVacancy XDsDac_GetVacancy -#endif - -/*********************************************************************/ -/** - * Macros for Driver XEmacLite - * - *********************************************************************/ -#ifndef XEmacLite_mReadReg -#define XEmacLite_mReadReg XEmacLite_ReadReg -#endif - -#ifndef XEmacLite_mWriteReg -#define XEmacLite_mWriteReg XEmacLite_WriteReg -#endif - -#ifndef XEmacLite_mGetTxStatus -#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus -#endif - -#ifndef XEmacLite_mSetTxStatus -#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus -#endif - -#ifndef XEmacLite_mGetRxStatus -#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus -#endif - -#ifndef XEmacLite_mSetRxStatus -#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus -#endif - -#ifndef XEmacLite_mIsTxDone -#define XEmacLite_mIsTxDone XEmacLite_IsTxDone -#endif - -#ifndef XEmacLite_mIsRxEmpty -#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty -#endif - -#ifndef XEmacLite_mNextTransmitAddr -#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr -#endif - -#ifndef XEmacLite_mNextReceiveAddr -#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr -#endif - -#ifndef XEmacLite_mIsMdioConfigured -#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured -#endif - -#ifndef XEmacLite_mIsLoopbackConfigured -#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured -#endif - -#ifndef XEmacLite_mGetReceiveDataLength -#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength -#endif - -#ifndef XEmacLite_mGetTxActive -#define XEmacLite_mGetTxActive XEmacLite_GetTxActive -#endif - -#ifndef XEmacLite_mSetTxActive -#define XEmacLite_mSetTxActive XEmacLite_SetTxActive -#endif - -/*********************************************************************/ -/** - * Macros for Driver XGpio - * - *********************************************************************/ -#ifndef XGpio_mWriteReg -#define XGpio_mWriteReg XGpio_WriteReg -#endif - -#ifndef XGpio_mReadReg -#define XGpio_mReadReg XGpio_ReadReg -#endif - -/*********************************************************************/ -/** - * Macros for Driver XHwIcap - * - *********************************************************************/ -#ifndef XHwIcap_mFifoWrite -#define XHwIcap_mFifoWrite XHwIcap_FifoWrite -#endif - -#ifndef XHwIcap_mFifoRead -#define XHwIcap_mFifoRead XHwIcap_FifoRead -#endif - -#ifndef XHwIcap_mSetSizeReg -#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg -#endif - -#ifndef XHwIcap_mGetControlReg -#define XHwIcap_mGetControlReg XHwIcap_GetControlReg -#endif - -#ifndef XHwIcap_mStartConfig -#define XHwIcap_mStartConfig XHwIcap_StartConfig -#endif - -#ifndef XHwIcap_mStartReadBack -#define XHwIcap_mStartReadBack XHwIcap_StartReadBack -#endif - -#ifndef XHwIcap_mGetStatusReg -#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg -#endif - -#ifndef XHwIcap_mIsTransferDone -#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone -#endif - -#ifndef XHwIcap_mIsDeviceBusy -#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy -#endif - -#ifndef XHwIcap_mIntrGlobalEnable -#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable -#endif - -#ifndef XHwIcap_mIntrGlobalDisable -#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable -#endif - -#ifndef XHwIcap_mIntrGetStatus -#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus -#endif - -#ifndef XHwIcap_mIntrDisable -#define XHwIcap_mIntrDisable XHwIcap_IntrDisable -#endif - -#ifndef XHwIcap_mIntrEnable -#define XHwIcap_mIntrEnable XHwIcap_IntrEnable -#endif - -#ifndef XHwIcap_mIntrGetEnabled -#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled -#endif - -#ifndef XHwIcap_mIntrClear -#define XHwIcap_mIntrClear XHwIcap_IntrClear -#endif - -#ifndef XHwIcap_mGetWrFifoVacancy -#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy -#endif - -#ifndef XHwIcap_mGetRdFifoOccupancy -#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy -#endif - -#ifndef XHwIcap_mSliceX2Col -#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col -#endif - -#ifndef XHwIcap_mSliceY2Row -#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row -#endif - -#ifndef XHwIcap_mSliceXY2Slice -#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice -#endif - -#ifndef XHwIcap_mReadReg -#define XHwIcap_mReadReg XHwIcap_ReadReg -#endif - -#ifndef XHwIcap_mWriteReg -#define XHwIcap_mWriteReg XHwIcap_WriteReg -#endif - -/*********************************************************************/ -/** - * Macros for Driver XIic - * - *********************************************************************/ -#ifndef XIic_mReadReg -#define XIic_mReadReg XIic_ReadReg -#endif - -#ifndef XIic_mWriteReg -#define XIic_mWriteReg XIic_WriteReg -#endif - -#ifndef XIic_mEnterCriticalRegion -#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable -#endif - -#ifndef XIic_mExitCriticalRegion -#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable -#endif - -#ifndef XIIC_GINTR_DISABLE -#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable -#endif - -#ifndef XIIC_GINTR_ENABLE -#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable -#endif - -#ifndef XIIC_IS_GINTR_ENABLED -#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled -#endif - -#ifndef XIIC_WRITE_IISR -#define XIIC_WRITE_IISR XIic_WriteIisr -#endif - -#ifndef XIIC_READ_IISR -#define XIIC_READ_IISR XIic_ReadIisr -#endif - -#ifndef XIIC_WRITE_IIER -#define XIIC_WRITE_IIER XIic_WriteIier -#endif - -#ifndef XIic_mClearIisr -#define XIic_mClearIisr XIic_ClearIisr -#endif - -#ifndef XIic_mSend7BitAddress -#define XIic_mSend7BitAddress XIic_Send7BitAddress -#endif - -#ifndef XIic_mDynSend7BitAddress -#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress -#endif - -#ifndef XIic_mDynSendStartStopAddress -#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress -#endif - -#ifndef XIic_mDynSendStop -#define XIic_mDynSendStop XIic_DynSendStop -#endif - -#ifndef XIic_mSend10BitAddrByte1 -#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1 -#endif - -#ifndef XIic_mSend10BitAddrByte2 -#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2 -#endif - -#ifndef XIic_mSend7BitAddr -#define XIic_mSend7BitAddr XIic_Send7BitAddr -#endif - -#ifndef XIic_mDisableIntr -#define XIic_mDisableIntr XIic_DisableIntr -#endif - -#ifndef XIic_mEnableIntr -#define XIic_mEnableIntr XIic_EnableIntr -#endif - -#ifndef XIic_mClearIntr -#define XIic_mClearIntr XIic_ClearIntr -#endif - -#ifndef XIic_mClearEnableIntr -#define XIic_mClearEnableIntr XIic_ClearEnableIntr -#endif - -#ifndef XIic_mFlushRxFifo -#define XIic_mFlushRxFifo XIic_FlushRxFifo -#endif - -#ifndef XIic_mFlushTxFifo -#define XIic_mFlushTxFifo XIic_FlushTxFifo -#endif - -#ifndef XIic_mReadRecvByte -#define XIic_mReadRecvByte XIic_ReadRecvByte -#endif - -#ifndef XIic_mWriteSendByte -#define XIic_mWriteSendByte XIic_WriteSendByte -#endif - -#ifndef XIic_mSetControlRegister -#define XIic_mSetControlRegister XIic_SetControlRegister -#endif - -/*********************************************************************/ -/** - * Macros for Driver XIntc - * - *********************************************************************/ -#ifndef XIntc_mMasterEnable -#define XIntc_mMasterEnable XIntc_MasterEnable -#endif - -#ifndef XIntc_mMasterDisable -#define XIntc_mMasterDisable XIntc_MasterDisable -#endif - -#ifndef XIntc_mEnableIntr -#define XIntc_mEnableIntr XIntc_EnableIntr -#endif - -#ifndef XIntc_mDisableIntr -#define XIntc_mDisableIntr XIntc_DisableIntr -#endif - -#ifndef XIntc_mAckIntr -#define XIntc_mAckIntr XIntc_AckIntr -#endif - -#ifndef XIntc_mGetIntrStatus -#define XIntc_mGetIntrStatus XIntc_GetIntrStatus -#endif - -/*********************************************************************/ -/** - * Macros for Driver XLlDma - * - *********************************************************************/ -#ifndef XLlDma_mBdRead -#define XLlDma_mBdRead XLlDma_BdRead -#endif - -#ifndef XLlDma_mBdWrite -#define XLlDma_mBdWrite XLlDma_BdWrite -#endif - -#ifndef XLlDma_mWriteReg -#define XLlDma_mWriteReg XLlDma_WriteReg -#endif - -#ifndef XLlDma_mReadReg -#define XLlDma_mReadReg XLlDma_ReadReg -#endif - -#ifndef XLlDma_mBdClear -#define XLlDma_mBdClear XLlDma_BdClear -#endif - -#ifndef XLlDma_mBdSetStsCtrl -#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl -#endif - -#ifndef XLlDma_mBdGetStsCtrl -#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl -#endif - -#ifndef XLlDma_mBdSetLength -#define XLlDma_mBdSetLength XLlDma_BdSetLength -#endif - -#ifndef XLlDma_mBdGetLength -#define XLlDma_mBdGetLength XLlDma_BdGetLength -#endif - -#ifndef XLlDma_mBdSetId -#define XLlDma_mBdSetId XLlDma_BdSetId -#endif - -#ifndef XLlDma_mBdGetId -#define XLlDma_mBdGetId XLlDma_BdGetId -#endif - -#ifndef XLlDma_mBdSetBufAddr -#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr -#endif - -#ifndef XLlDma_mBdGetBufAddr -#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr -#endif - -#ifndef XLlDma_mBdGetLength -#define XLlDma_mBdGetLength XLlDma_BdGetLength -#endif - -#ifndef XLlDma_mGetTxRing -#define XLlDma_mGetTxRing XLlDma_GetTxRing -#endif - -#ifndef XLlDma_mGetRxRing -#define XLlDma_mGetRxRing XLlDma_GetRxRing -#endif - -#ifndef XLlDma_mGetCr -#define XLlDma_mGetCr XLlDma_GetCr -#endif - -#ifndef XLlDma_mSetCr -#define XLlDma_mSetCr XLlDma_SetCr -#endif - -#ifndef XLlDma_mBdRingCntCalc -#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc -#endif - -#ifndef XLlDma_mBdRingMemCalc -#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc -#endif - -#ifndef XLlDma_mBdRingGetCnt -#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt -#endif - -#ifndef XLlDma_mBdRingGetFreeCnt -#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt -#endif - -#ifndef XLlDma_mBdRingSnapShotCurrBd -#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd -#endif - -#ifndef XLlDma_mBdRingNext -#define XLlDma_mBdRingNext XLlDma_BdRingNext -#endif - -#ifndef XLlDma_mBdRingPrev -#define XLlDma_mBdRingPrev XLlDma_BdRingPrev -#endif - -#ifndef XLlDma_mBdRingGetSr -#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr -#endif - -#ifndef XLlDma_mBdRingSetSr -#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr -#endif - -#ifndef XLlDma_mBdRingGetCr -#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr -#endif - -#ifndef XLlDma_mBdRingSetCr -#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr -#endif - -#ifndef XLlDma_mBdRingBusy -#define XLlDma_mBdRingBusy XLlDma_BdRingBusy -#endif - -#ifndef XLlDma_mBdRingIntEnable -#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable -#endif - -#ifndef XLlDma_mBdRingIntDisable -#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable -#endif - -#ifndef XLlDma_mBdRingIntGetEnabled -#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled -#endif - -#ifndef XLlDma_mBdRingGetIrq -#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq -#endif - -#ifndef XLlDma_mBdRingAckIrq -#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq -#endif - -/*********************************************************************/ -/** - * Macros for Driver XMbox - * - *********************************************************************/ -#ifndef XMbox_mWriteReg -#define XMbox_mWriteReg XMbox_WriteReg -#endif - -#ifndef XMbox_mReadReg -#define XMbox_mReadReg XMbox_ReadReg -#endif - -#ifndef XMbox_mWriteMBox -#define XMbox_mWriteMBox XMbox_WriteMBox -#endif - -#ifndef XMbox_mReadMBox -#define XMbox_mReadMBox XMbox_ReadMBox -#endif - -#ifndef XMbox_mFSLReadMBox -#define XMbox_mFSLReadMBox XMbox_FSLReadMBox -#endif - -#ifndef XMbox_mFSLWriteMBox -#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox -#endif - -#ifndef XMbox_mFSLIsEmpty -#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty -#endif - -#ifndef XMbox_mFSLIsFull -#define XMbox_mFSLIsFull XMbox_FSLIsFull -#endif - -#ifndef XMbox_mIsEmpty -#define XMbox_mIsEmpty XMbox_IsEmptyHw -#endif - -#ifndef XMbox_mIsFull -#define XMbox_mIsFull XMbox_IsFullHw -#endif - -/*********************************************************************/ -/** - * Macros for Driver XMpmc - * - *********************************************************************/ -#ifndef XMpmc_mReadReg -#define XMpmc_mReadReg XMpmc_ReadReg -#endif - -#ifndef XMpmc_mWriteReg -#define XMpmc_mWriteReg XMpmc_WriteReg -#endif - -/*********************************************************************/ -/** - * Macros for Driver XMutex - * - *********************************************************************/ -#ifndef XMutex_mWriteReg -#define XMutex_mWriteReg XMutex_WriteReg -#endif - -#ifndef XMutex_mReadReg -#define XMutex_mReadReg XMutex_ReadReg -#endif - -/*********************************************************************/ -/** - * Macros for Driver XPcie - * - *********************************************************************/ -#ifndef XPcie_mReadReg -#define XPcie_mReadReg XPcie_ReadReg -#endif - -#ifndef XPcie_mWriteReg -#define XPcie_mWriteReg XPcie_WriteReg -#endif - -/*********************************************************************/ -/** - * Macros for Driver XSpi - * - *********************************************************************/ -#ifndef XSpi_mIntrGlobalEnable -#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable -#endif - -#ifndef XSpi_mIntrGlobalDisable -#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable -#endif - -#ifndef XSpi_mIsIntrGlobalEnabled -#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled -#endif - -#ifndef XSpi_mIntrGetStatus -#define XSpi_mIntrGetStatus XSpi_IntrGetStatus -#endif - -#ifndef XSpi_mIntrClear -#define XSpi_mIntrClear XSpi_IntrClear -#endif - -#ifndef XSpi_mIntrEnable -#define XSpi_mIntrEnable XSpi_IntrEnable -#endif - -#ifndef XSpi_mIntrDisable -#define XSpi_mIntrDisable XSpi_IntrDisable -#endif - -#ifndef XSpi_mIntrGetEnabled -#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled -#endif - -#ifndef XSpi_mSetControlReg -#define XSpi_mSetControlReg XSpi_SetControlReg -#endif - -#ifndef XSpi_mGetControlReg -#define XSpi_mGetControlReg XSpi_GetControlReg -#endif - -#ifndef XSpi_mGetStatusReg -#define XSpi_mGetStatusReg XSpi_GetStatusReg -#endif - -#ifndef XSpi_mSetSlaveSelectReg -#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg -#endif - -#ifndef XSpi_mGetSlaveSelectReg -#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg -#endif - -#ifndef XSpi_mEnable -#define XSpi_mEnable XSpi_Enable -#endif - -#ifndef XSpi_mDisable -#define XSpi_mDisable XSpi_Disable -#endif - -/*********************************************************************/ -/** - * Macros for Driver XSysAce - * - *********************************************************************/ -#ifndef XSysAce_mGetControlReg -#define XSysAce_mGetControlReg XSysAce_GetControlReg -#endif - -#ifndef XSysAce_mSetControlReg -#define XSysAce_mSetControlReg XSysAce_SetControlReg -#endif - -#ifndef XSysAce_mOrControlReg -#define XSysAce_mOrControlReg XSysAce_OrControlReg -#endif - -#ifndef XSysAce_mAndControlReg -#define XSysAce_mAndControlReg XSysAce_AndControlReg -#endif - -#ifndef XSysAce_mGetErrorReg -#define XSysAce_mGetErrorReg XSysAce_GetErrorReg -#endif - -#ifndef XSysAce_mGetStatusReg -#define XSysAce_mGetStatusReg XSysAce_GetStatusReg -#endif - -#ifndef XSysAce_mWaitForLock -#define XSysAce_mWaitForLock XSysAce_WaitForLock -#endif - -#ifndef XSysAce_mEnableIntr -#define XSysAce_mEnableIntr XSysAce_EnableIntr -#endif - -#ifndef XSysAce_mDisableIntr -#define XSysAce_mDisableIntr XSysAce_DisableIntr -#endif - -#ifndef XSysAce_mIsReadyForCmd -#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd -#endif - -#ifndef XSysAce_mIsMpuLocked -#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked -#endif - -#ifndef XSysAce_mIsIntrEnabled -#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled -#endif - -/*********************************************************************/ -/** - * Macros for Driver XSysMon - * - *********************************************************************/ -#ifndef XSysMon_mIsEventSamplingModeSet -#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet -#endif - -#ifndef XSysMon_mIsDrpBusy -#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy -#endif - -#ifndef XSysMon_mIsDrpLocked -#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked -#endif - -#ifndef XSysMon_mRawToTemperature -#define XSysMon_mRawToTemperature XSysMon_RawToTemperature -#endif - -#ifndef XSysMon_mRawToVoltage -#define XSysMon_mRawToVoltage XSysMon_RawToVoltage -#endif - -#ifndef XSysMon_mTemperatureToRaw -#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw -#endif - -#ifndef XSysMon_mVoltageToRaw -#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw -#endif - -#ifndef XSysMon_mReadReg -#define XSysMon_mReadReg XSysMon_ReadReg -#endif - -#ifndef XSysMon_mWriteReg -#define XSysMon_mWriteReg XSysMon_WriteReg -#endif - -/*********************************************************************/ -/** - * Macros for Driver XTmrCtr - * - *********************************************************************/ -#ifndef XTimerCtr_mReadReg -#define XTimerCtr_mReadReg XTimerCtr_ReadReg -#endif - -#ifndef XTmrCtr_mWriteReg -#define XTmrCtr_mWriteReg XTmrCtr_WriteReg -#endif - -#ifndef XTmrCtr_mSetControlStatusReg -#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg -#endif - -#ifndef XTmrCtr_mGetControlStatusReg -#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg -#endif - -#ifndef XTmrCtr_mGetTimerCounterReg -#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg -#endif - -#ifndef XTmrCtr_mSetLoadReg -#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg -#endif - -#ifndef XTmrCtr_mGetLoadReg -#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg -#endif - -#ifndef XTmrCtr_mEnable -#define XTmrCtr_mEnable XTmrCtr_Enable -#endif - -#ifndef XTmrCtr_mDisable -#define XTmrCtr_mDisable XTmrCtr_Disable -#endif - -#ifndef XTmrCtr_mEnableIntr -#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr -#endif - -#ifndef XTmrCtr_mDisableIntr -#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr -#endif - -#ifndef XTmrCtr_mLoadTimerCounterReg -#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg -#endif - -#ifndef XTmrCtr_mHasEventOccurred -#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred -#endif - -/*********************************************************************/ -/** - * Macros for Driver XUartLite - * - *********************************************************************/ -#ifndef XUartLite_mUpdateStats -#define XUartLite_mUpdateStats XUartLite_UpdateStats -#endif - -#ifndef XUartLite_mWriteReg -#define XUartLite_mWriteReg XUartLite_WriteReg -#endif - -#ifndef XUartLite_mReadReg -#define XUartLite_mReadReg XUartLite_ReadReg -#endif - -#ifndef XUartLite_mClearStats -#define XUartLite_mClearStats XUartLite_ClearStats -#endif - -#ifndef XUartLite_mSetControlReg -#define XUartLite_mSetControlReg XUartLite_SetControlReg -#endif - -#ifndef XUartLite_mGetStatusReg -#define XUartLite_mGetStatusReg XUartLite_GetStatusReg -#endif - -#ifndef XUartLite_mIsReceiveEmpty -#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty -#endif - -#ifndef XUartLite_mIsTransmitFull -#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull -#endif - -#ifndef XUartLite_mIsIntrEnabled -#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled -#endif - -#ifndef XUartLite_mEnableIntr -#define XUartLite_mEnableIntr XUartLite_EnableIntr -#endif - -#ifndef XUartLite_mDisableIntr -#define XUartLite_mDisableIntr XUartLite_DisableIntr -#endif - -/*********************************************************************/ -/** - * Macros for Driver XUartNs550 - * - *********************************************************************/ -#ifndef XUartNs550_mUpdateStats -#define XUartNs550_mUpdateStats XUartNs550_UpdateStats -#endif - -#ifndef XUartNs550_mReadReg -#define XUartNs550_mReadReg XUartNs550_ReadReg -#endif - -#ifndef XUartNs550_mWriteReg -#define XUartNs550_mWriteReg XUartNs550_WriteReg -#endif - -#ifndef XUartNs550_mClearStats -#define XUartNs550_mClearStats XUartNs550_ClearStats -#endif - -#ifndef XUartNs550_mGetLineStatusReg -#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg -#endif - -#ifndef XUartNs550_mGetLineControlReg -#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg -#endif - -#ifndef XUartNs550_mSetLineControlReg -#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg -#endif - -#ifndef XUartNs550_mEnableIntr -#define XUartNs550_mEnableIntr XUartNs550_EnableIntr -#endif - -#ifndef XUartNs550_mDisableIntr -#define XUartNs550_mDisableIntr XUartNs550_DisableIntr -#endif - -#ifndef XUartNs550_mIsReceiveData -#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData -#endif - -#ifndef XUartNs550_mIsTransmitEmpty -#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty -#endif - -/*********************************************************************/ -/** - * Macros for Driver XUsb - * - *********************************************************************/ -#ifndef XUsb_mReadReg -#define XUsb_mReadReg XUsb_ReadReg -#endif - -#ifndef XUsb_mWriteReg -#define XUsb_mWriteReg XUsb_WriteReg -#endif - -#endif diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_misc_psreset_api.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_misc_psreset_api.c deleted file mode 100644 index d1054692edf67a2545bb4f165920302d20ffc9fb..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_misc_psreset_api.c +++ /dev/null @@ -1,531 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_misc_reset.c -* -* This file contains the implementation of the reset sequence for various -* zynq ps devices like DDR,OCM,Slcr,Ethernet,Usb.. controllers. The reset -* sequence provided to the interfaces is based on the provision in -* slcr reset functional blcok. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.00b kpc 03/07/13 First release -* </pre> -* -******************************************************************************/ - - -/***************************** Include Files *********************************/ -#include "xil_misc_psreset_api.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - - -/*****************************************************************************/ -/** -* This function contains the implementation for ddr reset. -* -* @param N/A. -* -* @return N/A. -* -* @note None. -* -******************************************************************************/ -void XDdr_ResetHw() -{ - u32 RegVal; - - /* Unlock the slcr register access lock */ - Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); - /* Assert and deassert the ddr softreset bit */ - RegVal = Xil_In32(XDDRC_CTRL_BASEADDR); - RegVal &= ~XDDRPS_CTRL_RESET_MASK; - Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal); - RegVal |= XDDRPS_CTRL_RESET_MASK; - Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal); - -} - -/*****************************************************************************/ -/** -* This function contains the implementation for remapping the ocm memory region -* -* @param N/A. -* -* @return N/A. -* -* @note None. -* -******************************************************************************/ -void XOcm_Remap() -{ - u32 RegVal; - - /* Unlock the slcr register access lock */ - Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); - /* Map the ocm region to postbootrom state */ - RegVal = Xil_In32(XSLCR_OCM_CFG_ADDR); - RegVal = (RegVal & ~XSLCR_OCM_CFG_HIADDR_MASK) | XSLCR_OCM_CFG_RESETVAL; - Xil_Out32(XSLCR_OCM_CFG_ADDR, RegVal); -} - -/*****************************************************************************/ -/** -* This function contains the implementation for SMC reset sequence -* -* @param BaseAddress of the interface -* -* @return N/A. -* -* @note None. -* -******************************************************************************/ -void XSmc_ResetHw(u32 BaseAddress) -{ - u32 RegVal; - - /* Clear the interuupts */ - RegVal = Xil_In32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET); - RegVal = RegVal | XSMC_MEMC_CLR_CONFIG_MASK; - Xil_Out32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET, RegVal); - /* Clear the idle counter registers */ - Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_0_OFFSET, 0x0); - Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_1_OFFSET, 0x0); - /* Update the ecc registers with reset values */ - Xil_Out32(BaseAddress + XSMC_ECC_MEMCFG1_OFFSET, - XSMC_ECC_MEMCFG1_RESET_VAL); - Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD1_OFFSET, - XSMC_ECC_MEMCMD1_RESET_VAL); - Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD2_OFFSET, - XSMC_ECC_MEMCMD2_RESET_VAL); - -} - -/*****************************************************************************/ -/** -* This function contains the implementation for updating the slcr mio registers -* with reset values -* @param N/A. -* -* @return N/A. -* -* @note None. -* -******************************************************************************/ -void XSlcr_MioWriteResetValues() -{ - u32 i; - - /* Unlock the slcr register access lock */ - Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); - /* Update all the MIO registers with reset values */ - for (i=0; i<=1;i++); - { - Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4)), - XSLCR_MIO_PIN_00_RESET_VAL); - } - for (; i<=8;i++); - { - Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4)), - XSLCR_MIO_PIN_02_RESET_VAL); - } - for (; i<=53 ;i++); - { - Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4)), - XSLCR_MIO_PIN_00_RESET_VAL); - } - - -} - -/*****************************************************************************/ -/** -* This function contains the implementation for updating the slcr pll registers -* with reset values -* @param N/A. -* -* @return N/A. -* -* @note None. -* -******************************************************************************/ -void XSlcr_PllWriteResetValues() -{ - - /* Unlock the slcr register access lock */ - Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); - - /* update the pll control registers with reset values */ - Xil_Out32(XSLCR_IO_PLL_CTRL_ADDR, XSLCR_IO_PLL_CTRL_RESET_VAL); - Xil_Out32(XSLCR_ARM_PLL_CTRL_ADDR, XSLCR_ARM_PLL_CTRL_RESET_VAL); - Xil_Out32(XSLCR_DDR_PLL_CTRL_ADDR, XSLCR_DDR_PLL_CTRL_RESET_VAL); - /* update the pll config registers with reset values */ - Xil_Out32(XSLCR_IO_PLL_CFG_ADDR, XSLCR_IO_PLL_CFG_RESET_VAL); - Xil_Out32(XSLCR_ARM_PLL_CFG_ADDR, XSLCR_ARM_PLL_CFG_RESET_VAL); - Xil_Out32(XSLCR_DDR_PLL_CFG_ADDR, XSLCR_DDR_PLL_CFG_RESET_VAL); - /* update the clock control registers with reset values */ - Xil_Out32(XSLCR_ARM_CLK_CTRL_ADDR, XSLCR_ARM_CLK_CTRL_RESET_VAL); - Xil_Out32(XSLCR_DDR_CLK_CTRL_ADDR, XSLCR_DDR_CLK_CTRL_RESET_VAL); -} - -/*****************************************************************************/ -/** -* This function contains the implementation for disabling the level shifters -* -* @param N/A. -* -* @return N/A. -* -* @note None. -* -******************************************************************************/ -void XSlcr_DisableLevelShifters() -{ - u32 RegVal; - /* Unlock the slcr register access lock */ - Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); - /* Disable the level shifters */ - RegVal = Xil_In32(XSLCR_LVL_SHFTR_EN_ADDR); - RegVal = RegVal & ~XSLCR_LVL_SHFTR_EN_MASK; - Xil_Out32(XSLCR_LVL_SHFTR_EN_ADDR, RegVal); - -} -/*****************************************************************************/ -/** -* This function contains the implementation for OCM software reset from the -* slcr -* -* @param N/A. -* -* @return N/A. -* -* @note None. -* -******************************************************************************/ -void XSlcr_OcmReset(void) -{ - u32 RegVal; - /* Unlock the slcr register access lock */ - Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); - /* Assert the reset */ - RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_OCM_RST_CTRL_VAL; - Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal); - /* Release the reset */ - RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_OCM_RST_CTRL_VAL; - Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal); -} - -/*****************************************************************************/ -/** -* This function contains the implementation for Ethernet software reset from -* the slcr -* @param N/A. -* -* @return N/A. -* -* @note None. -* -******************************************************************************/ -void XSlcr_EmacPsReset(void) -{ - u32 RegVal; - /* Unlock the slcr register access lock */ - Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); - /* Assert the reset */ - RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_GEM_RST_CTRL_VAL; - Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal); - /* Release the reset */ - RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_GEM_RST_CTRL_VAL; - Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal); -} - -/*****************************************************************************/ -/** -* This function contains the implementation for USB software reset from the -* slcr -* -* @param N/A. -* -* @return N/A. -* -* @note None. -* -******************************************************************************/ -void XSlcr_UsbPsReset(void) -{ - u32 RegVal; - /* Unlock the slcr register access lock */ - Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); - /* Assert the reset */ - RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_USB_RST_CTRL_VAL; - Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal); - /* Release the reset */ - RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_USB_RST_CTRL_VAL; - Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal); -} -/*****************************************************************************/ -/** -* This function contains the implementation for QSPI software reset from the -* slcr -* -* @param N/A. -* -* @return N/A. -* -* @note None. -* -******************************************************************************/ -void XSlcr_QspiPsReset(void) -{ - u32 RegVal; - /* Unlock the slcr register access lock */ - Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); - /* Assert the reset */ - RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_QSPI_RST_CTRL_VAL; - Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal); - /* Release the reset */ - RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_QSPI_RST_CTRL_VAL; - Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal); -} -/*****************************************************************************/ -/** -* This function contains the implementation for SPI software reset from the -* slcr -* -* @param N/A. -* -* @return N/A. -* -* @note None. -* -******************************************************************************/ -void XSlcr_SpiPsReset(void) -{ - u32 RegVal; - /* Unlock the slcr register access lock */ - Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); - /* Assert the reset */ - RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_SPI_RST_CTRL_VAL; - Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal); - /* Release the reset */ - RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_SPI_RST_CTRL_VAL; - Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal); -} -/*****************************************************************************/ -/** -* This function contains the implementation for i2c software reset from the slcr -* -* @param N/A. -* -* @return N/A. -* -* @note None. -* -******************************************************************************/ -void XSlcr_I2cPsReset(void) -{ - u32 RegVal; - /* Unlock the slcr register access lock */ - Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); - /* Assert the reset */ - RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_I2C_RST_CTRL_VAL; - Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal); - /* Release the reset */ - RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_I2C_RST_CTRL_VAL; - Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal); -} -/*****************************************************************************/ -/** -* This function contains the implementation for UART software reset from the -* slcr -* -* @param N/A. -* -* @return N/A. -* -* @note None. -* -******************************************************************************/ -void XSlcr_UartPsReset(void) -{ - u32 RegVal; - /* Unlock the slcr register access lock */ - Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); - /* Assert the reset */ - RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_UART_RST_CTRL_VAL; - Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal); - /* Release the reset */ - RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_UART_RST_CTRL_VAL; - Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal); -} -/*****************************************************************************/ -/** -* This function contains the implementation for CAN software reset from slcr -* registers -* -* @param N/A. -* -* @return N/A. -* -* @note None. -* -******************************************************************************/ -void XSlcr_CanPsReset(void) -{ - u32 RegVal; - /* Unlock the slcr register access lock */ - Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); - /* Assert the reset */ - RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_CAN_RST_CTRL_VAL; - Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal); - /* Release the reset */ - RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_CAN_RST_CTRL_VAL; - Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal); -} -/*****************************************************************************/ -/** -* This function contains the implementation for SMC software reset from the slcr -* -* @param N/A. -* -* @return N/A. -* -* @note None. -* -******************************************************************************/ -void XSlcr_SmcPsReset(void) -{ - u32 RegVal; - /* Unlock the slcr register access lock */ - Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); - /* Assert the reset */ - RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_SMC_RST_CTRL_VAL; - Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal); - /* Release the reset */ - RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_SMC_RST_CTRL_VAL; - Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal); -} -/*****************************************************************************/ -/** -* This function contains the implementation for DMA controller software reset -* from the slcr -* -* @param N/A. -* -* @return N/A. -* -* @note None. -* -******************************************************************************/ -void XSlcr_DmaPsReset(void) -{ - u32 RegVal; - /* Unlock the slcr register access lock */ - Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); - /* Assert the reset */ - RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_DMAC_RST_CTRL_VAL; - Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal); - /* Release the reset */ - RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_DMAC_RST_CTRL_VAL; - Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal); -} -/*****************************************************************************/ -/** -* This function contains the implementation for Gpio AMBA software reset from -* the slcr -* -* @param N/A. -* -* @return N/A. -* -* @note None. -* -******************************************************************************/ -void XSlcr_GpioPsReset(void) -{ - u32 RegVal; - /* Unlock the slcr register access lock */ - Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); - /* Assert the reset */ - RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR); - RegVal = RegVal | XSLCR_GPIO_RST_CTRL_VAL; - Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal); - /* Release the reset */ - RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR); - RegVal = RegVal & ~XSLCR_GPIO_RST_CTRL_VAL; - Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal); -} \ No newline at end of file diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_misc_psreset_api.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_misc_psreset_api.h deleted file mode 100644 index d74906877a1a21cb21308cb48b631af5721dc4ce..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_misc_psreset_api.h +++ /dev/null @@ -1,286 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* @file xil_misc_psreset_api.h -* -* This file contains the various register defintions and function prototypes for -* implementing the reset functionality of zynq ps devices -* -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.00b kpc 03/07/13 First release. -* </pre> -* -******************************************************************************/ - -#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */ -#define XIL_MISC_RESET_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - - -/***************************** Include Files *********************************/ -#include "xil_types.h" -#include "xil_io.h" - -/************************** Constant Definitions *****************************/ -#define XDDRC_CTRL_BASEADDR 0xF8006000 -#define XSLCR_BASEADDR 0xF8000000 -/**< OCM configuration register */ -#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x910) -/**< SLCR unlock register */ -#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x8) -/**< SLCR GEM0 rx clock control register */ -#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x138) -/**< SLCR GEM1 rx clock control register */ -#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x13C) -/**< SLCR GEM0 clock control register */ -#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x140) -/**< SLCR GEM1 clock control register */ -#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x144) -/**< SLCR SMC clock control register */ -#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x148) -/**< SLCR GEM reset control register */ -#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x214) -/**< SLCR USB0 clock control register */ -#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x130) -/**< SLCR USB1 clock control register */ -#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x134) -/**< SLCR USB1 reset control register */ -#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x210) -/**< SLCR SMC reset control register */ -#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x234) -/**< SLCR Level shifter enable register */ -#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x900) -/**< SLCR ARM pll control register */ -#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x100) -/**< SLCR DDR pll control register */ -#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x104) -/**< SLCR IO pll control register */ -#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x108) -/**< SLCR ARM pll configuration register */ -#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x110) -/**< SLCR DDR pll configuration register */ -#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x114) -/**< SLCR IO pll configuration register */ -#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x118) -/**< SLCR ARM clock control register */ -#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x120) -/**< SLCR DDR clock control register */ -#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x124) -/**< SLCR MIO pin address register */ -#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x700) -/**< SLCR DMAC reset control address register */ -#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x20C) -/**< SLCR USB reset control address register */ -#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x210) -/**< SLCR GEM reset control address register */ -#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x214) -/**< SLCR SDIO reset control address register */ -#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x218) -/**< SLCR SPI reset control address register */ -#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x21C) -/**< SLCR CAN reset control address register */ -#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x220) -/**< SLCR I2C reset control address register */ -#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x224) -/**< SLCR UART reset control address register */ -#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x228) -/**< SLCR GPIO reset control address register */ -#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x22C) -/**< SLCR LQSPI reset control address register */ -#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x230) -/**< SLCR SMC reset control address register */ -#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x234) -/**< SLCR OCM reset control address register */ -#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x238) - -/**< SMC mem controller clear config register */ -#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0C -/**< SMC idlecount configuration register */ -#define XSMC_REFRESH_PERIOD_0_OFFSET 0x20 -#define XSMC_REFRESH_PERIOD_1_OFFSET 0x24 -/**< SMC ECC configuration register */ -#define XSMC_ECC_MEMCFG1_OFFSET 0x404 -/**< SMC ECC command 1 register */ -#define XSMC_ECC_MEMCMD1_OFFSET 0x404 -/**< SMC ECC command 2 register */ -#define XSMC_ECC_MEMCMD2_OFFSET 0x404 - -/**< SLCR unlock code */ -#define XSLCR_UNLOCK_CODE 0x0000DF0D - -/**< SMC mem clear configuration mask */ -#define XSMC_MEMC_CLR_CONFIG_MASK 0x5F -/**< SMC ECC memconfig 1 reset value */ -#define XSMC_ECC_MEMCFG1_RESET_VAL 0x43 -/**< SMC ECC memcommand 1 reset value */ -#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080 -/**< SMC ECC memcommand 2 reset value */ -#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585 - -/**< DDR controller reset bit mask */ -#define XDDRPS_CTRL_RESET_MASK 0x1 -/**< SLCR OCM configuration reset value*/ -#define XSLCR_OCM_CFG_RESETVAL 0x8 -/**< SLCR OCM bank selection mask*/ -#define XSLCR_OCM_CFG_HIADDR_MASK 0xF -/**< SLCR level shifter enable mask*/ -#define XSLCR_LVL_SHFTR_EN_MASK 0xF - -/**< SLCR PLL register reset values */ -#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008 -#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008 -#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008 -#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0 -#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0 -#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0 -#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400 -#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003 - -/**< SLCR MIO register default values */ -#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601 -#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601 - -/**< SLCR Reset control registers default values */ -#define XSLCR_DMAC_RST_CTRL_VAL 0x1 -#define XSLCR_GEM_RST_CTRL_VAL 0xF3 -#define XSLCR_USB_RST_CTRL_VAL 0x3 -#define XSLCR_I2C_RST_CTRL_VAL 0x3 -#define XSLCR_SPI_RST_CTRL_VAL 0xF -#define XSLCR_UART_RST_CTRL_VAL 0xF -#define XSLCR_QSPI_RST_CTRL_VAL 0x3 -#define XSLCR_GPIO_RST_CTRL_VAL 0x1 -#define XSLCR_SMC_RST_CTRL_VAL 0x3 -#define XSLCR_OCM_RST_CTRL_VAL 0x1 -#define XSLCR_SDIO_RST_CTRL_VAL 0x33 -#define XSLCR_CAN_RST_CTRL_VAL 0x3 -/**************************** Type Definitions *******************************/ - -/* the following data type is used to hold a null terminated version string - * consisting of the following format, "X.YYX" - */ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ -/* - * Performs reset operation to the ddr interface - */ -void XDdr_ResetHw(); -/* - * Map the ocm region to post bootrom state - */ -void XOcm_Remap(); -/* - * Performs the smc interface reset - */ -void XSmc_ResetHw(u32 BaseAddress); -/* - * updates the MIO registers with reset values - */ -void XSlcr_MioWriteResetValues(); -/* - * updates the PLL and clock registers with reset values - */ -void XSlcr_PllWriteResetValues(); -/* - * Disables the level shifters - */ -void XSlcr_DisableLevelShifters(); -/* - * provides softreset to the GPIO interface - */ -void XSlcr_GpioPsReset(void); -/* - * provides softreset to the DMA interface - */ -void XSlcr_DmaPsReset(void); -/* - * provides softreset to the SMC interface - */ -void XSlcr_SmcPsReset(void); -/* - * provides softreset to the CAN interface - */ -void XSlcr_CanPsReset(void); -/* - * provides softreset to the Uart interface - */ -void XSlcr_UartPsReset(void); -/* - * provides softreset to the I2C interface - */ -void XSlcr_I2cPsReset(void); -/* - * provides softreset to the SPI interface - */ -void XSlcr_SpiPsReset(void); -/* - * provides softreset to the QSPI interface - */ -void XSlcr_QspiPsReset(void); -/* - * provides softreset to the USB interface - */ -void XSlcr_UsbPsReset(void); -/* - * provides softreset to the GEM interface - */ -void XSlcr_EmacPsReset(void); -/* - * provides softreset to the OCM interface - */ -void XSlcr_OcmReset(void); - - -#ifdef __cplusplus -} -#endif - -#endif /* XIL_MISC_RESET_H */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_misc_psreset_api.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_misc_psreset_api.o deleted file mode 100644 index 36a6b2c719cc7d3c09cc87a0c33fd21c98cd2e53..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_misc_psreset_api.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_mmu.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_mmu.c deleted file mode 100644 index bd1b27df8a5455e3ed52b8f33936d9350d44e798..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_mmu.c +++ /dev/null @@ -1,189 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2012 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -******************************************************************************/ -/*****************************************************************************/ -/** -* @file xil_mmu.c -* -* This file provides APIs for enabling/disabling MMU and setting the memory -* attributes for sections, in the MMU translation table. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- --------------------------------------------------- -* 1.00a sdm 01/12/12 Initial version -* 3.05a asa 03/10/12 Modified the Xil_EnableMMU to invalidate the caches -* before enabling back. -* 3.05a asa 04/15/12 Modified the Xil_SetTlbAttributes routine so that -* translation table and branch predictor arrays are -* invalidated, D-cache flushed before the attribute -* change is applied. This is done so that the user -* need not call Xil_DisableMMU before calling -* Xil_SetTlbAttributes. -* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file -* 'xil_errata.h' for errata description -* 3.11a asa 09/23/13 Modified Xil_SetTlbAttributes to flush the complete -* D cache after the translation table update. Removed the -* redundant TLB invalidation in the same API at the beginning. -* </pre> -* -* @note -* -* None. -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xil_cache.h" -#include "xpseudo_asm.h" -#include "xil_types.h" -#include "xil_mmu.h" -#include "xil_errata.h" - -/***************** Macros (Inline Functions) Definitions *********************/ - -/**************************** Type Definitions *******************************/ - -/************************** Constant Definitions *****************************/ - -/************************** Variable Definitions *****************************/ - -extern u32 MMUTable; - -/************************** Function Prototypes ******************************/ - -/***************************************************************************** -* -* Set the memory attributes for a section, in the translation table. Each -* section covers 1MB of memory. -* -* @param addr is the address for which attributes are to be set. -* @param attrib specifies the attributes for that memory region. -* -* @return None. -* -* @note The MMU and D-cache need not be disabled before changing an -* translation table attribute. -* -******************************************************************************/ -void Xil_SetTlbAttributes(u32 addr, u32 attrib) -{ - u32 *ptr; - u32 section; - - section = addr / 0x100000; - ptr = &MMUTable + section; - *ptr = (addr & 0xFFF00000) | attrib; - - Xil_DCacheFlush(); - - mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0); - /* Invalidate all branch predictors */ - mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0); - - dsb(); /* ensure completion of the BP and TLB invalidation */ - isb(); /* synchronize context on this processor */ -} - -/***************************************************************************** -* -* Invalidate the caches, enable MMU and D Caches for Cortex A9 processor. -* -* @param None. -* @return None. -* -******************************************************************************/ -void Xil_EnableMMU(void) -{ - u32 Reg; - Xil_DCacheInvalidate(); - Xil_ICacheInvalidate(); - -#ifdef __GNUC__ - Reg = mfcp(XREG_CP15_SYS_CONTROL); -#elif defined (__ICCARM__) - mfcp(XREG_CP15_SYS_CONTROL, Reg); -#else - { volatile register unsigned int Cp15Reg __asm(XREG_CP15_SYS_CONTROL); - Reg = Cp15Reg; } -#endif - Reg |= 0x05; - mtcp(XREG_CP15_SYS_CONTROL, Reg); - - dsb(); - isb(); -} - -/***************************************************************************** -* -* Disable MMU for Cortex A9 processors. This function invalidates the TLBs, -* Branch Predictor Array and flushed the D Caches before disabling -* the MMU and D cache. -* -* @param None. -* -* @return None. -* -******************************************************************************/ -void Xil_DisableMMU(void) -{ - u32 Reg; - - mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0); - mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0); - Xil_DCacheFlush(); - -#ifdef __GNUC__ - Reg = mfcp(XREG_CP15_SYS_CONTROL); -#elif defined (__ICCARM__) - mfcp(XREG_CP15_SYS_CONTROL, Reg); -#else - { volatile register unsigned int Cp15Reg __asm(XREG_CP15_SYS_CONTROL); - Reg = Cp15Reg; } -#endif - Reg &= ~0x05; -#ifdef CONFIG_ARM_ERRATA_794073 - /* Disable Branch Prediction */ - Reg &= ~0x800; -#endif - mtcp(XREG_CP15_SYS_CONTROL, Reg); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_mmu.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_mmu.h deleted file mode 100644 index edbb7e5232afe3b86166f398df07b35a8d8435cb..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_mmu.h +++ /dev/null @@ -1,87 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2012 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -******************************************************************************/ -/*****************************************************************************/ -/** -* @file xil_mmu.h -* -* -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- --------------------------------------------------- -* 1.00a sdm 01/12/12 Initial version -* </pre> -* -* @note -* -* None. -* -******************************************************************************/ - -#ifndef XIL_MMU_H -#define XIL_MMU_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/***************************** Include Files *********************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/**************************** Type Definitions *******************************/ - -/************************** Constant Definitions *****************************/ - -/************************** Variable Definitions *****************************/ - -/************************** Function Prototypes ******************************/ - -void Xil_SetTlbAttributes(u32 addr, u32 attrib); -void Xil_EnableMMU(void); -void Xil_DisableMMU(void); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* XIL_MMU_H */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_mmu.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_mmu.o deleted file mode 100644 index 1046a85dfe2e8c3c2b2bdacbb60cf8e698846a0d..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_mmu.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_printf.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_printf.c deleted file mode 100644 index 83b0c1469a14867a9077de5f3c92a26c6128e883..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_printf.c +++ /dev/null @@ -1,256 +0,0 @@ -/*---------------------------------------------------*/ -/* Modified from : */ -/* Public Domain version of printf */ -/* Rud Merriam, Compsult, Inc. Houston, Tx. */ -/* For Embedded Systems Programming, 1991 */ -/* */ -/*---------------------------------------------------*/ -#include "xil_printf.h" -#include <ctype.h> -#include <string.h> -#include <stdarg.h> - - -typedef struct params_s { - int len; - int num1; - int num2; - char pad_character; - int do_padding; - int left_flag; -} params_t; - - -/*---------------------------------------------------*/ -/* The purpose of this routine is to output data the */ -/* same as the standard printf function without the */ -/* overhead most run-time libraries involve. Usually */ -/* the printf brings in many kilobytes of code and */ -/* that is unacceptable in most embedded systems. */ -/*---------------------------------------------------*/ - - -/*---------------------------------------------------*/ -/* */ -/* This routine puts pad characters into the output */ -/* buffer. */ -/* */ -void padding( const int l_flag, params_t *par) -{ - int i; - - if (par->do_padding && l_flag && (par->len < par->num1)) - for (i=par->len; i<par->num1; i++) - outbyte( par->pad_character); -} - -/*---------------------------------------------------*/ -/* */ -/* This routine moves a string to the output buffer */ -/* as directed by the padding and positioning flags. */ -/* */ -void outs( charptr lp, params_t *par) -{ - /* pad on left if needed */ - par->len = strlen( lp); - padding( !(par->left_flag), par); - - /* Move string to the buffer */ - while (*lp && (par->num2)--) - outbyte( *lp++); - - /* Pad on right if needed */ - /* CR 439175 - elided next stmt. Seemed bogus. */ - /* par->len = strlen( lp); */ - padding( par->left_flag, par); -} - -/*---------------------------------------------------*/ -/* */ -/* This routine moves a number to the output buffer */ -/* as directed by the padding and positioning flags. */ -/* */ - -void outnum( const long n, const long base, params_t *par) -{ - charptr cp; - int negative; - char outbuf[32]; - const char digits[] = "0123456789ABCDEF"; - unsigned long num; - - /* Check if number is negative */ - if (base == 10 && n < 0L) { - negative = 1; - num = -(n); - } - else{ - num = (n); - negative = 0; - } - - /* Build number (backwards) in outbuf */ - cp = outbuf; - do { - *cp++ = digits[(int)(num % base)]; - } while ((num /= base) > 0); - if (negative) - *cp++ = '-'; - *cp-- = 0; - - /* Move the converted number to the buffer and */ - /* add in the padding where needed. */ - par->len = strlen(outbuf); - padding( !(par->left_flag), par); - while (cp >= outbuf) - outbyte( *cp--); - padding( par->left_flag, par); -} - -/*---------------------------------------------------*/ -/* */ -/* This routine gets a number from the format */ -/* string. */ -/* */ -int getnum( charptr* linep) -{ - int n; - charptr cp; - - n = 0; - cp = *linep; - while (isdigit(((int)*cp))) - n = n*10 + ((*cp++) - '0'); - *linep = cp; - return(n); -} - -/*---------------------------------------------------*/ -/* */ -/* This routine operates just like a printf/sprintf */ -/* routine. It outputs a set of data under the */ -/* control of a formatting string. Not all of the */ -/* standard C format control are supported. The ones */ -/* provided are primarily those needed for embedded */ -/* systems work. Primarily the floaing point */ -/* routines are omitted. Other formats could be */ -/* added easily by following the examples shown for */ -/* the supported formats. */ -/* */ - -/* void esp_printf( const func_ptr f_ptr, - const charptr ctrl1, ...) */ -void xil_printf( const char *ctrl1, ...) -{ - - int long_flag; - int dot_flag; - - params_t par; - - char ch; - va_list argp; - char *ctrl = (char *)ctrl1; - - va_start( argp, ctrl1); - - for ( ; *ctrl; ctrl++) { - - /* move format string chars to buffer until a */ - /* format control is found. */ - if (*ctrl != '%') { - outbyte(*ctrl); - continue; - } - - /* initialize all the flags for this format. */ - dot_flag = long_flag = par.left_flag = par.do_padding = 0; - par.pad_character = ' '; - par.num2=32767; - - try_next: - ch = *(++ctrl); - - if (isdigit((int)ch)) { - if (dot_flag) - par.num2 = getnum(&ctrl); - else { - if (ch == '0') - par.pad_character = '0'; - - par.num1 = getnum(&ctrl); - par.do_padding = 1; - } - ctrl--; - goto try_next; - } - - switch (tolower((int)ch)) { - case '%': - outbyte( '%'); - continue; - - case '-': - par.left_flag = 1; - break; - - case '.': - dot_flag = 1; - break; - - case 'l': - long_flag = 1; - break; - - case 'd': - if (long_flag || ch == 'D') { - outnum( va_arg(argp, long), 10L, &par); - continue; - } - else { - outnum( va_arg(argp, int), 10L, &par); - continue; - } - case 'x': - outnum((long)va_arg(argp, int), 16L, &par); - continue; - - case 's': - outs( va_arg( argp, char *), &par); - continue; - - case 'c': - outbyte( va_arg( argp, int)); - continue; - - case '\\': - switch (*ctrl) { - case 'a': - outbyte( 0x07); - break; - case 'h': - outbyte( 0x08); - break; - case 'r': - outbyte( 0x0D); - break; - case 'n': - outbyte( 0x0D); - outbyte( 0x0A); - break; - default: - outbyte( *ctrl); - break; - } - ctrl++; - break; - - default: - continue; - } - goto try_next; - } - va_end( argp); -} - -/*---------------------------------------------------*/ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_printf.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_printf.h deleted file mode 100644 index 89a051c23d3bfed90e15c8ac6d3e169b0e0ac23f..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_printf.h +++ /dev/null @@ -1,47 +0,0 @@ - #ifndef XIL_PRINTF_H - #define XIL_PRINTF_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <ctype.h> -#include <string.h> -#include <stdarg.h> -#include "xparameters.h" -#include "xil_types.h" - -/*----------------------------------------------------*/ -/* Use the following parameter passing structure to */ -/* make xil_printf re-entrant. */ -/*----------------------------------------------------*/ - -struct params_s; - - -/*---------------------------------------------------*/ -/* The purpose of this routine is to output data the */ -/* same as the standard printf function without the */ -/* overhead most run-time libraries involve. Usually */ -/* the printf brings in many kilobytes of code and */ -/* that is unacceptable in most embedded systems. */ -/*---------------------------------------------------*/ - -typedef char* charptr; -typedef int (*func_ptr)(int c); - -/* */ -void padding( const int l_flag, struct params_s *par); -void outs( charptr lp, struct params_s *par); -void outnum( const long n, const long base, struct params_s *par); -int getnum( charptr* linep); -void xil_printf( const char *ctrl1, ...); -void print( const char *ptr); -void outbyte (char); -char inbyte(void); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_printf.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_printf.o deleted file mode 100644 index b59d45589fd98e8962962916d48573a944a75d34..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_printf.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_testcache.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_testcache.c deleted file mode 100644 index 5eb3e1c3037a5dbe0d17f6c2d8c5f4ce82dc1c41..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_testcache.c +++ /dev/null @@ -1,224 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_testcache.c -* -* Contains utility functions to test cache. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.00a hbm 07/28/09 Initial release -* -* </pre> -* -* @note -* -* This file contain functions that all operate on HAL. -* -******************************************************************************/ -#include "xil_cache.h" -#include "xil_testcache.h" - -extern void xil_printf(const char *ctrl1, ...); - -#define DATA_LENGTH 128 - -static u32 Data[DATA_LENGTH]; - -/** -* Perform DCache range related API test such as Xil_DCacheFlushRange and -* Xil_DCacheInvalidateRange. This test function writes a constant value -* to the Data array, flushes the range, writes a new value, then invalidates -* the corresponding range. -* -* @return -* -* - 0 is returned for a pass -* - -1 is returned for a failure -*/ -int Xil_TestDCacheRange(void) -{ - int Index; - int Status; - - u32 Value; - - xil_printf("-- Cache Range Test --\n\r"); - - - for (Index = 0; Index < DATA_LENGTH; Index++) - Data[Index] = 0xA0A00505; - - xil_printf(" initialize Data done:\r\n"); - - Xil_DCacheFlushRange((u32)Data, DATA_LENGTH * sizeof(u32)); - - xil_printf(" flush range done\r\n"); - for (Index = 0; Index < DATA_LENGTH; Index++) - Data[Index] = Index + 3; - - Xil_DCacheInvalidateRange((u32)Data, DATA_LENGTH * sizeof(u32)); - - xil_printf(" invalidate dcache range done\r\n"); - - Status = 0; - - for (Index = 0; Index < DATA_LENGTH; Index++) { - Value = Data[Index]; - if (Value != 0xA0A00505) { - Status = -1; - xil_printf("Data[%d] = %x\r\n", Index, Value); - break; - } - } - - if (!Status) { - xil_printf(" Invalidate worked\r\n"); - } - else { - xil_printf("Error: Invalidate dcache range not working\r\n"); - } - - xil_printf("-- Cache Range Test Complete --\r\n"); - - return Status; - -} - -/** -* Perform DCache all related API test such as Xil_DCacheFlush and -* Xil_DCacheInvalidate. This test function writes a constant value -* to the Data array, flushes the DCache, writes a new value, then invalidates -* the DCache. -* -* @return -* - 0 is returned for a pass -* - -1 is returned for a failure -*/ -int Xil_TestDCacheAll(void) -{ - int Index; - int Status; - u32 Value; - - xil_printf("-- Cache All Test --\n\r"); - - - for (Index = 0; Index < DATA_LENGTH; Index++) - Data[Index] = 0x50500A0A; - - xil_printf(" initialize Data done:\r\n"); - - Xil_DCacheFlush(); - - xil_printf(" flush all done\r\n"); - - for (Index = 0; Index < DATA_LENGTH; Index++) - Data[Index] = Index + 3; - - Xil_DCacheInvalidate(); - - xil_printf(" invalidate all done\r\n"); - - Status = 0; - - for (Index = 0; Index < DATA_LENGTH; Index++) { - Value = Data[Index]; - if (Value != 0x50500A0A) { - Status = -1; - xil_printf("Data[%d] = %x\r\n", Index, Value); - break; - } - } - - if (!Status) { - xil_printf(" Invalidate all worked\r\n"); - } - else { - xil_printf("Error: Invalidate dcache all not working\r\n"); - } - - xil_printf("-- DCache all Test Complete --\n\r"); - - return Status; - -} - - -/** -* Perform Xil_ICacheInvalidateRange() on a few function pointers. -* -* @return -* -* - 0 is returned for a pass -* The function will hang if it fails. -*/ -int Xil_TestICacheRange(void) -{ - - Xil_ICacheInvalidateRange((u32)Xil_TestICacheRange, 1024); - Xil_ICacheInvalidateRange((u32)Xil_TestDCacheRange, 1024); - Xil_ICacheInvalidateRange((u32)Xil_TestDCacheAll, 1024); - - xil_printf("-- Invalidate icache range done --\r\n"); - - return 0; -} - -/** -* Perform Xil_ICacheInvalidate(). -* -* @return -* -* - 0 is returned for a pass -* The function will hang if it fails. -*/ -int Xil_TestICacheAll(void) -{ - Xil_ICacheInvalidate(); - xil_printf("-- Invalidate icache all done --\r\n"); - return 0; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_testcache.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_testcache.h deleted file mode 100644 index db6d29652e0ed5c79759404d6d6e274dec6e326f..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_testcache.h +++ /dev/null @@ -1,71 +0,0 @@ -/****************************************************************************** -* -* -* (c) Copyright 2009 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_testcache.h -* -* This file contains utility functions to test cache. -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a hbm 07/29/09 First release -* -******************************************************************************/ - -#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */ -#define XIL_TESTCACHE_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -extern int Xil_TestDCacheRange(void); -extern int Xil_TestDCacheAll(void); -extern int Xil_TestICacheRange(void); -extern int Xil_TestICacheAll(void); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_testcache.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_testcache.o deleted file mode 100644 index bbbb80aeb91d18c70c9caa780715fd5eeee47815..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_testcache.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_testio.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_testio.c deleted file mode 100644 index 5aa77905894e0bca0382b05bbf40616e7319101d..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_testio.c +++ /dev/null @@ -1,304 +0,0 @@ -/****************************************************************************** -* -* -* (c) Copyright 2009 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_testmemend.c -* -* Contains the memory test utility functions. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a hbm 08/25/09 First release -* </pre> -* -*****************************************************************************/ - -/***************************** Include Files ********************************/ -#include "xil_testio.h" -#include "xil_assert.h" -#include "xil_io.h" - -/************************** Constant Definitions ****************************/ -/************************** Function Prototypes *****************************/ - - - -/** - * - * Endian swap a 16-bit word. - * @param Data is the 16-bit word to be swapped. - * @return The endian swapped valud. - * - */ -static u16 Swap16(u16 Data) -{ - return ((Data >> 8) & 0x00FF) | ((Data << 8) & 0xFF00); -} - -/** - * - * Endian swap a 32-bit word. - * @param Data is the 32-bit word to be swapped. - * @return The endian swapped valud. - * - */ -static u32 Swap32(u32 Data) -{ - u16 Lo16; - u16 Hi16; - - u16 Swap16Lo; - u16 Swap16Hi; - - Hi16 = (u16)((Data >> 16) & 0x0000FFFF); - Lo16 = (u16)(Data & 0x0000FFFF); - - Swap16Lo = Swap16(Lo16); - Swap16Hi = Swap16(Hi16); - - return (((u32)(Swap16Lo)) << 16) | ((u32)Swap16Hi); -} - -/*****************************************************************************/ -/** -* -* Perform a destructive 8-bit wide register IO test where the register is -* accessed using Xil_Out8 and Xil_In8, and comparing the reading and writing -* values. -* -* @param Addr is a pointer to the region of memory to be tested. -* @param Len is the length of the block. -* @param Value is the constant used for writting the memory. -* -* @return -* -* - -1 is returned for a failure -* - 0 is returned for a pass -* -*****************************************************************************/ - -int Xil_TestIO8(u8 *Addr, int Len, u8 Value) -{ - u8 ValueIn; - int Index; - - for (Index = 0; Index < Len; Index++) { - Xil_Out8((u32)Addr, Value); - - ValueIn = Xil_In8((u32)Addr); - - if (Value != ValueIn) { - return -1; - } - } - - return 0; - -} - -/*****************************************************************************/ -/** -* -* Perform a destructive 16-bit wide register IO test. Each location is tested -* by sequentially writing a 16-bit wide register, reading the register, and -* comparing value. This function tests three kinds of register IO functions, -* normal register IO, little-endian register IO, and big-endian register IO. -* When testing little/big-endian IO, the function performs the following -* sequence, Xil_Out16LE/Xil_Out16BE, Xil_In16, Compare In-Out values, -* Xil_Out16, Xil_In16LE/Xil_In16BE, Compare In-Out values. Whether to swap the -* read-in value before comparing is controlled by the 5th argument. -* -* @param Addr is a pointer to the region of memory to be tested. -* @param Len is the length of the block. -* @param Value is the constant used for writting the memory. -* @param Kind is the test kind. Acceptable values are: -* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE. -* @param Swap indicates whether to byte swap the read-in value. -* -* @return -* -* - -1 is returned for a failure -* - 0 is returned for a pass -* -*****************************************************************************/ - -int Xil_TestIO16(u16 *Addr, int Len, u16 Value, int Kind, int Swap) -{ - u16 ValueIn; - int Index; - - for (Index = 0; Index < Len; Index++) { - switch (Kind) { - case XIL_TESTIO_LE: - Xil_Out16LE((u32)Addr, Value); - break; - case XIL_TESTIO_BE: - Xil_Out16BE((u32)Addr, Value); - break; - default: - Xil_Out16((u32)Addr, Value); - break; - } - - ValueIn = Xil_In16((u32)Addr); - - if (Kind && Swap) - ValueIn = Swap16(ValueIn); - - if (Value != ValueIn) { - return -1; - } - - /* second round */ - Xil_Out16((u32)Addr, Value); - - switch (Kind) { - case XIL_TESTIO_LE: - ValueIn = Xil_In16LE((u32)Addr); - break; - case XIL_TESTIO_BE: - ValueIn = Xil_In16BE((u32)Addr); - break; - default: - ValueIn = Xil_In16((u32)Addr); - break; - } - - - if (Kind && Swap) - ValueIn = Swap16(ValueIn); - - if (Value != ValueIn) { - return -1; - } - Addr++; - } - - return 0; - -} - - -/*****************************************************************************/ -/** -* -* Perform a destructive 32-bit wide register IO test. Each location is tested -* by sequentially writing a 32-bit wide regsiter, reading the register, and -* comparing value. This function tests three kinds of register IO functions, -* normal register IO, little-endian register IO, and big-endian register IO. -* When testing little/big-endian IO, the function perform the following -* sequence, Xil_Out32LE/Xil_Out32BE, Xil_In32, Compare, -* Xil_Out32, Xil_In32LE/Xil_In32BE, Compare. Whether to swap the read-in value -* before comparing is controlled by the 5th argument. -* -* @param Addr is a pointer to the region of memory to be tested. -* @param Len is the length of the block. -* @param Value is the constant used for writting the memory. -* @param Kind is the test kind. Acceptable values are: -* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE. -* @param Swap indicates whether to byte swap the read-in value. -* -* @return -* -* - -1 is returned for a failure -* - 0 is returned for a pass -* -*****************************************************************************/ -int Xil_TestIO32(u32 *Addr, int Len, u32 Value, int Kind, int Swap) -{ - u32 ValueIn; - int Index; - - for (Index = 0; Index < Len; Index++) { - switch (Kind) { - case XIL_TESTIO_LE: - Xil_Out32LE((u32)Addr, Value); - break; - case XIL_TESTIO_BE: - Xil_Out32BE((u32)Addr, Value); - break; - default: - Xil_Out32((u32)Addr, Value); - break; - } - - ValueIn = Xil_In32((u32)Addr); - - if (Kind && Swap) - ValueIn = Swap32(ValueIn); - - if (Value != ValueIn) { - return -1; - } - - /* second round */ - Xil_Out32((u32)Addr, Value); - - - switch (Kind) { - case XIL_TESTIO_LE: - ValueIn = Xil_In32LE((u32)Addr); - break; - case XIL_TESTIO_BE: - ValueIn = Xil_In32BE((u32)Addr); - break; - default: - ValueIn = Xil_In32((u32)Addr); - break; - } - - if (Kind && Swap) - ValueIn = Swap32(ValueIn); - - if (Value != ValueIn) { - return -1; - } - Addr++; - } - return 0; -} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_testio.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_testio.h deleted file mode 100644 index 33a8286f17c2be13a43f59c6f07d179fa1384054..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_testio.h +++ /dev/null @@ -1,101 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_testmemend.h -* -* This file contains utility functions to teach endian related memory -* IO functions. -* -* <b>Memory test description</b> -* -* A subset of the memory tests can be selected or all of the tests can be run -* in order. If there is an error detected by a subtest, the test stops and the -* failure code is returned. Further tests are not run even if all of the tests -* are selected. -* -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00 hbm 08/05/09 First release -* </pre> -* -******************************************************************************/ - -#ifndef XIL_TESTIO_H /* prevent circular inclusions */ -#define XIL_TESTIO_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ -#include "xil_types.h" - -/************************** Constant Definitions *****************************/ - - -#define XIL_TESTIO_DEFAULT 0 -#define XIL_TESTIO_LE 1 -#define XIL_TESTIO_BE 2 - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - -extern int Xil_TestIO8(u8 *Addr, int Len, u8 Value); -extern int Xil_TestIO16(u16 *Addr, int Len, u16 Value, int Kind, int Swap); -extern int Xil_TestIO32(u32 *Addr, int Len, u32 Value, int Kind, int Swap); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_testio.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_testio.o deleted file mode 100644 index af2a671f16943645980e19d3e9392720adc4983d..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_testio.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_testmem.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_testmem.c deleted file mode 100644 index 27a1a12709f47f6e2af677cbfaa42d8603215c87..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_testmem.c +++ /dev/null @@ -1,1004 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_testmem.c -* -* Contains the memory test utility functions. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a hbm 08/25/09 First release -* </pre> -* -*****************************************************************************/ - -/***************************** Include Files ********************************/ -#include "xil_testmem.h" -#include "xil_io.h" -#include "xil_assert.h" - -/************************** Constant Definitions ****************************/ -/************************** Function Prototypes *****************************/ - -static u32 RotateLeft(u32 Input, u8 Width); - -/* define ROTATE_RIGHT to give access to this functionality */ -/* #define ROTATE_RIGHT */ -#ifdef ROTATE_RIGHT -static u32 RotateRight(u32 Input, u8 Width); -#endif /* ROTATE_RIGHT */ - - -/*****************************************************************************/ -/** -* -* Perform a destructive 32-bit wide memory test. -* -* @param Addr is a pointer to the region of memory to be tested. -* @param Words is the length of the block. -* @param Pattern is the constant used for the constant pattern test, if 0, -* 0xDEADBEEF is used. -* @param Subtest is the test selected. See xil_testmem.h for possible -* values. -* -* @return -* -* - 0 is returned for a pass -* - -1 is returned for a failure -* -* @note -* -* Used for spaces where the address range of the region is smaller than -* the data width. If the memory range is greater than 2 ** Width, -* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will -* repeat on a boundry of a power of two making it more difficult to detect -* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR -* tests suffer the same problem. Ideally, if large blocks of memory are to be -* tested, break them up into smaller regions of memory to allow the test -* patterns used not to repeat over the region tested. -* -*****************************************************************************/ -int Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest) -{ - u32 I; - u32 J; - u32 Val; - u32 FirtVal; - u32 Word; - - Xil_AssertNonvoid(Words != 0); - Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST); - - /* - * variable initialization - */ - Val = XIL_TESTMEM_INIT_VALUE; - FirtVal = XIL_TESTMEM_INIT_VALUE; - - /* - * Select the proper Subtest - */ - switch (Subtest) { - - case XIL_TESTMEM_ALLMEMTESTS: - - /* this case executes all of the Subtests */ - - /* fall through case statement */ - - case XIL_TESTMEM_INCREMENT: - - /* - * Fill the memory with incrementing - * values starting from 'FirtVal' - */ - for (I = 0L; I < Words; I++) { - Addr[I] = Val; - Val++; - } - - /* - * Restore the reference 'Val' to the - * initial value - */ - Val = FirtVal; - - /* - * Check every word within the words - * of tested memory and compare it - * with the incrementing reference - * Val - */ - - for (I = 0L; I < Words; I++) { - Word = Addr[I]; - - if (Word != Val) { - return -1; - } - - Val++; - } - - - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - - - /* end of case 1 */ - - /* fall through case statement */ - - case XIL_TESTMEM_WALKONES: - /* - * set up to cycle through all possible initial - * test Patterns for walking ones test - */ - - for (J = 0L; J < 32; J++) { - /* - * Generate an initial value for walking ones test - * to test for bad data bits - */ - - Val = 1 << J; - - /* - * START walking ones test - * Write a one to each data bit indifferent locations - */ - - for (I = 0L; I < 32; I++) { - /* write memory location */ - Addr[I] = Val; - Val = (u32) RotateLeft(Val, 32); - } - - /* - * Restore the reference 'val' to the - * initial value - */ - Val = 1 << J; - - /* Read the values from each location that was - * written */ - for (I = 0L; I < 32; I++) { - /* read memory location */ - - Word = Addr[I]; - - if (Word != Val) { - return -1; - } - - Val = (u32)RotateLeft(Val, 32); - } - - } - - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - - /* end of case 2 */ - /* fall through case statement */ - - case XIL_TESTMEM_WALKZEROS: - /* - * set up to cycle through all possible - * initial test Patterns for walking zeros test - */ - - for (J = 0L; J < 32; J++) { - - /* - * Generate an initial value for walking ones test - * to test for bad data bits - */ - - Val = ~(1 << J); - - /* - * START walking zeros test - * Write a one to each data bit indifferent locations - */ - - for (I = 0L; I < 32; I++) { - /* write memory location */ - Addr[I] = Val; - Val = ~((u32)RotateLeft(~Val, 32)); - } - - /* - * Restore the reference 'Val' to the - * initial value - */ - - Val = ~(1 << J); - - /* Read the values from each location that was - * written */ - for (I = 0L; I < 32; I++) { - /* read memory location */ - Word = Addr[I]; - if (Word != Val) { - return -1; - } - Val = ~((u32)RotateLeft(~Val, 32)); - } - - } - - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - - /* end of case 3 */ - - /* fall through case statement */ - - case XIL_TESTMEM_INVERSEADDR: - /* Fill the memory with inverse of address */ - for (I = 0L; I < Words; I++) { - /* write memory location */ - Val = (u32) (~((u32) (&Addr[I]))); - Addr[I] = Val; - } - - /* - * Check every word within the words - * of tested memory - */ - - for (I = 0L; I < Words; I++) { - /* Read the location */ - Word = Addr[I]; - Val = (u32) (~((u32) (&Addr[I]))); - - if ((Word ^ Val) != 0x00000000) { - return -1; - } - } - - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 4 */ - - /* fall through case statement */ - - case XIL_TESTMEM_FIXEDPATTERN: - /* - * Generate an initial value for - * memory testing - */ - - if (Pattern == 0) { - Val = 0xDEADBEEF; - } - else { - Val = Pattern; - } - - /* - * Fill the memory with fixed Pattern - */ - - for (I = 0L; I < Words; I++) { - /* write memory location */ - Addr[I] = Val; - } - - /* - * Check every word within the words - * of tested memory and compare it - * with the fixed Pattern - */ - - for (I = 0L; I < Words; I++) { - - /* read memory location */ - - Word = Addr[I]; - if (Word != Val) { - return -1; - } - } - - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 5 */ - - /* this break is for the prior fall through case statements */ - - break; - - default: - return -1; - - } /* end of switch */ - - /* Successfully passed memory test ! */ - - return 0; -} - -/*****************************************************************************/ -/** -* -* Perform a destructive 16-bit wide memory test. -* -* @param Addr is a pointer to the region of memory to be tested. -* @param Words is the length of the block. -* @param Pattern is the constant used for the constant Pattern test, if 0, -* 0xDEADBEEF is used. -* @param Subtest is the test selected. See xil_testmem.h for possible -* values. -* -* @return -* -* - -1 is returned for a failure -* - 0 is returned for a pass -* -* @note -* -* Used for spaces where the address range of the region is smaller than -* the data width. If the memory range is greater than 2 ** Width, -* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will -* repeat on a boundry of a power of two making it more difficult to detect -* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR -* tests suffer the same problem. Ideally, if large blocks of memory are to be -* tested, break them up into smaller regions of memory to allow the test -* patterns used not to repeat over the region tested. -* -*****************************************************************************/ -int Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest) -{ - u32 I; - u32 J; - u16 Val; - u16 FirtVal; - u16 Word; - - Xil_AssertNonvoid(Words != 0); - Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST); - - /* - * variable initialization - */ - Val = XIL_TESTMEM_INIT_VALUE; - FirtVal = XIL_TESTMEM_INIT_VALUE; - - /* - * selectthe proper Subtest(s) - */ - - switch (Subtest) { - - case XIL_TESTMEM_ALLMEMTESTS: - - /* this case executes all of the Subtests */ - - /* fall through case statement */ - - case XIL_TESTMEM_INCREMENT: - /* - * Fill the memory with incrementing - * values starting from 'FirtVal' - */ - for (I = 0L; I < Words; I++) { - /* write memory location */ - Addr[I] = Val; - Val++; - } - /* - * Restore the reference 'Val' to the - * initial value - */ - Val = FirtVal; - - /* - * Check every word within the words - * of tested memory and compare it - * with the incrementing reference val - */ - - for (I = 0L; I < Words; I++) { - /* read memory location */ - Word = Addr[I]; - if (Word != Val) { - return -1; - } - Val++; - } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - - /* end of case 1 */ - /* fall through case statement */ - - case XIL_TESTMEM_WALKONES: - /* - * set up to cycle through all possible initial test - * Patterns for walking ones test - */ - - for (J = 0L; J < 16; J++) { - /* - * Generate an initial value for walking ones test - * to test for bad data bits - */ - - Val = 1 << J; - /* - * START walking ones test - * Write a one to each data bit indifferent locations - */ - - for (I = 0L; I < 16; I++) { - /* write memory location */ - Addr[I] = Val; - Val = (u16)RotateLeft(Val, 16); - } - /* - * Restore the reference 'Val' to the - * initial value - */ - Val = 1 << J; - /* Read the values from each location that was written */ - for (I = 0L; I < 16; I++) { - /* read memory location */ - Word = Addr[I]; - if (Word != Val) { - return -1; - } - Val = (u16)RotateLeft(Val, 16); - } - - } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 2 */ - /* fall through case statement */ - - case XIL_TESTMEM_WALKZEROS: - /* - * set up to cycle through all possible initial - * test Patterns for walking zeros test - */ - - for (J = 0L; J < 16; J++) { - /* - * Generate an initial value for walking ones - * test to test for bad - * data bits - */ - - Val = ~(1 << J); - /* - * START walking zeros test - * Write a one to each data bit indifferent locations - */ - - for (I = 0L; I < 16; I++) { - /* write memory location */ - Addr[I] = Val; - Val = ~((u16)RotateLeft(~Val, 16)); - } - /* - * Restore the reference 'Val' to the - * initial value - */ - Val = ~(1 << J); - /* Read the values from each location that was written */ - for (I = 0L; I < 16; I++) { - /* read memory location */ - Word = Addr[I]; - if (Word != Val) { - return -1; - } - Val = ~((u16)RotateLeft(~Val, 16)); - } - - } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 3 */ - /* fall through case statement */ - - case XIL_TESTMEM_INVERSEADDR: - /* Fill the memory with inverse of address */ - for (I = 0L; I < Words; I++) { - /* write memory location */ - Val = (u16) (~((u32) (&Addr[I]))); - Addr[I] = Val; - } - /* - * Check every word within the words - * of tested memory - */ - - for (I = 0L; I < Words; I++) { - /* read memory location */ - Word = Addr[I]; - Val = (u16) (~((u32) (&Addr[I]))); - if ((Word ^ Val) != 0x0000) { - return -1; - } - } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 4 */ - /* fall through case statement */ - - case XIL_TESTMEM_FIXEDPATTERN: - /* - * Generate an initial value for - * memory testing - */ - if (Pattern == 0) { - Val = 0xDEAD; - } - else { - Val = Pattern; - } - - /* - * Fill the memory with fixed pattern - */ - - for (I = 0L; I < Words; I++) { - /* write memory location */ - Addr[I] = Val; - } - - /* - * Check every word within the words - * of tested memory and compare it - * with the fixed pattern - */ - - for (I = 0L; I < Words; I++) { - /* read memory location */ - Word = Addr[I]; - if (Word != Val) { - return -1; - } - } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 5 */ - /* this break is for the prior fall through case statements */ - - break; - - default: - return -1; - - } /* end of switch */ - - /* Successfully passed memory test ! */ - - return 0; -} - - -/*****************************************************************************/ -/** -* -* Perform a destructive 8-bit wide memory test. -* -* @param Addr is a pointer to the region of memory to be tested. -* @param Words is the length of the block. -* @param Pattern is the constant used for the constant pattern test, if 0, -* 0xDEADBEEF is used. -* @param Subtest is the test selected. See xil_testmem.h for possible -* values. -* -* @return -* -* - -1 is returned for a failure -* - 0 is returned for a pass -* -* @note -* -* Used for spaces where the address range of the region is smaller than -* the data width. If the memory range is greater than 2 ** Width, -* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will -* repeat on a boundry of a power of two making it more difficult to detect -* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR -* tests suffer the same problem. Ideally, if large blocks of memory are to be -* tested, break them up into smaller regions of memory to allow the test -* patterns used not to repeat over the region tested. -* -*****************************************************************************/ -int Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest) -{ - u32 I; - u32 J; - u8 Val; - u8 FirtVal; - u8 Word; - - Xil_AssertNonvoid(Words != 0); - Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST); - - /* - * variable initialization - */ - Val = XIL_TESTMEM_INIT_VALUE; - FirtVal = XIL_TESTMEM_INIT_VALUE; - - /* - * select the proper Subtest(s) - */ - - switch (Subtest) { - - case XIL_TESTMEM_ALLMEMTESTS: - /* this case executes all of the Subtests */ - /* fall through case statement */ - - case XIL_TESTMEM_INCREMENT: - /* - * Fill the memory with incrementing - * values starting from 'FirtVal' - */ - for (I = 0L; I < Words; I++) { - /* write memory location */ - Addr[I] = Val; - Val++; - } - /* - * Restore the reference 'Val' to the - * initial value - */ - Val = FirtVal; - /* - * Check every word within the words - * of tested memory and compare it - * with the incrementing reference - * Val - */ - - for (I = 0L; I < Words; I++) { - /* read memory location */ - Word = Addr[I]; - if (Word != Val) { - return -1; - } - Val++; - } - - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 1 */ - - /* fall through case statement */ - - case XIL_TESTMEM_WALKONES: - /* - * set up to cycle through all possible initial - * test Patterns for walking ones test - */ - - for (J = 0L; J < 8; J++) { - /* - * Generate an initial value for walking ones test - * to test for bad data bits - */ - Val = 1 << J; - /* - * START walking ones test - * Write a one to each data bit indifferent locations - */ - for (I = 0L; I < 8; I++) { - /* write memory location */ - Addr[I] = Val; - Val = (u8)RotateLeft(Val, 8); - } - /* - * Restore the reference 'Val' to the - * initial value - */ - Val = 1 << J; - /* Read the values from each location that was written */ - for (I = 0L; I < 8; I++) { - /* read memory location */ - Word = Addr[I]; - if (Word != Val) { - return -1; - } - Val = (u8)RotateLeft(Val, 8); - } - } - - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 2 */ - /* fall through case statement */ - - case XIL_TESTMEM_WALKZEROS: - /* - * set up to cycle through all possible initial test - * Patterns for walking zeros test - */ - - for (J = 0L; J < 8; J++) { - /* - * Generate an initial value for walking ones test to test - * for bad data bits - */ - Val = ~(1 << J); - /* - * START walking zeros test - * Write a one to each data bit indifferent locations - */ - for (I = 0L; I < 8; I++) { - /* write memory location */ - Addr[I] = Val; - Val = ~((u8)RotateLeft(~Val, 8)); - } - /* - * Restore the reference 'Val' to the - * initial value - */ - Val = ~(1 << J); - /* Read the values from each location that was written */ - for (I = 0L; I < 8; I++) { - /* read memory location */ - Word = Addr[I]; - if (Word != Val) { - return -1; - } - - Val = ~((u8)RotateLeft(~Val, 8)); - } - } - - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 3 */ - /* fall through case statement */ - - case XIL_TESTMEM_INVERSEADDR: - /* Fill the memory with inverse of address */ - for (I = 0L; I < Words; I++) { - /* write memory location */ - Val = (u8) (~((u32) (&Addr[I]))); - Addr[I] = Val; - } - - /* - * Check every word within the words - * of tested memory - */ - - for (I = 0L; I < Words; I++) { - /* read memory location */ - Word = Addr[I]; - Val = (u8) (~((u32) (&Addr[I]))); - if ((Word ^ Val) != 0x00) { - return -1; - } - } - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - /* end of case 4 */ - /* fall through case statement */ - - case XIL_TESTMEM_FIXEDPATTERN: - /* - * Generate an initial value for - * memory testing - */ - - if (Pattern == 0) { - Val = 0xA5; - } - else { - Val = Pattern; - } - /* - * Fill the memory with fixed Pattern - */ - for (I = 0L; I < Words; I++) { - /* write memory location */ - Addr[I] = Val; - } - /* - * Check every word within the words - * of tested memory and compare it - * with the fixed Pattern - */ - - for (I = 0L; I < Words; I++) { - /* read memory location */ - Word = Addr[I]; - if (Word != Val) { - return -1; - } - } - - if (Subtest != XIL_TESTMEM_ALLMEMTESTS) { - return 0; - } - - /* end of case 5 */ - - /* this break is for the prior fall through case statements */ - - break; - - default: - return -1; - - } /* end of switch */ - - /* Successfully passed memory test ! */ - - return 0; -} - - -/*****************************************************************************/ -/** -* -* Rotates the provided value to the left one bit position -* -* @param Input is value to be rotated to the left -* @param Width is the number of bits in the input data -* -* @return -* -* The resulting unsigned long value of the rotate left -* -* @note -* -* None. -* -*****************************************************************************/ -static u32 RotateLeft(u32 Input, u8 Width) -{ - u32 Msb; - u32 ReturnVal; - u32 WidthMask; - u32 MsbMask; - - /* - * set up the WidthMask and the MsbMask - */ - - MsbMask = 1 << (Width - 1); - - WidthMask = (MsbMask << 1) - 1; - - /* - * set the Width of the Input to the correct width - */ - - Input = Input & WidthMask; - - Msb = Input & MsbMask; - - ReturnVal = Input << 1; - - if (Msb != 0x00000000) { - ReturnVal = ReturnVal | 0x00000001; - } - - ReturnVal = ReturnVal & WidthMask; - - return ReturnVal; - -} - -#ifdef ROTATE_RIGHT -/*****************************************************************************/ -/** -* -* Rotates the provided value to the right one bit position -* -* @param Input is value to be rotated to the right -* @param Width is the number of bits in the input data -* -* @return -* -* The resulting u32 value of the rotate right -* -* @note -* -* None. -* -*****************************************************************************/ -static u32 RotateRight(u32 Input, u8 Width) -{ - u32 Lsb; - u32 ReturnVal; - u32 WidthMask; - u32 MsbMask; - - /* - * set up the WidthMask and the MsbMask - */ - - MsbMask = 1 << (Width - 1); - - WidthMask = (MsbMask << 1) - 1; - - /* - * set the width of the input to the correct width - */ - - Input = Input & WidthMask; - - ReturnVal = Input >> 1; - - Lsb = Input & 0x00000001; - - if (Lsb != 0x00000000) { - ReturnVal = ReturnVal | MsbMask; - } - - ReturnVal = ReturnVal & WidthMask; - - return ReturnVal; - -} -#endif /* ROTATE_RIGHT */ - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_testmem.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_testmem.h deleted file mode 100644 index 74e131d5b17e69fa935887c6ba15c00f6a55d7c4..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_testmem.h +++ /dev/null @@ -1,173 +0,0 @@ -/****************************************************************************** -* -* -* (c) Copyright 2009 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_testmem.h -* -* This file contains utility functions to test memory. -* -* <b>Memory test description</b> -* -* A subset of the memory tests can be selected or all of the tests can be run -* in order. If there is an error detected by a subtest, the test stops and the -* failure code is returned. Further tests are not run even if all of the tests -* are selected. -* -* Subtest descriptions: -* <pre> -* XIL_TESTMEM_ALLMEMTESTS: -* Runs all of the following tests -* -* XIL_TESTMEM_INCREMENT: -* Incrementing Value Test. -* This test starts at 'XIL_TESTMEM_INIT_VALUE' and uses the -* incrementing value as the test value for memory. -* -* XIL_TESTMEM_WALKONES: -* Walking Ones Test. -* This test uses a walking '1' as the test value for memory. -* location 1 = 0x00000001 -* location 2 = 0x00000002 -* ... -* -* XIL_TESTMEM_WALKZEROS: -* Walking Zero's Test. -* This test uses the inverse value of the walking ones test -* as the test value for memory. -* location 1 = 0xFFFFFFFE -* location 2 = 0xFFFFFFFD -* ... -* -* XIL_TESTMEM_INVERSEADDR: -* Inverse Address Test. -* This test uses the inverse of the address of the location under test -* as the test value for memory. -* -* XIL_TESTMEM_FIXEDPATTERN: -* Fixed Pattern Test. -* This test uses the provided patters as the test value for memory. -* If zero is provided as the pattern the test uses '0xDEADBEEF". -* </pre> -* -* <i>WARNING</i> -* -* The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces -* have been set up. -* -* The address provided to the memory tests is not checked for -* validity except for the NULL case. It is possible to provide a code-space -* pointer for this test to start with and ultimately destroy executable code -* causing random failures. -* -* @note -* -* Used for spaces where the address range of the region is smaller than -* the data width. If the memory range is greater than 2 ** width, -* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will -* repeat on a boundry of a power of two making it more difficult to detect -* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR -* tests suffer the same problem. Ideally, if large blocks of memory are to be -* tested, break them up into smaller regions of memory to allow the test -* patterns used not to repeat over the region tested. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a hbm 08/25/09 First release -* </pre> -* -******************************************************************************/ - -#ifndef XIL_TESTMEM_H /* prevent circular inclusions */ -#define XIL_TESTMEM_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ -#include "xil_types.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - -/* xutil_memtest defines */ - -#define XIL_TESTMEM_INIT_VALUE 1 - -/** @name Memory subtests - * @{ - */ -/** - * See the detailed description of the subtests in the file description. - */ -#define XIL_TESTMEM_ALLMEMTESTS 0 -#define XIL_TESTMEM_INCREMENT 1 -#define XIL_TESTMEM_WALKONES 2 -#define XIL_TESTMEM_WALKZEROS 3 -#define XIL_TESTMEM_INVERSEADDR 4 -#define XIL_TESTMEM_FIXEDPATTERN 5 -#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN -/* @} */ - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - -/* xutil_testmem prototypes */ - -extern int Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest); -extern int Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest); -extern int Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_testmem.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_testmem.o deleted file mode 100644 index f38814230b78ce1b7ec39fa31d83d6b0ed9dedd0..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_testmem.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_types.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_types.h deleted file mode 100644 index f86329e8bd246e3bea2c47571ee75361f764c4c0..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xil_types.h +++ /dev/null @@ -1,160 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_types.h -* -* This file contains basic types for Xilinx software IP. - -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ------------------------------------------------------- -* 1.00a hbm 07/14/09 First release -* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros -* </pre> -* -******************************************************************************/ - -#ifndef XIL_TYPES_H /* prevent circular inclusions */ -#define XIL_TYPES_H /* by using protection macros */ - - -/************************** Constant Definitions *****************************/ - -#ifndef TRUE -# define TRUE 1 -#endif - -#ifndef FALSE -# define FALSE 0 -#endif - -#ifndef NULL -#define NULL 0 -#endif - -#define XIL_COMPONENT_IS_READY 0x11111111 /**< component has been initialized */ -#define XIL_COMPONENT_IS_STARTED 0x22222222 /**< component has been started */ - -/** @name New types - * New simple types. - * @{ - */ -#ifndef __KERNEL__ -#ifndef XBASIC_TYPES_H -/** - * guarded against xbasic_types.h. - */ -typedef unsigned char u8; -typedef unsigned short u16; -typedef unsigned long u32; - -#define __XUINT64__ -typedef struct -{ - u32 Upper; - u32 Lower; -} Xuint64; - -/*****************************************************************************/ -/** -* Return the most significant half of the 64 bit data type. -* -* @param x is the 64 bit word. -* -* @return The upper 32 bits of the 64 bit word. -* -* @note None. -* -******************************************************************************/ -#define XUINT64_MSW(x) ((x).Upper) - -/*****************************************************************************/ -/** -* Return the least significant half of the 64 bit data type. -* -* @param x is the 64 bit word. -* -* @return The lower 32 bits of the 64 bit word. -* -* @note None. -* -******************************************************************************/ -#define XUINT64_LSW(x) ((x).Lower) - -#endif /* XBASIC_TYPES_H */ - -/** - * xbasic_types.h does not typedef s* or u64 - */ -typedef unsigned long long u64; - -typedef char s8; -typedef short s16; -typedef long s32; -typedef long long s64; -#else -#include <linux/types.h> -#endif - - -/*@}*/ - - -/************************** Constant Definitions *****************************/ - -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -#ifndef NULL -#define NULL 0 -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xl2cc.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xl2cc.h deleted file mode 100644 index d7b4cfc94169710616a0067b09cdfc1ac6f8feaf..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xl2cc.h +++ /dev/null @@ -1,180 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2011-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -******************************************************************************/ -/*****************************************************************************/ -/** -* @file xl2cc.h -* -* This file contains the address definitions for the PL310 Level-2 Cache -* Controller. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- --------------------------------------------------- -* 1.00a sdm 02/01/10 Initial version -* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file -* 'xil_errata.h' for errata description -* </pre> -* -* @note -* -* None. -* -******************************************************************************/ - -#ifndef _XL2CC_H_ -#define _XL2CC_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/************************** Constant Definitions *****************************/ -/* L2CC Register Offsets */ -#define XPS_L2CC_ID_OFFSET 0x0000 -#define XPS_L2CC_TYPE_OFFSET 0x0004 -#define XPS_L2CC_CNTRL_OFFSET 0x0100 -#define XPS_L2CC_AUX_CNTRL_OFFSET 0x0104 -#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET 0x0108 -#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET 0x010C - -#define XPS_L2CC_EVNT_CNTRL_OFFSET 0x0200 -#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET 0x0204 -#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET 0x0208 -#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET 0x020C -#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET 0x0210 - -#define XPS_L2CC_IER_OFFSET 0x0214 /* Interrupt Mask */ -#define XPS_L2CC_IPR_OFFSET 0x0218 /* Masked interrupt status */ -#define XPS_L2CC_ISR_OFFSET 0x021C /* Raw Interrupt Status */ -#define XPS_L2CC_IAR_OFFSET 0x0220 /* Interrupt Clear */ - -#define XPS_L2CC_CACHE_SYNC_OFFSET 0x0730 /* Cache Sync */ -#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET 0x0740 /* Dummy Register for Cache Sync */ -#define XPS_L2CC_CACHE_INVLD_PA_OFFSET 0x0770 /* Cache Invalid by PA */ -#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET 0x077C /* Cache Invalid by Way */ -#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET 0x07B0 /* Cache Clean by PA */ -#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET 0x07B8 /* Cache Clean by Index */ -#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET 0x07BC /* Cache Clean by Way */ -#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET 0x07F0 /* Cache Invalidate and Clean by PA */ -#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET 0x07F8 /* Cache Invalidate and Clean by Index */ -#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET 0x07FC /* Cache Invalidate and Clean by Way */ - -#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET 0x0900 /* Cache Data Lockdown 0 by Way */ -#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET 0x0904 /* Cache Instruction Lockdown 0 by Way */ -#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET 0x0908 /* Cache Data Lockdown 1 by Way */ -#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET 0x090C /* Cache Instruction Lockdown 1 by Way */ -#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET 0x0910 /* Cache Data Lockdown 2 by Way */ -#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET 0x0914 /* Cache Instruction Lockdown 2 by Way */ -#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET 0x0918 /* Cache Data Lockdown 3 by Way */ -#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET 0x091C /* Cache Instruction Lockdown 3 by Way */ -#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET 0x0920 /* Cache Data Lockdown 4 by Way */ -#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET 0x0924 /* Cache Instruction Lockdown 4 by Way */ -#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET 0x0928 /* Cache Data Lockdown 5 by Way */ -#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET 0x092C /* Cache Instruction Lockdown 5 by Way */ -#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET 0x0930 /* Cache Data Lockdown 6 by Way */ -#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET 0x0934 /* Cache Instruction Lockdown 6 by Way */ -#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET 0x0938 /* Cache Data Lockdown 7 by Way */ -#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET 0x093C /* Cache Instruction Lockdown 7 by Way */ - -#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950 /* Cache Lockdown Line Enable */ -#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET 0x0954 /* Cache Unlock All Lines by Way */ - -#define XPS_L2CC_ADDR_FILTER_START_OFFSET 0x0C00 /* Start of address filtering */ -#define XPS_L2CC_ADDR_FILTER_END_OFFSET 0x0C04 /* Start of address filtering */ - -#define XPS_L2CC_DEBUG_CTRL_OFFSET 0x0F40 /* Debug Control Register */ - -/* XPS_L2CC_CNTRL_OFFSET bit masks */ -#define XPS_L2CC_ENABLE_MASK 0x00000001 /* enables the L2CC */ - -/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */ -#define XPS_L2CC_AUX_EBRESPE_MASK 0x40000000 /* Early BRESP Enable */ -#define XPS_L2CC_AUX_IPFE_MASK 0x20000000 /* Instruction Prefetch Enable */ -#define XPS_L2CC_AUX_DPFE_MASK 0x10000000 /* Data Prefetch Enable */ -#define XPS_L2CC_AUX_NSIC_MASK 0x08000000 /* Non-secure interrupt access control */ -#define XPS_L2CC_AUX_NSLE_MASK 0x04000000 /* Non-secure lockdown enable */ -#define XPS_L2CC_AUX_CRP_MASK 0x02000000 /* Cache replacement policy */ -#define XPS_L2CC_AUX_FWE_MASK 0x01800000 /* Force write allocate */ -#define XPS_L2CC_AUX_SAOE_MASK 0x00400000 /* Shared attribute override enable */ -#define XPS_L2CC_AUX_PE_MASK 0x00200000 /* Parity enable */ -#define XPS_L2CC_AUX_EMBE_MASK 0x00100000 /* Event monitor bus enable */ -#define XPS_L2CC_AUX_WAY_SIZE_MASK 0x000E0000 /* Way-size */ -#define XPS_L2CC_AUX_ASSOC_MASK 0x00010000 /* Associativity */ -#define XPS_L2CC_AUX_SAIE_MASK 0x00002000 /* Shared attribute invalidate enable */ -#define XPS_L2CC_AUX_EXCL_CACHE_MASK 0x00001000 /* Exclusive cache configuration */ -#define XPS_L2CC_AUX_SBDLE_MASK 0x00000800 /* Store buffer device limitation Enable */ -#define XPS_L2CC_AUX_HPSODRE_MASK 0x00000400 /* High Priority for SO and Dev Reads Enable */ -#define XPS_L2CC_AUX_FLZE_MASK 0x00000001 /* Full line of zero enable */ - -#define XPS_L2CC_AUX_REG_DEFAULT_MASK 0x72360000 /* Enable all prefetching, */ - /* Cache replacement policy, Parity enable, */ - /* Event monitor bus enable and Way Size (64 KB) */ -#define XPS_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFF /* */ - -#define XPS_L2CC_TAG_RAM_DEFAULT_MASK 0x00000111 /* latency for TAG RAM */ -#define XPS_L2CC_DATA_RAM_DEFAULT_MASK 0x00000121 /* latency for DATA RAM */ - -/* Interrupt bit masks */ -#define XPS_L2CC_IXR_DECERR_MASK 0x00000100 /* DECERR from L3 */ -#define XPS_L2CC_IXR_SLVERR_MASK 0x00000080 /* SLVERR from L3 */ -#define XPS_L2CC_IXR_ERRRD_MASK 0x00000040 /* Error on L2 data RAM (Read) */ -#define XPS_L2CC_IXR_ERRRT_MASK 0x00000020 /* Error on L2 tag RAM (Read) */ -#define XPS_L2CC_IXR_ERRWD_MASK 0x00000010 /* Error on L2 data RAM (Write) */ -#define XPS_L2CC_IXR_ERRWT_MASK 0x00000008 /* Error on L2 tag RAM (Write) */ -#define XPS_L2CC_IXR_PARRD_MASK 0x00000004 /* Parity Error on L2 data RAM (Read) */ -#define XPS_L2CC_IXR_PARRT_MASK 0x00000002 /* Parity Error on L2 tag RAM (Read) */ -#define XPS_L2CC_IXR_ECNTR_MASK 0x00000001 /* Event Counter1/0 Overflow Increment */ - -/* Address filtering mask and enable bit */ -#define XPS_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000 /* Address filtering valid bits*/ -#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001 /* Address filtering enable bit*/ - -/* Debug control bits */ -#define XPS_L2CC_DEBUG_SPIDEN_MASK 0x00000004 /* Debug SPIDEN bit */ -#define XPS_L2CC_DEBUG_DWB_MASK 0x00000002 /* Debug DWB bit, forces write through */ -#define XPS_L2CC_DEBUG_DCL_MASK 0x00000002 /* Debug DCL bit, disables cache line fill */ - -#ifdef __cplusplus -} -#endif - -#endif /* protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xl2cc_counter.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xl2cc_counter.c deleted file mode 100644 index b17d21734560653f4b0de9efa60ab2ad35cc8bce..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xl2cc_counter.c +++ /dev/null @@ -1,174 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2011-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xl2cc_counter.c -* -* This file contains APIs for configuring and controlling the event counters -* in PL310 L2 cache controller. For more information about the event counters, -* see xl2cc_counter.h. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a sdm 07/11/11 First release -* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address -* inside the APIs -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include <stdint.h> -#include "xparameters_ps.h" -#include "xl2cc_counter.h" -#include "xl2cc.h" - -/************************** Constant Definitions ****************************/ - -/**************************** Type Definitions ******************************/ - -/***************** Macros (Inline Functions) Definitions ********************/ - -/************************** Variable Definitions *****************************/ - -/************************** Function Prototypes ******************************/ - -void XL2cc_EventCtrReset(void); - -/******************************************************************************/ - -/****************************************************************************/ -/** -* -* This function initializes the event counters in L2 Cache controller with a -* set of event codes specified by the user. -* -* @param Event0 is the event code for counter 0. -* @param Event1 is the event code for counter 1. -* Use the event codes defined by XL2CC_* in xl2cc_counter.h. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XL2cc_EventCtrInit(int Event0, int Event1) -{ - - /* Write event code into cnt1 cfg reg */ - *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_CTRL_OFFSET)) = (Event1 << 2); - - /* Write event code into cnt0 cfg reg */ - *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_CTRL_OFFSET)) = (Event0 << 2); - - /* Reset counters */ - XL2cc_EventCtrReset(); -} - -/****************************************************************************/ -/** -* -* This function starts the event counters in L2 Cache controller. -* -* @param None. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XL2cc_EventCtrStart(void) -{ - XL2cc_EventCtrReset(); - - /* Enable counter */ - *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 1; -} - -/****************************************************************************/ -/** -* -* This function disables the event counters in L2 Cache controller, saves the -* counter values and resets the counters. -* -* @param EveCtr0 is an output parameter which is used to return the value -* in event counter 0. -* EveCtr1 is an output parameter which is used to return the value -* in event counter 1. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1) -{ - /* Disable counter */ - *((volatile u32*) (XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0; - - /* Save counter values */ - *EveCtr1 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_VAL_OFFSET)); - *EveCtr0 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_VAL_OFFSET)); - - XL2cc_EventCtrReset(); -} - -/****************************************************************************/ -/** -* -* This function resets the event counters in L2 Cache controller. -* -* @param None. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XL2cc_EventCtrReset(void) -{ - *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0x6; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xl2cc_counter.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xl2cc_counter.h deleted file mode 100644 index 30952b1dca611777b10c00f66d7dab8074fcad89..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xl2cc_counter.h +++ /dev/null @@ -1,117 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2011-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xl2cc_counter.h -* -* This header file contains APIs for configuring and controlling the event -* counters in PL310 L2 cache controller. -* PL310 has 2 event counters which can be used to count a variety of events -* like DRHIT, DRREQ, DWHIT, DWREQ, etc. This file defines configurations, -* where value configures the event counters to count a set of events. -* -* XL2cc_EventCtrInit API can be used to select a set of events and -* XL2cc_EventCtrStart configures the event counters and starts the counters. -* XL2cc_EventCtrStop diables the event counters and returns the counter values. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a sdm 07/11/11 First release -* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address -* inside the APIs -* </pre> -* -******************************************************************************/ - -#ifndef L2CCCOUNTER_H /* prevent circular inclusions */ -#define L2CCCOUNTER_H /* by using protection macros */ - -/***************************** Include Files ********************************/ - -#include "xpseudo_asm.h" -#include "xil_types.h" - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/************************** Constant Definitions ****************************/ - -/* - * The following constants define the event codes for the event counters. - */ -#define XL2CC_CO 0x1 -#define XL2CC_DRHIT 0x2 -#define XL2CC_DRREQ 0x3 -#define XL2CC_DWHIT 0x4 -#define XL2CC_DWREQ 0x5 -#define XL2CC_DWTREQ 0x6 -#define XL2CC_IRHIT 0x7 -#define XL2CC_IRREQ 0x8 -#define XL2CC_WA 0x9 -#define XL2CC_IPFALLOC 0xa -#define XL2CC_EPFHIT 0xb -#define XL2CC_EPFALLOC 0xc -#define XL2CC_SRRCVD 0xd -#define XL2CC_SRCONF 0xe -#define XL2CC_EPFRCVD 0xf - -/**************************** Type Definitions ******************************/ - -/***************** Macros (Inline Functions) Definitions ********************/ - -/************************** Variable Definitions ****************************/ - -/************************** Function Prototypes *****************************/ - -void XL2cc_EventCtrInit(int Event0, int Event1); -void XL2cc_EventCtrStart(void); -void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* L2CCCOUNTER_H */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xl2cc_counter.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xl2cc_counter.o deleted file mode 100644 index 7cbe2da8bc78fba49b78e758494fa21826c5cba3..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xl2cc_counter.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xparameters_ps.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xparameters_ps.h deleted file mode 100644 index 766e1705ba39fb5d731e58776a41fc0787e63626..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xparameters_ps.h +++ /dev/null @@ -1,334 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -******************************************************************************/ -/*****************************************************************************/ -/** -* @file xparameters_ps.h -* -* This file contains the address definitions for the hard peripherals -* attached to the ARM Cortex A9 core. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------- -------- --------------------------------------------------- -* 1.00a ecm/sdm 02/01/10 Initial version -* 3.04a sdm 02/02/12 Removed some of the defines as they are being generated through -* driver tcl -* </pre> -* -* @note -* -* None. -* -******************************************************************************/ - -#ifndef _XPARAMETERS_PS_H_ -#define _XPARAMETERS_PS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/************************** Constant Definitions *****************************/ - -/* - * This block contains constant declarations for the peripherals - * within the hardblock - */ - -/* Canonical definitions for DDR MEMORY */ -#define XPAR_DDR_MEM_BASEADDR 0x00000000 -#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFF - -/* Canonical definitions for Interrupts */ -#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID -#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID -#define XPAR_XUSBPS_0_INTR XPS_USB0_INT_ID -#define XPAR_XUSBPS_1_INTR XPS_USB1_INT_ID -#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID -#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID -#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID -#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID -#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID -#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID -#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID -#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID -#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID -#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID -#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID -#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID -#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID -#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID -#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID -#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID -#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID -#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID -#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID -#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID -#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID -#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID -#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID -#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID -#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID -#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID -#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID -#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID -#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID -#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID -#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID -#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID -#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID - - -#define XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR -#define XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR - - - -/* Canonical definitions for DMAC */ - - -/* Canonical definitions for WDT */ - -/* Canonical definitions for SLCR */ -#define XPAR_XSLCR_NUM_INSTANCES 1 -#define XPAR_XSLCR_0_DEVICE_ID 0 -#define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR - -/* Canonical definitions for SCU GIC */ -#define XPAR_SCUGIC_NUM_INSTANCES 1 -#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0 -#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x0100) -#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x1000) -#define XPAR_SCUGIC_ACK_BEFORE 0 - -/* Canonical definitions for Global Timer */ -#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1 -#define XPAR_GLOBAL_TMR_DEVICE_ID 0 -#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x200) -#define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID - - -/* Xilinx Parallel Flash Library (XilFlash) User Settings */ -#define XPAR_AXI_EMC - - -#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ - - -/* - * This block contains constant declarations for the peripherals - * within the hardblock. These have been put for bacwards compatibilty - */ - -#define XPS_PERIPHERAL_BASEADDR 0xE0000000 -#define XPS_UART0_BASEADDR 0xE0000000 -#define XPS_UART1_BASEADDR 0xE0001000 -#define XPS_USB0_BASEADDR 0xE0002000 -#define XPS_USB1_BASEADDR 0xE0003000 -#define XPS_I2C0_BASEADDR 0xE0004000 -#define XPS_I2C1_BASEADDR 0xE0005000 -#define XPS_SPI0_BASEADDR 0xE0006000 -#define XPS_SPI1_BASEADDR 0xE0007000 -#define XPS_CAN0_BASEADDR 0xE0008000 -#define XPS_CAN1_BASEADDR 0xE0009000 -#define XPS_GPIO_BASEADDR 0xE000A000 -#define XPS_GEM0_BASEADDR 0xE000B000 -#define XPS_GEM1_BASEADDR 0xE000C000 -#define XPS_QSPI_BASEADDR 0xE000D000 -#define XPS_PARPORT_CRTL_BASEADDR 0xE000E000 -#define XPS_SDIO0_BASEADDR 0xE0100000 -#define XPS_SDIO1_BASEADDR 0xE0101000 -#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000 -#define XPS_NAND_BASEADDR 0xE1000000 -#define XPS_PARPORT0_BASEADDR 0xE2000000 -#define XPS_PARPORT1_BASEADDR 0xE4000000 -#define XPS_QSPI_LINEAR_BASEADDR 0xFC000000 -#define XPS_SYS_CTRL_BASEADDR 0xF8000000 /* AKA SLCR */ -#define XPS_TTC0_BASEADDR 0xF8001000 -#define XPS_TTC1_BASEADDR 0xF8002000 -#define XPS_DMAC0_SEC_BASEADDR 0xF8003000 -#define XPS_DMAC0_NON_SEC_BASEADDR 0xF8004000 -#define XPS_WDT_BASEADDR 0xF8005000 -#define XPS_DDR_CTRL_BASEADDR 0xF8006000 -#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000 -#define XPS_AFI0_BASEADDR 0xF8008000 -#define XPS_AFI1_BASEADDR 0xF8009000 -#define XPS_AFI2_BASEADDR 0xF800A000 -#define XPS_AFI3_BASEADDR 0xF800B000 -#define XPS_OCM_BASEADDR 0xF800C000 -#define XPS_EFUSE_BASEADDR 0xF800D000 -#define XPS_CORESIGHT_BASEADDR 0xF8800000 -#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000 -#define XPS_SCU_PERIPH_BASE 0xF8F00000 -#define XPS_L2CC_BASEADDR 0xF8F02000 -#define XPS_SAM_RAM_BASEADDR 0xFFFC0000 -#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000 -#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000 -#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000 -#define XPS_PERIPH_APB_BASEADDR 0xF8000000 - -/* Shared Peripheral Interrupts (SPI) */ -#define XPS_CORE_PARITY0_INT_ID 32 -#define XPS_CORE_PARITY1_INT_ID 33 -#define XPS_L2CC_INT_ID 34 -#define XPS_OCMINTR_INT_ID 35 -#define XPS_ECC_INT_ID 36 -#define XPS_PMU0_INT_ID 37 -#define XPS_PMU1_INT_ID 38 -#define XPS_SYSMON_INT_ID 39 -#define XPS_DVC_INT_ID 40 -#define XPS_WDT_INT_ID 41 -#define XPS_TTC0_0_INT_ID 42 -#define XPS_TTC0_1_INT_ID 43 -#define XPS_TTC0_2_INT_ID 44 -#define XPS_DMA0_ABORT_INT_ID 45 -#define XPS_DMA0_INT_ID 46 -#define XPS_DMA1_INT_ID 47 -#define XPS_DMA2_INT_ID 48 -#define XPS_DMA3_INT_ID 49 -#define XPS_SMC_INT_ID 50 -#define XPS_QSPI_INT_ID 51 -#define XPS_GPIO_INT_ID 52 -#define XPS_USB0_INT_ID 53 -#define XPS_GEM0_INT_ID 54 -#define XPS_GEM0_WAKE_INT_ID 55 -#define XPS_SDIO0_INT_ID 56 -#define XPS_I2C0_INT_ID 57 -#define XPS_SPI0_INT_ID 58 -#define XPS_UART0_INT_ID 59 -#define XPS_CAN0_INT_ID 60 -#define XPS_FPGA0_INT_ID 61 -#define XPS_FPGA1_INT_ID 62 -#define XPS_FPGA2_INT_ID 63 -#define XPS_FPGA3_INT_ID 64 -#define XPS_FPGA4_INT_ID 65 -#define XPS_FPGA5_INT_ID 66 -#define XPS_FPGA6_INT_ID 67 -#define XPS_FPGA7_INT_ID 68 -#define XPS_TTC1_0_INT_ID 69 -#define XPS_TTC1_1_INT_ID 70 -#define XPS_TTC1_2_INT_ID 71 -#define XPS_DMA4_INT_ID 72 -#define XPS_DMA5_INT_ID 73 -#define XPS_DMA6_INT_ID 74 -#define XPS_DMA7_INT_ID 75 -#define XPS_USB1_INT_ID 76 -#define XPS_GEM1_INT_ID 77 -#define XPS_GEM1_WAKE_INT_ID 78 -#define XPS_SDIO1_INT_ID 79 -#define XPS_I2C1_INT_ID 80 -#define XPS_SPI1_INT_ID 81 -#define XPS_UART1_INT_ID 82 -#define XPS_CAN1_INT_ID 83 -#define XPS_FPGA8_INT_ID 84 -#define XPS_FPGA9_INT_ID 85 -#define XPS_FPGA10_INT_ID 86 -#define XPS_FPGA11_INT_ID 87 -#define XPS_FPGA12_INT_ID 88 -#define XPS_FPGA13_INT_ID 89 -#define XPS_FPGA14_INT_ID 90 -#define XPS_FPGA15_INT_ID 91 - -/* Private Peripheral Interrupts (PPI) */ -#define XPS_GLOBAL_TMR_INT_ID 27 /* SCU Global Timer interrupt */ -#define XPS_FIQ_INT_ID 28 /* FIQ from FPGA fabric */ -#define XPS_SCU_TMR_INT_ID 29 /* SCU Private Timer interrupt */ -#define XPS_SCU_WDT_INT_ID 30 /* SCU Private WDT interrupt */ -#define XPS_IRQ_INT_ID 31 /* IRQ from FPGA fabric */ - - -/* REDEFINES for TEST APP */ -/* Definitions for UART */ -#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID -#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID -#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID -#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID -#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID -#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID -#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID -#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID -#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID -#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID -#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID -#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID -#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID -#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID -#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID -#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID -#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID -#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID -#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID -#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID - -#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID - -/* For backwards compatibilty */ -#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ -#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ -#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ -#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ -#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ -#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ -#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ -#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ -#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ -#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ - -#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ - -#ifdef XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ -#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ -#endif - -#ifdef XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ -#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ -#endif - -#define XPAR_SCUTIMER_DEVICE_ID 0 -#define XPAR_SCUWDT_DEVICE_ID 0 - - -#ifdef __cplusplus -} -#endif - -#endif /* protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xpm_counter.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xpm_counter.c deleted file mode 100644 index 93304b989a10f62495fa94deda3b42512ba6d380..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xpm_counter.c +++ /dev/null @@ -1,304 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2011-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xpm_counter.c -* -* This file contains APIs for configuring and controlling the Cortex-A9 -* Performance Monitor Events. For more information about the event counters, -* see xpm_counter.h. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a sdm 07/11/11 First release -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xpm_counter.h" - -/************************** Constant Definitions ****************************/ - -/**************************** Type Definitions ******************************/ - -typedef const u32 PmcrEventCfg[XPM_CTRCOUNT]; - -/***************** Macros (Inline Functions) Definitions ********************/ - -/************************** Variable Definitions *****************************/ - -static PmcrEventCfg PmcrEvents[] = { - { - XPM_EVENT_SOFTINCR, - XPM_EVENT_INSRFETCH_CACHEREFILL, - XPM_EVENT_INSTRFECT_TLBREFILL, - XPM_EVENT_DATA_CACHEREFILL, - XPM_EVENT_DATA_CACHEACCESS, - XPM_EVENT_DATA_TLBREFILL - }, - { - XPM_EVENT_DATA_READS, - XPM_EVENT_DATA_WRITE, - XPM_EVENT_EXCEPTION, - XPM_EVENT_EXCEPRETURN, - XPM_EVENT_CHANGECONTEXT, - XPM_EVENT_SW_CHANGEPC - }, - { - XPM_EVENT_IMMEDBRANCH, - XPM_EVENT_UNALIGNEDACCESS, - XPM_EVENT_BRANCHMISS, - XPM_EVENT_CLOCKCYCLES, - XPM_EVENT_BRANCHPREDICT, - XPM_EVENT_JAVABYTECODE - }, - { - XPM_EVENT_SWJAVABYTECODE, - XPM_EVENT_JAVABACKBRANCH, - XPM_EVENT_COHERLINEMISS, - XPM_EVENT_COHERLINEHIT, - XPM_EVENT_INSTRSTALL, - XPM_EVENT_DATASTALL - }, - { - XPM_EVENT_MAINTLBSTALL, - XPM_EVENT_STREXPASS, - XPM_EVENT_STREXFAIL, - XPM_EVENT_DATAEVICT, - XPM_EVENT_NODISPATCH, - XPM_EVENT_ISSUEEMPTY - }, - { - XPM_EVENT_INSTRRENAME, - XPM_EVENT_PREDICTFUNCRET, - XPM_EVENT_MAINEXEC, - XPM_EVENT_SECEXEC, - XPM_EVENT_LDRSTR, - XPM_EVENT_FLOATRENAME - }, - { - XPM_EVENT_NEONRENAME, - XPM_EVENT_PLDSTALL, - XPM_EVENT_WRITESTALL, - XPM_EVENT_INSTRTLBSTALL, - XPM_EVENT_DATATLBSTALL, - XPM_EVENT_INSTR_uTLBSTALL - }, - { - XPM_EVENT_DATA_uTLBSTALL, - XPM_EVENT_DMB_STALL, - XPM_EVENT_INT_CLKEN, - XPM_EVENT_DE_CLKEN, - XPM_EVENT_INSTRISB, - XPM_EVENT_INSTRDSB - }, - { - XPM_EVENT_INSTRDMB, - XPM_EVENT_EXTINT, - XPM_EVENT_PLE_LRC, - XPM_EVENT_PLE_LRS, - XPM_EVENT_PLE_FLUSH, - XPM_EVENT_PLE_CMPL - }, - { - XPM_EVENT_PLE_OVFL, - XPM_EVENT_PLE_PROG, - XPM_EVENT_PLE_LRC, - XPM_EVENT_PLE_LRS, - XPM_EVENT_PLE_FLUSH, - XPM_EVENT_PLE_CMPL - }, - { - XPM_EVENT_DATASTALL, - XPM_EVENT_INSRFETCH_CACHEREFILL, - XPM_EVENT_INSTRFECT_TLBREFILL, - XPM_EVENT_DATA_CACHEREFILL, - XPM_EVENT_DATA_CACHEACCESS, - XPM_EVENT_DATA_TLBREFILL - }, -}; - -/************************** Function Prototypes ******************************/ - -void Xpm_DisableEventCounters(void); -void Xpm_EnableEventCounters (void); -void Xpm_ResetEventCounters (void); - -/******************************************************************************/ - -/****************************************************************************/ -/** -* -* This function disables the Cortex A9 event counters. -* -* @param None. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void Xpm_DisableEventCounters(void) -{ - /* Disable the event counters */ - mtcp(XREG_CP15_COUNT_ENABLE_CLR, 0x3f); -} - -/****************************************************************************/ -/** -* -* This function enables the Cortex A9 event counters. -* -* @param None. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void Xpm_EnableEventCounters(void) -{ - /* Enable the event counters */ - mtcp(XREG_CP15_COUNT_ENABLE_SET, 0x3f); -} - -/****************************************************************************/ -/** -* -* This function resets the Cortex A9 event counters. -* -* @param None. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void Xpm_ResetEventCounters(void) -{ - u32 Reg; - -#ifdef __GNUC__ - Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL); -#elif defined (__ICCARM__) - mfcp(XREG_CP15_PERF_MONITOR_CTRL, Reg); -#else - { register unsigned int C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL); - Reg = C15Reg; } -#endif - Reg |= (1 << 2); /* reset event counters */ - mtcp(XREG_CP15_PERF_MONITOR_CTRL, Reg); -} - -/****************************************************************************/ -/** -* -* This function configures the Cortex A9 event counters controller, with the -* event codes, in a configuration selected by the user and enables the counters. -* -* @param PmcrCfg is configuration value based on which the event counters -* are configured. -* Use XPM_CNTRCFG* values defined in xpm_counter.h. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void Xpm_SetEvents(int PmcrCfg) -{ - u32 Counter; - const u32 *Ptr = PmcrEvents[PmcrCfg]; - - Xpm_DisableEventCounters(); - - for(Counter = 0; Counter < XPM_CTRCOUNT; Counter++) { - - /* Selecet event counter */ - mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter); - - /* Set the event */ - mtcp(XREG_CP15_EVENT_TYPE_SEL, Ptr[Counter]); - } - - Xpm_ResetEventCounters(); - Xpm_EnableEventCounters(); -} - -/****************************************************************************/ -/** -* -* This function disables the event counters and returns the counter values. -* -* @param PmCtrValue is a pointer to an array of type u32 PmCtrValue[6]. -* It is an output parameter which is used to return the PM -* counter values. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void Xpm_GetEventCounters(u32 *PmCtrValue) -{ - u32 Counter; - - Xpm_DisableEventCounters(); - - for(Counter = 0; Counter < XPM_CTRCOUNT; Counter++) { - - mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter); -#ifdef __GNUC__ - PmCtrValue[Counter] = mfcp(XREG_CP15_PERF_MONITOR_COUNT); -#elif defined (__ICCARM__) - mfcp(XREG_CP15_PERF_MONITOR_COUNT, PmCtrValue[Counter]); -#else - { register unsigned int Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT); - PmCtrValue[Counter] = Cp15Reg; } -#endif - } -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xpm_counter.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xpm_counter.h deleted file mode 100644 index 2ef3f9fab63565cc936f87c2335dd090f786c114..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xpm_counter.h +++ /dev/null @@ -1,580 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2011-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xpm_counter.h -* -* This header file contains APIs for configuring and controlling the Cortex-A9 -* Performance Monitor Events. -* Cortex-A9 Performance Monitor has 6 event counters which can be used to -* count a variety of events described in Coretx-A9 TRM. This file defines -* configurations, where value configures the event counters to count a -* set of events. -* -* Xpm_SetEvents can be used to set the event counters to count a set of events -* and Xpm_GetEventCounters can be used to read the counter values. -* -* @note -* -* This file doesn't handle the Cortex-A9 cycle counter, as the cycle counter is -* being used for time keeping. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a sdm 07/11/11 First release -* </pre> -* -******************************************************************************/ - -#ifndef XPMCOUNTER_H /* prevent circular inclusions */ -#define XPMCOUNTER_H /* by using protection macros */ - -/***************************** Include Files ********************************/ - -#include <stdint.h> -#include "xpseudo_asm.h" -#include "xil_types.h" - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/************************** Constant Definitions ****************************/ - -/* Number of performance counters */ -#define XPM_CTRCOUNT 6 - -/* The following constants define the Cortex-A9 Performance Monitor Events */ - -/* - * Software increment. The register is incremented only on writes to the - * Software Increment Register - */ -#define XPM_EVENT_SOFTINCR 0x00 - -/* - * Instruction fetch that causes a refill at (at least) the lowest level(s) of - * instruction or unified cache. Includes the speculative linefills in the - * count - */ -#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01 - -/* - * Instruction fetch that causes a TLB refill at (at least) the lowest level of - * TLB. Includes the speculative requests in the count - */ -#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02 - -/* - * Data read or write operation that causes a refill at (at least) the lowest - * level(s)of data or unified cache. Counts the number of allocations performed - * in the Data Cache due to a read or a write - */ -#define XPM_EVENT_DATA_CACHEREFILL 0x03 - -/* - * Data read or write operation that causes a cache access at (at least) the - * lowest level(s) of data or unified cache. This includes speculative reads - */ -#define XPM_EVENT_DATA_CACHEACCESS 0x04 - -/* - * Data read or write operation that causes a TLB refill at (at least) the - * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI, - * CP15 Cache operation by MVA and CP15 VA to PA operations - */ -#define XPM_EVENT_DATA_TLBREFILL 0x05 - -/* - * Data read architecturally executed. Counts the number of data read - * instructions accepted by the Load Store Unit. This includes counting the - * speculative and aborted LDR/LDM, as well as the reads due to the SWP - * instructions - */ -#define XPM_EVENT_DATA_READS 0x06 - -/* - * Data write architecturally executed. Counts the number of data write - * instructions accepted by the Load Store Unit. This includes counting the - * speculative and aborted STR/STM, as well as the writes due to the SWP - * instructions - */ -#define XPM_EVENT_DATA_WRITE 0x07 - -/* Exception taken. Counts the number of exceptions architecturally taken.*/ -#define XPM_EVENT_EXCEPTION 0x09 - -/* Exception return architecturally executed.*/ -#define XPM_EVENT_EXCEPRETURN 0x0A - -/* - * Change to ContextID retired. Counts the number of instructions - * architecturally executed writing into the ContextID Register - */ -#define XPM_EVENT_CHANGECONTEXT 0x0B - -/* - * Software change of PC, except by an exception, architecturally executed. - * Count the number of PC changes architecturally executed, excluding the PC - * changes due to taken exceptions - */ -#define XPM_EVENT_SW_CHANGEPC 0x0C - -/* - * Immediate branch architecturally executed (taken or not taken). This includes - * the branches which are flushed due to a previous load/store which aborts - * late - */ -#define XPM_EVENT_IMMEDBRANCH 0x0D - -/* - * Unaligned access architecturally executed. Counts the number of aborted - * unaligned accessed architecturally executed, and the number of not-aborted - * unaligned accesses, including the speculative ones - */ -#define XPM_EVENT_UNALIGNEDACCESS 0x0F - -/* - * Branch mispredicted/not predicted. Counts the number of mispredicted or - * not-predicted branches executed. This includes the branches which are flushed - * due to a previous load/store which aborts late - */ -#define XPM_EVENT_BRANCHMISS 0x10 - -/* - * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This - * event is not exported on the PMUEVENT bus - */ -#define XPM_EVENT_CLOCKCYCLES 0x11 - -/* - * Branches or other change in program flow that could have been predicted by - * the branch prediction resources of the processor. This includes the branches - * which are flushed due to a previous load/store which aborts late - */ -#define XPM_EVENT_BRANCHPREDICT 0x12 - -/* - * Java bytecode execute. Counts the number of Java bytecodes being decoded, - * including speculative ones - */ -#define XPM_EVENT_JAVABYTECODE 0x40 - -/* - * Software Java bytecode executed. Counts the number of software java bytecodes - * being decoded, including speculative ones - */ -#define XPM_EVENT_SWJAVABYTECODE 0x41 - -/* - * Jazelle backward branches executed. Counts the number of Jazelle taken - * branches being executed. This includes the branches which are flushed due - * to a previous load/store which aborts late - */ -#define XPM_EVENT_JAVABACKBRANCH 0x42 - -/* - * Coherent linefill miss Counts the number of coherent linefill requests - * performed by the Cortex-A9 processor which also miss in all the other - * Cortex-A9 processors, meaning that the request is sent to the external - * memory - */ -#define XPM_EVENT_COHERLINEMISS 0x50 - -/* - * Coherent linefill hit. Counts the number of coherent linefill requests - * performed by the Cortex-A9 processor which hit in another Cortex-A9 - * processor, meaning that the linefill data is fetched directly from the - * relevant Cortex-A9 cache - */ -#define XPM_EVENT_COHERLINEHIT 0x51 - -/* - * Instruction cache dependent stall cycles. Counts the number of cycles where - * the processor is ready to accept new instructions, but does not receive any - * due to the instruction side not being able to provide any and the - * instruction cache is currently performing at least one linefill - */ -#define XPM_EVENT_INSTRSTALL 0x60 - -/* - * Data cache dependent stall cycles. Counts the number of cycles where the core - * has some instructions that it cannot issue to any pipeline, and the Load - * Store unit has at least one pending linefill request, and no pending - */ -#define XPM_EVENT_DATASTALL 0x61 - -/* - * Main TLB miss stall cycles. Counts the number of cycles where the processor - * is stalled waiting for the completion of translation table walks from the - * main TLB. The processor stalls can be due to the instruction side not being - * able to provide the instructions, or to the data side not being able to - * provide the necessary data, due to them waiting for the main TLB translation - * table walk to complete - */ -#define XPM_EVENT_MAINTLBSTALL 0x62 - -/* - * Counts the number of STREX instructions architecturally executed and - * passed - */ -#define XPM_EVENT_STREXPASS 0x63 - -/* - * Counts the number of STREX instructions architecturally executed and - * failed - */ -#define XPM_EVENT_STREXFAIL 0x64 - -/* - * Data eviction. Counts the number of eviction requests due to a linefill in - * the data cache - */ -#define XPM_EVENT_DATAEVICT 0x65 - -/* - * Counts the number of cycles where the issue stage does not dispatch any - * instruction because it is empty or cannot dispatch any instructions - */ -#define XPM_EVENT_NODISPATCH 0x66 - -/* - * Counts the number of cycles where the issue stage is empty - */ -#define XPM_EVENT_ISSUEEMPTY 0x67 - -/* - * Counts the number of instructions going through the Register Renaming stage. - * This number is an approximate number of the total number of instructions - * speculatively executed, and even more approximate of the total number of - * instructions architecturally executed. The approximation depends mainly on - * the branch misprediction rate. - * The renaming stage can handle two instructions in the same cycle so the event - * is two bits long: - * - b00 no instructions renamed - * - b01 one instruction renamed - * - b10 two instructions renamed - */ -#define XPM_EVENT_INSTRRENAME 0x68 - -/* - * Counts the number of procedure returns whose condition codes do not fail, - * excluding all returns from exception. This count includes procedure returns - * which are flushed due to a previous load/store which aborts late. - * Only the following instructions are reported: - * - BX R14 - * - MOV PC LR - * - POP {..,pc} - * - LDR pc,[sp],#offset - * The following instructions are not reported: - * - LDMIA R9!,{..,PC} (ThumbEE state only) - * - LDR PC,[R9],#offset (ThumbEE state only) - * - BX R0 (Rm != R14) - * - MOV PC,R0 (Rm != R14) - * - LDM SP,{...,PC} (writeback not specified) - * - LDR PC,[SP,#offset] (wrong addressing mode) - */ -#define XPM_EVENT_PREDICTFUNCRET 0x6E - -/* - * Counts the number of instructions being executed in the main execution - * pipeline of the processor, the multiply pipeline and arithmetic logic unit - * pipeline. The counted instructions are still speculative - */ -#define XPM_EVENT_MAINEXEC 0x70 - -/* - * Counts the number of instructions being executed in the processor second - * execution pipeline (ALU). The counted instructions are still speculative - */ -#define XPM_EVENT_SECEXEC 0x71 - -/* - * Counts the number of instructions being executed in the Load/Store unit. The - * counted instructions are still speculative - */ -#define XPM_EVENT_LDRSTR 0x72 - -/* - * Counts the number of Floating-point instructions going through the Register - * Rename stage. Instructions are still speculative in this stage. - *Two floating-point instructions can be renamed in the same cycle so the event - * is two bitslong: - *0b00 no floating-point instruction renamed - *0b01 one floating-point instruction renamed - *0b10 two floating-point instructions renamed - */ -#define XPM_EVENT_FLOATRENAME 0x73 - -/* - * Counts the number of Neon instructions going through the Register Rename - * stage.Instructions are still speculative in this stage. - * Two NEON instructions can be renamed in the same cycle so the event is two - * bits long: - *0b00 no NEON instruction renamed - *0b01 one NEON instruction renamed - *0b10 two NEON instructions renamed - */ -#define XPM_EVENT_NEONRENAME 0x74 - -/* - * Counts the number of cycles where the processor is stalled because PLD slots - * are all full - */ -#define XPM_EVENT_PLDSTALL 0x80 - -/* - * Counts the number of cycles when the processor is stalled and the data side - * is stalled too because it is full and executing writes to the external - * memory - */ -#define XPM_EVENT_WRITESTALL 0x81 - -/* - * Counts the number of stall cycles due to main TLB misses on requests issued - * by the instruction side - */ -#define XPM_EVENT_INSTRTLBSTALL 0x82 - -/* - * Counts the number of stall cycles due to main TLB misses on requests issued - * by the data side - */ -#define XPM_EVENT_DATATLBSTALL 0x83 - -/* - * Counts the number of stall cycles due to micro TLB misses on the instruction - * side. This event does not include main TLB miss stall cycles that are already - * counted in the corresponding main TLB event - */ -#define XPM_EVENT_INSTR_uTLBSTALL 0x84 - -/* - * Counts the number of stall cycles due to micro TLB misses on the data side. - * This event does not include main TLB miss stall cycles that are already - * counted in the corresponding main TLB event - */ -#define XPM_EVENT_DATA_uTLBSTALL 0x85 - -/* - * Counts the number of stall cycles because of the execution of a DMB memory - * barrier. This includes all DMB instructions being executed, even - * speculatively - */ -#define XPM_EVENT_DMB_STALL 0x86 - -/* - * Counts the number of cycles during which the integer core clock is enabled - */ -#define XPM_EVENT_INT_CLKEN 0x8A - -/* - * Counts the number of cycles during which the Data Engine clock is enabled - */ -#define XPM_EVENT_DE_CLKEN 0x8B - -/* - * Counts the number of ISB instructions architecturally executed - */ -#define XPM_EVENT_INSTRISB 0x90 - -/* - * Counts the number of DSB instructions architecturally executed - */ -#define XPM_EVENT_INSTRDSB 0x91 - -/* - * Counts the number of DMB instructions speculatively executed - */ -#define XPM_EVENT_INSTRDMB 0x92 - -/* - * Counts the number of external interrupts executed by the processor - */ -#define XPM_EVENT_EXTINT 0x93 - -/* - * PLE cache line request completed - */ -#define XPM_EVENT_PLE_LRC 0xA0 - -/* - * PLE cache line request skipped - */ -#define XPM_EVENT_PLE_LRS 0xA1 - -/* - * PLE FIFO flush - */ -#define XPM_EVENT_PLE_FLUSH 0xA2 - -/* - * PLE request complete - */ -#define XPM_EVENT_PLE_CMPL 0xA3 - -/* - * PLE FIFO overflow - */ -#define XPM_EVENT_PLE_OVFL 0xA4 - -/* - * PLE request programmed - */ -#define XPM_EVENT_PLE_PROG 0xA5 - -/* - * The following constants define the configurations for Cortex-A9 Performance - * Monitor Events. Each configuration configures the event counters for a set - * of events. - * ----------------------------------------------- - * Config PmCtr0... PmCtr5 - * ----------------------------------------------- - * XPM_CNTRCFG1 { XPM_EVENT_SOFTINCR, - * XPM_EVENT_INSRFETCH_CACHEREFILL, - * XPM_EVENT_INSTRFECT_TLBREFILL, - * XPM_EVENT_DATA_CACHEREFILL, - * XPM_EVENT_DATA_CACHEACCESS, - * XPM_EVENT_DATA_TLBREFILL } - * - * XPM_CNTRCFG2 { XPM_EVENT_DATA_READS, - * XPM_EVENT_DATA_WRITE, - * XPM_EVENT_EXCEPTION, - * XPM_EVENT_EXCEPRETURN, - * XPM_EVENT_CHANGECONTEXT, - * XPM_EVENT_SW_CHANGEPC } - * - * XPM_CNTRCFG3 { XPM_EVENT_IMMEDBRANCH, - * XPM_EVENT_UNALIGNEDACCESS, - * XPM_EVENT_BRANCHMISS, - * XPM_EVENT_CLOCKCYCLES, - * XPM_EVENT_BRANCHPREDICT, - * XPM_EVENT_JAVABYTECODE } - * - * XPM_CNTRCFG4 { XPM_EVENT_SWJAVABYTECODE, - * XPM_EVENT_JAVABACKBRANCH, - * XPM_EVENT_COHERLINEMISS, - * XPM_EVENT_COHERLINEHIT, - * XPM_EVENT_INSTRSTALL, - * XPM_EVENT_DATASTALL } - * - * XPM_CNTRCFG5 { XPM_EVENT_MAINTLBSTALL, - * XPM_EVENT_STREXPASS, - * XPM_EVENT_STREXFAIL, - * XPM_EVENT_DATAEVICT, - * XPM_EVENT_NODISPATCH, - * XPM_EVENT_ISSUEEMPTY } - * - * XPM_CNTRCFG6 { XPM_EVENT_INSTRRENAME, - * XPM_EVENT_PREDICTFUNCRET, - * XPM_EVENT_MAINEXEC, - * XPM_EVENT_SECEXEC, - * XPM_EVENT_LDRSTR, - * XPM_EVENT_FLOATRENAME } - * - * XPM_CNTRCFG7 { XPM_EVENT_NEONRENAME, - * XPM_EVENT_PLDSTALL, - * XPM_EVENT_WRITESTALL, - * XPM_EVENT_INSTRTLBSTALL, - * XPM_EVENT_DATATLBSTALL, - * XPM_EVENT_INSTR_uTLBSTALL } - * - * XPM_CNTRCFG8 { XPM_EVENT_DATA_uTLBSTALL, - * XPM_EVENT_DMB_STALL, - * XPM_EVENT_INT_CLKEN, - * XPM_EVENT_DE_CLKEN, - * XPM_EVENT_INSTRISB, - * XPM_EVENT_INSTRDSB } - * - * XPM_CNTRCFG9 { XPM_EVENT_INSTRDMB, - * XPM_EVENT_EXTINT, - * XPM_EVENT_PLE_LRC, - * XPM_EVENT_PLE_LRS, - * XPM_EVENT_PLE_FLUSH, - * XPM_EVENT_PLE_CMPL } - * - * XPM_CNTRCFG10 { XPM_EVENT_PLE_OVFL, - * XPM_EVENT_PLE_PROG, - * XPM_EVENT_PLE_LRC, - * XPM_EVENT_PLE_LRS, - * XPM_EVENT_PLE_FLUSH, - * XPM_EVENT_PLE_CMPL } - * - * XPM_CNTRCFG11 { XPM_EVENT_DATASTALL, - * XPM_EVENT_INSRFETCH_CACHEREFILL, - * XPM_EVENT_INSTRFECT_TLBREFILL, - * XPM_EVENT_DATA_CACHEREFILL, - * XPM_EVENT_DATA_CACHEACCESS, - * XPM_EVENT_DATA_TLBREFILL } - */ -#define XPM_CNTRCFG1 0 -#define XPM_CNTRCFG2 1 -#define XPM_CNTRCFG3 2 -#define XPM_CNTRCFG4 3 -#define XPM_CNTRCFG5 4 -#define XPM_CNTRCFG6 5 -#define XPM_CNTRCFG7 6 -#define XPM_CNTRCFG8 7 -#define XPM_CNTRCFG9 8 -#define XPM_CNTRCFG10 9 -#define XPM_CNTRCFG11 10 - -/**************************** Type Definitions ******************************/ - -/***************** Macros (Inline Functions) Definitions ********************/ - -/************************** Variable Definitions ****************************/ - -/************************** Function Prototypes *****************************/ - -/* Interface fuctions to access perfromance counters from abstraction layer */ -void Xpm_SetEvents(int PmcrCfg); -void Xpm_GetEventCounters(u32 *PmCtrValue); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xpm_counter.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xpm_counter.o deleted file mode 100644 index f4f09091d08bd31f5dc303f62f0d2948b1697a44..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xpm_counter.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xpseudo_asm.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xpseudo_asm.h deleted file mode 100644 index e44a79954063122c428275d4cc0d0e8ed1bd3252..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xpseudo_asm.h +++ /dev/null @@ -1,64 +0,0 @@ -/******************************************************************************* -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -*******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xpseudo_asm.h -* -* This header file contains macros for using inline assembler code. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a ecm 10/18/09 First release -* 3.04a sdm 01/02/12 Remove redundant dsb in mcr instruction. -* </pre> -* -******************************************************************************/ -#include "xreg_cortexa9.h" -#ifdef __GNUC__ - #include "xpseudo_asm_gcc.h" -#elif defined (__ICCARM__) - #include "xpseudo_asm_iccarm.h" -#else - #include "xpseudo_asm_rvct.h" -#endif diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xpseudo_asm_gcc.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xpseudo_asm_gcc.h deleted file mode 100644 index 52fac3b3481d0c6ce0f410384089549cedfcf2b2..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xpseudo_asm_gcc.h +++ /dev/null @@ -1,183 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xpseudo_asm_gcc.h -* -* This header file contains macros for using inline assembler code. It is -* written specifically for the GNU compiler. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- -------- -------- ----------------------------------------------- -* 1.00a ecm/sdm 10/28/09 First release -* </pre> -* -******************************************************************************/ - -#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */ -#define XPSEUDO_ASM_GCC_H /* by using protection macros */ - -/***************************** Include Files ********************************/ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/************************** Constant Definitions ****************************/ - -/**************************** Type Definitions ******************************/ - -/***************** Macros (Inline Functions) Definitions ********************/ - -/* necessary for pre-processor */ -#define stringify(s) tostring(s) -#define tostring(s) #s - -/* pseudo assembler instructions */ -#define mfcpsr() ({unsigned int rval; \ - __asm__ __volatile__(\ - "mrs %0, cpsr\n"\ - : "=r" (rval)\ - );\ - rval;\ - }) - -#define mtcpsr(v) __asm__ __volatile__(\ - "msr cpsr,%0\n"\ - : : "r" (v)\ - ) - -#define cpsiei() __asm__ __volatile__("cpsie i\n") -#define cpsidi() __asm__ __volatile__("cpsid i\n") - -#define cpsief() __asm__ __volatile__("cpsie f\n") -#define cpsidf() __asm__ __volatile__("cpsid f\n") - - - -#define mtgpr(rn, v) __asm__ __volatile__(\ - "mov r" stringify(rn) ", %0 \n"\ - : : "r" (v)\ - ) - -#define mfgpr(rn) ({unsigned int rval; \ - __asm__ __volatile__(\ - "mov %0,r" stringify(rn) "\n"\ - : "=r" (rval)\ - );\ - rval;\ - }) - -/* memory synchronization operations */ - -/* Instruction Synchronization Barrier */ -#define isb() __asm__ __volatile__ ("isb" : : : "memory") - -/* Data Synchronization Barrier */ -#define dsb() __asm__ __volatile__ ("dsb" : : : "memory") - -/* Data Memory Barrier */ -#define dmb() __asm__ __volatile__ ("dmb" : : : "memory") - - -/* Memory Operations */ -#define ldr(adr) ({unsigned long rval; \ - __asm__ __volatile__(\ - "ldr %0,[%1]"\ - : "=r" (rval) : "r" (adr)\ - );\ - rval;\ - }) - -#define ldrb(adr) ({unsigned char rval; \ - __asm__ __volatile__(\ - "ldrb %0,[%1]"\ - : "=r" (rval) : "r" (adr)\ - );\ - rval;\ - }) - -#define str(adr, val) __asm__ __volatile__(\ - "str %0,[%1]\n"\ - : : "r" (val), "r" (adr)\ - ) - -#define strb(adr, val) __asm__ __volatile__(\ - "strb %0,[%1]\n"\ - : : "r" (val), "r" (adr)\ - ) - -/* Count leading zeroes (clz) */ -#define clz(arg) ({unsigned char rval; \ - __asm__ __volatile__(\ - "clz %0,%1"\ - : "=r" (rval) : "r" (arg)\ - );\ - rval;\ - }) - -/* CP15 operations */ -#define mtcp(rn, v) __asm__ __volatile__(\ - "mcr " rn "\n"\ - : : "r" (v)\ - ); - -#define mfcp(rn) ({unsigned int rval; \ - __asm__ __volatile__(\ - "mrc " rn "\n"\ - : "=r" (rval)\ - );\ - rval;\ - }) - -/************************** Variable Definitions ****************************/ - -/************************** Function Prototypes *****************************/ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* XPSEUDO_ASM_GCC_H */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xreg_cortexa9.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xreg_cortexa9.h deleted file mode 100644 index 65e648f5476b77ff3b7e81ed87665072d91e5849..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xreg_cortexa9.h +++ /dev/null @@ -1,599 +0,0 @@ -/******************************************************************************* -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -*******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xreg_cortexa9.h -* -* This header file contains definitions for using inline assembler code. It is -* written specifically for the GNU, IAR, ARMCC compiler. -* -* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along -* with the positions of the bits within the registers. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- -------- -------- ----------------------------------------------- -* 1.00a ecm/sdm 10/20/09 First release -* </pre> -* -******************************************************************************/ -#ifndef XREG_CORTEXA9_H -#define XREG_CORTEXA9_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* GPRs */ -#define XREG_GPR0 r0 -#define XREG_GPR1 r1 -#define XREG_GPR2 r2 -#define XREG_GPR3 r3 -#define XREG_GPR4 r4 -#define XREG_GPR5 r5 -#define XREG_GPR6 r6 -#define XREG_GPR7 r7 -#define XREG_GPR8 r8 -#define XREG_GPR9 r9 -#define XREG_GPR10 r10 -#define XREG_GPR11 r11 -#define XREG_GPR12 r12 -#define XREG_GPR13 r13 -#define XREG_GPR14 r14 -#define XREG_GPR15 r15 -#define XREG_CPSR cpsr - -/* Coprocessor number defines */ -#define XREG_CP0 0 -#define XREG_CP1 1 -#define XREG_CP2 2 -#define XREG_CP3 3 -#define XREG_CP4 4 -#define XREG_CP5 5 -#define XREG_CP6 6 -#define XREG_CP7 7 -#define XREG_CP8 8 -#define XREG_CP9 9 -#define XREG_CP10 10 -#define XREG_CP11 11 -#define XREG_CP12 12 -#define XREG_CP13 13 -#define XREG_CP14 14 -#define XREG_CP15 15 - -/* Coprocessor control register defines */ -#define XREG_CR0 cr0 -#define XREG_CR1 cr1 -#define XREG_CR2 cr2 -#define XREG_CR3 cr3 -#define XREG_CR4 cr4 -#define XREG_CR5 cr5 -#define XREG_CR6 cr6 -#define XREG_CR7 cr7 -#define XREG_CR8 cr8 -#define XREG_CR9 cr9 -#define XREG_CR10 cr10 -#define XREG_CR11 cr11 -#define XREG_CR12 cr12 -#define XREG_CR13 cr13 -#define XREG_CR14 cr14 -#define XREG_CR15 cr15 - -/* Current Processor Status Register (CPSR) Bits */ -#define XREG_CPSR_THUMB_MODE 0x20 -#define XREG_CPSR_MODE_BITS 0x1F -#define XREG_CPSR_SYSTEM_MODE 0x1F -#define XREG_CPSR_UNDEFINED_MODE 0x1B -#define XREG_CPSR_DATA_ABORT_MODE 0x17 -#define XREG_CPSR_SVC_MODE 0x13 -#define XREG_CPSR_IRQ_MODE 0x12 -#define XREG_CPSR_FIQ_MODE 0x11 -#define XREG_CPSR_USER_MODE 0x10 - -#define XREG_CPSR_IRQ_ENABLE 0x80 -#define XREG_CPSR_FIQ_ENABLE 0x40 - -#define XREG_CPSR_N_BIT 0x80000000 -#define XREG_CPSR_Z_BIT 0x40000000 -#define XREG_CPSR_C_BIT 0x20000000 -#define XREG_CPSR_V_BIT 0x10000000 - - -/* CP15 defines */ -#if defined (__GNUC__) || defined (__ICCARM__) -/* C0 Register defines */ -#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0" -#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1" -#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2" -#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3" -#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5" - -#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0" -#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1" -#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2" -#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4" -#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5" -#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6" -#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7" - -#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0" -#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1" -#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2" -#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3" -#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4" - -#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0" -#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1" -#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7" - -#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0" - -/* C1 Register Defines */ -#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0" -#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1" -#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2" - -#define XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0" -#define XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1" -#define XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2" -#define XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3" - -#else /* RVCT */ -/* C0 Register defines */ -#define XREG_CP15_MAIN_ID "cp15:0:c0:c0:0" -#define XREG_CP15_CACHE_TYPE "cp15:0:c0:c0:1" -#define XREG_CP15_TCM_TYPE "cp15:0:c0:c0:2" -#define XREG_CP15_TLB_TYPE "cp15:0:c0:c0:3" -#define XREG_CP15_MULTI_PROC_AFFINITY "cp15:0:c0:c0:5" - -#define XREG_CP15_PROC_FEATURE_0 "cp15:0:c0:c1:0" -#define XREG_CP15_PROC_FEATURE_1 "cp15:0:c0:c1:1" -#define XREG_CP15_DEBUG_FEATURE_0 "cp15:0:c0:c1:2" -#define XREG_CP15_MEMORY_FEATURE_0 "cp15:0:c0:c1:4" -#define XREG_CP15_MEMORY_FEATURE_1 "cp15:0:c0:c1:5" -#define XREG_CP15_MEMORY_FEATURE_2 "cp15:0:c0:c1:6" -#define XREG_CP15_MEMORY_FEATURE_3 "cp15:0:c0:c1:7" - -#define XREG_CP15_INST_FEATURE_0 "cp15:0:c0:c2:0" -#define XREG_CP15_INST_FEATURE_1 "cp15:0:c0:c2:1" -#define XREG_CP15_INST_FEATURE_2 "cp15:0:c0:c2:2" -#define XREG_CP15_INST_FEATURE_3 "cp15:0:c0:c2:3" -#define XREG_CP15_INST_FEATURE_4 "cp15:0:c0:c2:4" - -#define XREG_CP15_CACHE_SIZE_ID "cp15:1:c0:c0:0" -#define XREG_CP15_CACHE_LEVEL_ID "cp15:1:c0:c0:1" -#define XREG_CP15_AUXILARY_ID "cp15:1:c0:c0:7" - -#define XREG_CP15_CACHE_SIZE_SEL "cp15:2:c0:c0:0" - -/* C1 Register Defines */ -#define XREG_CP15_SYS_CONTROL "cp15:0:c1:c0:0" -#define XREG_CP15_AUX_CONTROL "cp15:0:c1:c0:1" -#define XREG_CP15_CP_ACCESS_CONTROL "cp15:0:c1:c0:2" - -#define XREG_CP15_SECURE_CONFIG "cp15:0:c1:c1:0" -#define XREG_CP15_SECURE_DEBUG_ENABLE "cp15:0:c1:c1:1" -#define XREG_CP15_NS_ACCESS_CONTROL "cp15:0:c1:c1:2" -#define XREG_CP15_VIRTUAL_CONTROL "cp15:0:c1:c1:3" -#endif - -/* XREG_CP15_CONTROL bit defines */ -#define XREG_CP15_CONTROL_TE_BIT 0x40000000 -#define XREG_CP15_CONTROL_AFE_BIT 0x20000000 -#define XREG_CP15_CONTROL_TRE_BIT 0x10000000 -#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000 -#define XREG_CP15_CONTROL_EE_BIT 0x02000000 -#define XREG_CP15_CONTROL_HA_BIT 0x00020000 -#define XREG_CP15_CONTROL_RR_BIT 0x00004000 -#define XREG_CP15_CONTROL_V_BIT 0x00002000 -#define XREG_CP15_CONTROL_I_BIT 0x00001000 -#define XREG_CP15_CONTROL_Z_BIT 0x00000800 -#define XREG_CP15_CONTROL_SW_BIT 0x00000400 -#define XREG_CP15_CONTROL_B_BIT 0x00000080 -#define XREG_CP15_CONTROL_C_BIT 0x00000004 -#define XREG_CP15_CONTROL_A_BIT 0x00000002 -#define XREG_CP15_CONTROL_M_BIT 0x00000001 - -#if defined (__GNUC__) || defined (__ICCARM__) -/* C2 Register Defines */ -#define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0" -#define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1" -#define XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2" - -/* C3 Register Defines */ -#define XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0" - -/* C4 Register Defines */ -/* Not Used */ - -/* C5 Register Defines */ -#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0" -#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1" - -#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0" -#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1" - -/* C6 Register Defines */ -#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0" -#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2" - -/* C7 Register Defines */ -#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4" - -#define XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0" -#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6" - -#define XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0" - -#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0" -#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1" - -/* The CP15 register access below has been deprecated in favor of the new - * isb instruction in Cortex A9. - */ -#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4" -#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6" - -#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1" -#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2" - -#define XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0" -#define XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1" -#define XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2" -#define XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3" - -#define XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4" -#define XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5" -#define XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6" -#define XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7" - -#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1" -#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2" - -/* The next two CP15 register accesses below have been deprecated in favor - * of the new dsb and dmb instructions in Cortex A9. - */ -#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4" -#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5" - -#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1" - -#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1" - -#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1" -#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2" - -/* C8 Register Defines */ -#define XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0" -#define XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1" -#define XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2" -#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3" - -#define XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0" -#define XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1" -#define XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2" - -#define XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0" -#define XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1" -#define XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2" - -#define XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0" -#define XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1" -#define XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2" -#define XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3" - -/* C9 Register Defines */ -#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0" -#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1" -#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2" -#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3" -#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4" -#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5" - -#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0" -#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1" -#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2" - -#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0" -#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1" -#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2" - -/* C10 Register Defines */ -#define XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0" - -#define XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0" -#define XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1" - -/* C11 Register Defines */ -/* Not used */ - -/* C12 Register Defines */ -#define XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0" -#define XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1" - -#define XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0" -#define XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1" - -/* C13 Register Defines */ -#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1" -#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2" -#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3" -#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4" - -/* C14 Register Defines */ -/* not used */ - -/* C15 Register Defines */ -#define XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0" -#define XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0" - -#define XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2" -#define XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4" - -#define XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2" - -#define XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2" - -#define XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2" - -#else -/* C2 Register Defines */ -#define XREG_CP15_TTBR0 "cp15:0:c2:c0:0" -#define XREG_CP15_TTBR1 "cp15:0:c2:c0:1" -#define XREG_CP15_TTB_CONTROL "cp15:0:c2:c0:2" - -/* C3 Register Defines */ -#define XREG_CP15_DOMAIN_ACCESS_CTRL "cp15:0:c3:c0:0" - -/* C4 Register Defines */ -/* Not Used */ - -/* C5 Register Defines */ -#define XREG_CP15_DATA_FAULT_STATUS "cp15:0:c5:c0:0" -#define XREG_CP15_INST_FAULT_STATUS "cp15:0:c5:c0:1" - -#define XREG_CP15_AUX_DATA_FAULT_STATUS "cp15:0:c5:c1:0" -#define XREG_CP15_AUX_INST_FAULT_STATUS "cp15:0:c5:c1:1" - -/* C6 Register Defines */ -#define XREG_CP15_DATA_FAULT_ADDRESS "cp15:0:c6:c0:0" -#define XREG_CP15_INST_FAULT_ADDRESS "cp15:0:c6:c0:2" - -/* C7 Register Defines */ -#define XREG_CP15_NOP "cp15:0:c7:c0:4" - -#define XREG_CP15_INVAL_IC_POU_IS "cp15:0:c7:c1:0" -#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "cp15:0:c7:c1:6" - -#define XREG_CP15_PHYS_ADDR "cp15:0:c7:c4:0" - -#define XREG_CP15_INVAL_IC_POU "cp15:0:c7:c5:0" -#define XREG_CP15_INVAL_IC_LINE_MVA_POU "cp15:0:c7:c5:1" - -/* The CP15 register access below has been deprecated in favor of the new - * isb instruction in Cortex A9. - */ -#define XREG_CP15_INST_SYNC_BARRIER "cp15:0:c7:c5:4" -#define XREG_CP15_INVAL_BRANCH_ARRAY "cp15:0:c7:c5:6" - -#define XREG_CP15_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c6:1" -#define XREG_CP15_INVAL_DC_LINE_SW "cp15:0:c7:c6:2" - -#define XREG_CP15_VA_TO_PA_CURRENT_0 "cp15:0:c7:c8:0" -#define XREG_CP15_VA_TO_PA_CURRENT_1 "cp15:0:c7:c8:1" -#define XREG_CP15_VA_TO_PA_CURRENT_2 "cp15:0:c7:c8:2" -#define XREG_CP15_VA_TO_PA_CURRENT_3 "cp15:0:c7:c8:3" - -#define XREG_CP15_VA_TO_PA_OTHER_0 "cp15:0:c7:c8:4" -#define XREG_CP15_VA_TO_PA_OTHER_1 "cp15:0:c7:c8:5" -#define XREG_CP15_VA_TO_PA_OTHER_2 "cp15:0:c7:c8:6" -#define XREG_CP15_VA_TO_PA_OTHER_3 "cp15:0:c7:c8:7" - -#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "cp15:0:c7:c10:1" -#define XREG_CP15_CLEAN_DC_LINE_SW "cp15:0:c7:c10:2" - -/* The next two CP15 register accesses below have been deprecated in favor - * of the new dsb and dmb instructions in Cortex A9. - */ -#define XREG_CP15_DATA_SYNC_BARRIER "cp15:0:c7:c10:4" -#define XREG_CP15_DATA_MEMORY_BARRIER "cp15:0:c7:c10:5" - -#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "cp15:0:c7:c11:1" - -#define XREG_CP15_NOP2 "cp15:0:c7:c13:1" - -#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c14:1" -#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "cp15:0:c7:c14:2" - -/* C8 Register Defines */ -#define XREG_CP15_INVAL_TLB_IS "cp15:0:c8:c3:0" -#define XREG_CP15_INVAL_TLB_MVA_IS "cp15:0:c8:c3:1" -#define XREG_CP15_INVAL_TLB_ASID_IS "cp15:0:c8:c3:2" -#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "cp15:0:c8:c3:3" - -#define XREG_CP15_INVAL_ITLB_UNLOCKED "cp15:0:c8:c5:0" -#define XREG_CP15_INVAL_ITLB_MVA "cp15:0:c8:c5:1" -#define XREG_CP15_INVAL_ITLB_ASID "cp15:0:c8:c5:2" - -#define XREG_CP15_INVAL_DTLB_UNLOCKED "cp15:0:c8:c6:0" -#define XREG_CP15_INVAL_DTLB_MVA "cp15:0:c8:c6:1" -#define XREG_CP15_INVAL_DTLB_ASID "cp15:0:c8:c6:2" - -#define XREG_CP15_INVAL_UTLB_UNLOCKED "cp15:0:c8:c7:0" -#define XREG_CP15_INVAL_UTLB_MVA "cp15:0:c8:c7:1" -#define XREG_CP15_INVAL_UTLB_ASID "cp15:0:c8:c7:2" -#define XREG_CP15_INVAL_UTLB_MVA_ASID "cp15:0:c8:c7:3" - -/* C9 Register Defines */ -#define XREG_CP15_PERF_MONITOR_CTRL "cp15:0:c9:c12:0" -#define XREG_CP15_COUNT_ENABLE_SET "cp15:0:c9:c12:1" -#define XREG_CP15_COUNT_ENABLE_CLR "cp15:0:c9:c12:2" -#define XREG_CP15_V_FLAG_STATUS "cp15:0:c9:c12:3" -#define XREG_CP15_SW_INC "cp15:0:c9:c12:4" -#define XREG_CP15_EVENT_CNTR_SEL "cp15:0:c9:c12:5" - -#define XREG_CP15_PERF_CYCLE_COUNTER "cp15:0:c9:c13:0" -#define XREG_CP15_EVENT_TYPE_SEL "cp15:0:c9:c13:1" -#define XREG_CP15_PERF_MONITOR_COUNT "cp15:0:c9:c13:2" - -#define XREG_CP15_USER_ENABLE "cp15:0:c9:c14:0" -#define XREG_CP15_INTR_ENABLE_SET "cp15:0:c9:c14:1" -#define XREG_CP15_INTR_ENABLE_CLR "cp15:0:c9:c14:2" - -/* C10 Register Defines */ -#define XREG_CP15_TLB_LOCKDWN "cp15:0:c10:c0:0" - -#define XREG_CP15_PRI_MEM_REMAP "cp15:0:c10:c2:0" -#define XREG_CP15_NORM_MEM_REMAP "cp15:0:c10:c2:1" - -/* C11 Register Defines */ -/* Not used */ - -/* C12 Register Defines */ -#define XREG_CP15_VEC_BASE_ADDR "cp15:0:c12:c0:0" -#define XREG_CP15_MONITOR_VEC_BASE_ADDR "cp15:0:c12:c0:1" - -#define XREG_CP15_INTERRUPT_STATUS "cp15:0:c12:c1:0" -#define XREG_CP15_VIRTUALIZATION_INTR "cp15:0:c12:c1:1" - -/* C13 Register Defines */ -#define XREG_CP15_CONTEXT_ID "cp15:0:c13:c0:1" -#define USER_RW_THREAD_PID "cp15:0:c13:c0:2" -#define USER_RO_THREAD_PID "cp15:0:c13:c0:3" -#define USER_PRIV_THREAD_PID "cp15:0:c13:c0:4" - -/* C14 Register Defines */ -/* not used */ - -/* C15 Register Defines */ -#define XREG_CP15_POWER_CTRL "cp15:0:c15:c0:0" -#define XREG_CP15_CONFIG_BASE_ADDR "cp15:4:c15:c0:0" - -#define XREG_CP15_READ_TLB_ENTRY "cp15:5:c15:c4:2" -#define XREG_CP15_WRITE_TLB_ENTRY "cp15:5:c15:c4:4" - -#define XREG_CP15_MAIN_TLB_VA "cp15:5:c15:c5:2" - -#define XREG_CP15_MAIN_TLB_PA "cp15:5:c15:c6:2" - -#define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2" -#endif - - -/* MPE register definitions */ -#define XREG_FPSID c0 -#define XREG_FPSCR c1 -#define XREG_MVFR1 c6 -#define XREG_MVFR0 c7 -#define XREG_FPEXC c8 -#define XREG_FPINST c9 -#define XREG_FPINST2 c10 - -/* FPSID bits */ -#define XREG_FPSID_IMPLEMENTER_BIT (24) -#define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT) -#define XREG_FPSID_SOFTWARE (1<<23) -#define XREG_FPSID_ARCH_BIT (16) -#define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT) -#define XREG_FPSID_PART_BIT (8) -#define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT) -#define XREG_FPSID_VARIANT_BIT (4) -#define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT) -#define XREG_FPSID_REV_BIT (0) -#define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT) - -/* FPSCR bits */ -#define XREG_FPSCR_N_BIT (1 << 31) -#define XREG_FPSCR_Z_BIT (1 << 30) -#define XREG_FPSCR_C_BIT (1 << 29) -#define XREG_FPSCR_V_BIT (1 << 28) -#define XREG_FPSCR_QC (1 << 27) -#define XREG_FPSCR_AHP (1 << 26) -#define XREG_FPSCR_DEFAULT_NAN (1 << 25) -#define XREG_FPSCR_FLUSHTOZERO (1 << 24) -#define XREG_FPSCR_ROUND_NEAREST (0 << 22) -#define XREG_FPSCR_ROUND_PLUSINF (1 << 22) -#define XREG_FPSCR_ROUND_MINUSINF (2 << 22) -#define XREG_FPSCR_ROUND_TOZERO (3 << 22) -#define XREG_FPSCR_RMODE_BIT (22) -#define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT) -#define XREG_FPSCR_STRIDE_BIT (20) -#define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT) -#define XREG_FPSCR_LENGTH_BIT (16) -#define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT) -#define XREG_FPSCR_IDC (1 << 7) -#define XREG_FPSCR_IXC (1 << 4) -#define XREG_FPSCR_UFC (1 << 3) -#define XREG_FPSCR_OFC (1 << 2) -#define XREG_FPSCR_DZC (1 << 1) -#define XREG_FPSCR_IOC (1 << 0) - -/* MVFR0 bits */ -#define XREG_MVFR0_RMODE_BIT (28) -#define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT) -#define XREG_MVFR0_SHORT_VEC_BIT (24) -#define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT) -#define XREG_MVFR0_SQRT_BIT (20) -#define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT) -#define XREG_MVFR0_DIVIDE_BIT (16) -#define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT) -#define XREG_MVFR0_EXEC_TRAP_BIT (12) -#define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT) -#define XREG_MVFR0_DP_BIT (8) -#define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT) -#define XREG_MVFR0_SP_BIT (4) -#define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT) -#define XREG_MVFR0_A_SIMD_BIT (0) -#define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT) - -/* FPEXC bits */ -#define XREG_FPEXC_EX (1 << 31) -#define XREG_FPEXC_EN (1 << 30) -#define XREG_FPEXC_DEX (1 << 29) - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* XREG_CORTEXA9_H */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xstatus.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xstatus.h deleted file mode 100644 index 76d2a94c73eb4640b66c7b09096b5e2f718fb22f..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xstatus.h +++ /dev/null @@ -1,439 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2002-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xstatus.h -* -* This file contains Xilinx software status codes. Status codes have their -* own data type called int. These codes are used throughout the Xilinx -* device drivers. -* -******************************************************************************/ - -#ifndef XSTATUS_H /* prevent circular inclusions */ -#define XSTATUS_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" - -/************************** Constant Definitions *****************************/ - -/*********************** Common statuses 0 - 500 *****************************/ - -#define XST_SUCCESS 0L -#define XST_FAILURE 1L -#define XST_DEVICE_NOT_FOUND 2L -#define XST_DEVICE_BLOCK_NOT_FOUND 3L -#define XST_INVALID_VERSION 4L -#define XST_DEVICE_IS_STARTED 5L -#define XST_DEVICE_IS_STOPPED 6L -#define XST_FIFO_ERROR 7L /* an error occurred during an - operation with a FIFO such as - an underrun or overrun, this - error requires the device to - be reset */ -#define XST_RESET_ERROR 8L /* an error occurred which requires - the device to be reset */ -#define XST_DMA_ERROR 9L /* a DMA error occurred, this error - typically requires the device - using the DMA to be reset */ -#define XST_NOT_POLLED 10L /* the device is not configured for - polled mode operation */ -#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put - the specified data into */ -#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough - to hold the expected data */ -#define XST_NO_DATA 13L /* there was no data available */ -#define XST_REGISTER_ERROR 14L /* a register did not contain the - expected value */ -#define XST_INVALID_PARAM 15L /* an invalid parameter was passed - into the function */ -#define XST_NOT_SGDMA 16L /* the device is not configured for - scatter-gather DMA operation */ -#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */ -#define XST_NO_CALLBACK 18L /* a callback has not yet been - registered */ -#define XST_NO_FEATURE 19L /* device is not configured with - the requested feature */ -#define XST_NOT_INTERRUPT 20L /* device is not configured for - interrupt mode operation */ -#define XST_DEVICE_BUSY 21L /* device is busy */ -#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device - have maxed out */ -#define XST_IS_STARTED 23L /* used when part of device is - already started i.e. - sub channel */ -#define XST_IS_STOPPED 24L /* used when part of device is - already stopped i.e. - sub channel */ -#define XST_DATA_LOST 26L /* driver defined error */ -#define XST_RECV_ERROR 27L /* generic receive error */ -#define XST_SEND_ERROR 28L /* generic transmit error */ -#define XST_NOT_ENABLED 29L /* a requested service is not - available because it has not - been enabled */ - -/***************** Utility Component statuses 401 - 500 *********************/ - -#define XST_MEMTEST_FAILED 401L /* memory test failed */ - - -/***************** Common Components statuses 501 - 1000 *********************/ - -/********************* Packet Fifo statuses 501 - 510 ************************/ - -#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */ -#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */ -#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value - was invalid after reset */ -#define XST_PFIFO_ERROR 504L /* generic packet FIFO error */ -#define XST_PFIFO_DEADLOCK 505L /* packet FIFO is reporting - * empty and full simultaneously - */ - -/************************** DMA statuses 511 - 530 ***************************/ - -#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer - failed */ -#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value - was invalid after reset */ -#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains - no buffer descriptors ready - to be processed */ -#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */ -#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */ -#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of - the scatter gather list are - being used */ -#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer - descriptor which is to be - copied over in the scatter - list is locked */ -#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been - put into the scatter gather - list to be commited */ -#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold - specified was larger than the - total # of buffer descriptors - in the scatter gather list */ -#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has - already been created */ -#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has - been created */ -#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was - being started was not committed - to the list */ -#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start - has already been used by the - hardware so it can't be reused - */ -#define XST_DMA_SG_LIST_ERROR 526L /* general purpose list access - error */ -#define XST_DMA_BD_ERROR 527L /* general buffer descriptor - error */ - -/************************** IPIF statuses 531 - 550 ***************************/ - -#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width - was passed into the function */ -#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at - reset was not valid */ -#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt - status register did not read - back correctly */ -#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status - register did not reset when - acked */ -#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable - register was not updated when - other registers changed */ -#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt - status register did not read - back correctly */ -#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register - did not reset when acked */ -#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was - not updated correctly when other - registers changed */ -#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending - register did not indicate the - expected value */ -#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register - did not indicate the expected - value */ -#define XST_IPIF_ERROR 541L /* generic ipif error */ - -/****************** Device specific statuses 1001 - 4095 *********************/ - -/********************* Ethernet statuses 1001 - 1050 *************************/ - -#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough - * to hold the minimum number of - * buffers or descriptors */ -#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */ -#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */ -#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */ -#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Driver is out of buffers */ -#define XST_EMAC_PARSE_ERROR 1006L /* Invalid driver init string */ -#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late - * collision on polled send */ - -/*********************** UART statuses 1051 - 1075 ***************************/ -#define XST_UART - -#define XST_UART_INIT_ERROR 1051L -#define XST_UART_START_ERROR 1052L -#define XST_UART_CONFIG_ERROR 1053L -#define XST_UART_TEST_FAIL 1054L -#define XST_UART_BAUD_ERROR 1055L -#define XST_UART_BAUD_RANGE 1056L - - -/************************ IIC statuses 1076 - 1100 ***************************/ - -#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */ -#define XST_IIC_BUS_BUSY 1077 /* bus found busy */ -#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */ - /* general call address */ -#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */ - /* value after reset not valid */ -#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */ - /* value after reset not valid */ -#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */ - /* value after reset not valid */ -#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */ - /* value after reset not valid */ -#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */ - /* didn't return value written */ -#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */ - /* didn't return value written */ -#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */ - /* didn't return value written */ -#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */ - /* didn't return value written */ -#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */ - /* didn't return written value */ -#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */ - -/*********************** ATMC statuses 1101 - 1125 ***************************/ - -#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM - controller hit the max value - which requires the statistics - to be cleared */ - -/*********************** Flash statuses 1126 - 1150 **************************/ - -#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming - */ -#define XST_FLASH_READY 1127L /* Flash is ready for commands */ -#define XST_FLASH_ERROR 1128L /* Flash had detected an internal - error. Use XFlash_DeviceControl - to retrieve device specific codes - */ -#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state - */ -#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state - */ -#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by - driver */ -#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */ -#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */ -#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation - aborted due to a timeout */ -#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its - addressible range */ -#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */ -#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from - write/erase function with - XFL_NON_BLOCKING_WRITE/ERASE - option cleared */ -#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */ - -/*********************** SPI statuses 1151 - 1175 ****************************/ - -#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */ -#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */ -#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */ -#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */ -#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */ -#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being - * selected */ -#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */ -#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only - */ -#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */ -#define XST_SPI_SLAVE_MODE 1160 /* device has been addressed as slave */ -#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /* device received data in slave mode */ - -#define XST_SPI_COMMAND_ERROR 1162 /* unrecognised command - qspi only */ - -/********************** OPB Arbiter statuses 1176 - 1200 *********************/ - -#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either - * one master assigned to two or more - * priorities, or one master not - * assigned to any priority - */ -#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the - * priority levels without first - * suspending the use of priority - * levels - */ -#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but - * bus parking was not enabled - */ -#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed - * priority mode to allow the - * priorities to be changed - */ - -/************************ Intc statuses 1201 - 1225 **************************/ - -#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */ -#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */ - -/********************** TmrCtr statuses 1226 - 1250 **************************/ - -#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */ - -/********************** WdtTb statuses 1251 - 1275 ***************************/ - -#define XST_WDTTB_TIMER_FAILED 1251L - -/********************** PlbArb statuses 1276 - 1300 **************************/ - -#define XST_PLBARB_FAIL_SELFTEST 1276L - -/********************** Plb2Opb statuses 1301 - 1325 *************************/ - -#define XST_PLB2OPB_FAIL_SELFTEST 1301L - -/********************** Opb2Plb statuses 1326 - 1350 *************************/ - -#define XST_OPB2PLB_FAIL_SELFTEST 1326L - -/********************** SysAce statuses 1351 - 1360 **************************/ - -#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */ - -/********************** PCI Bridge statuses 1361 - 1375 **********************/ - -#define XST_PCI_INVALID_ADDRESS 1361L - -/********************** FlexRay constants 1400 - 1409 *************************/ - -#define XST_FR_TX_ERROR 1400 -#define XST_FR_TX_BUSY 1401 -#define XST_FR_BUF_LOCKED 1402 -#define XST_FR_NO_BUF 1403 - -/****************** USB constants 1410 - 1420 *******************************/ - -#define XST_USB_ALREADY_CONFIGURED 1410 -#define XST_USB_BUF_ALIGN_ERROR 1411 -#define XST_USB_NO_DESC_AVAILABLE 1412 -#define XST_USB_BUF_TOO_BIG 1413 -#define XST_USB_NO_BUF 1414 - -/****************** HWICAP constants 1421 - 1429 *****************************/ - -#define XST_HWICAP_WRITE_DONE 1421 - - -/****************** AXI VDMA constants 1430 - 1440 *****************************/ - -#define XST_VDMA_MISMATCH_ERROR 1430 - -/*********************** NAND Flash statuses 1441 - 1459 *********************/ - -#define XST_NAND_BUSY 1441L /* Flash is erasing or - * programming - */ -#define XST_NAND_READY 1442L /* Flash is ready for commands - */ -#define XST_NAND_ERROR 1443L /* Flash had detected an - * internal error. - */ -#define XST_NAND_PART_NOT_SUPPORTED 1444L /* Flash type not supported by - * driver - */ -#define XST_NAND_OPT_NOT_SUPPORTED 1445L /* Operation not supported - */ -#define XST_NAND_TIMEOUT_ERROR 1446L /* Programming or erase - * operation aborted due to a - * timeout - */ -#define XST_NAND_ADDRESS_ERROR 1447L /* Accessed flash outside its - * addressible range - */ -#define XST_NAND_ALIGNMENT_ERROR 1448L /* Write alignment error - */ -#define XST_NAND_PARAM_PAGE_ERROR 1449L /* Failed to read parameter - * page of the device - */ -#define XST_NAND_CACHE_ERROR 1450L /* Flash page buffer error - */ - -#define XST_NAND_WRITE_PROTECTED 1451L /* Flash is write protected - */ - -/**************************** Type Definitions *******************************/ - -typedef int XStatus; - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xtime_l.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xtime_l.c deleted file mode 100644 index 723d19acf550bcadecab243ed94ebb88e4157460..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xtime_l.c +++ /dev/null @@ -1,129 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* @file xtime_l.c -* -* This file contains low level functions to get/set time from the Global Timer -* register in the ARM Cortex A9 MP core. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------ -------- --------------------------------------------------- -* 1.00a rp/sdm 11/03/09 Initial release. -* 3.07a sgd 07/05/12 Upadted get/set time functions to make use Global Timer -* </pre> -* -* @note None. -* -******************************************************************************/ -/***************************** Include Files *********************************/ - -#include "xtime_l.h" -#include "xpseudo_asm.h" -#include "xil_types.h" -#include "xil_assert.h" -#include "xil_io.h" - -/***************** Macros (Inline Functions) Definitions *********************/ - -/**************************** Type Definitions *******************************/ - -/************************** Constant Definitions *****************************/ - -/************************** Variable Definitions *****************************/ - -/************************** Function Prototypes ******************************/ - -/**************************************************************************** -* -* Set the time in the Global Timer Counter Register. -* -* @param Value to be written to the Global Timer Counter Register. -* -* @return None. -* -* @note In multiprocessor environment reference time will reset/lost for -* all processors, when this function called by any one processor. -* -****************************************************************************/ -void XTime_SetTime(XTime Xtime) -{ - /* Disable Global Timer */ - Xil_Out32(GLOBAL_TMR_BASEADDR + GTIMER_CONTROL_OFFSET, 0x0); - - /* Updating Global Timer Counter Register */ - Xil_Out32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_LOWER_OFFSET, (u32)Xtime); - Xil_Out32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET, - (u32)(Xtime>>32)); - - /* Enable Global Timer */ - Xil_Out32(GLOBAL_TMR_BASEADDR + GTIMER_CONTROL_OFFSET, 0x1); -} - -/**************************************************************************** -* -* Get the time from the Global Timer Counter Register. -* -* @param Pointer to the location to be updated with the time. -* -* @return None. -* -* @note None. -* -****************************************************************************/ -void XTime_GetTime(XTime *Xtime) -{ - u32 low; - u32 high; - - /* Reading Global Timer Counter Register */ - do - { - high = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET); - low = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_LOWER_OFFSET); - } while(Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET) != high); - - *Xtime = (((XTime) high) << 32) | (XTime) low; -} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xtime_l.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xtime_l.h deleted file mode 100644 index e6550d3ce6a584cbaa3de8caa63715d8cadd7f31..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xtime_l.h +++ /dev/null @@ -1,96 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* @file xtime_l.h -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------ -------- --------------------------------------------------- -* 1.00a rp/sdm 11/03/09 Initial release. -* 3.06a sgd 05/15/12 Upadted get/set time functions to make use Global Timer -* 3.06a asa 06/17/12 Reverted back the changes to make use Global Timer. -* 3.07a sgd 07/05/12 Upadted get/set time functions to make use Global Timer -* </pre> -* -* @note None. -* -******************************************************************************/ - -#ifndef XTIME_H /* prevent circular inclusions */ -#define XTIME_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ -#include "xparameters.h" - -/***************** Macros (Inline Functions) Definitions *********************/ - -/**************************** Type Definitions *******************************/ - -typedef unsigned long long XTime; - -/************************** Constant Definitions *****************************/ -#define GLOBAL_TMR_BASEADDR XPAR_GLOBAL_TMR_BASEADDR -#define GTIMER_COUNTER_LOWER_OFFSET 0x00 -#define GTIMER_COUNTER_UPPER_OFFSET 0x04 -#define GTIMER_CONTROL_OFFSET 0x08 - - -/* Global Timer is always clocked at half of the CPU frequency */ -#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2) -/************************** Variable Definitions *****************************/ - -/************************** Function Prototypes ******************************/ - -void XTime_SetTime(XTime Xtime); -void XTime_GetTime(XTime *Xtime); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* XTIME_H */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xtime_l.o b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xtime_l.o deleted file mode 100644 index c14cbcb25d6a074e8557c7fbecbb343359a9aaa2..0000000000000000000000000000000000000000 Binary files a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/standalone_v3_11_a/src/xtime_l.o and /dev/null differ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/Makefile b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/Makefile deleted file mode 100644 index 20fb57c34fcffa1a80f21bb7356b8e30d60eb301..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -COMPILER= -ARCHIVER= -CP=cp -COMPILER_FLAGS= -EXTRA_COMPILER_FLAGS= -LIB=libxil.a - -RELEASEDIR=../../../lib -INCLUDEDIR=../../../include -INCLUDES=-I./. -I${INCLUDEDIR} - -OUTS = *.o - -LIBSOURCES=*.c -INCLUDEFILES=*.h - -libs: - echo "Compiling tmrctr" - $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) - $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} - make clean - -include: - ${CP} $(INCLUDEFILES) $(INCLUDEDIR) - -clean: - rm -rf ${OUTS} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr.c deleted file mode 100644 index 6ca63f6ec827ce9e0eb8d11f741ef56fb2a5d24a..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr.c +++ /dev/null @@ -1,531 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2002-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xtmrctr.c -* -* Contains required functions for the XTmrCtr driver. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a ecm 08/16/01 First release -* 1.00b jhl 02/21/02 Repartitioned the driver for smaller files -* 1.10b mta 03/21/07 Updated to new coding style -* 2.00a ktn 10/30/09 Updated to use HAL API's. _m is removed from all the macro -* definitions. -* 2.05a adk 15/05/13 Fixed the CR:693066 -* Added the IsStartedTmrCtr0/IsStartedTmrCtr1 members to the -* XTmrCtr instance structure. -* The IsStartedTmrCtrX will be assigned XIL_COMPONENT_IS_STARTED in -* the XTmrCtr_Start function. -* The IsStartedTmrCtrX will be cleared in the XTmrCtr_Stop function. -* There will be no Initialization done in the -* XTmrCtr_Initialize if both the timers have already started and -* the XST_DEVICE_IS_STARTED Status is returned. -* Removed the logic in the XTmrCtr_Initialize function -* which was checking the Register Value to know whether -* a timer has started or not. -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xstatus.h" -#include "xparameters.h" -#include "xtmrctr.h" -#include "xtmrctr_i.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - - -/************************** Variable Definitions *****************************/ - - -/*****************************************************************************/ -/** -* -* Initializes a specific timer/counter instance/driver. Initialize fields of -* the XTmrCtr structure, then reset the timer/counter.If a timer is already -* running then it is not initialized. -* -* -* @param InstancePtr is a pointer to the XTmrCtr instance. -* @param DeviceId is the unique id of the device controlled by this -* XTmrCtr component. Passing in a device id associates the -* generic XTmrCtr component to a specific device, as chosen by -* the caller or application developer. -* -* @return -* - XST_SUCCESS if initialization was successful -* - XST_DEVICE_IS_STARTED if the device has already been started -* - XST_DEVICE_NOT_FOUND if the device doesn't exist -* -* @note None. -* -******************************************************************************/ -int XTmrCtr_Initialize(XTmrCtr * InstancePtr, u16 DeviceId) -{ - XTmrCtr_Config *TmrCtrConfigPtr; - int TmrCtrNumber; - int TmrCtrLowIndex = 0; - int TmrCtrHighIndex = XTC_DEVICE_TIMER_COUNT; - - Xil_AssertNonvoid(InstancePtr != NULL); - - - /* - * If both the timers have already started, disallow the initialize and - * return a status indicating it is started. This allows the user to stop - * the device and reinitialize, but prevents a user from inadvertently - * initializing. - * In case one of the timers has not started then that particular timer - * will be initialized - */ - if ((InstancePtr->IsStartedTmrCtr0 == XIL_COMPONENT_IS_STARTED) && - (InstancePtr->IsStartedTmrCtr1 == XIL_COMPONENT_IS_STARTED)) { - return XST_DEVICE_IS_STARTED; - } - - - /* - * Ensure that only the timer which is NOT started can be initialized - */ - if ((InstancePtr->IsStartedTmrCtr0 == XIL_COMPONENT_IS_STARTED)) { - TmrCtrLowIndex = 1; - } else if ((InstancePtr->IsStartedTmrCtr1 == XIL_COMPONENT_IS_STARTED)) { - TmrCtrHighIndex = 1; - } else { - InstancePtr->IsStartedTmrCtr0 = 0; - InstancePtr->IsStartedTmrCtr1 = 0; - } - - - - /* - * Lookup the device configuration in the temporary CROM table. Use this - * configuration info down below when initializing this component. - */ - TmrCtrConfigPtr = XTmrCtr_LookupConfig(DeviceId); - - if (TmrCtrConfigPtr == (XTmrCtr_Config *) NULL) { - return XST_DEVICE_NOT_FOUND; - } - - /* - * Set some default values, including setting the callback - * handlers to stubs. - */ - InstancePtr->BaseAddress = TmrCtrConfigPtr->BaseAddress; - InstancePtr->Handler = NULL; - InstancePtr->CallBackRef = NULL; - - /* - * Clear the statistics for this driver - */ - InstancePtr->Stats.Interrupts = 0; - - /* Initialize the registers of each timer/counter in the device */ - - for (TmrCtrNumber = TmrCtrLowIndex; TmrCtrNumber < TmrCtrHighIndex; - TmrCtrNumber++) { - - /* - * Set the Compare register to 0 - */ - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TLR_OFFSET, 0); - /* - * Reset the timer and the interrupt, the reset bit will need to - * be cleared after this - */ - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TCSR_OFFSET, - XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK); - /* - * Set the control/status register to complete initialization by - * clearing the reset bit which was just set - */ - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TCSR_OFFSET, 0); - } - - /* - * Indicate the instance is ready to use, successfully initialized - */ - InstancePtr->IsReady = XIL_COMPONENT_IS_READY; - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* Starts the specified timer counter of the device such that it starts running. -* The timer counter is reset before it is started and the reset value is -* loaded into the timer counter. -* -* If interrupt mode is specified in the options, it is necessary for the caller -* to connect the interrupt handler of the timer/counter to the interrupt source, -* typically an interrupt controller, and enable the interrupt within the -* interrupt controller. -* -* @param InstancePtr is a pointer to the XTmrCtr instance. -* @param TmrCtrNumber is the timer counter of the device to operate on. -* Each device may contain multiple timer counters. The timer -* number is a zero based number with a range of -* 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XTmrCtr_Start(XTmrCtr * InstancePtr, u8 TmrCtrNumber) -{ - u32 ControlStatusReg; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the current register contents such that only the necessary bits - * of the register are modified in the following operations - */ - ControlStatusReg = XTmrCtr_ReadReg(InstancePtr->BaseAddress, - TmrCtrNumber, XTC_TCSR_OFFSET); - /* - * Reset the timer counter such that it reloads from the compare - * register and the interrupt is cleared simultaneously, the interrupt - * can only be cleared after reset such that the interrupt condition is - * cleared - */ - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TCSR_OFFSET, - XTC_CSR_LOAD_MASK); - - - - /* - * Indicate that the timer is started before enabling it - */ - if (TmrCtrNumber == 0) { - InstancePtr->IsStartedTmrCtr0 = XIL_COMPONENT_IS_STARTED; - } else { - InstancePtr->IsStartedTmrCtr1 = XIL_COMPONENT_IS_STARTED; - } - - - /* - * Remove the reset condition such that the timer counter starts running - * with the value loaded from the compare register - */ - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TCSR_OFFSET, - ControlStatusReg | XTC_CSR_ENABLE_TMR_MASK); -} - -/*****************************************************************************/ -/** -* -* Stops the timer counter by disabling it. -* -* It is the callers' responsibility to disconnect the interrupt handler of the -* timer_counter from the interrupt source, typically an interrupt controller, -* and disable the interrupt within the interrupt controller. -* -* @param InstancePtr is a pointer to the XTmrCtr instance. -* @param TmrCtrNumber is the timer counter of the device to operate on. -* Each device may contain multiple timer counters. The timer -* number is a zero based number with a range of -* 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XTmrCtr_Stop(XTmrCtr * InstancePtr, u8 TmrCtrNumber) -{ - u32 ControlStatusReg; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the current register contents - */ - ControlStatusReg = XTmrCtr_ReadReg(InstancePtr->BaseAddress, - TmrCtrNumber, XTC_TCSR_OFFSET); - /* - * Disable the timer counter such that it's not running - */ - ControlStatusReg &= ~(XTC_CSR_ENABLE_TMR_MASK); - - /* - * Write out the updated value to the actual register. - */ - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TCSR_OFFSET, ControlStatusReg); - - /* - * Indicate that the timer is stopped - */ - if (TmrCtrNumber == 0) { - InstancePtr->IsStartedTmrCtr0 = 0; - } else { - InstancePtr->IsStartedTmrCtr1 = 0; - } -} - -/*****************************************************************************/ -/** -* -* Get the current value of the specified timer counter. The timer counter -* may be either incrementing or decrementing based upon the current mode of -* operation. -* -* @param InstancePtr is a pointer to the XTmrCtr instance. -* @param TmrCtrNumber is the timer counter of the device to operate on. -* Each device may contain multiple timer counters. The timer -* number is a zero based number with a range of -* 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return The current value for the timer counter. -* -* @note None. -* -******************************************************************************/ -u32 XTmrCtr_GetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber) -{ - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - return XTmrCtr_ReadReg(InstancePtr->BaseAddress, - TmrCtrNumber, XTC_TCR_OFFSET); -} - -/*****************************************************************************/ -/** -* -* Set the reset value for the specified timer counter. This is the value -* that is loaded into the timer counter when it is reset. This value is also -* loaded when the timer counter is started. -* -* @param InstancePtr is a pointer to the XTmrCtr instance. -* @param TmrCtrNumber is the timer counter of the device to operate on. -* Each device may contain multiple timer counters. The timer -* number is a zero based number with a range of -* 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* @param ResetValue contains the value to be used to reset the timer -* counter. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XTmrCtr_SetResetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber, - u32 ResetValue) -{ - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TLR_OFFSET, ResetValue); -} - -/*****************************************************************************/ -/** -* -* Returns the timer counter value that was captured the last time the external -* capture input was asserted. -* -* @param InstancePtr is a pointer to the XTmrCtr instance. -* @param TmrCtrNumber is the timer counter of the device to operate on. -* Each device may contain multiple timer counters. The timer -* number is a zero based number with a range of -* 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return The current capture value for the indicated timer counter. -* -* @note None. -* -*******************************************************************************/ -u32 XTmrCtr_GetCaptureValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber) -{ - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - return XTmrCtr_ReadReg(InstancePtr->BaseAddress, - TmrCtrNumber, XTC_TLR_OFFSET); -} - -/*****************************************************************************/ -/** -* -* Resets the specified timer counter of the device. A reset causes the timer -* counter to set it's value to the reset value. -* -* @param InstancePtr is a pointer to the XTmrCtr instance. -* @param TmrCtrNumber is the timer counter of the device to operate on. -* Each device may contain multiple timer counters. The timer -* number is a zero based number with a range of -* 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XTmrCtr_Reset(XTmrCtr * InstancePtr, u8 TmrCtrNumber) -{ - u32 CounterControlReg; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read current contents of the register so it won't be destroyed - */ - CounterControlReg = XTmrCtr_ReadReg(InstancePtr->BaseAddress, - TmrCtrNumber, XTC_TCSR_OFFSET); - /* - * Reset the timer by toggling the reset bit in the register - */ - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TCSR_OFFSET, - CounterControlReg | XTC_CSR_LOAD_MASK); - - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TCSR_OFFSET, CounterControlReg); -} - -/*****************************************************************************/ -/** -* -* Checks if the specified timer counter of the device has expired. In capture -* mode, expired is defined as a capture occurred. In compare mode, expired is -* defined as the timer counter rolled over/under for up/down counting. -* -* When interrupts are enabled, the expiration causes an interrupt. This function -* is typically used to poll a timer counter to determine when it has expired. -* -* @param InstancePtr is a pointer to the XTmrCtr instance. -* @param TmrCtrNumber is the timer counter of the device to operate on. -* Each device may contain multiple timer counters. The timer -* number is a zero based number with a range of -* 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return TRUE if the timer has expired, and FALSE otherwise. -* -* @note None. -* -******************************************************************************/ -int XTmrCtr_IsExpired(XTmrCtr * InstancePtr, u8 TmrCtrNumber) -{ - u32 CounterControlReg; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Check if timer is expired - */ - CounterControlReg = XTmrCtr_ReadReg(InstancePtr->BaseAddress, - TmrCtrNumber, XTC_TCSR_OFFSET); - - return ((CounterControlReg & XTC_CSR_INT_OCCURED_MASK) == - XTC_CSR_INT_OCCURED_MASK); -} - -/***************************************************************************** -* -* Looks up the device configuration based on the unique device ID. The table -* TmrCtrConfigTable contains the configuration info for each device in the -* system. -* -* @param DeviceId is the unique device ID to search for in the config -* table. -* -* @return A pointer to the configuration that matches the given device ID, -* or NULL if no match is found. -* -* @note None. -* -******************************************************************************/ -XTmrCtr_Config *XTmrCtr_LookupConfig(u16 DeviceId) -{ - XTmrCtr_Config *CfgPtr = NULL; - int Index; - - for (Index = 0; Index < XPAR_XTMRCTR_NUM_INSTANCES; Index++) { - if (XTmrCtr_ConfigTable[Index].DeviceId == DeviceId) { - CfgPtr = &XTmrCtr_ConfigTable[Index]; - break; - } - } - - return CfgPtr; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr.h deleted file mode 100644 index 3ae4800778d037930a75ce5a42aaa39341689cf5..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr.h +++ /dev/null @@ -1,309 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2002-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xtmrctr.h -* -* The Xilinx timer/counter component. This component supports the Xilinx -* timer/counter. More detailed description of the driver operation can -* be found in the xtmrctr.c file. -* -* The Xilinx timer/counter supports the following features: -* - Polled mode. -* - Interrupt driven mode -* - enabling and disabling specific timers -* - PWM operation -* - Cascade Operation (This is to be used for getting a 64 bit timer and this -* feature is present in the latest versions of the axi_timer IP) -* -* The driver does not currently support the PWM operation of the device. -* -* The timer counter operates in 2 primary modes, compare and capture. In -* either mode, the timer counter may count up or down, with up being the -* default. -* -* Compare mode is typically used for creating a single time period or multiple -* repeating time periods in the auto reload mode, such as a periodic interrupt. -* When started, the timer counter loads an initial value, referred to as the -* compare value, into the timer counter and starts counting down or up. The -* timer counter expires when it rolls over/under depending upon the mode of -* counting. An external compare output signal may be configured such that a -* pulse is generated with this signal when it hits the compare value. -* -* Capture mode is typically used for measuring the time period between -* external events. This mode uses an external capture input signal to cause -* the value of the timer counter to be captured. When started, the timer -* counter loads an initial value, referred to as the compare value, - -* The timer can be configured to either cause an interrupt when the count -* reaches the compare value in compare mode or latch the current count -* value in the capture register when an external input is asserted -* in capture mode. The external capture input can be enabled/disabled using the -* XTmrCtr_SetOptions function. While in compare mode, it is also possible to -* drive an external output when the compare value is reached in the count -* register The external compare output can be enabled/disabled using the -* XTmrCtr_SetOptions function. -* -* <b>Interrupts</b> -* -* It is the responsibility of the application to connect the interrupt -* handler of the timer/counter to the interrupt source. The interrupt -* handler function, XTmrCtr_InterruptHandler, is visible such that the user -* can connect it to the interrupt source. Note that this interrupt handler -* does not provide interrupt context save and restore processing, the user -* must perform this processing. -* -* The driver services interrupts and passes timeouts to the upper layer -* software through callback functions. The upper layer software must register -* its callback functions during initialization. The driver requires callback -* functions for timers. -* -* @note -* The default settings for the timers are: -* - Interrupt generation disabled -* - Count up mode -* - Compare mode -* - Hold counter (will not reload the timer) -* - External compare output disabled -* - External capture input disabled -* - Pulse width modulation disabled -* - Timer disabled, waits for Start function to be called -* <br><br> -* A timer counter device may contain multiple timer counters. The symbol -* XTC_DEVICE_TIMER_COUNT defines the number of timer counters in the device. -* The device currently contains 2 timer counters. -* <br><br> -* This driver is intended to be RTOS and processor independent. It works with -* physical addresses only. Any needs for dynamic memory management, threads -* or thread mutual exclusion, virtual memory, or cache control must be -* satisfied by the layer above this driver. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00a ecm 08/16/01 First release -* 1.00b jhl 02/21/02 Repartitioned the driver for smaller files -* 1.10b mta 03/21/07 Updated to new coding style. -* 1.11a sdm 08/22/08 Removed support for static interrupt handlers from the MDD -* file -* 2.00a ktn 10/30/09 Updated to use HAL API's. _m is removed from all the macro -* definitions. -* 2.01a ktn 07/12/10 Renamed the macro XTimerCtr_ReadReg as XTmrCtr_ReadReg -* for naming consistency (CR 559142). -* 2.02a sdm 09/28/10 Updated the driver tcl to generate the xparameters -* for the timer clock frequency (CR 572679). -* 2.03a rvo 11/30/10 Added check to see if interrupt is enabled before further -* processing for CR 584557. -* 2.04a sdm 07/12/11 Added support for cascade mode operation. -* The cascade mode of operation is present in the latest -* versions of the axi_timer IP. Please check the HW -* Datasheet to see whether this feature is present in the -* version of the IP that you are using. -* 2.05a adk 15/05/13 Fixed the CR:693066 -* Added the IsStartedTmrCtr0/IsStartedTmrCtr1 members to the -* XTmrCtr instance structure. -* The IsStartedTmrCtrX will be assigned XIL_COMPONENT_IS_STARTED in -* the XTmrCtr_Start function. -* The IsStartedTmrCtrX will be cleared in the XTmrCtr_Stop function. -* There will be no Initialization done in the -* XTmrCtr_Initialize if both the timers have already started and -* the XST_DEVICE_IS_STARTED Status is returned. -* Removed the logic in the XTmrCtr_Initialize function -* which was checking the Register Value to know whether -* a timer has started or not. -* </pre> -* -******************************************************************************/ - -#ifndef XTMRCTR_H /* prevent circular inclusions */ -#define XTMRCTR_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xstatus.h" -#include "xtmrctr_l.h" - -/************************** Constant Definitions *****************************/ - -/** - * @name Configuration options - * These options are used in XTmrCtr_SetOptions() and XTmrCtr_GetOptions() - * @{ - */ -/** - * Used to configure the timer counter device. - * <pre> - * XTC_CASCADE_MODE_OPTION Enables the Cascade Mode only valid for TCSRO. - * XTC_ENABLE_ALL_OPTION Enables all timer counters at once. - * XTC_DOWN_COUNT_OPTION Configures the timer counter to count down from - * start value, the default is to count up. - * XTC_CAPTURE_MODE_OPTION Configures the timer to capture the timer - * counter value when the external capture line is - * asserted. The default mode is compare mode. - * XTC_INT_MODE_OPTION Enables the timer counter interrupt output. - * XTC_AUTO_RELOAD_OPTION In compare mode, configures the timer counter to - * reload from the compare value. The default mode - * causes the timer counter to hold when the - * compare value is hit. - * In capture mode, configures the timer counter to - * not hold the previous capture value if a new - * event occurs. The default mode cause the timer - * counter to hold the capture value until - * recognized. - * XTC_EXT_COMPARE_OPTION Enables the external compare output signal. - * </pre> - */ -#define XTC_CASCADE_MODE_OPTION 0x00000080UL -#define XTC_ENABLE_ALL_OPTION 0x00000040UL -#define XTC_DOWN_COUNT_OPTION 0x00000020UL -#define XTC_CAPTURE_MODE_OPTION 0x00000010UL -#define XTC_INT_MODE_OPTION 0x00000008UL -#define XTC_AUTO_RELOAD_OPTION 0x00000004UL -#define XTC_EXT_COMPARE_OPTION 0x00000002UL -/*@}*/ - -/**************************** Type Definitions *******************************/ - -/** - * This typedef contains configuration information for the device. - */ -typedef struct { - u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddress;/**< Register base address */ -} XTmrCtr_Config; - -/** - * Signature for the callback function. - * - * @param CallBackRef is a callback reference passed in by the upper layer - * when setting the callback functions, and passed back to the - * upper layer when the callback is invoked. Its type is - * unimportant to the driver, so it is a void pointer. - * @param TmrCtrNumber is the number of the timer/counter within the - * device. The device typically contains at least two - * timer/counters. The timer number is a zero based number with a - * range of 0 to (XTC_DEVICE_TIMER_COUNT - 1). - */ -typedef void (*XTmrCtr_Handler) (void *CallBackRef, u8 TmrCtrNumber); - - -/** - * Timer/Counter statistics - */ -typedef struct { - u32 Interrupts; /**< The number of interrupts that have occurred */ -} XTmrCtrStats; - -/** - * The XTmrCtr driver instance data. The user is required to allocate a - * variable of this type for every timer/counter device in the system. A - * pointer to a variable of this type is then passed to the driver API - * functions. - */ -typedef struct { - XTmrCtrStats Stats; /**< Component Statistics */ - u32 BaseAddress; /**< Base address of registers */ - u32 IsReady; /**< Device is initialized and ready */ - u32 IsStartedTmrCtr0; /**< Is Timer Counter 0 started */ - u32 IsStartedTmrCtr1; /**< Is Timer Counter 1 started */ - - XTmrCtr_Handler Handler; /**< Callback function */ - void *CallBackRef; /**< Callback reference for handler */ -} XTmrCtr; - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - -/* - * Required functions, in file xtmrctr.c - */ -int XTmrCtr_Initialize(XTmrCtr * InstancePtr, u16 DeviceId); -void XTmrCtr_Start(XTmrCtr * InstancePtr, u8 TmrCtrNumber); -void XTmrCtr_Stop(XTmrCtr * InstancePtr, u8 TmrCtrNumber); -u32 XTmrCtr_GetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber); -void XTmrCtr_SetResetValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber, - u32 ResetValue); -u32 XTmrCtr_GetCaptureValue(XTmrCtr * InstancePtr, u8 TmrCtrNumber); -int XTmrCtr_IsExpired(XTmrCtr * InstancePtr, u8 TmrCtrNumber); -void XTmrCtr_Reset(XTmrCtr * InstancePtr, u8 TmrCtrNumber); -XTmrCtr_Config *XTmrCtr_LookupConfig(u16 DeviceId); - -/* - * Functions for options, in file xtmrctr_options.c - */ -void XTmrCtr_SetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber, u32 Options); -u32 XTmrCtr_GetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber); - -/* - * Functions for statistics, in file xtmrctr_stats.c - */ -void XTmrCtr_GetStats(XTmrCtr * InstancePtr, XTmrCtrStats * StatsPtr); -void XTmrCtr_ClearStats(XTmrCtr * InstancePtr); - -/* - * Functions for self-test, in file xtmrctr_selftest.c - */ -int XTmrCtr_SelfTest(XTmrCtr * InstancePtr, u8 TmrCtrNumber); - -/* - * Functions for interrupts, in file xtmrctr_intr.c - */ -void XTmrCtr_SetHandler(XTmrCtr * InstancePtr, XTmrCtr_Handler FuncPtr, - void *CallBackRef); -void XTmrCtr_InterruptHandler(void *InstancePtr); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr_g.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr_g.c deleted file mode 100644 index bf05e92063a107574b46b49e443202417f66524c..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr_g.c +++ /dev/null @@ -1,30 +0,0 @@ - -/******************************************************************* -* -* CAUTION: This file is automatically generated by libgen. -* Version: Xilinx EDK 14.7 EDK_P.20131013 -* DO NOT EDIT. -* -* Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. - -* -* Description: Driver configuration -* -*******************************************************************/ - -#include "xparameters.h" -#include "xtmrctr.h" - -/* -* The configuration table for devices -*/ - -XTmrCtr_Config XTmrCtr_ConfigTable[] = -{ - { - XPAR_AXI_TIMER_0_DEVICE_ID, - XPAR_AXI_TIMER_0_BASEADDR - } -}; - - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr_i.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr_i.h deleted file mode 100644 index bcdb900d36fd00d8bd10a971d5db3d927f958685..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr_i.h +++ /dev/null @@ -1,88 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2002-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xtmrctr_i.h -* -* This file contains data which is shared between files internal to the -* XTmrCtr component. It is intended for internal use only. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00b jhl 02/06/02 First release -* 1.10b mta 03/21/07 Updated to new coding style -* 2.00a ktn 10/30/09 _m is removed from all the macro definitions. -* </pre> -* -******************************************************************************/ - -#ifndef XTMRCTR_I_H /* prevent circular inclusions */ -#define XTMRCTR_I_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" - -/************************** Constant Definitions *****************************/ - - -/************************** Function Prototypes ******************************/ - - -/************************** Variable Definitions *****************************/ - -extern XTmrCtr_Config XTmrCtr_ConfigTable[]; - -extern u8 XTmrCtr_Offsets[]; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr_intr.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr_intr.c deleted file mode 100644 index 5b8b94cf22e32bcda7c6a04aa15c0206d4874d54..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr_intr.c +++ /dev/null @@ -1,239 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2002-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xtmrctr_intr.c -* -* Contains interrupt-related functions for the XTmrCtr component. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00b jhl 02/06/02 First release -* 1.10b mta 03/21/07 Updated to new coding style -* 2.00a ktn 10/30/09 Updated to use HAL API's. _m is removed from all the macro -* definitions. -* 2.03a rvo 11/30/10 Added check to see if interrupt is enabled before further -* processing for CR 584557. -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xtmrctr.h" - - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - - -/************************** Variable Definitions *****************************/ - - -/*****************************************************************************/ -/** -* -* Sets the timer callback function, which the driver calls when the specified -* timer times out. -* -* @param InstancePtr is a pointer to the XTmrCtr instance . -* @param CallBackRef is the upper layer callback reference passed back -* when the callback function is invoked. -* @param FuncPtr is the pointer to the callback function. -* -* @return None. -* -* @note -* -* The handler is called within interrupt context so the function that is -* called should either be short or pass the more extensive processing off -* to another task to allow the interrupt to return and normal processing -* to continue. -* -******************************************************************************/ -void XTmrCtr_SetHandler(XTmrCtr * InstancePtr, XTmrCtr_Handler FuncPtr, - void *CallBackRef) -{ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(FuncPtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - InstancePtr->Handler = FuncPtr; - InstancePtr->CallBackRef = CallBackRef; -} - -/*****************************************************************************/ -/** -* -* Interrupt Service Routine (ISR) for the driver. This function only performs -* processing for the device and does not save and restore the interrupt context. -* -* @param InstancePtr contains a pointer to the timer/counter instance for -* the interrupt. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XTmrCtr_InterruptHandler(void *InstancePtr) -{ - XTmrCtr *TmrCtrPtr = NULL; - u8 TmrCtrNumber; - u32 ControlStatusReg; - - /* - * Verify that each of the inputs are valid. - */ - Xil_AssertVoid(InstancePtr != NULL); - - /* - * Convert the non-typed pointer to an timer/counter instance pointer - * such that there is access to the timer/counter - */ - TmrCtrPtr = (XTmrCtr *) InstancePtr; - - /* - * Loop thru each timer counter in the device and call the callback - * function for each timer which has caused an interrupt - */ - for (TmrCtrNumber = 0; - TmrCtrNumber < XTC_DEVICE_TIMER_COUNT; TmrCtrNumber++) { - - ControlStatusReg = XTmrCtr_ReadReg(TmrCtrPtr->BaseAddress, - TmrCtrNumber, - XTC_TCSR_OFFSET); - /* - * Check if interrupt is enabled - */ - if (ControlStatusReg & XTC_CSR_ENABLE_INT_MASK) { - - /* - * Check if timer expired and interrupt occured - */ - if (ControlStatusReg & XTC_CSR_INT_OCCURED_MASK) { - /* - * Increment statistics for the number of - * interrupts and call the callback to handle - * any application specific processing - */ - TmrCtrPtr->Stats.Interrupts++; - TmrCtrPtr->Handler(TmrCtrPtr->CallBackRef, - TmrCtrNumber); - /* - * Read the new Control/Status Register content. - */ - ControlStatusReg = - XTmrCtr_ReadReg(TmrCtrPtr->BaseAddress, - TmrCtrNumber, - XTC_TCSR_OFFSET); - /* - * If in compare mode and a single shot rather - * than auto reload mode then disable the timer - * and reset it such so that the interrupt can - * be acknowledged, this should be only temporary - * till the hardware is fixed - */ - if (((ControlStatusReg & - XTC_CSR_AUTO_RELOAD_MASK) == 0) && - ((ControlStatusReg & - XTC_CSR_CAPTURE_MODE_MASK)== 0)) { - /* - * Disable the timer counter and - * reset it such that the timer - * counter is loaded with the - * reset value allowing the - * interrupt to be acknowledged - */ - ControlStatusReg &= - ~XTC_CSR_ENABLE_TMR_MASK; - - XTmrCtr_WriteReg( - TmrCtrPtr->BaseAddress, - TmrCtrNumber, - XTC_TCSR_OFFSET, - ControlStatusReg | - XTC_CSR_LOAD_MASK); - - /* - * Clear the reset condition, - * the reset bit must be - * manually cleared by a 2nd write - * to the register - */ - XTmrCtr_WriteReg( - TmrCtrPtr->BaseAddress, - TmrCtrNumber, - XTC_TCSR_OFFSET, - ControlStatusReg); - } - - /* - * Acknowledge the interrupt by clearing the - * interrupt bit in the timer control status - * register, this is done after calling the - * handler so the application could call - * IsExpired, the interrupt is cleared by - * writing a 1 to the interrupt bit of the - * register without changing any of the other - * bits - */ - XTmrCtr_WriteReg(TmrCtrPtr->BaseAddress, - TmrCtrNumber, - XTC_TCSR_OFFSET, - ControlStatusReg | - XTC_CSR_INT_OCCURED_MASK); - } - } - } -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr_l.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr_l.c deleted file mode 100644 index 766a0bd406b9b889babe3bc0ad63ab32280c0ef9..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr_l.c +++ /dev/null @@ -1,85 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2002-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xtmrctr_l.c -* -* This file contains low-level driver functions that can be used to access the -* device. The user should refer to the hardware device specification for more -* details of the device operation. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00b jhl 04/24/02 First release -* 1.10b mta 03/21/07 Updated to new coding style -* 2.00a ktn 10/30/09 Updated to use HAL API's -* </pre> -* -******************************************************************************/ - - -/***************************** Include Files *********************************/ - -#include "xtmrctr_l.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - - -/************************** Variable Definitions *****************************/ - -/* The following table contains the offset from the base address of a timer - * counter device for each timer counter. A single device may contain multiple - * timer counters and the functions specify which one to operate on. - */ -u8 XTmrCtr_Offsets[] = { 0, XTC_TIMER_COUNTER_OFFSET }; diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr_l.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr_l.h deleted file mode 100644 index f926520351090eacab18d58a8fd92a7f0b15f1e5..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr_l.h +++ /dev/null @@ -1,435 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2002-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xtmrctr_l.h -* -* This header file contains identifiers and low-level driver functions (or -* macros) that can be used to access the device. The user should refer to the -* hardware device specification for more details of the device operation. -* High-level driver functions are defined in xtmrctr.h. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00b jhl 04/24/02 First release -* 1.10b mta 03/21/07 Updated to new coding style -* 2.00a ktn 10/30/09 Updated to use HAL API's. _m is removed from all the macro -* definitions. -* 2.01a ktn 07/12/10 Renamed the macro XTimerCtr_ReadReg as XTmrCtr_ReadReg -* for naming consistency (CR 559142). -* 2.04a sdm 07/12/11 Added the CASC mode bit in the TCSRO register for the -* cascade mode operation. -* The cascade mode of operation is present in the latest -* versions of the axi_timer IP. Please check the HW -* Datasheet to see whether this feature is present in the -* version of the IP that you are using. -* </pre> -* -******************************************************************************/ - -#ifndef XTMRCTR_L_H /* prevent circular inclusions */ -#define XTMRCTR_L_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_io.h" - -/************************** Constant Definitions *****************************/ - -/** - * Defines the number of timer counters within a single hardware device. This - * number is not currently parameterized in the hardware but may be in the - * future. - */ -#define XTC_DEVICE_TIMER_COUNT 2 - -/* Each timer counter consumes 16 bytes of address space */ - -#define XTC_TIMER_COUNTER_OFFSET 16 - -/** @name Register Offset Definitions - * Register offsets within a timer counter, there are multiple - * timer counters within a single device - * @{ - */ - -#define XTC_TCSR_OFFSET 0 /**< Control/Status register */ -#define XTC_TLR_OFFSET 4 /**< Load register */ -#define XTC_TCR_OFFSET 8 /**< Timer counter register */ - -/* @} */ - -/** @name Control Status Register Bit Definitions - * Control Status Register bit masks - * Used to configure the timer counter device. - * @{ - */ - -#define XTC_CSR_CASC_MASK 0x00000800 /**< Cascade Mode */ -#define XTC_CSR_ENABLE_ALL_MASK 0x00000400 /**< Enables all timer - counters */ -#define XTC_CSR_ENABLE_PWM_MASK 0x00000200 /**< Enables the Pulse Width - Modulation */ -#define XTC_CSR_INT_OCCURED_MASK 0x00000100 /**< If bit is set, an - interrupt has occured. - If set and '1' is - written to this bit - position, bit is - cleared. */ -#define XTC_CSR_ENABLE_TMR_MASK 0x00000080 /**< Enables only the - specific timer */ -#define XTC_CSR_ENABLE_INT_MASK 0x00000040 /**< Enables the interrupt - output. */ -#define XTC_CSR_LOAD_MASK 0x00000020 /**< Loads the timer using - the load value provided - earlier in the Load - Register, - XTC_TLR_OFFSET. */ -#define XTC_CSR_AUTO_RELOAD_MASK 0x00000010 /**< In compare mode, - configures - the timer counter to - reload from the - Load Register. The - default mode - causes the timer counter - to hold when the compare - value is hit. In capture - mode, configures the - timer counter to not - hold the previous - capture value if a new - event occurs. The - default mode cause the - timer counter to hold - the capture value until - recognized. */ -#define XTC_CSR_EXT_CAPTURE_MASK 0x00000008 /**< Enables the - external input - to the timer counter. */ -#define XTC_CSR_EXT_GENERATE_MASK 0x00000004 /**< Enables the - external generate output - for the timer. */ -#define XTC_CSR_DOWN_COUNT_MASK 0x00000002 /**< Configures the timer - counter to count down - from start value, the - default is to count - up.*/ -#define XTC_CSR_CAPTURE_MODE_MASK 0x00000001 /**< Enables the timer to - capture the timer - counter value when the - external capture line is - asserted. The default - mode is compare mode.*/ -/* @} */ - -/**************************** Type Definitions *******************************/ - -extern u8 XTmrCtr_Offsets[]; - -/***************** Macros (Inline Functions) Definitions *********************/ - -/*****************************************************************************/ -/** -* Read one of the timer counter registers. -* -* @param BaseAddress contains the base address of the timer counter -* device. -* @param TmrCtrNumber contains the specific timer counter within the -* device, a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* @param RegOffset contains the offset from the 1st register of the timer -* counter to select the specific register of the timer counter. -* -* @return The value read from the register, a 32 bit value. -* -* @note C-Style signature: -* u32 XTmrCtr_ReadReg(u32 BaseAddress, u8 TimerNumber, - unsigned RegOffset); -******************************************************************************/ -#define XTmrCtr_ReadReg(BaseAddress, TmrCtrNumber, RegOffset) \ - Xil_In32((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \ - (RegOffset)) - -#ifndef XTimerCtr_ReadReg -#define XTimerCtr_ReadReg XTmrCtr_ReadReg -#endif - -/*****************************************************************************/ -/** -* Write a specified value to a register of a timer counter. -* -* @param BaseAddress is the base address of the timer counter device. -* @param TmrCtrNumber is the specific timer counter within the device, a -* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* @param RegOffset contain the offset from the 1st register of the timer -* counter to select the specific register of the timer counter. -* @param ValueToWrite is the 32 bit value to be written to the register. -* -* @note C-Style signature: -* void XTmrCtr_WriteReg(u32 BaseAddress, u8 TimerNumber, -* unsigned RegOffset, u32 ValueToWrite); -******************************************************************************/ -#define XTmrCtr_WriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\ - Xil_Out32(((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \ - (RegOffset)), (ValueToWrite)) - -/****************************************************************************/ -/** -* -* Set the Control Status Register of a timer counter to the specified value. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, a -* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* @param RegisterValue is the 32 bit value to be written to the register. -* -* @return None. -* -* @note C-Style signature: -* void XTmrCtr_SetControlStatusReg(u32 BaseAddress, -* u8 TmrCtrNumber,u32 RegisterValue); -*****************************************************************************/ -#define XTmrCtr_SetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\ - XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \ - (RegisterValue)) - -/****************************************************************************/ -/** -* -* Get the Control Status Register of a timer counter. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, -* a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return The value read from the register, a 32 bit value. -* -* @note C-Style signature: -* u32 XTmrCtr_GetControlStatusReg(u32 BaseAddress, -* u8 TmrCtrNumber); -*****************************************************************************/ -#define XTmrCtr_GetControlStatusReg(BaseAddress, TmrCtrNumber) \ - XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET) - -/****************************************************************************/ -/** -* -* Get the Timer Counter Register of a timer counter. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, -* a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return The value read from the register, a 32 bit value. -* -* @note C-Style signature: -* u32 XTmrCtr_GetTimerCounterReg(u32 BaseAddress, -* u8 TmrCtrNumber); -*****************************************************************************/ -#define XTmrCtr_GetTimerCounterReg(BaseAddress, TmrCtrNumber) \ - XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TCR_OFFSET) \ - -/****************************************************************************/ -/** -* -* Set the Load Register of a timer counter to the specified value. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, a -* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* @param RegisterValue is the 32 bit value to be written to the register. -* -* @return None. -* -* @note C-Style signature: -* void XTmrCtr_SetLoadReg(u32 BaseAddress, u8 TmrCtrNumber, -* u32 RegisterValue); -*****************************************************************************/ -#define XTmrCtr_SetLoadReg(BaseAddress, TmrCtrNumber, RegisterValue) \ - XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TLR_OFFSET, \ - (RegisterValue)) - -/****************************************************************************/ -/** -* -* Get the Load Register of a timer counter. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, a -* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return The value read from the register, a 32 bit value. -* -* @note C-Style signature: -* u32 XTmrCtr_GetLoadReg(u32 BaseAddress, u8 TmrCtrNumber); -*****************************************************************************/ -#define XTmrCtr_GetLoadReg(BaseAddress, TmrCtrNumber) \ -XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), XTC_TLR_OFFSET) - -/****************************************************************************/ -/** -* -* Enable a timer counter such that it starts running. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, a -* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return None. -* -* @note C-Style signature: -* void XTmrCtr_Enable(u32 BaseAddress, u8 TmrCtrNumber); -*****************************************************************************/ -#define XTmrCtr_Enable(BaseAddress, TmrCtrNumber) \ - XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \ - (XTmrCtr_ReadReg((BaseAddress), ( TmrCtrNumber), \ - XTC_TCSR_OFFSET) | XTC_CSR_ENABLE_TMR_MASK)) - -/****************************************************************************/ -/** -* -* Disable a timer counter such that it stops running. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, -* a zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return None. -* -* @note C-Style signature: -* void XTmrCtr_Disable(u32 BaseAddress, u8 TmrCtrNumber); -*****************************************************************************/ -#define XTmrCtr_Disable(BaseAddress, TmrCtrNumber) \ - XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \ - (XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),\ - XTC_TCSR_OFFSET) & ~ XTC_CSR_ENABLE_TMR_MASK)) - -/****************************************************************************/ -/** -* -* Enable the interrupt for a timer counter. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, a -* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return None. -* -* @note C-Style signature: -* void XTmrCtr_EnableIntr(u32 BaseAddress, u8 TmrCtrNumber); -*****************************************************************************/ -#define XTmrCtr_EnableIntr(BaseAddress, TmrCtrNumber) \ - XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \ - (XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), \ - XTC_TCSR_OFFSET) | XTC_CSR_ENABLE_INT_MASK)) - -/****************************************************************************/ -/** -* -* Disable the interrupt for a timer counter. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, a -* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return None. -* -* @note C-Style signature: -* void XTmrCtr_DisableIntr(u32 BaseAddress, u8 TmrCtrNumber); -*****************************************************************************/ -#define XTmrCtr_DisableIntr(BaseAddress, TmrCtrNumber) \ - XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \ - (XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), \ - XTC_TCSR_OFFSET) & ~ XTC_CSR_ENABLE_INT_MASK)) - -/****************************************************************************/ -/** -* -* Cause the timer counter to load it's Timer Counter Register with the value -* in the Load Register. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, a -* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return None. -* -* @note C-Style signature: -* void XTmrCtr_LoadTimerCounterReg(u32 BaseAddress, - u8 TmrCtrNumber); -*****************************************************************************/ -#define XTmrCtr_LoadTimerCounterReg(BaseAddress, TmrCtrNumber) \ - XTmrCtr_WriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \ - (XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber),\ - XTC_TCSR_OFFSET) | XTC_CSR_LOAD_MASK)) - -/****************************************************************************/ -/** -* -* Determine if a timer counter event has occurred. Events are defined to be -* when a capture has occurred or the counter has roller over. -* -* @param BaseAddress is the base address of the device. -* @param TmrCtrNumber is the specific timer counter within the device, a -* zero based number, 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @note C-Style signature: -* int XTmrCtr_HasEventOccurred(u32 BaseAddress, u8 TmrCtrNumber); -*****************************************************************************/ -#define XTmrCtr_HasEventOccurred(BaseAddress, TmrCtrNumber) \ - ((XTmrCtr_ReadReg((BaseAddress), (TmrCtrNumber), \ - XTC_TCSR_OFFSET) & XTC_CSR_INT_OCCURED_MASK) == \ - XTC_CSR_INT_OCCURED_MASK) - -/************************** Function Prototypes ******************************/ -/************************** Variable Definitions *****************************/ -#ifdef __cplusplus -} -#endif -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr_options.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr_options.c deleted file mode 100644 index c070f27ca6455c898017c3c41392558b91834b4b..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr_options.c +++ /dev/null @@ -1,223 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2002-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xtmrctr_options.c -* -* Contains configuration options functions for the XTmrCtr component. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00b jhl 02/06/02 First release -* 1.10b mta 03/21/07 Updated to new coding style -* 2.00a ktn 10/30/09 Updated to use HAL API's. _m is removed from all the macro -* definitions. -* 2.04a sdm 07/12/11 Added support for the cascade mode operation. -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xtmrctr.h" -#include "xtmrctr_i.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - - -/************************** Variable Definitions *****************************/ - -/* - * The following data type maps an option to a register mask such that getting - * and setting the options may be table driven. - */ -typedef struct { - u32 Option; - u32 Mask; -} Mapping; - -/* - * Create the table which contains options which are to be processed to get/set - * the options. These options are table driven to allow easy maintenance and - * expansion of the options. - */ -static Mapping OptionsTable[] = { - {XTC_CASCADE_MODE_OPTION, XTC_CSR_CASC_MASK}, - {XTC_ENABLE_ALL_OPTION, XTC_CSR_ENABLE_ALL_MASK}, - {XTC_DOWN_COUNT_OPTION, XTC_CSR_DOWN_COUNT_MASK}, - {XTC_CAPTURE_MODE_OPTION, XTC_CSR_CAPTURE_MODE_MASK | - XTC_CSR_EXT_CAPTURE_MASK}, - {XTC_INT_MODE_OPTION, XTC_CSR_ENABLE_INT_MASK}, - {XTC_AUTO_RELOAD_OPTION, XTC_CSR_AUTO_RELOAD_MASK}, - {XTC_EXT_COMPARE_OPTION, XTC_CSR_EXT_GENERATE_MASK} -}; - -/* Create a constant for the number of entries in the table */ - -#define XTC_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(Mapping)) - -/*****************************************************************************/ -/** -* -* Enables the specified options for the specified timer counter. This function -* sets the options without regard to the current options of the driver. To -* prevent a loss of the current options, the user should call -* XTmrCtr_GetOptions() prior to this function and modify the retrieved options -* to pass into this function to prevent loss of the current options. -* -* @param InstancePtr is a pointer to the XTmrCtr instance. -* @param TmrCtrNumber is the timer counter of the device to operate on. -* Each device may contain multiple timer counters. The timer -* number is a zero based number with a range of -* 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* @param Options contains the desired options to be set or cleared. -* Setting the option to '1' enables the option, clearing the to -* '0' disables the option. The options are bit masks such that -* multiple options may be set or cleared. The options are -* described in xtmrctr.h. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XTmrCtr_SetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber, u32 Options) -{ - u32 CounterControlReg = 0; - u32 Index; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Loop through the Options table, turning the enable on or off - * depending on whether the bit is set in the incoming Options flag. - */ - - for (Index = 0; Index < XTC_NUM_OPTIONS; Index++) { - if (Options & OptionsTable[Index].Option) { - - /* - * Turn the option on - */ - CounterControlReg |= OptionsTable[Index].Mask; - } - else { - /* - * Turn the option off - */ - CounterControlReg &= ~OptionsTable[Index].Mask; - } - } - - /* - * Write out the updated value to the actual register - */ - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TCSR_OFFSET, CounterControlReg); -} - -/*****************************************************************************/ -/** -* -* Get the options for the specified timer counter. -* -* @param InstancePtr is a pointer to the XTmrCtr instance. -* @param TmrCtrNumber is the timer counter of the device to operate on -* Each device may contain multiple timer counters. The timer -* number is a zero based number with a range of -* 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return -* -* The currently set options. An option which is set to a '1' is enabled and -* set to a '0' is disabled. The options are bit masks such that multiple -* options may be set or cleared. The options are described in xtmrctr.h. -* -* @note None. -* -******************************************************************************/ -u32 XTmrCtr_GetOptions(XTmrCtr * InstancePtr, u8 TmrCtrNumber) -{ - - u32 Options = 0; - u32 CounterControlReg; - u32 Index; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the current contents of the control status register to allow - * the current options to be determined - */ - CounterControlReg = XTmrCtr_ReadReg(InstancePtr->BaseAddress, - TmrCtrNumber, XTC_TCSR_OFFSET); - /* - * Loop through the Options table, turning the enable on or off - * depending on whether the bit is set in the current register settings. - */ - for (Index = 0; Index < XTC_NUM_OPTIONS; Index++) { - if (CounterControlReg & OptionsTable[Index].Mask) { - Options |= OptionsTable[Index].Option; /* turn it on */ - } - else { - Options &= ~OptionsTable[Index].Option; /* turn it off */ - } - } - - return Options; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr_selftest.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr_selftest.c deleted file mode 100644 index 964bd54acade473de086f6239ea04e72de335008..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr_selftest.c +++ /dev/null @@ -1,172 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2002-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xtmrctr_selftest.c -* -* Contains diagnostic/self-test functions for the XTmrCtr component. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00b jhl 02/06/02 First release -* 1.10b mta 03/21/07 Updated to new coding style -* 2.00a ktn 10/30/09 Updated to use HAL API's. _m is removed from all the macro -* definitions. -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xil_io.h" -#include "xtmrctr.h" -#include "xtmrctr_i.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - - -/************************** Variable Definitions *****************************/ - - -/*****************************************************************************/ -/** -* -* Runs a self-test on the driver/device. This test verifies that the specified -* timer counter of the device can be enabled and increments. -* -* @param InstancePtr is a pointer to the XTmrCtr instance. -* @param TmrCtrNumber is the timer counter of the device to operate on. -* Each device may contain multiple timer counters. The timer -* number is a zero based number with a range of -* 0 - (XTC_DEVICE_TIMER_COUNT - 1). -* -* @return -* - XST_SUCCESS if self-test was successful -* - XST_FAILURE if the timer is not incrementing. -* -* @note -* -* This is a destructive test using the provided timer. The current settings -* of the timer are returned to the initialized values and all settings at the -* time this function is called are overwritten. -* -******************************************************************************/ -int XTmrCtr_SelfTest(XTmrCtr * InstancePtr, u8 TmrCtrNumber) -{ - u32 TimerCount1 = 0; - u32 TimerCount2 = 0; - u16 Count = 0; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(TmrCtrNumber < XTC_DEVICE_TIMER_COUNT); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Set the Capture register to 0 - */ - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TLR_OFFSET, 0); - - /* - * Reset the timer and the interrupt - */ - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TCSR_OFFSET, - XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK); - - /* - * Set the control/status register to enable timer - */ - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TCSR_OFFSET, XTC_CSR_ENABLE_TMR_MASK); - - /* - * Read the timer - */ - TimerCount1 = XTmrCtr_ReadReg(InstancePtr->BaseAddress, - TmrCtrNumber, XTC_TCR_OFFSET); - /* - * Make sure timer is incrementing if the Count rolls over to zero - * and the timer still has not incremented an error is returned - */ - - do { - TimerCount2 = XTmrCtr_ReadReg(InstancePtr->BaseAddress, - TmrCtrNumber, XTC_TCR_OFFSET); - Count++; - } - while ((TimerCount1 == TimerCount2) && (Count != 0)); - - /* - * Reset the timer and the interrupt - */ - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TCSR_OFFSET, - XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK); - - /* - * Set the control/status register to 0 to complete initialization - * this disables the timer completely and allows it to be used again - */ - - XTmrCtr_WriteReg(InstancePtr->BaseAddress, TmrCtrNumber, - XTC_TCSR_OFFSET, 0); - - if (TimerCount1 == TimerCount2) { - return XST_FAILURE; - } - else { - return XST_SUCCESS; - } -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr_stats.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr_stats.c deleted file mode 100644 index fc0da5f1b30b4d4b1af5ad39082cc8ef8ba77957..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/tmrctr_v2_05_a/src/xtmrctr_stats.c +++ /dev/null @@ -1,121 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2002-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xtmrctr_stats.c -* -* Contains function to get and clear statistics for the XTmrCtr component. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.00b jhl 02/06/02 First release. -* 1.10b mta 03/21/07 Updated for new coding style. -* 2.00a ktn 10/30/09 Updated to use HAL API's. -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xtmrctr.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - - -/************************** Variable Definitions *****************************/ - - -/*****************************************************************************/ -/** -* -* Get a copy of the XTmrCtrStats structure, which contains the current -* statistics for this driver. -* -* @param InstancePtr is a pointer to the XTmrCtr instance. -* @param StatsPtr is a pointer to a XTmrCtrStats structure which will get -* a copy of current statistics. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XTmrCtr_GetStats(XTmrCtr * InstancePtr, XTmrCtrStats * StatsPtr) -{ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(StatsPtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - StatsPtr->Interrupts = InstancePtr->Stats.Interrupts; -} - -/*****************************************************************************/ -/** -* -* Clear the XTmrCtrStats structure for this driver. -* -* @param InstancePtr is a pointer to the XTmrCtr instance. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XTmrCtr_ClearStats(XTmrCtr * InstancePtr) -{ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - InstancePtr->Stats.Interrupts = 0; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/Makefile b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/Makefile deleted file mode 100644 index 7d608cdae12f447d039b7397c4fb30f809114bb6..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -COMPILER= -ARCHIVER= -CP=cp -COMPILER_FLAGS= -EXTRA_COMPILER_FLAGS= -LIB=libxil.a - -CC_FLAGS = $(COMPILER_FLAGS) -ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) - -RELEASEDIR=../../../lib -INCLUDEDIR=../../../include -INCLUDES=-I./. -I${INCLUDEDIR} - -OUTS = *.o - -LIBSOURCES:=*.c -INCLUDEFILES:=*.h - -OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) - -libs: banner xuartps_libs clean - -%.o: %.c - ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< - -banner: - echo "Compiling uartps" - -xuartps_libs: ${OBJECTS} - $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} - -.PHONY: include -include: xuartps_includes - -xuartps_includes: - ${CP} ${INCLUDEFILES} ${INCLUDEDIR} - -clean: - rm -rf ${OBJECTS} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/xuartps.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/xuartps.c deleted file mode 100644 index ff89c945652a1c3d3a3fdb184435bd3c2265bde9..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/xuartps.c +++ /dev/null @@ -1,673 +0,0 @@ -/***************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -*****************************************************************************/ -/****************************************************************************/ -/** -* -* @file xuartps.c -* -* This file contains the implementation of the interface functions for XUartPs -* driver. Refer to the header file xuartps.h for more detailed information. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------ -------- ---------------------------------------------- -* 1.00 drg/jz 01/13/10 First Release -* </pre> -* -*****************************************************************************/ - -/***************************** Include Files ********************************/ - -#include "xstatus.h" -#include "xuartps.h" -#include "xil_io.h" - -/************************** Constant Definitions ****************************/ - -/* The following constant defines the amount of error that is allowed for - * a specified baud rate. This error is the difference between the actual - * baud rate that will be generated using the specified clock and the - * desired baud rate. - */ -#define XUARTPS_MAX_BAUD_ERROR_RATE 3 /* max % error allowed */ - -/**************************** Type Definitions ******************************/ - - -/***************** Macros (Inline Functions) Definitions ********************/ - - -/************************** Function Prototypes *****************************/ - -static void XUartPs_StubHandler(void *CallBackRef, u32 Event, - unsigned int ByteCount); - -unsigned int XUartPs_SendBuffer(XUartPs *InstancePtr); - -unsigned int XUartPs_ReceiveBuffer(XUartPs *InstancePtr); - -/************************** Variable Definitions ****************************/ - -/****************************************************************************/ -/** -* -* Initializes a specific XUartPs instance such that it is ready to be used. -* The data format of the device is setup for 8 data bits, 1 stop bit, and no -* parity by default. The baud rate is set to a default value specified by -* Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The -* receive FIFO threshold is set for 8 bytes. The default operating mode of the -* driver is polled mode. -* -* @param InstancePtr is a pointer to the XUartPs instance. -* @param Config is a reference to a structure containing information -* about a specific XUartPs driver. -* @param EffectiveAddr is the device base address in the virtual memory -* address space. The caller is responsible for keeping the address -* mapping from EffectiveAddr to the device physical base address -* unchanged once this function is invoked. Unexpected errors may -* occur if the address mapping changes after this function is -* called. If address translation is not used, pass in the physical -* address instead. -* -* @return -* -* - XST_SUCCESS if initialization was successful -* - XST_UART_BAUD_ERROR if the baud rate is not possible because -* the inputclock frequency is not divisible with an acceptable -* amount of error -* -* @note -* -* The default configuration for the UART after initialization is: -* -* - 19,200 bps or XPAR_DFT_BAUDRATE if defined -* - 8 data bits -* - 1 stop bit -* - no parity -* - FIFO's are enabled with a receive threshold of 8 bytes -* - The RX timeout is enabled with a timeout of 1 (4 char times) -* -* All interrupts are disabled. -* -*****************************************************************************/ -int XUartPs_CfgInitialize(XUartPs *InstancePtr, - XUartPs_Config * Config, u32 EffectiveAddr) -{ - int Status; - u32 ModeRegister; - u32 BaudRate; - - /* - * Assert validates the input arguments - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(Config != NULL); - - /* - * Setup the driver instance using passed in parameters - */ - InstancePtr->Config.BaseAddress = EffectiveAddr; - InstancePtr->Config.InputClockHz = Config->InputClockHz; - InstancePtr->Config.ModemPinsConnected = Config->ModemPinsConnected; - - /* - * Initialize other instance data to default values - */ - InstancePtr->Handler = XUartPs_StubHandler; - - InstancePtr->SendBuffer.NextBytePtr = NULL; - InstancePtr->SendBuffer.RemainingBytes = 0; - InstancePtr->SendBuffer.RequestedBytes = 0; - - InstancePtr->ReceiveBuffer.NextBytePtr = NULL; - InstancePtr->ReceiveBuffer.RemainingBytes = 0; - InstancePtr->ReceiveBuffer.RequestedBytes = 0; - - /* - * Flag that the driver instance is ready to use - */ - InstancePtr->IsReady = XIL_COMPONENT_IS_READY; - - /* - * Set the default baud rate here, can be changed prior to - * starting the device - */ - BaudRate = XUARTPS_DFT_BAUDRATE; - Status = XUartPs_SetBaudRate(InstancePtr, BaudRate); - if (Status != XST_SUCCESS) { - InstancePtr->IsReady = 0; - return Status; - } - - /* - * Set up the default data format: 8 bit data, 1 stop bit, no - * parity - */ - ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress, - XUARTPS_MR_OFFSET); - - /* - * Mask off what's already there - */ - ModeRegister &= ~(XUARTPS_MR_CHARLEN_MASK | - XUARTPS_MR_STOPMODE_MASK | - XUARTPS_MR_PARITY_MASK); - - /* - * Set the register value to the desired data format - */ - ModeRegister |= (XUARTPS_MR_CHARLEN_8_BIT | - XUARTPS_MR_STOPMODE_1_BIT | - XUARTPS_MR_PARITY_NONE); - - /* - * Write the mode register out - */ - XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET, - ModeRegister); - - /* - * Set the RX FIFO trigger at 8 data bytes. - */ - XUartPs_WriteReg(InstancePtr->Config.BaseAddress, - XUARTPS_RXWM_OFFSET, 0x08); - - /* - * Set the RX timeout to 1, which will be 4 character time - */ - XUartPs_WriteReg(InstancePtr->Config.BaseAddress, - XUARTPS_RXTOUT_OFFSET, 0x01); - - /* - * Disable all interrupts, polled mode is the default - */ - XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET, - XUARTPS_IXR_MASK); - - return XST_SUCCESS; -} - -/****************************************************************************/ -/** -* -* This functions sends the specified buffer using the device in either -* polled or interrupt driven mode. This function is non-blocking, if the device -* is busy sending data, it will return and indicate zero bytes were sent. -* Otherwise, it fills the TX FIFO as much as it can, and return the number of -* bytes sent. -* -* In a polled mode, this function will only send as much data as TX FIFO can -* buffer. The application may need to call it repeatedly to send the entire -* buffer. -* -* In interrupt mode, this function will start sending the specified buffer, -* then the interrupt handler will continue sending data until the entire -* buffer has been sent. A callback function, as specified by the application, -* will be called to indicate the completion of sending. -* -* @param InstancePtr is a pointer to the XUartPs instance. -* @param BufferPtr is pointer to a buffer of data to be sent. -* @param NumBytes contains the number of bytes to be sent. A value of -* zero will stop a previous send operation that is in progress -* in interrupt mode. Any data that was already put into the -* transmit FIFO will be sent. -* -* @return The number of bytes actually sent. -* -* @note -* -* The number of bytes is not asserted so that this function may be called with -* a value of zero to stop an operation that is already in progress. -* <br><br> -* -*****************************************************************************/ -unsigned int XUartPs_Send(XUartPs *InstancePtr, u8 *BufferPtr, - unsigned int NumBytes) -{ - unsigned int BytesSent; - - /* - * Asserts validate the input arguments - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(BufferPtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Disable the UART transmit interrupts to allow this call to stop a - * previous operation that may be interrupt driven. - */ - XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET, - (XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_TXFULL)); - - /* - * Setup the buffer parameters - */ - InstancePtr->SendBuffer.RequestedBytes = NumBytes; - InstancePtr->SendBuffer.RemainingBytes = NumBytes; - InstancePtr->SendBuffer.NextBytePtr = BufferPtr; - - /* - * Transmit interrupts will be enabled in XUartPs_SendBuffer(), after - * filling the TX FIFO. - */ - BytesSent = XUartPs_SendBuffer(InstancePtr); - - return BytesSent; -} - -/****************************************************************************/ -/** -* -* This function attempts to receive a specified number of bytes of data -* from the device and store it into the specified buffer. This function works -* for both polled or interrupt driven modes. It is non-blocking. -* -* In a polled mode, this function will only receive the data already in the -* RX FIFO. The application may need to call it repeatedly to receive the -* entire buffer. Polled mode is the default mode of operation for the device. -* -* In interrupt mode, this function will start the receiving, if not the entire -* buffer has been received, the interrupt handler will continue receiving data -* until the entire buffer has been received. A callback function, as specified -* by the application, will be called to indicate the completion of the -* receiving or error conditions. -* -* @param InstancePtr is a pointer to the XUartPs instance -* @param BufferPtr is pointer to buffer for data to be received into -* @param NumBytes is the number of bytes to be received. A value of zero -* will stop a previous receive operation that is in progress in -* interrupt mode. -* -* @return The number of bytes received. -* -* @note -* -* The number of bytes is not asserted so that this function may be called -* with a value of zero to stop an operation that is already in progress. -* -*****************************************************************************/ -unsigned int XUartPs_Recv(XUartPs *InstancePtr, - u8 *BufferPtr, unsigned int NumBytes) -{ - unsigned int ReceivedCount; - u32 ImrRegister; - - /* - * Assert validates the input arguments - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(BufferPtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Disable all the interrupts. - * This stops a previous operation that may be interrupt driven - */ - ImrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress, - XUARTPS_IMR_OFFSET); - XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET, - XUARTPS_IXR_MASK); - - /* - * Setup the buffer parameters - */ - InstancePtr->ReceiveBuffer.RequestedBytes = NumBytes; - InstancePtr->ReceiveBuffer.RemainingBytes = NumBytes; - InstancePtr->ReceiveBuffer.NextBytePtr = BufferPtr; - - /* - * Receive the data from the device - */ - ReceivedCount = XUartPs_ReceiveBuffer(InstancePtr); - - /* - * Restore the interrupt state - */ - XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET, - ImrRegister); - - return ReceivedCount; -} - -/****************************************************************************/ -/* -* -* This function sends a buffer that has been previously specified by setting -* up the instance variables of the instance. This function is an internal -* function for the XUartPs driver such that it may be called from a shell -* function that sets up the buffer or from an interrupt handler. -* -* This function sends the specified buffer in either polled or interrupt -* driven modes. This function is non-blocking. -* -* In a polled mode, this function only sends as much data as the TX FIFO -* can buffer. The application may need to call it repeatedly to send the -* entire buffer. -* -* In interrupt mode, this function starts the sending of the buffer, if not -* the entire buffer has been sent, then the interrupt handler continues the -* sending until the entire buffer has been sent. A callback function, as -* specified by the application, will be called to indicate the completion of -* sending. -* -* @param InstancePtr is a pointer to the XUartPs instance -* -* @return The number of bytes actually sent -* -* @note None. -* -*****************************************************************************/ -unsigned int XUartPs_SendBuffer(XUartPs *InstancePtr) -{ - unsigned int SentCount = 0; - u32 ImrRegister; - - /* - * If the TX FIFO is full, send nothing. - * Otherwise put bytes into the TX FIFO unil it is full, or all of the - * data has been put into the FIFO. - */ - while ((!XUartPs_IsTransmitFull(InstancePtr->Config.BaseAddress)) && - (InstancePtr->SendBuffer.RemainingBytes > SentCount)) { - - /* - * Fill the FIFO from the buffer - */ - XUartPs_WriteReg(InstancePtr->Config.BaseAddress, - XUARTPS_FIFO_OFFSET, - InstancePtr->SendBuffer. - NextBytePtr[SentCount]); - - /* - * Incriment the send count. - */ - SentCount++; - } - - /* - * Update the buffer to reflect the bytes that were sent from it - */ - InstancePtr->SendBuffer.NextBytePtr += SentCount; - InstancePtr->SendBuffer.RemainingBytes -= SentCount; - - /* - * If interrupts are enabled as indicated by the receive interrupt, then - * enable the TX FIFO empty interrupt, so further action can be taken - * for this sending. - */ - ImrRegister = - XUartPs_ReadReg(InstancePtr->Config.BaseAddress, - XUARTPS_IMR_OFFSET); - if ((ImrRegister & XUARTPS_IXR_RXFULL) || - (ImrRegister & XUARTPS_IXR_RXEMPTY) || - (ImrRegister & XUARTPS_IXR_RXOVR)) { - - XUartPs_WriteReg(InstancePtr->Config.BaseAddress, - XUARTPS_IER_OFFSET, - ImrRegister | XUARTPS_IXR_TXEMPTY); - } - - return SentCount; -} - -/****************************************************************************/ -/* -* -* This function receives a buffer that has been previously specified by setting -* up the instance variables of the instance. This function is an internal -* function, and it may be called from a shell function that sets up the buffer -* or from an interrupt handler. -* -* This function attempts to receive a specified number of bytes from the -* device and store it into the specified buffer. This function works for -* either polled or interrupt driven modes. It is non-blocking. -* -* In polled mode, this function only receives as much data as in the RX FIFO. -* The application may need to call it repeatedly to receive the entire buffer. -* Polled mode is the default mode for the driver. -* -* In interrupt mode, this function starts the receiving, if not the entire -* buffer has been received, the interrupt handler will continue until the -* entire buffer has been received. A callback function, as specified by the -* application, will be called to indicate the completion of the receiving or -* error conditions. -* -* @param InstancePtr is a pointer to the XUartPs instance -* -* @return The number of bytes received. -* -* @note None. -* -*****************************************************************************/ -unsigned int XUartPs_ReceiveBuffer(XUartPs *InstancePtr) -{ - u32 CsrRegister; - unsigned int ReceivedCount = 0; - - /* - * Read the Channel Status Register to determine if there is any data in - * the RX FIFO - */ - CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress, - XUARTPS_SR_OFFSET); - - /* - * Loop until there is no more data in RX FIFO or the specified - * number of bytes has been received - */ - while((ReceivedCount < InstancePtr->ReceiveBuffer.RemainingBytes)&& - (0 == (CsrRegister & XUARTPS_SR_RXEMPTY))){ - - InstancePtr->ReceiveBuffer.NextBytePtr[ReceivedCount] = - XUartPs_ReadReg(InstancePtr->Config. - BaseAddress, - XUARTPS_FIFO_OFFSET); - - ReceivedCount++; - - CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress, - XUARTPS_SR_OFFSET); - } - - /* - * Update the receive buffer to reflect the number of bytes just - * received - */ - InstancePtr->ReceiveBuffer.NextBytePtr += ReceivedCount; - InstancePtr->ReceiveBuffer.RemainingBytes -= ReceivedCount; - - return ReceivedCount; -} - -/*****************************************************************************/ -/** -* -* Sets the baud rate for the device. Checks the input value for -* validity and also verifies that the requested rate can be configured to -* within the maximum error range specified by XUARTPS_MAX_BAUD_ERROR_RATE. -* If the provided rate is not possible, the current setting is unchanged. -* -* @param InstancePtr is a pointer to the XUartPs instance -* @param BaudRate to be set -* -* @return -* - XST_SUCCESS if everything configured as expected -* - XST_UART_BAUD_ERROR if the requested rate is not available -* because there was too much error -* -* @note None. -* -*****************************************************************************/ -int XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate) -{ - u8 IterBAUDDIV; /* Iterator for available baud divisor values */ - u32 BRGR_Value; /* Calculated value for baud rate generator */ - u32 CalcBaudRate; /* Calculated baud rate */ - u32 BaudError; /* Diff between calculated and requested baud rate */ - u32 Best_BRGR = 0; /* Best value for baud rate generator */ - u8 Best_BAUDDIV = 0; /* Best value for baud divisor */ - u32 Best_Error = 0xFFFFFFFF; - u32 PercentError; - u32 ModeReg; - u32 InputClk; - - /* - * Asserts validate the input arguments - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(BaudRate <= XUARTPS_MAX_RATE); - Xil_AssertNonvoid(BaudRate >= XUARTPS_MIN_RATE); - - /* - * Make sure the baud rate is not impossilby large. - * Fastest possible baud rate is Input Clock / 2. - */ - if ((BaudRate * 2) > InstancePtr->Config.InputClockHz) { - return XST_UART_BAUD_ERROR; - } - /* - * Check whether the input clock is divided by 8 - */ - ModeReg = XUartPs_ReadReg( InstancePtr->Config.BaseAddress, - XUARTPS_MR_OFFSET); - - InputClk = InstancePtr->Config.InputClockHz; - if(ModeReg & XUARTPS_MR_CLKSEL) { - InputClk = InstancePtr->Config.InputClockHz / 8; - } - - /* - * Determine the Baud divider. It can be 4to 254. - * Loop through all possible combinations - */ - for (IterBAUDDIV = 4; IterBAUDDIV < 255; IterBAUDDIV++) { - - /* - * Calculate the value for BRGR register - */ - BRGR_Value = InputClk / (BaudRate * (IterBAUDDIV + 1)); - - /* - * Calculate the baud rate from the BRGR value - */ - CalcBaudRate = InputClk/ (BRGR_Value * (IterBAUDDIV + 1)); - - /* - * Avoid unsigned integer underflow - */ - if (BaudRate > CalcBaudRate) { - BaudError = BaudRate - CalcBaudRate; - } - else { - BaudError = CalcBaudRate - BaudRate; - } - - /* - * Find the calculated baud rate closest to requested baud rate. - */ - if (Best_Error > BaudError) { - - Best_BRGR = BRGR_Value; - Best_BAUDDIV = IterBAUDDIV; - Best_Error = BaudError; - } - } - - /* - * Make sure the best error is not too large. - */ - PercentError = (Best_Error * 100) / BaudRate; - if (XUARTPS_MAX_BAUD_ERROR_RATE < PercentError) { - return XST_UART_BAUD_ERROR; - } - - /* - * Disable TX and RX to avoid glitches when setting the baud rate. - */ - XUartPs_DisableUart(InstancePtr); - - XUartPs_WriteReg(InstancePtr->Config.BaseAddress, - XUARTPS_BAUDGEN_OFFSET, Best_BRGR); - XUartPs_WriteReg(InstancePtr->Config.BaseAddress, - XUARTPS_BAUDDIV_OFFSET, Best_BAUDDIV); - - /* - * Enable device - */ - XUartPs_EnableUart(InstancePtr); - - InstancePtr->BaudRate = BaudRate; - - return XST_SUCCESS; - -} - -/****************************************************************************/ -/** -* -* This function is a stub handler that is the default handler such that if the -* application has not set the handler when interrupts are enabled, this -* function will be called. -* -* @param CallBackRef is unused by this function. -* @param Event is unused by this function. -* @param ByteCount is unused by this function. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -static void XUartPs_StubHandler(void *CallBackRef, u32 Event, - unsigned int ByteCount) -{ - (void) CallBackRef; - (void) Event; - (void) ByteCount; - /* - * Assert occurs always since this is a stub and should never be called - */ - Xil_AssertVoidAlways(); -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/xuartps.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/xuartps.h deleted file mode 100644 index c00060fe544f81f627ab20b042ce9bb44939c3dd..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/xuartps.h +++ /dev/null @@ -1,511 +0,0 @@ -/***************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -*****************************************************************************/ -/****************************************************************************/ -/** -* -* @file xuartps.h -* -* This driver supports the following features: -* -* - Dynamic data format (baud rate, data bits, stop bits, parity) -* - Polled mode -* - Interrupt driven mode -* - Transmit and receive FIFOs (32 byte FIFO depth) -* - Access to the external modem control lines -* -* <b>Initialization & Configuration</b> -* -* The XUartPs_Config structure is used by the driver to configure itself. -* Fields inside this structure are properties of XUartPs based on its hardware -* build. -* -* To support multiple runtime loading and initialization strategies employed -* by various operating systems, the driver instance can be initialized in the -* following way: -* -* - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a -* configuration structure provided by the caller. If running in a system -* with address translation, the parameter EffectiveAddr should be the -* virtual address. -* -* <b>Baud Rate</b> -* -* The UART has an internal baud rate generator, which furnishes the baud rate -* clock for both the receiver and the transmitter. Ther input clock frequency -* can be either the master clock or the master clock divided by 8, configured -* through the mode register. -* -* Accompanied with the baud rate divider register, the baud rate is determined -* by: -* <pre> -* baud_rate = input_clock / (bgen * (bdiv + 1) -* </pre> -* where bgen is the value of the baud rate generator, and bdiv is the value of -* baud rate divider. -* -* <b>Interrupts</b> -* -* The FIFOs are not flushed when the driver is initialized, but a function is -* provided to allow the user to reset the FIFOs if desired. -* -* The driver defaults to no interrupts at initialization such that interrupts -* must be enabled if desired. An interrupt is generated for one of the -* following conditions. -* -* - A change in the modem signals -* - Data in the receive FIFO for a configuable time without receiver activity -* - A parity error -* - A framing error -* - An overrun error -* - Transmit FIFO is full -* - Transmit FIFO is empty -* - Receive FIFO is full -* - Receive FIFO is empty -* - Data in the receive FIFO equal to the receive threshold -* -* The application can control which interrupts are enabled using the -* XUartPs_SetInterruptMask() function. -* -* In order to use interrupts, it is necessary for the user to connect the -* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt -* system of the application. A separate handler should be provided by the -* application to communicate with the interrupt system, and conduct -* application specific interrupt handling. An application registers its own -* handler through the XUartPs_SetHandler() function. -* -* <b>Data Transfer</b> -* -* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the -* driver to allow data to be sent and received. They can be used in either -* polled or interrupt mode. -* -* @note -* -* The default configuration for the UART after initialization is: -* -* - 9,600 bps or XPAR_DFT_BAUDRATE if defined -* - 8 data bits -* - 1 stop bit -* - no parity -* - FIFO's are enabled with a receive threshold of 8 bytes -* - The RX timeout is enabled with a timeout of 1 (4 char times) -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------ -------- ---------------------------------------------- -* 1.00a drg/jz 01/12/10 First Release -* 1.00a sdm 09/27/11 Fixed compiler warnings and also a bug -* in XUartPs_SetFlowDelay where the value was not -* being written to the register. -* 1.01a sdm 12/20/11 Removed the InputClockHz parameter from the XUartPs -* instance structure and the driver is updated to use -* InputClockHz parameter from the XUartPs_Config config -* structure. -* Added a parameter to XUartPs_Config structure which -* specifies whether the user has selected Modem pins -* to be connected to MIO or FMIO. -* Added the tcl file to generate the xparameters.h -* 1.02a sg 05/16/12 Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix. -* 1.03a sg 07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS -* with the correct values for CR 666724 -* Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL -* and XUARTPS_IXR_TTRIG. -* Modified the name of these defines -* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD -* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI -* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR -* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS -* 1.05a hk 08/22/13 Added API for uart reset and related -* constant definitions. -* -* </pre> -* -*****************************************************************************/ - -#ifndef XUARTPS_H /* prevent circular inclusions */ -#define XUARTPS_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files ********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xstatus.h" -#include "xuartps_hw.h" - -/************************** Constant Definitions ****************************/ - -/* - * The following constants indicate the max and min baud rates and these - * numbers are based only on the testing that has been done. The hardware - * is capable of other baud rates. - */ -#define XUARTPS_MAX_RATE 115200 -#define XUARTPS_MIN_RATE 110 - -#define XUARTPS_DFT_BAUDRATE 115200 /* Default baud rate */ - -/** @name Configuration options - * @{ - */ -/** - * These constants specify the options that may be set or retrieved - * with the driver, each is a unique bit mask such that multiple options - * may be specified. These constants indicate the available options - * in active state. - * - */ - -#define XUARTPS_OPTION_SET_BREAK 0x0080 /**< Starts break transmission */ -#define XUARTPS_OPTION_STOP_BREAK 0x0040 /**< Stops break transmission */ -#define XUARTPS_OPTION_RESET_TMOUT 0x0020 /**< Reset the receive timeout */ -#define XUARTPS_OPTION_RESET_TX 0x0010 /**< Reset the transmitter */ -#define XUARTPS_OPTION_RESET_RX 0x0008 /**< Reset the receiver */ -#define XUARTPS_OPTION_ASSERT_RTS 0x0004 /**< Assert the RTS bit */ -#define XUARTPS_OPTION_ASSERT_DTR 0x0002 /**< Assert the DTR bit */ -#define XUARTPS_OPTION_SET_FCM 0x0001 /**< Turn on flow control mode */ -/*@}*/ - - -/** @name Channel Operational Mode - * - * The UART can operate in one of four modes: Normal, Local Loopback, Remote - * Loopback, or automatic echo. - * - * @{ - */ - -#define XUARTPS_OPER_MODE_NORMAL 0x00 /**< Normal Mode */ -#define XUARTPS_OPER_MODE_AUTO_ECHO 0x01 /**< Auto Echo Mode */ -#define XUARTPS_OPER_MODE_LOCAL_LOOP 0x02 /**< Local Loopback Mode */ -#define XUARTPS_OPER_MODE_REMOTE_LOOP 0x03 /**< Remote Loopback Mode */ - -/* @} */ - -/** @name Data format values - * - * These constants specify the data format that the driver supports. - * The data format includes the number of data bits, the number of stop - * bits and parity. - * - * @{ - */ -#define XUARTPS_FORMAT_8_BITS 0 /**< 8 data bits */ -#define XUARTPS_FORMAT_7_BITS 2 /**< 7 data bits */ -#define XUARTPS_FORMAT_6_BITS 3 /**< 6 data bits */ - -#define XUARTPS_FORMAT_NO_PARITY 4 /**< No parity */ -#define XUARTPS_FORMAT_MARK_PARITY 3 /**< Mark parity */ -#define XUARTPS_FORMAT_SPACE_PARITY 2 /**< parity */ -#define XUARTPS_FORMAT_ODD_PARITY 1 /**< Odd parity */ -#define XUARTPS_FORMAT_EVEN_PARITY 0 /**< Even parity */ - -#define XUARTPS_FORMAT_2_STOP_BIT 2 /**< 2 stop bits */ -#define XUARTPS_FORMAT_1_5_STOP_BIT 1 /**< 1.5 stop bits */ -#define XUARTPS_FORMAT_1_STOP_BIT 0 /**< 1 stop bit */ -/*@}*/ - -/** @name Callback events - * - * These constants specify the handler events that an application can handle - * using its specific handler function. Note that these constants are not bit - * mask, so only one event can be passed to an application at a time. - * - * @{ - */ -#define XUARTPS_EVENT_RECV_DATA 1 /**< Data receiving done */ -#define XUARTPS_EVENT_RECV_TOUT 2 /**< A receive timeout occurred */ -#define XUARTPS_EVENT_SENT_DATA 3 /**< Data transmission done */ -#define XUARTPS_EVENT_RECV_ERROR 4 /**< A receive error detected */ -#define XUARTPS_EVENT_MODEM 5 /**< Modem status changed */ -/*@}*/ - - -/**************************** Type Definitions ******************************/ - -/** - * This typedef contains configuration information for the device. - */ -typedef struct { - u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddress; /**< Base address of device (IPIF) */ - u32 InputClockHz;/**< Input clock frequency */ - int ModemPinsConnected; /** Specifies whether modem pins are connected - * to MIO or FMIO */ -} XUartPs_Config; - -/* - * Keep track of state information about a data buffer in the interrupt mode. - */ -typedef struct { - u8 *NextBytePtr; - unsigned int RequestedBytes; - unsigned int RemainingBytes; -} XUartPsBuffer; - -/** - * Keep track of data format setting of a device. - */ -typedef struct { - u32 BaudRate; /**< In bps, ie 1200 */ - u32 DataBits; /**< Number of data bits */ - u32 Parity; /**< Parity */ - u8 StopBits; /**< Number of stop bits */ -} XUartPsFormat; - -/******************************************************************************/ -/** - * This data type defines a handler that an application defines to communicate - * with interrupt system to retrieve state information about an application. - * - * @param CallBackRef is a callback reference passed in by the upper layer - * when setting the handler, and is passed back to the upper layer - * when the handler is called. It is used to find the device driver - * instance. - * @param Event contains one of the event constants indicating events that - * have occurred. - * @param EventData contains the number of bytes sent or received at the - * time of the call for send and receive events and contains the - * modem status for modem events. - * - ******************************************************************************/ -typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event, - unsigned int EventData); - -/** - * The XUartPs driver instance data structure. A pointer to an instance data - * structure is passed around by functions to refer to a specific driver - * instance. - */ -typedef struct { - XUartPs_Config Config; /* Configuration data structure */ - u32 InputClockHz; /* Input clock frequency */ - u32 IsReady; /* Device is initialized and ready */ - u32 BaudRate; /* Current baud rate */ - - XUartPsBuffer SendBuffer; - XUartPsBuffer ReceiveBuffer; - - XUartPs_Handler Handler; - void *CallBackRef; /* Callback reference for event handler */ -} XUartPs; - - -/***************** Macros (Inline Functions) Definitions ********************/ - -/****************************************************************************/ -/** -* Get the UART Channel Status Register. -* -* @param InstancePtr is a pointer to the XUartPs instance. -* -* @return The value read from the register. -* -* @note C-Style signature: -* u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr) -* -******************************************************************************/ -#define XUartPs_GetChannelStatus(InstancePtr) \ - Xil_In32(((InstancePtr)->Config.BaseAddress) + XUARTPS_SR_OFFSET) - -/****************************************************************************/ -/** -* Get the UART Mode Control Register. -* -* @param InstancePtr is a pointer to the XUartPs instance. -* -* @return The value read from the register. -* -* @note C-Style signature: -* u32 XUartPs_GetControl(XUartPs *InstancePtr) -* -******************************************************************************/ -#define XUartPs_GetModeControl(InstancePtr) \ - Xil_In32(((InstancePtr)->Config.BaseAddress) + XUARTPS_CR_OFFSET) - -/****************************************************************************/ -/** -* Set the UART Mode Control Register. -* -* @param InstancePtr is a pointer to the XUartPs instance. -* @param RegisterValue is the value to be written to the register. -* -* @return None. -* -* @note C-Style signature: -* void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue) -* -******************************************************************************/ -#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \ - Xil_Out32(((InstancePtr)->Config.BaseAddress) + XUARTPS_CR_OFFSET, \ - (RegisterValue)) - -/****************************************************************************/ -/** -* Enable the transmitter and receiver of the UART. -* -* @param InstancePtr is a pointer to the XUartPs instance. -* -* @return None. -* -* @note C-Style signature: -* void XUartPs_EnableUart(XUartPs *InstancePtr) -* -******************************************************************************/ -#define XUartPs_EnableUart(InstancePtr) \ - Xil_Out32(((InstancePtr)->Config.BaseAddress + XUARTPS_CR_OFFSET), \ - ((Xil_In32((InstancePtr)->Config.BaseAddress + XUARTPS_CR_OFFSET) & \ - ~XUARTPS_CR_EN_DIS_MASK) | (XUARTPS_CR_RX_EN | XUARTPS_CR_TX_EN))) - -/****************************************************************************/ -/** -* Disable the transmitter and receiver of the UART. -* -* @param InstancePtr is a pointer to the XUartPs instance. -* -* @return None. -* -* @note C-Style signature: -* void XUartPs_DisableUart(XUartPs *InstancePtr) -* -******************************************************************************/ -#define XUartPs_DisableUart(InstancePtr) \ - Xil_Out32(((InstancePtr)->Config.BaseAddress + XUARTPS_CR_OFFSET), \ - (((Xil_In32((InstancePtr)->Config.BaseAddress + XUARTPS_CR_OFFSET)) & \ - ~XUARTPS_CR_EN_DIS_MASK) | (XUARTPS_CR_RX_DIS | XUARTPS_CR_TX_DIS))) - -/****************************************************************************/ -/** -* Determine if the transmitter FIFO is empty. -* -* @param InstancePtr is a pointer to the XUartPs instance. -* -* @return -* - TRUE if a byte can be sent -* - FALSE if the Transmitter Fifo is not empty -* -* @note C-Style signature: -* u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr) -* -******************************************************************************/ -#define XUartPs_IsTransmitEmpty(InstancePtr) \ - ((Xil_In32(((InstancePtr)->Config.BaseAddress) + XUARTPS_SR_OFFSET) & \ - XUARTPS_SR_TXEMPTY) == XUARTPS_SR_TXEMPTY) - - -/************************** Function Prototypes *****************************/ - -/* - * Static lookup function implemented in xuartps_sinit.c - */ -XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId); - -/* - * Interface functions implemented in xuartps.c - */ -int XUartPs_CfgInitialize(XUartPs *InstancePtr, - XUartPs_Config * Config, u32 EffectiveAddr); - -unsigned int XUartPs_Send(XUartPs *InstancePtr, u8 *BufferPtr, - unsigned int NumBytes); - -unsigned int XUartPs_Recv(XUartPs *InstancePtr, u8 *BufferPtr, - unsigned int NumBytes); - -int XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate); - -/* - * Options functions in xuartps_options.c - */ -void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options); - -u16 XUartPs_GetOptions(XUartPs *InstancePtr); - -void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel); - -u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr); - -u16 XUartPs_GetModemStatus(XUartPs *InstancePtr); - -u32 XUartPs_IsSending(XUartPs *InstancePtr); - -u8 XUartPs_GetOperMode(XUartPs *InstancePtr); - -void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode); - -u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr); - -void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue); - -u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr); - -void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout); - -int XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * Format); -void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * Format); - -/* - * interrupt functions in xuartps_intr.c - */ -u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr); - -void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask); - -void XUartPs_InterruptHandler(XUartPs *InstancePtr); - -void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr, - void *CallBackRef); - -/* - * self-test functions in xuartps_selftest.c - */ -int XUartPs_SelfTest(XUartPs *InstancePtr); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/xuartps_g.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/xuartps_g.c deleted file mode 100644 index 2d86c04aa1cfb2ade231b4bd55cf61f640ccc5f8..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/xuartps_g.c +++ /dev/null @@ -1,38 +0,0 @@ - -/******************************************************************* -* -* CAUTION: This file is automatically generated by libgen. -* Version: Xilinx EDK 14.7 EDK_P.20131013 -* DO NOT EDIT. -* -* Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. - -* -* Description: Driver configuration -* -*******************************************************************/ - -#include "xparameters.h" -#include "xuartps.h" - -/* -* The configuration table for devices -*/ - -XUartPs_Config XUartPs_ConfigTable[] = -{ - { - XPAR_PS7_UART_0_DEVICE_ID, - XPAR_PS7_UART_0_BASEADDR, - XPAR_PS7_UART_0_UART_CLK_FREQ_HZ, - XPAR_PS7_UART_0_HAS_MODEM - }, - { - XPAR_PS7_UART_1_DEVICE_ID, - XPAR_PS7_UART_1_BASEADDR, - XPAR_PS7_UART_1_UART_CLK_FREQ_HZ, - XPAR_PS7_UART_1_HAS_MODEM - } -}; - - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/xuartps_hw.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/xuartps_hw.c deleted file mode 100644 index b7fe10ab845542d3558d6ac7357c40496222c6d4..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/xuartps_hw.c +++ /dev/null @@ -1,201 +0,0 @@ -/***************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -*****************************************************************************/ -/****************************************************************************/ -/** -* -* @file xuartps_hw.c -* -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------ -------- ---------------------------------------------- -* 1.00 drg/jz 01/12/10 First Release -* 1.05a hk 08/22/13 Added reset function -* </pre> -* -*****************************************************************************/ - -/***************************** Include Files ********************************/ -#include "xuartps_hw.h" - -/************************** Constant Definitions ****************************/ - - -/***************** Macros (Inline Functions) Definitions ********************/ - - -/************************** Function Prototypes ******************************/ - - -/************************** Variable Definitions *****************************/ - -/****************************************************************************/ -/** -* -* This function sends one byte using the device. This function operates in -* polled mode and blocks until the data has been put into the TX FIFO register. -* -* @param BaseAddress contains the base address of the device. -* @param Data contains the byte to be sent. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XUartPs_SendByte(u32 BaseAddress, u8 Data) -{ - /* - * Wait until there is space in TX FIFO - */ - while (XUartPs_IsTransmitFull(BaseAddress)); - - /* - * Write the byte into the TX FIFO - */ - XUartPs_WriteReg(BaseAddress, XUARTPS_FIFO_OFFSET, Data); -} - -/****************************************************************************/ -/** -* -* This function receives a byte from the device. It operates in polled mode -* and blocks until a byte has received. -* -* @param BaseAddress contains the base address of the device. -* -* @return The data byte received. -* -* @note None. -* -*****************************************************************************/ -u8 XUartPs_RecvByte(u32 BaseAddress) -{ - /* - * Wait until there is data - */ - while (!XUartPs_IsReceiveData(BaseAddress)); - - /* - * Return the byte received - */ - return (XUartPs_ReadReg(BaseAddress, XUARTPS_FIFO_OFFSET)); -} - -/****************************************************************************/ -/** -* -* This function resets UART -* -* @param BaseAddress contains the base address of the device. -* -* @return None -* -* @note None. -* -*****************************************************************************/ -void XUartPs_ResetHw(u32 BaseAddress) -{ - - /* - * Disable interrupts - */ - XUartPs_WriteReg(BaseAddress, XUARTPS_IDR_OFFSET, XUARTPS_IXR_MASK); - - /* - * Disable receive and transmit - */ - XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET, - XUARTPS_CR_RX_DIS | XUARTPS_CR_TX_DIS); - - /* - * Software reset of receive and transmit - * This clears the FIFO. - */ - XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET, - XUARTPS_CR_TXRST | XUARTPS_CR_RXRST); - - /* - * Clear status flags - SW reset wont clear sticky flags. - */ - XUartPs_WriteReg(BaseAddress, XUARTPS_ISR_OFFSET, XUARTPS_IXR_MASK); - - /* - * Mode register reset value : All zeroes - * Normal mode, even parity, 1 stop bit - */ - XUartPs_WriteReg(BaseAddress, XUARTPS_MR_OFFSET, - XUARTPS_MR_CHMODE_NORM); - - /* - * Rx and TX trigger register reset values - */ - XUartPs_WriteReg(BaseAddress, XUARTPS_RXWM_OFFSET, - XUARTPS_RXWM_RESET_VAL); - XUartPs_WriteReg(BaseAddress, XUARTPS_TXWM_OFFSET, - XUARTPS_TXWM_RESET_VAL); - - /* - * Rx timeout disabled by default - */ - XUartPs_WriteReg(BaseAddress, XUARTPS_RXTOUT_OFFSET, - XUARTPS_RXTOUT_DISABLE); - - /* - * Baud rate generator and dividor reset values - */ - XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDGEN_OFFSET, - XUARTPS_BAUDGEN_RESET_VAL); - XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDDIV_OFFSET, - XUARTPS_BAUDDIV_RESET_VAL); - - /* - * Control register reset value - - * RX and TX are disable by default - */ - XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET, - XUARTPS_CR_RX_DIS | XUARTPS_CR_TX_DIS | - XUARTPS_CR_STOPBRK); - -} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/xuartps_hw.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/xuartps_hw.h deleted file mode 100644 index 768e38027c16f60d1ca2b9804e4f1130b24603ae..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/xuartps_hw.h +++ /dev/null @@ -1,432 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xuartps_hw.h -* -* This header file contains the hardware interface of an XUartPs device. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------ -------- ---------------------------------------------- -* 1.00 drg/jz 01/12/10 First Release -* 1.03a sg 09/04/12 Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL -* and XUARTPS_IXR_TTRIG. -* Modified the names of these defines -* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD -* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI -* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR -* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS -* 1.05a hk 08/22/13 Added prototype for uart reset and related -* constant definitions. -* -* </pre> -* -******************************************************************************/ -#ifndef XUARTPS_HW_H /* prevent circular inclusions */ -#define XUARTPS_HW_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xil_io.h" - -/************************** Constant Definitions *****************************/ - -/** @name Register Map - * - * Register offsets for the UART. - * @{ - */ -#define XUARTPS_CR_OFFSET 0x00 /**< Control Register [8:0] */ -#define XUARTPS_MR_OFFSET 0x04 /**< Mode Register [9:0] */ -#define XUARTPS_IER_OFFSET 0x08 /**< Interrupt Enable [12:0] */ -#define XUARTPS_IDR_OFFSET 0x0C /**< Interrupt Disable [12:0] */ -#define XUARTPS_IMR_OFFSET 0x10 /**< Interrupt Mask [12:0] */ -#define XUARTPS_ISR_OFFSET 0x14 /**< Interrupt Status [12:0]*/ -#define XUARTPS_BAUDGEN_OFFSET 0x18 /**< Baud Rate Generator [15:0] */ -#define XUARTPS_RXTOUT_OFFSET 0x1C /**< RX Timeout [7:0] */ -#define XUARTPS_RXWM_OFFSET 0x20 /**< RX FIFO Trigger Level [5:0] */ -#define XUARTPS_MODEMCR_OFFSET 0x24 /**< Modem Control [5:0] */ -#define XUARTPS_MODEMSR_OFFSET 0x28 /**< Modem Status [8:0] */ -#define XUARTPS_SR_OFFSET 0x2C /**< Channel Status [14:0] */ -#define XUARTPS_FIFO_OFFSET 0x30 /**< FIFO [7:0] */ -#define XUARTPS_BAUDDIV_OFFSET 0x34 /**< Baud Rate Divider [7:0] */ -#define XUARTPS_FLOWDEL_OFFSET 0x38 /**< Flow Delay [5:0] */ -#define XUARTPS_TXWM_OFFSET 0x44 /**< TX FIFO Trigger Level [5:0] */ -/* @} */ - -/** @name Control Register - * - * The Control register (CR) controls the major functions of the device. - * - * Control Register Bit Definition - */ - -#define XUARTPS_CR_STOPBRK 0x00000100 /**< Stop transmission of break */ -#define XUARTPS_CR_STARTBRK 0x00000080 /**< Set break */ -#define XUARTPS_CR_TORST 0x00000040 /**< RX timeout counter restart */ -#define XUARTPS_CR_TX_DIS 0x00000020 /**< TX disabled. */ -#define XUARTPS_CR_TX_EN 0x00000010 /**< TX enabled */ -#define XUARTPS_CR_RX_DIS 0x00000008 /**< RX disabled. */ -#define XUARTPS_CR_RX_EN 0x00000004 /**< RX enabled */ -#define XUARTPS_CR_EN_DIS_MASK 0x0000003C /**< Enable/disable Mask */ -#define XUARTPS_CR_TXRST 0x00000002 /**< TX logic reset */ -#define XUARTPS_CR_RXRST 0x00000001 /**< RX logic reset */ -/* @}*/ - - -/** @name Mode Register - * - * The mode register (MR) defines the mode of transfer as well as the data - * format. If this register is modified during transmission or reception, - * data validity cannot be guaranteed. - * - * Mode Register Bit Definition - * @{ - */ -#define XUARTPS_MR_CCLK 0x00000400 /**< Input clock selection */ -#define XUARTPS_MR_CHMODE_R_LOOP 0x00000300 /**< Remote loopback mode */ -#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200 /**< Local loopback mode */ -#define XUARTPS_MR_CHMODE_ECHO 0x00000100 /**< Auto echo mode */ -#define XUARTPS_MR_CHMODE_NORM 0x00000000 /**< Normal mode */ -#define XUARTPS_MR_CHMODE_SHIFT 8 /**< Mode shift */ -#define XUARTPS_MR_CHMODE_MASK 0x00000300 /**< Mode mask */ -#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080 /**< 2 stop bits */ -#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040 /**< 1.5 stop bits */ -#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000 /**< 1 stop bit */ -#define XUARTPS_MR_STOPMODE_SHIFT 6 /**< Stop bits shift */ -#define XUARTPS_MR_STOPMODE_MASK 0x000000A0 /**< Stop bits mask */ -#define XUARTPS_MR_PARITY_NONE 0x00000020 /**< No parity mode */ -#define XUARTPS_MR_PARITY_MARK 0x00000018 /**< Mark parity mode */ -#define XUARTPS_MR_PARITY_SPACE 0x00000010 /**< Space parity mode */ -#define XUARTPS_MR_PARITY_ODD 0x00000008 /**< Odd parity mode */ -#define XUARTPS_MR_PARITY_EVEN 0x00000000 /**< Even parity mode */ -#define XUARTPS_MR_PARITY_SHIFT 3 /**< Parity setting shift */ -#define XUARTPS_MR_PARITY_MASK 0x00000038 /**< Parity mask */ -#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006 /**< 6 bits data */ -#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004 /**< 7 bits data */ -#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000 /**< 8 bits data */ -#define XUARTPS_MR_CHARLEN_SHIFT 1 /**< Data Length shift */ -#define XUARTPS_MR_CHARLEN_MASK 0x00000006 /**< Data length mask */ -#define XUARTPS_MR_CLKSEL 0x00000001 /**< Input clock selection */ -/* @} */ - - -/** @name Interrupt Registers - * - * Interrupt control logic uses the interrupt enable register (IER) and the - * interrupt disable register (IDR) to set the value of the bits in the - * interrupt mask register (IMR). The IMR determines whether to pass an - * interrupt to the interrupt status register (ISR). - * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an - * interrupt. IMR and ISR are read only, and IER and IDR are write only. - * Reading either IER or IDR returns 0x00. - * - * All four registers have the same bit definitions. - * - * @{ - */ -#define XUARTPS_IXR_TOVR 0x00001000 /**< Tx FIFO Overflow interrupt */ -#define XUARTPS_IXR_TNFUL 0x00000800 /**< Tx FIFO Nearly Full interrupt */ -#define XUARTPS_IXR_TTRIG 0x00000400 /**< Tx Trig interrupt */ -#define XUARTPS_IXR_DMS 0x00000200 /**< Modem status change interrupt */ -#define XUARTPS_IXR_TOUT 0x00000100 /**< Timeout error interrupt */ -#define XUARTPS_IXR_PARITY 0x00000080 /**< Parity error interrupt */ -#define XUARTPS_IXR_FRAMING 0x00000040 /**< Framing error interrupt */ -#define XUARTPS_IXR_OVER 0x00000020 /**< Overrun error interrupt */ -#define XUARTPS_IXR_TXFULL 0x00000010 /**< TX FIFO full interrupt. */ -#define XUARTPS_IXR_TXEMPTY 0x00000008 /**< TX FIFO empty interrupt. */ -#define XUARTPS_IXR_RXFULL 0x00000004 /**< RX FIFO full interrupt. */ -#define XUARTPS_IXR_RXEMPTY 0x00000002 /**< RX FIFO empty interrupt. */ -#define XUARTPS_IXR_RXOVR 0x00000001 /**< RX FIFO trigger interrupt. */ -#define XUARTPS_IXR_MASK 0x00001FFF /**< Valid bit mask */ -/* @} */ - - -/** @name Baud Rate Generator Register - * - * The baud rate generator control register (BRGR) is a 16 bit register that - * controls the receiver bit sample clock and baud rate. - * Valid values are 1 - 65535. - * - * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit - * in the MR register. - * @{ - */ -#define XUARTPS_BAUDGEN_DISABLE 0x00000000 /**< Disable clock */ -#define XUARTPS_BAUDGEN_MASK 0x0000FFFF /**< Valid bits mask */ -#define XUARTPS_BAUDGEN_RESET_VAL 0x0000028B /**< Reset value */ - -/** @name Baud Divisor Rate register - * - * The baud rate divider register (BDIV) controls how much the bit sample - * rate is divided by. It sets the baud rate. - * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored. - * - * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by - * the MR_CCLK bit in the MR register. - * @{ - */ -#define XUARTPS_BAUDDIV_MASK 0x000000FF /**< 8 bit baud divider mask */ -#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000F /**< Reset value */ -/* @} */ - - -/** @name Receiver Timeout Register - * - * Use the receiver timeout register (RTR) to detect an idle condition on - * the receiver data line. - * - * @{ - */ -#define XUARTPS_RXTOUT_DISABLE 0x00000000 /**< Disable time out */ -#define XUARTPS_RXTOUT_MASK 0x000000FF /**< Valid bits mask */ - -/** @name Receiver FIFO Trigger Level Register - * - * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at - * which the RX FIFO triggers an interrupt event. - * @{ - */ - -#define XUARTPS_RXWM_DISABLE 0x00000000 /**< Disable RX trigger interrupt */ -#define XUARTPS_RXWM_MASK 0x0000003F /**< Valid bits mask */ -#define XUARTPS_RXWM_RESET_VAL 0x00000020 /**< Reset value */ -/* @} */ - -/** @name Transmit FIFO Trigger Level Register - * - * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at - * which the TX FIFO triggers an interrupt event. - * @{ - */ - -#define XUARTPS_TXWM_MASK 0x0000003F /**< Valid bits mask */ -#define XUARTPS_TXWM_RESET_VAL 0x00000020 /**< Reset value */ -/* @} */ - -/** @name Modem Control Register - * - * This register (MODEMCR) controls the interface with the modem or data set, - * or a peripheral device emulating a modem. - * - * @{ - */ -#define XUARTPS_MODEMCR_FCM 0x00000010 /**< Flow control mode */ -#define XUARTPS_MODEMCR_RTS 0x00000002 /**< Request to send */ -#define XUARTPS_MODEMCR_DTR 0x00000001 /**< Data terminal ready */ -/* @} */ - -/** @name Modem Status Register - * - * This register (MODEMSR) indicates the current state of the control lines - * from a modem, or another peripheral device, to the CPU. In addition, four - * bits of the modem status register provide change information. These bits - * are set to a logic 1 whenever a control input from the modem changes state. - * - * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem - * status interrupt is generated and this is reflected in the modem status - * register. - * - * @{ - */ -#define XUARTPS_MODEMSR_FCMS 0x00000100 /**< Flow control mode (FCMS) */ -#define XUARTPS_MODEMSR_DCD 0x00000080 /**< Complement of DCD input */ -#define XUARTPS_MODEMSR_RI 0x00000040 /**< Complement of RI input */ -#define XUARTPS_MODEMSR_DSR 0x00000020 /**< Complement of DSR input */ -#define XUARTPS_MODEMSR_CTS 0x00000010 /**< Complement of CTS input */ -#define XUARTPS_MODEMSR_DDCD 0x00000008 /**< Delta DCD indicator */ -#define XUARTPS_MODEMSR_TERI 0x00000004 /**< Trailing Edge Ring Indicator */ -#define XUARTPS_MODEMSR_DDSR 0x00000002 /**< Change of DSR */ -#define XUARTPS_MODEMSR_DCTS 0x00000001 /**< Change of CTS */ -/* @} */ - -/** @name Channel Status Register - * - * The channel status register (CSR) is provided to enable the control logic - * to monitor the status of bits in the channel interrupt status register, - * even if these are masked out by the interrupt mask register. - * - * @{ - */ -#define XUARTPS_SR_TNFUL 0x00004000 /**< TX FIFO Nearly Full Status */ -#define XUARTPS_SR_TTRIG 0x00002000 /**< TX FIFO Trigger Status */ -#define XUARTPS_SR_FLOWDEL 0x00001000 /**< RX FIFO fill over flow delay */ -#define XUARTPS_SR_TACTIVE 0x00000800 /**< TX active */ -#define XUARTPS_SR_RACTIVE 0x00000400 /**< RX active */ -#define XUARTPS_SR_DMS 0x00000200 /**< Delta modem status change */ -#define XUARTPS_SR_TOUT 0x00000100 /**< RX timeout */ -#define XUARTPS_SR_PARITY 0x00000080 /**< RX parity error */ -#define XUARTPS_SR_FRAME 0x00000040 /**< RX frame error */ -#define XUARTPS_SR_OVER 0x00000020 /**< RX overflow error */ -#define XUARTPS_SR_TXFULL 0x00000010 /**< TX FIFO full */ -#define XUARTPS_SR_TXEMPTY 0x00000008 /**< TX FIFO empty */ -#define XUARTPS_SR_RXFULL 0x00000004 /**< RX FIFO full */ -#define XUARTPS_SR_RXEMPTY 0x00000002 /**< RX FIFO empty */ -#define XUARTPS_SR_RXOVR 0x00000001 /**< RX FIFO fill over trigger */ -/* @} */ - -/** @name Flow Delay Register - * - * Operation of the flow delay register (FLOWDEL) is very similar to the - * receive FIFO trigger register. An internal trigger signal activates when the - * FIFO is filled to the level set by this register. This trigger will not - * cause an interrupt, although it can be read through the channel status - * register. In hardware flow control mode, RTS is deactivated when the trigger - * becomes active. RTS only resets when the FIFO level is four less than the - * level of the flow delay trigger and the flow delay trigger is not activated. - * A value less than 4 disables the flow delay. - * @{ - */ -#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */ -/* @} */ - - - -/* - * Defines for backwards compatabilty, will be removed - * in the next version of the driver - */ -#define XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD -#define XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI -#define XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR -#define XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS - - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - -/****************************************************************************/ -/** -* Read a UART register. -* -* @param BaseAddress contains the base address of the device. -* @param RegOffset contains the offset from the base address of the -* device. -* -* @return The value read from the register. -* -* @note C-Style signature: -* u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset) -* -******************************************************************************/ -#define XUartPs_ReadReg(BaseAddress, RegOffset) \ - Xil_In32((BaseAddress) + (RegOffset)) - -/***************************************************************************/ -/** -* Write a UART register. -* -* @param BaseAddress contains the base address of the device. -* @param RegOffset contains the offset from the base address of the -* device. -* @param RegisterValue is the value to be written to the register. -* -* @return None. -* -* @note C-Style signature: -* void XUartPs_WriteReg(u32 BaseAddress, int RegOffset, -* u16 RegisterValue) -* -******************************************************************************/ -#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ - Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue)) - -/****************************************************************************/ -/** -* Determine if there is receive data in the receiver and/or FIFO. -* -* @param BaseAddress contains the base address of the device. -* -* @return TRUE if there is receive data, FALSE otherwise. -* -* @note C-Style signature: -* u32 XUartPs_IsReceiveData(u32 BaseAddress) -* -******************************************************************************/ -#define XUartPs_IsReceiveData(BaseAddress) \ - !((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \ - XUARTPS_SR_RXEMPTY) == XUARTPS_SR_RXEMPTY) - -/****************************************************************************/ -/** -* Determine if a byte of data can be sent with the transmitter. -* -* @param BaseAddress contains the base address of the device. -* -* @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the -* FIFO. -* -* @note C-Style signature: -* u32 XUartPs_IsTransmitFull(u32 BaseAddress) -* -******************************************************************************/ -#define XUartPs_IsTransmitFull(BaseAddress) \ - ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \ - XUARTPS_SR_TXFULL) == XUARTPS_SR_TXFULL) - -/************************** Function Prototypes ******************************/ - -void XUartPs_SendByte(u32 BaseAddress, u8 Data); - -u8 XUartPs_RecvByte(u32 BaseAddress); - -void XUartPs_ResetHw(u32 BaseAddress); - -/************************** Variable Definitions *****************************/ - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/xuartps_intr.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/xuartps_intr.c deleted file mode 100644 index 5cfbd0e6f6fcb5db07a5406188c1005419aae967..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/xuartps_intr.c +++ /dev/null @@ -1,452 +0,0 @@ -/***************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -*****************************************************************************/ -/****************************************************************************/ -/** -* -* @file xuartps_intr.c -* -* This file contains the functions for interrupt handling -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------ -------- ----------------------------------------------- -* 1.00 drg/jz 01/13/10 First Release -* </pre> -* -*****************************************************************************/ - -/***************************** Include Files ********************************/ - -#include "xuartps.h" - -/************************** Constant Definitions ****************************/ - -/**************************** Type Definitions ******************************/ - -/***************** Macros (Inline Functions) Definitions ********************/ - -/************************** Function Prototypes *****************************/ - -static void ReceiveDataHandler(XUartPs *InstancePtr); -static void SendDataHandler(XUartPs *InstancePtr, u32 isrstatus); -static void ReceiveErrorHandler(XUartPs *InstancePtr); -static void ReceiveTimeoutHandler(XUartPs *InstancePtr); -static void ModemHandler(XUartPs *InstancePtr); - - -/* Internal function prototypes implemented in xuartps.c */ -extern unsigned int XUartPs_ReceiveBuffer(XUartPs *InstancePtr); -extern unsigned int XUartPs_SendBuffer(XUartPs *InstancePtr); - -/************************** Variable Definitions ****************************/ - -typedef void (*Handler)(XUartPs *InstancePtr); - -/****************************************************************************/ -/** -* -* This function gets the interrupt mask -* -* @param InstancePtr is a pointer to the XUartPs instance. -* -* @return -* The current interrupt mask. The mask indicates which interupts -* are enabled. -* -* @note None. -* -*****************************************************************************/ -u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr) -{ - /* - * Assert validates the input argument - */ - Xil_AssertNonvoid(InstancePtr != NULL); - - /* - * Read the Interrupt Mask register - */ - return (XUartPs_ReadReg(InstancePtr->Config.BaseAddress, - XUARTPS_IMR_OFFSET)); -} - -/****************************************************************************/ -/** -* -* This function sets the interrupt mask. -* -* @param InstancePtr is a pointer to the XUartPs instance -* @param Mask contains the interrupts to be enabled or disabled. -* A '1' enables an interupt, and a '0' disables. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask) -{ - /* - * Assert validates the input arguments - */ - Xil_AssertVoid(InstancePtr != NULL); - - Mask &= XUARTPS_IXR_MASK; - - /* - * Write the mask to the IER Register - */ - XUartPs_WriteReg(InstancePtr->Config.BaseAddress, - XUARTPS_IER_OFFSET, Mask); - - /* - * Write the inverse of the Mask to the IDR register - */ - XUartPs_WriteReg(InstancePtr->Config.BaseAddress, - XUARTPS_IDR_OFFSET, (~Mask)); - -} - -/****************************************************************************/ -/** -* -* This function sets the handler that will be called when an event (interrupt) -* occurs that needs application's attention. -* -* @param InstancePtr is a pointer to the XUartPs instance -* @param FuncPtr is the pointer to the callback function. -* @param CallBackRef is the upper layer callback reference passed back -* when the callback function is invoked. -* -* @return None. -* -* @note -* -* There is no assert on the CallBackRef since the driver doesn't know what it -* is (nor should it) -* -*****************************************************************************/ -void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr, - void *CallBackRef) -{ - /* - * Asserts validate the input arguments - * CallBackRef not checked, no way to know what is valid - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(FuncPtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - InstancePtr->Handler = FuncPtr; - InstancePtr->CallBackRef = CallBackRef; -} - -/****************************************************************************/ -/** -* -* This function is the interrupt handler for the driver. -* It must be connected to an interrupt system by the application such that it -* can be called when an interrupt occurs. -* -* @param InstancePtr contains a pointer to the driver instance -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XUartPs_InterruptHandler(XUartPs *InstancePtr) -{ - u32 IsrStatus; - - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the interrupt ID register to determine which - * interrupt is active - */ - IsrStatus = XUartPs_ReadReg(InstancePtr->Config.BaseAddress, - XUARTPS_IMR_OFFSET); - - IsrStatus &= XUartPs_ReadReg(InstancePtr->Config.BaseAddress, - XUARTPS_ISR_OFFSET); - - /* - * Dispatch an appropiate handler. - */ - if(0 != (IsrStatus & (XUARTPS_IXR_RXOVR | XUARTPS_IXR_RXEMPTY | - XUARTPS_IXR_RXFULL))) { - /* Recieved data interrupt */ - ReceiveDataHandler(InstancePtr); - } - - if(0 != (IsrStatus & (XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_TXFULL))) { - /* Transmit data interrupt */ - SendDataHandler(InstancePtr, IsrStatus); - } - - if(0 != (IsrStatus & (XUARTPS_IXR_OVER | XUARTPS_IXR_FRAMING | - XUARTPS_IXR_PARITY))) { - /* Recieved Error Status interrupt */ - ReceiveErrorHandler(InstancePtr); - } - - if(0 != (IsrStatus & XUARTPS_IXR_TOUT )) { - /* Recieved Timeout interrupt */ - ReceiveTimeoutHandler(InstancePtr); - } - - if(0 != (IsrStatus & XUARTPS_IXR_DMS)) { - /* Modem status interrupt */ - ModemHandler(InstancePtr); - } - - /* - * Clear the interrupt status. - */ - XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_ISR_OFFSET, - IsrStatus); - -} - -/****************************************************************************/ -/* -* -* This function handles interrupts for receive errors which include -* overrun errors, framing errors, parity errors, and the break interrupt. -* -* @param InstancePtr is a pointer to the XUartPs instance. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -static void ReceiveErrorHandler(XUartPs *InstancePtr) -{ - /* - * If there are bytes still to be received in the specified buffer - * go ahead and receive them. Removing bytes from the RX FIFO will - * clear the interrupt. - */ - if (InstancePtr->ReceiveBuffer.RemainingBytes != 0) { - XUartPs_ReceiveBuffer(InstancePtr); - } - - /* - * Call the application handler to indicate that there is a receive - * error or a break interrupt, if the application cares about the - * error it call a function to get the last errors. - */ - InstancePtr->Handler(InstancePtr->CallBackRef, - XUARTPS_EVENT_RECV_ERROR, - (InstancePtr->ReceiveBuffer.RequestedBytes - - InstancePtr->ReceiveBuffer.RemainingBytes)); - -} -/****************************************************************************/ -/** -* -* This function handles the receive timeout interrupt. This interrupt occurs -* whenever a number of bytes have been present in the RX FIFO and the receive -* data line has been idle for at lease 4 or more character times, (the timeout -* is set using XUartPs_SetrecvTimeout() function). -* -* @param InstancePtr is a pointer to the XUartPs instance -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -static void ReceiveTimeoutHandler(XUartPs *InstancePtr) -{ - u32 Event; - - /* - * If there are bytes still to be received in the specified buffer - * go ahead and receive them. Removing bytes from the RX FIFO will - * clear the interrupt. - */ - if (InstancePtr->ReceiveBuffer.RemainingBytes != 0) { - XUartPs_ReceiveBuffer(InstancePtr); - } - - /* - * If there are no more bytes to receive then indicate that this is - * not a receive timeout but the end of the buffer reached, a timeout - * normally occurs if # of bytes is not divisible by FIFO threshold, - * don't rely on previous test of remaining bytes since receive - * function updates it - */ - if (InstancePtr->ReceiveBuffer.RemainingBytes != 0) { - Event = XUARTPS_EVENT_RECV_TOUT; - } else { - Event = XUARTPS_EVENT_RECV_DATA; - } - - /* - * Call the application handler to indicate that there is a receive - * timeout or data event - */ - InstancePtr->Handler(InstancePtr->CallBackRef, Event, - InstancePtr->ReceiveBuffer.RequestedBytes - - InstancePtr->ReceiveBuffer.RemainingBytes); - -} -/****************************************************************************/ -/** -* -* This function handles the interrupt when data is in RX FIFO. -* -* @param InstancePtr is a pointer to the XUartPs instance -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -static void ReceiveDataHandler(XUartPs *InstancePtr) -{ - /* - * If there are bytes still to be received in the specified buffer - * go ahead and receive them. Removing bytes from the RX FIFO will - * clear the interrupt. - */ - if (InstancePtr->ReceiveBuffer.RemainingBytes != 0) { - XUartPs_ReceiveBuffer(InstancePtr); - } - - - /* If the last byte of a message was received then call the application - * handler, this code should not use an else from the previous check of - * the number of bytes to receive because the call to receive the buffer - * updates the bytes ramained - */ - if (InstancePtr->ReceiveBuffer.RemainingBytes == 0) { - InstancePtr->Handler(InstancePtr->CallBackRef, - XUARTPS_EVENT_RECV_DATA, - (InstancePtr->ReceiveBuffer.RequestedBytes - - InstancePtr->ReceiveBuffer.RemainingBytes)); - } - -} - -/****************************************************************************/ -/** -* -* This function handles the interrupt when data has been sent, the transmit -* FIFO is empty (transmitter holding register). -* -* @param InstancePtr is a pointer to the XUartPs instance -* @param IsrStatus is the register value for channel status register -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus) -{ - - /* - * If there are not bytes to be sent from the specified buffer then disable - * the transmit interrupt so it will stop interrupting as it interrupts - * any time the FIFO is empty - */ - if (InstancePtr->SendBuffer.RemainingBytes == 0) { - XUartPs_WriteReg(InstancePtr->Config.BaseAddress, - XUARTPS_IDR_OFFSET, - (XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_TXFULL)); - - /* Call the application handler to indicate the sending is done */ - InstancePtr->Handler(InstancePtr->CallBackRef, - XUARTPS_EVENT_SENT_DATA, - InstancePtr->SendBuffer.RequestedBytes - - InstancePtr->SendBuffer.RemainingBytes); - } - - /* - * If TX FIFO is empty, send more. - */ - else if(IsrStatus & XUARTPS_IXR_TXEMPTY) { - XUartPs_SendBuffer(InstancePtr); - } - -} - -/****************************************************************************/ -/** -* -* This function handles modem interrupts. It does not do any processing -* except to call the application handler to indicate a modem event. -* -* @param InstancePtr is a pointer to the XUartPs instance -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -static void ModemHandler(XUartPs *InstancePtr) -{ - u32 MsrRegister; - - /* - * Read the modem status register so that the interrupt is acknowledged - * and it can be passed to the callback handler with the event - */ - MsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress, - XUARTPS_MODEMSR_OFFSET); - - /* - * Call the application handler to indicate the modem status changed, - * passing the modem status and the event data in the call - */ - InstancePtr->Handler(InstancePtr->CallBackRef, - XUARTPS_EVENT_MODEM, - MsrRegister); - -} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/xuartps_options.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/xuartps_options.c deleted file mode 100644 index 6d7688df58f363adbf1cebdae725bf21841c6905..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/xuartps_options.c +++ /dev/null @@ -1,805 +0,0 @@ -/***************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -*****************************************************************************/ -/****************************************************************************/ -/** -* -* @file xuartps_options.c -* -* The implementation of the options functions for the XUartPs driver. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------ -------- ----------------------------------------------- -* 1.00 drg/jz 01/13/10 First Release -* 1.00 sdm 09/27/11 Fixed a bug in XUartPs_SetFlowDelay where the input -* value was not being written to the register. -* -* </pre> -* -*****************************************************************************/ - -/***************************** Include Files ********************************/ - -#include "xuartps.h" - -/************************** Constant Definitions ****************************/ - -/**************************** Type Definitions ******************************/ - -/***************** Macros (Inline Functions) Definitions ********************/ - -/************************** Variable Definitions ****************************/ -/* - * The following data type is a map from an option to the offset in the - * register to which it belongs as well as its bit mask in that register. - */ -typedef struct { - u16 Option; - u16 RegisterOffset; - u32 Mask; -} Mapping; - -/* - * Create the table which contains options which are to be processed to get/set - * the options. These options are table driven to allow easy maintenance and - * expansion of the options. - */ - -static Mapping OptionsTable[] = { - {XUARTPS_OPTION_SET_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STARTBRK}, - {XUARTPS_OPTION_STOP_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STOPBRK}, - {XUARTPS_OPTION_RESET_TMOUT, XUARTPS_CR_OFFSET, XUARTPS_CR_TORST}, - {XUARTPS_OPTION_RESET_TX, XUARTPS_CR_OFFSET, XUARTPS_CR_TXRST}, - {XUARTPS_OPTION_RESET_RX, XUARTPS_CR_OFFSET, XUARTPS_CR_RXRST}, - {XUARTPS_OPTION_ASSERT_RTS, XUARTPS_MODEMCR_OFFSET, - XUARTPS_MODEMCR_RTS}, - {XUARTPS_OPTION_ASSERT_DTR, XUARTPS_MODEMCR_OFFSET, - XUARTPS_MODEMCR_DTR}, - {XUARTPS_OPTION_SET_FCM, XUARTPS_MODEMCR_OFFSET, XUARTPS_MODEMCR_FCM} -}; - -/* Create a constant for the number of entries in the table */ - -#define XUARTPS_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(Mapping)) - -/************************** Function Prototypes *****************************/ - -/****************************************************************************/ -/** -* -* Gets the options for the specified driver instance. The options are -* implemented as bit masks such that multiple options may be enabled or -* disabled simulataneously. -* -* @param InstancePtr is a pointer to the XUartPs instance. -* -* @return -* -* The current options for the UART. The optionss are bit masks that are -* contained in the file xuartps.h and named XUARTPS_OPTION_*. -* -* @note None. -* -*****************************************************************************/ -u16 XUartPs_GetOptions(XUartPs *InstancePtr) -{ - u16 Options = 0; - u32 Register; - unsigned int Index; - - /* - * Assert validates the input arguments - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Loop thru the options table to map the physical options in the - * registers of the UART to the logical options to be returned - */ - for (Index = 0; Index < XUARTPS_NUM_OPTIONS; Index++) { - Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress, - OptionsTable[Index]. - RegisterOffset); - - /* - * If the bit in the register which correlates to the option - * is set, then set the corresponding bit in the options, - * ignoring any bits which are zero since the options variable - * is initialized to zero - */ - if (Register & OptionsTable[Index].Mask) { - Options |= OptionsTable[Index].Option; - } - } - - return Options; -} - -/****************************************************************************/ -/** -* -* Sets the options for the specified driver instance. The options are -* implemented as bit masks such that multiple options may be enabled or -* disabled simultaneously. -* -* The GetOptions function may be called to retrieve the currently enabled -* options. The result is ORed in the desired new settings to be enabled and -* ANDed with the inverse to clear the settings to be disabled. The resulting -* value is then used as the options for the SetOption function call. -* -* @param InstancePtr is a pointer to the XUartPs instance. -* @param Options contains the options to be set which are bit masks -* contained in the file xuartps.h and named XUARTPS_OPTION_*. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options) -{ - unsigned int Index; - u32 Register; - - /* - * Assert validates the input arguments - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Loop thru the options table to map the logical options to the - * physical options in the registers of the UART. - */ - for (Index = 0; Index < XUARTPS_NUM_OPTIONS; Index++) { - - /* - * Read the register which contains option so that the register - * can be changed without destoying any other bits of the - * register. - */ - Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress, - OptionsTable[Index]. - RegisterOffset); - - /* - * If the option is set in the input, then set the corresponding - * bit in the specified register, otherwise clear the bit in - * the register. - */ - if (Options & OptionsTable[Index].Option) { - Register |= OptionsTable[Index].Mask; - } - else { - Register &= ~OptionsTable[Index].Mask; - } - - /* Write the new value to the register to set the option */ - XUartPs_WriteReg(InstancePtr->Config.BaseAddress, - OptionsTable[Index].RegisterOffset, - Register); - } - -} - -/****************************************************************************/ -/** -* -* This function gets the receive FIFO trigger level. The receive trigger -* level indicates the number of bytes in the receive FIFO that cause a receive -* data event (interrupt) to be generated. -* -* @param InstancePtr is a pointer to the XUartPs instance. -* -* @return The current receive FIFO trigger level. This is a value -* from 0-31. -* -* @note None. -* -*****************************************************************************/ -u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr) -{ - u8 RtrigRegister; - - /* - * Assert validates the input arguments - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the value of the FIFO control register so that the threshold - * can be retrieved, this read takes special register processing - */ - RtrigRegister = (u8) XUartPs_ReadReg(InstancePtr->Config.BaseAddress, - XUARTPS_RXWM_OFFSET); - - /* Return only the trigger level from the register value */ - - return (RtrigRegister & XUARTPS_RXWM_MASK); -} - -/****************************************************************************/ -/** -* -* This functions sets the receive FIFO trigger level. The receive trigger -* level specifies the number of bytes in the receive FIFO that cause a receive -* data event (interrupt) to be generated. -* -* @param InstancePtr is a pointer to the XUartPs instance. -* @param TriggerLevel contains the trigger level to set. -* -* @return None -* -* @note None. -* -*****************************************************************************/ -void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel) -{ - u32 RtrigRegister; - - /* - * Assert validates the input arguments - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(TriggerLevel <= XUARTPS_RXWM_MASK); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - RtrigRegister = TriggerLevel & XUARTPS_RXWM_MASK; - - /* - * Write the new value for the FIFO control register to it such that the - * threshold is changed - */ - XUartPs_WriteReg(InstancePtr->Config.BaseAddress, - XUARTPS_RXWM_OFFSET, RtrigRegister); - -} - -/****************************************************************************/ -/** -* -* This function gets the modem status from the specified UART. The modem -* status indicates any changes of the modem signals. This function allows -* the modem status to be read in a polled mode. The modem status is updated -* whenever it is read such that reading it twice may not yield the same -* results. -* -* @param InstancePtr is a pointer to the XUartPs instance. -* -* @return -* -* The modem status which are bit masks that are contained in the file -* xuartps.h and named XUARTPS_MODEM_*. -* -* @note -* -* The bit masks used for the modem status are the exact bits of the modem -* status register with no abstraction. -* -*****************************************************************************/ -u16 XUartPs_GetModemStatus(XUartPs *InstancePtr) -{ - u32 ModemStatusRegister; - - /* - * Assert validates the input arguments - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* Read the modem status register to return - */ - ModemStatusRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress, - XUARTPS_MODEMSR_OFFSET); - return ModemStatusRegister; -} - -/****************************************************************************/ -/** -* -* This function determines if the specified UART is sending data. -* -* @param InstancePtr is a pointer to the XUartPs instance. -* -* @return -* - TRUE if the UART is sending data -* - FALSE if UART is not sending data -* -* @note None. -* -*****************************************************************************/ -u32 XUartPs_IsSending(XUartPs *InstancePtr) -{ - u32 ChanStatRegister; - - /* - * Assert validates the input arguments - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the channel status register to determine if the transmitter is - * active - */ - ChanStatRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress, - XUARTPS_SR_OFFSET); - - /* - * If the transmitter is active, or the TX FIFO is not empty, then indicate - * that the UART is still sending some data - */ - return ((XUARTPS_SR_TACTIVE == (ChanStatRegister & - XUARTPS_SR_TACTIVE)) || - (XUARTPS_SR_TXEMPTY != (ChanStatRegister & - XUARTPS_SR_TXEMPTY))); -} - -/****************************************************************************/ -/** -* -* This function gets the operational mode of the UART. The UART can operate -* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic -* echo. -* -* @param InstancePtr is a pointer to the XUartPs instance. -* -* @return -* -* The operational mode is specified by constants defined in xuartps.h. The -* constants are named XUARTPS_OPER_MODE_* -* -* @note None. -* -*****************************************************************************/ -u8 XUartPs_GetOperMode(XUartPs *InstancePtr) -{ - u32 ModeRegister; - u8 OperMode; - - /* - * Assert validates the input arguments - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the Mode register. - */ - ModeRegister = - XUartPs_ReadReg(InstancePtr->Config.BaseAddress, - XUARTPS_MR_OFFSET); - - ModeRegister &= XUARTPS_MR_CHMODE_MASK; - /* - * Return the constant - */ - switch (ModeRegister) { - case XUARTPS_MR_CHMODE_NORM: - OperMode = XUARTPS_OPER_MODE_NORMAL; - break; - case XUARTPS_MR_CHMODE_ECHO: - OperMode = XUARTPS_OPER_MODE_AUTO_ECHO; - break; - case XUARTPS_MR_CHMODE_L_LOOP: - OperMode = XUARTPS_OPER_MODE_LOCAL_LOOP; - break; - case XUARTPS_MR_CHMODE_R_LOOP: - OperMode = XUARTPS_OPER_MODE_REMOTE_LOOP; - break; - default: - OperMode = (u8) ((ModeRegister & XUARTPS_MR_CHMODE_MASK) >> - XUARTPS_MR_CHMODE_SHIFT); - } - - return OperMode; -} - -/****************************************************************************/ -/** -* -* This function sets the operational mode of the UART. The UART can operate -* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic -* echo. -* -* @param InstancePtr is a pointer to the XUartPs instance. -* @param OperationMode is the mode of the UART. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode) -{ - u32 ModeRegister; - - /* - * Assert validates the input arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(OperationMode <= XUARTPS_OPER_MODE_REMOTE_LOOP); - - /* - * Read the Mode register. - */ - ModeRegister = - XUartPs_ReadReg(InstancePtr->Config.BaseAddress, - XUARTPS_MR_OFFSET); - - /* - * Set the correct value by masking the bits, then ORing the const. - */ - ModeRegister &= ~XUARTPS_MR_CHMODE_MASK; - - switch (OperationMode) { - case XUARTPS_OPER_MODE_NORMAL: - ModeRegister |= XUARTPS_MR_CHMODE_NORM; - break; - case XUARTPS_OPER_MODE_AUTO_ECHO: - ModeRegister |= XUARTPS_MR_CHMODE_ECHO; - break; - case XUARTPS_OPER_MODE_LOCAL_LOOP: - ModeRegister |= XUARTPS_MR_CHMODE_L_LOOP; - break; - case XUARTPS_OPER_MODE_REMOTE_LOOP: - ModeRegister |= XUARTPS_MR_CHMODE_R_LOOP; - break; - } - - XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET, - ModeRegister); - -} - -/****************************************************************************/ -/** -* -* This function sets the Flow Delay. -* 0 - 3: Flow delay inactive -* 4 - 32: If Flow Control mode is enabled, UART_rtsN is deactivated when the -* receive FIFO fills to this level. -* -* @param InstancePtr is a pointer to the XUartPs instance. -* -* @return -* -* The Flow Delay is specified by constants defined in xuartps_hw.h. The -* constants are named XUARTPS_FLOWDEL* -* -* @note None. -* -*****************************************************************************/ -u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr) -{ - u32 FdelRegister; - - /* - * Assert validates the input arguments - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the Mode register. - */ - FdelRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress, - XUARTPS_FLOWDEL_OFFSET); - - /* - * Return the contents of the flow delay register - */ - return (u8) (FdelRegister & XUARTPS_FLOWDEL_MASK); -} - -/****************************************************************************/ -/** -* -* This function sets the Flow Delay. -* 0 - 3: Flow delay inactive -* 4 - 63: If Flow Control mode is enabled, UART_rtsN is deactivated when the -* receive FIFO fills to this level. -* -* @param InstancePtr is a pointer to the XUartPs instance. -* @param FlowDelayValue is the Setting for the flow delay. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue) -{ - u32 FdelRegister; - - /* - * Assert validates the input arguments - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(FlowDelayValue > XUARTPS_FLOWDEL_MASK); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Set the correct value by shifting the input constant, then masking - * the bits - */ - FdelRegister = (FlowDelayValue & XUARTPS_FLOWDEL_MASK); - - XUartPs_WriteReg(InstancePtr->Config.BaseAddress, - XUARTPS_FLOWDEL_OFFSET, FdelRegister); - -} - -/****************************************************************************/ -/** -* -* This function gets the Receive Timeout of the UART. -* -* @param InstancePtr is a pointer to the XUartPs instance. -* -* @return The current setting for receive time out. -* -* @note None. -* -*****************************************************************************/ -u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr) -{ - u32 RtoRegister; - - /* - * Assert validates the input arguments - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the Recieve Timeout register. - */ - RtoRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress, - XUARTPS_RXTOUT_OFFSET); - - /* - * Return the contents of the mode register shifted appropriately - */ - return (RtoRegister & XUARTPS_RXTOUT_MASK); -} - -/****************************************************************************/ -/** -* -* This function sets the Receive Timeout of the UART. -* -* @param InstancePtr is a pointer to the XUartPs instance. -* @param RecvTimeout setting allows the UART to detect an idle connection -* on the reciever data line. -* Timeout duration = RecvTimeout x 4 x Bit Period. 0 disables the -* timeout function. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout) -{ - u32 RtoRegister; - - /* - * Assert validates the input arguments - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Set the correct value by masking the bits - */ - RtoRegister = (RecvTimeout & XUARTPS_RXTOUT_MASK); - - XUartPs_WriteReg(InstancePtr->Config.BaseAddress, - XUARTPS_RXTOUT_OFFSET, RtoRegister); - - /* - * Configure CR to restart the receiver timeout counter - */ - RtoRegister = - XUartPs_ReadReg(InstancePtr->Config.BaseAddress, - XUARTPS_CR_OFFSET); - XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_CR_OFFSET, - (RtoRegister | XUARTPS_CR_TORST)); - -} -/****************************************************************************/ -/** -* -* Sets the data format for the device. The data format includes the -* baud rate, number of data bits, number of stop bits, and parity. It is the -* caller's responsibility to ensure that the UART is not sending or receiving -* data when this function is called. -* -* @param InstancePtr is a pointer to the XUartPs instance. -* @param FormatPtr is a pointer to a format structure containing the data -* format to be set. -* -* @return -* - XST_SUCCESS if the data format was successfully set. -* - XST_UART_BAUD_ERROR indicates the baud rate could not be -* set because of the amount of error with the baud rate and -* the input clock frequency. -* - XST_INVALID_PARAM if one of the parameters was not valid. -* -* @note -* -* The data types in the format type, data bits and parity, are 32 bit fields -* to prevent a compiler warning. -* The asserts in this function will cause a warning if these fields are -* bytes. -* <br><br> -* -*****************************************************************************/ -int XUartPs_SetDataFormat(XUartPs *InstancePtr, - XUartPsFormat * FormatPtr) -{ - int Status; - u32 ModeRegister; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(FormatPtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Verify the inputs specified are valid - */ - if ((FormatPtr->DataBits > XUARTPS_FORMAT_6_BITS) || - (FormatPtr->StopBits > XUARTPS_FORMAT_2_STOP_BIT) || - (FormatPtr->Parity > XUARTPS_FORMAT_NO_PARITY)) { - return XST_INVALID_PARAM; - } - - /* - * Try to set the baud rate and if it's not successful then don't - * continue altering the data format, this is done first to avoid the - * format from being altered when an error occurs - */ - Status = XUartPs_SetBaudRate(InstancePtr, FormatPtr->BaudRate); - if (Status != XST_SUCCESS) { - return Status; - } - - ModeRegister = - XUartPs_ReadReg(InstancePtr->Config.BaseAddress, - XUARTPS_MR_OFFSET); - - /* - * Set the length of data (8,7,6) by first clearing out the bits - * that control it in the register, then set the length in the register - */ - ModeRegister &= ~XUARTPS_MR_CHARLEN_MASK; - ModeRegister |= (FormatPtr->DataBits << XUARTPS_MR_CHARLEN_SHIFT); - - /* - * Set the number of stop bits in the mode register by first clearing - * out the bits that control it in the register, then set the number - * of stop bits in the register. - */ - ModeRegister &= ~XUARTPS_MR_STOPMODE_MASK; - ModeRegister |= (FormatPtr->StopBits << XUARTPS_MR_STOPMODE_SHIFT); - - /* - * Set the parity by first clearing out the bits that control it in the - * register, then set the bits in the register, the default is no parity - * after clearing the register bits - */ - ModeRegister &= ~XUARTPS_MR_PARITY_MASK; - ModeRegister |= (FormatPtr->Parity << XUARTPS_MR_PARITY_SHIFT); - - /* - * Update the mode register - */ - XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET, - ModeRegister); - - return XST_SUCCESS; -} - -/****************************************************************************/ -/** -* -* Gets the data format for the specified UART. The data format includes the -* baud rate, number of data bits, number of stop bits, and parity. -* -* @param InstancePtr is a pointer to the XUartPs instance. -* @param FormatPtr is a pointer to a format structure that will contain -* the data format after this call completes. -* -* @return None. -* -* @note None. -* -* -*****************************************************************************/ -void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr) -{ - u32 ModeRegister; - - - /* - * Assert validates the input arguments - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(FormatPtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Get the baud rate from the instance, this is not retrieved from the - * hardware because it is only kept as a divisor such that it is more - * difficult to get back to the baud rate - */ - FormatPtr->BaudRate = InstancePtr->BaudRate; - - ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress, - XUARTPS_MR_OFFSET); - - /* - * Get the length of data (8,7,6,5) - */ - FormatPtr->DataBits = - (ModeRegister & XUARTPS_MR_CHARLEN_MASK) >> - XUARTPS_MR_CHARLEN_SHIFT; - - /* - * Get the number of stop bits - */ - FormatPtr->StopBits = - (ModeRegister & XUARTPS_MR_STOPMODE_MASK) >> - XUARTPS_MR_STOPMODE_SHIFT; - - /* - * Determine what parity is - */ - FormatPtr->Parity = - (ModeRegister & XUARTPS_MR_PARITY_MASK) >> - XUARTPS_MR_PARITY_SHIFT; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/xuartps_selftest.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/xuartps_selftest.c deleted file mode 100644 index 42b8cafa93ef9d9d64f61abf453176916b6439f2..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/xuartps_selftest.c +++ /dev/null @@ -1,176 +0,0 @@ -/***************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -*****************************************************************************/ -/****************************************************************************/ -/** -* -* @file xuartps_selftest.c -* -* This file contains the self-test functions for the XUartPs driver. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------ -------- ----------------------------------------------- -* 1.00 drg/jz 01/13/108First Release -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xstatus.h" -#include "xuartps.h" - -/************************** Constant Definitions *****************************/ - - -/**************************** Type Definitions *******************************/ - - -/***************** Macros (Inline Functions) Definitions *********************/ - -#define XUARTPS_TOTAL_BYTES 32 - -/************************** Variable Definitions *****************************/ - -static u8 TestString[XUARTPS_TOTAL_BYTES]="abcdefghABCDEFGH012345677654321"; -static u8 ReturnString[XUARTPS_TOTAL_BYTES]; - -/************************** Function Prototypes ******************************/ - - -/****************************************************************************/ -/** -* -* This function runs a self-test on the driver and hardware device. This self -* test performs a local loopback and verifies data can be sent and received. -* -* The time for this test is proportional to the baud rate that has been set -* prior to calling this function. -* -* The mode and control registers are restored before return. -* -* @param InstancePtr is a pointer to the XUartPs instance -* -* @return -* - XST_SUCCESS if the test was successful -* - XST_UART_TEST_FAIL if the test failed looping back the data -* -* @note -* -* This function can hang if the hardware is not functioning properly. -* -******************************************************************************/ -int XUartPs_SelfTest(XUartPs *InstancePtr) -{ - int Status = XST_SUCCESS; - u32 IntrRegister; - u32 ModeRegister; - u8 Index; - - /* - * Assert validates the input arguments - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Disable all interrupts in the interrupt disable register - */ - IntrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress, - XUARTPS_IMR_OFFSET); - XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET, - XUARTPS_IXR_MASK); - - /* - * Setup for local loopback - */ - ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress, - XUARTPS_MR_OFFSET); - XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET, - ((ModeRegister & (~XUARTPS_MR_CHMODE_MASK)) | - XUARTPS_MR_CHMODE_L_LOOP)); - - /* - * Send a number of bytes and receive them, one at a time. - */ - for (Index = 0; Index < XUARTPS_TOTAL_BYTES; Index++) { - /* - * Send out the byte and if it was not sent then the failure - * will be caught in the comparison at the end - */ - XUartPs_Send(InstancePtr, &TestString[Index], 1); - - /* - * Wait until the byte is received. This can hang if the HW - * is broken. Watch for the FIFO empty flag to be false. - */ - while (!(XUartPs_IsReceiveData(InstancePtr->Config. - BaseAddress))); - - /* - * Receive the byte - */ - XUartPs_Recv(InstancePtr, &ReturnString[Index], 1); - } - - /* - * Compare the bytes received to the bytes sent to verify the exact data - * was received - */ - for (Index = 0; Index < XUARTPS_TOTAL_BYTES; Index++) { - if (TestString[Index] != ReturnString[Index]) { - Status = XST_UART_TEST_FAIL; - } - } - - /* - * Restore the registers which were altered to put into polling and - * loopback modes so that this test is not destructive - */ - XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET, - IntrRegister); - XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET, - ModeRegister); - - return Status; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/xuartps_sinit.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/xuartps_sinit.c deleted file mode 100644 index 4a2c7d1a82ff6e81b6981b21c96442acdde687b1..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/uartps_v1_05_a/src/xuartps_sinit.c +++ /dev/null @@ -1,104 +0,0 @@ -/***************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -*****************************************************************************/ -/****************************************************************************/ -/** -* -* @file xuartps_sinit.c -* -* The implementation of the XUartPs driver's static initialzation -* functionality. -* -* <pre> -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ------ -------- ----------------------------------------------- -* 1.00 drg/jz 01/13/10 First Release -* </pre> -* -*****************************************************************************/ - -/***************************** Include Files ********************************/ - -#include "xstatus.h" -#include "xparameters.h" -#include "xuartps.h" - -/************************** Constant Definitions ****************************/ - -/**************************** Type Definitions ******************************/ - -/***************** Macros (Inline Functions) Definitions ********************/ - -/************************** Variable Definitions ****************************/ -extern XUartPs_Config XUartPs_ConfigTable[]; - -/************************** Function Prototypes *****************************/ - -/****************************************************************************/ -/** -* -* Looks up the device configuration based on the unique device ID. The table -* contains the configuration info for each device in the system. -* -* @param DeviceId contains the ID of the device -* -* @return A pointer to the configuration structure or NULL if the -* specified device is not in the system. -* -* @note None. -* -******************************************************************************/ -XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId) -{ - XUartPs_Config *CfgPtr = NULL; - - int Index; - - for (Index = 0; Index < XPAR_XUARTPS_NUM_INSTANCES; Index++) { - if (XUartPs_ConfigTable[Index].DeviceId == DeviceId) { - CfgPtr = &XUartPs_ConfigTable[Index]; - break; - } - } - - return CfgPtr; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/Makefile b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/Makefile deleted file mode 100644 index 7cf97e2f02131dc8dcc848251f88cf637781f852..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -COMPILER= -ARCHIVER= -CP=cp -COMPILER_FLAGS= -EXTRA_COMPILER_FLAGS= -LIB=libxil.a - -CC_FLAGS = $(COMPILER_FLAGS) -ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) - -RELEASEDIR=../../../lib -INCLUDEDIR=../../../include -INCLUDES=-I./. -I${INCLUDEDIR} - -OUTS = *.o - -LIBSOURCES:=*.c -INCLUDEFILES:=*.h - -OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) - -libs: banner xusbps_libs clean - -%.o: %.c - ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< - -banner: - echo "Compiling usbps" - -xusbps_libs: ${OBJECTS} - $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} - -.PHONY: include -include: xusbps_includes - -xusbps_includes: - ${CP} ${INCLUDEFILES} ${INCLUDEDIR} - -clean: - rm -rf ${OBJECTS} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/xusbps.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/xusbps.c deleted file mode 100644 index 82344db51caacea7dda01f98fc7ed4d0e83cc9e5..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/xusbps.c +++ /dev/null @@ -1,437 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/******************************************************************************/ -/** - * @file xusbps.c - * - * The XUsbPs driver. Functions in this file are the minimum required - * functions for this driver. See xusbps.h for a detailed description of the - * driver. - * - * @note None. - * - * <pre> - * MODIFICATION HISTORY: - * - * Ver Who Date Changes - * ----- ---- -------- -------------------------------------------------------- - * 1.00a jz 10/10/10 First release - * </pre> - ******************************************************************************/ - -/***************************** Include Files **********************************/ -#include <stdio.h> -#include "xusbps.h" - -/************************** Constant Definitions ******************************/ - -/**************************** Type Definitions ********************************/ - -/***************** Macros (Inline Functions) Definitions **********************/ - -/************************** Variable Definitions ******************************/ - -/************************** Function Prototypes *******************************/ - -/*****************************************************************************/ -/** -* -* This function initializes a XUsbPs instance/driver. -* -* The initialization entails: -* - Initialize all members of the XUsbPs structure. -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* @param ConfigPtr is a pointer to a XUsbPs_Config configuration -* structure. This structure will contain the requested -* configuration for the device. Typically, this is a local -* structure and the content of which will be copied into the -* configuration structure within XUsbPs. -* @param VirtBaseAddress is the base address of the device. For systems -* with virtual memory, this address must be the virtual address -* of the device. -* For systems that do not support virtual memory this address -* should be the physical address of the device. For backwards -* compatibilty NULL may be passed in systems that do not support -* virtual memory (deprecated). -* -* @return -* - XST_SUCCESS no errors occured. -* - XST_FAILURE an error occured during initialization. -* -* @note -* After calling XUsbPs_CfgInitialize() the controller -* IS NOT READY for use. Before the controller can be used its -* DEVICE parameters must be configured. See xusbps.h -* for details. -* -******************************************************************************/ -int XUsbPs_CfgInitialize(XUsbPs *InstancePtr, - const XUsbPs_Config *ConfigPtr, u32 VirtBaseAddress) -{ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(ConfigPtr != NULL); - - /* Copy the config structure. */ - InstancePtr->Config = *ConfigPtr; - - /* Check if the user provided a non-NULL base address. If so, we have - * to overwrite the base address in the configuration structure. - */ - if (0 != VirtBaseAddress) { - InstancePtr->Config.BaseAddress = VirtBaseAddress; - } - - /* Initialize the XUsbPs structure to default values. */ - InstancePtr->CurrentAltSetting = XUSBPS_DEFAULT_ALT_SETTING; - - InstancePtr->HandlerFunc = NULL; - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* This function performs device reset, device is stopped at the end. -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XUsbPs_DeviceReset(XUsbPs *InstancePtr) -{ - int Timeout; - - /* Clear all setup token semaphores by reading the - * XUSBPS_EPSTAT_OFFSET register and writing its value back to - * itself. - */ - XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPSTAT_OFFSET, - XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPSTAT_OFFSET)); - - /* Clear all the endpoint complete status bits by reading the - * XUSBPS_EPCOMPL_OFFSET register and writings its value back - * to itself. - */ - XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPCOMPL_OFFSET, - XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPCOMPL_OFFSET)); - - /* Cancel all endpoint prime status by waiting until all bits - * in XUSBPS_EPPRIME_OFFSET are 0 and then writing 0xFFFFFFFF - * to XUSBPS_EPFLUSH_OFFSET. - * - * Avoid hanging here by using a Timeout counter... - */ - Timeout = XUSBPS_TIMEOUT_COUNTER; - while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPPRIME_OFFSET) & - XUSBPS_EP_ALL_MASK) && --Timeout) { - /* NOP */ - } - XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPFLUSH_OFFSET, 0xFFFFFFFF); - - XUsbPs_Stop(InstancePtr); - - /* Write to CR register for controller reset */ - XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET, - XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - XUSBPS_CMD_OFFSET) | XUSBPS_CMD_RST_MASK); - - /* Wait for reset to finish, hardware clears the reset bit once done */ - Timeout = 1000000; - while((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - XUSBPS_CMD_OFFSET) & - XUSBPS_CMD_RST_MASK) && --Timeout) { - /* NOP */ - } -} -/*****************************************************************************/ -/** -* -* This function resets the USB device. All the configuration registers are -* reset to their default values. The function waits until the reset operation -* is complete or for a certain duration within which the reset operation is -* expected to be completed. -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* -* @return -* - XST_SUCCESS Reset operation completed successfully. -* - XST_FAILURE Reset operation timed out. -* -* @note None. -* -******************************************************************************/ -int XUsbPs_Reset(XUsbPs *InstancePtr) -{ - int Timeout; - - Xil_AssertNonvoid(InstancePtr != NULL); - - /* Write a 1 to the RESET bit. The RESET bit is cleared by HW once the - * RESET is complete. - * - * We are going to wait for the RESET bit to clear before we return - * from this function. Unfortunately we do not have timers available at - * this point to determine when we should report a Timeout. - * - * However, by using a large number for the poll loop we can assume - * that the polling operation will take longer than the expected time - * the HW needs to RESET. If the poll loop expires we can assume a - * Timeout. The drawback is that on a slow system (and even on a fast - * system) this can lead to _very_ long Timeout periods. - */ - XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, - XUSBPS_CMD_OFFSET, XUSBPS_CMD_RST_MASK); - - - /* Wait for the RESET bit to be cleared by HW. */ - Timeout = XUSBPS_TIMEOUT_COUNTER; - while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - XUSBPS_CMD_OFFSET) & - XUSBPS_CMD_RST_MASK) && --Timeout) { - /* NOP */ - } - - if (0 == Timeout) { - return XST_FAILURE; - } - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** - * USB Suspend - * - * In order to conserve power, USB devices automatically enter the suspended - * state when the device has observed no bus traffic for a specified period. - * When suspended, the USB device maintains any internal status, including its - * address and configuration. Attached devices must be prepared to suspend at - * any time they are powered, regardless of if they have been assigned a - * non-default address, are configured, or neither. Bus activity may cease due - * to the host entering a suspend mode of its own. In addition, a USB device - * shall also enter the suspended state when the hub port it is attached to is - * disabled. - * - * A USB device exits suspend mode when there is bus activity. A USB device may - * also request the host to exit suspend mode or selective suspend by using - * electrical signaling to indicate remote wakeup. The ability of a device to - * signal remote wakeup is optional. If the USB device is capable of remote - * wakeup signaling, the device must support the ability of the host to enable - * and disable this capability. When the device is reset, remote wakeup - * signaling must be disabled. - * - * @param InstancePtr is a pointer to XUsbPs instance of the controller. - * - * @return - * - XST_SUCCESS if the USB device has entered Suspend mode - * successfully - * - XST_FAILURE on any error - * - * @note None. - * - ******************************************************************************/ -int XUsbPs_Suspend(const XUsbPs *InstancePtr) -{ - (void) InstancePtr; - - return XST_SUCCESS; -} - - -/*****************************************************************************/ -/** -* USB Resume -* - If the USB controller is suspended, its operation is resumed when any -* non-idle signaling is received on its upstream facing port. -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* -* @return -* - XST_SUCCESS if the USB device has Resumed successfully -* - XST_FAILURE on any error -* -* @note None. -* -******************************************************************************/ -int XUsbPs_Resume(const XUsbPs *InstancePtr) -{ - (void) InstancePtr; - return XST_SUCCESS; -} - - -/*****************************************************************************/ -/** -* USB Assert Resume -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* -* @return -* - XST_SUCCESS if the USB device has Resumed successfully -* - XST_FAILURE on any error -* -* @note None. -* -******************************************************************************/ - -int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr) -{ - (void) InstancePtr; - return XST_SUCCESS; -} - - -/****************************************************************************/ -/** - * This function returns the size of the DMAable memory required by the driver - * to store the Endpoint Device Queue Head List, the Transfer Descriptors and - * all OUT (receive) Transfer Descriptor buffers. - * - * @param CfgPtr is pointer to the XUsbPs_DeviceConfig instance of the - * controller. - * - * @return The number of bytes of DMAable memory required. - * Returns 0 on error. - * - * @note - * All the endpoint parameters in the XUsbPs_DeviceConfig data - * structure must be configured to their desired values before - * calling this function. - * - *****************************************************************************/ -u32 XUsbPs_DeviceMemRequired(const XUsbPs_DeviceConfig *CfgPtr) -{ - int EndPointNum; - u32 Size; - - Xil_AssertNonvoid(NULL != CfgPtr); - - /* Start with the amount required to be able to align the allocated - * memory block to XUSBPS_dQH_BASE_ALIGN. The first data structure put - * into this memory block is the Device Queue Head List which must be - * aligned at a XUSBPS_dQH_BASE_ALIGN boundary. - */ - Size = XUSBPS_dQH_BASE_ALIGN; - - /* Add the size required for the Queue Heads. There are 2 Queue Heads - * per Endpoint. We need to allocate memory even for endpoints that are - * not used. - */ - Size += CfgPtr->NumEndpoints * 2 * XUSBPS_dQH_ALIGN; - - /* Add the size required for the Transfer Descriptors and the OUT - * buffers. - */ - for (EndPointNum = 0; EndPointNum < CfgPtr->NumEndpoints; EndPointNum++) { - if (XUSBPS_EP_TYPE_NONE != CfgPtr->EpCfg[EndPointNum].Out.Type) { - /* Memory required for OUT Transfer Descriptors. - */ - Size += CfgPtr->EpCfg[EndPointNum].Out.NumBufs * - XUSBPS_dTD_ALIGN; - /* Memory required for OUT buffers. - */ - Size += CfgPtr->EpCfg[EndPointNum].Out.NumBufs * - CfgPtr->EpCfg[EndPointNum].Out.BufSize; - } - - - if (XUSBPS_EP_TYPE_NONE != CfgPtr->EpCfg[EndPointNum].In.Type) { - /* Memory required for IN Transfer Descriptors. - */ - Size += CfgPtr->EpCfg[EndPointNum].In.NumBufs * - XUSBPS_dTD_ALIGN; - } - - } - - return Size; -} - - -/****************************************************************************/ -/** -* This functions sets the controller's DEVICE address. It also sets the -* advance bit so the controller will wait for the next IN-ACK before the new -* address takes effect. -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* @param Address is the Address of the device. -* -* @return -* - XST_SUCCESS: Address set successfully. -* - XST_FAILURE: An error occured. -* - XST_INVALID_PARAM: Invalid parameter passed, e.g. address -* value too big. -* -* @note None. -* -*****************************************************************************/ -int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address) -{ - Xil_AssertNonvoid(InstancePtr != NULL); - - /* Check address range validity. */ - if (Address > XUSBPS_DEVICEADDR_MAX) { - return XST_INVALID_PARAM; - } - - /* Set the address register with the Address value provided. Also set - * the Address Advance Bit. This will cause the address to be set only - * after an IN occured and has been ACKed on the endpoint. - */ - XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, - XUSBPS_DEVICEADDR_OFFSET, - (Address << XUSBPS_DEVICEADDR_ADDR_SHIFT) | - XUSBPS_DEVICEADDR_DEVICEAADV_MASK); - - return XST_SUCCESS; -} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/xusbps.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/xusbps.h deleted file mode 100644 index a4a552393bb0ddc428ac606be7786ae33e954f12..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/xusbps.h +++ /dev/null @@ -1,1091 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** - * - * @file xusbps.h - * - * This file contains the implementation of the XUsbPs driver. It is the - * driver for an USB controller in DEVICE or HOST mode. - * - * <h2>Introduction</h2> - * - * The Spartan-3AF Embedded Peripheral Block contains a USB controller for - * communication with serial peripherals or hosts. The USB controller supports - * Host, Device and On the Go (OTG) applications. - * - * <h2>USB Controller Features</h2> - * - * - Supports Low Speed USB 1.1 (1.5Mbps), Full Speed USB 1.1 (12Mbps), and - * High Speed USB 2.0 (480Mbps) data speeds - * - Supports Device, Host and OTG operational modes - * - ULPI transceiver interface for USB 2.0 operation - * - Integrated USB Full and Low speed serial transceiver interfaces for lowest - * cost connections - * - * <h2>Initialization & Configuration</h2> - * - * The configuration of the USB driver happens in multiple stages: - * - * - (a) Configuration of the basic parameters: - * In this stage the basic parameters for the driver are configured, - * including the base address and the controller ID. - * - * - (b) Configuration of the DEVICE endpoints (if applicable): - * If DEVICE mode is desired, the endpoints of the controller need to be - * configured using the XUsbPs_DeviceConfig data structure. Once the - * endpoint configuration is set up in the data structure, the user needs to - * call XUsbPs_DeviceMemRequired() to obtain the required size of DMAable - * memory that the driver needs for operation with the given configuration. - * The user then needs to allocate the required amount of DMAable memory and - * finalize the configuration of the XUsbPs_DeviceConfig data structure, - * e.g. setting the DMAMemVirt and DMAMemPhys members. - * - * - (c) Configuration of the DEVICE modes: - * In the second stage the parameters for DEVICE are configured. - * The caller only needs to configure the modes that are - * actually used. Configuration is done with the: - * XUsbPs_ConfigureDevice() - * Configuration parameters are defined and passed - * into these functions using the: - * XUsbPs_DeviceConfig data structures. - * - * - * <h2>USB Device Endpoints</h2> - * - * The USB core supports up to 4 endpoints. Each endpoint has two directions, - * an OUT (RX) and an IN (TX) direction. Note that the direction is viewed from - * the host's perspective. Endpoint 0 defaults to be the control endpoint and - * does not need to be set up. Other endpoints need to be configured and set up - * depending on the application. Only endpoints that are actuelly used by the - * application need to be initialized. - * See the example code (xusbps_intr_example.c) for more information. - * - * - * <h2>Interrupt Handling</h2> - * - * The USB core uses one interrupt line to report interrupts to the CPU. - * Interrupts are handled by the driver's interrupt handler function - * XUsbPs_IntrHandler(). - * It has to be registered with the OS's interrupt subsystem. The driver's - * interrupt handler divides incoming interrupts into two categories: - * - * - General device interrupts - * - Endopint related interrupts - * - * The user (typically the adapter layer) can register general interrupt - * handler fucntions and endpoint specific interrupt handler functions with the - * driver to receive those interrupts by calling the - * XUsbPs_IntrSetHandler() - * and - * XUsbPs_EpSetHandler() - * functions respectively. Calling these functions with a NULL pointer as the - * argument for the function pointer will "clear" the handler function. - * - * The user can register one handler function for the generic interrupts and - * two handler functions for each endpoint, one for the RX (OUT) and one for - * the TX (IN) direction. For some applications it may be useful to register a - * single endpoint handler function for muliple endpoints/directions. - * - * When a callback function is called by the driver, parameters identifying the - * type of the interrupt will be passed into the handler functions. For general - * interrupts the interrupt mask will be passed into the handler function. For - * endpoint interrupts the parameters include the number of the endpoint, the - * direction (OUT/IN) and the type of the interrupt. - * - * - * <h2>Data buffer handling</h2> - * - * Data buffers are sent to and received from endpoint using the - * XUsbPs_EpBufferSend() - * and - * XUsbPs_EpBufferReceive() - * functions. - * - * User data buffer size is limited to 16 Kbytes. If the user wants to send a - * data buffer that is bigger than this limit it needs to break down the data - * buffer into multiple fragments and send the fragments individually. - * - * Data buffers can be aligned at any boundary. - * - * - * <h3>Zero copy</h3> - * - * The driver uses a zero copy mechanism which imposes certain restrictions to - * the way the user can handle the data buffers. - * - * One restriction is that the user needs to release a buffer after it is done - * processing the data in the buffer. - * - * Similarly, when the user sends a data buffer it MUST not re-use the buffer - * until it is notified by the driver that the buffer has been transmitted. The - * driver will notify the user via the registered endpoint interrupt handling - * function by sending a XUSBPS_EP_EVENT_DATA_TX event. - * - * - * <h2>DMA</h2> - * - * The driver uses DMA internally to move data from/to memory. This behaviour - * is transparent to the user. Keeping the DMA handling hidden from the user - * has the advantage that the same API can be used with USB cores that do not - * support DMA. - * - * - * <pre> - * MODIFICATION HISTORY: - * - * Ver Who Date Changes - * ----- ---- -------- ---------------------------------------------------------- - * 1.00a wgr 10/10/10 First release - * 1.02a wgr 05/16/12 Removed comments as they are showing up in SDK - * Tabs for CR 657898 - * 1.03a nm 09/21/12 Fixed CR#678977. Added proper sequence for setup packet - * handling. - * 1.04a nm 10/23/12 Fixed CR# 679106. - * 11/02/12 Fixed CR# 683931. Mult bits are set properly in dQH. - * </pre> - * - ******************************************************************************/ - -#ifndef XUSBPS_H -#define XUSBPS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xusbps_hw.h" -#include "xil_types.h" -#include "xstatus.h" - -/************************** Constant Definitions *****************************/ - -/** - * @name System hang prevention Timeout counter value. - * - * This value is used throughout the code to initialize a Timeout counter that - * is used when hard polling a register. The ides is to initialize the Timeout - * counter to a value that is longer than any expected Timeout but short enough - * so the system will continue to work and report an error while the user is - * still paying attention. A reasonable Timeout time would be about 10 seconds. - * The XUSBPS_TIMEOUT_COUNTER value should be chosen so a polling loop would - * run about 10 seconds before a Timeout is detected. For example: - * - * int Timeout = XUSBPS_TIMEOUT_COUNTER; - * while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - * XUSBPS_CMD_OFFSET) & - * XUSBPS_CMD_RST_MASK) && --Timeout) { - * ; - * } - * if (0 == Timeout) { - * return XST_FAILURE; - * } - * - */ -#define XUSBPS_TIMEOUT_COUNTER 1000000 - - -/** - * @name Endpoint Direction (bitmask) - * Definitions to be used with Endpoint related function that require a - * 'Direction' parameter. - * - * NOTE: - * The direction is always defined from the perspective of the HOST! This - * means that an IN endpoint on the controller is used for sending data while - * the OUT endpoint on the controller is used for receiving data. - * @{ - */ -#define XUSBPS_EP_DIRECTION_IN 0x01 /**< Endpoint direction IN. */ -#define XUSBPS_EP_DIRECTION_OUT 0x02 /**< Endpoint direction OUT. */ -/* @} */ - - -/** - * @name Endpoint Type - * Definitions to be used with Endpoint related functions that require a 'Type' - * parameter. - * @{ - */ -#define XUSBPS_EP_TYPE_NONE 0 /**< Endpoint is not used. */ -#define XUSBPS_EP_TYPE_CONTROL 1 /**< Endpoint for Control Transfers */ -#define XUSBPS_EP_TYPE_ISOCHRONOUS 2 /**< Endpoint for isochronous data */ -#define XUSBPS_EP_TYPE_BULK 3 /**< Endpoint for BULK Transfers. */ -#define XUSBPS_EP_TYPE_INTERRUPT 4 /**< Endpoint for interrupt Transfers */ -/* @} */ - -/** - * Endpoint Max Packet Length in DeviceConfig is a coded value, ch9.6.6. - * - * @{ - */ -#define ENDPOINT_MAXP_LENGTH 0x400 -#define ENDPOINT_MAXP_MULT_MASK 0xC00 -#define ENDPOINT_MAXP_MULT_SHIFT 10 -/* @} */ - -/** - * @name Field names for status retrieval - * Definitions for the XUsbPs_GetStatus() function call 'StatusType' - * parameter. - * @{ - */ -#define XUSBPS_EP_STS_ADDRESS 1 /**< Address of controller. */ -#define XUSBPS_EP_STS_CONTROLLER_STATE 2 /**< Current controller state. */ -/* @} */ - - - -/** - * @name USB Default alternate setting - * - * @{ - */ -#define XUSBPS_DEFAULT_ALT_SETTING 0 /**< The default alternate setting is 0 */ -/* @} */ - -/** - * @name Endpoint event types - * Definitions that are used to identify events that occur on endpoints. Passed - * to the endpoint event handler functions registered with - * XUsbPs_EpSetHandler(). - * @{ - */ -#define XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED 0x01 - /**< Setup data has been received on the enpoint. */ -#define XUSBPS_EP_EVENT_DATA_RX 0x02 - /**< Data frame has been received on the endpoint. */ -#define XUSBPS_EP_EVENT_DATA_TX 0x03 - /**< Data frame has been sent on the endpoint. */ -/* @} */ - - -/* - * Maximum packet size for endpoint, 1024 - * @{ - */ -#define XUSBPS_MAX_PACKET_SIZE 1024 - /**< Maximum value can be put into the queue head */ -/* @} */ -/**************************** Type Definitions *******************************/ - -/****************************************************************************** - * This data type defines the callback function to be used for Endpoint - * handlers. - * - * @param CallBackRef is the Callback reference passed in by the upper - * layer when setting the handler, and is passed back to the upper - * layer when the handler is called. - * @param EpNum is the Number of the endpoint that caused the event. - * @param EventType is the type of the event that occured on the endpoint. - * @param Data is a pointer to user data pointer specified when callback - * was registered. - */ -typedef void (*XUsbPs_EpHandlerFunc)(void *CallBackRef, - u8 EpNum, u8 EventType, void *Data); - - -/****************************************************************************** - * This data type defines the callback function to be used for the general - * interrupt handler. - * - * @param CallBackRef is the Callback reference passed in by the upper - * layer when setting the handler, and is passed back to the upper - * layer when the handler is called. - * @param IrqMask is the Content of the interrupt status register. This - * value can be used by the callback function to distinguish the - * individual interrupt types. - */ -typedef void (*XUsbPs_IntrHandlerFunc)(void *CallBackRef, u32 IrqMask); - - -/******************************************************************************/ - -/* The following type definitions are used for referencing Queue Heads and - * Transfer Descriptors. The structures themselves are not used, however, the - * types are used in the API to avoid using (void *) pointers. - */ -typedef u8 XUsbPs_dQH[XUSBPS_dQH_ALIGN]; -typedef u8 XUsbPs_dTD[XUSBPS_dTD_ALIGN]; - - -/** - * The following data structures are used internally by the L0/L1 driver. - * Their contents MUST NOT be changed by the upper layers. - */ - -/** - * The following data structure represents OUT endpoint. - */ -typedef struct { - XUsbPs_dQH *dQH; - /**< Pointer to the Queue Head structure of the endpoint. */ - - XUsbPs_dTD *dTDs; - /**< Pointer to the first dTD of the dTD list for this - * endpoint. */ - - XUsbPs_dTD *dTDCurr; - /**< Buffer to the currently processed descriptor. */ - - u8 *dTDBufs; - /**< Pointer to the first buffer of the buffer list for this - * endpoint. */ - - XUsbPs_EpHandlerFunc HandlerFunc; - /**< Handler function for this endpoint. */ - void *HandlerRef; - /**< User data reference for the handler. */ -} XUsbPs_EpOut; - - -/** - * The following data structure represents IN endpoint. - */ -typedef struct { - XUsbPs_dQH *dQH; - /**< Pointer to the Queue Head structure of the endpoint. */ - - XUsbPs_dTD *dTDs; - /**< List of pointers to the Transfer Descriptors of the - * endpoint. */ - - XUsbPs_dTD *dTDHead; - /**< Buffer to the next available descriptor in the list. */ - - XUsbPs_dTD *dTDTail; - /**< Buffer to the last unsent descriptor in the list*/ - - XUsbPs_EpHandlerFunc HandlerFunc; - /**< Handler function for this endpoint. */ - void *HandlerRef; - /**< User data reference for the handler. */ -} XUsbPs_EpIn; - - -/** - * The following data structure represents an endpoint used internally - * by the L0/L1 driver. - */ -typedef struct { - /* Each endpoint has an OUT and an IN component. - */ - XUsbPs_EpOut Out; /**< OUT endpoint structure */ - XUsbPs_EpIn In; /**< IN endpoint structure */ -} XUsbPs_Endpoint; - - - -/** - * The following structure is used by the user to receive Setup Data from an - * endpoint. Using this structure simplifies the process of interpreting the - * setup data in the core's data fields. - * - * The naming scheme for the members of this structure is different from the - * naming scheme found elsewhere in the code. The members of this structure are - * defined in the Chapter 9 USB reference guide. Using this naming scheme makes - * it easier for people familiar with the standard to read the code. - */ -typedef struct { - u8 bmRequestType; /**< bmRequestType in setup data */ - u8 bRequest; /**< bRequest in setup data */ - u16 wValue; /**< wValue in setup data */ - u16 wIndex; /**< wIndex in setup data */ - u16 wLength; /**< wLength in setup data */ -} -XUsbPs_SetupData; - - -/** - * Data structures used to configure endpoints. - */ -typedef struct { - u32 Type; - /**< Endpoint type: - - XUSBPS_EP_TYPE_CONTROL - - XUSBPS_EP_TYPE_ISOCHRONOUS - - XUSBPS_EP_TYPE_BULK - - XUSBPS_EP_TYPE_INTERRUPT */ - - u32 NumBufs; - /**< Number of buffers to be handled by this endpoint. */ - u32 BufSize; - /**< Buffer size. Only relevant for OUT (receive) Endpoints. */ - - u16 MaxPacketSize; - /**< Maximum packet size for this endpoint. This number will - * define the maximum number of bytes sent on the wire per - * transaction. Range: 0..1024 */ -} XUsbPs_EpSetup; - - -/** - * Endpoint configuration structure. - */ -typedef struct { - XUsbPs_EpSetup Out; /**< OUT component of endpoint. */ - XUsbPs_EpSetup In; /**< IN component of endpoint. */ -} XUsbPs_EpConfig; - - -/** - * The XUsbPs_DeviceConfig structure contains the configuration information to - * configure the USB controller for DEVICE mode. This data structure is used - * with the XUsbPs_ConfigureDevice() function call. - */ -typedef struct { - u8 NumEndpoints; /**< Number of Endpoints for the controller. - This number depends on the runtime - configuration of driver. The driver may - configure fewer endpoints than are available - in the core. */ - - XUsbPs_EpConfig EpCfg[XUSBPS_MAX_ENDPOINTS]; - /**< List of endpoint configurations. */ - - u32 DMAMemVirt; /**< Virtual base address of DMAable memory - allocated for the driver. */ - - u32 DMAMemPhys; /**< Physical base address of DMAable memory - allocated for the driver. */ - - /* The following members are used internally by the L0/L1 driver. They - * MUST NOT be accesses and/or modified in any way by the upper layers. - * - * The reason for having these members is that we generally try to - * avoid allocating memory in the L0/L1 driver as we want to be OS - * independent. In order to avoid allocating memory for this data - * structure wihin L0/L1 we put it into the XUsbPs_DeviceConfig - * structure which is allocated by the caller. - */ - XUsbPs_Endpoint Ep[XUSBPS_MAX_ENDPOINTS]; - /**< List of endpoint metadata structures. */ - - u32 PhysAligned; /**< 64 byte aligned base address of the DMA - memory block. Will be computed and set by - the L0/L1 driver. */ -} XUsbPs_DeviceConfig; - - -/** - * The XUsbPs_Config structure contains configuration information for the USB - * controller. - * - * This structure only contains the basic configuration for the controller. The - * caller also needs to initialize the controller for the DEVICE mode - * using the XUsbPs_DeviceConfig data structures with the - * XUsbPs_ConfigureDevice() function call - */ -typedef struct { - u16 DeviceID; /**< Unique ID of controller. */ - u32 BaseAddress; /**< Core register base address. */ -} XUsbPs_Config; - - -/** - * The XUsbPs driver instance data. The user is required to allocate a - * variable of this type for every USB controller in the system. A pointer to a - * variable of this type is then passed to the driver API functions. - */ -typedef struct { - XUsbPs_Config Config; /**< Configuration structure */ - - int CurrentAltSetting; /**< Current alternative setting of interface */ - - void *UserDataPtr; /**< Data pointer to be used by upper layers to - store application dependent data structures. - The upper layers are responsible to allocated - and free the memory. The driver will not - mofidy this data pointer. */ - - /** - * The following structures hold the configuration for DEVICE mode - * of the controller. They are initialized using the - * XUsbPs_ConfigureDevice() function call. - */ - XUsbPs_DeviceConfig DeviceConfig; - /**< Configuration for the DEVICE mode. */ - - XUsbPs_IntrHandlerFunc HandlerFunc; - /**< Handler function for the controller. */ - void *HandlerRef; - /**< User data reference for the handler. */ - u32 HandlerMask; - /**< User interrupt mask. Defines which interrupts will cause - * the callback to be called. */ -} XUsbPs; - - -/***************** Macros (Inline Functions) Definitions *********************/ - -/****************************************************************************** - * - * USB CONTROLLER RELATED MACROS - * - ******************************************************************************/ -/*****************************************************************************/ -/** - * This macro returns the current frame number. - * - * @param InstancePtr is a pointer to the XUsbPs instance of the - * controller. - * - * @return The current frame number. - * - * @note C-style signature: - * u32 XUsbPs_GetFrameNum(const XUsbPs *InstancePtr) - * - ******************************************************************************/ -#define XUsbPs_GetFrameNum(InstancePtr) \ - XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, XUSBPS_FRAME_OFFSET) - - -/*****************************************************************************/ -/** - * This macro starts the USB engine. - * - * @param InstancePtr is a pointer to the XUsbPs instance of the - * controller. - * - * @note C-style signature: - * void XUsbPs_Start(XUsbPs *InstancePtr) - * - ******************************************************************************/ -#define XUsbPs_Start(InstancePtr) \ - XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK) - - -/*****************************************************************************/ -/** - * This macro stops the USB engine. - * - * @param InstancePtr is a pointer to the XUsbPs instance of the - * controller. - * - * @note C-style signature: - * void XUsbPs_Stop(XUsbPs *InstancePtr) - * - ******************************************************************************/ -#define XUsbPs_Stop(InstancePtr) \ - XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK) - - -/*****************************************************************************/ -/** - * This macro forces the USB engine to be in Full Speed (FS) mode. - * - * @param InstancePtr is a pointer to the XUsbPs instance of the - * controller. - * - * @note C-style signature: - * void XUsbPs_ForceFS(XUsbPs *InstancePtr) - * - ******************************************************************************/ -#define XUsbPs_ForceFS(InstancePtr) \ - XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \ - XUSBPS_PORTSCR_PFSC_MASK) - - -/*****************************************************************************/ -/** - * This macro starts the USB Timer 0, with repeat option for period of - * one second. - * - * @param InstancePtr is a pointer to XUsbPs instance of the controller. - * @param Interval is the interval for Timer0 to generate an interrupt - * - * @note C-style signature: - * void XUsbPs_StartTimer0(XUsbPs *InstancePtr, u32 Interval) - * - ******************************************************************************/ -#define XUsbPs_StartTimer0(InstancePtr, Interval) \ -{ \ - XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \ - XUSBPS_TIMER0_LD_OFFSET, (Interval)); \ - XUsbPs_SetBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \ - XUSBPS_TIMER_RUN_MASK | \ - XUSBPS_TIMER_RESET_MASK | \ - XUSBPS_TIMER_REPEAT_MASK); \ -} \ - - -/*****************************************************************************/ -/** -* This macro stops Timer 0. -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* -* @note C-style signature: -* void XUsbPs_StopTimer0(XUsbPs *InstancePtr) -* -******************************************************************************/ -#define XUsbPs_StopTimer0(InstancePtr) \ - XUsbPs_ClrBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \ - XUSBPS_TIMER_RUN_MASK) - - -/*****************************************************************************/ -/** -* This macro reads Timer 0. -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* -* @note C-style signature: -* void XUsbPs_ReadTimer0(XUsbPs *InstancePtr) -* -******************************************************************************/ -#define XUsbPs_ReadTimer0(InstancePtr) \ - XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ - XUSBPS_TIMER0_CTL_OFFSET) & \ - XUSBPS_TIMER_COUNTER_MASK - - -/*****************************************************************************/ -/** -* This macro force remote wakeup on host -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* -* @note C-style signature: -* void XUsbPs_RemoteWakeup(XUsbPs *InstancePtr) -* -******************************************************************************/ -#define XUsbPs_RemoteWakeup(InstancePtr) \ - XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \ - XUSBPS_PORTSCR_FPR_MASK) - - -/****************************************************************************** - * - * ENDPOINT RELATED MACROS - * - ******************************************************************************/ -/*****************************************************************************/ -/** -* This macro enables the given endpoint for the given direction. -* -* @param InstancePtr is a pointer to the XUsbPs instance of the -* controller. -* @param EpNum is number of the endpoint to enable. -* @param Dir is direction of the endpoint (bitfield): -* - XUSBPS_EP_DIRECTION_OUT -* - XUSBPS_EP_DIRECTION_IN -* -* @note C-style signature: -* void XUsbPs_EpEnable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir) -* -******************************************************************************/ -#define XUsbPs_EpEnable(InstancePtr, EpNum, Dir) \ - XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \ - ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \ - ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0)) - - -/*****************************************************************************/ -/** -* This macro disables the given endpoint for the given direction. -* -* @param InstancePtr is a pointer to the XUsbPs instance of the -* controller. -* @param EpNum is the number of the endpoint to disable. -* @param Dir is the direction of the endpoint (bitfield): -* - XUSBPS_EP_DIRECTION_OUT -* - XUSBPS_EP_DIRECTION_IN -* -* @note C-style signature: -* void XUsbPs_EpDisable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir) -* -******************************************************************************/ -#define XUsbPs_EpDisable(InstancePtr, EpNum, Dir) \ - XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \ - ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \ - ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0)) - - -/*****************************************************************************/ -/** -* This macro stalls the given endpoint for the given direction, and flush -* the buffers. -* -* @param InstancePtr is a pointer to the XUsbPs instance of the -* controller. -* @param EpNum is number of the endpoint to stall. -* @param Dir is the direction of the endpoint (bitfield): -* - XUSBPS_EP_DIRECTION_OUT -* - XUSBPS_EP_DIRECTION_IN -* -* @note C-style signature: -* void XUsbPs_EpStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir) -* -******************************************************************************/ -#define XUsbPs_EpStall(InstancePtr, EpNum, Dir) \ - XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \ - ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \ - ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0)) - - -/*****************************************************************************/ -/** -* This macro unstalls the given endpoint for the given direction. -* -* @param InstancePtr is a pointer to the XUsbPs instance of the -* controller. -* @param EpNum is the Number of the endpoint to unstall. -* @param Dir is the Direction of the endpoint (bitfield): -* - XUSBPS_EP_DIRECTION_OUT -* - XUSBPS_EP_DIRECTION_IN -* -* @note C-style signature: -* void XUsbPs_EpUnStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir) -* -******************************************************************************/ -#define XUsbPs_EpUnStall(InstancePtr, EpNum, Dir) \ - XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \ - ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \ - ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0)) - - -/*****************************************************************************/ -/** -* This macro flush an endpoint upon interface disable -* -* @param InstancePtr is a pointer to the XUsbPs instance of the -* controller. -* @param EpNum is the number of the endpoint to flush. -* @param Dir is the direction of the endpoint (bitfield): -* - XUSBPS_EP_DIRECTION_OUT -* - XUSBPS_EP_DIRECTION_IN -* -* @note C-style signature: -* void XUsbPs_EpFlush(XUsbPs *InstancePtr, u8 EpNum, u8 Dir) -* -******************************************************************************/ -#define XUsbPs_EpFlush(InstancePtr, EpNum, Dir) \ - XUsbPs_SetBits(InstancePtr, XUSBPS_EPFLUSH_OFFSET, \ - EpNum << ((Dir) & XUSBPS_EP_DIRECTION_OUT ? \ - XUSBPS_EPFLUSH_RX_SHIFT:XUSBPS_EPFLUSH_TX_SHIFT)) \ - -/*****************************************************************************/ -/** -* This macro enables the interrupts defined by the bit mask. -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* @param IntrMask is the Bit mask of interrupts to be enabled. -* -* @note C-style signature: -* void XUsbPs_IntrEnable(XUsbPs *InstancePtr, u32 IntrMask) -* -******************************************************************************/ -#define XUsbPs_IntrEnable(InstancePtr, IntrMask) \ - XUsbPs_SetBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask) - - -/*****************************************************************************/ -/** -* This function disables the interrupts defined by the bit mask. -* -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* @param IntrMask is a Bit mask of interrupts to be disabled. -* -* @note C-style signature: -* void XUsbPs_IntrDisable(XUsbPs *InstancePtr, u32 IntrMask) -* -******************************************************************************/ -#define XUsbPs_IntrDisable(InstancePtr, IntrMask) \ - XUsbPs_ClrBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask) - - -/*****************************************************************************/ -/** -* This macro enables the endpoint NAK interrupts defined by the bit mask. -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be -* enabled. -* @note C-style signature: -* void XUsbPs_NakIntrEnable(XUsbPs *InstancePtr, u32 NakIntrMask) -* -******************************************************************************/ -#define XUsbPs_NakIntrEnable(InstancePtr, NakIntrMask) \ - XUsbPs_SetBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask) - - -/*****************************************************************************/ -/** -* This macro disables the endpoint NAK interrupts defined by the bit mask. -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* @param NakIntrMask is a Bit mask of endpoint NAK interrupts to be -* disabled. -* -* @note -* C-style signature: -* void XUsbPs_NakIntrDisable(XUsbPs *InstancePtr, u32 NakIntrMask) -* -******************************************************************************/ -#define XUsbPs_NakIntrDisable(InstancePtr, NakIntrMask) \ - XUsbPs_ClrBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask) - - -/*****************************************************************************/ -/** -* This function clears the endpoint NAK interrupts status defined by the -* bit mask. -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be cleared. -* -* @note C-style signature: -* void XUsbPs_NakIntrClear(XUsbPs *InstancePtr, u32 NakIntrMask) -* -******************************************************************************/ -#define XUsbPs_NakIntrClear(InstancePtr, NakIntrMask) \ - XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \ - XUSBPS_EPNAKISR_OFFSET, NakIntrMask) - - - -/*****************************************************************************/ -/** -* This macro sets the Interrupt Threshold value in the control register -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* @param Threshold is the Interrupt threshold to be set. -* Allowed values: -* - XUSBPS_CMD_ITHRESHOLD_0 - Immediate interrupt -* - XUSBPS_CMD_ITHRESHOLD_1 - 1 Frame -* - XUSBPS_CMD_ITHRESHOLD_2 - 2 Frames -* - XUSBPS_CMD_ITHRESHOLD_4 - 4 Frames -* - XUSBPS_CMD_ITHRESHOLD_8 - 8 Frames -* - XUSBPS_CMD_ITHRESHOLD_16 - 16 Frames -* - XUSBPS_CMD_ITHRESHOLD_32 - 32 Frames -* - XUSBPS_CMD_ITHRESHOLD_64 - 64 Frames -* -* @note -* C-style signature: -* void XUsbPs_SetIntrThreshold(XUsbPs *InstancePtr, u8 Threshold) -* -******************************************************************************/ -#define XUsbPs_SetIntrThreshold(InstancePtr, Threshold) \ - XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \ - XUSBPS_CMD_OFFSET, (Threshold))\ - - -/*****************************************************************************/ -/** -* This macro sets the Tripwire bit in the USB command register. -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* -* @note C-style signature: -* void XUsbPs_SetTripwire(XUsbPs *InstancePtr) -* -******************************************************************************/ -#define XUsbPs_SetTripwire(InstancePtr) \ - XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, \ - XUSBPS_CMD_ATDTW_MASK) - - -/*****************************************************************************/ -/** -* This macro clears the Tripwire bit in the USB command register. -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* -* @note C-style signature: -* void XUsbPs_ClrTripwire(XUsbPs *InstancePtr) -* -******************************************************************************/ -#define XUsbPs_ClrTripwire(InstancePtr) \ - XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, \ - XUSBPS_CMD_ATDTW_MASK) - - -/*****************************************************************************/ -/** -* This macro checks if the Tripwire bit in the USB command register is set. -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* -* @return -* - TRUE: The tripwire bit is still set. -* - FALSE: The tripwire bit has been cleared. -* -* @note C-style signature: -* int XUsbPs_TripwireIsSet(XUsbPs *InstancePtr) -* -******************************************************************************/ -#define XUsbPs_TripwireIsSet(InstancePtr) \ - (XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ - XUSBPS_CMD_OFFSET) & \ - XUSBPS_CMD_ATDTW_MASK ? TRUE : FALSE) - - -/****************************************************************************** -* -* GENERAL REGISTER / BIT MANIPULATION MACROS -* -******************************************************************************/ -/****************************************************************************/ -/** -* This macro sets the given bit mask in the register. -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* @param RegOffset is the register offset to be written. -* @param Bits is the Bits to be set in the register -* -* @return None. -* -* @note C-style signature: -* void XUsbPs_SetBits(u32 BaseAddress, u32 RegOffset, u32 Bits) -* -*****************************************************************************/ -#define XUsbPs_SetBits(InstancePtr, RegOffset, Bits) \ - XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \ - XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ - RegOffset) | (Bits)); - - -/****************************************************************************/ -/** -* -* This macro clears the given bits in the register. -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* @param RegOffset is the register offset to be written. -* @param Bits are the bits to be cleared in the register -* -* @return None. -* -* @note -* C-style signature: -* void XUsbPs_ClrBits(u32 BaseAddress, u32 RegOffset, u32 Bits) -* -*****************************************************************************/ -#define XUsbPs_ClrBits(InstancePtr, RegOffset, Bits) \ - XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \ - XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ - RegOffset) & ~(Bits)); - - -/************************** Function Prototypes ******************************/ - -/** - * Setup / Initialize functions. - * - * Implemented in file xusbps.c - */ -int XUsbPs_CfgInitialize(XUsbPs *InstancePtr, - const XUsbPs_Config *ConfigPtr, u32 BaseAddress); - -int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr, - const XUsbPs_DeviceConfig *CfgPtr); -u32 XUsbPs_DeviceMemRequired(const XUsbPs_DeviceConfig *CfgPtr); - -/** - * Common functions used for DEVICE/HOST mode. - */ -int XUsbPs_Reset(XUsbPs *InstancePtr); - -/** - * DEVICE mode specific functions. - */ -int XUsbPs_BusReset(XUsbPs *InstancePtr); -u32 XUsbPs_DeviceMemRequired(const XUsbPs_DeviceConfig *CfgPtr); -int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address); - - -/** - * Handling Suspend and Resume. - * - * Implemented in xusbps.c - */ -int XUsbPs_Suspend(const XUsbPs *InstancePtr); -int XUsbPs_Resume(const XUsbPs *InstancePtr); -int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr); - - -/* - * Functions for managing Endpoints / Transfers - * - * Implemented in file xusbps_endpoint.c - */ -int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum, - const u8 *BufferPtr, u32 BufferLen); -int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum, - u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle); -void XUsbPs_EpBufferRelease(u32 Handle); - -int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction, - XUsbPs_EpHandlerFunc CallBackFunc, - void *CallBackRef); -int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum, - XUsbPs_SetupData *SetupDataPtr); - -int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction); - -int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr, - int EpNum, unsigned short NewDirection, int DirectionChanged); - -/* - * Interrupt handling functions - * - * Implemented in file xusbps_intr.c - */ -void XUsbPs_IntrHandler(void *InstancePtr); - -int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr, - XUsbPs_IntrHandlerFunc CallBackFunc, - void *CallBackRef, u32 Mask); -/* - * Helper functions for static configuration. - * Implemented in xusbps_sinit.c - */ -XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceId); - -#ifdef __cplusplus -} -#endif - -#endif /* XUSBPS_H */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/xusbps_endpoint.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/xusbps_endpoint.c deleted file mode 100644 index 853e8907e63b74b04ba9e2383f7799c94d9b7b62..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/xusbps_endpoint.c +++ /dev/null @@ -1,1384 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/******************************************************************************/ -/** - * @file xusbps_endpoint.c - * - * Endpoint specific function implementations. - * - * @note None. - * - * <pre> - * MODIFICATION HISTORY: - * - * Ver Who Date Changes - * ----- ---- -------- -------------------------------------------------------- - * 1.00a jz 10/10/10 First release - * 1.03a nm 09/21/12 Fixed CR#678977. Added proper sequence for setup packet - * handling. - * 1.04a nm 11/02/12 Fixed CR#683931. Mult bits are set properly in dQH. - * </pre> - ******************************************************************************/ - -/***************************** Include Files **********************************/ - -#include <string.h> /* for bzero() */ -#include <stdio.h> - -#include "xusbps.h" -#include "xusbps_endpoint.h" - -/************************** Constant Definitions ******************************/ - -/**************************** Type Definitions ********************************/ - -/************************** Variable Definitions ******************************/ - -/************************** Function Prototypes ******************************/ - -static void XUsbPs_EpListInit(XUsbPs_DeviceConfig *DevCfgPtr); -static void XUsbPs_dQHInit(XUsbPs_DeviceConfig *DevCfgPtr); -static int XUsbPs_dTDInit(XUsbPs_DeviceConfig *DevCfgPtr); -static int XUsbPs_dTDAttachBuffer(XUsbPs_dTD *dTDPtr, - const u8 *BufferPtr, u32 BufferLen); - -static void XUsbPs_dQHSetMaxPacketLenISO(XUsbPs_dQH *dQHPtr, u32 Len); - -/* Functions to reconfigure endpoint upon host's set alternate interface - * request. - */ -static void XUsbPs_dQHReinitEp(XUsbPs_DeviceConfig *DevCfgPtr, - int EpNum, unsigned short NewDirection); -static int XUsbPs_dTDReinitEp(XUsbPs_DeviceConfig *DevCfgPtr, - int EpNum, unsigned short NewDirection); - -/******************************* Functions ************************************/ - -/*****************************************************************************/ -/** - * - * This function configures the DEVICE side of the controller. The caller needs - * to pass in the desired configuration (e.g. number of endpoints) and a - * DMAable buffer that will hold the Queue Head List and the Transfer - * Descriptors. The required size for this buffer can be obtained by the caller - * using the: XUsbPs_DeviceMemRequired() macro. - * - * @param InstancePtr is a pointer to the XUsbPs instance of the - * controller. - * @param CfgPtr is a pointer to the configuration structure that contains - * the desired DEVICE side configuration. - * - * @return - * - XST_SUCCESS: The operation completed successfully. - * - XST_FAILURE: An error occured. - * - * @note - * The caller may configure the controller for both, DEVICE and - * HOST side. - * - ******************************************************************************/ -int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr, - const XUsbPs_DeviceConfig *CfgPtr) -{ - int Status; - u32 ModeValue = 0x0; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(CfgPtr != NULL); - - /* Copy the configuration data over into the local instance structure */ - InstancePtr->DeviceConfig = *CfgPtr; - - - /* Align the buffer to a 2048 byte (XUSBPS_dQH_BASE_ALIGN) boundary.*/ - InstancePtr->DeviceConfig.PhysAligned = - (InstancePtr->DeviceConfig.DMAMemPhys + - XUSBPS_dQH_BASE_ALIGN) & - ~(XUSBPS_dQH_BASE_ALIGN -1); - - - /* Clear out the buffer.*/ - memset((void *) InstancePtr->DeviceConfig.DMAMemPhys, 0, - XUsbPs_DeviceMemRequired(&InstancePtr->DeviceConfig)); - - /* Initialize the endpoint pointer list data structure. */ - XUsbPs_EpListInit(&InstancePtr->DeviceConfig); - - - /* Initialize the Queue Head structures in DMA memory. */ - XUsbPs_dQHInit(&InstancePtr->DeviceConfig); - - - /* Initialize the Transfer Descriptors in DMA memory.*/ - Status = XUsbPs_dTDInit(&InstancePtr->DeviceConfig); - if (XST_SUCCESS != Status) { - return XST_FAILURE; - } - - /* Changing the DEVICE mode requires a controller RESET. */ - if (XST_SUCCESS != XUsbPs_Reset(InstancePtr)) { - return XST_FAILURE; - } - - /* Set the Queue Head List address. */ - XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPLISTADDR_OFFSET, - InstancePtr->DeviceConfig.PhysAligned); - - /* Set the USB mode register to configure DEVICE mode. - * - * XUSBPS_MODE_SLOM_MASK note: - * Disable Setup Lockout. Setup Lockout is not required as we - * will be using the tripwire mechanism when handling setup - * packets. - */ - ModeValue = XUSBPS_MODE_CM_DEVICE_MASK | XUSBPS_MODE_SLOM_MASK; - - XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, - XUSBPS_MODE_OFFSET, ModeValue); - - XUsbPs_SetBits(InstancePtr, XUSBPS_OTGCSR_OFFSET, - XUSBPS_OTGSC_OT_MASK); - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* This function sends a given data buffer. -* -* @param InstancePtr is a pointer to XUsbPs instance of the controller. -* @param EpNum is the number of the endpoint to receive data from. -* @param BufferPtr is a pointer to the buffer to send. -* @param BufferLen is the Buffer length. -* -* @return -* - XST_SUCCESS: The operation completed successfully. -* - XST_FAILURE: An error occured. -* - XST_USB_BUF_TOO_BIG: Provided buffer is too big (>16kB). -* - XST_USB_NO_DESC_AVAILABLE: No TX descriptor is available. -* -******************************************************************************/ -int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum, - const u8 *BufferPtr, u32 BufferLen) -{ - int Status; - u32 Token; - XUsbPs_EpIn *Ep; - XUsbPs_dTD *DescPtr; - u32 Length; - u32 PipeEmpty = 1; - u32 Mask = 0x00010000; - u32 BitMask = Mask << EpNum; - u32 RegValue; - u32 Temp; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints); - - /* Locate the next available buffer in the ring. A buffer is available - * if its descriptor is not active. - */ - Ep = &InstancePtr->DeviceConfig.Ep[EpNum].In; - - Xil_DCacheFlushRange((unsigned int)BufferPtr, BufferLen); - - if(Ep->dTDTail != Ep->dTDHead) { - PipeEmpty = 0; - } - XUsbPs_dTDInvalidateCache(Ep->dTDHead); - - /* Tell the caller if we do not have any descriptors available. */ - if (XUsbPs_dTDIsActive(Ep->dTDHead)) { - return XST_USB_NO_DESC_AVAILABLE; - } - - /* Remember the current head. */ - DescPtr = Ep->dTDHead; - - do { - Length = (BufferLen > XUSBPS_dTD_BUF_MAX_SIZE) ? XUSBPS_dTD_BUF_MAX_SIZE : BufferLen; - /* Attach the provided buffer to the current descriptor.*/ - Status = XUsbPs_dTDAttachBuffer(Ep->dTDHead, BufferPtr, Length); - if (XST_SUCCESS != Status) { - return XST_FAILURE; - } - BufferLen -= Length; - BufferPtr += Length; - - XUsbPs_dTDSetActive(Ep->dTDHead); - if(BufferLen == 0) - XUsbPs_dTDSetIOC(Ep->dTDHead); - XUsbPs_dTDClrTerminate(Ep->dTDHead); - XUsbPs_dTDFlushCache(Ep->dTDHead); - - /* Advance the head descriptor pointer to the next descriptor. */ - Ep->dTDHead = XUsbPs_dTDGetNLP(Ep->dTDHead); - /* Terminate the next descriptor and flush the cache.*/ - XUsbPs_dTDInvalidateCache(Ep->dTDHead); - /* Tell the caller if we do not have any descriptors available. */ - if (XUsbPs_dTDIsActive(Ep->dTDHead)) { - return XST_USB_NO_DESC_AVAILABLE; - } - } while(BufferLen); - - XUsbPs_dTDSetTerminate(Ep->dTDHead); - XUsbPs_dTDFlushCache(Ep->dTDHead); - - if(!PipeEmpty) { - /* Read the endpoint prime register. */ - RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_EPPRIME_OFFSET); - if(RegValue & BitMask) { - return XST_SUCCESS; - } - - do { - RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET); - XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET, - RegValue | XUSBPS_CMD_ATDTW_MASK); - Temp = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_EPRDY_OFFSET) - & BitMask; - } while(!(XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET) & - XUSBPS_CMD_ATDTW_MASK)); - - RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET); - XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET, - RegValue & ~XUSBPS_CMD_ATDTW_MASK); - - if(Temp) { - return XST_SUCCESS; - } - } - - /* Check, if the DMA engine is still running. If it is running, we do - * not clear Queue Head fields. - * - * Same cache rule as for the Transfer Descriptor applies for the Queue - * Head. - */ - XUsbPs_dQHInvalidateCache(Ep->dQH); - /* Add the dTD to the dQH */ - XUsbPs_WritedQH(Ep->dQH, XUSBPS_dQHdTDNLP, DescPtr); - Token = XUsbPs_ReaddQH(Ep->dQH, XUSBPS_dQHdTDTOKEN); - Token &= ~(XUSBPS_dTDTOKEN_ACTIVE_MASK | XUSBPS_dTDTOKEN_HALT_MASK); - XUsbPs_WritedQH(Ep->dQH, XUSBPS_dQHdTDTOKEN, Token); - - XUsbPs_dQHFlushCache(Ep->dQH); - - Status = XUsbPs_EpPrime(InstancePtr, EpNum, XUSBPS_EP_DIRECTION_IN); - - return Status; -} - -/*****************************************************************************/ -/** - * This function receives a data buffer from the endpoint of the given endpoint - * number. - * - * @param InstancePtr is a pointer to the XUsbPs instance of the - * controller. - * @param EpNum is the number of the endpoint to receive data from. - * @param BufferPtr (OUT param) is a pointer to the buffer pointer to hold - * the reference of the data buffer. - * @param BufferLenPtr (OUT param) is a pointer to the integer that will - * hold the buffer length. - * @param Handle is the opaque handle to be used when the buffer is - * released. - * - * @return - * - XST_SUCCESS: The operation completed successfully. - * - XST_FAILURE: An error occured. - * - XST_USB_NO_BUF: No buffer available. - * - * @note - * After handling the data in the buffer, the user MUST release - * the buffer using the Handle by calling the - * XUsbPs_EpBufferRelease() function. - * - ******************************************************************************/ -int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum, - u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle) -{ - XUsbPs_EpOut *Ep; - XUsbPs_EpSetup *EpSetup; - u32 length = 0; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(BufferPtr != NULL); - Xil_AssertNonvoid(BufferLenPtr != NULL); - Xil_AssertNonvoid(Handle != NULL); - Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints); - - /* Locate the next available buffer in the ring. A buffer is available - * if its descriptor is not active. - */ - Ep = &InstancePtr->DeviceConfig.Ep[EpNum].Out; - - XUsbPs_dTDInvalidateCache(Ep->dTDCurr); - - if (XUsbPs_dTDIsActive(Ep->dTDCurr)) { - return XST_USB_NO_BUF; - } - - /* The buffer is not active which means that it has been processed by - * the DMA engine and contains valid data. - */ - EpSetup = &InstancePtr->DeviceConfig.EpCfg[EpNum].Out; - - - /* Use the buffer pointer stored in the "user data" field of the - * Transfer Descriptor. - */ - *BufferPtr = (u8 *) XUsbPs_ReaddTD(Ep->dTDCurr, - XUSBPS_dTDUSERDATA); - - length = EpSetup->BufSize - - XUsbPs_dTDGetTransferLen(Ep->dTDCurr); - - if(length > 0) { - *BufferLenPtr = length; - }else { - *BufferLenPtr = 0; - } - - *Handle = (u32) Ep->dTDCurr; - - - /* Reset the descriptor's BufferPointer0 and Transfer Length fields to - * their original value. Note that we can not yet re-activate the - * descriptor as the caller will be using the attached buffer. Once the - * caller releases the buffer by calling XUsbPs_EpBufferRelease(), we - * can re-activate the descriptor. - */ - XUsbPs_WritedTD(Ep->dTDCurr, XUSBPS_dTDBPTR0, *BufferPtr); - XUsbPs_dTDSetTransferLen(Ep->dTDCurr, EpSetup->BufSize); - - XUsbPs_dTDFlushCache(Ep->dTDCurr); - - return XST_SUCCESS; -} - - -/*****************************************************************************/ -/** -* This function returns a previously received data buffer to the driver. -* -* @param Handle is a pointer to the buffer that is returned. -* -* @return None. -* -******************************************************************************/ -void XUsbPs_EpBufferRelease(u32 Handle) -{ - XUsbPs_dTD *dTDPtr; - - /* Perform sanity check on Handle.*/ - Xil_AssertVoid((0 != Handle) && (0 == (Handle % XUSBPS_dTD_ALIGN))); - - /* Activate the descriptor and clear the Terminate bit. Make sure to do - * the proper cache handling. - */ - dTDPtr = (XUsbPs_dTD *) Handle; - - XUsbPs_dTDInvalidateCache(dTDPtr); - - XUsbPs_dTDClrTerminate(dTDPtr); - XUsbPs_dTDSetActive(dTDPtr); - XUsbPs_dTDSetIOC(dTDPtr); - - XUsbPs_dTDFlushCache(dTDPtr); - -} - - -/*****************************************************************************/ -/** - * This function sets the handler for endpoint events. - * - * @param InstancePtr is a pointer to the XUsbPs instance of the - * controller. - * @param EpNum is the number of the endpoint to receive data from. - * @param Direction is the direction of the endpoint (bitfield): - * - XUSBPS_EP_DIRECTION_OUT - * - XUSBPS_EP_DIRECTION_IN - * @param CallBackFunc is the Handler callback function. - * Can be NULL if the user wants to disable the handler entry. - * @param CallBackRef is the user definable data pointer that will be - * passed back if the handler is called. May be NULL. - * - * @return - * - XST_SUCCESS: The operation completed successfully. - * - XST_FAILURE: An error occured. - * - XST_INVALID_PARAM: Invalid parameter passed. - * - * @note - * The user can disable a handler by setting the callback function - * pointer to NULL. - * - ******************************************************************************/ -int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction, - XUsbPs_EpHandlerFunc CallBackFunc, - void *CallBackRef) -{ - XUsbPs_Endpoint *Ep; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(CallBackFunc != NULL); - Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints); - - Ep = &InstancePtr->DeviceConfig.Ep[EpNum]; - - if(Direction & XUSBPS_EP_DIRECTION_OUT) { - Ep->Out.HandlerFunc = CallBackFunc; - Ep->Out.HandlerRef = CallBackRef; - } - - if(Direction & XUSBPS_EP_DIRECTION_IN) { - Ep->In.HandlerFunc = CallBackFunc; - Ep->In.HandlerRef = CallBackRef; - } - - return XST_SUCCESS; -} - - -/*****************************************************************************/ -/** -* This function primes an endpoint. -* -* @param InstancePtr is pointer to the XUsbPs instance. -* @param EpNum is the number of the endpoint to receive data from. -* @param Direction is the direction of the endpoint (bitfield): -* - XUSBPS_EP_DIRECTION_OUT -* - XUSBPS_EP_DIRECTION_IN -* -* @return -* - XST_SUCCESS: The operation completed successfully. -* - XST_FAILURE: An error occured. -* - XST_INVALID_PARAM: Invalid parameter passed. -* -* @note None. -* -******************************************************************************/ -int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction) -{ - u32 Mask; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints); - - /* Get the right bit mask for the endpoint direction. */ - switch (Direction) { - - case XUSBPS_EP_DIRECTION_OUT: - Mask = 0x00000001; - break; - - case XUSBPS_EP_DIRECTION_IN: - Mask = 0x00010000; - break; - - default: - return XST_INVALID_PARAM; - } - - /* Write the endpoint prime register. */ - XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPPRIME_OFFSET, Mask << EpNum); - - return XST_SUCCESS; -} - - -/*****************************************************************************/ -/** -* This function extracts the Setup Data from a given endpoint. -* -* @param InstancePtr is a pointer to the XUsbPs instance of the -* controller. -* @param EpNum is the number of the endpoint to receive data from. -* @param SetupDataPtr is a pointer to the setup data structure to be -* filled. -* -* @return -* - XST_SUCCESS: The operation completed successfully. -* - XST_FAILURE: An error occured. -* -* @note None. -******************************************************************************/ -int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum, - XUsbPs_SetupData *SetupDataPtr) -{ - XUsbPs_EpOut *Ep; - - u32 Data[2]; - u8 *p; - - int Timeout; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(SetupDataPtr != NULL); - Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints); - - Ep = &InstancePtr->DeviceConfig.Ep[EpNum].Out; - - - /* Get the data from the Queue Heads Setup buffer into local variables - * so we can extract the setup data values. - */ - do { - /* Arm the tripwire. The tripwire will tell us if a new setup - * packet arrived (in which case the tripwire bit will be - * cleared) while we were reading the buffer. If a new setup - * packet arrived the buffer is corrupted and we continue - * reading. - */ - XUsbPs_SetTripwire(InstancePtr); - - XUsbPs_dQHInvalidateCache(Ep->dQH); - - Data[0] = XUsbPs_ReaddQH(Ep->dQH, XUSBPS_dQHSUB0); - Data[1] = XUsbPs_ReaddQH(Ep->dQH, XUSBPS_dQHSUB1); - } while (FALSE == XUsbPs_TripwireIsSet(InstancePtr)); - - /* Clear the pending endpoint setup stat bit. - */ - XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPSTAT_OFFSET, 1 << EpNum); - - /* Clear the Tripwire bit and continue. - */ - XUsbPs_ClrTripwire(InstancePtr); - - - /* Data in the setup buffer is being converted by the core to big - * endian format. We have to take care of proper byte swapping when - * reading the setup data values. - * - * Need to check if there is a smarter way to do this and take the - * processor/memory-controller endianess into account? - */ - p = (u8 *) Data; - - SetupDataPtr->bmRequestType = p[0]; - SetupDataPtr->bRequest = p[1]; - SetupDataPtr->wValue = (p[3] << 8) | p[2]; - SetupDataPtr->wIndex = (p[5] << 8) | p[4]; - SetupDataPtr->wLength = (p[7] << 8) | p[6]; - - /* Before we leave we need to make sure that the endpoint setup bit has - * cleared. It needs to be 0 before the endpoint can be re-primed. - * - * Note: According to the documentation this endpoint setup bit should - * clear within 1-2us after it has been written above. This means that - * we should never catch it being 1 here. However, we still need to - * poll it to make sure. Just in case, we use a counter 'Timeout' so we - * won't hang here if the bit is stuck for some reason. - */ - Timeout = XUSBPS_TIMEOUT_COUNTER; - while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPSTAT_OFFSET) & - (1 << EpNum)) && --Timeout) { - /* NOP */ - } - if (0 == Timeout) { - return XST_FAILURE; - } - - return XST_SUCCESS; -} - - -/*****************************************************************************/ -/** -* -* This function initializes the endpoint pointer data structure. -* -* The function sets up the local data structure with the aligned addresses for -* the Queue Head and Transfer Descriptors. -* -* @param DevCfgPtr is pointer to the XUsbPs DEVICE configuration -* structure. -* -* @return none -* -* @note -* Endpoints of type XUSBPS_EP_TYPE_NONE are not used in the -* system. Therefore no memory is reserved for them. -* -******************************************************************************/ -static void XUsbPs_EpListInit(XUsbPs_DeviceConfig *DevCfgPtr) -{ - int EpNum; - u8 *p; - - XUsbPs_Endpoint *Ep; - XUsbPs_EpConfig *EpCfg; - - /* Set up the XUsbPs_Endpoint array. This array is used to define the - * location of the Queue Head list and the Transfer Descriptors in the - * block of DMA memory that has been passed into the driver. - * - * 'p' is used to set the pointers in the local data structure. - * Initially 'p' is pointed to the beginning of the DMAable memory - * block. As pointers are assigned, 'p' is incremented by the size of - * the respective object. - */ - Ep = DevCfgPtr->Ep; - EpCfg = DevCfgPtr->EpCfg; - - /* Start off with 'p' pointing to the (aligned) beginning of the DMA - * buffer. - */ - p = (u8 *) DevCfgPtr->PhysAligned; - - - /* Initialize the Queue Head pointer list. - * - * Each endpoint has two Queue Heads. One for the OUT direction and one - * for the IN direction. An OUT Queue Head is always followed by an IN - * Queue Head. - * - * Queue Head alignment is XUSBPS_dQH_ALIGN. - * - * Note that we have to reserve space here for unused endpoints. - */ - for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) { - /* OUT Queue Head */ - Ep[EpNum].Out.dQH = (XUsbPs_dQH *) p; - p += XUSBPS_dQH_ALIGN; - - /* IN Queue Head */ - Ep[EpNum].In.dQH = (XUsbPs_dQH *) p; - p += XUSBPS_dQH_ALIGN; - } - - - /* 'p' now points to the first address after the Queue Head list. The - * Transfer Descriptors start here. - * - * Each endpoint has a variable number of Transfer Descriptors - * depending on user configuration. - * - * Transfer Descriptor alignment is XUSBPS_dTD_ALIGN. - */ - for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) { - /* OUT Descriptors. - */ - if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) { - Ep[EpNum].Out.dTDs = (XUsbPs_dTD *) p; - Ep[EpNum].Out.dTDCurr = (XUsbPs_dTD *) p; - p += XUSBPS_dTD_ALIGN * EpCfg[EpNum].Out.NumBufs; - } - - /* IN Descriptors. - */ - if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].In.Type) { - Ep[EpNum].In.dTDs = (XUsbPs_dTD *) p; - Ep[EpNum].In.dTDHead = (XUsbPs_dTD *) p; - Ep[EpNum].In.dTDTail = (XUsbPs_dTD *) p; - p += XUSBPS_dTD_ALIGN * EpCfg[EpNum].In.NumBufs; - } - } - - - /* 'p' now points to the first address after the Transfer Descriptors. - * The data buffers for the OUT Transfer Desciptors start here. - * - * Note that IN (TX) Transfer Descriptors are not assigned buffers at - * this point. Buffers will be assigned when the user calls the send() - * function. - */ - for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) { - - if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) { - /* If BufSize for this endpoint is set to 0 it means - * that we do not need to attach a buffer to this - * descriptor. We also initialize it's buffer pointer - * to NULL. - */ - if (0 == EpCfg[EpNum].Out.BufSize) { - Ep[EpNum].Out.dTDBufs = NULL; - continue; - } - - Ep[EpNum].Out.dTDBufs = p; - p += EpCfg[EpNum].Out.BufSize * EpCfg[EpNum].Out.NumBufs; - } - } - - - /* Initialize the endpoint event handlers to NULL. - */ - for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) { - Ep[EpNum].Out.HandlerFunc = NULL; - Ep[EpNum].In.HandlerFunc = NULL; - } -} - - -/*****************************************************************************/ -/** -* -* This function initializes the Queue Head List in memory. -* -* @param DevCfgPtr is a pointer to the XUsbPs DEVICE configuration -* structure. -* -* @return None -* -* @note None. -* -******************************************************************************/ -static void XUsbPs_dQHInit(XUsbPs_DeviceConfig *DevCfgPtr) -{ - int EpNum; - - XUsbPs_Endpoint *Ep; - XUsbPs_EpConfig *EpCfg; - - /* Setup pointers for simpler access. */ - Ep = DevCfgPtr->Ep; - EpCfg = DevCfgPtr->EpCfg; - - - /* Go through the list of Queue Head entries and: - * - * - Set Transfer Descriptor addresses - * - Set Maximum Packet Size - * - Disable Zero Length Termination (ZLT) for non-isochronous transfers - * - Enable Interrupt On Setup (IOS) - * - */ - for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) { - - /* OUT Queue Heads.*/ - if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) { - XUsbPs_WritedQH(Ep[EpNum].Out.dQH, - XUSBPS_dQHCPTR, Ep[EpNum].Out.dTDs); - - /* For isochronous, ep max packet size translates to different - * values in queue head than other types. - * Also enable ZLT for isochronous. - */ - if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].Out.Type) { - XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].Out.dQH, - EpCfg[EpNum].Out.MaxPacketSize); - XUsbPs_dQHEnableZLT(Ep[EpNum].Out.dQH); - }else { - XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].Out.dQH, - EpCfg[EpNum].Out.MaxPacketSize); - XUsbPs_dQHDisableZLT(Ep[EpNum].Out.dQH); - } - - /* Only control OUT needs this */ - if(XUSBPS_EP_TYPE_CONTROL == EpCfg[EpNum].Out.Type) { - XUsbPs_dQHSetIOS(Ep[EpNum].Out.dQH); - } - - /* Set up the overlay next dTD pointer. */ - XUsbPs_WritedQH(Ep[EpNum].Out.dQH, - XUSBPS_dQHdTDNLP, Ep[EpNum].Out.dTDs); - - XUsbPs_dQHFlushCache(Ep[EpNum].Out.dQH); - } - - - /* IN Queue Heads. */ - if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].In.Type) { - XUsbPs_WritedQH(Ep[EpNum].In.dQH, - XUSBPS_dQHCPTR, Ep[EpNum].In.dTDs); - - - /* Isochronous ep packet size can be larger than 1024.*/ - if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].In.Type) { - XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].In.dQH, - EpCfg[EpNum].In.MaxPacketSize); - XUsbPs_dQHEnableZLT(Ep[EpNum].In.dQH); - }else { - XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].In.dQH, - EpCfg[EpNum].In.MaxPacketSize); - XUsbPs_dQHDisableZLT(Ep[EpNum].In.dQH); - } - - XUsbPs_dQHFlushCache(Ep[EpNum].In.dQH); - } - } -} - - -/*****************************************************************************/ -/** - * - * This function initializes the Transfer Descriptors lists in memory. - * - * @param DevCfgPtr is a pointer to the XUsbPs DEVICE configuration - * structure. - * - * @return - * - XST_SUCCESS: The operation completed successfully. - * - XST_FAILURE: An error occured. - * - ******************************************************************************/ -static int XUsbPs_dTDInit(XUsbPs_DeviceConfig *DevCfgPtr) -{ - int EpNum; - - XUsbPs_Endpoint *Ep; - XUsbPs_EpConfig *EpCfg; - - /* Setup pointers for simpler access. */ - Ep = DevCfgPtr->Ep; - EpCfg = DevCfgPtr->EpCfg; - - - /* Walk through the list of endpoints and initialize their Transfer - * Descriptors. - */ - for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) { - int Td; - int NumdTD; - - XUsbPs_EpOut *Out = &Ep[EpNum].Out; - XUsbPs_EpIn *In = &Ep[EpNum].In; - - - /* OUT Descriptors - * =============== - * - * + Set the next link pointer - * + Set the interrupt complete and the active bit - * + Attach the buffer to the dTD - */ - if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) { - NumdTD = EpCfg[EpNum].Out.NumBufs; - } - else { - NumdTD = 0; - } - - for (Td = 0; Td < NumdTD; ++Td) { - int Status; - - int NextTd = (Td + 1) % NumdTD; - - XUsbPs_dTDInvalidateCache(&Out->dTDs[Td]); - - /* Set NEXT link pointer. */ - XUsbPs_WritedTD(&Out->dTDs[Td], XUSBPS_dTDNLP, - &Out->dTDs[NextTd]); - - /* Set the OUT descriptor ACTIVE and enable the - * interrupt on complete. - */ - XUsbPs_dTDSetActive(&Out->dTDs[Td]); - XUsbPs_dTDSetIOC(&Out->dTDs[Td]); - - - /* Set up the data buffer with the descriptor. If the - * buffer pointer is NULL it means that we do not need - * to attach a buffer to this descriptor. - */ - if (NULL == Out->dTDBufs) { - XUsbPs_dTDFlushCache(&Out->dTDs[Td]); - continue; - } - - Status = XUsbPs_dTDAttachBuffer( - &Out->dTDs[Td], - Out->dTDBufs + - (Td * EpCfg[EpNum].Out.BufSize), - EpCfg[EpNum].Out.BufSize); - if (XST_SUCCESS != Status) { - return XST_FAILURE; - } - - XUsbPs_dTDFlushCache(&Out->dTDs[Td]); - } - - - /* IN Descriptors - * ============== - * - * + Set the next link pointer - * + Set the Terminate bit to mark it available - */ - if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].In.Type) { - NumdTD = EpCfg[EpNum].In.NumBufs; - } - else { - NumdTD = 0; - } - - for (Td = 0; Td < NumdTD; ++Td) { - int NextTd = (Td + 1) % NumdTD; - - XUsbPs_dTDInvalidateCache(&In->dTDs[Td]); - - /* Set NEXT link pointer. */ - XUsbPs_WritedTD(In->dTDs[Td], XUSBPS_dTDNLP, - In->dTDs[NextTd]); - - /* Set the IN descriptor's TERMINATE bits. */ - XUsbPs_dTDSetTerminate(In->dTDs[Td]); - - XUsbPs_dTDFlushCache(&In->dTDs[Td]); - } - } - - return XST_SUCCESS; -} - - -/*****************************************************************************/ -/** - * - * This function associates a buffer with a Transfer Descriptor. The function - * will take care of splitting the buffer into multiple 4kB aligned segments if - * the buffer happens to span one or more 4kB pages. - * - * @param dTDIndex is a pointer to the Transfer Descriptor - * @param BufferPtr is pointer to the buffer to link to the descriptor. - * @param BufferLen is the length of the buffer. - * - * @return - * - XST_SUCCESS: The operation completed successfully. - * - XST_FAILURE: An error occured. - * - XST_USB_BUF_TOO_BIG: The provided buffer is bigger than tha - * maximum allowed buffer size (16k). - * - * @note - * Cache invalidation and flushing needs to be handler by the - * caller of this function. - * - ******************************************************************************/ -static int XUsbPs_dTDAttachBuffer(XUsbPs_dTD *dTDPtr, - const u8 *BufferPtr, u32 BufferLen) -{ - u32 BufAddr; - u32 BufEnd; - u32 PtrNum; - - Xil_AssertNonvoid(dTDPtr != NULL); - - /* Check if the buffer is smaller than 16kB. */ - if (BufferLen > XUSBPS_dTD_BUF_MAX_SIZE) { - return XST_USB_BUF_TOO_BIG; - } - - /* Get a u32 of the buffer pointer to avoid casting in the following - * logic operations. - */ - BufAddr = (u32) BufferPtr; - - - /* Set the buffer pointer 0. Buffer pointer 0 can point to any location - * in memory. It does not need to be 4kB aligned. However, if the - * provided buffer spans one or more 4kB boundaries, we need to set up - * the subsequent buffer pointers which must be 4kB aligned. - */ - XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDBPTR(0), BufAddr); - - /* Check if the buffer spans a 4kB boundary. - * - * Only do this check, if we are not sending a 0-length buffer. - */ - if (BufferLen > 0) { - BufEnd = BufAddr + BufferLen -1; - PtrNum = 1; - - while ((BufAddr & 0xFFFFF000) != (BufEnd & 0xFFFFF000)) { - /* The buffer spans at least one boundary, let's set - * the next buffer pointer and repeat the procedure - * until the end of the buffer and the pointer written - * are in the same 4kB page. - */ - BufAddr = (BufAddr + 0x1000) & 0xFFFFF000; - XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDBPTR(PtrNum), - BufAddr); - PtrNum++; - } - } - - /* Set the length of the buffer. */ - XUsbPs_dTDSetTransferLen(dTDPtr, BufferLen); - - - /* We remember the buffer pointer in the user data field (reserved - * field in the dTD). This makes it easier to reset the buffer pointer - * after a buffer has been received on the endpoint. The buffer pointer - * needs to be reset because the DMA engine modifies the buffer pointer - * while receiving. - */ - XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDUSERDATA, BufferPtr); - - return XST_SUCCESS; -} - - -/*****************************************************************************/ -/** - * This function set the Max PacketLen for the queue head for isochronous EP. - * - * If the max packet length is greater than XUSBPS_MAX_PACKET_SIZE, then - * Mult bits are set to reflect that. - * - * @param dQHPtr is a pointer to the dQH element. - * @param Len is the Length to be set. - * - ******************************************************************************/ -static void XUsbPs_dQHSetMaxPacketLenISO(XUsbPs_dQH *dQHPtr, u32 Len) -{ - u32 Mult = (Len & ENDPOINT_MAXP_MULT_MASK) >> ENDPOINT_MAXP_MULT_SHIFT; - u32 MaxPktSize = (Mult > 1) ? ENDPOINT_MAXP_LENGTH : Len; - - if (MaxPktSize > XUSBPS_MAX_PACKET_SIZE) { - return; - } - - if (Mult > 3) { - return; - } - - /* Set Max packet size */ - XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, - (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & - ~XUSBPS_dQHCFG_MPL_MASK) | - (MaxPktSize << XUSBPS_dQHCFG_MPL_SHIFT)); - - /* Set Mult to tell hardware how many transactions in each microframe */ - XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, - (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & - ~XUSBPS_dQHCFG_MULT_MASK) | - (Mult << XUSBPS_dQHCFG_MULT_SHIFT)); - -} - -/*****************************************************************************/ -/** -* This function reconfigures one Ep corresponding to host's request of setting -* alternate interface. The endpoint has been disabled before this call. -* -* Both QH and dTDs are updated for the new configuration. -* -* @param InstancePtr is a pointer to the XUsbPs instance of the -* controller. -* @param CfgPtr -* Pointer to the updated XUsbPs DEVICE configuration structure. -* -* @param EpNum -* The endpoint to be reconfigured. -* -* @param NewDirection -* The new transfer direction the endpoint. -* -* @param DirectionChanged -* A boolean value indicate whether the transfer direction has changed. -* -* @return -* XST_SUCCESS upon success, XST_FAILURE otherwise. -* -******************************************************************************/ -int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr, - int EpNum, unsigned short NewDirection, - int DirectionChanged) { - - int Status = XST_SUCCESS; - XUsbPs_Endpoint *Ep; - XUsbPs_EpConfig *EpCfg; - - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(CfgPtr != NULL); - - Ep = CfgPtr->Ep; - EpCfg = CfgPtr->EpCfg; - - /* If transfer direction changes, dTDs has to be reset - * Number of buffers are preset and should not to be changed. - */ - if(DirectionChanged) { - if(NewDirection == XUSBPS_EP_DIRECTION_OUT) { - u8 *p; - - /* Swap the pointer to the dTDs. - */ - Ep[EpNum].Out.dTDs = Ep[EpNum].In.dTDs; - p = (u8 *)(Ep[EpNum].Out.dTDs + XUSBPS_dTD_ALIGN * EpCfg[EpNum].Out.NumBufs); - - /* Set the OUT buffer if buffer size is not zero - */ - if(EpCfg[EpNum].Out.BufSize > 0) { - Ep[EpNum].Out.dTDBufs = p; - } - } else if(NewDirection == XUSBPS_EP_DIRECTION_IN) { - Ep[EpNum].In.dTDs = Ep[EpNum].Out.dTDs; - } - } - - /* Reset dTD progress tracking pointers - */ - if(NewDirection == XUSBPS_EP_DIRECTION_IN) { - Ep[EpNum].In.dTDHead = Ep[EpNum].In.dTDTail = Ep[EpNum].In.dTDs; - } else if(NewDirection == XUSBPS_EP_DIRECTION_OUT) { - Ep[EpNum].Out.dTDCurr = Ep[EpNum].Out.dTDs; - } - - /* Reinitialize information in QH - */ - XUsbPs_dQHReinitEp(CfgPtr, EpNum, NewDirection); - - /* Reinitialize the dTD linked list, and flush the cache - */ - Status = XUsbPs_dTDReinitEp(CfgPtr, EpNum, NewDirection); - if(Status != XST_SUCCESS) { - return Status; - } - - return XST_SUCCESS; -} - - -/*****************************************************************************/ -/** - * This function re-initializes the Queue Head List in memory. - * The endpoint 1 has been disabled before this call. - * - * @param DevCfgPtr - * Pointer to the updated XUsbPs DEVICE configuration structure. - * - * @param EpNum - * The endpoint to be reconfigured. - * - * @param NewDirection - * The new transfer direction of endpoint 1 - * - * @return none - * - ******************************************************************************/ -static void XUsbPs_dQHReinitEp(XUsbPs_DeviceConfig *DevCfgPtr, -int EpNum, unsigned short NewDirection) -{ - XUsbPs_Endpoint *Ep; - XUsbPs_EpConfig *EpCfg; - - /* Setup pointers for simpler access. - */ - Ep = DevCfgPtr->Ep; - EpCfg = DevCfgPtr->EpCfg; - - - /* Go through the list of Queue Head entries and: - * - * - Set Transfer Descriptor addresses - * - Set Maximum Packet Size - * - Disable Zero Length Termination (ZLT) for non-isochronous transfers - * - Enable Interrupt On Setup (IOS) - * - */ - if(NewDirection == XUSBPS_EP_DIRECTION_OUT) { - /* OUT Queue Heads. - */ - XUsbPs_WritedQH(Ep[EpNum].Out.dQH, - XUSBPS_dQHCPTR, Ep[EpNum].Out.dTDs); - - /* For isochronous, ep max packet size translates to different - * values in queue head than other types. - * Also enable ZLT for isochronous. - */ - if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].Out.Type) { - XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].Out.dQH, - EpCfg[EpNum].Out.MaxPacketSize); - XUsbPs_dQHEnableZLT(Ep[EpNum].Out.dQH); - }else { - XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].Out.dQH, - EpCfg[EpNum].Out.MaxPacketSize); - XUsbPs_dQHDisableZLT(Ep[EpNum].Out.dQH); - } - - XUsbPs_dQHSetIOS(Ep[EpNum].Out.dQH); - - /* Set up the overlay next dTD pointer. - */ - XUsbPs_WritedQH(Ep[EpNum].Out.dQH, - XUSBPS_dQHdTDNLP, Ep[EpNum].Out.dTDs); - - XUsbPs_dQHFlushCache(Ep[EpNum].Out.dQH); - - } else if(NewDirection == XUSBPS_EP_DIRECTION_IN) { - - /* IN Queue Heads. - */ - XUsbPs_WritedQH(Ep[EpNum].In.dQH, - XUSBPS_dQHCPTR, Ep[EpNum].In.dTDs); - - /* Isochronous ep packet size can be larger than 1024. */ - if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].In.Type) { - XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].In.dQH, - EpCfg[EpNum].In.MaxPacketSize); - XUsbPs_dQHEnableZLT(Ep[EpNum].In.dQH); - }else { - XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].In.dQH, - EpCfg[EpNum].In.MaxPacketSize); - XUsbPs_dQHDisableZLT(Ep[EpNum].In.dQH); - } - - XUsbPs_dQHSetIOS(Ep[EpNum].In.dQH); - - XUsbPs_dQHFlushCache(Ep[EpNum].In.dQH); - } - -} - -/*****************************************************************************/ -/** - * - * This function re-initializes the Transfer Descriptors lists in memory. - * The endpoint has been disabled before the call. The transfer descriptors - * list pointer has been initialized too. - * - * @param DevCfgPtr - * Pointer to the XUsbPs DEVICE configuration structure. - * - * @param EpNum - * The endpoint to be reconfigured. - * - * @param NewDirection - * The new transfer direction of endpoint 1 - * - * @return - * - XST_SUCCESS: The operation completed successfully. - * - XST_FAILURE: An error occured. - * - ******************************************************************************/ -static int XUsbPs_dTDReinitEp(XUsbPs_DeviceConfig *DevCfgPtr, -int EpNum, unsigned short NewDirection) -{ - XUsbPs_Endpoint *Ep; - XUsbPs_EpConfig *EpCfg; - int Td; - int NumdTD; - - - /* Setup pointers for simpler access. - */ - Ep = DevCfgPtr->Ep; - EpCfg = DevCfgPtr->EpCfg; - - - if(NewDirection == XUSBPS_EP_DIRECTION_OUT) { - XUsbPs_EpOut *Out = &Ep[EpNum].Out; - - /* OUT Descriptors - * =============== - * - * + Set the next link pointer - * + Set the interrupt complete and the active bit - * + Attach the buffer to the dTD - */ - NumdTD = EpCfg[EpNum].Out.NumBufs; - - for (Td = 0; Td < NumdTD; ++Td) { - int Status; - - int NextTd = (Td + 1) % NumdTD; - - XUsbPs_dTDInvalidateCache(&Out->dTDs[Td]); - - /* Set NEXT link pointer. - */ - XUsbPs_WritedTD(&Out->dTDs[Td], XUSBPS_dTDNLP, - &Out->dTDs[NextTd]); - - /* Set the OUT descriptor ACTIVE and enable the - * interrupt on complete. - */ - XUsbPs_dTDSetActive(&Out->dTDs[Td]); - XUsbPs_dTDSetIOC(&Out->dTDs[Td]); - - /* Set up the data buffer with the descriptor. If the - * buffer pointer is NULL it means that we do not need - * to attach a buffer to this descriptor. - */ - if (Out->dTDBufs != NULL) { - - Status = XUsbPs_dTDAttachBuffer( - &Out->dTDs[Td], - Out->dTDBufs + - (Td * EpCfg[EpNum].Out.BufSize), - EpCfg[EpNum].Out.BufSize); - if (Status != XST_SUCCESS) { - return XST_FAILURE; - } - } - XUsbPs_dTDFlushCache(&Out->dTDs[Td]); - } - } else if(NewDirection == XUSBPS_EP_DIRECTION_IN) { - XUsbPs_EpIn *In = &Ep[EpNum].In; - - /* IN Descriptors - * ============== - * - * + Set the next link pointer - * + Set the Terminate bit to mark it available - */ - NumdTD = EpCfg[EpNum].In.NumBufs; - - for (Td = 0; Td < NumdTD; ++Td) { - int NextTd = (Td + 1) % NumdTD; - - XUsbPs_dTDInvalidateCache(&In->dTDs[Td]); - - /* Set NEXT link pointer. - */ - XUsbPs_WritedTD(&In->dTDs[Td], XUSBPS_dTDNLP, - &In->dTDs[NextTd]); - - /* Set the IN descriptor's TERMINATE bits. - */ - XUsbPs_dTDSetTerminate(&In->dTDs[Td]); - - XUsbPs_dTDFlushCache(&In->dTDs[Td]); - } - } - - return XST_SUCCESS; -} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/xusbps_endpoint.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/xusbps_endpoint.h deleted file mode 100644 index 98d701c8338e2cab7e5e605a4d5f7643228e6ddb..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/xusbps_endpoint.h +++ /dev/null @@ -1,521 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** - * - * @file xusbps_endpoint.h - * - * This is an internal file containung the definitions for endpoints. It is - * included by the xusbps_endpoint.c which is implementing the endpoint - * functions and by xusbps_intr.c. - * - * <pre> - * MODIFICATION HISTORY: - * - * Ver Who Date Changes - * ----- ---- -------- -------------------------------------------------------- - * 1.00a wgr 10/10/10 First release - * </pre> - * - ******************************************************************************/ -#ifndef XUSBPS_ENDPOINT_H -#define XUSBPS_ENDPOINT_H - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_cache.h" -#include "xusbps.h" -#include "xil_types.h" - -/**************************** Type Definitions *******************************/ - -/************************** Constant Definitions *****************************/ - - -/** - * Endpoint Device Transfer Descriptor - * - * The dTD describes to the device controller the location and quantity of data - * to be sent/received for given transfer. The driver does not attempt to - * modify any field in an active dTD except the Next Link Pointer. - */ -#define XUSBPS_dTDNLP 0x00 /**< Pointer to the next descriptor */ -#define XUSBPS_dTDTOKEN 0x04 /**< Descriptor Token */ -#define XUSBPS_dTDBPTR0 0x08 /**< Buffer Pointer 0 */ -#define XUSBPS_dTDBPTR1 0x0C /**< Buffer Pointer 1 */ -#define XUSBPS_dTDBPTR2 0x10 /**< Buffer Pointer 2 */ -#define XUSBPS_dTDBPTR3 0x14 /**< Buffer Pointer 3 */ -#define XUSBPS_dTDBPTR4 0x18 /**< Buffer Pointer 4 */ -#define XUSBPS_dTDBPTR(n) (XUSBPS_dTDBPTR0 + (n) * 0x04) -#define XUSBPS_dTDRSRVD 0x1C /**< Reserved field */ - -/* We use the reserved field in the dTD to store user data. */ -#define XUSBPS_dTDUSERDATA XUSBPS_dTDRSRVD /**< Reserved field */ - - -/** @name dTD Next Link Pointer (dTDNLP) bit positions. - * @{ - */ -#define XUSBPS_dTDNLP_T_MASK 0x00000001 - /**< USB dTD Next Link Pointer Terminate Bit */ -#define XUSBPS_dTDNLP_ADDR_MASK 0xFFFFFFE0 - /**< USB dTD Next Link Pointer Address [31:5] */ -/* @} */ - - -/** @name dTD Token (dTDTOKEN) bit positions. - * @{ - */ -#define XUSBPS_dTDTOKEN_XERR_MASK 0x00000008 /**< dTD Transaction Error */ -#define XUSBPS_dTDTOKEN_BUFERR_MASK 0x00000020 /**< dTD Data Buffer Error */ -#define XUSBPS_dTDTOKEN_HALT_MASK 0x00000040 /**< dTD Halted Flag */ -#define XUSBPS_dTDTOKEN_ACTIVE_MASK 0x00000080 /**< dTD Active Bit */ -#define XUSBPS_dTDTOKEN_MULTO_MASK 0x00000C00 /**< Multiplier Override Field [1:0] */ -#define XUSBPS_dTDTOKEN_IOC_MASK 0x00008000 /**< Interrupt on Complete Bit */ -#define XUSBPS_dTDTOKEN_LEN_MASK 0x7FFF0000 /**< Transfer Length Field */ -/* @} */ - - -/***************** Macros (Inline Functions) Definitions *********************/ - -/*****************************************************************************/ -/** - * - * IMPORTANT NOTE: - * =============== - * - * Many of the following macros modify Device Queue Head (dQH) data structures - * and Device Transfer Descriptor (dTD) data structures. Those structures can - * potentially reside in CACHED memory. Therefore, it's the callers - * responsibility to ensure cache coherency by using provided - * - * XUsbPs_dQHInvalidateCache() - * XUsbPs_dQHFlushCache() - * XUsbPs_dTDInvalidateCache() - * XUsbPs_dTDFlushCache() - * - * function calls. - * - ******************************************************************************/ -#define XUsbPs_dTDInvalidateCache(dTDPtr) \ - Xil_DCacheInvalidateRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD)) - -#define XUsbPs_dTDFlushCache(dTDPtr) \ - Xil_DCacheFlushRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD)) - -#define XUsbPs_dQHInvalidateCache(dQHPtr) \ - Xil_DCacheInvalidateRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH)) - -#define XUsbPs_dQHFlushCache(dQHPtr) \ - Xil_DCacheFlushRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH)) - -/*****************************************************************************/ -/** - * - * This macro sets the Transfer Length for the given Transfer Descriptor. - * - * @param dTDPtr is pointer to the dTD element. - * @param Len is the length to be set. Range: 0..16384 - * - * @note C-style signature: - * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len) - * - ******************************************************************************/ -#define XUsbPs_dTDSetTransferLen(dTDPtr, Len) \ - XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \ - (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \ - ~XUSBPS_dTDTOKEN_LEN_MASK) | ((Len) << 16)) - - -/*****************************************************************************/ -/** - * - * This macro gets the Next Link pointer of the given Transfer Descriptor. - * - * @param dTDPtr is pointer to the dTD element. - * - * @return TransferLength field of the descriptor. - * - * @note C-style signature: - * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr) - * - ******************************************************************************/ -#define XUsbPs_dTDGetNLP(dTDPtr) \ - (XUsbPs_dTD *) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP)\ - & XUSBPS_dTDNLP_ADDR_MASK)) - - -/*****************************************************************************/ -/** - * - * This macro sets the Next Link pointer of the given Transfer Descriptor. - * - * @param dTDPtr is a pointer to the dTD element. - * @param NLP is the Next Link Pointer - * - * @note C-style signature: - * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len) - * - ******************************************************************************/ -#define XUsbPs_dTDSetNLP(dTDPtr, NLP) \ - XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \ - (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \ - ~XUSBPS_dTDNLP_ADDR_MASK) | \ - ((NLP) & XUSBPS_dTDNLP_ADDR_MASK)) - - -/*****************************************************************************/ -/** - * - * This macro gets the Transfer Length for the given Transfer Descriptor. - * - * @param dTDPtr is a pointer to the dTD element. - * - * @return TransferLength field of the descriptor. - * - * @note C-style signature: - * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr) - * - ******************************************************************************/ -#define XUsbPs_dTDGetTransferLen(dTDPtr) \ - (u32) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) \ - & XUSBPS_dTDTOKEN_LEN_MASK) >> 16) - - -/*****************************************************************************/ -/** - * - * This macro sets the Interrupt On Complete (IOC) bit for the given Transfer - * Descriptor. - * - * @param dTDPtr is a pointer to the dTD element. - * - * @note C-style signature: - * void XUsbPs_dTDSetIOC(u32 dTDPtr) - * - ******************************************************************************/ -#define XUsbPs_dTDSetIOC(dTDPtr) \ - XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \ - XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \ - XUSBPS_dTDTOKEN_IOC_MASK) - - -/*****************************************************************************/ -/** - * - * This macro sets the Terminate bit for the given Transfer Descriptor. - * - * @param dTDPtr is a pointer to the dTD element. - * - * @note C-style signature: - * void XUsbPs_dTDSetTerminate(u32 dTDPtr) - * - ******************************************************************************/ -#define XUsbPs_dTDSetTerminate(dTDPtr) \ - XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \ - XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) | \ - XUSBPS_dTDNLP_T_MASK) - - -/*****************************************************************************/ -/** - * - * This macro clears the Terminate bit for the given Transfer Descriptor. - * - * @param dTDPtr is a pointer to the dTD element. - * - * @note C-style signature: - * void XUsbPs_dTDClrTerminate(u32 dTDPtr) - * - ******************************************************************************/ -#define XUsbPs_dTDClrTerminate(dTDPtr) \ - XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \ - XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \ - ~XUSBPS_dTDNLP_T_MASK) - - -/*****************************************************************************/ -/** - * - * This macro checks if the given descriptor is active. - * - * @param dTDPtr is a pointer to the dTD element. - * - * @return - * - TRUE: The buffer is active. - * - FALSE: The buffer is not active. - * - * @note C-style signature: - * int XUsbPs_dTDIsActive(u32 dTDPtr) - * - ******************************************************************************/ -#define XUsbPs_dTDIsActive(dTDPtr) \ - ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \ - XUSBPS_dTDTOKEN_ACTIVE_MASK) ? TRUE : FALSE) - - -/*****************************************************************************/ -/** - * - * This macro sets the Active bit for the given Transfer Descriptor. - * - * @param dTDPtr is a pointer to the dTD element. - * - * @note C-style signature: - * void XUsbPs_dTDSetActive(u32 dTDPtr) - * - ******************************************************************************/ -#define XUsbPs_dTDSetActive(dTDPtr) \ - XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \ - XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \ - XUSBPS_dTDTOKEN_ACTIVE_MASK) - - -/*****************************************************************************/ -/** - * - * This macro reads the content of a field in a Transfer Descriptor. - * - * @param dTDPtr is a pointer to the dTD element. - * @param Id is the field ID inside the dTD element to read. - * - * @note C-style signature: - * u32 XUsbPs_ReaddTD(u32 dTDPtr, u32 Id) - * - ******************************************************************************/ -#define XUsbPs_ReaddTD(dTDPtr, Id) (*(u32 *)((u32)(dTDPtr) + (u32)(Id))) - -/*****************************************************************************/ -/** - * - * This macro writes a value to a field in a Transfer Descriptor. - * - * @param dTDPtr is pointer to the dTD element. - * @param Id is the field ID inside the dTD element to read. - * @param Val is the value to write to the field. - * - * @note C-style signature: - * u32 XUsbPs_WritedTD(u32 dTDPtr, u32 Id, u32 Val) - * - ******************************************************************************/ -#define XUsbPs_WritedTD(dTDPtr, Id, Val) \ - (*(u32 *) ((u32)(dTDPtr) + (u32)(Id)) = (u32)(Val)) - - -/******************************************************************************/ -/** - * Endpoint Device Queue Head - * - * Device queue heads are arranged in an array in a continuous area of memory - * pointed to by the ENDPOINTLISTADDR pointer. The device controller will index - * into this array based upon the endpoint number received from the USB bus. - * All information necessary to respond to transactions for all primed - * transfers is contained in this list so the Device Controller can readily - * respond to incoming requests without having to traverse a linked list. - * - * The device Endpoint Queue Head (dQH) is where all transfers are managed. The - * dQH is a 48-byte data structure, but must be aligned on a 64-byte boundary. - * During priming of an endpoint, the dTD (device transfer descriptor) is - * copied into the overlay area of the dQH, which starts at the nextTD pointer - * DWord and continues through the end of the buffer pointers DWords. After a - * transfer is complete, the dTD status DWord is updated in the dTD pointed to - * by the currentTD pointer. While a packet is in progress, the overlay area of - * the dQH is used as a staging area for the dTD so that the Device Controller - * can access needed information with little minimal latency. - * - * @note - * Software must ensure that no interface data structure reachable by the - * Device Controller spans a 4K-page boundary. The first element of the - * Endpoint Queue Head List must be aligned on a 4K boundary. - */ -#define XUSBPS_dQHCFG 0x00 /**< dQH Configuration */ -#define XUSBPS_dQHCPTR 0x04 /**< dQH Current dTD Pointer */ -#define XUSBPS_dQHdTDNLP 0x08 /**< dTD Next Link Ptr in dQH - overlay */ -#define XUSBPS_dQHdTDTOKEN 0x0C /**< dTD Token in dQH overlay */ -#define XUSBPS_dQHSUB0 0x28 /**< USB dQH Setup Buffer 0 */ -#define XUSBPS_dQHSUB1 0x2C /**< USB dQH Setup Buffer 1 */ - - -/** @name dQH Configuration (dQHCFG) bit positions. - * @{ - */ -#define XUSBPS_dQHCFG_IOS_MASK 0x00008000 - /**< USB dQH Interrupt on Setup Bit */ -#define XUSBPS_dQHCFG_MPL_MASK 0x07FF0000 - /**< USB dQH Maximum Packet Length - * Field [10:0] */ -#define XUSBPS_dQHCFG_MPL_SHIFT 16 -#define XUSBPS_dQHCFG_ZLT_MASK 0x20000000 - /**< USB dQH Zero Length Termination - * Select Bit */ -#define XUSBPS_dQHCFG_MULT_MASK 0xC0000000 - /* USB dQH Number of Transactions Field - * [1:0] */ -#define XUSBPS_dQHCFG_MULT_SHIFT 30 -/* @} */ - - -/*****************************************************************************/ -/** - * - * This macro sets the Maximum Packet Length field of the give Queue Head. - * - * @param dQHPtr is a pointer to the dQH element. - * @param Len is the length to be set. - * - * @note C-style signature: - * void XUsbPs_dQHSetMaxPacketLen(u32 dQHPtr, u32 Len) - * - ******************************************************************************/ -#define XUsbPs_dQHSetMaxPacketLen(dQHPtr, Len) \ - XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ - (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \ - ~XUSBPS_dQHCFG_MPL_MASK) | ((Len) << 16)) - -/*****************************************************************************/ -/** - * - * This macro sets the Interrupt On Setup (IOS) bit for an endpoint. - * - * @param dQHPtr is a pointer to the dQH element. - * - * @note C-style signature: - * void XUsbPs_dQHSetIOS(u32 dQHPtr) - * - ******************************************************************************/ -#define XUsbPs_dQHSetIOS(dQHPtr) \ - XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ - XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \ - XUSBPS_dQHCFG_IOS_MASK) - -/*****************************************************************************/ -/** - * - * This macro clears the Interrupt On Setup (IOS) bit for an endpoint. - * - * @param dQHPtr is a pointer to the dQH element. - * - * @note C-style signature: - * void XUsbPs_dQHClrIOS(u32 dQHPtr) - * - ******************************************************************************/ -#define XUsbPs_dQHClrIOS(dQHPtr) \ - XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ - XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \ - ~XUSBPS_dQHCFG_IOS_MASK) - -/*****************************************************************************/ -/** - * - * This macro enables Zero Length Termination for the endpoint. - * - * @param dQHPtr is a pointer to the dQH element. - * - * @note C-style signature: - * void XUsbPs_dQHEnableZLT(u32 dQHPtr) - * - * - ******************************************************************************/ -#define XUsbPs_dQHEnableZLT(dQHPtr) \ - XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ - XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \ - ~XUSBPS_dQHCFG_ZLT_MASK) - - -/*****************************************************************************/ -/** - * - * This macro disables Zero Length Termination for the endpoint. - * - * @param dQHPtr is a pointer to the dQH element. - * - * @note C-style signature: - * void XUsbPs_dQHDisableZLT(u32 dQHPtr) - * - * - ******************************************************************************/ -#define XUsbPs_dQHDisableZLT(dQHPtr) \ - XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ - XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \ - XUSBPS_dQHCFG_ZLT_MASK) - -/*****************************************************************************/ -/** - * - * This macro reads the content of a field in a Queue Head. - * - * @param dQHPtr is a pointer to the dQH element. - * @param Id is the Field ID inside the dQH element to read. - * - * @note C-style signature: - * u32 XUsbPs_ReaddQH(u32 dQHPtr, u32 Id) - * - ******************************************************************************/ -#define XUsbPs_ReaddQH(dQHPtr, Id) (*(u32 *)((u32)(dQHPtr) + (u32) (Id))) - -/*****************************************************************************/ -/** - * - * This macro writes a value to a field in a Queue Head. - * - * @param dQHPtr is a pointer to the dQH element. - * @param Id is the Field ID inside the dQH element to read. - * @param Val is the Value to write to the field. - * - * @note C-style signature: - * u32 XUsbPs_WritedQH(u32 dQHPtr, u32 Id, u32 Val) - * - ******************************************************************************/ -#define XUsbPs_WritedQH(dQHPtr, Id, Val) \ - (*(u32 *) ((u32)(dQHPtr) + (u32)(Id)) = (u32)(Val)) - - - -#ifdef __cplusplus -} -#endif - -#endif /* XUSBPS_ENDPOINT_H */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/xusbps_g.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/xusbps_g.c deleted file mode 100644 index c84509f298d9697d1bf5f979fa162109edb52a5c..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/xusbps_g.c +++ /dev/null @@ -1,30 +0,0 @@ - -/******************************************************************* -* -* CAUTION: This file is automatically generated by libgen. -* Version: Xilinx EDK 14.7 EDK_P.20131013 -* DO NOT EDIT. -* -* Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. - -* -* Description: Driver configuration -* -*******************************************************************/ - -#include "xparameters.h" -#include "xusbps.h" - -/* -* The configuration table for devices -*/ - -XUsbPs_Config XUsbPs_ConfigTable[] = -{ - { - XPAR_PS7_USB_0_DEVICE_ID, - XPAR_PS7_USB_0_BASEADDR - } -}; - - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/xusbps_hw.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/xusbps_hw.c deleted file mode 100644 index bdcb9a85904ea92f9e8b48d73507880c192c3198..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/xusbps_hw.c +++ /dev/null @@ -1,128 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/****************************************************************************/ -/** - * - * @file xusbps_hw.c - * - * The implementation of the XUsbPs interface reset functionality - * - * <pre> - * MODIFICATION HISTORY: - * - * Ver Who Date Changes - * ----- ---- -------- ----------------------------------------------- - * 1.05a kpc 10/10/10 first version - * </pre> - * - *****************************************************************************/ - -/***************************** Include Files ********************************/ - -#include "xstatus.h" -#include "xusbps.h" -#include "xparameters.h" - - -/************************** Constant Definitions ****************************/ -#define XUSBPS_RESET_TIMEOUT 0xFFFFF -/**************************** Type Definitions ******************************/ - -/***************** Macros (Inline Functions) Definitions ********************/ - -/************************** Variable Definitions ****************************/ - - -/************************** Function Prototypes *****************************/ - - -/*****************************************************************************/ -/** -* This function perform the reset sequence to the given usbps interface by -* configuring the appropriate control bits in the usbps specifc registers. -* the usbps reset sequence involves the below steps -* Disbale the interrupts -* Clear the status registers -* Apply the reset command and wait for reset complete status -* Update the relevant control registers with reset values -* @param BaseAddress of the interface -* -* @return N/A. -* -* @note None. -* -******************************************************************************/ -void XUsbPs_ResetHw(u32 BaseAddress) -{ - u32 RegVal; - u32 Timeout = 0; - - /* Host and device mode */ - /* Disable the interrupts */ - XUsbPs_WriteReg(BaseAddress,XUSBPS_IER_OFFSET,0x0); - /* Clear the interuupt status */ - RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_ISR_OFFSET); - XUsbPs_WriteReg(BaseAddress,XUSBPS_ISR_OFFSET,RegVal); - - /* Perform the reset operation using USB CMD register */ - RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_CMD_OFFSET); - RegVal = RegVal | XUSBPS_CMD_RST_MASK; - XUsbPs_WriteReg(BaseAddress,XUSBPS_CMD_OFFSET,RegVal); - RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_CMD_OFFSET); - /* Wait till the reset operation returns success */ - /* - * FIX ME: right now no indication to the caller or user about - * timeout overflow - */ - while ((RegVal & XUSBPS_CMD_RST_MASK) && (Timeout < XUSBPS_RESET_TIMEOUT)) - { - RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_CMD_OFFSET); - Timeout++; - } - /* Update periodic list base address register with reset value */ - XUsbPs_WriteReg(BaseAddress,XUSBPS_LISTBASE_OFFSET,0x0); - /* Update async/endpoint list base address register with reset value */ - XUsbPs_WriteReg(BaseAddress,XUSBPS_ASYNCLISTADDR_OFFSET,0x0); - -} - - - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/xusbps_hw.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/xusbps_hw.h deleted file mode 100644 index 5986f65bd885edf99fb8f9c959d190813be5e4e2..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/xusbps_hw.h +++ /dev/null @@ -1,531 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** - * - * @file xusbps_hw.h - * - * This header file contains identifiers and low-level driver functions (or - * macros) that can be used to access the device. High-level driver functions - * are defined in xusbps.h. - * - * <pre> - * MODIFICATION HISTORY: - * - * Ver Who Date Changes - * ----- ---- -------- ----------------------------------------------- - * 1.00a wgr 10/10/10 First release - * 1.04a nm 10/23/12 Fixed CR# 679106. - * 1.05a kpc 07/03/13 Added XUsbPs_ResetHw function prototype - * </pre> - * - ******************************************************************************/ -#ifndef XUSBPS_HW_H -#define XUSBPS_HW_H - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xil_io.h" - -/************************** Constant Definitions *****************************/ - - -#define XUSBPS_REG_SPACING 4 - -/** @name Timer 0 Register offsets - * - * @{ - */ -#define XUSBPS_TIMER0_LD_OFFSET 0x00000080 -#define XUSBPS_TIMER0_CTL_OFFSET 0x00000084 -/* @} */ - -/** @name Timer Control Register bit mask - * - * @{ - */ -#define XUSBPS_TIMER_RUN_MASK 0x80000000 -#define XUSBPS_TIMER_STOP_MASK 0x80000000 -#define XUSBPS_TIMER_RESET_MASK 0x40000000 -#define XUSBPS_TIMER_REPEAT_MASK 0x01000000 -/* @} */ - -/** @name Timer Control Register bit mask - * - * @{ - */ -#define XUSBPS_TIMER_COUNTER_MASK 0x00FFFFFF -/* @} */ - -/** @name Device Hardware Parameters - * - * @{ - */ -#define XUSBPS_HWDEVICE_OFFSET 0x0000000C - -#define XUSBPS_EP_NUM_MASK 0x3E -#define XUSBPS_EP_NUM_SHIFT 1 -/* @} */ - -/** @name Capability Regsiter offsets - */ -#define XUSBPS_HCSPARAMS_OFFSET 0x00000104 - -/** @name Operational Register offsets. - * Register comments are tagged with "H:" and "D:" for Host and Device modes, - * respectively. - * Tags are only present for registers that have a different meaning DEVICE and - * HOST modes. Most registers are only valid for either DEVICE or HOST mode. - * Those registers don't have tags. - * @{ - */ -#define XUSBPS_CMD_OFFSET 0x00000140 /**< Configuration */ -#define XUSBPS_ISR_OFFSET 0x00000144 /**< Interrupt Status */ -#define XUSBPS_IER_OFFSET 0x00000148 /**< Interrupt Enable */ -#define XUSBPS_FRAME_OFFSET 0x0000014C /**< USB Frame Index */ -#define XUSBPS_LISTBASE_OFFSET 0x00000154 /**< H: Periodic List Base Address */ -#define XUSBPS_DEVICEADDR_OFFSET 0x00000154 /**< D: Device Address */ -#define XUSBPS_ASYNCLISTADDR_OFFSET 0x00000158 /**< H: Async List Address */ -#define XUSBPS_EPLISTADDR_OFFSET 0x00000158 /**< D: Endpoint List Addr */ -#define XUSBPS_TTCTRL_OFFSET 0x0000015C /**< TT Control */ -#define XUSBPS_BURSTSIZE_OFFSET 0x00000160 /**< Burst Size */ -#define XUSBPS_TXFILL_OFFSET 0x00000164 /**< Tx Fill Tuning */ -#define XUSBPS_ULPIVIEW_OFFSET 0x00000170 /**< ULPI Viewport */ -#define XUSBPS_EPNAKISR_OFFSET 0x00000178 /**< Endpoint NAK IRQ Status */ -#define XUSBPS_EPNAKIER_OFFSET 0x0000017C /**< Endpoint NAK IRQ Enable */ -#define XUSBPS_PORTSCR1_OFFSET 0x00000184 /**< Port Control/Status 1 */ - -/* NOTE: The Port Control / Status Register index is 1-based. */ -#define XUSBPS_PORTSCRn_OFFSET(n) \ - (XUSBPS_PORTSCR1_OFFSET + (((n)-1) * XUSBPS_REG_SPACING)) - - -#define XUSBPS_OTGCSR_OFFSET 0x000001A4 /**< OTG Status and Control */ -#define XUSBPS_MODE_OFFSET 0x000001A8 /**< USB Mode */ -#define XUSBPS_EPSTAT_OFFSET 0x000001AC /**< Endpoint Setup Status */ -#define XUSBPS_EPPRIME_OFFSET 0x000001B0 /**< Endpoint Prime */ -#define XUSBPS_EPFLUSH_OFFSET 0x000001B4 /**< Endpoint Flush */ -#define XUSBPS_EPRDY_OFFSET 0x000001B8 /**< Endpoint Ready */ -#define XUSBPS_EPCOMPL_OFFSET 0x000001BC /**< Endpoint Complete */ -#define XUSBPS_EPCR0_OFFSET 0x000001C0 /**< Endpoint Control 0 */ -#define XUSBPS_EPCR1_OFFSET 0x000001C4 /**< Endpoint Control 1 */ -#define XUSBPS_EPCR2_OFFSET 0x000001C8 /**< Endpoint Control 2 */ -#define XUSBPS_EPCR3_OFFSET 0x000001CC /**< Endpoint Control 3 */ -#define XUSBPS_EPCR4_OFFSET 0x000001D0 /**< Endpoint Control 4 */ - -#define XUSBPS_MAX_ENDPOINTS 4 /**< Number of supported Endpoints in - * this core. */ -#define XUSBPS_EP_OUT_MASK 0x0000001F /**< OUR (RX) endpoint mask */ -#define XUSBPS_EP_IN_MASK 0x001F0000 /**< IN (TX) endpoint mask */ -#define XUSBPS_EP_ALL_MASK 0x001F001F /**< Mask used for endpoint control - * registers */ -#define XUSBPS_EPCRn_OFFSET(n) \ - (XUSBPS_EPCR0_OFFSET + ((n) * XUSBPS_REG_SPACING)) - -#define XUSBPS_EPFLUSH_RX_SHIFT 0 -#define XUSBPS_EPFLUSH_TX_SHIFT 16 - -/* @} */ - - - -/** @name Endpoint Control Register (EPCR) bit positions. - * @{ - */ - -/* Definitions for TX Endpoint bits */ -#define XUSBPS_EPCR_TXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - TX */ -#define XUSBPS_EPCR_TXT_ISO_MASK 0x00040000 /**< Isochronous. Endpoint */ -#define XUSBPS_EPCR_TXT_BULK_MASK 0x00080000 /**< Bulk Endpoint - TX */ -#define XUSBPS_EPCR_TXT_INTR_MASK 0x000C0000 /**< Interrupt Endpoint */ -#define XUSBPS_EPCR_TXS_MASK 0x00010000 /**< Stall TX endpoint */ -#define XUSBPS_EPCR_TXE_MASK 0x00800000 /**< Transmit enable - TX */ -#define XUSBPS_EPCR_TXR_MASK 0x00400000 /**< Data Toggle Reset Bit */ - - -/* Definitions for RX Endpoint bits */ -#define XUSBPS_EPCR_RXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - RX */ -#define XUSBPS_EPCR_RXT_ISO_MASK 0x00000004 /**< Isochronous Endpoint */ -#define XUSBPS_EPCR_RXT_BULK_MASK 0x00000008 /**< Bulk Endpoint - RX */ -#define XUSBPS_EPCR_RXT_INTR_MASK 0x0000000C /**< Interrupt Endpoint */ -#define XUSBPS_EPCR_RXS_MASK 0x00000001 /**< Stall RX endpoint. */ -#define XUSBPS_EPCR_RXE_MASK 0x00000080 /**< Transmit enable. - RX */ -#define XUSBPS_EPCR_RXR_MASK 0x00000040 /**< Data Toggle Reset Bit */ -/* @} */ - - -/** @name USB Command Register (CR) bit positions. - * @{ - */ -#define XUSBPS_CMD_RS_MASK 0x00000001 /**< Run/Stop */ -#define XUSBPS_CMD_RST_MASK 0x00000002 /**< Controller RESET */ -#define XUSBPS_CMD_FS01_MASK 0x0000000C /**< Frame List Size bit 0,1 */ -#define XUSBPS_CMD_PSE_MASK 0x00000010 /**< Periodic Sched Enable */ -#define XUSBPS_CMD_ASE_MASK 0x00000020 /**< Async Sched Enable */ -#define XUSBPS_CMD_IAA_MASK 0x00000040 /**< IRQ Async Advance Doorbell */ -#define XUSBPS_CMD_ASP_MASK 0x00000300 /**< Async Sched Park Mode Cnt */ -#define XUSBPS_CMD_ASPE_MASK 0x00000800 /**< Async Sched Park Mode Enbl */ -#define XUSBPS_CMD_SUTW_MASK 0x00002000 /**< Setup TripWire */ -#define XUSBPS_CMD_ATDTW_MASK 0x00004000 /**< Add dTD TripWire */ -#define XUSBPS_CMD_FS2_MASK 0x00008000 /**< Frame List Size bit 2 */ -#define XUSBPS_CMD_ITC_MASK 0x00FF0000 /**< IRQ Threshold Control */ -/* @} */ - - -/** - * @name Interrupt Threshold - * These definitions are used by software to set the maximum rate at which the - * USB controller will generate interrupt requests. The interrupt interval is - * given in number of micro-frames. - * - * USB defines a full-speed 1 ms frame time indicated by a Start Of Frame (SOF) - * packet each and every 1ms. USB also defines a high-speed micro-frame with a - * 125us frame time. For each micro-frame a SOF (Start Of Frame) packet is - * generated. Data is sent in between the SOF packets. The interrupt threshold - * defines how many micro-frames the controller waits before issuing an - * interrupt after data has been received. - * - * For a threshold of 0 the controller will issue an interrupt immediately - * after the last byte of the data has been received. For a threshold n>0 the - * controller will wait for n micro-frames before issuing an interrupt. - * - * Therefore, a setting of 8 micro-frames (default) means that the controller - * will issue at most 1 interrupt per millisecond. - * - * @{ - */ -#define XUSBPS_CMD_ITHRESHOLD_0 0x00 /**< Immediate interrupt. */ -#define XUSBPS_CMD_ITHRESHOLD_1 0x01 /**< 1 micro-frame */ -#define XUSBPS_CMD_ITHRESHOLD_2 0x02 /**< 2 micro-frames */ -#define XUSBPS_CMD_ITHRESHOLD_4 0x04 /**< 4 micro-frames */ -#define XUSBPS_CMD_ITHRESHOLD_8 0x08 /**< 8 micro-frames */ -#define XUSBPS_CMD_ITHRESHOLD_16 0x10 /**< 16 micro-frames */ -#define XUSBPS_CMD_ITHRESHOLD_32 0x20 /**< 32 micro-frames */ -#define XUSBPS_CMD_ITHRESHOLD_64 0x40 /**< 64 micro-frames */ -#define XUSBPS_CMD_ITHRESHOLD_MAX XUSBPS_CMD_ITHRESHOLD_64 -#define XUSBPS_CMD_ITHRESHOLD_DEFAULT XUSBPS_CMD_ITHRESHOLD_8 -/* @} */ - - - -/** @name USB Interrupt Status Register (ISR) / Interrupt Enable Register (IER) - * bit positions. - * @{ - */ -#define XUSBPS_IXR_UI_MASK 0x00000001 /**< USB Transaction Complete */ -#define XUSBPS_IXR_UE_MASK 0x00000002 /**< Transaction Error */ -#define XUSBPS_IXR_PC_MASK 0x00000004 /**< Port Change Detect */ -#define XUSBPS_IXR_FRE_MASK 0x00000008 /**< Frame List Rollover */ -#define XUSBPS_IXR_AA_MASK 0x00000020 /**< Async Advance */ -#define XUSBPS_IXR_UR_MASK 0x00000040 /**< RESET Received */ -#define XUSBPS_IXR_SR_MASK 0x00000080 /**< Start of Frame */ -#define XUSBPS_IXR_SLE_MASK 0x00000100 /**< Device Controller Suspend */ -#define XUSBPS_IXR_ULPI_MASK 0x00000400 /**< ULPI IRQ */ -#define XUSBPS_IXR_HCH_MASK 0x00001000 /**< Host Controller Halted - * Read Only */ -#define XUSBPS_IXR_RCL_MASK 0x00002000 /**< USB Reclamation Read Only */ -#define XUSBPS_IXR_PS_MASK 0x00004000 /**< Periodic Sched Status - * Read Only */ -#define XUSBPS_IXR_AS_MASK 0x00008000 /**< Async Sched Status Read only */ -#define XUSBPS_IXR_NAK_MASK 0x00010000 /**< NAK IRQ */ -#define XUSBPS_IXR_UA_MASK 0x00040000 /**< USB Host Async IRQ */ -#define XUSBPS_IXR_UP_MASK 0x00080000 /**< USB Host Periodic IRQ */ -#define XUSBPS_IXR_TI0_MASK 0x01000000 /**< Timer 0 Interrupt */ -#define XUSBPS_IXR_TI1_MASK 0x02000000 /**< Timer 1 Interrupt */ - -#define XUSBPS_IXR_ALL (XUSBPS_IXR_UI_MASK | \ - XUSBPS_IXR_UE_MASK | \ - XUSBPS_IXR_PC_MASK | \ - XUSBPS_IXR_FRE_MASK | \ - XUSBPS_IXR_AA_MASK | \ - XUSBPS_IXR_UR_MASK | \ - XUSBPS_IXR_SR_MASK | \ - XUSBPS_IXR_SLE_MASK | \ - XUSBPS_IXR_ULPI_MASK | \ - XUSBPS_IXR_HCH_MASK | \ - XUSBPS_IXR_RCL_MASK | \ - XUSBPS_IXR_PS_MASK | \ - XUSBPS_IXR_AS_MASK | \ - XUSBPS_IXR_NAK_MASK | \ - XUSBPS_IXR_UA_MASK | \ - XUSBPS_IXR_UP_MASK | \ - XUSBPS_IXR_TI0_MASK | \ - XUSBPS_IXR_TI1_MASK) - /**< Mask for ALL IRQ types */ -/* @} */ - - -/** @name USB Mode Register (MODE) bit positions. - * @{ - */ -#define XUSBPS_MODE_CM_MASK 0x00000003 /**< Controller Mode Select */ -#define XUSBPS_MODE_CM_IDLE_MASK 0x00000000 -#define XUSBPS_MODE_CM_DEVICE_MASK 0x00000002 -#define XUSBPS_MODE_CM_HOST_MASK 0x00000003 -#define XUSBPS_MODE_ES_MASK 0x00000004 /**< USB Endian Select */ -#define XUSBPS_MODE_SLOM_MASK 0x00000008 /**< USB Setup Lockout Mode Disable */ -#define XUSBPS_MODE_SDIS_MASK 0x00000010 -#define XUSBPS_MODE_VALID_MASK 0x0000001F - -/* @} */ - - -/** @name USB Device Address Register (DEVICEADDR) bit positions. - * @{ - */ -#define XUSBPS_DEVICEADDR_DEVICEAADV_MASK 0x01000000 - /**< Device Addr Auto Advance */ -#define XUSBPS_DEVICEADDR_ADDR_MASK 0xFE000000 - /**< Device Address */ -#define XUSBPS_DEVICEADDR_ADDR_SHIFT 25 - /**< Address shift */ -#define XUSBPS_DEVICEADDR_MAX 127 - /**< Biggest allowed address */ -/* @} */ - -/** @name USB TT Control Register (TTCTRL) bit positions. - * @{ - */ -#define XUSBPS_TTCTRL_HUBADDR_MASK 0x7F000000 /**< TT Hub Address */ -/* @} */ - - -/** @name USB Burst Size Register (BURSTSIZE) bit posisions. - * @{ - */ -#define XUSBPS_BURSTSIZE_RX_MASK 0x000000FF /**< RX Burst Length */ -#define XUSBPS_BURSTSIZE_TX_MASK 0x0000FF00 /**< TX Burst Length */ -/* @} */ - - -/** @name USB Tx Fill Tuning Register (TXFILL) bit positions. - * @{ - */ -#define XUSBPS_TXFILL_OVERHEAD_MASK 0x000000FF - /**< Scheduler Overhead */ -#define XUSBPS_TXFILL_HEALTH_MASK 0x00001F00 - /**< Scheduler Health Cntr */ -#define XUSBPS_TXFILL_BURST_MASK 0x003F0000 - /**< FIFO Burst Threshold */ -/* @} */ - - -/** @name USB ULPI Viewport Register (ULPIVIEW) bit positions. - * @{ - */ -#define XUSBPS_ULPIVIEW_DATWR_MASK 0x000000FF /**< ULPI Data Write */ -#define XUSBPS_ULPIVIEW_DATRD_MASK 0x0000FF00 /**< ULPI Data Read */ -#define XUSBPS_ULPIVIEW_ADDR_MASK 0x00FF0000 /**< ULPI Data Address */ -#define XUSBPS_ULPIVIEW_PORT_MASK 0x07000000 /**< ULPI Port Number */ -#define XUSBPS_ULPIVIEW_SS_MASK 0x08000000 /**< ULPI Synchronous State */ -#define XUSBPS_ULPIVIEW_RW_MASK 0x20000000 /**< ULPI Read/Write Control */ -#define XUSBPS_ULPIVIEW_RUN_MASK 0x40000000 /**< ULPI Run */ -#define XUSBPS_ULPIVIEW_WU_MASK 0x80000000 /**< ULPI Wakeup */ -/* @} */ - - -/** @name Port Status Control Register bit positions. - * @{ - */ -#define XUSBPS_PORTSCR_CCS_MASK 0x00000001 /**< Current Connect Status */ -#define XUSBPS_PORTSCR_CSC_MASK 0x00000002 /**< Connect Status Change */ -#define XUSBPS_PORTSCR_PE_MASK 0x00000004 /**< Port Enable/Disable */ -#define XUSBPS_PORTSCR_PEC_MASK 0x00000008 /**< Port Enable/Disable Change */ -#define XUSBPS_PORTSCR_OCA_MASK 0x00000010 /**< Over-current Active */ -#define XUSBPS_PORTSCR_OCC_MASK 0x00000020 /**< Over-current Change */ -#define XUSBPS_PORTSCR_FPR_MASK 0x00000040 /**< Force Port Resume */ -#define XUSBPS_PORTSCR_SUSP_MASK 0x00000080 /**< Suspend */ -#define XUSBPS_PORTSCR_PR_MASK 0x00000100 /**< Port Reset */ -#define XUSBPS_PORTSCR_HSP_MASK 0x00000200 /**< High Speed Port */ -#define XUSBPS_PORTSCR_LS_MASK 0x00000C00 /**< Line Status */ -#define XUSBPS_PORTSCR_PP_MASK 0x00001000 /**< Port Power */ -#define XUSBPS_PORTSCR_PO_MASK 0x00002000 /**< Port Owner */ -#define XUSBPS_PORTSCR_PIC_MASK 0x0000C000 /**< Port Indicator Control */ -#define XUSBPS_PORTSCR_PTC_MASK 0x000F0000 /**< Port Test Control */ -#define XUSBPS_PORTSCR_WKCN_MASK 0x00100000 /**< Wake on Connect Enable */ -#define XUSBPS_PORTSCR_WKDS_MASK 0x00200000 /**< Wake on Disconnect Enable */ -#define XUSBPS_PORTSCR_WKOC_MASK 0x00400000 /**< Wake on Over-current Enable */ -#define XUSBPS_PORTSCR_PHCD_MASK 0x00800000 /**< PHY Low Power Suspend - - * Clock Disable */ -#define XUSBPS_PORTSCR_PFSC_MASK 0x01000000 /**< Port Force Full Speed - * Connect */ -#define XUSBPS_PORTSCR_PSPD_MASK 0x0C000000 /**< Port Speed */ -/* @} */ - - -/** @name On-The-Go Status Control Register (OTGCSR) bit positions. - * @{ - */ -#define XUSBPS_OTGSC_VD_MASK 0x00000001 /**< VBus Discharge Bit */ -#define XUSBPS_OTGSC_VC_MASK 0x00000002 /**< VBus Charge Bit */ -#define XUSBPS_OTGSC_HAAR_MASK 0x00000004 /**< HW Assist Auto Reset - * Enable Bit */ -#define XUSBPS_OTGSC_OT_MASK 0x00000008 /**< OTG Termination Bit */ -#define XUSBPS_OTGSC_DP_MASK 0x00000010 /**< Data Pulsing Pull-up - * Enable Bit */ -#define XUSBPS_OTGSC_IDPU_MASK 0x00000020 /**< ID Pull-up Enable Bit */ -#define XUSBPS_OTGSC_HADP_MASK 0x00000040 /**< HW Assist Data Pulse - * Enable Bit */ -#define XUSBPS_OTGSC_HABA_MASK 0x00000080 /**< USB Hardware Assist - * B Disconnect to A - * Connect Enable Bit */ -#define XUSBPS_OTGSC_ID_MASK 0x00000100 /**< ID Status Flag */ -#define XUSBPS_OTGSC_AVV_MASK 0x00000200 /**< USB A VBus Valid Interrupt Status Flag */ -#define XUSBPS_OTGSC_ASV_MASK 0x00000400 /**< USB A Session Valid Interrupt Status Flag */ -#define XUSBPS_OTGSC_BSV_MASK 0x00000800 /**< USB B Session Valid Status Flag */ -#define XUSBPS_OTGSC_BSE_MASK 0x00001000 /**< USB B Session End Status Flag */ -#define XUSBPS_OTGSC_1MST_MASK 0x00002000 /**< USB 1 Millisecond Timer Status Flag */ -#define XUSBPS_OTGSC_DPS_MASK 0x00004000 /**< Data Pulse Status Flag */ -#define XUSBPS_OTGSC_IDIS_MASK 0x00010000 /**< USB ID Interrupt Status Flag */ -#define XUSBPS_OTGSC_AVVIS_MASK 0x00020000 /**< USB A VBus Valid Interrupt Status Flag */ -#define XUSBPS_OTGSC_ASVIS_MASK 0x00040000 /**< USB A Session Valid Interrupt Status Flag */ -#define XUSBPS_OTGSC_BSVIS_MASK 0x00080000 /**< USB B Session Valid Interrupt Status Flag */ -#define XUSBPS_OTGSC_BSEIS_MASK 0x00100000 /**< USB B Session End Interrupt Status Flag */ -#define XUSBPS_OTGSC_1MSS_MASK 0x00200000 /**< 1 Millisecond Timer Interrupt Status Flag */ -#define XUSBPS_OTGSC_DPIS_MASK 0x00400000 /**< Data Pulse Interrupt Status Flag */ -#define XUSBPS_OTGSC_IDIE_MASK 0x01000000 /**< ID Interrupt Enable Bit */ -#define XUSBPS_OTGSC_AVVIE_MASK 0x02000000 /**< USB A VBus Valid Interrupt Enable Bit */ -#define XUSBPS_OTGSC_ASVIE_MASK 0x04000000 /**< USB A Session Valid Interrupt Enable Bit */ -#define XUSBPS_OTGSC_BSVIE_MASK 0x08000000 /**< USB B Session Valid Interrupt Enable Bit */ -#define XUSBPS_OTGSC_BSEE_MASK 0x10000000 /**< USB B Session End Interrupt Enable Bit */ -#define XUSBPS_OTGSC_1MSE_MASK 0x20000000 /**< 1 Millisecond Timer - * Interrupt Enable Bit */ -#define XUSBPS_OTGSC_DPIE_MASK 0x40000000 /**< Data Pulse Interrupt - * Enable Bit */ - -#define XUSBPS_OTG_ISB_ALL (XUSBPS_OTGSC_IDIS_MASK |\ - XUSBPS_OTGSC_AVVIS_MASK | \ - XUSBPS_OTGSC_ASVIS_MASK | \ - XUSBPS_OTGSC_BSVIS_MASK | \ - XUSBPS_OTGSC_BSEIS_MASK | \ - XUSBPS_OTGSC_1MSS_MASK | \ - XUSBPS_OTGSC_DPIS_MASK) - /** Mask for All IRQ status masks */ - -#define XUSBPS_OTG_IEB_ALL (XUSBPS_OTGSC_IDIE_MASK |\ - XUSBPS_OTGSC_AVVIE_MASK | \ - XUSBPS_OTGSC_ASVIE_MASK | \ - XUSBPS_OTGSC_BSVIE_MASK | \ - XUSBPS_OTGSC_BSEE_IEB_MASK | \ - XUSBPS_OTGSC_1MSE_MASK | \ - XUSBPS_OTGSC_DPIE_MASK) - /** Mask for All IRQ Enable masks */ -/* @} */ - - -/**< Alignment of the Device Queue Head List BASE. */ -#define XUSBPS_dQH_BASE_ALIGN 2048 - -/**< Alignment of a Device Queue Head structure. */ -#define XUSBPS_dQH_ALIGN 64 - -/**< Alignment of a Device Transfer Descriptor structure. */ -#define XUSBPS_dTD_ALIGN 32 - -/**< Size of one RX buffer for a OUT Transfer Descriptor. */ -#define XUSBPS_dTD_BUF_SIZE 4096 - -/**< Maximum size of one RX/TX buffer. */ -#define XUSBPS_dTD_BUF_MAX_SIZE 16*1024 - -/**< Alignment requirement for Transfer Descriptor buffers. */ -#define XUSBPS_dTD_BUF_ALIGN 4096 - - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/****************************************************************************/ -/** -* -* This macro reads the given register. -* -* @param BaseAddress is the base address for the USB registers. -* @param RegOffset is the register offset to be read. -* -* @return The 32-bit value of the register. -* -* @note C-style signature: -* u32 XUsbPs_ReadReg(u32 BaseAddress, u32 RegOffset) -* -*****************************************************************************/ -#define XUsbPs_ReadReg(BaseAddress, RegOffset) \ - Xil_In32(BaseAddress + (RegOffset)) - - -/****************************************************************************/ -/** -* -* This macro writes the given register. -* -* @param BaseAddress is the the base address for the USB registers. -* @param RegOffset is the register offset to be written. -* @param Data is the the 32-bit value to write to the register. -* -* @return None. -* -* @note C-style signature: -* void XUsbPs_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) -* - *****************************************************************************/ -#define XUsbPs_WriteReg(BaseAddress, RegOffset, Data) \ - Xil_Out32(BaseAddress + (RegOffset), (Data)) - - -/************************** Function Prototypes ******************************/ -/* - * Perform reset operation to the USB PS interface - */ -void XUsbPs_ResetHw(u32 BaseAddress); -/************************** Variable Definitions ******************************/ - -#ifdef __cplusplus -} -#endif - -#endif /* XUSBPS_L_H */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/xusbps_intr.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/xusbps_intr.c deleted file mode 100644 index 96ce39f79bdc39888bb51c5df1e1b4bf370bec45..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/xusbps_intr.c +++ /dev/null @@ -1,476 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/******************************************************************************/ -/** - * @file xusbps_intr.c - * - * This file contains the functions that are related to interrupt processing - * for the EPB USB driver. - * - * <pre> - * MODIFICATION HISTORY: - * - * Ver Who Date Changes - * ----- ---- -------- ---------------------------------------------------------- - * 1.00a jz 10/10/10 First release - * 1.03a nm 09/21/12 Fixed CR#678977. Added proper sequence for setup packet - * handling. - * </pre> - ******************************************************************************/ - -/***************************** Include Files **********************************/ - -#include "xusbps.h" -#include "xusbps_endpoint.h" - -/************************** Constant Definitions ******************************/ - -/**************************** Type Definitions ********************************/ - -/***************** Macros (Inline Functions) Definitions **********************/ - -/************************** Variable Definitions ******************************/ - -/************************** Function Prototypes *******************************/ - -static void XUsbPs_IntrHandleTX(XUsbPs *InstancePtr, u32 EpCompl); -static void XUsbPs_IntrHandleRX(XUsbPs *InstancePtr, u32 EpCompl); -static void XUsbPs_IntrHandleReset(XUsbPs *InstancePtr, u32 IrqSts); -static void XUsbPs_IntrHandleEp0Setup(XUsbPs *InstancePtr); - -/*****************************************************************************/ -/** -* This function is the first-level interrupt handler for the USB core. All USB -* interrupts will be handled here. Depending on the type of the interrupt, -* second level interrupt handler may be called. Second level interrupt -* handlers will be registered by the user using the: -* XUsbPs_IntrSetHandler() -* and/or -* XUsbPs_EpSetHandler() -* functions. -* -* -* @param HandlerRef is a Reference passed to the interrupt register -* function. In our case this will be a pointer to the XUsbPs -* instance. -* -* @return None -* -* @note None -* -******************************************************************************/ -void XUsbPs_IntrHandler(void *HandlerRef) -{ - XUsbPs *InstancePtr; - - u32 IrqSts; - - Xil_AssertVoid(HandlerRef != NULL); - - InstancePtr = (XUsbPs *) HandlerRef; - - /* Handle controller (non-endpoint) related interrupts. */ - IrqSts = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - XUSBPS_ISR_OFFSET); - - /* Clear the interrupt status register. */ - XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, - XUSBPS_ISR_OFFSET, IrqSts); - - /* Nak interrupt, used to respond to host's IN request */ - if(IrqSts & XUSBPS_IXR_NAK_MASK) { - /* Ack the hardware */ - XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPNAKISR_OFFSET, - XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPNAKISR_OFFSET)); - } - - - /*************************************************************** - * - * Handle general interrupts. Endpoint interrupts will be handler - * later. - * - */ - - /* RESET interrupt.*/ - if (IrqSts & XUSBPS_IXR_UR_MASK) { - XUsbPs_IntrHandleReset(InstancePtr, IrqSts); - return; - } - - /* Check if we have a user handler that needs to be called. Note that - * this is the handler for general interrupts. Endpoint interrupts will - * be handled below. - */ - if ((IrqSts & InstancePtr->HandlerMask) && InstancePtr->HandlerFunc) { - (InstancePtr->HandlerFunc)(InstancePtr->HandlerRef, IrqSts); - } - - - /*************************************************************** - * - * Handle Endpoint interrupts. - * - */ - if (IrqSts & XUSBPS_IXR_UI_MASK) { - u32 EpStat; - u32 EpCompl; - - /* ENDPOINT 0 SETUP PACKET HANDLING - * - * Check if we got a setup packet on endpoint 0. Currently we - * only check for setup packets on endpoint 0 as we would not - * expect setup packets on any other endpoint (even though it - * is possible to send setup packets on other endpoints). - */ - EpStat = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPSTAT_OFFSET); - if (EpStat & 0x0001) { - /* Handle the setup packet */ - XUsbPs_IntrHandleEp0Setup(InstancePtr); - - /* Re-Prime the endpoint. - * Endpoint is de-primed if a setup packet comes in. - */ - XUsbPs_EpPrime(InstancePtr, 0, XUSBPS_EP_DIRECTION_OUT); - } - - /* Check for RX and TX complete interrupts. */ - EpCompl = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPCOMPL_OFFSET); - - - /* ACK the complete interrupts. */ - XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPCOMPL_OFFSET, EpCompl); - - /* Check OUT (RX) endpoints. */ - if (EpCompl & XUSBPS_EP_OUT_MASK) { - XUsbPs_IntrHandleRX(InstancePtr, EpCompl); - } - - /* Check IN (TX) endpoints. */ - if (EpCompl & XUSBPS_EP_IN_MASK) { - XUsbPs_IntrHandleTX(InstancePtr, EpCompl); - } - } -} - - -/*****************************************************************************/ -/** -* This function registers the user callback handler for controller -* (non-endpoint) interrupts. -* -* @param InstancePtr is a pointer to the XUsbPs instance of the -* controller. -* @param CallBackFunc is the Callback function to register. -* CallBackFunc may be NULL to clear the entry. -* @param CallBackRef is the user data reference passed to the -* callback function. CallBackRef may be NULL. -* @param Mask is the User interrupt mask. Defines which interrupts -* will cause the callback to be called. -* -* @return -* - XST_SUCCESS: Callback registered successfully. -* - XST_FAILURE: Callback could not be registered. -* -* @note None. -* -******************************************************************************/ -int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr, - XUsbPs_IntrHandlerFunc CallBackFunc, - void *CallBackRef, u32 Mask) -{ - Xil_AssertNonvoid(InstancePtr != NULL); - - InstancePtr->HandlerFunc = CallBackFunc; - InstancePtr->HandlerRef = CallBackRef; - InstancePtr->HandlerMask = Mask; - - return XST_SUCCESS; -} - - -/*****************************************************************************/ -/** -* This function handles TX buffer interrupts. It is called by the interrupt -* when a transmit complete interrupt occurs. It returns buffers of completed -* descriptors to the caller. -* -* @param InstancePtr is a pointer to the XUsbPs instance of the -* controller. -* @param EpCompl is the Bit mask of endpoints that caused a transmit -* complete interrupt. -* -* @return None -* -* @note None. -* -******************************************************************************/ -static void XUsbPs_IntrHandleTX(XUsbPs *InstancePtr, u32 EpCompl) -{ - int Index; - u32 Mask; - int NumEp; - - /* Check all endpoints for TX complete bits. - */ - Mask = 0x00010000; - NumEp = InstancePtr->DeviceConfig.NumEndpoints; - - /* Check for every endpoint if its TX complete bit is - * set. - */ - for (Index = 0; Index < NumEp; Index++, Mask <<= 1) { - XUsbPs_EpIn *Ep; - - if (!(EpCompl & Mask)) { - continue; - } - /* The TX complete bit for this endpoint is - * set. Walk the list of descriptors to see - * which ones are completed. - */ - Ep = &InstancePtr->DeviceConfig.Ep[Index].In; - while (Ep->dTDTail != Ep->dTDHead) { - - XUsbPs_dTDInvalidateCache(Ep->dTDTail); - - /* If the descriptor is not active then the buffer has - * not been sent yet. - */ - if (XUsbPs_dTDIsActive(Ep->dTDTail)) { - break; - } - - if (Ep->HandlerFunc) { - void *BufPtr; - - BufPtr = (void *) XUsbPs_ReaddTD(Ep->dTDTail, - XUSBPS_dTDUSERDATA); - - Ep->HandlerFunc(Ep->HandlerRef, Index, - XUSBPS_EP_EVENT_DATA_TX, - BufPtr); - } - - Ep->dTDTail = XUsbPs_dTDGetNLP(Ep->dTDTail); - } - } -} - - -/*****************************************************************************/ -/** - * This function handles RX buffer interrupts. It is called by the interrupt - * when a receive complete interrupt occurs. It notifies the callback functions - * that have been registered with the individual endpoints that data has been - * received. - * - * @param InstancePtr - * Pointer to the XUsbPs instance of the controller. - * - * @param EpCompl - * Bit mask of endpoints that caused a receive complete interrupt. - * @return - * none - * - ******************************************************************************/ -static void XUsbPs_IntrHandleRX(XUsbPs *InstancePtr, u32 EpCompl) -{ - XUsbPs_EpOut *Ep; - int Index; - u32 Mask; - int NumEp; - - /* Check all endpoints for RX complete bits. */ - Mask = 0x00000001; - NumEp = InstancePtr->DeviceConfig.NumEndpoints; - - - /* Check for every endpoint if its RX complete bit is set.*/ - for (Index = 0; Index < NumEp; Index++, Mask <<= 1) { - int numP = 0; - - if (!(EpCompl & Mask)) { - continue; - } - Ep = &InstancePtr->DeviceConfig.Ep[Index].Out; - - XUsbPs_dTDInvalidateCache(Ep->dTDCurr); - - /* Handle all finished dTDs */ - while (!XUsbPs_dTDIsActive(Ep->dTDCurr)) { - numP += 1; - if (Ep->HandlerFunc) { - Ep->HandlerFunc(Ep->HandlerRef, Index, - XUSBPS_EP_EVENT_DATA_RX, NULL); - } - - Ep->dTDCurr = XUsbPs_dTDGetNLP(Ep->dTDCurr); - XUsbPs_dTDInvalidateCache(Ep->dTDCurr); - } - /* Re-Prime the endpoint.*/ - XUsbPs_EpPrime(InstancePtr, Index, XUSBPS_EP_DIRECTION_OUT); - } -} - - -/*****************************************************************************/ -/** -* This function handles a RESET interrupt. It will notify the interrupt -* handler callback of the RESET condition. -* -* @param InstancePtr is pointer to the XUsbPs instance of the controller -* @param IrqSts is the Interrupt status register content. -* To be passed on to the user. -* -* @return None -* -* @Note None. -* -******************************************************************************/ -static void XUsbPs_IntrHandleReset(XUsbPs *InstancePtr, u32 IrqSts) -{ - int Timeout; - - /* Clear all setup token semaphores by reading the - * XUSBPS_EPSTAT_OFFSET register and writing its value back to - * itself. - */ - XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPSTAT_OFFSET, - XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPSTAT_OFFSET)); - - /* Clear all the endpoint complete status bits by reading the - * XUSBPS_EPCOMPL_OFFSET register and writings its value back - * to itself. - */ - XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPCOMPL_OFFSET, - XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPCOMPL_OFFSET)); - - /* Cancel all endpoint prime status by waiting until all bits - * in XUSBPS_EPPRIME_OFFSET are 0 and then writing 0xFFFFFFFF - * to XUSBPS_EPFLUSH_OFFSET. - * - * Avoid hanging here by using a Timeout counter... - */ - Timeout = XUSBPS_TIMEOUT_COUNTER; - while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPPRIME_OFFSET) & - XUSBPS_EP_ALL_MASK) && --Timeout) { - /* NOP */ - } - XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, - XUSBPS_EPFLUSH_OFFSET, 0xFFFFFFFF); - - /* Make sure that the reset bit in XUSBPS_PORTSCR1_OFFSET is - * still set at this point. If the code gets to this point and - * the reset bit has already been cleared we are in trouble and - * hardware reset is necessary. - */ - if (!(XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, - XUSBPS_PORTSCR1_OFFSET) & - XUSBPS_PORTSCR_PR_MASK)) { - /* Send a notification to the user that a hardware - * RESET is required. At this point we can only hope - * that the user registered an interrupt handler and - * will issue a hardware RESET. - */ - if (InstancePtr->HandlerFunc) { - (InstancePtr->HandlerFunc)(InstancePtr->HandlerRef, - IrqSts); - } - else { - for (;;); - } - - /* If we get here there is nothing more to do. The user - * should have reset the core. - */ - return; - } - - /* Check if we have a user handler that needs to be called. - */ - if (InstancePtr->HandlerFunc) { - (InstancePtr->HandlerFunc)(InstancePtr->HandlerRef, IrqSts); - } - - /* We are done. After RESET we don't proceed in the interrupt - * handler. - */ -} - - -/*****************************************************************************/ -/** -* This function handles a Setup Packet interrupt. It will notify the interrupt -* handler callback of the RESET condition. -* -* @param InstancePtr is a pointer to the XUsbPs instance of the -* controller. -* -* @return None -* -* @Note None -* -******************************************************************************/ -static void XUsbPs_IntrHandleEp0Setup(XUsbPs *InstancePtr) -{ - - XUsbPs_EpOut *Ep; - - /* Notifiy the user. */ - Ep = &InstancePtr->DeviceConfig.Ep[0].Out; - - if (Ep->HandlerFunc) { - Ep->HandlerFunc(Ep->HandlerRef, 0, - XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED, NULL); - } -} - - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/xusbps_sinit.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/xusbps_sinit.c deleted file mode 100644 index 7e218e94e068b56bfc098a24ceef019753692897..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/usbps_v1_05_a/src/xusbps_sinit.c +++ /dev/null @@ -1,105 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/****************************************************************************/ -/** - * - * @file xusbps_sinit.c - * - * The implementation of the XUsbPs driver's static initialzation - * functionality. - * - * <pre> - * MODIFICATION HISTORY: - * - * Ver Who Date Changes - * ----- ---- -------- ----------------------------------------------- - * 1.00a wgr 10/10/10 First release - * </pre> - * - *****************************************************************************/ - -/***************************** Include Files ********************************/ - -#include "xstatus.h" -#include "xusbps.h" -#include "xparameters.h" - -/************************** Constant Definitions ****************************/ - -/**************************** Type Definitions ******************************/ - -/***************** Macros (Inline Functions) Definitions ********************/ - -/************************** Variable Definitions ****************************/ - -extern XUsbPs_Config XUsbPs_ConfigTable[]; - -/************************** Function Prototypes *****************************/ - -/****************************************************************************/ -/** -* -* Looks up the controller configuration based on the unique controller ID. A -* table contains the configuration info for each controller in the system. -* -* @param DeviceID is the ID of the controller to look up the -* configuration for. -* -* @return -* A pointer to the configuration found or NULL if the specified -* controller ID was not found. -* -******************************************************************************/ -XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceID) -{ - XUsbPs_Config *CfgPtr = NULL; - - int Index; - - for (Index = 0; Index < XPAR_XUSBPS_NUM_INSTANCES; Index++) { - if (XUsbPs_ConfigTable[Index].DeviceID == DeviceID) { - CfgPtr = &XUsbPs_ConfigTable[Index]; - break; - } - } - - return CfgPtr; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v1_02_a/src/Makefile b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v1_02_a/src/Makefile deleted file mode 100644 index 96aeb0c5faeba9e014ea9814da78793feb656359..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v1_02_a/src/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -COMPILER= -ARCHIVER= -CP=cp -COMPILER_FLAGS= -EXTRA_COMPILER_FLAGS= -LIB=libxil.a - -CC_FLAGS = $(COMPILER_FLAGS) -ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) - -RELEASEDIR=../../../lib -INCLUDEDIR=../../../include -INCLUDES=-I./. -I${INCLUDEDIR} - -OUTS = *.o - -LIBSOURCES:=*.c -INCLUDEFILES:=*.h - -OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) - -libs: banner xadcps_libs clean - -%.o: %.c - ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< - -banner: - echo "Compiling xadcps" - -xadcps_libs: ${OBJECTS} - $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} - -.PHONY: include -include: xadcps_includes - -xadcps_includes: - ${CP} ${INCLUDEFILES} ${INCLUDEDIR} - -clean: - rm -rf ${OBJECTS} - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v1_02_a/src/xadcps.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v1_02_a/src/xadcps.c deleted file mode 100644 index 662b4c1ca30786c07f809ba0c46179e64598cbb4..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v1_02_a/src/xadcps.c +++ /dev/null @@ -1,1835 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file xadcps.c -* -* This file contains the driver API functions that can be used to access -* the XADC device. -* -* Refer to the xadcps.h header file for more information about this driver. -* -* @note None. -* -* <pre> -* -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ----- -------- ----------------------------------------------------- -* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver -* 1.01a bss 02/18/13 Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables -* XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs -* to fix CR #693371 -* </pre> -* -*****************************************************************************/ - -/***************************** Include Files ********************************/ - -#include "xadcps.h" - -/************************** Constant Definitions ****************************/ - -/**************************** Type Definitions ******************************/ - -/***************** Macros (Inline Functions) Definitions ********************/ - -/************************** Function Prototypes *****************************/ - -void XAdcPs_WriteInternalReg(XAdcPs *InstancePtr, u32 RegOffset, u32 Data); -u32 XAdcPs_ReadInternalReg(XAdcPs *InstancePtr, u32 RegOffset); - - -/************************** Variable Definitions ****************************/ - - -/*****************************************************************************/ -/** -* -* This function initializes a specific XAdcPs device/instance. This function -* must be called prior to using the XADC device. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* @param ConfigPtr points to the XAdcPs device configuration structure. -* @param EffectiveAddr is the device base address in the virtual memory -* address space. If the address translation is not used then the -* physical address is passed. -* Unexpected errors may occur if the address mapping is changed -* after this function is invoked. -* -* @return -* - XST_SUCCESS if successful. -* -* @note The user needs to first call the XAdcPs_LookupConfig() API -* which returns the Configuration structure pointer which is -* passed as a parameter to the XAdcPs_CfgInitialize() API. -* -******************************************************************************/ -int XAdcPs_CfgInitialize(XAdcPs *InstancePtr, XAdcPs_Config *ConfigPtr, - u32 EffectiveAddr) -{ - - u32 RegValue; - /* - * Assert the input arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(ConfigPtr != NULL); - - - /* - * Set the values read from the device config and the base address. - */ - InstancePtr->Config.DeviceId = ConfigPtr->DeviceId; - InstancePtr->Config.BaseAddress = EffectiveAddr; - - /* Write Unlock value to Device Config Unlock register */ - XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, - XADCPS_UNLK_OFFSET, XADCPS_UNLK_VALUE); - - /* Enable the PS access of xadc and set FIFO thresholds */ - - RegValue = XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress, - XADCPS_CFG_OFFSET); - - RegValue = RegValue | XADCPS_CFG_ENABLE_MASK | - XADCPS_CFG_CFIFOTH_MASK | XADCPS_CFG_DFIFOTH_MASK; - - XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, - XADCPS_CFG_OFFSET, RegValue); - - /* Release xadc from reset */ - - XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, - XADCPS_MCTL_OFFSET, 0x00); - - /* - * Indicate the instance is now ready to use and - * initialized without error. - */ - InstancePtr->IsReady = XIL_COMPONENT_IS_READY; - - return XST_SUCCESS; -} - - -/****************************************************************************/ -/** -* -* The functions sets the contents of the Config Register. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* @param Data is the 32 bit data to be written to the Register. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XAdcPs_SetConfigRegister(XAdcPs *InstancePtr, u32 Data) -{ - /* - * Assert the arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, - XADCPS_CFG_OFFSET, Data); - -} - - -/****************************************************************************/ -/** -* -* The functions reads the contents of the Config Register. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* -* @return A 32-bit value representing the contents of the Config Register. -* Use the XADCPS_SR_*_MASK constants defined in xadcps_hw.h to -* interpret the returned value. -* -* @note None. -* -*****************************************************************************/ -u32 XAdcPs_GetConfigRegister(XAdcPs *InstancePtr) -{ - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the Config Register and return the value. - */ - return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress, - XADCPS_CFG_OFFSET); -} - - -/****************************************************************************/ -/** -* -* The functions reads the contents of the Miscellaneous Status Register. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* -* @return A 32-bit value representing the contents of the Miscellaneous -* Status Register. Use the XADCPS_MSTS_*_MASK constants defined -* in xadcps_hw.h to interpret the returned value. -* -* @note None. -* -*****************************************************************************/ -u32 XAdcPs_GetMiscStatus(XAdcPs *InstancePtr) -{ - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the Miscellaneous Status Register and return the value. - */ - return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress, - XADCPS_MSTS_OFFSET); -} - - -/****************************************************************************/ -/** -* -* The functions sets the contents of the Miscellaneous Control register. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* @param Data is the 32 bit data to be written to the Register. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XAdcPs_SetMiscCtrlRegister(XAdcPs *InstancePtr, u32 Data) -{ - /* - * Assert the arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Write to the Miscellaneous control register Register. - */ - XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, - XADCPS_MCTL_OFFSET, Data); -} - - -/****************************************************************************/ -/** -* -* The functions reads the contents of the Miscellaneous control register. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* -* @return A 32-bit value representing the contents of the Config Register. -* Use the XADCPS_SR_*_MASK constants defined in xadcps_hw.h to -* interpret the returned value. -* -* @note None. -* -*****************************************************************************/ -u32 XAdcPs_GetMiscCtrlRegister(XAdcPs *InstancePtr) -{ - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the Miscellaneous control register and return the value. - */ - return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress, - XADCPS_MCTL_OFFSET); -} - - -/*****************************************************************************/ -/** -* -* This function resets the XADC Hard Macro in the device. -* -* @param InstancePtr is a pointer to the Xxadc instance. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void XAdcPs_Reset(XAdcPs *InstancePtr) -{ - /* - * Assert the arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Generate the reset by Control - * register and release from reset - */ - XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, - XADCPS_MCTL_OFFSET, 0x10); - XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, - XADCPS_MCTL_OFFSET, 0x00); -} - - -/****************************************************************************/ -/** -* -* Get the ADC converted data for the specified channel. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* @param Channel is the channel number. Use the XADCPS_CH_* defined in -* the file xadcps.h. -* The valid channels are -* - 0 to 6 -* - 13 to 31 -* -* @return A 16-bit value representing the ADC converted data for the -* specified channel. The XADC Monitor/ADC device guarantees -* a 10 bit resolution for the ADC converted data and data is the -* 10 MSB bits of the 16 data read from the device. -* -* @note The channels 7,8,9 are used for calibration of the device and -* hence there is no associated data with this channel. -* -*****************************************************************************/ -u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel) -{ - - u32 RegData; - - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid((Channel <= XADCPS_CH_VBRAM) || - ((Channel >= XADCPS_CH_VCCPINT) && - (Channel <= XADCPS_CH_AUX_MAX))); - - RegData = XAdcPs_ReadInternalReg(InstancePtr, - (XADCPS_TEMP_OFFSET + - Channel)); - return (u16) RegData; -} - -/****************************************************************************/ -/** -* -* This function gets the calibration coefficient data for the specified -* parameter. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* @param CoeffType specifies the calibration coefficient -* to be read. Use XADCPS_CALIB_* constants defined in xadcps.h to -* specify the calibration coefficient to be read. -* -* @return A 16-bit value representing the calibration coefficient. -* The XADC device guarantees a 10 bit resolution for -* the ADC converted data and data is the 10 MSB bits of the 16 -* data read from the device. -* -* @note None. -* -*****************************************************************************/ -u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType) -{ - u32 RegData; - - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(CoeffType <= XADCPS_CALIB_GAIN_ERROR_COEFF); - - /* - * Read the selected calibration coefficient. - */ - RegData = XAdcPs_ReadInternalReg(InstancePtr, - (XADCPS_ADC_A_SUPPLY_CALIB_OFFSET + - CoeffType)); - return (u16) RegData; -} - -/****************************************************************************/ -/** -* -* This function reads the Minimum/Maximum measurement for one of the -* specified parameters. Use XADCPS_MAX_* and XADCPS_MIN_* constants defined in -* xadcps.h to specify the parameters (Temperature, VccInt, VccAux, VBram, -* VccPInt, VccPAux and VccPDro). -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* @param MeasurementType specifies the parameter for which the -* Minimum/Maximum measurement has to be read. -* Use XADCPS_MAX_* and XADCPS_MIN_* constants defined in xadcps.h to -* specify the data to be read. -* -* @return A 16-bit value representing the maximum/minimum measurement for -* specified parameter. -* The XADC device guarantees a 10 bit resolution for -* the ADC converted data and data is the 10 MSB bits of the 16 -* data read from the device. -* -* @note None. -* -*****************************************************************************/ -u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType) -{ - u32 RegData; - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid((MeasurementType <= XADCPS_MAX_VCCPDRO) || - ((MeasurementType >= XADCPS_MIN_VCCPINT) && - (MeasurementType <= XADCPS_MIN_VCCPDRO))) - - /* - * Read and return the specified Minimum/Maximum measurement. - */ - RegData = XAdcPs_ReadInternalReg(InstancePtr, - (XADCPS_MAX_TEMP_OFFSET + - MeasurementType)); - return (u16) RegData; -} - -/****************************************************************************/ -/** -* -* This function sets the number of samples of averaging that is to be done for -* all the channels in both the single channel mode and sequence mode of -* operations. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* @param Average is the number of samples of averaging programmed to the -* Configuration Register 0. Use the XADCPS_AVG_* definitions defined -* in xadcps.h file : -* - XADCPS_AVG_0_SAMPLES for no averaging -* - XADCPS_AVG_16_SAMPLES for 16 samples of averaging -* - XADCPS_AVG_64_SAMPLES for 64 samples of averaging -* - XADCPS_AVG_256_SAMPLES for 256 samples of averaging -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average) -{ - u32 RegData; - - /* - * Assert the arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Average <= XADCPS_AVG_256_SAMPLES); - - /* - * Write the averaging value into the Configuration Register 0. - */ - RegData = XAdcPs_ReadInternalReg(InstancePtr, - XADCPS_CFR0_OFFSET) & - (~XADCPS_CFR0_AVG_VALID_MASK); - - RegData |= (((u32) Average << XADCPS_CFR0_AVG_SHIFT)); - XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET, - RegData); - -} - -/****************************************************************************/ -/** -* -* This function returns the number of samples of averaging configured for all -* the channels in the Configuration Register 0. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* -* @return The averaging read from the Configuration Register 0 is -* returned. Use the XADCPS_AVG_* bit definitions defined in -* xadcps.h file to interpret the returned value : -* - XADCPS_AVG_0_SAMPLES means no averaging -* - XADCPS_AVG_16_SAMPLES means 16 samples of averaging -* - XADCPS_AVG_64_SAMPLES means 64 samples of averaging -* - XADCPS_AVG_256_SAMPLES means 256 samples of averaging -* -* @note None. -* -*****************************************************************************/ -u8 XAdcPs_GetAvg(XAdcPs *InstancePtr) -{ - u32 Average; - - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the averaging value from the Configuration Register 0. - */ - Average = XAdcPs_ReadInternalReg(InstancePtr, - XADCPS_CFR0_OFFSET) & XADCPS_CFR0_AVG_VALID_MASK; - - - return ((u8) (Average >> XADCPS_CFR0_AVG_SHIFT)); -} - -/****************************************************************************/ -/** -* -* The function sets the given parameters in the Configuration Register 0 in -* the single channel mode. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* @param Channel is the channel number for the singel channel mode. -* The valid channels are 0 to 5, 8, and 16 to 31. -* If the external Mux is used then this specifies the channel -* oonnected to the external Mux. Please read the Device Spec -* to know which channels are valid. -* @param IncreaseAcqCycles is a boolean parameter which specifies whether -* the Acquisition time for the external channels has to be -* increased to 10 ADCCLK cycles (specify TRUE) or remain at the -* default 4 ADCCLK cycles (specify FALSE). This parameter is -* only valid for the external channels. -* @param IsDifferentialMode is a boolean parameter which specifies -* unipolar(specify FALSE) or differential mode (specify TRUE) for -* the analog inputs. The input mode is only valid for the -* external channels. -* -* @return -* - XST_SUCCESS if the given values were written successfully to -* the Configuration Register 0. -* - XST_FAILURE if the channel sequencer is enabled or the input -* parameters are not valid for the selected channel. -* -* @note -* - The number of samples for the averaging for all the channels -* is set by using the function XAdcPs_SetAvg. -* - The calibration of the device is done by doing a ADC -* conversion on the calibration channel(channel 8). The input -* parameters IncreaseAcqCycles, IsDifferentialMode and -* IsEventMode are not valid for this channel -* -* -*****************************************************************************/ -int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr, - u8 Channel, - int IncreaseAcqCycles, - int IsEventMode, - int IsDifferentialMode) -{ - u32 RegValue; - - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid((Channel <= XADCPS_CH_VREFN) || - (Channel == XADCPS_CH_ADC_CALIB) || - ((Channel >= XADCPS_CH_AUX_MIN) && - (Channel <= XADCPS_CH_AUX_MAX))); - Xil_AssertNonvoid((IncreaseAcqCycles == TRUE) || - (IncreaseAcqCycles == FALSE)); - Xil_AssertNonvoid((IsEventMode == TRUE) || (IsEventMode == FALSE)); - Xil_AssertNonvoid((IsDifferentialMode == TRUE) || - (IsDifferentialMode == FALSE)); - - /* - * Check if the device is in single channel mode else return failure - */ - if ((XAdcPs_GetSequencerMode(InstancePtr) != - XADCPS_SEQ_MODE_SINGCHAN)) { - return XST_FAILURE; - } - - /* - * Read the Configuration Register 0. - */ - RegValue = XAdcPs_ReadInternalReg(InstancePtr, - XADCPS_CFR0_OFFSET) & - XADCPS_CFR0_AVG_VALID_MASK; - - /* - * Select the number of acquisition cycles. The acquisition cycles is - * only valid for the external channels. - */ - if (IncreaseAcqCycles == TRUE) { - if (((Channel >= XADCPS_CH_AUX_MIN) && - (Channel <= XADCPS_CH_AUX_MAX)) || - (Channel == XADCPS_CH_VPVN)){ - RegValue |= XADCPS_CFR0_ACQ_MASK; - } else { - return XST_FAILURE; - } - - } - - /* - * Select the input mode. The input mode is only valid for the - * external channels. - */ - if (IsDifferentialMode == TRUE) { - - if (((Channel >= XADCPS_CH_AUX_MIN) && - (Channel <= XADCPS_CH_AUX_MAX)) || - (Channel == XADCPS_CH_VPVN)){ - RegValue |= XADCPS_CFR0_DU_MASK; - } else { - return XST_FAILURE; - } - } - - /* - * Select the ADC mode. - */ - if (IsEventMode == TRUE) { - RegValue |= XADCPS_CFR0_EC_MASK; - } - - /* - * Write the given values into the Configuration Register 0. - */ - RegValue |= (Channel & XADCPS_CFR0_CHANNEL_MASK); - XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET, - RegValue); - - return XST_SUCCESS; -} - -/****************************************************************************/ -/** -* -* This function enables the alarm outputs for the specified alarms in the -* Configuration Register 1. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* @param AlmEnableMask is the bit-mask of the alarm outputs to be enabled -* in the Configuration Register 1. -* Bit positions of 1 will be enabled. Bit positions of 0 will be -* disabled. This mask is formed by OR'ing XADCPS_CFR1_ALM_*_MASK and -* XADCPS_CFR1_OT_MASK masks defined in xadcps_hw.h. -* -* @return None. -* -* @note The implementation of the alarm enables in the Configuration -* register 1 is such that the alarms for bit positions of 1 will -* be disabled and alarms for bit positions of 0 will be enabled. -* The alarm outputs specified by the AlmEnableMask are negated -* before writing to the Configuration Register 1. -* -* -*****************************************************************************/ -void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask) -{ - u32 RegValue; - - /* - * Assert the arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - - RegValue = XAdcPs_ReadInternalReg(InstancePtr, XADCPS_CFR1_OFFSET); - - RegValue &= (u32)~XADCPS_CFR1_ALM_ALL_MASK; - RegValue |= (~AlmEnableMask & XADCPS_CFR1_ALM_ALL_MASK); - - /* - * Enable/disables the alarm enables for the specified alarm bits in the - * Configuration Register 1. - */ - XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET, - RegValue); -} - -/****************************************************************************/ -/** -* -* This function gets the status of the alarm output enables in the -* Configuration Register 1. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* -* @return This is the bit-mask of the enabled alarm outputs in the -* Configuration Register 1. Use the masks XADCPS_CFR1_ALM*_* and -* XADCPS_CFR1_OT_MASK defined in xadcps_hw.h to interpret the -* returned value. -* Bit positions of 1 indicate that the alarm output is enabled. -* Bit positions of 0 indicate that the alarm output is disabled. -* -* -* @note The implementation of the alarm enables in the Configuration -* register 1 is such that alarms for the bit positions of 1 will -* be disabled and alarms for bit positions of 0 will be enabled. -* The enabled alarm outputs returned by this function is the -* negated value of the the data read from the Configuration -* Register 1. -* -*****************************************************************************/ -u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr) -{ - u32 RegValue; - - /* - * Assert the arguments - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the status of alarm output enables from the Configuration - * Register 1. - */ - RegValue = XAdcPs_ReadInternalReg(InstancePtr, - XADCPS_CFR1_OFFSET) & XADCPS_CFR1_ALM_ALL_MASK; - return (u16) (~RegValue & XADCPS_CFR1_ALM_ALL_MASK); -} - -/****************************************************************************/ -/** -* -* This function enables the specified calibration in the Configuration -* Register 1 : -* -* - XADCPS_CFR1_CAL_ADC_OFFSET_MASK : Calibration 0 -ADC offset correction -* - XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK : Calibration 1 -ADC gain and offset -* correction -* - XADCPS_CFR1_CAL_PS_OFFSET_MASK : Calibration 2 -Power Supply sensor -* offset correction -* - XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK : Calibration 3 -Power Supply sensor -* gain and offset correction -* - XADCPS_CFR1_CAL_DISABLE_MASK : No Calibration -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* @param Calibration is the Calibration to be applied. -* Use XADCPS_CFR1_CAL*_* bits defined in xadcps_hw.h. -* Multiple calibrations can be enabled at a time by oring the -* XADCPS_CFR1_CAL_ADC_* and XADCPS_CFR1_CAL_PS_* bits. -* Calibration can be disabled by specifying - XADCPS_CFR1_CAL_DISABLE_MASK; -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration) -{ - u32 RegValue; - - /* - * Assert the arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(((Calibration >= XADCPS_CFR1_CAL_ADC_OFFSET_MASK) && - (Calibration <= XADCPS_CFR1_CAL_VALID_MASK)) || - (Calibration == XADCPS_CFR1_CAL_DISABLE_MASK)); - - /* - * Set the specified calibration in the Configuration Register 1. - */ - RegValue = XAdcPs_ReadInternalReg(InstancePtr, - XADCPS_CFR1_OFFSET); - - RegValue &= (~ XADCPS_CFR1_CAL_VALID_MASK); - RegValue |= (Calibration & XADCPS_CFR1_CAL_VALID_MASK); - XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET, - RegValue); - -} - -/****************************************************************************/ -/** -* -* This function reads the value of the calibration enables from the -* Configuration Register 1. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* -* @return The value of the calibration enables in the Configuration -* Register 1 : -* - XADCPS_CFR1_CAL_ADC_OFFSET_MASK : ADC offset correction -* - XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK : ADC gain and offset -* correction -* - XADCPS_CFR1_CAL_PS_OFFSET_MASK : Power Supply sensor offset -* correction -* - XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK : Power Supply sensor -* gain and offset correction -* - XADCPS_CFR1_CAL_DISABLE_MASK : No Calibration -* -* @note None. -* -*****************************************************************************/ -u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr) -{ - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the calibration enables from the Configuration Register 1. - */ - return (u16) XAdcPs_ReadInternalReg(InstancePtr, - XADCPS_CFR1_OFFSET) & XADCPS_CFR1_CAL_VALID_MASK; - -} - -/****************************************************************************/ -/** -* -* This function sets the specified Channel Sequencer Mode in the Configuration -* Register 1 : -* - Default safe mode (XADCPS_SEQ_MODE_SAFE) -* - One pass through sequence (XADCPS_SEQ_MODE_ONEPASS) -* - Continuous channel sequencing (XADCPS_SEQ_MODE_CONTINPASS) -* - Single Channel/Sequencer off (XADCPS_SEQ_MODE_SINGCHAN) -* - Simulataneous sampling mode (XADCPS_SEQ_MODE_SIMUL_SAMPLING) -* - Independent mode (XADCPS_SEQ_MODE_INDEPENDENT) -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* @param SequencerMode is the sequencer mode to be set. -* Use XADCPS_SEQ_MODE_* bits defined in xadcps.h. -* @return None. -* -* @note Only one of the modes can be enabled at a time. Please -* read the Spec of the XADC for further information about the -* sequencer modes. -* -* -*****************************************************************************/ -void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode) -{ - u32 RegValue; - - /* - * Assert the arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid((SequencerMode <= XADCPS_SEQ_MODE_SIMUL_SAMPLING) || - (SequencerMode == XADCPS_SEQ_MODE_INDEPENDENT)); - - /* - * Set the specified sequencer mode in the Configuration Register 1. - */ - RegValue = XAdcPs_ReadInternalReg(InstancePtr, - XADCPS_CFR1_OFFSET); - RegValue &= (~ XADCPS_CFR1_SEQ_VALID_MASK); - RegValue |= ((SequencerMode << XADCPS_CFR1_SEQ_SHIFT) & - XADCPS_CFR1_SEQ_VALID_MASK); - XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET, - RegValue); - -} - -/****************************************************************************/ -/** -* -* This function gets the channel sequencer mode from the Configuration -* Register 1. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* -* @return The channel sequencer mode : -* - XADCPS_SEQ_MODE_SAFE : Default safe mode -* - XADCPS_SEQ_MODE_ONEPASS : One pass through sequence -* - XADCPS_SEQ_MODE_CONTINPASS : Continuous channel sequencing -* - XADCPS_SEQ_MODE_SINGCHAN : Single channel/Sequencer off -* - XADCPS_SEQ_MODE_SIMUL_SAMPLING : Simulataneous sampling mode -* - XADCPS_SEQ_MODE_INDEPENDENT : Independent mode -* -* -* @note None. -* -*****************************************************************************/ -u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr) -{ - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the channel sequencer mode from the Configuration Register 1. - */ - return ((u8) ((XAdcPs_ReadInternalReg(InstancePtr, - XADCPS_CFR1_OFFSET) & XADCPS_CFR1_SEQ_VALID_MASK) >> - XADCPS_CFR1_SEQ_SHIFT)); - -} - -/****************************************************************************/ -/** -* -* The function sets the frequency of the ADCCLK by configuring the DCLK to -* ADCCLK ratio in the Configuration Register #2 -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* @param Divisor is clock divisor used to derive ADCCLK from DCLK. -* Valid values of the divisor are -* - 0 to 255. Values 0, 1, 2 are all mapped to 2. -* Refer to the device specification for more details -* -* @return None. -* -* @note - The ADCCLK is an internal clock used by the ADC and is -* synchronized to the DCLK clock. The ADCCLK is equal to DCLK -* divided by the user selection in the Configuration Register 2. -* - There is no Assert on the minimum value of the Divisor. -* -*****************************************************************************/ -void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor) -{ - /* - * Assert the arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Write the divisor value into the Configuration Register #2. - */ - XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR2_OFFSET, - Divisor << XADCPS_CFR2_CD_SHIFT); - -} - -/****************************************************************************/ -/** -* -* The function gets the ADCCLK divisor from the Configuration Register 2. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* -* @return The divisor read from the Configuration Register 2. -* -* @note The ADCCLK is an internal clock used by the ADC and is -* synchronized to the DCLK clock. The ADCCLK is equal to DCLK -* divided by the user selection in the Configuration Register 2. -* -*****************************************************************************/ -u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr) -{ - u16 Divisor; - - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the divisor value from the Configuration Register 2. - */ - Divisor = (u16) XAdcPs_ReadInternalReg(InstancePtr, - XADCPS_CFR2_OFFSET); - - return (u8) (Divisor >> XADCPS_CFR2_CD_SHIFT); -} - -/****************************************************************************/ -/** -* -* This function enables the specified channels in the ADC Channel Selection -* Sequencer Registers. The sequencer must be disabled before writing to these -* regsiters. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* @param ChEnableMask is the bit mask of all the channels to be enabled. -* Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the Channel -* numbers. Bit masks of 1 will be enabled and bit mask of 0 will -* be disabled. -* The ChEnableMask is a 32 bit mask that is written to the two -* 16 bit ADC Channel Selection Sequencer Registers. -* -* @return -* - XST_SUCCESS if the given values were written successfully to -* the ADC Channel Selection Sequencer Registers. -* - XST_FAILURE if the channel sequencer is enabled. -* -* @note None -* -*****************************************************************************/ -int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask) -{ - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * The sequencer must be disabled for writing any of these registers - * Return XST_FAILURE if the channel sequencer is enabled. - */ - if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) { - return XST_FAILURE; - } - - /* - * Enable the specified channels in the ADC Channel Selection Sequencer - * Registers. - */ - XAdcPs_WriteInternalReg(InstancePtr, - XADCPS_SEQ00_OFFSET, - (ChEnableMask & XADCPS_SEQ00_CH_VALID_MASK)); - - XAdcPs_WriteInternalReg(InstancePtr, - XADCPS_SEQ01_OFFSET, - (ChEnableMask >> XADCPS_SEQ_CH_AUX_SHIFT) & - XADCPS_SEQ01_CH_VALID_MASK); - - return XST_SUCCESS; -} - -/****************************************************************************/ -/** -* -* This function gets the channel enable bits status from the ADC Channel -* Selection Sequencer Registers. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* -* @return Gets the channel enable bits. Use XADCPS_SEQ_CH__* defined in -* xadcps_hw.h to interpret the Channel numbers. Bit masks of 1 -* are the channels that are enabled and bit mask of 0 are -* the channels that are disabled. -* -* @return None -* -* @note None -* -*****************************************************************************/ -u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr) -{ - u32 RegValEnable; - - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the channel enable bits for all the channels from the ADC - * Channel Selection Register. - */ - RegValEnable = XAdcPs_ReadInternalReg(InstancePtr, - XADCPS_SEQ00_OFFSET) & - XADCPS_SEQ00_CH_VALID_MASK; - RegValEnable |= (XAdcPs_ReadInternalReg(InstancePtr, - XADCPS_SEQ01_OFFSET) & - XADCPS_SEQ01_CH_VALID_MASK) << - XADCPS_SEQ_CH_AUX_SHIFT; - - - return RegValEnable; -} - -/****************************************************************************/ -/** -* -* This function enables the averaging for the specified channels in the ADC -* Channel Averaging Enable Sequencer Registers. The sequencer must be disabled -* before writing to these regsiters. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* @param AvgEnableChMask is the bit mask of all the channels for which -* averaging is to be enabled. Use XADCPS_SEQ_CH__* defined in -* xadcps_hw.h to specify the Channel numbers. Averaging will be -* enabled for bit masks of 1 and disabled for bit mask of 0. -* The AvgEnableChMask is a 32 bit mask that is written to the two -* 16 bit ADC Channel Averaging Enable Sequencer Registers. -* -* @return -* - XST_SUCCESS if the given values were written successfully to -* the ADC Channel Averaging Enables Sequencer Registers. -* - XST_FAILURE if the channel sequencer is enabled. -* -* @note None -* -*****************************************************************************/ -int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask) -{ - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * The sequencer must be disabled for writing any of these registers - * Return XST_FAILURE if the channel sequencer is enabled. - */ - if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) { - return XST_FAILURE; - } - - /* - * Enable/disable the averaging for the specified channels in the - * ADC Channel Averaging Enables Sequencer Registers. - */ - XAdcPs_WriteInternalReg(InstancePtr, - XADCPS_SEQ02_OFFSET, - (AvgEnableChMask & XADCPS_SEQ02_CH_VALID_MASK)); - - XAdcPs_WriteInternalReg(InstancePtr, - XADCPS_SEQ03_OFFSET, - (AvgEnableChMask >> XADCPS_SEQ_CH_AUX_SHIFT) & - XADCPS_SEQ03_CH_VALID_MASK); - - return XST_SUCCESS; -} - -/****************************************************************************/ -/** -* -* This function returns the channels for which the averaging has been enabled -* in the ADC Channel Averaging Enables Sequencer Registers. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* -* @returns The status of averaging (enabled/disabled) for all the channels. -* Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to interpret the -* Channel numbers. Bit masks of 1 are the channels for which -* averaging is enabled and bit mask of 0 are the channels for -* averaging is disabled -* -* @note None -* -*****************************************************************************/ -u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr) -{ - u32 RegValAvg; - - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the averaging enable status for all the channels from the - * ADC Channel Averaging Enables Sequencer Registers. - */ - RegValAvg = XAdcPs_ReadInternalReg(InstancePtr, - XADCPS_SEQ02_OFFSET) & XADCPS_SEQ02_CH_VALID_MASK; - RegValAvg |= (XAdcPs_ReadInternalReg(InstancePtr, - XADCPS_SEQ03_OFFSET) & XADCPS_SEQ03_CH_VALID_MASK) << - XADCPS_SEQ_CH_AUX_SHIFT; - - return RegValAvg; -} - -/****************************************************************************/ -/** -* -* This function sets the Analog input mode for the specified channels in the ADC -* Channel Analog-Input Mode Sequencer Registers. The sequencer must be disabled -* before writing to these regsiters. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* @param InputModeChMask is the bit mask of all the channels for which -* the input mode is differential mode. Use XADCPS_SEQ_CH__* defined -* in xadcps_hw.h to specify the channel numbers. Differential -* input mode will be set for bit masks of 1 and unipolar input -* mode for bit masks of 0. -* The InputModeChMask is a 32 bit mask that is written to the two -* 16 bit ADC Channel Analog-Input Mode Sequencer Registers. -* -* @return -* - XST_SUCCESS if the given values were written successfully to -* the ADC Channel Analog-Input Mode Sequencer Registers. -* - XST_FAILURE if the channel sequencer is enabled. -* -* @note None -* -*****************************************************************************/ -int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask) -{ - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * The sequencer must be disabled for writing any of these registers - * Return XST_FAILURE if the channel sequencer is enabled. - */ - if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) { - return XST_FAILURE; - } - - /* - * Set the input mode for the specified channels in the ADC Channel - * Analog-Input Mode Sequencer Registers. - */ - XAdcPs_WriteInternalReg(InstancePtr, - XADCPS_SEQ04_OFFSET, - (InputModeChMask & XADCPS_SEQ04_CH_VALID_MASK)); - - XAdcPs_WriteInternalReg(InstancePtr, - XADCPS_SEQ05_OFFSET, - (InputModeChMask >> XADCPS_SEQ_CH_AUX_SHIFT) & - XADCPS_SEQ05_CH_VALID_MASK); - - return XST_SUCCESS; -} - -/****************************************************************************/ -/** -* -* This function gets the Analog input mode for all the channels from -* the ADC Channel Analog-Input Mode Sequencer Registers. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* -* @returns The input mode for all the channels. -* Use XADCPS_SEQ_CH_* defined in xadcps_hw.h to interpret the -* Channel numbers. Bit masks of 1 are the channels for which -* input mode is differential and bit mask of 0 are the channels -* for which input mode is unipolar. -* -* @note None. -* -*****************************************************************************/ -u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr) -{ - u32 InputMode; - - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Get the input mode for all the channels from the ADC Channel - * Analog-Input Mode Sequencer Registers. - */ - InputMode = XAdcPs_ReadInternalReg(InstancePtr, - XADCPS_SEQ04_OFFSET) & - XADCPS_SEQ04_CH_VALID_MASK; - InputMode |= (XAdcPs_ReadInternalReg(InstancePtr, - XADCPS_SEQ05_OFFSET) & - XADCPS_SEQ05_CH_VALID_MASK) << - XADCPS_SEQ_CH_AUX_SHIFT; - - return InputMode; -} - -/****************************************************************************/ -/** -* -* This function sets the number of Acquisition cycles in the ADC Channel -* Acquisition Time Sequencer Registers. The sequencer must be disabled -* before writing to these regsiters. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* @param AcqCyclesChMask is the bit mask of all the channels for which -* the number of acquisition cycles is to be extended. -* Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the Channel -* numbers. Acquisition cycles will be extended to 10 ADCCLK cycles -* for bit masks of 1 and will be the default 4 ADCCLK cycles for -* bit masks of 0. -* The AcqCyclesChMask is a 32 bit mask that is written to the two -* 16 bit ADC Channel Acquisition Time Sequencer Registers. -* -* @return -* - XST_SUCCESS if the given values were written successfully to -* the Channel Sequencer Registers. -* - XST_FAILURE if the channel sequencer is enabled. -* -* @note None. -* -*****************************************************************************/ -int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask) -{ - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * The sequencer must be disabled for writing any of these registers - * Return XST_FAILURE if the channel sequencer is enabled. - */ - if ((XAdcPs_GetSequencerMode(InstancePtr) != - XADCPS_SEQ_MODE_SAFE)) { - return XST_FAILURE; - } - - /* - * Set the Acquisition time for the specified channels in the - * ADC Channel Acquisition Time Sequencer Registers. - */ - XAdcPs_WriteInternalReg(InstancePtr, - XADCPS_SEQ06_OFFSET, - (AcqCyclesChMask & XADCPS_SEQ06_CH_VALID_MASK)); - - XAdcPs_WriteInternalReg(InstancePtr, - XADCPS_SEQ07_OFFSET, - (AcqCyclesChMask >> XADCPS_SEQ_CH_AUX_SHIFT) & - XADCPS_SEQ07_CH_VALID_MASK); - - return XST_SUCCESS; -} - -/****************************************************************************/ -/** -* -* This function gets the status of acquisition from the ADC Channel Acquisition -* Time Sequencer Registers. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* -* @returns The acquisition time for all the channels. -* Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to interpret the -* Channel numbers. Bit masks of 1 are the channels for which -* acquisition cycles are extended and bit mask of 0 are the -* channels for which acquisition cycles are not extended. -* -* @note None -* -*****************************************************************************/ -u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr) -{ - u32 RegValAcq; - - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Get the Acquisition cycles for the specified channels from the ADC - * Channel Acquisition Time Sequencer Registers. - */ - RegValAcq = XAdcPs_ReadInternalReg(InstancePtr, - XADCPS_SEQ06_OFFSET) & - XADCPS_SEQ06_CH_VALID_MASK; - RegValAcq |= (XAdcPs_ReadInternalReg(InstancePtr, - XADCPS_SEQ07_OFFSET) & - XADCPS_SEQ07_CH_VALID_MASK) << - XADCPS_SEQ_CH_AUX_SHIFT; - - return RegValAcq; -} - -/****************************************************************************/ -/** -* -* This functions sets the contents of the given Alarm Threshold Register. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* @param AlarmThrReg is the index of an Alarm Threshold Register to -* be set. Use XADCPS_ATR_* constants defined in xadcps.h to -* specify the index. -* @param Value is the 16-bit threshold value to write into the register. -* -* @return None. -* -* @note Use XAdcPs_SetOverTemp() to set the Over Temperature upper -* threshold value. -* -*****************************************************************************/ -void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value) -{ - - /* - * Assert the arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(AlarmThrReg <= XADCPS_ATR_VCCPDRO_LOWER); - - /* - * Write the value into the specified Alarm Threshold Register. - */ - XAdcPs_WriteInternalReg(InstancePtr, XADCPS_ATR_TEMP_UPPER_OFFSET + - AlarmThrReg,Value); - -} - -/****************************************************************************/ -/** -* -* This function returns the contents of the specified Alarm Threshold Register. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* @param AlarmThrReg is the index of an Alarm Threshold Register -* to be read. Use XADCPS_ATR_* constants defined in xadcps_hw.h -* to specify the index. -* -* @return A 16-bit value representing the contents of the selected Alarm -* Threshold Register. -* -* @note None. -* -*****************************************************************************/ -u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg) -{ - u32 RegData; - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(AlarmThrReg <= XADCPS_ATR_VCCPDRO_LOWER); - - /* - * Read the specified Alarm Threshold Register and return - * the value - */ - RegData = XAdcPs_ReadInternalReg(InstancePtr, - (XADCPS_ATR_TEMP_UPPER_OFFSET + AlarmThrReg)); - - return (u16) RegData; -} - - -/****************************************************************************/ -/** -* -* This function enables programming of the powerdown temperature for the -* OverTemp signal in the OT Powerdown register. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr) -{ - u16 OtUpper; - - /* - * Assert the arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the OT upper Alarm Threshold Register. - */ - OtUpper = XAdcPs_ReadInternalReg(InstancePtr, - XADCPS_ATR_OT_UPPER_OFFSET); - OtUpper &= ~(XADCPS_ATR_OT_UPPER_ENB_MASK); - - /* - * Preserve the powerdown value and write OT enable value the into the - * OT Upper Alarm Threshold Register. - */ - OtUpper |= XADCPS_ATR_OT_UPPER_ENB_VAL; - XAdcPs_WriteInternalReg(InstancePtr, - XADCPS_ATR_OT_UPPER_OFFSET, OtUpper); -} - -/****************************************************************************/ -/** -* -* This function disables programming of the powerdown temperature for the -* OverTemp signal in the OT Powerdown register. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* -* @return None. -* -* @note None. -* -* -*****************************************************************************/ -void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr) -{ - u16 OtUpper; - - /* - * Assert the arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the OT Upper Alarm Threshold Register. - */ - OtUpper = XAdcPs_ReadInternalReg(InstancePtr, - XADCPS_ATR_OT_UPPER_OFFSET); - OtUpper &= ~(XADCPS_ATR_OT_UPPER_ENB_MASK); - - XAdcPs_WriteInternalReg(InstancePtr, - XADCPS_ATR_OT_UPPER_OFFSET, OtUpper); -} - - -/****************************************************************************/ -/** -* -* The function enables the Event mode or Continuous mode in the sequencer mode. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* @param IsEventMode is a boolean parameter that specifies continuous -* sampling (specify FALSE) or event driven sampling mode (specify -* TRUE) for the given channel. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode) -{ - u32 RegValue; - - /* - * Assert the arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid((IsEventMode == TRUE) || (IsEventMode == FALSE)); - - /* - * Read the Configuration Register 0. - */ - RegValue = XAdcPs_ReadInternalReg(InstancePtr, - XADCPS_CFR0_OFFSET) & - (~XADCPS_CFR0_EC_MASK); - - /* - * Set the ADC mode. - */ - if (IsEventMode == TRUE) { - RegValue |= XADCPS_CFR0_EC_MASK; - } else { - RegValue &= ~XADCPS_CFR0_EC_MASK; - } - - XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET, - RegValue); -} - - -/****************************************************************************/ -/** -* -* This function returns the sampling mode. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* -* @return The sampling mode -* - 0 specifies continuous sampling -* - 1 specifies event driven sampling mode -* -* @note None. -* -*****************************************************************************/ -int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr) -{ - u32 Mode; - - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the sampling mode from the Configuration Register 0. - */ - Mode = XAdcPs_ReadInternalReg(InstancePtr, - XADCPS_CFR0_OFFSET) & - XADCPS_CFR0_EC_MASK; - if (Mode) { - - return 1; - } - - return (0); -} - - -/****************************************************************************/ -/** -* -* This function sets the External Mux mode. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* @param MuxMode specifies whether External Mux is used -* - FALSE specifies NO external MUX -* - TRUE specifies External Mux is used -* @param Channel specifies the channel to be used for the -* external Mux. Please read the Device Spec for which -* channels are valid for which mode. -* -* @return None. -* -* @note There is no Assert in this function for checking the channel -* number if the external Mux is used. The user should provide a -* valid channel number. -* -*****************************************************************************/ -void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel) -{ - u32 RegValue; - - /* - * Assert the arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid((MuxMode == TRUE) || (MuxMode == FALSE)); - - /* - * Read the Configuration Register 0. - */ - RegValue = XAdcPs_ReadInternalReg(InstancePtr, - XADCPS_CFR0_OFFSET) & - (~XADCPS_CFR0_MUX_MASK); - /* - * Select the Mux mode and the channel to be used. - */ - if (MuxMode == TRUE) { - RegValue |= XADCPS_CFR0_MUX_MASK; - RegValue |= (Channel & XADCPS_CFR0_CHANNEL_MASK); - - } - - /* - * Write the mux mode into the Configuration Register 0. - */ - XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET, - RegValue); -} - - -/****************************************************************************/ -/** -* -* This function sets the Power Down mode. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* @param Mode specifies the Power Down Mode -* - XADCPS_PD_MODE_NONE specifies NO Power Down (Both ADC A and -* ADC B are enabled) -* - XADCPS_PD_MODE_ADCB specfies the Power Down of ADC B -* - XADCPS_PD_MODE_XADC specifies the Power Down of -* both ADC A and ADC B. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode) -{ - u32 RegValue; - - /* - * Assert the arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - Xil_AssertVoid(Mode < XADCPS_PD_MODE_XADC); - - - /* - * Read the Configuration Register 2. - */ - RegValue = XAdcPs_ReadInternalReg(InstancePtr, - XADCPS_CFR2_OFFSET) & - (~XADCPS_CFR2_PD_MASK); - /* - * Select the Power Down mode. - */ - RegValue |= (Mode << XADCPS_CFR2_PD_SHIFT); - - XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR2_OFFSET, - RegValue); -} - -/****************************************************************************/ -/** -* -* This function gets the Power Down mode. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* -* @return Mode specifies the Power Down Mode -* - XADCPS_PD_MODE_NONE specifies NO Power Down (Both ADC A and -* ADC B are enabled) -* - XADCPS_PD_MODE_ADCB specfies the Power Down of ADC B -* - XADCPS_PD_MODE_XADC specifies the Power Down of -* both ADC A and ADC B. -* -* @note None. -* -*****************************************************************************/ -u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr) -{ - u32 RegValue; - - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Read the Power Down Mode. - */ - RegValue = XAdcPs_ReadInternalReg(InstancePtr, - XADCPS_CFR2_OFFSET) & - (~XADCPS_CFR2_PD_MASK); - /* - * Return the Power Down mode. - */ - return (RegValue >> XADCPS_CFR2_PD_SHIFT); - -} - -/****************************************************************************/ -/** -* -* This function is used for writing to XADC Registers using the command FIFO. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* @param RegOffset is the offset of the XADC register to be written. -* @param Data is the data to be written. -* -* @return None. -* -* @note None. -* -* -*****************************************************************************/ -void XAdcPs_WriteInternalReg(XAdcPs *InstancePtr, u32 RegOffset, u32 Data) -{ - u32 RegData; - - /* - * Write the Data into the FIFO Register. - */ - RegData = XAdcPs_FormatWriteData(RegOffset, Data, TRUE); - - XAdcPs_WriteFifo(InstancePtr, RegData); - - /* Read the Read FIFO after any write since for each write - * one location of Read FIFO gets updated - */ - XAdcPs_ReadFifo(InstancePtr); - -} - - -/****************************************************************************/ -/** -* -* This function is used for reading from the XADC Registers using the Data FIFO. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* @param RegOffset is the offset of the XADC register to be read. -* -* @return Data read from the FIFO -* -* @note None. -* -* -*****************************************************************************/ -u32 XAdcPs_ReadInternalReg(XAdcPs *InstancePtr, u32 RegOffset) -{ - - u32 RegData; - - RegData = XAdcPs_FormatWriteData(RegOffset, 0x0, FALSE); - - /* Read cmd to FIFO*/ - XAdcPs_WriteFifo(InstancePtr, RegData); - - /* Do a Dummy read */ - RegData = XAdcPs_ReadFifo(InstancePtr); - - /* Do a Dummy write to get the actual read */ - XAdcPs_WriteFifo(InstancePtr, RegData); - - /* Do the Actual read */ - RegData = XAdcPs_ReadFifo(InstancePtr); - - return RegData; - -} - - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v1_02_a/src/xadcps.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v1_02_a/src/xadcps.h deleted file mode 100644 index 7c53621effb3bba8f941d69255d94b5925f8fac4..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v1_02_a/src/xadcps.h +++ /dev/null @@ -1,566 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file xadcps.h -* -* The XAdcPs driver supports the Xilinx XADC/ADC device. -* -* The XADC/ADC device has the following features: -* - 10-bit, 200-KSPS (kilo samples per second) -* Analog-to-Digital Converter (ADC) -* - Monitoring of on-chip supply voltages and temperature -* - 1 dedicated differential analog-input pair and -* 16 auxiliary differential analog-input pairs -* - Automatic alarms based on user defined limits for the on-chip -* supply voltages and temperature -* - Automatic Channel Sequencer, programmable averaging, programmable -* acquisition time for the external inputs, unipolar or differential -* input selection for the external inputs -* - Inbuilt Calibration -* - Optional interrupt request generation -* -* -* The user should refer to the hardware device specification for detailed -* information about the device. -* -* This header file contains the prototypes of driver functions that can -* be used to access the XADC/ADC device. -* -* -* <b> XADC Channel Sequencer Modes </b> -* -* The XADC Channel Sequencer supports the following operating modes: -* -* - <b> Default </b>: This is the default mode after power up. -* In this mode of operation the XADC operates in -* a sequence mode, monitoring the on chip sensors: -* Temperature, VCCINT, and VCCAUX. -* - <b> One pass through sequence </b>: In this mode the XADC -* converts the channels enabled in the Sequencer Channel Enable -* registers for a single pass and then stops. -* - <b> Continuous cycling of sequence </b>: In this mode the XADC -* converts the channels enabled in the Sequencer Channel Enable -* registers continuously. -* - <b> Single channel mode</b>: In this mode the XADC Channel -* Sequencer is disabled and the XADC operates in a -* Single Channel Mode. -* The XADC can operate either in a Continuous or Event -* driven sampling mode in the single channel mode. -* - <b> Simultaneous Sampling Mode</b>: In this mode the XADC Channel -* Sequencer will automatically sequence through eight fixed pairs -* of auxiliary analog input channels for simulataneous conversion. -* - <b> Independent ADC mode</b>: In this mode the first ADC (A) is used to -* is used to implement a fixed monitoring mode similar to the -* default mode but the alarm fucntions ar eenabled. -* The second ADC (B) is available to be used with external analog -* input channels only. -* -* Read the XADC spec for more information about the sequencer modes. -* -* <b> Initialization and Configuration </b> -* -* The device driver enables higher layer software (e.g., an application) to -* communicate to the XADC/ADC device. -* -* XAdcPs_CfgInitialize() API is used to initialize the XADC/ADC -* device. The user needs to first call the XAdcPs_LookupConfig() API which -* returns the Configuration structure pointer which is passed as a parameter to -* the XAdcPs_CfgInitialize() API. -* -* -* <b>Interrupts</b> -* -* The XADC/ADC device supports interrupt driven mode and the default -* operation mode is polling mode. -* -* The interrupt mode is available only if hardware is configured to support -* interrupts. -* -* This driver does not provide a Interrupt Service Routine (ISR) for the device. -* It is the responsibility of the application to provide one if needed. Refer to -* the interrupt example provided with this driver for details on using the -* device in interrupt mode. -* -* -* <b> Virtual Memory </b> -* -* This driver supports Virtual Memory. The RTOS is responsible for calculating -* the correct device base address in Virtual Memory space. -* -* -* <b> Threads </b> -* -* This driver is not thread safe. Any needs for threads or thread mutual -* exclusion must be satisfied by the layer above this driver. -* -* -* <b> Asserts </b> -* -* Asserts are used within all Xilinx drivers to enforce constraints on argument -* values. Asserts can be turned off on a system-wide basis by defining, at -* compile time, the NDEBUG identifier. By default, asserts are turned on and it -* is recommended that users leave asserts on during development. -* -* -* <b> Building the driver </b> -* -* The XAdcPs driver is composed of several source files. This allows the user -* to build and link only those parts of the driver that are necessary. -* -* <b> Limitations of the driver </b> -* -* XADC/ADC device can be accessed through the JTAG port and the PLB -* interface. The driver implementation does not support the simultaneous access -* of the device by both these interfaces. The user has to care of this situation -* in the user application code. -* -* <br><br> -* -* <pre> -* -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ----- -------- ----------------------------------------------------- -* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver -* 1.01a bss 02/18/13 Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables -* XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs -* in xadcps.c to fix CR #693371 -* </pre> -* -*****************************************************************************/ -#ifndef XADCPS_H /* Prevent circular inclusions */ -#define XADCPS_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files ********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xstatus.h" -#include "xadcps_hw.h" - -/************************** Constant Definitions ****************************/ - - -/** - * @name Indexes for the different channels. - * @{ - */ -#define XADCPS_CH_TEMP 0x0 /**< On Chip Temperature */ -#define XADCPS_CH_VCCINT 0x1 /**< VCCINT */ -#define XADCPS_CH_VCCAUX 0x2 /**< VCCAUX */ -#define XADCPS_CH_VPVN 0x3 /**< VP/VN Dedicated analog inputs */ -#define XADCPS_CH_VREFP 0x4 /**< VREFP */ -#define XADCPS_CH_VREFN 0x5 /**< VREFN */ -#define XADCPS_CH_VBRAM 0x6 /**< On-chip VBRAM Data Reg, 7 series */ -#define XADCPS_CH_SUPPLY_CALIB 0x07 /**< Supply Calib Data Reg */ -#define XADCPS_CH_ADC_CALIB 0x08 /**< ADC Offset Channel Reg */ -#define XADCPS_CH_GAINERR_CALIB 0x09 /**< Gain Error Channel Reg */ -#define XADCPS_CH_VCCPINT 0x0D /**< On-chip PS VCCPINT Channel , Zynq */ -#define XADCPS_CH_VCCPAUX 0x0E /**< On-chip PS VCCPAUX Channel , Zynq */ -#define XADCPS_CH_VCCPDRO 0x0F /**< On-chip PS VCCPDRO Channel , Zynq */ -#define XADCPS_CH_AUX_MIN 16 /**< Channel number for 1st Aux Channel */ -#define XADCPS_CH_AUX_MAX 31 /**< Channel number for Last Aux channel */ - -/*@}*/ - - -/** - * @name Indexes for reading the Calibration Coefficient Data. - * @{ - */ -#define XADCPS_CALIB_SUPPLY_COEFF 0 /**< Supply Offset Calib Coefficient */ -#define XADCPS_CALIB_ADC_COEFF 1 /**< ADC Offset Calib Coefficient */ -#define XADCPS_CALIB_GAIN_ERROR_COEFF 2 /**< Gain Error Calib Coefficient*/ -/*@}*/ - - -/** - * @name Indexes for reading the Minimum/Maximum Measurement Data. - * @{ - */ -#define XADCPS_MAX_TEMP 0 /**< Maximum Temperature Data */ -#define XADCPS_MAX_VCCINT 1 /**< Maximum VCCINT Data */ -#define XADCPS_MAX_VCCAUX 2 /**< Maximum VCCAUX Data */ -#define XADCPS_MAX_VBRAM 3 /**< Maximum VBRAM Data */ -#define XADCPS_MIN_TEMP 4 /**< Minimum Temperature Data */ -#define XADCPS_MIN_VCCINT 5 /**< Minimum VCCINT Data */ -#define XADCPS_MIN_VCCAUX 6 /**< Minimum VCCAUX Data */ -#define XADCPS_MIN_VBRAM 7 /**< Minimum VBRAM Data */ -#define XADCPS_MAX_VCCPINT 8 /**< Maximum VCCPINT Register , Zynq */ -#define XADCPS_MAX_VCCPAUX 9 /**< Maximum VCCPAUX Register , Zynq */ -#define XADCPS_MAX_VCCPDRO 0xA /**< Maximum VCCPDRO Register , Zynq */ -#define XADCPS_MIN_VCCPINT 0xC /**< Minimum VCCPINT Register , Zynq */ -#define XADCPS_MIN_VCCPAUX 0xD /**< Minimum VCCPAUX Register , Zynq */ -#define XADCPS_MIN_VCCPDRO 0xE /**< Minimum VCCPDRO Register , Zynq */ - -/*@}*/ - - -/** - * @name Alarm Threshold(Limit) Register (ATR) indexes. - * @{ - */ -#define XADCPS_ATR_TEMP_UPPER 0 /**< High user Temperature */ -#define XADCPS_ATR_VCCINT_UPPER 1 /**< VCCINT high voltage limit register */ -#define XADCPS_ATR_VCCAUX_UPPER 2 /**< VCCAUX high voltage limit register */ -#define XADCPS_ATR_OT_UPPER 3 /**< VCCAUX high voltage limit register */ -#define XADCPS_ATR_TEMP_LOWER 4 /**< Upper Over Temperature limit Reg */ -#define XADCPS_ATR_VCCINT_LOWER 5 /**< VCCINT high voltage limit register */ -#define XADCPS_ATR_VCCAUX_LOWER 6 /**< VCCAUX low voltage limit register */ -#define XADCPS_ATR_OT_LOWER 7 /**< Lower Over Temperature limit */ -#define XADCPS_ATR_VBRAM_UPPER_ 8 /**< VRBAM Upper Alarm Reg, 7 Series */ -#define XADCPS_ATR_VCCPINT_UPPER 9 /**< VCCPINT Upper Alarm Reg, Zynq */ -#define XADCPS_ATR_VCCPAUX_UPPER 0xA /**< VCCPAUX Upper Alarm Reg, Zynq */ -#define XADCPS_ATR_VCCPDRO_UPPER 0xB /**< VCCPDRO Upper Alarm Reg, Zynq */ -#define XADCPS_ATR_VBRAM_LOWER 0xC /**< VRBAM Lower Alarm Reg, 7 Series */ -#define XADCPS_ATR_VCCPINT_LOWER 0xD /**< VCCPINT Lower Alarm Reg , Zynq */ -#define XADCPS_ATR_VCCPAUX_LOWER 0xE /**< VCCPAUX Lower Alarm Reg , Zynq */ -#define XADCPS_ATR_VCCPDRO_LOWER 0xF /**< VCCPDRO Lower Alarm Reg , Zynq */ - -/*@}*/ - - -/** - * @name Averaging to be done for the channels. - * @{ - */ -#define XADCPS_AVG_0_SAMPLES 0 /**< No Averaging */ -#define XADCPS_AVG_16_SAMPLES 1 /**< Average 16 samples */ -#define XADCPS_AVG_64_SAMPLES 2 /**< Average 64 samples */ -#define XADCPS_AVG_256_SAMPLES 3 /**< Average 256 samples */ - -/*@}*/ - - -/** - * @name Channel Sequencer Modes of operation - * @{ - */ -#define XADCPS_SEQ_MODE_SAFE 0 /**< Default Safe Mode */ -#define XADCPS_SEQ_MODE_ONEPASS 1 /**< Onepass through Sequencer */ -#define XADCPS_SEQ_MODE_CONTINPASS 2 /**< Continuous Cycling Sequencer */ -#define XADCPS_SEQ_MODE_SINGCHAN 3 /**< Single channel -No Sequencing */ -#define XADCPS_SEQ_MODE_SIMUL_SAMPLING 4 /**< Simultaneous sampling */ -#define XADCPS_SEQ_MODE_INDEPENDENT 8 /**< Independent mode */ - -/*@}*/ - - - -/** - * @name Power Down Modes - * @{ - */ -#define XADCPS_PD_MODE_NONE 0 /**< No Power Down */ -#define XADCPS_PD_MODE_ADCB 1 /**< Power Down ADC B */ -#define XADCPS_PD_MODE_XADC 2 /**< Power Down ADC A and ADC B */ -/*@}*/ - -/**************************** Type Definitions ******************************/ - -/** - * This typedef contains configuration information for the XADC/ADC - * device. - */ -typedef struct { - u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddress; /**< Device base address */ -} XAdcPs_Config; - - -/** - * The driver's instance data. The user is required to allocate a variable - * of this type for every XADC/ADC device in the system. A pointer to - * a variable of this type is then passed to the driver API functions. - */ -typedef struct { - XAdcPs_Config Config; /**< XAdcPs_Config of current device */ - u32 IsReady; /**< Device is initialized and ready */ - -} XAdcPs; - -/***************** Macros (Inline Functions) Definitions ********************/ - -/****************************************************************************/ -/** -* -* This macro checks if the XADC device is in Event Sampling mode. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* -* @return -* - TRUE if the device is in Event Sampling Mode. -* - FALSE if the device is in Continuous Sampling Mode. -* -* @note C-Style signature: -* int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr); -* -*****************************************************************************/ -#define XAdcPs_IsEventSamplingModeSet(InstancePtr) \ - (((XAdcPs_ReadInternalReg(InstancePtr, \ - XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ? \ - TRUE : FALSE)) - - -/****************************************************************************/ -/** -* -* This macro checks if the XADC device is in External Mux mode. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* -* @return -* - TRUE if the device is in External Mux Mode. -* - FALSE if the device is NOT in External Mux Mode. -* -* @note C-Style signature: -* int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr); -* -*****************************************************************************/ -#define XAdcPs_IsExternalMuxModeSet(InstancePtr) \ - (((XAdcPs_ReadInternalReg(InstancePtr, \ - XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ? \ - TRUE : FALSE)) - -/****************************************************************************/ -/** -* -* This macro converts XADC Raw Data to Temperature(centigrades). -* -* @param AdcData is the Raw ADC Data from XADC. -* -* @return The Temperature in centigrades. -* -* @note C-Style signature: -* float XAdcPs_RawToTemperature(u32 AdcData); -* -*****************************************************************************/ -#define XAdcPs_RawToTemperature(AdcData) \ - ((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f) - -/****************************************************************************/ -/** -* -* This macro converts XADC/ADC Raw Data to Voltage(volts). -* -* @param AdcData is the XADC/ADC Raw Data. -* -* @return The Voltage in volts. -* -* @note C-Style signature: -* float XAdcPs_RawToVoltage(u32 AdcData); -* -*****************************************************************************/ -#define XAdcPs_RawToVoltage(AdcData) \ - ((((float)(AdcData))* (3.0f))/65536.0f) - -/****************************************************************************/ -/** -* -* This macro converts Temperature in centigrades to XADC/ADC Raw Data. -* -* @param Temperature is the Temperature in centigrades to be -* converted to XADC/ADC Raw Data. -* -* @return The XADC/ADC Raw Data. -* -* @note C-Style signature: -* int XAdcPs_TemperatureToRaw(float Temperature); -* -*****************************************************************************/ -#define XAdcPs_TemperatureToRaw(Temperature) \ - ((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f)) - -/****************************************************************************/ -/** -* -* This macro converts Voltage in Volts to XADC/ADC Raw Data. -* -* @param Voltage is the Voltage in volts to be converted to -* XADC/ADC Raw Data. -* -* @return The XADC/ADC Raw Data. -* -* @note C-Style signature: -* int XAdcPs_VoltageToRaw(float Voltage); -* -*****************************************************************************/ -#define XAdcPs_VoltageToRaw(Voltage) \ - ((int)((Voltage)*65536.0f/3.0f)) - - -/****************************************************************************/ -/** -* -* This macro is used for writing to the XADC Registers using the -* command FIFO. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* -* @return None. -* -* @note C-Style signature: -* void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data); -* -*****************************************************************************/ -#define XAdcPs_WriteFifo(InstancePtr, Data) \ - XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, \ - XADCPS_CMDFIFO_OFFSET, Data); - - -/****************************************************************************/ -/** -* -* This macro is used for reading from the XADC Registers using the -* data FIFO. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* -* @return Data read from the FIFO -* -* @note C-Style signature: -* u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr); -* -*****************************************************************************/ -#define XAdcPs_ReadFifo(InstancePtr) \ - XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress, \ - XADCPS_RDFIFO_OFFSET); - - -/************************** Function Prototypes *****************************/ - - - -/** - * Functions in xadcps_sinit.c - */ -XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId); - -/** - * Functions in xadcps.c - */ -int XAdcPs_CfgInitialize(XAdcPs *InstancePtr, - XAdcPs_Config *ConfigPtr, - u32 EffectiveAddr); - - -u32 XAdcPs_GetStatus(XAdcPs *InstancePtr); - -u32 XAdcPs_GetAlarmOutputStatus(XAdcPs *InstancePtr); - -void XAdcPs_StartAdcConversion(XAdcPs *InstancePtr); - -void XAdcPs_Reset(XAdcPs *InstancePtr); - -u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel); - -u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType); - -u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType); - -void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average); -u8 XAdcPs_GetAvg(XAdcPs *InstancePtr); - -int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr, - u8 Channel, - int IncreaseAcqCycles, - int IsEventMode, - int IsDifferentialMode); - - -void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask); -u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr); - -void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration); -u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr); - -void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode); -u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr); - -void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor); -u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr); - -int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask); -u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr); - -int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask); -u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr); - -int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask); -u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr); - -int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask); -u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr); - -void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value); -u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg); - -void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr); -void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr); - -/** - * Functions in xadcps_selftest.c - */ -int XAdcPs_SelfTest(XAdcPs *InstancePtr); - -/** - * Functions in xadcps_intr.c - */ -void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask); -void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask); -u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr); - -u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr); -void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask); - - -#ifdef __cplusplus -} -#endif - -#endif /* End of protection macro. */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v1_02_a/src/xadcps_g.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v1_02_a/src/xadcps_g.c deleted file mode 100644 index ee803820ef6aa6020453a53a5f8e68acd94548b6..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v1_02_a/src/xadcps_g.c +++ /dev/null @@ -1,30 +0,0 @@ - -/******************************************************************* -* -* CAUTION: This file is automatically generated by libgen. -* Version: Xilinx EDK 14.7 EDK_P.20131013 -* DO NOT EDIT. -* -* Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. - -* -* Description: Driver configuration -* -*******************************************************************/ - -#include "xparameters.h" -#include "xadcps.h" - -/* -* The configuration table for devices -*/ - -XAdcPs_Config XAdcPs_ConfigTable[] = -{ - { - XPAR_PS7_XADC_0_DEVICE_ID, - XPAR_PS7_XADC_0_BASEADDR - } -}; - - diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v1_02_a/src/xadcps_hw.h b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v1_02_a/src/xadcps_hw.h deleted file mode 100644 index 75054277442ffdd3621266f56bcf3e97b77f2955..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v1_02_a/src/xadcps_hw.h +++ /dev/null @@ -1,506 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file xadcps_hw.h -* -* This header file contains identifiers and basic driver functions (or -* macros) that can be used to access the XADC device through the Device -* Config Interface of the Zynq. -* -* -* Refer to the device specification for more information about this driver. -* -* @note None. -* -* -* <pre> -* -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ----- -------- ----------------------------------------------------- -* 1.00a bss 12/22/11 First release based on the XPS/AXI xadc driver -* -* </pre> -* -*****************************************************************************/ -#ifndef XADCPS_HW_H /* Prevent circular inclusions */ -#define XADCPS_HW_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files ********************************/ - -#include "xil_types.h" -#include "xil_assert.h" -#include "xil_io.h" - -/************************** Constant Definitions ****************************/ - - -/**@name Register offsets of XADC in the Device Config - * - * The following constants provide access to each of the registers of the - * XADC device. - * @{ - */ - -#define XADCPS_CFG_OFFSET 0x100 /**< Configuration Register */ -#define XADCPS_INT_STS_OFFSET 0x104 /**< Interrupt Status Register */ -#define XADCPS_INT_MASK_OFFSET 0x108 /**< Interrupt Mask Register */ -#define XADCPS_MSTS_OFFSET 0x10C /**< Misc status register */ -#define XADCPS_CMDFIFO_OFFSET 0x110 /**< Command FIFO Register */ -#define XADCPS_RDFIFO_OFFSET 0x114 /**< Read FIFO Register */ -#define XADCPS_MCTL_OFFSET 0x118 /**< Misc control register */ - -/* @} */ - - - - - -/** @name XADC Config Register Bit definitions - * @{ - */ -#define XADCPS_CFG_ENABLE_MASK 0x80000000 /**< Enable access from PS mask */ -#define XADCPS_CFG_CFIFOTH_MASK 0x00F00000 /**< Command FIFO Threshold mask */ -#define XADCPS_CFG_DFIFOTH_MASK 0x000F0000 /**< Data FIFO Threshold mask */ -#define XADCPS_CFG_WEDGE_MASK 0x00002000 /**< Write Edge Mask */ -#define XADCPS_CFG_REDGE_MASK 0x00001000 /**< Read Edge Mask */ -#define XADCPS_CFG_TCKRATE_MASK 0x00000300 /**< Clock freq control */ -#define XADCPS_CFG_IGAP_MASK 0x0000001F /**< Idle Gap between - * successive commands */ -/* @} */ - - -/** @name XADC Interrupt Status/Mask Register Bit definitions - * - * The definitions are same for the Interrupt Status Register and - * Interrupt Mask Register. They are defined only once. - * @{ - */ -#define XADCPS_INTX_ALL_MASK 0x000003FF /**< Alarm Signals Mask */ -#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200 /**< CMD FIFO less than threshold */ -#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100 /**< Data FIFO greater than threshold */ -#define XADCPS_INTX_OT_MASK 0x00000080 /**< Over temperature Alarm Status */ -#define XADCPS_INTX_ALM_ALL_MASK 0x0000007F /**< Alarm Signals Mask */ -#define XADCPS_INTX_ALM6_MASK 0x00000040 /**< Alarm 6 Mask */ -#define XADCPS_INTX_ALM5_MASK 0x00000020 /**< Alarm 5 Mask */ -#define XADCPS_INTX_ALM4_MASK 0x00000010 /**< Alarm 4 Mask */ -#define XADCPS_INTX_ALM3_MASK 0x00000008 /**< Alarm 3 Mask */ -#define XADCPS_INTX_ALM2_MASK 0x00000004 /**< Alarm 2 Mask */ -#define XADCPS_INTX_ALM1_MASK 0x00000002 /**< Alarm 1 Mask */ -#define XADCPS_INTX_ALM0_MASK 0x00000001 /**< Alarm 0 Mask */ - -/* @} */ - - -/** @name XADC Miscellaneous Register Bit definitions - * @{ - */ -#define XADCPS_MSTS_CFIFO_LVL_MASK 0x000F0000 /**< Command FIFO Level mask */ -#define XADCPS_MSTS_DFIFO_LVL_MASK 0x0000F000 /**< Data FIFO Level Mask */ -#define XADCPS_MSTS_CFIFOF_MASK 0x00000800 /**< Command FIFO Full Mask */ -#define XADCPS_MSTS_CFIFOE_MASK 0x00000400 /**< Command FIFO Empty Mask */ -#define XADCPS_MSTS_DFIFOF_MASK 0x00000200 /**< Data FIFO Full Mask */ -#define XADCPS_MSTS_DFIFOE_MASK 0x00000100 /**< Data FIFO Empty Mask */ -#define XADCPS_MSTS_OT_MASK 0x00000080 /**< Over Temperature Mask */ -#define XADCPS_MSTS_ALM_MASK 0x0000007F /**< Alarms Mask */ -/* @} */ - - -/** @name XADC Miscellaneous Control Register Bit definitions - * @{ - */ -#define XADCPS_MCTL_RESET_MASK 0x00000010 /**< Reset XADC */ -#define XADCPS_MCTL_FLUSH_MASK 0x00000001 /**< Flush the FIFOs */ -/* @} */ - - -/**@name Internal Register offsets of the XADC - * - * The following constants provide access to each of the internal registers of - * the XADC device. - * @{ - */ - -/* - * XADC Internal Channel Registers - */ -#define XADCPS_TEMP_OFFSET 0x00 /**< On-chip Temperature Reg */ -#define XADCPS_VCCINT_OFFSET 0x01 /**< On-chip VCCINT Data Reg */ -#define XADCPS_VCCAUX_OFFSET 0x02 /**< On-chip VCCAUX Data Reg */ -#define XADCPS_VPVN_OFFSET 0x03 /**< ADC out of VP/VN */ -#define XADCPS_VREFP_OFFSET 0x04 /**< On-chip VREFP Data Reg */ -#define XADCPS_VREFN_OFFSET 0x05 /**< On-chip VREFN Data Reg */ -#define XADCPS_VBRAM_OFFSET 0x06 /**< On-chip VBRAM , 7 Series */ -#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET 0x08 /**< ADC A Supply Offset Reg */ -#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET 0x09 /**< ADC A Offset Data Reg */ -#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0A /**< ADC A Gain Error Reg */ -#define XADCPS_VCCPINT_OFFSET 0x0D /**< On-chip VCCPINT Reg, Zynq */ -#define XADCPS_VCCPAUX_OFFSET 0x0E /**< On-chip VCCPAUX Reg, Zynq */ -#define XADCPS_VCCPDRO_OFFSET 0x0F /**< On-chip VCCPDRO Reg, Zynq */ - -/* - * XADC External Channel Registers - */ -#define XADCPS_AUX00_OFFSET 0x10 /**< ADC out of VAUXP0/VAUXN0 */ -#define XADCPS_AUX01_OFFSET 0x11 /**< ADC out of VAUXP1/VAUXN1 */ -#define XADCPS_AUX02_OFFSET 0x12 /**< ADC out of VAUXP2/VAUXN2 */ -#define XADCPS_AUX03_OFFSET 0x13 /**< ADC out of VAUXP3/VAUXN3 */ -#define XADCPS_AUX04_OFFSET 0x14 /**< ADC out of VAUXP4/VAUXN4 */ -#define XADCPS_AUX05_OFFSET 0x15 /**< ADC out of VAUXP5/VAUXN5 */ -#define XADCPS_AUX06_OFFSET 0x16 /**< ADC out of VAUXP6/VAUXN6 */ -#define XADCPS_AUX07_OFFSET 0x17 /**< ADC out of VAUXP7/VAUXN7 */ -#define XADCPS_AUX08_OFFSET 0x18 /**< ADC out of VAUXP8/VAUXN8 */ -#define XADCPS_AUX09_OFFSET 0x19 /**< ADC out of VAUXP9/VAUXN9 */ -#define XADCPS_AUX10_OFFSET 0x1A /**< ADC out of VAUXP10/VAUXN10 */ -#define XADCPS_AUX11_OFFSET 0x1B /**< ADC out of VAUXP11/VAUXN11 */ -#define XADCPS_AUX12_OFFSET 0x1C /**< ADC out of VAUXP12/VAUXN12 */ -#define XADCPS_AUX13_OFFSET 0x1D /**< ADC out of VAUXP13/VAUXN13 */ -#define XADCPS_AUX14_OFFSET 0x1E /**< ADC out of VAUXP14/VAUXN14 */ -#define XADCPS_AUX15_OFFSET 0x1F /**< ADC out of VAUXP15/VAUXN15 */ - -/* - * XADC Registers for Maximum/Minimum data captured for the - * on chip Temperature/VCCINT/VCCAUX data. - */ -#define XADCPS_MAX_TEMP_OFFSET 0x20 /**< Max Temperature Reg */ -#define XADCPS_MAX_VCCINT_OFFSET 0x21 /**< Max VCCINT Register */ -#define XADCPS_MAX_VCCAUX_OFFSET 0x22 /**< Max VCCAUX Register */ -#define XADCPS_MAX_VCCBRAM_OFFSET 0x23 /**< Max BRAM Register, 7 series */ -#define XADCPS_MIN_TEMP_OFFSET 0x24 /**< Min Temperature Reg */ -#define XADCPS_MIN_VCCINT_OFFSET 0x25 /**< Min VCCINT Register */ -#define XADCPS_MIN_VCCAUX_OFFSET 0x26 /**< Min VCCAUX Register */ -#define XADCPS_MIN_VCCBRAM_OFFSET 0x27 /**< Min BRAM Register, 7 series */ -#define XADCPS_MAX_VCCPINT_OFFSET 0x28 /**< Max VCCPINT Register, Zynq */ -#define XADCPS_MAX_VCCPAUX_OFFSET 0x29 /**< Max VCCPAUX Register, Zynq */ -#define XADCPS_MAX_VCCPDRO_OFFSET 0x2A /**< Max VCCPDRO Register, Zynq */ -#define XADCPS_MIN_VCCPINT_OFFSET 0x2C /**< Min VCCPINT Register, Zynq */ -#define XADCPS_MIN_VCCPAUX_OFFSET 0x2D /**< Min VCCPAUX Register, Zynq */ -#define XADCPS_MIN_VCCPDRO_OFFSET 0x2E /**< Min VCCPDRO Register,Zynq */ - /* Undefined 0x2F to 0x3E */ -#define XADCPS_FLAG_OFFSET 0x3F /**< Flag Register */ - -/* - * XADC Configuration Registers - */ -#define XADCPS_CFR0_OFFSET 0x40 /**< Configuration Register 0 */ -#define XADCPS_CFR1_OFFSET 0x41 /**< Configuration Register 1 */ -#define XADCPS_CFR2_OFFSET 0x42 /**< Configuration Register 2 */ - -/* Test Registers 0x43 to 0x47 */ - -/* - * XADC Sequence Registers - */ -#define XADCPS_SEQ00_OFFSET 0x48 /**< Seq Reg 00 Adc Channel Selection */ -#define XADCPS_SEQ01_OFFSET 0x49 /**< Seq Reg 01 Adc Channel Selection */ -#define XADCPS_SEQ02_OFFSET 0x4A /**< Seq Reg 02 Adc Average Enable */ -#define XADCPS_SEQ03_OFFSET 0x4B /**< Seq Reg 03 Adc Average Enable */ -#define XADCPS_SEQ04_OFFSET 0x4C /**< Seq Reg 04 Adc Input Mode Select */ -#define XADCPS_SEQ05_OFFSET 0x4D /**< Seq Reg 05 Adc Input Mode Select */ -#define XADCPS_SEQ06_OFFSET 0x4E /**< Seq Reg 06 Adc Acquisition Select */ -#define XADCPS_SEQ07_OFFSET 0x4F /**< Seq Reg 07 Adc Acquisition Select */ - -/* - * XADC Alarm Threshold/Limit Registers (ATR) - */ -#define XADCPS_ATR_TEMP_UPPER_OFFSET 0x50 /**< Temp Upper Alarm Register */ -#define XADCPS_ATR_VCCINT_UPPER_OFFSET 0x51 /**< VCCINT Upper Alarm Reg */ -#define XADCPS_ATR_VCCAUX_UPPER_OFFSET 0x52 /**< VCCAUX Upper Alarm Reg */ -#define XADCPS_ATR_OT_UPPER_OFFSET 0x53 /**< Over Temp Upper Alarm Reg */ -#define XADCPS_ATR_TEMP_LOWER_OFFSET 0x54 /**< Temp Lower Alarm Register */ -#define XADCPS_ATR_VCCINT_LOWER_OFFSET 0x55 /**< VCCINT Lower Alarm Reg */ -#define XADCPS_ATR_VCCAUX_LOWER_OFFSET 0x56 /**< VCCAUX Lower Alarm Reg */ -#define XADCPS_ATR_OT_LOWER_OFFSET 0x57 /**< Over Temp Lower Alarm Reg */ -#define XADCPS_ATR_VBRAM_UPPER_OFFSET 0x58 /**< VBRAM Upper Alarm, 7 series */ -#define XADCPS_ATR_VCCPINT_UPPER_OFFSET 0x59 /**< VCCPINT Upper Alarm, Zynq */ -#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET 0x5A /**< VCCPAUX Upper Alarm, Zynq */ -#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET 0x5B /**< VCCPDRO Upper Alarm, Zynq */ -#define XADCPS_ATR_VBRAM_LOWER_OFFSET 0x5C /**< VRBAM Lower Alarm, 7 Series */ -#define XADCPS_ATR_VCCPINT_LOWER_OFFSET 0x5D /**< VCCPINT Lower Alarm, Zynq */ -#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET 0x5E /**< VCCPAUX Lower Alarm, Zynq */ -#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET 0x5F /**< VCCPDRO Lower Alarm, Zynq */ - -/* Undefined 0x60 to 0x7F */ - -/*@}*/ - - - -/** - * @name Configuration Register 0 (CFR0) mask(s) - * @{ - */ -#define XADCPS_CFR0_CAL_AVG_MASK 0x8000 /**< Averaging enable Mask */ -#define XADCPS_CFR0_AVG_VALID_MASK 0x3000 /**< Averaging bit Mask */ -#define XADCPS_CFR0_AVG1_MASK 0x0000 /**< No Averaging */ -#define XADCPS_CFR0_AVG16_MASK 0x1000 /**< Average 16 samples */ -#define XADCPS_CFR0_AVG64_MASK 0x2000 /**< Average 64 samples */ -#define XADCPS_CFR0_AVG256_MASK 0x3000 /**< Average 256 samples */ -#define XADCPS_CFR0_AVG_SHIFT 12 /**< Averaging bits shift */ -#define XADCPS_CFR0_MUX_MASK 0x0800 /**< External Mask Enable */ -#define XADCPS_CFR0_DU_MASK 0x0400 /**< Bipolar/Unipolar mode */ -#define XADCPS_CFR0_EC_MASK 0x0200 /**< Event driven/ - * Continuous mode selection - */ -#define XADCPS_CFR0_ACQ_MASK 0x0100 /**< Add acquisition by 6 ADCCLK */ -#define XADCPS_CFR0_CHANNEL_MASK 0x001F /**< Channel number bit Mask */ - -/*@}*/ - -/** - * @name Configuration Register 1 (CFR1) mask(s) - * @{ - */ -#define XADCPS_CFR1_SEQ_VALID_MASK 0xF000 /**< Sequence bit Mask */ -#define XADCPS_CFR1_SEQ_SAFEMODE_MASK 0x0000 /**< Default Safe Mode */ -#define XADCPS_CFR1_SEQ_ONEPASS_MASK 0x1000 /**< Onepass through Seq */ -#define XADCPS_CFR1_SEQ_CONTINPASS_MASK 0x2000 /**< Continuous Cycling Seq */ -#define XADCPS_CFR1_SEQ_SINGCHAN_MASK 0x3000 /**< Single channel - No Seq */ -#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x4000 /**< Simulataneous Sampling Mask */ -#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK 0x8000 /**< Independent Mode */ -#define XADCPS_CFR1_SEQ_SHIFT 12 /**< Sequence bit shift */ -#define XADCPS_CFR1_ALM_VCCPDRO_MASK 0x0800 /**< Alm 6 - VCCPDRO, Zynq */ -#define XADCPS_CFR1_ALM_VCCPAUX_MASK 0x0400 /**< Alm 5 - VCCPAUX, Zynq */ -#define XADCPS_CFR1_ALM_VCCPINT_MASK 0x0200 /**< Alm 4 - VCCPINT, Zynq */ -#define XADCPS_CFR1_ALM_VBRAM_MASK 0x0100 /**< Alm 3 - VBRAM, 7 series */ -#define XADCPS_CFR1_CAL_VALID_MASK 0x00F0 /**< Valid Calibration Mask */ -#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x0080 /**< Calibration 3 -Power - Supply Gain/Offset - Enable */ -#define XADCPS_CFR1_CAL_PS_OFFSET_MASK 0x0040 /**< Calibration 2 -Power - Supply Offset Enable */ -#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x0020 /**< Calibration 1 -ADC Gain - Offset Enable */ -#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK 0x0010 /**< Calibration 0 -ADC Offset - Enable */ -#define XADCPS_CFR1_CAL_DISABLE_MASK 0x0000 /**< No Calibration */ -#define XADCPS_CFR1_ALM_ALL_MASK 0x0F0F /**< Mask for all alarms */ -#define XADCPS_CFR1_ALM_VCCAUX_MASK 0x0008 /**< Alarm 2 - VCCAUX Enable */ -#define XADCPS_CFR1_ALM_VCCINT_MASK 0x0004 /**< Alarm 1 - VCCINT Enable */ -#define XADCPS_CFR1_ALM_TEMP_MASK 0x0002 /**< Alarm 0 - Temperature */ -#define XADCPS_CFR1_OT_MASK 0x0001 /**< Over Temperature Enable */ - -/*@}*/ - -/** - * @name Configuration Register 2 (CFR2) mask(s) - * @{ - */ -#define XADCPS_CFR2_CD_VALID_MASK 0xFF00 /**<Clock Divisor bit Mask */ -#define XADCPS_CFR2_CD_SHIFT 8 /**<Num of shift on division */ -#define XADCPS_CFR2_CD_MIN 8 /**<Minimum value of divisor */ -#define XADCPS_CFR2_CD_MAX 255 /**<Maximum value of divisor */ - -#define XADCPS_CFR2_CD_MIN 8 /**<Minimum value of divisor */ -#define XADCPS_CFR2_PD_MASK 0x0030 /**<Power Down Mask */ -#define XADCPS_CFR2_PD_XADC_MASK 0x0030 /**<Power Down XADC Mask */ -#define XADCPS_CFR2_PD_ADC1_MASK 0x0020 /**<Power Down ADC1 Mask */ -#define XADCPS_CFR2_PD_SHIFT 4 /**<Power Down Shift */ -/*@}*/ - -/** - * @name Sequence Register (SEQ) Bit Definitions - * @{ - */ -#define XADCPS_SEQ_CH_CALIB 0x00000001 /**< ADC Calibration Channel */ -#define XADCPS_SEQ_CH_VCCPINT 0x00000020 /**< VCCPINT, Zynq Only */ -#define XADCPS_SEQ_CH_VCCPAUX 0x00000040 /**< VCCPAUX, Zynq Only */ -#define XADCPS_SEQ_CH_VCCPDRO 0x00000080 /**< VCCPDRO, Zynq Only */ -#define XADCPS_SEQ_CH_TEMP 0x00000100 /**< On Chip Temperature Channel */ -#define XADCPS_SEQ_CH_VCCINT 0x00000200 /**< VCCINT Channel */ -#define XADCPS_SEQ_CH_VCCAUX 0x00000400 /**< VCCAUX Channel */ -#define XADCPS_SEQ_CH_VPVN 0x00000800 /**< VP/VN analog inputs Channel */ -#define XADCPS_SEQ_CH_VREFP 0x00001000 /**< VREFP Channel */ -#define XADCPS_SEQ_CH_VREFN 0x00002000 /**< VREFN Channel */ -#define XADCPS_SEQ_CH_VBRAM 0x00004000 /**< VBRAM Channel, 7 series */ -#define XADCPS_SEQ_CH_AUX00 0x00010000 /**< 1st Aux Channel */ -#define XADCPS_SEQ_CH_AUX01 0x00020000 /**< 2nd Aux Channel */ -#define XADCPS_SEQ_CH_AUX02 0x00040000 /**< 3rd Aux Channel */ -#define XADCPS_SEQ_CH_AUX03 0x00080000 /**< 4th Aux Channel */ -#define XADCPS_SEQ_CH_AUX04 0x00100000 /**< 5th Aux Channel */ -#define XADCPS_SEQ_CH_AUX05 0x00200000 /**< 6th Aux Channel */ -#define XADCPS_SEQ_CH_AUX06 0x00400000 /**< 7th Aux Channel */ -#define XADCPS_SEQ_CH_AUX07 0x00800000 /**< 8th Aux Channel */ -#define XADCPS_SEQ_CH_AUX08 0x01000000 /**< 9th Aux Channel */ -#define XADCPS_SEQ_CH_AUX09 0x02000000 /**< 10th Aux Channel */ -#define XADCPS_SEQ_CH_AUX10 0x04000000 /**< 11th Aux Channel */ -#define XADCPS_SEQ_CH_AUX11 0x08000000 /**< 12th Aux Channel */ -#define XADCPS_SEQ_CH_AUX12 0x10000000 /**< 13th Aux Channel */ -#define XADCPS_SEQ_CH_AUX13 0x20000000 /**< 14th Aux Channel */ -#define XADCPS_SEQ_CH_AUX14 0x40000000 /**< 15th Aux Channel */ -#define XADCPS_SEQ_CH_AUX15 0x80000000 /**< 16th Aux Channel */ - -#define XADCPS_SEQ00_CH_VALID_MASK 0x7FE1 /**< Mask for the valid channels */ -#define XADCPS_SEQ01_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */ - -#define XADCPS_SEQ02_CH_VALID_MASK 0x7FE0 /**< Mask for the valid channels */ -#define XADCPS_SEQ03_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */ - -#define XADCPS_SEQ04_CH_VALID_MASK 0x0800 /**< Mask for the valid channels */ -#define XADCPS_SEQ05_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */ - -#define XADCPS_SEQ06_CH_VALID_MASK 0x0800 /**< Mask for the valid channels */ -#define XADCPS_SEQ07_CH_VALID_MASK 0xFFFF /**< Mask for the valid channels */ - - -#define XADCPS_SEQ_CH_AUX_SHIFT 16 /**< Shift for the Aux Channel */ - -/*@}*/ - -/** - * @name OT Upper Alarm Threshold Register Bit Definitions - * @{ - */ - -#define XADCPS_ATR_OT_UPPER_ENB_MASK 0x000F /**< Mask for OT enable */ -#define XADCPS_ATR_OT_UPPER_VAL_MASK 0xFFF0 /**< Mask for OT value */ -#define XADCPS_ATR_OT_UPPER_VAL_SHIFT 4 /**< Shift for OT value */ -#define XADCPS_ATR_OT_UPPER_ENB_VAL 0x0003 /**< Value for OT enable */ -#define XADCPS_ATR_OT_UPPER_VAL_MAX 0x0FFF /**< Max OT value */ - -/*@}*/ - - -/** - * @name JTAG DRP Bit Definitions - * @{ - */ -#define XADCPS_JTAG_DATA_MASK 0x0000FFFF /**< Mask for the Data */ -#define XADCPS_JTAG_ADDR_MASK 0x03FF0000 /**< Mask for the Addr */ -#define XADCPS_JTAG_ADDR_SHIFT 16 /**< Shift for the Addr */ -#define XADCPS_JTAG_CMD_MASK 0x3C000000 /**< Mask for the Cmd */ -#define XADCPS_JTAG_CMD_WRITE_MASK 0x08000000 /**< Mask for CMD Write */ -#define XADCPS_JTAG_CMD_READ_MASK 0x04000000 /**< Mask for CMD Read */ -#define XADCPS_JTAG_CMD_SHIFT 26 /**< Shift for the Cmd */ - -/*@}*/ - -/** @name Unlock Register Definitions - * @{ - */ - #define XADCPS_UNLK_OFFSET 0x034 /**< Unlock Register */ - #define XADCPS_UNLK_VALUE 0x757BDF0D /**< Unlock Value */ - - /* @} */ - - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/*****************************************************************************/ -/** -* -* Read a register of the XADC device. This macro provides register -* access to all registers using the register offsets defined above. -* -* @param BaseAddress contains the base address of the device. -* @param RegOffset is the offset of the register to read. -* -* @return The contents of the register. -* -* @note C-style Signature: -* u32 XAdcPs_ReadReg(u32 BaseAddress, u32 RegOffset); -* -******************************************************************************/ -#define XAdcPs_ReadReg(BaseAddress, RegOffset) \ - (Xil_In32((BaseAddress) + (RegOffset))) - -/*****************************************************************************/ -/** -* -* Write a register of the XADC device. This macro provides -* register access to all registers using the register offsets defined above. -* -* @param BaseAddress contains the base address of the device. -* @param RegOffset is the offset of the register to write. -* @param Data is the value to write to the register. -* -* @return None. -* -* @note C-style Signature: -* void XAdcPs_WriteReg(u32 BaseAddress, -* u32 RegOffset,u32 Data) -* -******************************************************************************/ -#define XAdcPs_WriteReg(BaseAddress, RegOffset, Data) \ - (Xil_Out32((BaseAddress) + (RegOffset), (Data))) - -/************************** Function Prototypes ******************************/ - - -/*****************************************************************************/ -/** -* -* Formats the data to be written to the the XADC registers. -* -* @param RegOffset is the offset of the Register -* @param Data is the data to be written to the Register if it is -* a write. -* @param ReadWrite specifies whether it is a Read or a Write. -* Use 0 for Read, 1 for Write. -* -* @return None. -* -* @note C-style Signature: -* void XAdcPs_FormatWriteData(u32 RegOffset, -* u16 Data, int ReadWrite) -* -******************************************************************************/ -#define XAdcPs_FormatWriteData(RegOffset, Data, ReadWrite) \ - ((ReadWrite ? XADCPS_JTAG_CMD_WRITE_MASK : XADCPS_JTAG_CMD_READ_MASK ) | \ - ((RegOffset << XADCPS_JTAG_ADDR_SHIFT) & XADCPS_JTAG_ADDR_MASK) | \ - (Data & XADCPS_JTAG_DATA_MASK)) - - - -#ifdef __cplusplus -} -#endif - -#endif /* End of protection macro. */ diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v1_02_a/src/xadcps_intr.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v1_02_a/src/xadcps_intr.c deleted file mode 100644 index c66c584544011e00649d903173c2313b317ac467..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v1_02_a/src/xadcps_intr.c +++ /dev/null @@ -1,256 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xadcps_intr.c -* -* This file contains interrupt handling API functions of the XADC -* device. -* -* The device must be configured at hardware build time to support interrupt -* for all the functions in this file to work. -* -* Refer to xadcps.h header file and device specification for more information. -* -* @note -* -* Calling the interrupt functions without including the interrupt component will -* result in asserts if asserts are enabled, and will result in a unpredictable -* behavior if the asserts are not enabled. -* -* <pre> -* -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ----- -------- ----------------------------------------------------- -* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver -* -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xadcps.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/************************** Variable Definitions *****************************/ - - -/****************************************************************************/ -/** -* -* This function enables the specified interrupts in the device. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* @param Mask is the bit-mask of the interrupts to be enabled. -* Bit positions of 1 will be enabled. Bit positions of 0 will -* keep the previous setting. This mask is formed by OR'ing -* XADCPS_INTX_* bits defined in xadcps_hw.h. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask) -{ - u32 RegValue; - - /* - * Assert the arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Disable the specified interrupts in the IPIER. - */ - RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress, - XADCPS_INT_MASK_OFFSET); - RegValue &= ~(Mask & XADCPS_INTX_ALL_MASK); - XAdcPs_WriteReg(InstancePtr->Config.BaseAddress, - XADCPS_INT_MASK_OFFSET, - RegValue); -} - - -/****************************************************************************/ -/** -* -* This function disables the specified interrupts in the device. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* @param Mask is the bit-mask of the interrupts to be disabled. -* Bit positions of 1 will be disabled. Bit positions of 0 will -* keep the previous setting. This mask is formed by OR'ing -* XADCPS_INTX_* bits defined in xadcps_hw.h. -* -* @return None. -* -* @note None -* -*****************************************************************************/ -void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask) -{ - u32 RegValue; - - /* - * Assert the arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Enable the specified interrupts in the IPIER. - */ - RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress, - XADCPS_INT_MASK_OFFSET); - RegValue |= (Mask & XADCPS_INTX_ALL_MASK); - XAdcPs_WriteReg(InstancePtr->Config.BaseAddress, - XADCPS_INT_MASK_OFFSET, - RegValue); -} -/****************************************************************************/ -/** -* -* This function returns the enabled interrupts read from the Interrupt Mask -* Register (IPIER). Use the XADCPS_IPIXR_* constants defined in xadcps_hw.h to -* interpret the returned value. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* -* @return A 32-bit value representing the contents of the I. -* -* @note None. -* -*****************************************************************************/ -u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr) -{ - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Return the value read from the Interrupt Enable Register. - */ - return (~ XAdcPs_ReadReg(InstancePtr->Config.BaseAddress, - XADCPS_INT_MASK_OFFSET) & XADCPS_INTX_ALL_MASK); -} - -/****************************************************************************/ -/** -* -* This function returns the interrupt status read from Interrupt Status -* Register(IPISR). Use the XADCPS_IPIXR_* constants defined in xadcps_hw.h -* to interpret the returned value. -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* -* @return A 32-bit value representing the contents of the IPISR. -* -* @note The device must be configured at hardware build time to include -* interrupt component for this function to work. -* -*****************************************************************************/ -u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr) -{ - /* - * Assert the arguments. - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Return the value read from the Interrupt Status register. - */ - return XAdcPs_ReadReg(InstancePtr->Config.BaseAddress, - XADCPS_INT_STS_OFFSET) & XADCPS_INTX_ALL_MASK; -} - -/****************************************************************************/ -/** -* -* This function clears the specified interrupts in the Interrupt Status -* Register (IPISR). -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* @param Mask is the bit-mask of the interrupts to be cleared. -* Bit positions of 1 will be cleared. Bit positions of 0 will not -* change the previous interrupt status. This mask is formed by -* OR'ing XADCPS_IPIXR_* bits which are defined in xadcps_hw.h. -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask) -{ - u32 RegValue; - - /* - * Assert the arguments. - */ - Xil_AssertVoid(InstancePtr != NULL); - Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - /* - * Clear the specified interrupts in the Interrupt Status register. - */ - RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress, - XADCPS_INT_STS_OFFSET); - RegValue &= (Mask & XADCPS_INTX_ALL_MASK); - XAdcPs_WriteReg(InstancePtr->Config.BaseAddress, XADCPS_INT_STS_OFFSET, - RegValue); - -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v1_02_a/src/xadcps_selftest.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v1_02_a/src/xadcps_selftest.c deleted file mode 100644 index 9a6d97e573ee5273327b702b5aacb7dff577fc93..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v1_02_a/src/xadcps_selftest.c +++ /dev/null @@ -1,147 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xadcps_selftest.c -* -* This file contains a diagnostic self test function for the XAdcPs driver. -* The self test function does a simple read/write test of the Alarm Threshold -* Register. -* -* See xadcps.h for more information. -* -* @note None. -* -* <pre> -* -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ----- -------- ----------------------------------------------------- -* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver -* -* </pre> -* -*****************************************************************************/ - -/***************************** Include Files ********************************/ - -#include "xadcps.h" - -/************************** Constant Definitions ****************************/ - -/* - * The following constant defines the test value to be written - * to the Alarm Threshold Register - */ -#define XADCPS_ATR_TEST_VALUE 0x55 - -/**************************** Type Definitions ******************************/ - -/***************** Macros (Inline Functions) Definitions ********************/ - -/************************** Variable Definitions ****************************/ - -/************************** Function Prototypes *****************************/ - -/*****************************************************************************/ -/** -* -* Run a self-test on the driver/device. The test -* - Resets the device, -* - Writes a value into the Alarm Threshold register and reads it back -* for comparison. -* - Resets the device again. -* -* -* @param InstancePtr is a pointer to the XAdcPs instance. -* -* @return -* - XST_SUCCESS if the value read from the Alarm Threshold -* register is the same as the value written. -* - XST_FAILURE Otherwise -* -* @note This is a destructive test in that resets of the device are -* performed. Refer to the device specification for the -* device status after the reset operation. -* -******************************************************************************/ -int XAdcPs_SelfTest(XAdcPs *InstancePtr) -{ - int Status; - u32 RegValue; - - /* - * Assert the argument - */ - Xil_AssertNonvoid(InstancePtr != NULL); - Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - - - /* - * Reset the device to get it back to its default state - */ - XAdcPs_Reset(InstancePtr); - - /* - * Write a value into the Alarm Threshold registers, read it back, and - * do the comparison - */ - XAdcPs_SetAlarmThreshold(InstancePtr, XADCPS_ATR_VCCINT_UPPER, - XADCPS_ATR_TEST_VALUE); - RegValue = XAdcPs_GetAlarmThreshold(InstancePtr, XADCPS_ATR_VCCINT_UPPER); - - if (RegValue == XADCPS_ATR_TEST_VALUE) { - Status = XST_SUCCESS; - } else { - Status = XST_FAILURE; - } - - /* - * Reset the device again to its default state. - */ - XAdcPs_Reset(InstancePtr); - /* - * Return the test result. - */ - return Status; -} diff --git a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v1_02_a/src/xadcps_sinit.c b/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v1_02_a/src/xadcps_sinit.c deleted file mode 100644 index 3ba9409a2c0b4b71a2fe7651027d10e74c15af76..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/ps7_cortexa9_0/libsrc/xadcps_v1_02_a/src/xadcps_sinit.c +++ /dev/null @@ -1,109 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved. -* -* This file contains confidential and proprietary information of Xilinx, Inc. -* and is protected under U.S. and international copyright and other -* intellectual property laws. -* -* DISCLAIMER -* This disclaimer is not a license and does not grant any rights to the -* materials distributed herewith. Except as otherwise provided in a valid -* license issued to you by Xilinx, and to the maximum extent permitted by -* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL -* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, -* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF -* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; -* and (2) Xilinx shall not be liable (whether in contract or tort, including -* negligence, or under any other theory of liability) for any loss or damage -* of any kind or nature related to, arising under or in connection with these -* materials, including for any direct, or any indirect, special, incidental, -* or consequential loss or damage (including loss of data, profits, goodwill, -* or any type of loss or damage suffered as a result of any action brought by -* a third party) even if such damage or loss was reasonably foreseeable or -* Xilinx had been advised of the possibility of the same. -* -* CRITICAL APPLICATIONS -* Xilinx products are not designed or intended to be fail-safe, or for use in -* any application requiring fail-safe performance, such as life-support or -* safety devices or systems, Class III medical devices, nuclear facilities, -* applications related to the deployment of airbags, or any other applications -* that could lead to death, personal injury, or severe property or -* environmental damage (individually and collectively, "Critical -* Applications"). Customer assumes the sole risk and liability of any use of -* Xilinx products in Critical Applications, subject only to applicable laws -* and regulations governing limitations on product liability. -* -* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE -* AT ALL TIMES. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xadcps_sinit.c -* -* This file contains the implementation of the XAdcPs driver's static -* initialization functionality. -* -* @note None. -* -* <pre> -* -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ----- -------- ----------------------------------------------------- -* 1.00a ssb 12/22/11 First release based on the XPS/AXI XADC driver -* -* </pre> -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xparameters.h" -#include "xadcps.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/************************** Variable Definitions *****************************/ -extern XAdcPs_Config XAdcPs_ConfigTable[]; - -/*****************************************************************************/ -/** -* -* This function looks up the device configuration based on the unique device ID. -* The table XAdcPs_ConfigTable contains the configuration info for each device -* in the system. -* -* @param DeviceId contains the ID of the device for which the -* device configuration pointer is to be returned. -* -* @return -* - A pointer to the configuration found. -* - NULL if the specified device ID was not found. -* -* @note None. -* -******************************************************************************/ -XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId) -{ - XAdcPs_Config *CfgPtr = NULL; - u32 Index; - - for (Index=0; Index < 1; Index++) { - if (XAdcPs_ConfigTable[Index].DeviceId == DeviceId) { - CfgPtr = &XAdcPs_ConfigTable[Index]; - break; - } - } - - return CfgPtr; -} diff --git a/quad/sw/system_bsp/system.mss b/quad/sw/system_bsp/system.mss deleted file mode 100644 index e39ad14f5e036ab424fb2b9345ec97f2169960de..0000000000000000000000000000000000000000 --- a/quad/sw/system_bsp/system.mss +++ /dev/null @@ -1,292 +0,0 @@ - - PARAMETER VERSION = 2.2.0 - - -BEGIN OS - PARAMETER OS_NAME = standalone - PARAMETER OS_VER = 3.11.a - PARAMETER PROC_INSTANCE = ps7_cortexa9_0 - PARAMETER STDIN = ps7_uart_1 - PARAMETER STDOUT = ps7_uart_1 -END - - -BEGIN PROCESSOR - PARAMETER DRIVER_NAME = cpu_cortexa9 - PARAMETER DRIVER_VER = 1.01.a - PARAMETER HW_INSTANCE = ps7_cortexa9_0 - PARAMETER EXTRA_COMPILER_FLAGS = -g -O0 -END - - -BEGIN DRIVER - PARAMETER DRIVER_NAME = gpio - PARAMETER DRIVER_VER = 3.01.a - PARAMETER HW_INSTANCE = btns_4bits_tri_io -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = ps7_afi_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = ps7_afi_1 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = ps7_afi_2 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = ps7_afi_3 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = ps7_coresight_comp_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = ps7_ddr_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = ps7_ddrc_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = devcfg - PARAMETER DRIVER_VER = 2.04.a - PARAMETER HW_INSTANCE = ps7_dev_cfg_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = dmaps - PARAMETER DRIVER_VER = 1.06.a - PARAMETER HW_INSTANCE = ps7_dma_ns -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = dmaps - PARAMETER DRIVER_VER = 1.06.a - PARAMETER HW_INSTANCE = ps7_dma_s -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = emacps - PARAMETER DRIVER_VER = 1.05.a - PARAMETER HW_INSTANCE = ps7_ethernet_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = ps7_globaltimer_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = gpiops - PARAMETER DRIVER_VER = 1.02.a - PARAMETER HW_INSTANCE = ps7_gpio_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = ps7_gpv_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = iicps - PARAMETER DRIVER_VER = 1.04.a - PARAMETER HW_INSTANCE = ps7_i2c_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = ps7_intc_dist_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = ps7_iop_bus_config_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = ps7_l2cachec_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = ps7_ocmc_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = qspips - PARAMETER DRIVER_VER = 2.03.a - PARAMETER HW_INSTANCE = ps7_qspi_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = ps7_qspi_linear_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = ps7_ram_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = ps7_ram_1 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = ps7_scuc_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = scugic - PARAMETER DRIVER_VER = 1.05.a - PARAMETER HW_INSTANCE = ps7_scugic_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = scutimer - PARAMETER DRIVER_VER = 1.02.a - PARAMETER HW_INSTANCE = ps7_scutimer_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = scuwdt - PARAMETER DRIVER_VER = 1.02.a - PARAMETER HW_INSTANCE = ps7_scuwdt_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = ps7_sd_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = ps7_slcr_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = uartps - PARAMETER DRIVER_VER = 1.05.a - PARAMETER HW_INSTANCE = ps7_uart_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = uartps - PARAMETER DRIVER_VER = 1.05.a - PARAMETER HW_INSTANCE = ps7_uart_1 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = usbps - PARAMETER DRIVER_VER = 1.05.a - PARAMETER HW_INSTANCE = ps7_usb_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = xadcps - PARAMETER DRIVER_VER = 1.02.a - PARAMETER HW_INSTANCE = ps7_xadc_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = pwm_recorder_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = pwm_recorder_1 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = pwm_recorder_2 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = pwm_recorder_3 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = pwm_recorder_4 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = pwm_recorder_5 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = pwm_signal_out_wkillswitch_0 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = pwm_signal_out_wkillswitch_1 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = pwm_signal_out_wkillswitch_2 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 1.00.a - PARAMETER HW_INSTANCE = pwm_signal_out_wkillswitch_3 -END - -BEGIN DRIVER - PARAMETER DRIVER_NAME = tmrctr - PARAMETER DRIVER_VER = 2.05.a - PARAMETER HW_INSTANCE = axi_timer_0 -END - -